src/cpu/sparc/vm/sharedRuntime_sparc.cpp

Tue, 24 Jul 2012 10:51:00 -0700

author
twisti
date
Tue, 24 Jul 2012 10:51:00 -0700
changeset 3969
1d7922586cf6
parent 3627
8a48c2906f91
child 4037
da91efe96a93
permissions
-rw-r--r--

7023639: JSR 292 method handle invocation needs a fast path for compiled code
6984705: JSR 292 method handle creation should not go through JNI
Summary: remove assembly code for JDK 7 chained method handles
Reviewed-by: jrose, twisti, kvn, mhaupt
Contributed-by: John Rose <john.r.rose@oracle.com>, Christian Thalinger <christian.thalinger@oracle.com>, Michael Haupt <michael.haupt@oracle.com>

duke@435 1 /*
never@3500 2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
duke@435 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
duke@435 4 *
duke@435 5 * This code is free software; you can redistribute it and/or modify it
duke@435 6 * under the terms of the GNU General Public License version 2 only, as
duke@435 7 * published by the Free Software Foundation.
duke@435 8 *
duke@435 9 * This code is distributed in the hope that it will be useful, but WITHOUT
duke@435 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
duke@435 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
duke@435 12 * version 2 for more details (a copy is included in the LICENSE file that
duke@435 13 * accompanied this code).
duke@435 14 *
duke@435 15 * You should have received a copy of the GNU General Public License version
duke@435 16 * 2 along with this work; if not, write to the Free Software Foundation,
duke@435 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
duke@435 18 *
trims@1907 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
trims@1907 20 * or visit www.oracle.com if you need additional information or have any
trims@1907 21 * questions.
duke@435 22 *
duke@435 23 */
duke@435 24
stefank@2314 25 #include "precompiled.hpp"
stefank@2314 26 #include "asm/assembler.hpp"
stefank@2314 27 #include "assembler_sparc.inline.hpp"
stefank@2314 28 #include "code/debugInfoRec.hpp"
stefank@2314 29 #include "code/icBuffer.hpp"
stefank@2314 30 #include "code/vtableStubs.hpp"
stefank@2314 31 #include "interpreter/interpreter.hpp"
stefank@2314 32 #include "oops/compiledICHolderOop.hpp"
stefank@2314 33 #include "prims/jvmtiRedefineClassesTrace.hpp"
stefank@2314 34 #include "runtime/sharedRuntime.hpp"
stefank@2314 35 #include "runtime/vframeArray.hpp"
stefank@2314 36 #include "vmreg_sparc.inline.hpp"
stefank@2314 37 #ifdef COMPILER1
stefank@2314 38 #include "c1/c1_Runtime1.hpp"
stefank@2314 39 #endif
stefank@2314 40 #ifdef COMPILER2
stefank@2314 41 #include "opto/runtime.hpp"
stefank@2314 42 #endif
stefank@2314 43 #ifdef SHARK
stefank@2314 44 #include "compiler/compileBroker.hpp"
stefank@2314 45 #include "shark/sharkCompiler.hpp"
stefank@2314 46 #endif
duke@435 47
duke@435 48 #define __ masm->
duke@435 49
duke@435 50
duke@435 51 class RegisterSaver {
duke@435 52
duke@435 53 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
duke@435 54 // The Oregs are problematic. In the 32bit build the compiler can
duke@435 55 // have O registers live with 64 bit quantities. A window save will
duke@435 56 // cut the heads off of the registers. We have to do a very extensive
duke@435 57 // stack dance to save and restore these properly.
duke@435 58
duke@435 59 // Note that the Oregs problem only exists if we block at either a polling
duke@435 60 // page exception a compiled code safepoint that was not originally a call
duke@435 61 // or deoptimize following one of these kinds of safepoints.
duke@435 62
duke@435 63 // Lots of registers to save. For all builds, a window save will preserve
duke@435 64 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
duke@435 65 // builds a window-save will preserve the %o registers. In the LION build
duke@435 66 // we need to save the 64-bit %o registers which requires we save them
duke@435 67 // before the window-save (as then they become %i registers and get their
duke@435 68 // heads chopped off on interrupt). We have to save some %g registers here
duke@435 69 // as well.
duke@435 70 enum {
duke@435 71 // This frame's save area. Includes extra space for the native call:
duke@435 72 // vararg's layout space and the like. Briefly holds the caller's
duke@435 73 // register save area.
duke@435 74 call_args_area = frame::register_save_words_sp_offset +
duke@435 75 frame::memory_parameter_word_sp_offset*wordSize,
duke@435 76 // Make sure save locations are always 8 byte aligned.
duke@435 77 // can't use round_to because it doesn't produce compile time constant
duke@435 78 start_of_extra_save_area = ((call_args_area + 7) & ~7),
duke@435 79 g1_offset = start_of_extra_save_area, // g-regs needing saving
duke@435 80 g3_offset = g1_offset+8,
duke@435 81 g4_offset = g3_offset+8,
duke@435 82 g5_offset = g4_offset+8,
duke@435 83 o0_offset = g5_offset+8,
duke@435 84 o1_offset = o0_offset+8,
duke@435 85 o2_offset = o1_offset+8,
duke@435 86 o3_offset = o2_offset+8,
duke@435 87 o4_offset = o3_offset+8,
duke@435 88 o5_offset = o4_offset+8,
duke@435 89 start_of_flags_save_area = o5_offset+8,
duke@435 90 ccr_offset = start_of_flags_save_area,
duke@435 91 fsr_offset = ccr_offset + 8,
duke@435 92 d00_offset = fsr_offset+8, // Start of float save area
duke@435 93 register_save_size = d00_offset+8*32
duke@435 94 };
duke@435 95
duke@435 96
duke@435 97 public:
duke@435 98
duke@435 99 static int Oexception_offset() { return o0_offset; };
duke@435 100 static int G3_offset() { return g3_offset; };
duke@435 101 static int G5_offset() { return g5_offset; };
duke@435 102 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
duke@435 103 static void restore_live_registers(MacroAssembler* masm);
duke@435 104
duke@435 105 // During deoptimization only the result register need to be restored
duke@435 106 // all the other values have already been extracted.
duke@435 107
duke@435 108 static void restore_result_registers(MacroAssembler* masm);
duke@435 109 };
duke@435 110
duke@435 111 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
duke@435 112 // Record volatile registers as callee-save values in an OopMap so their save locations will be
duke@435 113 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
duke@435 114 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
duke@435 115 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
duke@435 116 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
duke@435 117 int i;
kvn@1442 118 // Always make the frame size 16 byte aligned.
duke@435 119 int frame_size = round_to(additional_frame_words + register_save_size, 16);
duke@435 120 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
duke@435 121 int frame_size_in_slots = frame_size / sizeof(jint);
duke@435 122 // CodeBlob frame size is in words.
duke@435 123 *total_frame_words = frame_size / wordSize;
duke@435 124 // OopMap* map = new OopMap(*total_frame_words, 0);
duke@435 125 OopMap* map = new OopMap(frame_size_in_slots, 0);
duke@435 126
duke@435 127 #if !defined(_LP64)
duke@435 128
duke@435 129 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
duke@435 130 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@435 131 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@435 132 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@435 133 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@435 134 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@435 135 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@435 136 #endif /* _LP64 */
duke@435 137
duke@435 138 __ save(SP, -frame_size, SP);
duke@435 139
duke@435 140 #ifndef _LP64
duke@435 141 // Reload the 64 bit Oregs. Although they are now Iregs we load them
duke@435 142 // to Oregs here to avoid interrupts cutting off their heads
duke@435 143
duke@435 144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@435 145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@435 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@435 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@435 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@435 149 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@435 150
duke@435 151 __ stx(O0, SP, o0_offset+STACK_BIAS);
duke@435 152 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
duke@435 153
duke@435 154 __ stx(O1, SP, o1_offset+STACK_BIAS);
duke@435 155
duke@435 156 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
duke@435 157
duke@435 158 __ stx(O2, SP, o2_offset+STACK_BIAS);
duke@435 159 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
duke@435 160
duke@435 161 __ stx(O3, SP, o3_offset+STACK_BIAS);
duke@435 162 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
duke@435 163
duke@435 164 __ stx(O4, SP, o4_offset+STACK_BIAS);
duke@435 165 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
duke@435 166
duke@435 167 __ stx(O5, SP, o5_offset+STACK_BIAS);
duke@435 168 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
duke@435 169 #endif /* _LP64 */
duke@435 170
coleenp@548 171
coleenp@548 172 #ifdef _LP64
coleenp@548 173 int debug_offset = 0;
coleenp@548 174 #else
coleenp@548 175 int debug_offset = 4;
coleenp@548 176 #endif
duke@435 177 // Save the G's
duke@435 178 __ stx(G1, SP, g1_offset+STACK_BIAS);
coleenp@548 179 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
duke@435 180
duke@435 181 __ stx(G3, SP, g3_offset+STACK_BIAS);
coleenp@548 182 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
duke@435 183
duke@435 184 __ stx(G4, SP, g4_offset+STACK_BIAS);
coleenp@548 185 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
duke@435 186
duke@435 187 __ stx(G5, SP, g5_offset+STACK_BIAS);
coleenp@548 188 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
duke@435 189
duke@435 190 // This is really a waste but we'll keep things as they were for now
duke@435 191 if (true) {
duke@435 192 #ifndef _LP64
duke@435 193 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
duke@435 194 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
duke@435 195 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
duke@435 196 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
duke@435 197 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
duke@435 198 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
duke@435 199 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
duke@435 200 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
duke@435 201 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
duke@435 202 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
coleenp@548 203 #endif /* _LP64 */
duke@435 204 }
duke@435 205
duke@435 206
duke@435 207 // Save the flags
duke@435 208 __ rdccr( G5 );
duke@435 209 __ stx(G5, SP, ccr_offset+STACK_BIAS);
duke@435 210 __ stxfsr(SP, fsr_offset+STACK_BIAS);
duke@435 211
kvn@1442 212 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
duke@435 213 int offset = d00_offset;
kvn@1442 214 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@435 215 FloatRegister f = as_FloatRegister(i);
duke@435 216 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
kvn@1442 217 // Record as callee saved both halves of double registers (2 float registers).
duke@435 218 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
kvn@1442 219 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
duke@435 220 offset += sizeof(double);
duke@435 221 }
duke@435 222
duke@435 223 // And we're done.
duke@435 224
duke@435 225 return map;
duke@435 226 }
duke@435 227
duke@435 228
duke@435 229 // Pop the current frame and restore all the registers that we
duke@435 230 // saved.
duke@435 231 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
duke@435 232
duke@435 233 // Restore all the FP registers
kvn@1442 234 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
duke@435 235 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
duke@435 236 }
duke@435 237
duke@435 238 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
duke@435 239 __ wrccr (G1) ;
duke@435 240
duke@435 241 // Restore the G's
duke@435 242 // Note that G2 (AKA GThread) must be saved and restored separately.
duke@435 243 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
duke@435 244
duke@435 245 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@435 246 __ ldx(SP, g3_offset+STACK_BIAS, G3);
duke@435 247 __ ldx(SP, g4_offset+STACK_BIAS, G4);
duke@435 248 __ ldx(SP, g5_offset+STACK_BIAS, G5);
duke@435 249
duke@435 250
duke@435 251 #if !defined(_LP64)
duke@435 252 // Restore the 64-bit O's.
duke@435 253 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@435 254 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@435 255 __ ldx(SP, o2_offset+STACK_BIAS, O2);
duke@435 256 __ ldx(SP, o3_offset+STACK_BIAS, O3);
duke@435 257 __ ldx(SP, o4_offset+STACK_BIAS, O4);
duke@435 258 __ ldx(SP, o5_offset+STACK_BIAS, O5);
duke@435 259
duke@435 260 // And temporarily place them in TLS
duke@435 261
duke@435 262 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@435 263 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@435 264 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
duke@435 265 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
duke@435 266 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
duke@435 267 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
duke@435 268 #endif /* _LP64 */
duke@435 269
duke@435 270 // Restore flags
duke@435 271
duke@435 272 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
duke@435 273
duke@435 274 __ restore();
duke@435 275
duke@435 276 #if !defined(_LP64)
duke@435 277 // Now reload the 64bit Oregs after we've restore the window.
duke@435 278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@435 279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@435 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
duke@435 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
duke@435 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
duke@435 283 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
duke@435 284 #endif /* _LP64 */
duke@435 285
duke@435 286 }
duke@435 287
duke@435 288 // Pop the current frame and restore the registers that might be holding
duke@435 289 // a result.
duke@435 290 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
duke@435 291
duke@435 292 #if !defined(_LP64)
duke@435 293 // 32bit build returns longs in G1
duke@435 294 __ ldx(SP, g1_offset+STACK_BIAS, G1);
duke@435 295
duke@435 296 // Retrieve the 64-bit O's.
duke@435 297 __ ldx(SP, o0_offset+STACK_BIAS, O0);
duke@435 298 __ ldx(SP, o1_offset+STACK_BIAS, O1);
duke@435 299 // and save to TLS
duke@435 300 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
duke@435 301 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
duke@435 302 #endif /* _LP64 */
duke@435 303
duke@435 304 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
duke@435 305
duke@435 306 __ restore();
duke@435 307
duke@435 308 #if !defined(_LP64)
duke@435 309 // Now reload the 64bit Oregs after we've restore the window.
duke@435 310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
duke@435 311 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
duke@435 312 #endif /* _LP64 */
duke@435 313
duke@435 314 }
duke@435 315
duke@435 316 // The java_calling_convention describes stack locations as ideal slots on
duke@435 317 // a frame with no abi restrictions. Since we must observe abi restrictions
duke@435 318 // (like the placement of the register window) the slots must be biased by
duke@435 319 // the following value.
duke@435 320 static int reg2offset(VMReg r) {
duke@435 321 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
duke@435 322 }
duke@435 323
never@3500 324 static VMRegPair reg64_to_VMRegPair(Register r) {
never@3500 325 VMRegPair ret;
never@3500 326 if (wordSize == 8) {
never@3500 327 ret.set2(r->as_VMReg());
never@3500 328 } else {
never@3500 329 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
never@3500 330 }
never@3500 331 return ret;
never@3500 332 }
never@3500 333
duke@435 334 // ---------------------------------------------------------------------------
duke@435 335 // Read the array of BasicTypes from a signature, and compute where the
duke@435 336 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
duke@435 337 // quantities. Values less than VMRegImpl::stack0 are registers, those above
duke@435 338 // refer to 4-byte stack slots. All stack slots are based off of the window
duke@435 339 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
duke@435 340 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
duke@435 341 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
duke@435 342 // integer registers. Values 64-95 are the (32-bit only) float registers.
duke@435 343 // Each 32-bit quantity is given its own number, so the integer registers
duke@435 344 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
duke@435 345 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
duke@435 346
duke@435 347 // Register results are passed in O0-O5, for outgoing call arguments. To
duke@435 348 // convert to incoming arguments, convert all O's to I's. The regs array
duke@435 349 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
duke@435 350 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
duke@435 351 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
duke@435 352 // passed (used as a placeholder for the other half of longs and doubles in
duke@435 353 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
duke@435 354 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
duke@435 355 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
duke@435 356 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
duke@435 357 // same VMRegPair.
duke@435 358
duke@435 359 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
duke@435 360 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
duke@435 361 // units regardless of build.
duke@435 362
duke@435 363
duke@435 364 // ---------------------------------------------------------------------------
duke@435 365 // The compiled Java calling convention. The Java convention always passes
duke@435 366 // 64-bit values in adjacent aligned locations (either registers or stack),
duke@435 367 // floats in float registers and doubles in aligned float pairs. Values are
duke@435 368 // packed in the registers. There is no backing varargs store for values in
duke@435 369 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
duke@435 370 // passed in I's, because longs in I's get their heads chopped off at
duke@435 371 // interrupt).
duke@435 372 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
duke@435 373 VMRegPair *regs,
duke@435 374 int total_args_passed,
duke@435 375 int is_outgoing) {
duke@435 376 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
duke@435 377
duke@435 378 // Convention is to pack the first 6 int/oop args into the first 6 registers
duke@435 379 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
duke@435 380 // into F0-F7, extras spill to the stack. Then pad all register sets to
duke@435 381 // align. Then put longs and doubles into the same registers as they fit,
duke@435 382 // else spill to the stack.
duke@435 383 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
duke@435 384 const int flt_reg_max = 8;
duke@435 385 //
duke@435 386 // Where 32-bit 1-reg longs start being passed
duke@435 387 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
duke@435 388 // So make it look like we've filled all the G regs that c2 wants to use.
duke@435 389 Register g_reg = TieredCompilation ? noreg : G1;
duke@435 390
duke@435 391 // Count int/oop and float args. See how many stack slots we'll need and
duke@435 392 // where the longs & doubles will go.
duke@435 393 int int_reg_cnt = 0;
duke@435 394 int flt_reg_cnt = 0;
duke@435 395 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
duke@435 396 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
duke@435 397 int stk_reg_pairs = 0;
duke@435 398 for (int i = 0; i < total_args_passed; i++) {
duke@435 399 switch (sig_bt[i]) {
duke@435 400 case T_LONG: // LP64, longs compete with int args
duke@435 401 assert(sig_bt[i+1] == T_VOID, "");
duke@435 402 #ifdef _LP64
twisti@3969 403 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@435 404 #endif
duke@435 405 break;
duke@435 406 case T_OBJECT:
duke@435 407 case T_ARRAY:
duke@435 408 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
twisti@3969 409 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@435 410 #ifndef _LP64
duke@435 411 else stk_reg_pairs++;
duke@435 412 #endif
duke@435 413 break;
duke@435 414 case T_INT:
duke@435 415 case T_SHORT:
duke@435 416 case T_CHAR:
duke@435 417 case T_BYTE:
duke@435 418 case T_BOOLEAN:
twisti@3969 419 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
duke@435 420 else stk_reg_pairs++;
duke@435 421 break;
duke@435 422 case T_FLOAT:
twisti@3969 423 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
duke@435 424 else stk_reg_pairs++;
duke@435 425 break;
duke@435 426 case T_DOUBLE:
duke@435 427 assert(sig_bt[i+1] == T_VOID, "");
duke@435 428 break;
duke@435 429 case T_VOID:
duke@435 430 break;
duke@435 431 default:
duke@435 432 ShouldNotReachHere();
duke@435 433 }
duke@435 434 }
duke@435 435
duke@435 436 // This is where the longs/doubles start on the stack.
duke@435 437 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
duke@435 438
duke@435 439 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
duke@435 440
duke@435 441 // int stk_reg = frame::register_save_words*(wordSize>>2);
duke@435 442 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
duke@435 443 int stk_reg = 0;
duke@435 444 int int_reg = 0;
duke@435 445 int flt_reg = 0;
duke@435 446
duke@435 447 // Now do the signature layout
duke@435 448 for (int i = 0; i < total_args_passed; i++) {
duke@435 449 switch (sig_bt[i]) {
duke@435 450 case T_INT:
duke@435 451 case T_SHORT:
duke@435 452 case T_CHAR:
duke@435 453 case T_BYTE:
duke@435 454 case T_BOOLEAN:
duke@435 455 #ifndef _LP64
duke@435 456 case T_OBJECT:
duke@435 457 case T_ARRAY:
duke@435 458 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@435 459 #endif // _LP64
duke@435 460 if (int_reg < int_reg_max) {
duke@435 461 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@435 462 regs[i].set1(r->as_VMReg());
duke@435 463 } else {
duke@435 464 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@435 465 }
duke@435 466 break;
duke@435 467
duke@435 468 #ifdef _LP64
duke@435 469 case T_OBJECT:
duke@435 470 case T_ARRAY:
duke@435 471 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
duke@435 472 if (int_reg < int_reg_max) {
duke@435 473 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@435 474 regs[i].set2(r->as_VMReg());
duke@435 475 } else {
duke@435 476 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@435 477 stk_reg_pairs += 2;
duke@435 478 }
duke@435 479 break;
duke@435 480 #endif // _LP64
duke@435 481
duke@435 482 case T_LONG:
duke@435 483 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
duke@435 484 #ifdef _LP64
duke@435 485 if (int_reg < int_reg_max) {
duke@435 486 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
duke@435 487 regs[i].set2(r->as_VMReg());
duke@435 488 } else {
duke@435 489 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@435 490 stk_reg_pairs += 2;
duke@435 491 }
duke@435 492 #else
never@739 493 #ifdef COMPILER2
duke@435 494 // For 32-bit build, can't pass longs in O-regs because they become
duke@435 495 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
duke@435 496 // spare and available. This convention isn't used by the Sparc ABI or
duke@435 497 // anywhere else. If we're tiered then we don't use G-regs because c1
never@739 498 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
duke@435 499 // G0: zero
duke@435 500 // G1: 1st Long arg
duke@435 501 // G2: global allocated to TLS
duke@435 502 // G3: used in inline cache check
duke@435 503 // G4: 2nd Long arg
duke@435 504 // G5: used in inline cache check
duke@435 505 // G6: used by OS
duke@435 506 // G7: used by OS
duke@435 507
duke@435 508 if (g_reg == G1) {
duke@435 509 regs[i].set2(G1->as_VMReg()); // This long arg in G1
duke@435 510 g_reg = G4; // Where the next arg goes
duke@435 511 } else if (g_reg == G4) {
duke@435 512 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
duke@435 513 g_reg = noreg; // No more longs in registers
duke@435 514 } else {
duke@435 515 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@435 516 stk_reg_pairs += 2;
duke@435 517 }
duke@435 518 #else // COMPILER2
duke@435 519 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@435 520 stk_reg_pairs += 2;
duke@435 521 #endif // COMPILER2
never@739 522 #endif // _LP64
duke@435 523 break;
duke@435 524
duke@435 525 case T_FLOAT:
duke@435 526 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
twisti@3969 527 else regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
duke@435 528 break;
duke@435 529 case T_DOUBLE:
duke@435 530 assert(sig_bt[i+1] == T_VOID, "expecting half");
duke@435 531 if (flt_reg_pairs + 1 < flt_reg_max) {
duke@435 532 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
duke@435 533 flt_reg_pairs += 2;
duke@435 534 } else {
duke@435 535 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
duke@435 536 stk_reg_pairs += 2;
duke@435 537 }
duke@435 538 break;
duke@435 539 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
duke@435 540 default:
duke@435 541 ShouldNotReachHere();
duke@435 542 }
duke@435 543 }
duke@435 544
duke@435 545 // retun the amount of stack space these arguments will need.
duke@435 546 return stk_reg_pairs;
duke@435 547
duke@435 548 }
duke@435 549
twisti@1441 550 // Helper class mostly to avoid passing masm everywhere, and handle
twisti@1441 551 // store displacement overflow logic.
duke@435 552 class AdapterGenerator {
duke@435 553 MacroAssembler *masm;
duke@435 554 Register Rdisp;
duke@435 555 void set_Rdisp(Register r) { Rdisp = r; }
duke@435 556
duke@435 557 void patch_callers_callsite();
duke@435 558
duke@435 559 // base+st_off points to top of argument
twisti@1861 560 int arg_offset(const int st_off) { return st_off; }
duke@435 561 int next_arg_offset(const int st_off) {
twisti@1861 562 return st_off - Interpreter::stackElementSize;
twisti@1441 563 }
twisti@1441 564
twisti@1441 565 // Argument slot values may be loaded first into a register because
twisti@1441 566 // they might not fit into displacement.
twisti@1441 567 RegisterOrConstant arg_slot(const int st_off);
twisti@1441 568 RegisterOrConstant next_arg_slot(const int st_off);
twisti@1441 569
duke@435 570 // Stores long into offset pointed to by base
duke@435 571 void store_c2i_long(Register r, Register base,
duke@435 572 const int st_off, bool is_stack);
duke@435 573 void store_c2i_object(Register r, Register base,
duke@435 574 const int st_off);
duke@435 575 void store_c2i_int(Register r, Register base,
duke@435 576 const int st_off);
duke@435 577 void store_c2i_double(VMReg r_2,
duke@435 578 VMReg r_1, Register base, const int st_off);
duke@435 579 void store_c2i_float(FloatRegister f, Register base,
duke@435 580 const int st_off);
duke@435 581
duke@435 582 public:
duke@435 583 void gen_c2i_adapter(int total_args_passed,
duke@435 584 // VMReg max_arg,
duke@435 585 int comp_args_on_stack, // VMRegStackSlots
duke@435 586 const BasicType *sig_bt,
duke@435 587 const VMRegPair *regs,
duke@435 588 Label& skip_fixup);
duke@435 589 void gen_i2c_adapter(int total_args_passed,
duke@435 590 // VMReg max_arg,
duke@435 591 int comp_args_on_stack, // VMRegStackSlots
duke@435 592 const BasicType *sig_bt,
duke@435 593 const VMRegPair *regs);
duke@435 594
duke@435 595 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
duke@435 596 };
duke@435 597
duke@435 598
duke@435 599 // Patch the callers callsite with entry to compiled code if it exists.
duke@435 600 void AdapterGenerator::patch_callers_callsite() {
duke@435 601 Label L;
duke@435 602 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
kvn@3037 603 __ br_null(G3_scratch, false, Assembler::pt, L);
duke@435 604 // Schedule the branch target address early.
duke@435 605 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@435 606 // Call into the VM to patch the caller, then jump to compiled callee
duke@435 607 __ save_frame(4); // Args in compiled layout; do not blow them
duke@435 608
duke@435 609 // Must save all the live Gregs the list is:
duke@435 610 // G1: 1st Long arg (32bit build)
duke@435 611 // G2: global allocated to TLS
duke@435 612 // G3: used in inline cache check (scratch)
duke@435 613 // G4: 2nd Long arg (32bit build);
duke@435 614 // G5: used in inline cache check (methodOop)
duke@435 615
duke@435 616 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
duke@435 617
duke@435 618 #ifdef _LP64
duke@435 619 // mov(s,d)
duke@435 620 __ mov(G1, L1);
duke@435 621 __ mov(G4, L4);
duke@435 622 __ mov(G5_method, L5);
duke@435 623 __ mov(G5_method, O0); // VM needs target method
duke@435 624 __ mov(I7, O1); // VM needs caller's callsite
duke@435 625 // Must be a leaf call...
duke@435 626 // can be very far once the blob has been relocated
twisti@1162 627 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
duke@435 628 __ relocate(relocInfo::runtime_call_type);
twisti@1162 629 __ jumpl_to(dest, O7, O7);
duke@435 630 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@435 631 __ mov(L7_thread_cache, G2_thread);
duke@435 632 __ mov(L1, G1);
duke@435 633 __ mov(L4, G4);
duke@435 634 __ mov(L5, G5_method);
duke@435 635 #else
duke@435 636 __ stx(G1, FP, -8 + STACK_BIAS);
duke@435 637 __ stx(G4, FP, -16 + STACK_BIAS);
duke@435 638 __ mov(G5_method, L5);
duke@435 639 __ mov(G5_method, O0); // VM needs target method
duke@435 640 __ mov(I7, O1); // VM needs caller's callsite
duke@435 641 // Must be a leaf call...
duke@435 642 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
duke@435 643 __ delayed()->mov(G2_thread, L7_thread_cache);
duke@435 644 __ mov(L7_thread_cache, G2_thread);
duke@435 645 __ ldx(FP, -8 + STACK_BIAS, G1);
duke@435 646 __ ldx(FP, -16 + STACK_BIAS, G4);
duke@435 647 __ mov(L5, G5_method);
duke@435 648 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@435 649 #endif /* _LP64 */
duke@435 650
duke@435 651 __ restore(); // Restore args
duke@435 652 __ bind(L);
duke@435 653 }
duke@435 654
twisti@1441 655
twisti@1441 656 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
twisti@1441 657 RegisterOrConstant roc(arg_offset(st_off));
twisti@1441 658 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@435 659 }
duke@435 660
twisti@1441 661 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
twisti@1441 662 RegisterOrConstant roc(next_arg_offset(st_off));
twisti@1441 663 return __ ensure_simm13_or_reg(roc, Rdisp);
duke@435 664 }
twisti@1441 665
twisti@1441 666
duke@435 667 // Stores long into offset pointed to by base
duke@435 668 void AdapterGenerator::store_c2i_long(Register r, Register base,
duke@435 669 const int st_off, bool is_stack) {
duke@435 670 #ifdef _LP64
duke@435 671 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@435 672 // data is passed in only 1 slot.
duke@435 673 __ stx(r, base, next_arg_slot(st_off));
duke@435 674 #else
ysr@777 675 #ifdef COMPILER2
duke@435 676 // Misaligned store of 64-bit data
duke@435 677 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@435 678 __ srlx(r, 32, r);
duke@435 679 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@435 680 #else
duke@435 681 if (is_stack) {
duke@435 682 // Misaligned store of 64-bit data
duke@435 683 __ stw(r, base, arg_slot(st_off)); // lo bits
duke@435 684 __ srlx(r, 32, r);
duke@435 685 __ stw(r, base, next_arg_slot(st_off)); // hi bits
duke@435 686 } else {
duke@435 687 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
duke@435 688 __ stw(r , base, next_arg_slot(st_off)); // hi bits
duke@435 689 }
duke@435 690 #endif // COMPILER2
ysr@777 691 #endif // _LP64
duke@435 692 }
duke@435 693
duke@435 694 void AdapterGenerator::store_c2i_object(Register r, Register base,
duke@435 695 const int st_off) {
duke@435 696 __ st_ptr (r, base, arg_slot(st_off));
duke@435 697 }
duke@435 698
duke@435 699 void AdapterGenerator::store_c2i_int(Register r, Register base,
duke@435 700 const int st_off) {
duke@435 701 __ st (r, base, arg_slot(st_off));
duke@435 702 }
duke@435 703
duke@435 704 // Stores into offset pointed to by base
duke@435 705 void AdapterGenerator::store_c2i_double(VMReg r_2,
duke@435 706 VMReg r_1, Register base, const int st_off) {
duke@435 707 #ifdef _LP64
duke@435 708 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@435 709 // data is passed in only 1 slot.
duke@435 710 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@435 711 #else
duke@435 712 // Need to marshal 64-bit value from misaligned Lesp loads
duke@435 713 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
duke@435 714 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
duke@435 715 #endif
duke@435 716 }
duke@435 717
duke@435 718 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
duke@435 719 const int st_off) {
duke@435 720 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
duke@435 721 }
duke@435 722
duke@435 723 void AdapterGenerator::gen_c2i_adapter(
duke@435 724 int total_args_passed,
duke@435 725 // VMReg max_arg,
duke@435 726 int comp_args_on_stack, // VMRegStackSlots
duke@435 727 const BasicType *sig_bt,
duke@435 728 const VMRegPair *regs,
duke@435 729 Label& skip_fixup) {
duke@435 730
duke@435 731 // Before we get into the guts of the C2I adapter, see if we should be here
duke@435 732 // at all. We've come from compiled code and are attempting to jump to the
duke@435 733 // interpreter, which means the caller made a static call to get here
duke@435 734 // (vcalls always get a compiled target if there is one). Check for a
duke@435 735 // compiled target. If there is one, we need to patch the caller's call.
duke@435 736 // However we will run interpreted if we come thru here. The next pass
duke@435 737 // thru the call site will run compiled. If we ran compiled here then
duke@435 738 // we can (theorectically) do endless i2c->c2i->i2c transitions during
duke@435 739 // deopt/uncommon trap cycles. If we always go interpreted here then
duke@435 740 // we can have at most one and don't need to play any tricks to keep
duke@435 741 // from endlessly growing the stack.
duke@435 742 //
duke@435 743 // Actually if we detected that we had an i2c->c2i transition here we
duke@435 744 // ought to be able to reset the world back to the state of the interpreted
duke@435 745 // call and not bother building another interpreter arg area. We don't
duke@435 746 // do that at this point.
duke@435 747
duke@435 748 patch_callers_callsite();
duke@435 749
duke@435 750 __ bind(skip_fixup);
duke@435 751
duke@435 752 // Since all args are passed on the stack, total_args_passed*wordSize is the
duke@435 753 // space we need. Add in varargs area needed by the interpreter. Round up
duke@435 754 // to stack alignment.
twisti@1861 755 const int arg_size = total_args_passed * Interpreter::stackElementSize;
duke@435 756 const int varargs_area =
duke@435 757 (frame::varargs_offset - frame::register_save_words)*wordSize;
duke@435 758 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
duke@435 759
duke@435 760 int bias = STACK_BIAS;
duke@435 761 const int interp_arg_offset = frame::varargs_offset*wordSize +
twisti@1861 762 (total_args_passed-1)*Interpreter::stackElementSize;
duke@435 763
duke@435 764 Register base = SP;
duke@435 765
duke@435 766 #ifdef _LP64
duke@435 767 // In the 64bit build because of wider slots and STACKBIAS we can run
duke@435 768 // out of bits in the displacement to do loads and stores. Use g3 as
duke@435 769 // temporary displacement.
twisti@3310 770 if (!Assembler::is_simm13(extraspace)) {
duke@435 771 __ set(extraspace, G3_scratch);
duke@435 772 __ sub(SP, G3_scratch, SP);
duke@435 773 } else {
duke@435 774 __ sub(SP, extraspace, SP);
duke@435 775 }
duke@435 776 set_Rdisp(G3_scratch);
duke@435 777 #else
duke@435 778 __ sub(SP, extraspace, SP);
duke@435 779 #endif // _LP64
duke@435 780
duke@435 781 // First write G1 (if used) to where ever it must go
duke@435 782 for (int i=0; i<total_args_passed; i++) {
twisti@1861 783 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@435 784 VMReg r_1 = regs[i].first();
duke@435 785 VMReg r_2 = regs[i].second();
duke@435 786 if (r_1 == G1_scratch->as_VMReg()) {
duke@435 787 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@435 788 store_c2i_object(G1_scratch, base, st_off);
duke@435 789 } else if (sig_bt[i] == T_LONG) {
duke@435 790 assert(!TieredCompilation, "should not use register args for longs");
duke@435 791 store_c2i_long(G1_scratch, base, st_off, false);
duke@435 792 } else {
duke@435 793 store_c2i_int(G1_scratch, base, st_off);
duke@435 794 }
duke@435 795 }
duke@435 796 }
duke@435 797
duke@435 798 // Now write the args into the outgoing interpreter space
duke@435 799 for (int i=0; i<total_args_passed; i++) {
twisti@1861 800 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
duke@435 801 VMReg r_1 = regs[i].first();
duke@435 802 VMReg r_2 = regs[i].second();
duke@435 803 if (!r_1->is_valid()) {
duke@435 804 assert(!r_2->is_valid(), "");
duke@435 805 continue;
duke@435 806 }
duke@435 807 // Skip G1 if found as we did it first in order to free it up
duke@435 808 if (r_1 == G1_scratch->as_VMReg()) {
duke@435 809 continue;
duke@435 810 }
duke@435 811 #ifdef ASSERT
duke@435 812 bool G1_forced = false;
duke@435 813 #endif // ASSERT
duke@435 814 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
duke@435 815 #ifdef _LP64
duke@435 816 Register ld_off = Rdisp;
duke@435 817 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
duke@435 818 #else
duke@435 819 int ld_off = reg2offset(r_1) + extraspace + bias;
kvn@1686 820 #endif // _LP64
duke@435 821 #ifdef ASSERT
duke@435 822 G1_forced = true;
duke@435 823 #endif // ASSERT
duke@435 824 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
duke@435 825 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
duke@435 826 else __ ldx(base, ld_off, G1_scratch);
duke@435 827 }
duke@435 828
duke@435 829 if (r_1->is_Register()) {
duke@435 830 Register r = r_1->as_Register()->after_restore();
duke@435 831 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
duke@435 832 store_c2i_object(r, base, st_off);
duke@435 833 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
kvn@1686 834 #ifndef _LP64
duke@435 835 if (TieredCompilation) {
duke@435 836 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
duke@435 837 }
kvn@1686 838 #endif // _LP64
duke@435 839 store_c2i_long(r, base, st_off, r_2->is_stack());
duke@435 840 } else {
duke@435 841 store_c2i_int(r, base, st_off);
duke@435 842 }
duke@435 843 } else {
duke@435 844 assert(r_1->is_FloatRegister(), "");
duke@435 845 if (sig_bt[i] == T_FLOAT) {
duke@435 846 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
duke@435 847 } else {
duke@435 848 assert(sig_bt[i] == T_DOUBLE, "wrong type");
duke@435 849 store_c2i_double(r_2, r_1, base, st_off);
duke@435 850 }
duke@435 851 }
duke@435 852 }
duke@435 853
duke@435 854 #ifdef _LP64
duke@435 855 // Need to reload G3_scratch, used for temporary displacements.
duke@435 856 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
duke@435 857
duke@435 858 // Pass O5_savedSP as an argument to the interpreter.
duke@435 859 // The interpreter will restore SP to this value before returning.
duke@435 860 __ set(extraspace, G1);
duke@435 861 __ add(SP, G1, O5_savedSP);
duke@435 862 #else
duke@435 863 // Pass O5_savedSP as an argument to the interpreter.
duke@435 864 // The interpreter will restore SP to this value before returning.
duke@435 865 __ add(SP, extraspace, O5_savedSP);
duke@435 866 #endif // _LP64
duke@435 867
duke@435 868 __ mov((frame::varargs_offset)*wordSize -
twisti@1861 869 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
duke@435 870 // Jump to the interpreter just as if interpreter was doing it.
duke@435 871 __ jmpl(G3_scratch, 0, G0);
duke@435 872 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
duke@435 873 // (really L0) is in use by the compiled frame as a generic temp. However,
duke@435 874 // the interpreter does not know where its args are without some kind of
duke@435 875 // arg pointer being passed in. Pass it in Gargs.
duke@435 876 __ delayed()->add(SP, G1, Gargs);
duke@435 877 }
duke@435 878
twisti@3969 879 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg,
twisti@3969 880 address code_start, address code_end,
twisti@3969 881 Label& L_ok) {
twisti@3969 882 Label L_fail;
twisti@3969 883 __ set(ExternalAddress(code_start), temp_reg);
twisti@3969 884 __ set(pointer_delta(code_end, code_start, 1), temp2_reg);
twisti@3969 885 __ cmp(pc_reg, temp_reg);
twisti@3969 886 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail);
twisti@3969 887 __ delayed()->add(temp_reg, temp2_reg, temp_reg);
twisti@3969 888 __ cmp(pc_reg, temp_reg);
twisti@3969 889 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok);
twisti@3969 890 __ bind(L_fail);
twisti@3969 891 }
twisti@3969 892
duke@435 893 void AdapterGenerator::gen_i2c_adapter(
duke@435 894 int total_args_passed,
duke@435 895 // VMReg max_arg,
duke@435 896 int comp_args_on_stack, // VMRegStackSlots
duke@435 897 const BasicType *sig_bt,
duke@435 898 const VMRegPair *regs) {
duke@435 899
duke@435 900 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
duke@435 901 // layout. Lesp was saved by the calling I-frame and will be restored on
duke@435 902 // return. Meanwhile, outgoing arg space is all owned by the callee
duke@435 903 // C-frame, so we can mangle it at will. After adjusting the frame size,
duke@435 904 // hoist register arguments and repack other args according to the compiled
duke@435 905 // code convention. Finally, end in a jump to the compiled code. The entry
duke@435 906 // point address is the start of the buffer.
duke@435 907
duke@435 908 // We will only enter here from an interpreted frame and never from after
duke@435 909 // passing thru a c2i. Azul allowed this but we do not. If we lose the
duke@435 910 // race and use a c2i we will remain interpreted for the race loser(s).
duke@435 911 // This removes all sorts of headaches on the x86 side and also eliminates
duke@435 912 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
duke@435 913
twisti@3969 914 // More detail:
twisti@3969 915 // Adapters can be frameless because they do not require the caller
twisti@3969 916 // to perform additional cleanup work, such as correcting the stack pointer.
twisti@3969 917 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
twisti@3969 918 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
twisti@3969 919 // even if a callee has modified the stack pointer.
twisti@3969 920 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
twisti@3969 921 // routinely repairs its caller's stack pointer (from sender_sp, which is set
twisti@3969 922 // up via the senderSP register).
twisti@3969 923 // In other words, if *either* the caller or callee is interpreted, we can
twisti@3969 924 // get the stack pointer repaired after a call.
twisti@3969 925 // This is why c2i and i2c adapters cannot be indefinitely composed.
twisti@3969 926 // In particular, if a c2i adapter were to somehow call an i2c adapter,
twisti@3969 927 // both caller and callee would be compiled methods, and neither would
twisti@3969 928 // clean up the stack pointer changes performed by the two adapters.
twisti@3969 929 // If this happens, control eventually transfers back to the compiled
twisti@3969 930 // caller, but with an uncorrected stack, causing delayed havoc.
twisti@3969 931
twisti@3969 932 if (VerifyAdapterCalls &&
twisti@3969 933 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
twisti@3969 934 // So, let's test for cascading c2i/i2c adapters right now.
twisti@3969 935 // assert(Interpreter::contains($return_addr) ||
twisti@3969 936 // StubRoutines::contains($return_addr),
twisti@3969 937 // "i2c adapter must return to an interpreter frame");
twisti@3969 938 __ block_comment("verify_i2c { ");
twisti@3969 939 Label L_ok;
twisti@3969 940 if (Interpreter::code() != NULL)
twisti@3969 941 range_check(masm, O7, O0, O1,
twisti@3969 942 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
twisti@3969 943 L_ok);
twisti@3969 944 if (StubRoutines::code1() != NULL)
twisti@3969 945 range_check(masm, O7, O0, O1,
twisti@3969 946 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
twisti@3969 947 L_ok);
twisti@3969 948 if (StubRoutines::code2() != NULL)
twisti@3969 949 range_check(masm, O7, O0, O1,
twisti@3969 950 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
twisti@3969 951 L_ok);
twisti@3969 952 const char* msg = "i2c adapter must return to an interpreter frame";
twisti@3969 953 __ block_comment(msg);
twisti@3969 954 __ stop(msg);
twisti@3969 955 __ bind(L_ok);
twisti@3969 956 __ block_comment("} verify_i2ce ");
twisti@3969 957 }
twisti@3969 958
duke@435 959 // As you can see from the list of inputs & outputs there are not a lot
duke@435 960 // of temp registers to work with: mostly G1, G3 & G4.
duke@435 961
duke@435 962 // Inputs:
duke@435 963 // G2_thread - TLS
duke@435 964 // G5_method - Method oop
jrose@1145 965 // G4 (Gargs) - Pointer to interpreter's args
jrose@1145 966 // O0..O4 - free for scratch
jrose@1145 967 // O5_savedSP - Caller's saved SP, to be restored if needed
duke@435 968 // O6 - Current SP!
duke@435 969 // O7 - Valid return address
jrose@1145 970 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@435 971
duke@435 972 // Outputs:
duke@435 973 // G2_thread - TLS
duke@435 974 // G1, G4 - Outgoing long args in 32-bit build
duke@435 975 // O0-O5 - Outgoing args in compiled layout
duke@435 976 // O6 - Adjusted or restored SP
duke@435 977 // O7 - Valid return address
twisti@1919 978 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
duke@435 979 // F0-F7 - more outgoing args
duke@435 980
duke@435 981
jrose@1145 982 // Gargs is the incoming argument base, and also an outgoing argument.
duke@435 983 __ sub(Gargs, BytesPerWord, Gargs);
duke@435 984
duke@435 985 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
duke@435 986 // WITH O7 HOLDING A VALID RETURN PC
duke@435 987 //
duke@435 988 // | |
duke@435 989 // : java stack :
duke@435 990 // | |
duke@435 991 // +--------------+ <--- start of outgoing args
duke@435 992 // | receiver | |
duke@435 993 // : rest of args : |---size is java-arg-words
duke@435 994 // | | |
duke@435 995 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
duke@435 996 // | | |
duke@435 997 // : unused : |---Space for max Java stack, plus stack alignment
duke@435 998 // | | |
duke@435 999 // +--------------+ <--- SP + 16*wordsize
duke@435 1000 // | |
duke@435 1001 // : window :
duke@435 1002 // | |
duke@435 1003 // +--------------+ <--- SP
duke@435 1004
duke@435 1005 // WE REPACK THE STACK. We use the common calling convention layout as
duke@435 1006 // discovered by calling SharedRuntime::calling_convention. We assume it
duke@435 1007 // causes an arbitrary shuffle of memory, which may require some register
duke@435 1008 // temps to do the shuffle. We hope for (and optimize for) the case where
duke@435 1009 // temps are not needed. We may have to resize the stack slightly, in case
duke@435 1010 // we need alignment padding (32-bit interpreter can pass longs & doubles
duke@435 1011 // misaligned, but the compilers expect them aligned).
duke@435 1012 //
duke@435 1013 // | |
duke@435 1014 // : java stack :
duke@435 1015 // | |
duke@435 1016 // +--------------+ <--- start of outgoing args
duke@435 1017 // | pad, align | |
duke@435 1018 // +--------------+ |
duke@435 1019 // | ints, floats | |---Outgoing stack args, packed low.
duke@435 1020 // +--------------+ | First few args in registers.
duke@435 1021 // : doubles : |
duke@435 1022 // | longs | |
duke@435 1023 // +--------------+ <--- SP' + 16*wordsize
duke@435 1024 // | |
duke@435 1025 // : window :
duke@435 1026 // | |
duke@435 1027 // +--------------+ <--- SP'
duke@435 1028
duke@435 1029 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
duke@435 1030 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
duke@435 1031 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
duke@435 1032
duke@435 1033 // Cut-out for having no stack args. Since up to 6 args are passed
duke@435 1034 // in registers, we will commonly have no stack args.
duke@435 1035 if (comp_args_on_stack > 0) {
duke@435 1036
duke@435 1037 // Convert VMReg stack slots to words.
duke@435 1038 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
duke@435 1039 // Round up to miminum stack alignment, in wordSize
duke@435 1040 comp_words_on_stack = round_to(comp_words_on_stack, 2);
duke@435 1041 // Now compute the distance from Lesp to SP. This calculation does not
duke@435 1042 // include the space for total_args_passed because Lesp has not yet popped
duke@435 1043 // the arguments.
duke@435 1044 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
duke@435 1045 }
duke@435 1046
duke@435 1047 // Will jump to the compiled code just as if compiled code was doing it.
duke@435 1048 // Pre-load the register-jump target early, to schedule it better.
duke@435 1049 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
duke@435 1050
duke@435 1051 // Now generate the shuffle code. Pick up all register args and move the
duke@435 1052 // rest through G1_scratch.
duke@435 1053 for (int i=0; i<total_args_passed; i++) {
duke@435 1054 if (sig_bt[i] == T_VOID) {
duke@435 1055 // Longs and doubles are passed in native word order, but misaligned
duke@435 1056 // in the 32-bit build.
duke@435 1057 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
duke@435 1058 continue;
duke@435 1059 }
duke@435 1060
duke@435 1061 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
duke@435 1062 // 32-bit build and aligned in the 64-bit build. Look for the obvious
duke@435 1063 // ldx/lddf optimizations.
duke@435 1064
duke@435 1065 // Load in argument order going down.
twisti@1861 1066 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@435 1067 set_Rdisp(G1_scratch);
duke@435 1068
duke@435 1069 VMReg r_1 = regs[i].first();
duke@435 1070 VMReg r_2 = regs[i].second();
duke@435 1071 if (!r_1->is_valid()) {
duke@435 1072 assert(!r_2->is_valid(), "");
duke@435 1073 continue;
duke@435 1074 }
duke@435 1075 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
duke@435 1076 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
duke@435 1077 if (r_2->is_valid()) r_2 = r_1->next();
duke@435 1078 }
duke@435 1079 if (r_1->is_Register()) { // Register argument
duke@435 1080 Register r = r_1->as_Register()->after_restore();
duke@435 1081 if (!r_2->is_valid()) {
duke@435 1082 __ ld(Gargs, arg_slot(ld_off), r);
duke@435 1083 } else {
duke@435 1084 #ifdef _LP64
duke@435 1085 // In V9, longs are given 2 64-bit slots in the interpreter, but the
duke@435 1086 // data is passed in only 1 slot.
twisti@1441 1087 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
duke@435 1088 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@435 1089 __ ldx(Gargs, slot, r);
duke@435 1090 #else
duke@435 1091 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
duke@435 1092 // stack shuffle. Load the first 2 longs into G1/G4 later.
duke@435 1093 #endif
duke@435 1094 }
duke@435 1095 } else {
duke@435 1096 assert(r_1->is_FloatRegister(), "");
duke@435 1097 if (!r_2->is_valid()) {
duke@435 1098 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
duke@435 1099 } else {
duke@435 1100 #ifdef _LP64
duke@435 1101 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
duke@435 1102 // data is passed in only 1 slot. This code also handles longs that
duke@435 1103 // are passed on the stack, but need a stack-to-stack move through a
duke@435 1104 // spare float register.
twisti@1441 1105 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
duke@435 1106 next_arg_slot(ld_off) : arg_slot(ld_off);
duke@435 1107 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
duke@435 1108 #else
duke@435 1109 // Need to marshal 64-bit value from misaligned Lesp loads
duke@435 1110 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
duke@435 1111 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
duke@435 1112 #endif
duke@435 1113 }
duke@435 1114 }
duke@435 1115 // Was the argument really intended to be on the stack, but was loaded
duke@435 1116 // into F8/F9?
duke@435 1117 if (regs[i].first()->is_stack()) {
duke@435 1118 assert(r_1->as_FloatRegister() == F8, "fix this code");
duke@435 1119 // Convert stack slot to an SP offset
duke@435 1120 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
duke@435 1121 // Store down the shuffled stack word. Target address _is_ aligned.
twisti@1441 1122 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
twisti@1441 1123 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
twisti@1441 1124 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
duke@435 1125 }
duke@435 1126 }
duke@435 1127 bool made_space = false;
duke@435 1128 #ifndef _LP64
duke@435 1129 // May need to pick up a few long args in G1/G4
duke@435 1130 bool g4_crushed = false;
duke@435 1131 bool g3_crushed = false;
duke@435 1132 for (int i=0; i<total_args_passed; i++) {
duke@435 1133 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
duke@435 1134 // Load in argument order going down
twisti@1861 1135 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
duke@435 1136 // Need to marshal 64-bit value from misaligned Lesp loads
duke@435 1137 Register r = regs[i].first()->as_Register()->after_restore();
duke@435 1138 if (r == G1 || r == G4) {
duke@435 1139 assert(!g4_crushed, "ordering problem");
duke@435 1140 if (r == G4){
duke@435 1141 g4_crushed = true;
duke@435 1142 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@435 1143 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@435 1144 } else {
duke@435 1145 // better schedule this way
duke@435 1146 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@435 1147 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
duke@435 1148 }
duke@435 1149 g3_crushed = true;
duke@435 1150 __ sllx(r, 32, r);
duke@435 1151 __ or3(G3_scratch, r, r);
duke@435 1152 } else {
duke@435 1153 assert(r->is_out(), "longs passed in two O registers");
duke@435 1154 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
duke@435 1155 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
duke@435 1156 }
duke@435 1157 }
duke@435 1158 }
duke@435 1159 #endif
duke@435 1160
duke@435 1161 // Jump to the compiled code just as if compiled code was doing it.
duke@435 1162 //
duke@435 1163 #ifndef _LP64
duke@435 1164 if (g3_crushed) {
duke@435 1165 // Rats load was wasted, at least it is in cache...
twisti@1162 1166 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
duke@435 1167 }
duke@435 1168 #endif /* _LP64 */
duke@435 1169
duke@435 1170 // 6243940 We might end up in handle_wrong_method if
duke@435 1171 // the callee is deoptimized as we race thru here. If that
duke@435 1172 // happens we don't want to take a safepoint because the
duke@435 1173 // caller frame will look interpreted and arguments are now
duke@435 1174 // "compiled" so it is much better to make this transition
duke@435 1175 // invisible to the stack walking code. Unfortunately if
duke@435 1176 // we try and find the callee by normal means a safepoint
duke@435 1177 // is possible. So we stash the desired callee in the thread
duke@435 1178 // and the vm will find there should this case occur.
twisti@1162 1179 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
duke@435 1180 __ st_ptr(G5_method, callee_target_addr);
duke@435 1181
duke@435 1182 if (StressNonEntrant) {
duke@435 1183 // Open a big window for deopt failure
duke@435 1184 __ save_frame(0);
duke@435 1185 __ mov(G0, L0);
duke@435 1186 Label loop;
duke@435 1187 __ bind(loop);
duke@435 1188 __ sub(L0, 1, L0);
kvn@3037 1189 __ br_null_short(L0, Assembler::pt, loop);
duke@435 1190
duke@435 1191 __ restore();
duke@435 1192 }
duke@435 1193
duke@435 1194
duke@435 1195 __ jmpl(G3, 0, G0);
duke@435 1196 __ delayed()->nop();
duke@435 1197 }
duke@435 1198
duke@435 1199 // ---------------------------------------------------------------
duke@435 1200 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
duke@435 1201 int total_args_passed,
duke@435 1202 // VMReg max_arg,
duke@435 1203 int comp_args_on_stack, // VMRegStackSlots
duke@435 1204 const BasicType *sig_bt,
never@1622 1205 const VMRegPair *regs,
never@1622 1206 AdapterFingerPrint* fingerprint) {
duke@435 1207 address i2c_entry = __ pc();
duke@435 1208
duke@435 1209 AdapterGenerator agen(masm);
duke@435 1210
duke@435 1211 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
duke@435 1212
duke@435 1213
duke@435 1214 // -------------------------------------------------------------------------
duke@435 1215 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
duke@435 1216 // args start out packed in the compiled layout. They need to be unpacked
duke@435 1217 // into the interpreter layout. This will almost always require some stack
duke@435 1218 // space. We grow the current (compiled) stack, then repack the args. We
duke@435 1219 // finally end in a jump to the generic interpreter entry point. On exit
duke@435 1220 // from the interpreter, the interpreter will restore our SP (lest the
duke@435 1221 // compiled code, which relys solely on SP and not FP, get sick).
duke@435 1222
duke@435 1223 address c2i_unverified_entry = __ pc();
duke@435 1224 Label skip_fixup;
duke@435 1225 {
duke@435 1226 #if !defined(_LP64) && defined(COMPILER2)
duke@435 1227 Register R_temp = L0; // another scratch register
duke@435 1228 #else
duke@435 1229 Register R_temp = G1; // another scratch register
duke@435 1230 #endif
duke@435 1231
twisti@1162 1232 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@435 1233
duke@435 1234 __ verify_oop(O0);
duke@435 1235 __ verify_oop(G5_method);
coleenp@548 1236 __ load_klass(O0, G3_scratch);
duke@435 1237 __ verify_oop(G3_scratch);
duke@435 1238
duke@435 1239 #if !defined(_LP64) && defined(COMPILER2)
duke@435 1240 __ save(SP, -frame::register_save_words*wordSize, SP);
duke@435 1241 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@435 1242 __ verify_oop(R_temp);
duke@435 1243 __ cmp(G3_scratch, R_temp);
duke@435 1244 __ restore();
duke@435 1245 #else
duke@435 1246 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
duke@435 1247 __ verify_oop(R_temp);
duke@435 1248 __ cmp(G3_scratch, R_temp);
duke@435 1249 #endif
duke@435 1250
duke@435 1251 Label ok, ok2;
duke@435 1252 __ brx(Assembler::equal, false, Assembler::pt, ok);
duke@435 1253 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
twisti@1162 1254 __ jump_to(ic_miss, G3_scratch);
duke@435 1255 __ delayed()->nop();
duke@435 1256
duke@435 1257 __ bind(ok);
duke@435 1258 // Method might have been compiled since the call site was patched to
duke@435 1259 // interpreted if that is the case treat it as a miss so we can get
duke@435 1260 // the call site corrected.
duke@435 1261 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
duke@435 1262 __ bind(ok2);
kvn@3037 1263 __ br_null(G3_scratch, false, Assembler::pt, skip_fixup);
duke@435 1264 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
twisti@1162 1265 __ jump_to(ic_miss, G3_scratch);
duke@435 1266 __ delayed()->nop();
duke@435 1267
duke@435 1268 }
duke@435 1269
duke@435 1270 address c2i_entry = __ pc();
duke@435 1271
duke@435 1272 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
duke@435 1273
duke@435 1274 __ flush();
never@1622 1275 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
duke@435 1276
duke@435 1277 }
duke@435 1278
duke@435 1279 // Helper function for native calling conventions
duke@435 1280 static VMReg int_stk_helper( int i ) {
duke@435 1281 // Bias any stack based VMReg we get by ignoring the window area
duke@435 1282 // but not the register parameter save area.
duke@435 1283 //
duke@435 1284 // This is strange for the following reasons. We'd normally expect
duke@435 1285 // the calling convention to return an VMReg for a stack slot
duke@435 1286 // completely ignoring any abi reserved area. C2 thinks of that
duke@435 1287 // abi area as only out_preserve_stack_slots. This does not include
duke@435 1288 // the area allocated by the C abi to store down integer arguments
duke@435 1289 // because the java calling convention does not use it. So
duke@435 1290 // since c2 assumes that there are only out_preserve_stack_slots
duke@435 1291 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
duke@435 1292 // location the c calling convention must add in this bias amount
duke@435 1293 // to make up for the fact that the out_preserve_stack_slots is
duke@435 1294 // insufficient for C calls. What a mess. I sure hope those 6
duke@435 1295 // stack words were worth it on every java call!
duke@435 1296
duke@435 1297 // Another way of cleaning this up would be for out_preserve_stack_slots
duke@435 1298 // to take a parameter to say whether it was C or java calling conventions.
duke@435 1299 // Then things might look a little better (but not much).
duke@435 1300
duke@435 1301 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
duke@435 1302 if( mem_parm_offset < 0 ) {
duke@435 1303 return as_oRegister(i)->as_VMReg();
duke@435 1304 } else {
duke@435 1305 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
duke@435 1306 // Now return a biased offset that will be correct when out_preserve_slots is added back in
duke@435 1307 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
duke@435 1308 }
duke@435 1309 }
duke@435 1310
duke@435 1311
duke@435 1312 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
duke@435 1313 VMRegPair *regs,
duke@435 1314 int total_args_passed) {
duke@435 1315
duke@435 1316 // Return the number of VMReg stack_slots needed for the args.
duke@435 1317 // This value does not include an abi space (like register window
duke@435 1318 // save area).
duke@435 1319
duke@435 1320 // The native convention is V8 if !LP64
duke@435 1321 // The LP64 convention is the V9 convention which is slightly more sane.
duke@435 1322
duke@435 1323 // We return the amount of VMReg stack slots we need to reserve for all
duke@435 1324 // the arguments NOT counting out_preserve_stack_slots. Since we always
duke@435 1325 // have space for storing at least 6 registers to memory we start with that.
duke@435 1326 // See int_stk_helper for a further discussion.
duke@435 1327 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
duke@435 1328
duke@435 1329 #ifdef _LP64
duke@435 1330 // V9 convention: All things "as-if" on double-wide stack slots.
duke@435 1331 // Hoist any int/ptr/long's in the first 6 to int regs.
duke@435 1332 // Hoist any flt/dbl's in the first 16 dbl regs.
duke@435 1333 int j = 0; // Count of actual args, not HALVES
duke@435 1334 for( int i=0; i<total_args_passed; i++, j++ ) {
duke@435 1335 switch( sig_bt[i] ) {
duke@435 1336 case T_BOOLEAN:
duke@435 1337 case T_BYTE:
duke@435 1338 case T_CHAR:
duke@435 1339 case T_INT:
duke@435 1340 case T_SHORT:
duke@435 1341 regs[i].set1( int_stk_helper( j ) ); break;
duke@435 1342 case T_LONG:
duke@435 1343 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@435 1344 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@435 1345 case T_ARRAY:
duke@435 1346 case T_OBJECT:
duke@435 1347 regs[i].set2( int_stk_helper( j ) );
duke@435 1348 break;
duke@435 1349 case T_FLOAT:
duke@435 1350 if ( j < 16 ) {
duke@435 1351 // V9ism: floats go in ODD registers
duke@435 1352 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
duke@435 1353 } else {
duke@435 1354 // V9ism: floats go in ODD stack slot
duke@435 1355 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
duke@435 1356 }
duke@435 1357 break;
duke@435 1358 case T_DOUBLE:
duke@435 1359 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@435 1360 if ( j < 16 ) {
duke@435 1361 // V9ism: doubles go in EVEN/ODD regs
duke@435 1362 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
duke@435 1363 } else {
duke@435 1364 // V9ism: doubles go in EVEN/ODD stack slots
duke@435 1365 regs[i].set2(VMRegImpl::stack2reg(j<<1));
duke@435 1366 }
duke@435 1367 break;
duke@435 1368 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
duke@435 1369 default:
duke@435 1370 ShouldNotReachHere();
duke@435 1371 }
duke@435 1372 if (regs[i].first()->is_stack()) {
duke@435 1373 int off = regs[i].first()->reg2stack();
duke@435 1374 if (off > max_stack_slots) max_stack_slots = off;
duke@435 1375 }
duke@435 1376 if (regs[i].second()->is_stack()) {
duke@435 1377 int off = regs[i].second()->reg2stack();
duke@435 1378 if (off > max_stack_slots) max_stack_slots = off;
duke@435 1379 }
duke@435 1380 }
duke@435 1381
duke@435 1382 #else // _LP64
duke@435 1383 // V8 convention: first 6 things in O-regs, rest on stack.
duke@435 1384 // Alignment is willy-nilly.
duke@435 1385 for( int i=0; i<total_args_passed; i++ ) {
duke@435 1386 switch( sig_bt[i] ) {
duke@435 1387 case T_ADDRESS: // raw pointers, like current thread, for VM calls
duke@435 1388 case T_ARRAY:
duke@435 1389 case T_BOOLEAN:
duke@435 1390 case T_BYTE:
duke@435 1391 case T_CHAR:
duke@435 1392 case T_FLOAT:
duke@435 1393 case T_INT:
duke@435 1394 case T_OBJECT:
duke@435 1395 case T_SHORT:
duke@435 1396 regs[i].set1( int_stk_helper( i ) );
duke@435 1397 break;
duke@435 1398 case T_DOUBLE:
duke@435 1399 case T_LONG:
duke@435 1400 assert( sig_bt[i+1] == T_VOID, "expecting half" );
duke@435 1401 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
duke@435 1402 break;
duke@435 1403 case T_VOID: regs[i].set_bad(); break;
duke@435 1404 default:
duke@435 1405 ShouldNotReachHere();
duke@435 1406 }
duke@435 1407 if (regs[i].first()->is_stack()) {
duke@435 1408 int off = regs[i].first()->reg2stack();
duke@435 1409 if (off > max_stack_slots) max_stack_slots = off;
duke@435 1410 }
duke@435 1411 if (regs[i].second()->is_stack()) {
duke@435 1412 int off = regs[i].second()->reg2stack();
duke@435 1413 if (off > max_stack_slots) max_stack_slots = off;
duke@435 1414 }
duke@435 1415 }
duke@435 1416 #endif // _LP64
duke@435 1417
duke@435 1418 return round_to(max_stack_slots + 1, 2);
duke@435 1419
duke@435 1420 }
duke@435 1421
duke@435 1422
duke@435 1423 // ---------------------------------------------------------------------------
duke@435 1424 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@435 1425 switch (ret_type) {
duke@435 1426 case T_FLOAT:
duke@435 1427 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
duke@435 1428 break;
duke@435 1429 case T_DOUBLE:
duke@435 1430 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
duke@435 1431 break;
duke@435 1432 }
duke@435 1433 }
duke@435 1434
duke@435 1435 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
duke@435 1436 switch (ret_type) {
duke@435 1437 case T_FLOAT:
duke@435 1438 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
duke@435 1439 break;
duke@435 1440 case T_DOUBLE:
duke@435 1441 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
duke@435 1442 break;
duke@435 1443 }
duke@435 1444 }
duke@435 1445
duke@435 1446 // Check and forward and pending exception. Thread is stored in
duke@435 1447 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
duke@435 1448 // is no exception handler. We merely pop this frame off and throw the
duke@435 1449 // exception in the caller's frame.
duke@435 1450 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
duke@435 1451 Label L;
duke@435 1452 __ br_null(Rex_oop, false, Assembler::pt, L);
duke@435 1453 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
duke@435 1454 // Since this is a native call, we *know* the proper exception handler
duke@435 1455 // without calling into the VM: it's the empty function. Just pop this
duke@435 1456 // frame and then jump to forward_exception_entry; O7 will contain the
duke@435 1457 // native caller's return PC.
twisti@1162 1458 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
twisti@1162 1459 __ jump_to(exception_entry, G3_scratch);
duke@435 1460 __ delayed()->restore(); // Pop this frame off.
duke@435 1461 __ bind(L);
duke@435 1462 }
duke@435 1463
duke@435 1464 // A simple move of integer like type
duke@435 1465 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@435 1466 if (src.first()->is_stack()) {
duke@435 1467 if (dst.first()->is_stack()) {
duke@435 1468 // stack to stack
duke@435 1469 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@435 1470 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1471 } else {
duke@435 1472 // stack to reg
duke@435 1473 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@435 1474 }
duke@435 1475 } else if (dst.first()->is_stack()) {
duke@435 1476 // reg to stack
duke@435 1477 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1478 } else {
duke@435 1479 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@435 1480 }
duke@435 1481 }
duke@435 1482
duke@435 1483 // On 64 bit we will store integer like items to the stack as
duke@435 1484 // 64 bits items (sparc abi) even though java would only store
duke@435 1485 // 32bits for a parameter. On 32bit it will simply be 32 bits
duke@435 1486 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
duke@435 1487 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@435 1488 if (src.first()->is_stack()) {
duke@435 1489 if (dst.first()->is_stack()) {
duke@435 1490 // stack to stack
duke@435 1491 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@435 1492 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1493 } else {
duke@435 1494 // stack to reg
duke@435 1495 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@435 1496 }
duke@435 1497 } else if (dst.first()->is_stack()) {
duke@435 1498 // reg to stack
duke@435 1499 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1500 } else {
duke@435 1501 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@435 1502 }
duke@435 1503 }
duke@435 1504
duke@435 1505
never@3500 1506 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
never@3500 1507 if (src.first()->is_stack()) {
never@3500 1508 if (dst.first()->is_stack()) {
never@3500 1509 // stack to stack
never@3500 1510 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5);
never@3500 1511 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
never@3500 1512 } else {
never@3500 1513 // stack to reg
never@3500 1514 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
never@3500 1515 }
never@3500 1516 } else if (dst.first()->is_stack()) {
never@3500 1517 // reg to stack
never@3500 1518 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
never@3500 1519 } else {
never@3500 1520 __ mov(src.first()->as_Register(), dst.first()->as_Register());
never@3500 1521 }
never@3500 1522 }
never@3500 1523
never@3500 1524
duke@435 1525 // An oop arg. Must pass a handle not the oop itself
duke@435 1526 static void object_move(MacroAssembler* masm,
duke@435 1527 OopMap* map,
duke@435 1528 int oop_handle_offset,
duke@435 1529 int framesize_in_slots,
duke@435 1530 VMRegPair src,
duke@435 1531 VMRegPair dst,
duke@435 1532 bool is_receiver,
duke@435 1533 int* receiver_offset) {
duke@435 1534
duke@435 1535 // must pass a handle. First figure out the location we use as a handle
duke@435 1536
duke@435 1537 if (src.first()->is_stack()) {
duke@435 1538 // Oop is already on the stack
duke@435 1539 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
duke@435 1540 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
duke@435 1541 __ ld_ptr(rHandle, 0, L4);
duke@435 1542 #ifdef _LP64
duke@435 1543 __ movr( Assembler::rc_z, L4, G0, rHandle );
duke@435 1544 #else
duke@435 1545 __ tst( L4 );
duke@435 1546 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@435 1547 #endif
duke@435 1548 if (dst.first()->is_stack()) {
duke@435 1549 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1550 }
duke@435 1551 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
duke@435 1552 if (is_receiver) {
duke@435 1553 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
duke@435 1554 }
duke@435 1555 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
duke@435 1556 } else {
duke@435 1557 // Oop is in an input register pass we must flush it to the stack
duke@435 1558 const Register rOop = src.first()->as_Register();
duke@435 1559 const Register rHandle = L5;
duke@435 1560 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
duke@435 1561 int offset = oop_slot*VMRegImpl::stack_slot_size;
duke@435 1562 Label skip;
duke@435 1563 __ st_ptr(rOop, SP, offset + STACK_BIAS);
duke@435 1564 if (is_receiver) {
duke@435 1565 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
duke@435 1566 }
duke@435 1567 map->set_oop(VMRegImpl::stack2reg(oop_slot));
duke@435 1568 __ add(SP, offset + STACK_BIAS, rHandle);
duke@435 1569 #ifdef _LP64
duke@435 1570 __ movr( Assembler::rc_z, rOop, G0, rHandle );
duke@435 1571 #else
duke@435 1572 __ tst( rOop );
duke@435 1573 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
duke@435 1574 #endif
duke@435 1575
duke@435 1576 if (dst.first()->is_stack()) {
duke@435 1577 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1578 } else {
duke@435 1579 __ mov(rHandle, dst.first()->as_Register());
duke@435 1580 }
duke@435 1581 }
duke@435 1582 }
duke@435 1583
duke@435 1584 // A float arg may have to do float reg int reg conversion
duke@435 1585 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@435 1586 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
duke@435 1587
duke@435 1588 if (src.first()->is_stack()) {
duke@435 1589 if (dst.first()->is_stack()) {
duke@435 1590 // stack to stack the easiest of the bunch
duke@435 1591 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@435 1592 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1593 } else {
duke@435 1594 // stack to reg
duke@435 1595 if (dst.first()->is_Register()) {
duke@435 1596 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@435 1597 } else {
duke@435 1598 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@435 1599 }
duke@435 1600 }
duke@435 1601 } else if (dst.first()->is_stack()) {
duke@435 1602 // reg to stack
duke@435 1603 if (src.first()->is_Register()) {
duke@435 1604 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1605 } else {
duke@435 1606 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1607 }
duke@435 1608 } else {
duke@435 1609 // reg to reg
duke@435 1610 if (src.first()->is_Register()) {
duke@435 1611 if (dst.first()->is_Register()) {
duke@435 1612 // gpr -> gpr
duke@435 1613 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@435 1614 } else {
duke@435 1615 // gpr -> fpr
duke@435 1616 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
duke@435 1617 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@435 1618 }
duke@435 1619 } else if (dst.first()->is_Register()) {
duke@435 1620 // fpr -> gpr
duke@435 1621 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
duke@435 1622 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
duke@435 1623 } else {
duke@435 1624 // fpr -> fpr
duke@435 1625 // In theory these overlap but the ordering is such that this is likely a nop
duke@435 1626 if ( src.first() != dst.first()) {
duke@435 1627 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@435 1628 }
duke@435 1629 }
duke@435 1630 }
duke@435 1631 }
duke@435 1632
duke@435 1633 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@435 1634 VMRegPair src_lo(src.first());
duke@435 1635 VMRegPair src_hi(src.second());
duke@435 1636 VMRegPair dst_lo(dst.first());
duke@435 1637 VMRegPair dst_hi(dst.second());
duke@435 1638 simple_move32(masm, src_lo, dst_lo);
duke@435 1639 simple_move32(masm, src_hi, dst_hi);
duke@435 1640 }
duke@435 1641
duke@435 1642 // A long move
duke@435 1643 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@435 1644
duke@435 1645 // Do the simple ones here else do two int moves
duke@435 1646 if (src.is_single_phys_reg() ) {
duke@435 1647 if (dst.is_single_phys_reg()) {
duke@435 1648 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@435 1649 } else {
duke@435 1650 // split src into two separate registers
duke@435 1651 // Remember hi means hi address or lsw on sparc
duke@435 1652 // Move msw to lsw
duke@435 1653 if (dst.second()->is_reg()) {
duke@435 1654 // MSW -> MSW
duke@435 1655 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
duke@435 1656 // Now LSW -> LSW
duke@435 1657 // this will only move lo -> lo and ignore hi
duke@435 1658 VMRegPair split(dst.second());
duke@435 1659 simple_move32(masm, src, split);
duke@435 1660 } else {
duke@435 1661 VMRegPair split(src.first(), L4->as_VMReg());
duke@435 1662 // MSW -> MSW (lo ie. first word)
duke@435 1663 __ srax(src.first()->as_Register(), 32, L4);
duke@435 1664 split_long_move(masm, split, dst);
duke@435 1665 }
duke@435 1666 }
duke@435 1667 } else if (dst.is_single_phys_reg()) {
duke@435 1668 if (src.is_adjacent_aligned_on_stack(2)) {
never@739 1669 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@435 1670 } else {
duke@435 1671 // dst is a single reg.
duke@435 1672 // Remember lo is low address not msb for stack slots
duke@435 1673 // and lo is the "real" register for registers
duke@435 1674 // src is
duke@435 1675
duke@435 1676 VMRegPair split;
duke@435 1677
duke@435 1678 if (src.first()->is_reg()) {
duke@435 1679 // src.lo (msw) is a reg, src.hi is stk/reg
duke@435 1680 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
duke@435 1681 split.set_pair(dst.first(), src.first());
duke@435 1682 } else {
duke@435 1683 // msw is stack move to L5
duke@435 1684 // lsw is stack move to dst.lo (real reg)
duke@435 1685 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
duke@435 1686 split.set_pair(dst.first(), L5->as_VMReg());
duke@435 1687 }
duke@435 1688
duke@435 1689 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
duke@435 1690 // msw -> src.lo/L5, lsw -> dst.lo
duke@435 1691 split_long_move(masm, src, split);
duke@435 1692
duke@435 1693 // So dst now has the low order correct position the
duke@435 1694 // msw half
duke@435 1695 __ sllx(split.first()->as_Register(), 32, L5);
duke@435 1696
duke@435 1697 const Register d = dst.first()->as_Register();
duke@435 1698 __ or3(L5, d, d);
duke@435 1699 }
duke@435 1700 } else {
duke@435 1701 // For LP64 we can probably do better.
duke@435 1702 split_long_move(masm, src, dst);
duke@435 1703 }
duke@435 1704 }
duke@435 1705
duke@435 1706 // A double move
duke@435 1707 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
duke@435 1708
duke@435 1709 // The painful thing here is that like long_move a VMRegPair might be
duke@435 1710 // 1: a single physical register
duke@435 1711 // 2: two physical registers (v8)
duke@435 1712 // 3: a physical reg [lo] and a stack slot [hi] (v8)
duke@435 1713 // 4: two stack slots
duke@435 1714
duke@435 1715 // Since src is always a java calling convention we know that the src pair
duke@435 1716 // is always either all registers or all stack (and aligned?)
duke@435 1717
duke@435 1718 // in a register [lo] and a stack slot [hi]
duke@435 1719 if (src.first()->is_stack()) {
duke@435 1720 if (dst.first()->is_stack()) {
duke@435 1721 // stack to stack the easiest of the bunch
duke@435 1722 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
duke@435 1723 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
duke@435 1724 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@435 1725 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1726 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@435 1727 } else {
duke@435 1728 // stack to reg
duke@435 1729 if (dst.second()->is_stack()) {
duke@435 1730 // stack -> reg, stack -> stack
duke@435 1731 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@435 1732 if (dst.first()->is_Register()) {
duke@435 1733 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@435 1734 } else {
duke@435 1735 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@435 1736 }
duke@435 1737 // This was missing. (very rare case)
duke@435 1738 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@435 1739 } else {
duke@435 1740 // stack -> reg
duke@435 1741 // Eventually optimize for alignment QQQ
duke@435 1742 if (dst.first()->is_Register()) {
duke@435 1743 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
duke@435 1744 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
duke@435 1745 } else {
duke@435 1746 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
duke@435 1747 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
duke@435 1748 }
duke@435 1749 }
duke@435 1750 }
duke@435 1751 } else if (dst.first()->is_stack()) {
duke@435 1752 // reg to stack
duke@435 1753 if (src.first()->is_Register()) {
duke@435 1754 // Eventually optimize for alignment QQQ
duke@435 1755 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1756 if (src.second()->is_stack()) {
duke@435 1757 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
duke@435 1758 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@435 1759 } else {
duke@435 1760 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@435 1761 }
duke@435 1762 } else {
duke@435 1763 // fpr to stack
duke@435 1764 if (src.second()->is_stack()) {
duke@435 1765 ShouldNotReachHere();
duke@435 1766 } else {
duke@435 1767 // Is the stack aligned?
duke@435 1768 if (reg2offset(dst.first()) & 0x7) {
duke@435 1769 // No do as pairs
duke@435 1770 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1771 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
duke@435 1772 } else {
duke@435 1773 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
duke@435 1774 }
duke@435 1775 }
duke@435 1776 }
duke@435 1777 } else {
duke@435 1778 // reg to reg
duke@435 1779 if (src.first()->is_Register()) {
duke@435 1780 if (dst.first()->is_Register()) {
duke@435 1781 // gpr -> gpr
duke@435 1782 __ mov(src.first()->as_Register(), dst.first()->as_Register());
duke@435 1783 __ mov(src.second()->as_Register(), dst.second()->as_Register());
duke@435 1784 } else {
duke@435 1785 // gpr -> fpr
duke@435 1786 // ought to be able to do a single store
duke@435 1787 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
duke@435 1788 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
duke@435 1789 // ought to be able to do a single load
duke@435 1790 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
duke@435 1791 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
duke@435 1792 }
duke@435 1793 } else if (dst.first()->is_Register()) {
duke@435 1794 // fpr -> gpr
duke@435 1795 // ought to be able to do a single store
duke@435 1796 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
duke@435 1797 // ought to be able to do a single load
duke@435 1798 // REMEMBER first() is low address not LSB
duke@435 1799 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
duke@435 1800 if (dst.second()->is_Register()) {
duke@435 1801 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
duke@435 1802 } else {
duke@435 1803 __ ld(FP, -4 + STACK_BIAS, L4);
duke@435 1804 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
duke@435 1805 }
duke@435 1806 } else {
duke@435 1807 // fpr -> fpr
duke@435 1808 // In theory these overlap but the ordering is such that this is likely a nop
duke@435 1809 if ( src.first() != dst.first()) {
duke@435 1810 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
duke@435 1811 }
duke@435 1812 }
duke@435 1813 }
duke@435 1814 }
duke@435 1815
duke@435 1816 // Creates an inner frame if one hasn't already been created, and
duke@435 1817 // saves a copy of the thread in L7_thread_cache
duke@435 1818 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
duke@435 1819 if (!*already_created) {
duke@435 1820 __ save_frame(0);
duke@435 1821 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
duke@435 1822 // Don't use save_thread because it smashes G2 and we merely want to save a
duke@435 1823 // copy
duke@435 1824 __ mov(G2_thread, L7_thread_cache);
duke@435 1825 *already_created = true;
duke@435 1826 }
duke@435 1827 }
duke@435 1828
never@3500 1829
never@3500 1830 static void save_or_restore_arguments(MacroAssembler* masm,
never@3500 1831 const int stack_slots,
never@3500 1832 const int total_in_args,
never@3500 1833 const int arg_save_area,
never@3500 1834 OopMap* map,
never@3500 1835 VMRegPair* in_regs,
never@3500 1836 BasicType* in_sig_bt) {
never@3500 1837 // if map is non-NULL then the code should store the values,
never@3500 1838 // otherwise it should load them.
never@3500 1839 if (map != NULL) {
never@3500 1840 // Fill in the map
never@3500 1841 for (int i = 0; i < total_in_args; i++) {
never@3500 1842 if (in_sig_bt[i] == T_ARRAY) {
never@3500 1843 if (in_regs[i].first()->is_stack()) {
never@3500 1844 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
never@3500 1845 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
never@3500 1846 } else if (in_regs[i].first()->is_Register()) {
never@3500 1847 map->set_oop(in_regs[i].first());
never@3500 1848 } else {
never@3500 1849 ShouldNotReachHere();
never@3500 1850 }
never@3500 1851 }
never@3500 1852 }
never@3500 1853 }
never@3500 1854
never@3500 1855 // Save or restore double word values
never@3500 1856 int handle_index = 0;
never@3500 1857 for (int i = 0; i < total_in_args; i++) {
never@3500 1858 int slot = handle_index + arg_save_area;
never@3500 1859 int offset = slot * VMRegImpl::stack_slot_size;
never@3500 1860 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) {
never@3500 1861 const Register reg = in_regs[i].first()->as_Register();
never@3500 1862 if (reg->is_global()) {
never@3500 1863 handle_index += 2;
never@3500 1864 assert(handle_index <= stack_slots, "overflow");
never@3500 1865 if (map != NULL) {
never@3500 1866 __ stx(reg, SP, offset + STACK_BIAS);
never@3500 1867 } else {
never@3500 1868 __ ldx(SP, offset + STACK_BIAS, reg);
never@3500 1869 }
never@3500 1870 }
never@3500 1871 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) {
never@3500 1872 handle_index += 2;
never@3500 1873 assert(handle_index <= stack_slots, "overflow");
never@3500 1874 if (map != NULL) {
never@3500 1875 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
never@3500 1876 } else {
never@3500 1877 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
never@3500 1878 }
never@3500 1879 }
never@3500 1880 }
never@3500 1881 // Save floats
never@3500 1882 for (int i = 0; i < total_in_args; i++) {
never@3500 1883 int slot = handle_index + arg_save_area;
never@3500 1884 int offset = slot * VMRegImpl::stack_slot_size;
never@3500 1885 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) {
never@3500 1886 handle_index++;
never@3500 1887 assert(handle_index <= stack_slots, "overflow");
never@3500 1888 if (map != NULL) {
never@3500 1889 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS);
never@3500 1890 } else {
never@3500 1891 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister());
never@3500 1892 }
never@3500 1893 }
never@3500 1894 }
never@3500 1895
never@3500 1896 }
never@3500 1897
never@3500 1898
never@3500 1899 // Check GC_locker::needs_gc and enter the runtime if it's true. This
never@3500 1900 // keeps a new JNI critical region from starting until a GC has been
never@3500 1901 // forced. Save down any oops in registers and describe them in an
never@3500 1902 // OopMap.
never@3500 1903 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
never@3500 1904 const int stack_slots,
never@3500 1905 const int total_in_args,
never@3500 1906 const int arg_save_area,
never@3500 1907 OopMapSet* oop_maps,
never@3500 1908 VMRegPair* in_regs,
never@3500 1909 BasicType* in_sig_bt) {
never@3500 1910 __ block_comment("check GC_locker::needs_gc");
never@3500 1911 Label cont;
never@3500 1912 AddressLiteral sync_state(GC_locker::needs_gc_address());
never@3500 1913 __ load_bool_contents(sync_state, G3_scratch);
never@3500 1914 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont);
never@3500 1915 __ delayed()->nop();
never@3500 1916
never@3500 1917 // Save down any values that are live in registers and call into the
never@3500 1918 // runtime to halt for a GC
never@3500 1919 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
never@3500 1920 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3500 1921 arg_save_area, map, in_regs, in_sig_bt);
never@3500 1922
never@3500 1923 __ mov(G2_thread, L7_thread_cache);
never@3500 1924
never@3500 1925 __ set_last_Java_frame(SP, noreg);
never@3500 1926
never@3500 1927 __ block_comment("block_for_jni_critical");
never@3500 1928 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type);
never@3500 1929 __ delayed()->mov(L7_thread_cache, O0);
never@3500 1930 oop_maps->add_gc_map( __ offset(), map);
never@3500 1931
never@3500 1932 __ restore_thread(L7_thread_cache); // restore G2_thread
never@3500 1933 __ reset_last_Java_frame();
never@3500 1934
never@3500 1935 // Reload all the register arguments
never@3500 1936 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3500 1937 arg_save_area, NULL, in_regs, in_sig_bt);
never@3500 1938
never@3500 1939 __ bind(cont);
never@3500 1940 #ifdef ASSERT
never@3500 1941 if (StressCriticalJNINatives) {
never@3500 1942 // Stress register saving
never@3500 1943 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
never@3500 1944 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3500 1945 arg_save_area, map, in_regs, in_sig_bt);
never@3500 1946 // Destroy argument registers
never@3500 1947 for (int i = 0; i < total_in_args; i++) {
never@3500 1948 if (in_regs[i].first()->is_Register()) {
never@3500 1949 const Register reg = in_regs[i].first()->as_Register();
never@3500 1950 if (reg->is_global()) {
never@3500 1951 __ mov(G0, reg);
never@3500 1952 }
never@3500 1953 } else if (in_regs[i].first()->is_FloatRegister()) {
never@3500 1954 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister());
never@3500 1955 }
never@3500 1956 }
never@3500 1957
never@3500 1958 save_or_restore_arguments(masm, stack_slots, total_in_args,
never@3500 1959 arg_save_area, NULL, in_regs, in_sig_bt);
never@3500 1960 }
never@3500 1961 #endif
never@3500 1962 }
never@3500 1963
never@3500 1964 // Unpack an array argument into a pointer to the body and the length
never@3500 1965 // if the array is non-null, otherwise pass 0 for both.
never@3500 1966 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
never@3500 1967 // Pass the length, ptr pair
never@3500 1968 Label is_null, done;
never@3500 1969 if (reg.first()->is_stack()) {
never@3500 1970 VMRegPair tmp = reg64_to_VMRegPair(L2);
never@3500 1971 // Load the arg up from the stack
never@3500 1972 move_ptr(masm, reg, tmp);
never@3500 1973 reg = tmp;
never@3500 1974 }
never@3500 1975 __ cmp(reg.first()->as_Register(), G0);
never@3500 1976 __ brx(Assembler::equal, false, Assembler::pt, is_null);
never@3500 1977 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4);
never@3500 1978 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg);
never@3500 1979 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4);
never@3500 1980 move32_64(masm, reg64_to_VMRegPair(L4), length_arg);
never@3500 1981 __ ba_short(done);
never@3500 1982 __ bind(is_null);
never@3500 1983 // Pass zeros
never@3500 1984 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg);
never@3500 1985 move32_64(masm, reg64_to_VMRegPair(G0), length_arg);
never@3500 1986 __ bind(done);
never@3500 1987 }
never@3500 1988
twisti@3969 1989 static void verify_oop_args(MacroAssembler* masm,
twisti@3969 1990 int total_args_passed,
twisti@3969 1991 const BasicType* sig_bt,
twisti@3969 1992 const VMRegPair* regs) {
twisti@3969 1993 Register temp_reg = G5_method; // not part of any compiled calling seq
twisti@3969 1994 if (VerifyOops) {
twisti@3969 1995 for (int i = 0; i < total_args_passed; i++) {
twisti@3969 1996 if (sig_bt[i] == T_OBJECT ||
twisti@3969 1997 sig_bt[i] == T_ARRAY) {
twisti@3969 1998 VMReg r = regs[i].first();
twisti@3969 1999 assert(r->is_valid(), "bad oop arg");
twisti@3969 2000 if (r->is_stack()) {
twisti@3969 2001 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
twisti@3969 2002 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg);
twisti@3969 2003 __ ld_ptr(SP, ld_off, temp_reg);
twisti@3969 2004 __ verify_oop(temp_reg);
twisti@3969 2005 } else {
twisti@3969 2006 __ verify_oop(r->as_Register());
twisti@3969 2007 }
twisti@3969 2008 }
twisti@3969 2009 }
twisti@3969 2010 }
twisti@3969 2011 }
twisti@3969 2012
twisti@3969 2013 static void gen_special_dispatch(MacroAssembler* masm,
twisti@3969 2014 int total_args_passed,
twisti@3969 2015 int comp_args_on_stack,
twisti@3969 2016 vmIntrinsics::ID special_dispatch,
twisti@3969 2017 const BasicType* sig_bt,
twisti@3969 2018 const VMRegPair* regs) {
twisti@3969 2019 verify_oop_args(masm, total_args_passed, sig_bt, regs);
twisti@3969 2020
twisti@3969 2021 // Now write the args into the outgoing interpreter space
twisti@3969 2022 bool has_receiver = false;
twisti@3969 2023 Register receiver_reg = noreg;
twisti@3969 2024 int member_arg_pos = -1;
twisti@3969 2025 Register member_reg = noreg;
twisti@3969 2026 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(special_dispatch);
twisti@3969 2027 if (ref_kind != 0) {
twisti@3969 2028 member_arg_pos = total_args_passed - 1; // trailing MemberName argument
twisti@3969 2029 member_reg = G5_method; // known to be free at this point
twisti@3969 2030 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
twisti@3969 2031 } else if (special_dispatch == vmIntrinsics::_invokeBasic) {
twisti@3969 2032 has_receiver = true;
twisti@3969 2033 } else {
twisti@3969 2034 fatal(err_msg("special_dispatch=%d", special_dispatch));
twisti@3969 2035 }
twisti@3969 2036
twisti@3969 2037 if (member_reg != noreg) {
twisti@3969 2038 // Load the member_arg into register, if necessary.
twisti@3969 2039 assert(member_arg_pos >= 0 && member_arg_pos < total_args_passed, "oob");
twisti@3969 2040 assert(sig_bt[member_arg_pos] == T_OBJECT, "dispatch argument must be an object");
twisti@3969 2041 VMReg r = regs[member_arg_pos].first();
twisti@3969 2042 assert(r->is_valid(), "bad member arg");
twisti@3969 2043 if (r->is_stack()) {
twisti@3969 2044 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
twisti@3969 2045 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
twisti@3969 2046 __ ld_ptr(SP, ld_off, member_reg);
twisti@3969 2047 } else {
twisti@3969 2048 // no data motion is needed
twisti@3969 2049 member_reg = r->as_Register();
twisti@3969 2050 }
twisti@3969 2051 }
twisti@3969 2052
twisti@3969 2053 if (has_receiver) {
twisti@3969 2054 // Make sure the receiver is loaded into a register.
twisti@3969 2055 assert(total_args_passed > 0, "oob");
twisti@3969 2056 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
twisti@3969 2057 VMReg r = regs[0].first();
twisti@3969 2058 assert(r->is_valid(), "bad receiver arg");
twisti@3969 2059 if (r->is_stack()) {
twisti@3969 2060 // Porting note: This assumes that compiled calling conventions always
twisti@3969 2061 // pass the receiver oop in a register. If this is not true on some
twisti@3969 2062 // platform, pick a temp and load the receiver from stack.
twisti@3969 2063 assert(false, "receiver always in a register");
twisti@3969 2064 receiver_reg = G3_scratch; // known to be free at this point
twisti@3969 2065 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS;
twisti@3969 2066 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg);
twisti@3969 2067 __ ld_ptr(SP, ld_off, receiver_reg);
twisti@3969 2068 } else {
twisti@3969 2069 // no data motion is needed
twisti@3969 2070 receiver_reg = r->as_Register();
twisti@3969 2071 }
twisti@3969 2072 }
twisti@3969 2073
twisti@3969 2074 // Figure out which address we are really jumping to:
twisti@3969 2075 MethodHandles::generate_method_handle_dispatch(masm, special_dispatch,
twisti@3969 2076 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
twisti@3969 2077 }
twisti@3969 2078
duke@435 2079 // ---------------------------------------------------------------------------
duke@435 2080 // Generate a native wrapper for a given method. The method takes arguments
duke@435 2081 // in the Java compiled code convention, marshals them to the native
duke@435 2082 // convention (handlizes oops, etc), transitions to native, makes the call,
duke@435 2083 // returns to java state (possibly blocking), unhandlizes any result and
duke@435 2084 // returns.
twisti@3969 2085 //
twisti@3969 2086 // Critical native functions are a shorthand for the use of
twisti@3969 2087 // GetPrimtiveArrayCritical and disallow the use of any other JNI
twisti@3969 2088 // functions. The wrapper is expected to unpack the arguments before
twisti@3969 2089 // passing them to the callee and perform checks before and after the
twisti@3969 2090 // native call to ensure that they GC_locker
twisti@3969 2091 // lock_critical/unlock_critical semantics are followed. Some other
twisti@3969 2092 // parts of JNI setup are skipped like the tear down of the JNI handle
twisti@3969 2093 // block and the check for pending exceptions it's impossible for them
twisti@3969 2094 // to be thrown.
twisti@3969 2095 //
twisti@3969 2096 // They are roughly structured like this:
twisti@3969 2097 // if (GC_locker::needs_gc())
twisti@3969 2098 // SharedRuntime::block_for_jni_critical();
twisti@3969 2099 // tranistion to thread_in_native
twisti@3969 2100 // unpack arrray arguments and call native entry point
twisti@3969 2101 // check for safepoint in progress
twisti@3969 2102 // check if any thread suspend flags are set
twisti@3969 2103 // call into JVM and possible unlock the JNI critical
twisti@3969 2104 // if a GC was suppressed while in the critical native.
twisti@3969 2105 // transition back to thread_in_Java
twisti@3969 2106 // return to caller
twisti@3969 2107 //
duke@435 2108 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
duke@435 2109 methodHandle method,
twisti@2687 2110 int compile_id,
duke@435 2111 int total_in_args,
duke@435 2112 int comp_args_on_stack, // in VMRegStackSlots
twisti@3969 2113 BasicType* in_sig_bt,
twisti@3969 2114 VMRegPair* in_regs,
duke@435 2115 BasicType ret_type) {
twisti@3969 2116 if (method->is_method_handle_intrinsic()) {
twisti@3969 2117 vmIntrinsics::ID iid = method->intrinsic_id();
twisti@3969 2118 intptr_t start = (intptr_t)__ pc();
twisti@3969 2119 int vep_offset = ((intptr_t)__ pc()) - start;
twisti@3969 2120 gen_special_dispatch(masm,
twisti@3969 2121 total_in_args,
twisti@3969 2122 comp_args_on_stack,
twisti@3969 2123 method->intrinsic_id(),
twisti@3969 2124 in_sig_bt,
twisti@3969 2125 in_regs);
twisti@3969 2126 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
twisti@3969 2127 __ flush();
twisti@3969 2128 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
twisti@3969 2129 return nmethod::new_native_nmethod(method,
twisti@3969 2130 compile_id,
twisti@3969 2131 masm->code(),
twisti@3969 2132 vep_offset,
twisti@3969 2133 frame_complete,
twisti@3969 2134 stack_slots / VMRegImpl::slots_per_word,
twisti@3969 2135 in_ByteSize(-1),
twisti@3969 2136 in_ByteSize(-1),
twisti@3969 2137 (OopMapSet*)NULL);
twisti@3969 2138 }
never@3500 2139 bool is_critical_native = true;
never@3500 2140 address native_func = method->critical_native_function();
never@3500 2141 if (native_func == NULL) {
never@3500 2142 native_func = method->native_function();
never@3500 2143 is_critical_native = false;
never@3500 2144 }
never@3500 2145 assert(native_func != NULL, "must have function");
duke@435 2146
duke@435 2147 // Native nmethod wrappers never take possesion of the oop arguments.
duke@435 2148 // So the caller will gc the arguments. The only thing we need an
duke@435 2149 // oopMap for is if the call is static
duke@435 2150 //
duke@435 2151 // An OopMap for lock (and class if static), and one for the VM call itself
duke@435 2152 OopMapSet *oop_maps = new OopMapSet();
duke@435 2153 intptr_t start = (intptr_t)__ pc();
duke@435 2154
duke@435 2155 // First thing make an ic check to see if we should even be here
duke@435 2156 {
duke@435 2157 Label L;
duke@435 2158 const Register temp_reg = G3_scratch;
twisti@1162 2159 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
duke@435 2160 __ verify_oop(O0);
coleenp@548 2161 __ load_klass(O0, temp_reg);
kvn@3037 2162 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
duke@435 2163
twisti@1162 2164 __ jump_to(ic_miss, temp_reg);
duke@435 2165 __ delayed()->nop();
duke@435 2166 __ align(CodeEntryAlignment);
duke@435 2167 __ bind(L);
duke@435 2168 }
duke@435 2169
duke@435 2170 int vep_offset = ((intptr_t)__ pc()) - start;
duke@435 2171
duke@435 2172 #ifdef COMPILER1
duke@435 2173 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
duke@435 2174 // Object.hashCode can pull the hashCode from the header word
duke@435 2175 // instead of doing a full VM transition once it's been computed.
duke@435 2176 // Since hashCode is usually polymorphic at call sites we can't do
duke@435 2177 // this optimization at the call site without a lot of work.
duke@435 2178 Label slowCase;
duke@435 2179 Register receiver = O0;
duke@435 2180 Register result = O0;
duke@435 2181 Register header = G3_scratch;
duke@435 2182 Register hash = G3_scratch; // overwrite header value with hash value
duke@435 2183 Register mask = G1; // to get hash field from header
duke@435 2184
duke@435 2185 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
duke@435 2186 // We depend on hash_mask being at most 32 bits and avoid the use of
duke@435 2187 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
duke@435 2188 // vm: see markOop.hpp.
duke@435 2189 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
duke@435 2190 __ sethi(markOopDesc::hash_mask, mask);
duke@435 2191 __ btst(markOopDesc::unlocked_value, header);
duke@435 2192 __ br(Assembler::zero, false, Assembler::pn, slowCase);
duke@435 2193 if (UseBiasedLocking) {
duke@435 2194 // Check if biased and fall through to runtime if so
duke@435 2195 __ delayed()->nop();
duke@435 2196 __ btst(markOopDesc::biased_lock_bit_in_place, header);
duke@435 2197 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
duke@435 2198 }
duke@435 2199 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
duke@435 2200
duke@435 2201 // Check for a valid (non-zero) hash code and get its value.
duke@435 2202 #ifdef _LP64
duke@435 2203 __ srlx(header, markOopDesc::hash_shift, hash);
duke@435 2204 #else
duke@435 2205 __ srl(header, markOopDesc::hash_shift, hash);
duke@435 2206 #endif
duke@435 2207 __ andcc(hash, mask, hash);
duke@435 2208 __ br(Assembler::equal, false, Assembler::pn, slowCase);
duke@435 2209 __ delayed()->nop();
duke@435 2210
duke@435 2211 // leaf return.
duke@435 2212 __ retl();
duke@435 2213 __ delayed()->mov(hash, result);
duke@435 2214 __ bind(slowCase);
duke@435 2215 }
duke@435 2216 #endif // COMPILER1
duke@435 2217
duke@435 2218
duke@435 2219 // We have received a description of where all the java arg are located
duke@435 2220 // on entry to the wrapper. We need to convert these args to where
duke@435 2221 // the jni function will expect them. To figure out where they go
duke@435 2222 // we convert the java signature to a C signature by inserting
duke@435 2223 // the hidden arguments as arg[0] and possibly arg[1] (static method)
duke@435 2224
never@3500 2225 int total_c_args = total_in_args;
never@3500 2226 int total_save_slots = 6 * VMRegImpl::slots_per_word;
never@3500 2227 if (!is_critical_native) {
never@3500 2228 total_c_args += 1;
never@3500 2229 if (method->is_static()) {
never@3500 2230 total_c_args++;
never@3500 2231 }
never@3500 2232 } else {
never@3500 2233 for (int i = 0; i < total_in_args; i++) {
never@3500 2234 if (in_sig_bt[i] == T_ARRAY) {
never@3500 2235 // These have to be saved and restored across the safepoint
never@3500 2236 total_c_args++;
never@3500 2237 }
never@3500 2238 }
duke@435 2239 }
duke@435 2240
duke@435 2241 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
never@3500 2242 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
never@3500 2243 BasicType* in_elem_bt = NULL;
duke@435 2244
duke@435 2245 int argc = 0;
never@3500 2246 if (!is_critical_native) {
never@3500 2247 out_sig_bt[argc++] = T_ADDRESS;
never@3500 2248 if (method->is_static()) {
never@3500 2249 out_sig_bt[argc++] = T_OBJECT;
never@3500 2250 }
never@3500 2251
never@3500 2252 for (int i = 0; i < total_in_args ; i++ ) {
never@3500 2253 out_sig_bt[argc++] = in_sig_bt[i];
never@3500 2254 }
never@3500 2255 } else {
never@3500 2256 Thread* THREAD = Thread::current();
never@3500 2257 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
never@3500 2258 SignatureStream ss(method->signature());
never@3500 2259 for (int i = 0; i < total_in_args ; i++ ) {
never@3500 2260 if (in_sig_bt[i] == T_ARRAY) {
never@3500 2261 // Arrays are passed as int, elem* pair
never@3500 2262 out_sig_bt[argc++] = T_INT;
never@3500 2263 out_sig_bt[argc++] = T_ADDRESS;
never@3500 2264 Symbol* atype = ss.as_symbol(CHECK_NULL);
never@3500 2265 const char* at = atype->as_C_string();
never@3500 2266 if (strlen(at) == 2) {
never@3500 2267 assert(at[0] == '[', "must be");
never@3500 2268 switch (at[1]) {
never@3500 2269 case 'B': in_elem_bt[i] = T_BYTE; break;
never@3500 2270 case 'C': in_elem_bt[i] = T_CHAR; break;
never@3500 2271 case 'D': in_elem_bt[i] = T_DOUBLE; break;
never@3500 2272 case 'F': in_elem_bt[i] = T_FLOAT; break;
never@3500 2273 case 'I': in_elem_bt[i] = T_INT; break;
never@3500 2274 case 'J': in_elem_bt[i] = T_LONG; break;
never@3500 2275 case 'S': in_elem_bt[i] = T_SHORT; break;
never@3500 2276 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
never@3500 2277 default: ShouldNotReachHere();
never@3500 2278 }
never@3500 2279 }
never@3500 2280 } else {
never@3500 2281 out_sig_bt[argc++] = in_sig_bt[i];
never@3500 2282 in_elem_bt[i] = T_VOID;
never@3500 2283 }
never@3500 2284 if (in_sig_bt[i] != T_VOID) {
never@3500 2285 assert(in_sig_bt[i] == ss.type(), "must match");
never@3500 2286 ss.next();
never@3500 2287 }
never@3500 2288 }
duke@435 2289 }
duke@435 2290
duke@435 2291 // Now figure out where the args must be stored and how much stack space
duke@435 2292 // they require (neglecting out_preserve_stack_slots but space for storing
duke@435 2293 // the 1st six register arguments). It's weird see int_stk_helper.
duke@435 2294 //
duke@435 2295 int out_arg_slots;
duke@435 2296 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
duke@435 2297
never@3500 2298 if (is_critical_native) {
never@3500 2299 // Critical natives may have to call out so they need a save area
never@3500 2300 // for register arguments.
never@3500 2301 int double_slots = 0;
never@3500 2302 int single_slots = 0;
never@3500 2303 for ( int i = 0; i < total_in_args; i++) {
never@3500 2304 if (in_regs[i].first()->is_Register()) {
never@3500 2305 const Register reg = in_regs[i].first()->as_Register();
never@3500 2306 switch (in_sig_bt[i]) {
never@3500 2307 case T_ARRAY:
never@3500 2308 case T_BOOLEAN:
never@3500 2309 case T_BYTE:
never@3500 2310 case T_SHORT:
never@3500 2311 case T_CHAR:
never@3500 2312 case T_INT: assert(reg->is_in(), "don't need to save these"); break;
never@3500 2313 case T_LONG: if (reg->is_global()) double_slots++; break;
never@3500 2314 default: ShouldNotReachHere();
never@3500 2315 }
never@3500 2316 } else if (in_regs[i].first()->is_FloatRegister()) {
never@3500 2317 switch (in_sig_bt[i]) {
never@3500 2318 case T_FLOAT: single_slots++; break;
never@3500 2319 case T_DOUBLE: double_slots++; break;
never@3500 2320 default: ShouldNotReachHere();
never@3500 2321 }
never@3500 2322 }
never@3500 2323 }
never@3500 2324 total_save_slots = double_slots * 2 + single_slots;
never@3500 2325 }
never@3500 2326
duke@435 2327 // Compute framesize for the wrapper. We need to handlize all oops in
duke@435 2328 // registers. We must create space for them here that is disjoint from
duke@435 2329 // the windowed save area because we have no control over when we might
duke@435 2330 // flush the window again and overwrite values that gc has since modified.
duke@435 2331 // (The live window race)
duke@435 2332 //
duke@435 2333 // We always just allocate 6 word for storing down these object. This allow
duke@435 2334 // us to simply record the base and use the Ireg number to decide which
duke@435 2335 // slot to use. (Note that the reg number is the inbound number not the
duke@435 2336 // outbound number).
duke@435 2337 // We must shuffle args to match the native convention, and include var-args space.
duke@435 2338
duke@435 2339 // Calculate the total number of stack slots we will need.
duke@435 2340
duke@435 2341 // First count the abi requirement plus all of the outgoing args
duke@435 2342 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
duke@435 2343
duke@435 2344 // Now the space for the inbound oop handle area
duke@435 2345
never@3500 2346 int oop_handle_offset = round_to(stack_slots, 2);
never@3500 2347 stack_slots += total_save_slots;
duke@435 2348
duke@435 2349 // Now any space we need for handlizing a klass if static method
duke@435 2350
duke@435 2351 int klass_slot_offset = 0;
duke@435 2352 int klass_offset = -1;
duke@435 2353 int lock_slot_offset = 0;
duke@435 2354 bool is_static = false;
duke@435 2355
duke@435 2356 if (method->is_static()) {
duke@435 2357 klass_slot_offset = stack_slots;
duke@435 2358 stack_slots += VMRegImpl::slots_per_word;
duke@435 2359 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
duke@435 2360 is_static = true;
duke@435 2361 }
duke@435 2362
duke@435 2363 // Plus a lock if needed
duke@435 2364
duke@435 2365 if (method->is_synchronized()) {
duke@435 2366 lock_slot_offset = stack_slots;
duke@435 2367 stack_slots += VMRegImpl::slots_per_word;
duke@435 2368 }
duke@435 2369
duke@435 2370 // Now a place to save return value or as a temporary for any gpr -> fpr moves
duke@435 2371 stack_slots += 2;
duke@435 2372
duke@435 2373 // Ok The space we have allocated will look like:
duke@435 2374 //
duke@435 2375 //
duke@435 2376 // FP-> | |
duke@435 2377 // |---------------------|
duke@435 2378 // | 2 slots for moves |
duke@435 2379 // |---------------------|
duke@435 2380 // | lock box (if sync) |
duke@435 2381 // |---------------------| <- lock_slot_offset
duke@435 2382 // | klass (if static) |
duke@435 2383 // |---------------------| <- klass_slot_offset
duke@435 2384 // | oopHandle area |
duke@435 2385 // |---------------------| <- oop_handle_offset
duke@435 2386 // | outbound memory |
duke@435 2387 // | based arguments |
duke@435 2388 // | |
duke@435 2389 // |---------------------|
duke@435 2390 // | vararg area |
duke@435 2391 // |---------------------|
duke@435 2392 // | |
duke@435 2393 // SP-> | out_preserved_slots |
duke@435 2394 //
duke@435 2395 //
duke@435 2396
duke@435 2397
duke@435 2398 // Now compute actual number of stack words we need rounding to make
duke@435 2399 // stack properly aligned.
duke@435 2400 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
duke@435 2401
duke@435 2402 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
duke@435 2403
duke@435 2404 // Generate stack overflow check before creating frame
duke@435 2405 __ generate_stack_overflow_check(stack_size);
duke@435 2406
duke@435 2407 // Generate a new frame for the wrapper.
duke@435 2408 __ save(SP, -stack_size, SP);
duke@435 2409
duke@435 2410 int frame_complete = ((intptr_t)__ pc()) - start;
duke@435 2411
duke@435 2412 __ verify_thread();
duke@435 2413
never@3500 2414 if (is_critical_native) {
never@3500 2415 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args,
never@3500 2416 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
never@3500 2417 }
duke@435 2418
duke@435 2419 //
duke@435 2420 // We immediately shuffle the arguments so that any vm call we have to
duke@435 2421 // make from here on out (sync slow path, jvmti, etc.) we will have
duke@435 2422 // captured the oops from our caller and have a valid oopMap for
duke@435 2423 // them.
duke@435 2424
duke@435 2425 // -----------------
duke@435 2426 // The Grand Shuffle
duke@435 2427 //
duke@435 2428 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
duke@435 2429 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
duke@435 2430 // the class mirror instead of a receiver. This pretty much guarantees that
duke@435 2431 // register layout will not match. We ignore these extra arguments during
duke@435 2432 // the shuffle. The shuffle is described by the two calling convention
duke@435 2433 // vectors we have in our possession. We simply walk the java vector to
duke@435 2434 // get the source locations and the c vector to get the destinations.
duke@435 2435 // Because we have a new window and the argument registers are completely
duke@435 2436 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
duke@435 2437 // here.
duke@435 2438
duke@435 2439 // This is a trick. We double the stack slots so we can claim
duke@435 2440 // the oops in the caller's frame. Since we are sure to have
duke@435 2441 // more args than the caller doubling is enough to make
duke@435 2442 // sure we can capture all the incoming oop args from the
duke@435 2443 // caller.
duke@435 2444 //
duke@435 2445 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
duke@435 2446 // Record sp-based slot for receiver on stack for non-static methods
duke@435 2447 int receiver_offset = -1;
duke@435 2448
duke@435 2449 // We move the arguments backward because the floating point registers
duke@435 2450 // destination will always be to a register with a greater or equal register
duke@435 2451 // number or the stack.
duke@435 2452
duke@435 2453 #ifdef ASSERT
duke@435 2454 bool reg_destroyed[RegisterImpl::number_of_registers];
duke@435 2455 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
duke@435 2456 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
duke@435 2457 reg_destroyed[r] = false;
duke@435 2458 }
duke@435 2459 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
duke@435 2460 freg_destroyed[f] = false;
duke@435 2461 }
duke@435 2462
duke@435 2463 #endif /* ASSERT */
duke@435 2464
never@3500 2465 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) {
duke@435 2466
duke@435 2467 #ifdef ASSERT
duke@435 2468 if (in_regs[i].first()->is_Register()) {
duke@435 2469 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
duke@435 2470 } else if (in_regs[i].first()->is_FloatRegister()) {
duke@435 2471 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
duke@435 2472 }
duke@435 2473 if (out_regs[c_arg].first()->is_Register()) {
duke@435 2474 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
duke@435 2475 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
duke@435 2476 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
duke@435 2477 }
duke@435 2478 #endif /* ASSERT */
duke@435 2479
duke@435 2480 switch (in_sig_bt[i]) {
duke@435 2481 case T_ARRAY:
never@3500 2482 if (is_critical_native) {
never@3500 2483 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]);
never@3500 2484 c_arg--;
never@3500 2485 break;
never@3500 2486 }
duke@435 2487 case T_OBJECT:
never@3500 2488 assert(!is_critical_native, "no oop arguments");
duke@435 2489 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
duke@435 2490 ((i == 0) && (!is_static)),
duke@435 2491 &receiver_offset);
duke@435 2492 break;
duke@435 2493 case T_VOID:
duke@435 2494 break;
duke@435 2495
duke@435 2496 case T_FLOAT:
duke@435 2497 float_move(masm, in_regs[i], out_regs[c_arg]);
never@3500 2498 break;
duke@435 2499
duke@435 2500 case T_DOUBLE:
duke@435 2501 assert( i + 1 < total_in_args &&
duke@435 2502 in_sig_bt[i + 1] == T_VOID &&
duke@435 2503 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
duke@435 2504 double_move(masm, in_regs[i], out_regs[c_arg]);
duke@435 2505 break;
duke@435 2506
duke@435 2507 case T_LONG :
duke@435 2508 long_move(masm, in_regs[i], out_regs[c_arg]);
duke@435 2509 break;
duke@435 2510
duke@435 2511 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
duke@435 2512
duke@435 2513 default:
duke@435 2514 move32_64(masm, in_regs[i], out_regs[c_arg]);
duke@435 2515 }
duke@435 2516 }
duke@435 2517
duke@435 2518 // Pre-load a static method's oop into O1. Used both by locking code and
duke@435 2519 // the normal JNI call code.
never@3500 2520 if (method->is_static() && !is_critical_native) {
duke@435 2521 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
duke@435 2522
duke@435 2523 // Now handlize the static class mirror in O1. It's known not-null.
duke@435 2524 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
duke@435 2525 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
duke@435 2526 __ add(SP, klass_offset + STACK_BIAS, O1);
duke@435 2527 }
duke@435 2528
duke@435 2529
duke@435 2530 const Register L6_handle = L6;
duke@435 2531
duke@435 2532 if (method->is_synchronized()) {
never@3500 2533 assert(!is_critical_native, "unhandled");
duke@435 2534 __ mov(O1, L6_handle);
duke@435 2535 }
duke@435 2536
duke@435 2537 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
duke@435 2538 // except O6/O7. So if we must call out we must push a new frame. We immediately
duke@435 2539 // push a new frame and flush the windows.
duke@435 2540 #ifdef _LP64
duke@435 2541 intptr_t thepc = (intptr_t) __ pc();
duke@435 2542 {
duke@435 2543 address here = __ pc();
duke@435 2544 // Call the next instruction
duke@435 2545 __ call(here + 8, relocInfo::none);
duke@435 2546 __ delayed()->nop();
duke@435 2547 }
duke@435 2548 #else
duke@435 2549 intptr_t thepc = __ load_pc_address(O7, 0);
duke@435 2550 #endif /* _LP64 */
duke@435 2551
duke@435 2552 // We use the same pc/oopMap repeatedly when we call out
duke@435 2553 oop_maps->add_gc_map(thepc - start, map);
duke@435 2554
duke@435 2555 // O7 now has the pc loaded that we will use when we finally call to native.
duke@435 2556
duke@435 2557 // Save thread in L7; it crosses a bunch of VM calls below
duke@435 2558 // Don't use save_thread because it smashes G2 and we merely
duke@435 2559 // want to save a copy
duke@435 2560 __ mov(G2_thread, L7_thread_cache);
duke@435 2561
duke@435 2562
duke@435 2563 // If we create an inner frame once is plenty
duke@435 2564 // when we create it we must also save G2_thread
duke@435 2565 bool inner_frame_created = false;
duke@435 2566
duke@435 2567 // dtrace method entry support
duke@435 2568 {
duke@435 2569 SkipIfEqual skip_if(
duke@435 2570 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@435 2571 // create inner frame
duke@435 2572 __ save_frame(0);
duke@435 2573 __ mov(G2_thread, L7_thread_cache);
duke@435 2574 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@435 2575 __ call_VM_leaf(L7_thread_cache,
duke@435 2576 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
duke@435 2577 G2_thread, O1);
duke@435 2578 __ restore();
duke@435 2579 }
duke@435 2580
dcubed@1045 2581 // RedefineClasses() tracing support for obsolete method entry
dcubed@1045 2582 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
dcubed@1045 2583 // create inner frame
dcubed@1045 2584 __ save_frame(0);
dcubed@1045 2585 __ mov(G2_thread, L7_thread_cache);
dcubed@1045 2586 __ set_oop_constant(JNIHandles::make_local(method()), O1);
dcubed@1045 2587 __ call_VM_leaf(L7_thread_cache,
dcubed@1045 2588 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
dcubed@1045 2589 G2_thread, O1);
dcubed@1045 2590 __ restore();
dcubed@1045 2591 }
dcubed@1045 2592
duke@435 2593 // We are in the jni frame unless saved_frame is true in which case
duke@435 2594 // we are in one frame deeper (the "inner" frame). If we are in the
duke@435 2595 // "inner" frames the args are in the Iregs and if the jni frame then
duke@435 2596 // they are in the Oregs.
duke@435 2597 // If we ever need to go to the VM (for locking, jvmti) then
duke@435 2598 // we will always be in the "inner" frame.
duke@435 2599
duke@435 2600 // Lock a synchronized method
duke@435 2601 int lock_offset = -1; // Set if locked
duke@435 2602 if (method->is_synchronized()) {
duke@435 2603 Register Roop = O1;
duke@435 2604 const Register L3_box = L3;
duke@435 2605
duke@435 2606 create_inner_frame(masm, &inner_frame_created);
duke@435 2607
duke@435 2608 __ ld_ptr(I1, 0, O1);
duke@435 2609 Label done;
duke@435 2610
duke@435 2611 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
duke@435 2612 __ add(FP, lock_offset+STACK_BIAS, L3_box);
duke@435 2613 #ifdef ASSERT
duke@435 2614 if (UseBiasedLocking) {
duke@435 2615 // making the box point to itself will make it clear it went unused
duke@435 2616 // but also be obviously invalid
duke@435 2617 __ st_ptr(L3_box, L3_box, 0);
duke@435 2618 }
duke@435 2619 #endif // ASSERT
duke@435 2620 //
duke@435 2621 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
duke@435 2622 //
duke@435 2623 __ compiler_lock_object(Roop, L1, L3_box, L2);
duke@435 2624 __ br(Assembler::equal, false, Assembler::pt, done);
duke@435 2625 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
duke@435 2626
duke@435 2627
duke@435 2628 // None of the above fast optimizations worked so we have to get into the
duke@435 2629 // slow case of monitor enter. Inline a special case of call_VM that
duke@435 2630 // disallows any pending_exception.
duke@435 2631 __ mov(Roop, O0); // Need oop in O0
duke@435 2632 __ mov(L3_box, O1);
duke@435 2633
duke@435 2634 // Record last_Java_sp, in case the VM code releases the JVM lock.
duke@435 2635
duke@435 2636 __ set_last_Java_frame(FP, I7);
duke@435 2637
duke@435 2638 // do the call
duke@435 2639 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
duke@435 2640 __ delayed()->mov(L7_thread_cache, O2);
duke@435 2641
duke@435 2642 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@435 2643 __ reset_last_Java_frame();
duke@435 2644
duke@435 2645 #ifdef ASSERT
duke@435 2646 { Label L;
duke@435 2647 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@3037 2648 __ br_null_short(O0, Assembler::pt, L);
duke@435 2649 __ stop("no pending exception allowed on exit from IR::monitorenter");
duke@435 2650 __ bind(L);
duke@435 2651 }
duke@435 2652 #endif
duke@435 2653 __ bind(done);
duke@435 2654 }
duke@435 2655
duke@435 2656
duke@435 2657 // Finally just about ready to make the JNI call
duke@435 2658
duke@435 2659 __ flush_windows();
duke@435 2660 if (inner_frame_created) {
duke@435 2661 __ restore();
duke@435 2662 } else {
duke@435 2663 // Store only what we need from this frame
duke@435 2664 // QQQ I think that non-v9 (like we care) we don't need these saves
duke@435 2665 // either as the flush traps and the current window goes too.
duke@435 2666 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@435 2667 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
duke@435 2668 }
duke@435 2669
duke@435 2670 // get JNIEnv* which is first argument to native
never@3500 2671 if (!is_critical_native) {
never@3500 2672 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
never@3500 2673 }
duke@435 2674
duke@435 2675 // Use that pc we placed in O7 a while back as the current frame anchor
duke@435 2676 __ set_last_Java_frame(SP, O7);
duke@435 2677
never@3500 2678 // We flushed the windows ages ago now mark them as flushed before transitioning.
never@3500 2679 __ set(JavaFrameAnchor::flushed, G3_scratch);
never@3500 2680 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
never@3500 2681
duke@435 2682 // Transition from _thread_in_Java to _thread_in_native.
duke@435 2683 __ set(_thread_in_native, G3_scratch);
duke@435 2684
duke@435 2685 #ifdef _LP64
never@3500 2686 AddressLiteral dest(native_func);
duke@435 2687 __ relocate(relocInfo::runtime_call_type);
twisti@1162 2688 __ jumpl_to(dest, O7, O7);
duke@435 2689 #else
never@3500 2690 __ call(native_func, relocInfo::runtime_call_type);
duke@435 2691 #endif
never@3500 2692 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@435 2693
duke@435 2694 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@435 2695
duke@435 2696 // Unpack native results. For int-types, we do any needed sign-extension
duke@435 2697 // and move things into I0. The return value there will survive any VM
duke@435 2698 // calls for blocking or unlocking. An FP or OOP result (handle) is done
duke@435 2699 // specially in the slow-path code.
duke@435 2700 switch (ret_type) {
duke@435 2701 case T_VOID: break; // Nothing to do!
duke@435 2702 case T_FLOAT: break; // Got it where we want it (unless slow-path)
duke@435 2703 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
duke@435 2704 // In 64 bits build result is in O0, in O0, O1 in 32bit build
duke@435 2705 case T_LONG:
duke@435 2706 #ifndef _LP64
duke@435 2707 __ mov(O1, I1);
duke@435 2708 #endif
duke@435 2709 // Fall thru
duke@435 2710 case T_OBJECT: // Really a handle
duke@435 2711 case T_ARRAY:
duke@435 2712 case T_INT:
duke@435 2713 __ mov(O0, I0);
duke@435 2714 break;
duke@435 2715 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
duke@435 2716 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
duke@435 2717 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
duke@435 2718 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
duke@435 2719 break; // Cannot de-handlize until after reclaiming jvm_lock
duke@435 2720 default:
duke@435 2721 ShouldNotReachHere();
duke@435 2722 }
duke@435 2723
never@3500 2724 Label after_transition;
duke@435 2725 // must we block?
duke@435 2726
duke@435 2727 // Block, if necessary, before resuming in _thread_in_Java state.
duke@435 2728 // In order for GC to work, don't clear the last_Java_sp until after blocking.
duke@435 2729 { Label no_block;
twisti@1162 2730 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
duke@435 2731
duke@435 2732 // Switch thread to "native transition" state before reading the synchronization state.
duke@435 2733 // This additional state is necessary because reading and testing the synchronization
duke@435 2734 // state is not atomic w.r.t. GC, as this scenario demonstrates:
duke@435 2735 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
duke@435 2736 // VM thread changes sync state to synchronizing and suspends threads for GC.
duke@435 2737 // Thread A is resumed to finish this native method, but doesn't block here since it
duke@435 2738 // didn't see any synchronization is progress, and escapes.
duke@435 2739 __ set(_thread_in_native_trans, G3_scratch);
twisti@1162 2740 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
duke@435 2741 if(os::is_MP()) {
duke@435 2742 if (UseMembar) {
duke@435 2743 // Force this write out before the read below
duke@435 2744 __ membar(Assembler::StoreLoad);
duke@435 2745 } else {
duke@435 2746 // Write serialization page so VM thread can do a pseudo remote membar.
duke@435 2747 // We use the current thread pointer to calculate a thread specific
duke@435 2748 // offset to write to within the page. This minimizes bus traffic
duke@435 2749 // due to cache line collision.
duke@435 2750 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
duke@435 2751 }
duke@435 2752 }
duke@435 2753 __ load_contents(sync_state, G3_scratch);
duke@435 2754 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
duke@435 2755
duke@435 2756 Label L;
twisti@1162 2757 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
duke@435 2758 __ br(Assembler::notEqual, false, Assembler::pn, L);
twisti@1162 2759 __ delayed()->ld(suspend_state, G3_scratch);
kvn@3037 2760 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block);
duke@435 2761 __ bind(L);
duke@435 2762
duke@435 2763 // Block. Save any potential method result value before the operation and
duke@435 2764 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
duke@435 2765 // lets us share the oopMap we used when we went native rather the create
duke@435 2766 // a distinct one for this pc
duke@435 2767 //
duke@435 2768 save_native_result(masm, ret_type, stack_slots);
never@3500 2769 if (!is_critical_native) {
never@3500 2770 __ call_VM_leaf(L7_thread_cache,
never@3500 2771 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
never@3500 2772 G2_thread);
never@3500 2773 } else {
never@3500 2774 __ call_VM_leaf(L7_thread_cache,
never@3500 2775 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition),
never@3500 2776 G2_thread);
never@3500 2777 }
duke@435 2778
duke@435 2779 // Restore any method result value
duke@435 2780 restore_native_result(masm, ret_type, stack_slots);
never@3500 2781
never@3500 2782 if (is_critical_native) {
never@3500 2783 // The call above performed the transition to thread_in_Java so
never@3500 2784 // skip the transition logic below.
never@3500 2785 __ ba(after_transition);
never@3500 2786 __ delayed()->nop();
never@3500 2787 }
never@3500 2788
duke@435 2789 __ bind(no_block);
duke@435 2790 }
duke@435 2791
duke@435 2792 // thread state is thread_in_native_trans. Any safepoint blocking has already
duke@435 2793 // happened so we can now change state to _thread_in_Java.
duke@435 2794 __ set(_thread_in_Java, G3_scratch);
twisti@1162 2795 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
never@3500 2796 __ bind(after_transition);
duke@435 2797
duke@435 2798 Label no_reguard;
twisti@1162 2799 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
kvn@3037 2800 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard);
duke@435 2801
duke@435 2802 save_native_result(masm, ret_type, stack_slots);
duke@435 2803 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
duke@435 2804 __ delayed()->nop();
duke@435 2805
duke@435 2806 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@435 2807 restore_native_result(masm, ret_type, stack_slots);
duke@435 2808
duke@435 2809 __ bind(no_reguard);
duke@435 2810
duke@435 2811 // Handle possible exception (will unlock if necessary)
duke@435 2812
duke@435 2813 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
duke@435 2814
duke@435 2815 // Unlock
duke@435 2816 if (method->is_synchronized()) {
duke@435 2817 Label done;
duke@435 2818 Register I2_ex_oop = I2;
duke@435 2819 const Register L3_box = L3;
duke@435 2820 // Get locked oop from the handle we passed to jni
duke@435 2821 __ ld_ptr(L6_handle, 0, L4);
duke@435 2822 __ add(SP, lock_offset+STACK_BIAS, L3_box);
duke@435 2823 // Must save pending exception around the slow-path VM call. Since it's a
duke@435 2824 // leaf call, the pending exception (if any) can be kept in a register.
duke@435 2825 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
duke@435 2826 // Now unlock
duke@435 2827 // (Roop, Rmark, Rbox, Rscratch)
duke@435 2828 __ compiler_unlock_object(L4, L1, L3_box, L2);
duke@435 2829 __ br(Assembler::equal, false, Assembler::pt, done);
duke@435 2830 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
duke@435 2831
duke@435 2832 // save and restore any potential method result value around the unlocking
duke@435 2833 // operation. Will save in I0 (or stack for FP returns).
duke@435 2834 save_native_result(masm, ret_type, stack_slots);
duke@435 2835
duke@435 2836 // Must clear pending-exception before re-entering the VM. Since this is
duke@435 2837 // a leaf call, pending-exception-oop can be safely kept in a register.
duke@435 2838 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@435 2839
duke@435 2840 // slow case of monitor enter. Inline a special case of call_VM that
duke@435 2841 // disallows any pending_exception.
duke@435 2842 __ mov(L3_box, O1);
duke@435 2843
duke@435 2844 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
duke@435 2845 __ delayed()->mov(L4, O0); // Need oop in O0
duke@435 2846
duke@435 2847 __ restore_thread(L7_thread_cache); // restore G2_thread
duke@435 2848
duke@435 2849 #ifdef ASSERT
duke@435 2850 { Label L;
duke@435 2851 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
kvn@3037 2852 __ br_null_short(O0, Assembler::pt, L);
duke@435 2853 __ stop("no pending exception allowed on exit from IR::monitorexit");
duke@435 2854 __ bind(L);
duke@435 2855 }
duke@435 2856 #endif
duke@435 2857 restore_native_result(masm, ret_type, stack_slots);
duke@435 2858 // check_forward_pending_exception jump to forward_exception if any pending
duke@435 2859 // exception is set. The forward_exception routine expects to see the
duke@435 2860 // exception in pending_exception and not in a register. Kind of clumsy,
duke@435 2861 // since all folks who branch to forward_exception must have tested
duke@435 2862 // pending_exception first and hence have it in a register already.
duke@435 2863 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
duke@435 2864 __ bind(done);
duke@435 2865 }
duke@435 2866
duke@435 2867 // Tell dtrace about this method exit
duke@435 2868 {
duke@435 2869 SkipIfEqual skip_if(
duke@435 2870 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
duke@435 2871 save_native_result(masm, ret_type, stack_slots);
duke@435 2872 __ set_oop_constant(JNIHandles::make_local(method()), O1);
duke@435 2873 __ call_VM_leaf(L7_thread_cache,
duke@435 2874 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
duke@435 2875 G2_thread, O1);
duke@435 2876 restore_native_result(masm, ret_type, stack_slots);
duke@435 2877 }
duke@435 2878
duke@435 2879 // Clear "last Java frame" SP and PC.
duke@435 2880 __ verify_thread(); // G2_thread must be correct
duke@435 2881 __ reset_last_Java_frame();
duke@435 2882
duke@435 2883 // Unpack oop result
duke@435 2884 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
duke@435 2885 Label L;
duke@435 2886 __ addcc(G0, I0, G0);
duke@435 2887 __ brx(Assembler::notZero, true, Assembler::pt, L);
duke@435 2888 __ delayed()->ld_ptr(I0, 0, I0);
duke@435 2889 __ mov(G0, I0);
duke@435 2890 __ bind(L);
duke@435 2891 __ verify_oop(I0);
duke@435 2892 }
duke@435 2893
never@3500 2894 if (!is_critical_native) {
never@3500 2895 // reset handle block
never@3500 2896 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
never@3500 2897 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
never@3500 2898
never@3500 2899 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
never@3500 2900 check_forward_pending_exception(masm, G3_scratch);
never@3500 2901 }
duke@435 2902
duke@435 2903
duke@435 2904 // Return
duke@435 2905
duke@435 2906 #ifndef _LP64
duke@435 2907 if (ret_type == T_LONG) {
duke@435 2908
duke@435 2909 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
duke@435 2910 __ sllx(I0, 32, G1); // Shift bits into high G1
duke@435 2911 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
duke@435 2912 __ or3 (I1, G1, G1); // OR 64 bits into G1
duke@435 2913 }
duke@435 2914 #endif
duke@435 2915
duke@435 2916 __ ret();
duke@435 2917 __ delayed()->restore();
duke@435 2918
duke@435 2919 __ flush();
duke@435 2920
duke@435 2921 nmethod *nm = nmethod::new_native_nmethod(method,
twisti@2687 2922 compile_id,
duke@435 2923 masm->code(),
duke@435 2924 vep_offset,
duke@435 2925 frame_complete,
duke@435 2926 stack_slots / VMRegImpl::slots_per_word,
duke@435 2927 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
duke@435 2928 in_ByteSize(lock_offset),
duke@435 2929 oop_maps);
never@3500 2930
never@3500 2931 if (is_critical_native) {
never@3500 2932 nm->set_lazy_critical_native(true);
never@3500 2933 }
duke@435 2934 return nm;
duke@435 2935
duke@435 2936 }
duke@435 2937
kamg@551 2938 #ifdef HAVE_DTRACE_H
kamg@551 2939 // ---------------------------------------------------------------------------
kamg@551 2940 // Generate a dtrace nmethod for a given signature. The method takes arguments
kamg@551 2941 // in the Java compiled code convention, marshals them to the native
kamg@551 2942 // abi and then leaves nops at the position you would expect to call a native
kamg@551 2943 // function. When the probe is enabled the nops are replaced with a trap
kamg@551 2944 // instruction that dtrace inserts and the trace will cause a notification
kamg@551 2945 // to dtrace.
kamg@551 2946 //
kamg@551 2947 // The probes are only able to take primitive types and java/lang/String as
kamg@551 2948 // arguments. No other java types are allowed. Strings are converted to utf8
kamg@551 2949 // strings so that from dtrace point of view java strings are converted to C
kamg@551 2950 // strings. There is an arbitrary fixed limit on the total space that a method
kamg@551 2951 // can use for converting the strings. (256 chars per string in the signature).
kamg@551 2952 // So any java string larger then this is truncated.
kamg@551 2953
kamg@551 2954 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
kamg@551 2955 static bool offsets_initialized = false;
kamg@551 2956
kamg@551 2957 nmethod *SharedRuntime::generate_dtrace_nmethod(
kamg@551 2958 MacroAssembler *masm, methodHandle method) {
kamg@551 2959
kamg@551 2960
kamg@551 2961 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
kamg@551 2962 // be single threaded in this method.
kamg@551 2963 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
kamg@551 2964
kamg@551 2965 // Fill in the signature array, for the calling-convention call.
kamg@551 2966 int total_args_passed = method->size_of_parameters();
kamg@551 2967
kamg@551 2968 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
kamg@551 2969 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
kamg@551 2970
kamg@551 2971 // The signature we are going to use for the trap that dtrace will see
kamg@551 2972 // java/lang/String is converted. We drop "this" and any other object
kamg@551 2973 // is converted to NULL. (A one-slot java/lang/Long object reference
kamg@551 2974 // is converted to a two-slot long, which is why we double the allocation).
kamg@551 2975 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
kamg@551 2976 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
kamg@551 2977
kamg@551 2978 int i=0;
kamg@551 2979 int total_strings = 0;
kamg@551 2980 int first_arg_to_pass = 0;
kamg@551 2981 int total_c_args = 0;
kamg@551 2982
kamg@551 2983 // Skip the receiver as dtrace doesn't want to see it
kamg@551 2984 if( !method->is_static() ) {
kamg@551 2985 in_sig_bt[i++] = T_OBJECT;
kamg@551 2986 first_arg_to_pass = 1;
kamg@551 2987 }
kamg@551 2988
kamg@551 2989 SignatureStream ss(method->signature());
kamg@551 2990 for ( ; !ss.at_return_type(); ss.next()) {
kamg@551 2991 BasicType bt = ss.type();
kamg@551 2992 in_sig_bt[i++] = bt; // Collect remaining bits of signature
kamg@551 2993 out_sig_bt[total_c_args++] = bt;
kamg@551 2994 if( bt == T_OBJECT) {
coleenp@2497 2995 Symbol* s = ss.as_symbol_or_null();
kamg@551 2996 if (s == vmSymbols::java_lang_String()) {
kamg@551 2997 total_strings++;
kamg@551 2998 out_sig_bt[total_c_args-1] = T_ADDRESS;
kamg@551 2999 } else if (s == vmSymbols::java_lang_Boolean() ||
kamg@551 3000 s == vmSymbols::java_lang_Byte()) {
kamg@551 3001 out_sig_bt[total_c_args-1] = T_BYTE;
kamg@551 3002 } else if (s == vmSymbols::java_lang_Character() ||
kamg@551 3003 s == vmSymbols::java_lang_Short()) {
kamg@551 3004 out_sig_bt[total_c_args-1] = T_SHORT;
kamg@551 3005 } else if (s == vmSymbols::java_lang_Integer() ||
kamg@551 3006 s == vmSymbols::java_lang_Float()) {
kamg@551 3007 out_sig_bt[total_c_args-1] = T_INT;
kamg@551 3008 } else if (s == vmSymbols::java_lang_Long() ||
kamg@551 3009 s == vmSymbols::java_lang_Double()) {
kamg@551 3010 out_sig_bt[total_c_args-1] = T_LONG;
kamg@551 3011 out_sig_bt[total_c_args++] = T_VOID;
kamg@551 3012 }
kamg@551 3013 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
kamg@551 3014 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
kamg@551 3015 // We convert double to long
kamg@551 3016 out_sig_bt[total_c_args-1] = T_LONG;
kamg@551 3017 out_sig_bt[total_c_args++] = T_VOID;
kamg@551 3018 } else if ( bt == T_FLOAT) {
kamg@551 3019 // We convert float to int
kamg@551 3020 out_sig_bt[total_c_args-1] = T_INT;
kamg@551 3021 }
kamg@551 3022 }
kamg@551 3023
kamg@551 3024 assert(i==total_args_passed, "validly parsed signature");
kamg@551 3025
kamg@551 3026 // Now get the compiled-Java layout as input arguments
kamg@551 3027 int comp_args_on_stack;
kamg@551 3028 comp_args_on_stack = SharedRuntime::java_calling_convention(
kamg@551 3029 in_sig_bt, in_regs, total_args_passed, false);
kamg@551 3030
kamg@551 3031 // We have received a description of where all the java arg are located
kamg@551 3032 // on entry to the wrapper. We need to convert these args to where
kamg@551 3033 // the a native (non-jni) function would expect them. To figure out
kamg@551 3034 // where they go we convert the java signature to a C signature and remove
kamg@551 3035 // T_VOID for any long/double we might have received.
kamg@551 3036
kamg@551 3037
kamg@551 3038 // Now figure out where the args must be stored and how much stack space
kamg@551 3039 // they require (neglecting out_preserve_stack_slots but space for storing
kamg@551 3040 // the 1st six register arguments). It's weird see int_stk_helper.
kamg@551 3041 //
kamg@551 3042 int out_arg_slots;
kamg@551 3043 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
kamg@551 3044
kamg@551 3045 // Calculate the total number of stack slots we will need.
kamg@551 3046
kamg@551 3047 // First count the abi requirement plus all of the outgoing args
kamg@551 3048 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
kamg@551 3049
kamg@551 3050 // Plus a temp for possible converion of float/double/long register args
kamg@551 3051
kamg@551 3052 int conversion_temp = stack_slots;
kamg@551 3053 stack_slots += 2;
kamg@551 3054
kamg@551 3055
kamg@551 3056 // Now space for the string(s) we must convert
kamg@551 3057
kamg@551 3058 int string_locs = stack_slots;
kamg@551 3059 stack_slots += total_strings *
kamg@551 3060 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
kamg@551 3061
kamg@551 3062 // Ok The space we have allocated will look like:
kamg@551 3063 //
kamg@551 3064 //
kamg@551 3065 // FP-> | |
kamg@551 3066 // |---------------------|
kamg@551 3067 // | string[n] |
kamg@551 3068 // |---------------------| <- string_locs[n]
kamg@551 3069 // | string[n-1] |
kamg@551 3070 // |---------------------| <- string_locs[n-1]
kamg@551 3071 // | ... |
kamg@551 3072 // | ... |
kamg@551 3073 // |---------------------| <- string_locs[1]
kamg@551 3074 // | string[0] |
kamg@551 3075 // |---------------------| <- string_locs[0]
kamg@551 3076 // | temp |
kamg@551 3077 // |---------------------| <- conversion_temp
kamg@551 3078 // | outbound memory |
kamg@551 3079 // | based arguments |
kamg@551 3080 // | |
kamg@551 3081 // |---------------------|
kamg@551 3082 // | |
kamg@551 3083 // SP-> | out_preserved_slots |
kamg@551 3084 //
kamg@551 3085 //
kamg@551 3086
kamg@551 3087 // Now compute actual number of stack words we need rounding to make
kamg@551 3088 // stack properly aligned.
kamg@551 3089 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
kamg@551 3090
kamg@551 3091 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
kamg@551 3092
kamg@551 3093 intptr_t start = (intptr_t)__ pc();
kamg@551 3094
kamg@551 3095 // First thing make an ic check to see if we should even be here
kamg@551 3096
kamg@551 3097 {
kamg@551 3098 Label L;
kamg@551 3099 const Register temp_reg = G3_scratch;
twisti@1162 3100 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
kamg@551 3101 __ verify_oop(O0);
kamg@551 3102 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
kvn@3037 3103 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L);
kamg@551 3104
twisti@1162 3105 __ jump_to(ic_miss, temp_reg);
kamg@551 3106 __ delayed()->nop();
kamg@551 3107 __ align(CodeEntryAlignment);
kamg@551 3108 __ bind(L);
kamg@551 3109 }
kamg@551 3110
kamg@551 3111 int vep_offset = ((intptr_t)__ pc()) - start;
kamg@551 3112
kamg@551 3113
kamg@551 3114 // The instruction at the verified entry point must be 5 bytes or longer
kamg@551 3115 // because it can be patched on the fly by make_non_entrant. The stack bang
kamg@551 3116 // instruction fits that requirement.
kamg@551 3117
kamg@551 3118 // Generate stack overflow check before creating frame
kamg@551 3119 __ generate_stack_overflow_check(stack_size);
kamg@551 3120
kamg@551 3121 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
kamg@551 3122 "valid size for make_non_entrant");
kamg@551 3123
kamg@551 3124 // Generate a new frame for the wrapper.
kamg@551 3125 __ save(SP, -stack_size, SP);
kamg@551 3126
kamg@551 3127 // Frame is now completed as far a size and linkage.
kamg@551 3128
kamg@551 3129 int frame_complete = ((intptr_t)__ pc()) - start;
kamg@551 3130
kamg@551 3131 #ifdef ASSERT
kamg@551 3132 bool reg_destroyed[RegisterImpl::number_of_registers];
kamg@551 3133 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
kamg@551 3134 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
kamg@551 3135 reg_destroyed[r] = false;
kamg@551 3136 }
kamg@551 3137 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
kamg@551 3138 freg_destroyed[f] = false;
kamg@551 3139 }
kamg@551 3140
kamg@551 3141 #endif /* ASSERT */
kamg@551 3142
kamg@551 3143 VMRegPair zero;
kamg@611 3144 const Register g0 = G0; // without this we get a compiler warning (why??)
kamg@611 3145 zero.set2(g0->as_VMReg());
kamg@551 3146
kamg@551 3147 int c_arg, j_arg;
kamg@551 3148
kamg@551 3149 Register conversion_off = noreg;
kamg@551 3150
kamg@551 3151 for (j_arg = first_arg_to_pass, c_arg = 0 ;
kamg@551 3152 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
kamg@551 3153
kamg@551 3154 VMRegPair src = in_regs[j_arg];
kamg@551 3155 VMRegPair dst = out_regs[c_arg];
kamg@551 3156
kamg@551 3157 #ifdef ASSERT
kamg@551 3158 if (src.first()->is_Register()) {
kamg@551 3159 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
kamg@551 3160 } else if (src.first()->is_FloatRegister()) {
kamg@551 3161 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
kamg@551 3162 FloatRegisterImpl::S)], "ack!");
kamg@551 3163 }
kamg@551 3164 if (dst.first()->is_Register()) {
kamg@551 3165 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
kamg@551 3166 } else if (dst.first()->is_FloatRegister()) {
kamg@551 3167 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
kamg@551 3168 FloatRegisterImpl::S)] = true;
kamg@551 3169 }
kamg@551 3170 #endif /* ASSERT */
kamg@551 3171
kamg@551 3172 switch (in_sig_bt[j_arg]) {
kamg@551 3173 case T_ARRAY:
kamg@551 3174 case T_OBJECT:
kamg@551 3175 {
kamg@551 3176 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
kamg@551 3177 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
kamg@551 3178 // need to unbox a one-slot value
kamg@551 3179 Register in_reg = L0;
kamg@551 3180 Register tmp = L2;
kamg@551 3181 if ( src.first()->is_reg() ) {
kamg@551 3182 in_reg = src.first()->as_Register();
kamg@551 3183 } else {
kamg@551 3184 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
kamg@551 3185 "must be");
kamg@551 3186 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
kamg@551 3187 }
kamg@551 3188 // If the final destination is an acceptable register
kamg@551 3189 if ( dst.first()->is_reg() ) {
kamg@551 3190 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
kamg@551 3191 tmp = dst.first()->as_Register();
kamg@551 3192 }
kamg@551 3193 }
kamg@551 3194
kamg@551 3195 Label skipUnbox;
kamg@551 3196 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
kamg@551 3197 __ mov(G0, tmp->successor());
kamg@551 3198 }
kamg@551 3199 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
kamg@551 3200 __ delayed()->mov(G0, tmp);
kamg@551 3201
kvn@600 3202 BasicType bt = out_sig_bt[c_arg];
kvn@600 3203 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
kvn@600 3204 switch (bt) {
kamg@551 3205 case T_BYTE:
kamg@551 3206 __ ldub(in_reg, box_offset, tmp); break;
kamg@551 3207 case T_SHORT:
kamg@551 3208 __ lduh(in_reg, box_offset, tmp); break;
kamg@551 3209 case T_INT:
kamg@551 3210 __ ld(in_reg, box_offset, tmp); break;
kamg@551 3211 case T_LONG:
kamg@551 3212 __ ld_long(in_reg, box_offset, tmp); break;
kamg@551 3213 default: ShouldNotReachHere();
kamg@551 3214 }
kamg@551 3215
kamg@551 3216 __ bind(skipUnbox);
kamg@551 3217 // If tmp wasn't final destination copy to final destination
kamg@551 3218 if (tmp == L2) {
kamg@551 3219 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
kamg@551 3220 if (out_sig_bt[c_arg] == T_LONG) {
kamg@551 3221 long_move(masm, tmp_as_VM, dst);
kamg@551 3222 } else {
kamg@551 3223 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
kamg@551 3224 }
kamg@551 3225 }
kamg@551 3226 if (out_sig_bt[c_arg] == T_LONG) {
kamg@551 3227 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
kamg@551 3228 ++c_arg; // move over the T_VOID to keep the loop indices in sync
kamg@551 3229 }
kamg@551 3230 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@551 3231 Register s =
kamg@551 3232 src.first()->is_reg() ? src.first()->as_Register() : L2;
kamg@551 3233 Register d =
kamg@551 3234 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@551 3235
kamg@551 3236 // We store the oop now so that the conversion pass can reach
kamg@551 3237 // while in the inner frame. This will be the only store if
kamg@551 3238 // the oop is NULL.
kamg@551 3239 if (s != L2) {
kamg@551 3240 // src is register
kamg@551 3241 if (d != L2) {
kamg@551 3242 // dst is register
kamg@551 3243 __ mov(s, d);
kamg@551 3244 } else {
kamg@551 3245 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@551 3246 STACK_BIAS), "must be");
kamg@551 3247 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@551 3248 }
kamg@551 3249 } else {
kamg@551 3250 // src not a register
kamg@551 3251 assert(Assembler::is_simm13(reg2offset(src.first()) +
kamg@551 3252 STACK_BIAS), "must be");
kamg@551 3253 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
kamg@551 3254 if (d == L2) {
kamg@551 3255 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@551 3256 STACK_BIAS), "must be");
kamg@551 3257 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@551 3258 }
kamg@551 3259 }
kamg@551 3260 } else if (out_sig_bt[c_arg] != T_VOID) {
kamg@551 3261 // Convert the arg to NULL
kamg@551 3262 if (dst.first()->is_reg()) {
kamg@551 3263 __ mov(G0, dst.first()->as_Register());
kamg@551 3264 } else {
kamg@551 3265 assert(Assembler::is_simm13(reg2offset(dst.first()) +
kamg@551 3266 STACK_BIAS), "must be");
kamg@551 3267 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
kamg@551 3268 }
kamg@551 3269 }
kamg@551 3270 }
kamg@551 3271 break;
kamg@551 3272 case T_VOID:
kamg@551 3273 break;
kamg@551 3274
kamg@551 3275 case T_FLOAT:
kamg@551 3276 if (src.first()->is_stack()) {
kamg@551 3277 // Stack to stack/reg is simple
kamg@551 3278 move32_64(masm, src, dst);
kamg@551 3279 } else {
kamg@551 3280 if (dst.first()->is_reg()) {
kamg@551 3281 // freg -> reg
kamg@551 3282 int off =
kamg@551 3283 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@551 3284 Register d = dst.first()->as_Register();
kamg@551 3285 if (Assembler::is_simm13(off)) {
kamg@551 3286 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@551 3287 SP, off);
kamg@551 3288 __ ld(SP, off, d);
kamg@551 3289 } else {
kamg@551 3290 if (conversion_off == noreg) {
kamg@551 3291 __ set(off, L6);
kamg@551 3292 conversion_off = L6;
kamg@551 3293 }
kamg@551 3294 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@551 3295 SP, conversion_off);
kamg@551 3296 __ ld(SP, conversion_off , d);
kamg@551 3297 }
kamg@551 3298 } else {
kamg@551 3299 // freg -> mem
kamg@551 3300 int off = STACK_BIAS + reg2offset(dst.first());
kamg@551 3301 if (Assembler::is_simm13(off)) {
kamg@551 3302 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@551 3303 SP, off);
kamg@551 3304 } else {
kamg@551 3305 if (conversion_off == noreg) {
kamg@551 3306 __ set(off, L6);
kamg@551 3307 conversion_off = L6;
kamg@551 3308 }
kamg@551 3309 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
kamg@551 3310 SP, conversion_off);
kamg@551 3311 }
kamg@551 3312 }
kamg@551 3313 }
kamg@551 3314 break;
kamg@551 3315
kamg@551 3316 case T_DOUBLE:
kamg@551 3317 assert( j_arg + 1 < total_args_passed &&
kamg@551 3318 in_sig_bt[j_arg + 1] == T_VOID &&
kamg@551 3319 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
kamg@551 3320 if (src.first()->is_stack()) {
kamg@551 3321 // Stack to stack/reg is simple
kamg@551 3322 long_move(masm, src, dst);
kamg@551 3323 } else {
kamg@551 3324 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
kamg@551 3325
kamg@551 3326 // Destination could be an odd reg on 32bit in which case
kamg@551 3327 // we can't load direct to the destination.
kamg@551 3328
kamg@551 3329 if (!d->is_even() && wordSize == 4) {
kamg@551 3330 d = L2;
kamg@551 3331 }
kamg@551 3332 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@551 3333 if (Assembler::is_simm13(off)) {
kamg@551 3334 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@551 3335 SP, off);
kamg@551 3336 __ ld_long(SP, off, d);
kamg@551 3337 } else {
kamg@551 3338 if (conversion_off == noreg) {
kamg@551 3339 __ set(off, L6);
kamg@551 3340 conversion_off = L6;
kamg@551 3341 }
kamg@551 3342 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
kamg@551 3343 SP, conversion_off);
kamg@551 3344 __ ld_long(SP, conversion_off, d);
kamg@551 3345 }
kamg@551 3346 if (d == L2) {
kamg@551 3347 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@551 3348 }
kamg@551 3349 }
kamg@551 3350 break;
kamg@551 3351
kamg@551 3352 case T_LONG :
kamg@551 3353 // 32bit can't do a split move of something like g1 -> O0, O1
kamg@551 3354 // so use a memory temp
kamg@551 3355 if (src.is_single_phys_reg() && wordSize == 4) {
kamg@551 3356 Register tmp = L2;
kamg@551 3357 if (dst.first()->is_reg() &&
kamg@551 3358 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
kamg@551 3359 tmp = dst.first()->as_Register();
kamg@551 3360 }
kamg@551 3361
kamg@551 3362 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
kamg@551 3363 if (Assembler::is_simm13(off)) {
kamg@551 3364 __ stx(src.first()->as_Register(), SP, off);
kamg@551 3365 __ ld_long(SP, off, tmp);
kamg@551 3366 } else {
kamg@551 3367 if (conversion_off == noreg) {
kamg@551 3368 __ set(off, L6);
kamg@551 3369 conversion_off = L6;
kamg@551 3370 }
kamg@551 3371 __ stx(src.first()->as_Register(), SP, conversion_off);
kamg@551 3372 __ ld_long(SP, conversion_off, tmp);
kamg@551 3373 }
kamg@551 3374
kamg@551 3375 if (tmp == L2) {
kamg@551 3376 long_move(masm, reg64_to_VMRegPair(L2), dst);
kamg@551 3377 }
kamg@551 3378 } else {
kamg@551 3379 long_move(masm, src, dst);
kamg@551 3380 }
kamg@551 3381 break;
kamg@551 3382
kamg@551 3383 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
kamg@551 3384
kamg@551 3385 default:
kamg@551 3386 move32_64(masm, src, dst);
kamg@551 3387 }
kamg@551 3388 }
kamg@551 3389
kamg@551 3390
kamg@551 3391 // If we have any strings we must store any register based arg to the stack
kamg@551 3392 // This includes any still live xmm registers too.
kamg@551 3393
kamg@551 3394 if (total_strings > 0 ) {
kamg@551 3395
kamg@551 3396 // protect all the arg registers
kamg@551 3397 __ save_frame(0);
kamg@551 3398 __ mov(G2_thread, L7_thread_cache);
kamg@551 3399 const Register L2_string_off = L2;
kamg@551 3400
kamg@551 3401 // Get first string offset
kamg@551 3402 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
kamg@551 3403
kamg@551 3404 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
kamg@551 3405 if (out_sig_bt[c_arg] == T_ADDRESS) {
kamg@551 3406
kamg@551 3407 VMRegPair dst = out_regs[c_arg];
kamg@551 3408 const Register d = dst.first()->is_reg() ?
kamg@551 3409 dst.first()->as_Register()->after_save() : noreg;
kamg@551 3410
kamg@551 3411 // It's a string the oop and it was already copied to the out arg
kamg@551 3412 // position
kamg@551 3413 if (d != noreg) {
kamg@551 3414 __ mov(d, O0);
kamg@551 3415 } else {
kamg@551 3416 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@551 3417 "must be");
kamg@551 3418 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
kamg@551 3419 }
kamg@551 3420 Label skip;
kamg@551 3421
kamg@551 3422 __ br_null(O0, false, Assembler::pn, skip);
kamg@551 3423 __ delayed()->add(FP, L2_string_off, O1);
kamg@551 3424
kamg@551 3425 if (d != noreg) {
kamg@551 3426 __ mov(O1, d);
kamg@551 3427 } else {
kamg@551 3428 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
kamg@551 3429 "must be");
kamg@551 3430 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
kamg@551 3431 }
kamg@551 3432
kamg@551 3433 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
kamg@551 3434 relocInfo::runtime_call_type);
kamg@551 3435 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
kamg@551 3436
kamg@551 3437 __ bind(skip);
kamg@551 3438
kamg@551 3439 }
kamg@551 3440
kamg@551 3441 }
kamg@551 3442 __ mov(L7_thread_cache, G2_thread);
kamg@551 3443 __ restore();
kamg@551 3444
kamg@551 3445 }
kamg@551 3446
kamg@551 3447
kamg@551 3448 // Ok now we are done. Need to place the nop that dtrace wants in order to
kamg@551 3449 // patch in the trap
kamg@551 3450
kamg@551 3451 int patch_offset = ((intptr_t)__ pc()) - start;
kamg@551 3452
kamg@551 3453 __ nop();
kamg@551 3454
kamg@551 3455
kamg@551 3456 // Return
kamg@551 3457
kamg@551 3458 __ ret();
kamg@551 3459 __ delayed()->restore();
kamg@551 3460
kamg@551 3461 __ flush();
kamg@551 3462
kamg@551 3463 nmethod *nm = nmethod::new_dtrace_nmethod(
kamg@551 3464 method, masm->code(), vep_offset, patch_offset, frame_complete,
kamg@551 3465 stack_slots / VMRegImpl::slots_per_word);
kamg@551 3466 return nm;
kamg@551 3467
kamg@551 3468 }
kamg@551 3469
kamg@551 3470 #endif // HAVE_DTRACE_H
kamg@551 3471
duke@435 3472 // this function returns the adjust size (in number of words) to a c2i adapter
duke@435 3473 // activation for use during deoptimization
duke@435 3474 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
duke@435 3475 assert(callee_locals >= callee_parameters,
duke@435 3476 "test and remove; got more parms than locals");
duke@435 3477 if (callee_locals < callee_parameters)
duke@435 3478 return 0; // No adjustment for negative locals
twisti@1861 3479 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
duke@435 3480 return round_to(diff, WordsPerLong);
duke@435 3481 }
duke@435 3482
duke@435 3483 // "Top of Stack" slots that may be unused by the calling convention but must
duke@435 3484 // otherwise be preserved.
duke@435 3485 // On Intel these are not necessary and the value can be zero.
duke@435 3486 // On Sparc this describes the words reserved for storing a register window
duke@435 3487 // when an interrupt occurs.
duke@435 3488 uint SharedRuntime::out_preserve_stack_slots() {
duke@435 3489 return frame::register_save_words * VMRegImpl::slots_per_word;
duke@435 3490 }
duke@435 3491
duke@435 3492 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
duke@435 3493 //
duke@435 3494 // Common out the new frame generation for deopt and uncommon trap
duke@435 3495 //
duke@435 3496 Register G3pcs = G3_scratch; // Array of new pcs (input)
duke@435 3497 Register Oreturn0 = O0;
duke@435 3498 Register Oreturn1 = O1;
duke@435 3499 Register O2UnrollBlock = O2;
duke@435 3500 Register O3array = O3; // Array of frame sizes (input)
duke@435 3501 Register O4array_size = O4; // number of frames (input)
duke@435 3502 Register O7frame_size = O7; // number of frames (input)
duke@435 3503
duke@435 3504 __ ld_ptr(O3array, 0, O7frame_size);
duke@435 3505 __ sub(G0, O7frame_size, O7frame_size);
duke@435 3506 __ save(SP, O7frame_size, SP);
duke@435 3507 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
duke@435 3508
duke@435 3509 #ifdef ASSERT
duke@435 3510 // make sure that the frames are aligned properly
duke@435 3511 #ifndef _LP64
duke@435 3512 __ btst(wordSize*2-1, SP);
coleenp@3627 3513 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc);
duke@435 3514 #endif
duke@435 3515 #endif
duke@435 3516
duke@435 3517 // Deopt needs to pass some extra live values from frame to frame
duke@435 3518
duke@435 3519 if (deopt) {
duke@435 3520 __ mov(Oreturn0->after_save(), Oreturn0);
duke@435 3521 __ mov(Oreturn1->after_save(), Oreturn1);
duke@435 3522 }
duke@435 3523
duke@435 3524 __ mov(O4array_size->after_save(), O4array_size);
duke@435 3525 __ sub(O4array_size, 1, O4array_size);
duke@435 3526 __ mov(O3array->after_save(), O3array);
duke@435 3527 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
duke@435 3528 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
duke@435 3529
duke@435 3530 #ifdef ASSERT
duke@435 3531 // trash registers to show a clear pattern in backtraces
duke@435 3532 __ set(0xDEAD0000, I0);
duke@435 3533 __ add(I0, 2, I1);
duke@435 3534 __ add(I0, 4, I2);
duke@435 3535 __ add(I0, 6, I3);
duke@435 3536 __ add(I0, 8, I4);
duke@435 3537 // Don't touch I5 could have valuable savedSP
duke@435 3538 __ set(0xDEADBEEF, L0);
duke@435 3539 __ mov(L0, L1);
duke@435 3540 __ mov(L0, L2);
duke@435 3541 __ mov(L0, L3);
duke@435 3542 __ mov(L0, L4);
duke@435 3543 __ mov(L0, L5);
duke@435 3544
duke@435 3545 // trash the return value as there is nothing to return yet
duke@435 3546 __ set(0xDEAD0001, O7);
duke@435 3547 #endif
duke@435 3548
duke@435 3549 __ mov(SP, O5_savedSP);
duke@435 3550 }
duke@435 3551
duke@435 3552
duke@435 3553 static void make_new_frames(MacroAssembler* masm, bool deopt) {
duke@435 3554 //
duke@435 3555 // loop through the UnrollBlock info and create new frames
duke@435 3556 //
duke@435 3557 Register G3pcs = G3_scratch;
duke@435 3558 Register Oreturn0 = O0;
duke@435 3559 Register Oreturn1 = O1;
duke@435 3560 Register O2UnrollBlock = O2;
duke@435 3561 Register O3array = O3;
duke@435 3562 Register O4array_size = O4;
duke@435 3563 Label loop;
duke@435 3564
duke@435 3565 // Before we make new frames, check to see if stack is available.
duke@435 3566 // Do this after the caller's return address is on top of stack
duke@435 3567 if (UseStackBanging) {
duke@435 3568 // Get total frame size for interpreted frames
twisti@1162 3569 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
duke@435 3570 __ bang_stack_size(O4, O3, G3_scratch);
duke@435 3571 }
duke@435 3572
twisti@1162 3573 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
twisti@1162 3574 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
twisti@1162 3575 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
duke@435 3576
duke@435 3577 // Adjust old interpreter frame to make space for new frame's extra java locals
duke@435 3578 //
duke@435 3579 // We capture the original sp for the transition frame only because it is needed in
duke@435 3580 // order to properly calculate interpreter_sp_adjustment. Even though in real life
duke@435 3581 // every interpreter frame captures a savedSP it is only needed at the transition
duke@435 3582 // (fortunately). If we had to have it correct everywhere then we would need to
duke@435 3583 // be told the sp_adjustment for each frame we create. If the frame size array
duke@435 3584 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
duke@435 3585 // for each frame we create and keep up the illusion every where.
duke@435 3586 //
duke@435 3587
twisti@1162 3588 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
duke@435 3589 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
duke@435 3590 __ sub(SP, O7, SP);
duke@435 3591
duke@435 3592 #ifdef ASSERT
duke@435 3593 // make sure that there is at least one entry in the array
duke@435 3594 __ tst(O4array_size);
coleenp@3627 3595 __ breakpoint_trap(Assembler::zero, Assembler::icc);
duke@435 3596 #endif
duke@435 3597
duke@435 3598 // Now push the new interpreter frames
duke@435 3599 __ bind(loop);
duke@435 3600
duke@435 3601 // allocate a new frame, filling the registers
duke@435 3602
duke@435 3603 gen_new_frame(masm, deopt); // allocate an interpreter frame
duke@435 3604
kvn@3037 3605 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop);
duke@435 3606 __ delayed()->add(O3array, wordSize, O3array);
duke@435 3607 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
duke@435 3608
duke@435 3609 }
duke@435 3610
duke@435 3611 //------------------------------generate_deopt_blob----------------------------
duke@435 3612 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@435 3613 // instead.
duke@435 3614 void SharedRuntime::generate_deopt_blob() {
duke@435 3615 // allocate space for the code
duke@435 3616 ResourceMark rm;
duke@435 3617 // setup code generation tools
duke@435 3618 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
kvn@3582 3619 if (UseStackBanging) {
kvn@3582 3620 pad += StackShadowPages*16 + 32;
kvn@3582 3621 }
duke@435 3622 #ifdef _LP64
duke@435 3623 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
duke@435 3624 #else
duke@435 3625 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
duke@435 3626 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
duke@435 3627 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
duke@435 3628 #endif /* _LP64 */
duke@435 3629 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@435 3630 FloatRegister Freturn0 = F0;
duke@435 3631 Register Greturn1 = G1;
duke@435 3632 Register Oreturn0 = O0;
duke@435 3633 Register Oreturn1 = O1;
duke@435 3634 Register O2UnrollBlock = O2;
never@1472 3635 Register L0deopt_mode = L0;
never@1472 3636 Register G4deopt_mode = G4_scratch;
duke@435 3637 int frame_size_words;
twisti@1162 3638 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
duke@435 3639 #if !defined(_LP64) && defined(COMPILER2)
twisti@1162 3640 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
duke@435 3641 #endif
duke@435 3642 Label cont;
duke@435 3643
duke@435 3644 OopMapSet *oop_maps = new OopMapSet();
duke@435 3645
duke@435 3646 //
duke@435 3647 // This is the entry point for code which is returning to a de-optimized
duke@435 3648 // frame.
duke@435 3649 // The steps taken by this frame are as follows:
duke@435 3650 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
duke@435 3651 // and all potentially live registers (at a pollpoint many registers can be live).
duke@435 3652 //
duke@435 3653 // - call the C routine: Deoptimization::fetch_unroll_info (this function
duke@435 3654 // returns information about the number and size of interpreter frames
duke@435 3655 // which are equivalent to the frame which is being deoptimized)
duke@435 3656 // - deallocate the unpack frame, restoring only results values. Other
duke@435 3657 // volatile registers will now be captured in the vframeArray as needed.
duke@435 3658 // - deallocate the deoptimization frame
duke@435 3659 // - in a loop using the information returned in the previous step
duke@435 3660 // push new interpreter frames (take care to propagate the return
duke@435 3661 // values through each new frame pushed)
duke@435 3662 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
duke@435 3663 // - call the C routine: Deoptimization::unpack_frames (this function
duke@435 3664 // lays out values on the interpreter frame which was just created)
duke@435 3665 // - deallocate the dummy unpack_frame
duke@435 3666 // - ensure that all the return values are correctly set and then do
duke@435 3667 // a return to the interpreter entry point
duke@435 3668 //
duke@435 3669 // Refer to the following methods for more information:
duke@435 3670 // - Deoptimization::fetch_unroll_info
duke@435 3671 // - Deoptimization::unpack_frames
duke@435 3672
duke@435 3673 OopMap* map = NULL;
duke@435 3674
duke@435 3675 int start = __ offset();
duke@435 3676
duke@435 3677 // restore G2, the trampoline destroyed it
duke@435 3678 __ get_thread();
duke@435 3679
duke@435 3680 // On entry we have been called by the deoptimized nmethod with a call that
duke@435 3681 // replaced the original call (or safepoint polling location) so the deoptimizing
duke@435 3682 // pc is now in O7. Return values are still in the expected places
duke@435 3683
duke@435 3684 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
kvn@3037 3685 __ ba(cont);
never@1472 3686 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode);
duke@435 3687
duke@435 3688 int exception_offset = __ offset() - start;
duke@435 3689
duke@435 3690 // restore G2, the trampoline destroyed it
duke@435 3691 __ get_thread();
duke@435 3692
duke@435 3693 // On entry we have been jumped to by the exception handler (or exception_blob
duke@435 3694 // for server). O0 contains the exception oop and O7 contains the original
duke@435 3695 // exception pc. So if we push a frame here it will look to the
duke@435 3696 // stack walking code (fetch_unroll_info) just like a normal call so
duke@435 3697 // state will be extracted normally.
duke@435 3698
duke@435 3699 // save exception oop in JavaThread and fall through into the
duke@435 3700 // exception_in_tls case since they are handled in same way except
duke@435 3701 // for where the pending exception is kept.
twisti@1162 3702 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
duke@435 3703
duke@435 3704 //
duke@435 3705 // Vanilla deoptimization with an exception pending in exception_oop
duke@435 3706 //
duke@435 3707 int exception_in_tls_offset = __ offset() - start;
duke@435 3708
duke@435 3709 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@435 3710 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@435 3711
duke@435 3712 // Restore G2_thread
duke@435 3713 __ get_thread();
duke@435 3714
duke@435 3715 #ifdef ASSERT
duke@435 3716 {
duke@435 3717 // verify that there is really an exception oop in exception_oop
duke@435 3718 Label has_exception;
twisti@1162 3719 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
kvn@3037 3720 __ br_notnull_short(Oexception, Assembler::pt, has_exception);
duke@435 3721 __ stop("no exception in thread");
duke@435 3722 __ bind(has_exception);
duke@435 3723
duke@435 3724 // verify that there is no pending exception
duke@435 3725 Label no_pending_exception;
twisti@1162 3726 Address exception_addr(G2_thread, Thread::pending_exception_offset());
duke@435 3727 __ ld_ptr(exception_addr, Oexception);
kvn@3037 3728 __ br_null_short(Oexception, Assembler::pt, no_pending_exception);
duke@435 3729 __ stop("must not have pending exception here");
duke@435 3730 __ bind(no_pending_exception);
duke@435 3731 }
duke@435 3732 #endif
duke@435 3733
kvn@3037 3734 __ ba(cont);
never@1472 3735 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);;
duke@435 3736
duke@435 3737 //
duke@435 3738 // Reexecute entry, similar to c2 uncommon trap
duke@435 3739 //
duke@435 3740 int reexecute_offset = __ offset() - start;
duke@435 3741
duke@435 3742 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
duke@435 3743 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@435 3744
never@1472 3745 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode);
duke@435 3746
duke@435 3747 __ bind(cont);
duke@435 3748
duke@435 3749 __ set_last_Java_frame(SP, noreg);
duke@435 3750
duke@435 3751 // do the call by hand so we can get the oopmap
duke@435 3752
duke@435 3753 __ mov(G2_thread, L7_thread_cache);
duke@435 3754 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
duke@435 3755 __ delayed()->mov(G2_thread, O0);
duke@435 3756
duke@435 3757 // Set an oopmap for the call site this describes all our saved volatile registers
duke@435 3758
duke@435 3759 oop_maps->add_gc_map( __ offset()-start, map);
duke@435 3760
duke@435 3761 __ mov(L7_thread_cache, G2_thread);
duke@435 3762
duke@435 3763 __ reset_last_Java_frame();
duke@435 3764
duke@435 3765 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
duke@435 3766 // so this move will survive
duke@435 3767
never@1472 3768 __ mov(L0deopt_mode, G4deopt_mode);
duke@435 3769
duke@435 3770 __ mov(O0, O2UnrollBlock->after_save());
duke@435 3771
duke@435 3772 RegisterSaver::restore_result_registers(masm);
duke@435 3773
duke@435 3774 Label noException;
kvn@3037 3775 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException);
duke@435 3776
duke@435 3777 // Move the pending exception from exception_oop to Oexception so
duke@435 3778 // the pending exception will be picked up the interpreter.
duke@435 3779 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
duke@435 3780 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
duke@435 3781 __ bind(noException);
duke@435 3782
duke@435 3783 // deallocate the deoptimization frame taking care to preserve the return values
duke@435 3784 __ mov(Oreturn0, Oreturn0->after_save());
duke@435 3785 __ mov(Oreturn1, Oreturn1->after_save());
duke@435 3786 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@435 3787 __ restore();
duke@435 3788
duke@435 3789 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@435 3790
duke@435 3791 make_new_frames(masm, true);
duke@435 3792
duke@435 3793 // push a dummy "unpack_frame" taking care of float return values and
duke@435 3794 // call Deoptimization::unpack_frames to have the unpacker layout
duke@435 3795 // information in the interpreter frames just created and then return
duke@435 3796 // to the interpreter entry point
duke@435 3797 __ save(SP, -frame_size_words*wordSize, SP);
duke@435 3798 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
duke@435 3799 #if !defined(_LP64)
duke@435 3800 #if defined(COMPILER2)
iveresov@2138 3801 // 32-bit 1-register longs return longs in G1
iveresov@2138 3802 __ stx(Greturn1, saved_Greturn1_addr);
duke@435 3803 #endif
duke@435 3804 __ set_last_Java_frame(SP, noreg);
never@1472 3805 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode);
duke@435 3806 #else
duke@435 3807 // LP64 uses g4 in set_last_Java_frame
never@1472 3808 __ mov(G4deopt_mode, O1);
duke@435 3809 __ set_last_Java_frame(SP, G0);
duke@435 3810 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
duke@435 3811 #endif
duke@435 3812 __ reset_last_Java_frame();
duke@435 3813 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
duke@435 3814
duke@435 3815 #if !defined(_LP64) && defined(COMPILER2)
duke@435 3816 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
iveresov@2138 3817 // I0/I1 if the return value is long.
iveresov@2138 3818 Label not_long;
kvn@3037 3819 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long);
iveresov@2138 3820 __ ldd(saved_Greturn1_addr,I0);
iveresov@2138 3821 __ bind(not_long);
duke@435 3822 #endif
duke@435 3823 __ ret();
duke@435 3824 __ delayed()->restore();
duke@435 3825
duke@435 3826 masm->flush();
duke@435 3827 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
duke@435 3828 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
duke@435 3829 }
duke@435 3830
duke@435 3831 #ifdef COMPILER2
duke@435 3832
duke@435 3833 //------------------------------generate_uncommon_trap_blob--------------------
duke@435 3834 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
duke@435 3835 // instead.
duke@435 3836 void SharedRuntime::generate_uncommon_trap_blob() {
duke@435 3837 // allocate space for the code
duke@435 3838 ResourceMark rm;
duke@435 3839 // setup code generation tools
duke@435 3840 int pad = VerifyThread ? 512 : 0;
kvn@3582 3841 if (UseStackBanging) {
kvn@3582 3842 pad += StackShadowPages*16 + 32;
kvn@3582 3843 }
duke@435 3844 #ifdef _LP64
duke@435 3845 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
duke@435 3846 #else
duke@435 3847 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
duke@435 3848 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
duke@435 3849 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
duke@435 3850 #endif
duke@435 3851 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@435 3852 Register O2UnrollBlock = O2;
duke@435 3853 Register O2klass_index = O2;
duke@435 3854
duke@435 3855 //
duke@435 3856 // This is the entry point for all traps the compiler takes when it thinks
duke@435 3857 // it cannot handle further execution of compilation code. The frame is
duke@435 3858 // deoptimized in these cases and converted into interpreter frames for
duke@435 3859 // execution
duke@435 3860 // The steps taken by this frame are as follows:
duke@435 3861 // - push a fake "unpack_frame"
duke@435 3862 // - call the C routine Deoptimization::uncommon_trap (this function
duke@435 3863 // packs the current compiled frame into vframe arrays and returns
duke@435 3864 // information about the number and size of interpreter frames which
duke@435 3865 // are equivalent to the frame which is being deoptimized)
duke@435 3866 // - deallocate the "unpack_frame"
duke@435 3867 // - deallocate the deoptimization frame
duke@435 3868 // - in a loop using the information returned in the previous step
duke@435 3869 // push interpreter frames;
duke@435 3870 // - create a dummy "unpack_frame"
duke@435 3871 // - call the C routine: Deoptimization::unpack_frames (this function
duke@435 3872 // lays out values on the interpreter frame which was just created)
duke@435 3873 // - deallocate the dummy unpack_frame
duke@435 3874 // - return to the interpreter entry point
duke@435 3875 //
duke@435 3876 // Refer to the following methods for more information:
duke@435 3877 // - Deoptimization::uncommon_trap
duke@435 3878 // - Deoptimization::unpack_frame
duke@435 3879
duke@435 3880 // the unloaded class index is in O0 (first parameter to this blob)
duke@435 3881
duke@435 3882 // push a dummy "unpack_frame"
duke@435 3883 // and call Deoptimization::uncommon_trap to pack the compiled frame into
duke@435 3884 // vframe array and return the UnrollBlock information
duke@435 3885 __ save_frame(0);
duke@435 3886 __ set_last_Java_frame(SP, noreg);
duke@435 3887 __ mov(I0, O2klass_index);
duke@435 3888 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
duke@435 3889 __ reset_last_Java_frame();
duke@435 3890 __ mov(O0, O2UnrollBlock->after_save());
duke@435 3891 __ restore();
duke@435 3892
duke@435 3893 // deallocate the deoptimized frame taking care to preserve the return values
duke@435 3894 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
duke@435 3895 __ restore();
duke@435 3896
duke@435 3897 // Allocate new interpreter frame(s) and possible c2i adapter frame
duke@435 3898
duke@435 3899 make_new_frames(masm, false);
duke@435 3900
duke@435 3901 // push a dummy "unpack_frame" taking care of float return values and
duke@435 3902 // call Deoptimization::unpack_frames to have the unpacker layout
duke@435 3903 // information in the interpreter frames just created and then return
duke@435 3904 // to the interpreter entry point
duke@435 3905 __ save_frame(0);
duke@435 3906 __ set_last_Java_frame(SP, noreg);
duke@435 3907 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
duke@435 3908 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
duke@435 3909 __ reset_last_Java_frame();
duke@435 3910 __ ret();
duke@435 3911 __ delayed()->restore();
duke@435 3912
duke@435 3913 masm->flush();
duke@435 3914 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
duke@435 3915 }
duke@435 3916
duke@435 3917 #endif // COMPILER2
duke@435 3918
duke@435 3919 //------------------------------generate_handler_blob-------------------
duke@435 3920 //
duke@435 3921 // Generate a special Compile2Runtime blob that saves all registers, and sets
duke@435 3922 // up an OopMap.
duke@435 3923 //
duke@435 3924 // This blob is jumped to (via a breakpoint and the signal handler) from a
duke@435 3925 // safepoint in compiled code. On entry to this blob, O7 contains the
duke@435 3926 // address in the original nmethod at which we should resume normal execution.
duke@435 3927 // Thus, this blob looks like a subroutine which must preserve lots of
duke@435 3928 // registers and return normally. Note that O7 is never register-allocated,
duke@435 3929 // so it is guaranteed to be free here.
duke@435 3930 //
duke@435 3931
duke@435 3932 // The hardest part of what this blob must do is to save the 64-bit %o
duke@435 3933 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
duke@435 3934 // an interrupt will chop off their heads. Making space in the caller's frame
duke@435 3935 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
duke@435 3936 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
duke@435 3937 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
duke@435 3938 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
duke@435 3939 // Tricky, tricky, tricky...
duke@435 3940
never@2950 3941 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) {
duke@435 3942 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
duke@435 3943
duke@435 3944 // allocate space for the code
duke@435 3945 ResourceMark rm;
duke@435 3946 // setup code generation tools
duke@435 3947 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
duke@435 3948 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
duke@435 3949 // even larger with TraceJumps
duke@435 3950 int pad = TraceJumps ? 512 : 0;
duke@435 3951 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
duke@435 3952 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@435 3953 int frame_size_words;
duke@435 3954 OopMapSet *oop_maps = new OopMapSet();
duke@435 3955 OopMap* map = NULL;
duke@435 3956
duke@435 3957 int start = __ offset();
duke@435 3958
duke@435 3959 // If this causes a return before the processing, then do a "restore"
duke@435 3960 if (cause_return) {
duke@435 3961 __ restore();
duke@435 3962 } else {
duke@435 3963 // Make it look like we were called via the poll
duke@435 3964 // so that frame constructor always sees a valid return address
duke@435 3965 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
duke@435 3966 __ sub(O7, frame::pc_return_offset, O7);
duke@435 3967 }
duke@435 3968
duke@435 3969 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@435 3970
duke@435 3971 // setup last_Java_sp (blows G4)
duke@435 3972 __ set_last_Java_frame(SP, noreg);
duke@435 3973
duke@435 3974 // call into the runtime to handle illegal instructions exception
duke@435 3975 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
duke@435 3976 __ mov(G2_thread, O0);
duke@435 3977 __ save_thread(L7_thread_cache);
duke@435 3978 __ call(call_ptr);
duke@435 3979 __ delayed()->nop();
duke@435 3980
duke@435 3981 // Set an oopmap for the call site.
duke@435 3982 // We need this not only for callee-saved registers, but also for volatile
duke@435 3983 // registers that the compiler might be keeping live across a safepoint.
duke@435 3984
duke@435 3985 oop_maps->add_gc_map( __ offset() - start, map);
duke@435 3986
duke@435 3987 __ restore_thread(L7_thread_cache);
duke@435 3988 // clear last_Java_sp
duke@435 3989 __ reset_last_Java_frame();
duke@435 3990
duke@435 3991 // Check for exceptions
duke@435 3992 Label pending;
duke@435 3993
duke@435 3994 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
kvn@3037 3995 __ br_notnull_short(O1, Assembler::pn, pending);
duke@435 3996
duke@435 3997 RegisterSaver::restore_live_registers(masm);
duke@435 3998
duke@435 3999 // We are back the the original state on entry and ready to go.
duke@435 4000
duke@435 4001 __ retl();
duke@435 4002 __ delayed()->nop();
duke@435 4003
duke@435 4004 // Pending exception after the safepoint
duke@435 4005
duke@435 4006 __ bind(pending);
duke@435 4007
duke@435 4008 RegisterSaver::restore_live_registers(masm);
duke@435 4009
duke@435 4010 // We are back the the original state on entry.
duke@435 4011
duke@435 4012 // Tail-call forward_exception_entry, with the issuing PC in O7,
duke@435 4013 // so it looks like the original nmethod called forward_exception_entry.
duke@435 4014 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
duke@435 4015 __ JMP(O0, 0);
duke@435 4016 __ delayed()->nop();
duke@435 4017
duke@435 4018 // -------------
duke@435 4019 // make sure all code is generated
duke@435 4020 masm->flush();
duke@435 4021
duke@435 4022 // return exception blob
duke@435 4023 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
duke@435 4024 }
duke@435 4025
duke@435 4026 //
duke@435 4027 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
duke@435 4028 //
duke@435 4029 // Generate a stub that calls into vm to find out the proper destination
duke@435 4030 // of a java call. All the argument registers are live at this point
duke@435 4031 // but since this is generic code we don't know what they are and the caller
duke@435 4032 // must do any gc of the args.
duke@435 4033 //
never@2950 4034 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
duke@435 4035 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
duke@435 4036
duke@435 4037 // allocate space for the code
duke@435 4038 ResourceMark rm;
duke@435 4039 // setup code generation tools
duke@435 4040 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
duke@435 4041 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
duke@435 4042 // even larger with TraceJumps
duke@435 4043 int pad = TraceJumps ? 512 : 0;
duke@435 4044 CodeBuffer buffer(name, 1600 + pad, 512);
duke@435 4045 MacroAssembler* masm = new MacroAssembler(&buffer);
duke@435 4046 int frame_size_words;
duke@435 4047 OopMapSet *oop_maps = new OopMapSet();
duke@435 4048 OopMap* map = NULL;
duke@435 4049
duke@435 4050 int start = __ offset();
duke@435 4051
duke@435 4052 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
duke@435 4053
duke@435 4054 int frame_complete = __ offset();
duke@435 4055
duke@435 4056 // setup last_Java_sp (blows G4)
duke@435 4057 __ set_last_Java_frame(SP, noreg);
duke@435 4058
duke@435 4059 // call into the runtime to handle illegal instructions exception
duke@435 4060 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
duke@435 4061 __ mov(G2_thread, O0);
duke@435 4062 __ save_thread(L7_thread_cache);
duke@435 4063 __ call(destination, relocInfo::runtime_call_type);
duke@435 4064 __ delayed()->nop();
duke@435 4065
duke@435 4066 // O0 contains the address we are going to jump to assuming no exception got installed
duke@435 4067
duke@435 4068 // Set an oopmap for the call site.
duke@435 4069 // We need this not only for callee-saved registers, but also for volatile
duke@435 4070 // registers that the compiler might be keeping live across a safepoint.
duke@435 4071
duke@435 4072 oop_maps->add_gc_map( __ offset() - start, map);
duke@435 4073
duke@435 4074 __ restore_thread(L7_thread_cache);
duke@435 4075 // clear last_Java_sp
duke@435 4076 __ reset_last_Java_frame();
duke@435 4077
duke@435 4078 // Check for exceptions
duke@435 4079 Label pending;
duke@435 4080
duke@435 4081 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
kvn@3037 4082 __ br_notnull_short(O1, Assembler::pn, pending);
duke@435 4083
duke@435 4084 // get the returned methodOop
duke@435 4085
duke@435 4086 __ get_vm_result(G5_method);
duke@435 4087 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
duke@435 4088
duke@435 4089 // O0 is where we want to jump, overwrite G3 which is saved and scratch
duke@435 4090
duke@435 4091 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
duke@435 4092
duke@435 4093 RegisterSaver::restore_live_registers(masm);
duke@435 4094
duke@435 4095 // We are back the the original state on entry and ready to go.
duke@435 4096
duke@435 4097 __ JMP(G3, 0);
duke@435 4098 __ delayed()->nop();
duke@435 4099
duke@435 4100 // Pending exception after the safepoint
duke@435 4101
duke@435 4102 __ bind(pending);
duke@435 4103
duke@435 4104 RegisterSaver::restore_live_registers(masm);
duke@435 4105
duke@435 4106 // We are back the the original state on entry.
duke@435 4107
duke@435 4108 // Tail-call forward_exception_entry, with the issuing PC in O7,
duke@435 4109 // so it looks like the original nmethod called forward_exception_entry.
duke@435 4110 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
duke@435 4111 __ JMP(O0, 0);
duke@435 4112 __ delayed()->nop();
duke@435 4113
duke@435 4114 // -------------
duke@435 4115 // make sure all code is generated
duke@435 4116 masm->flush();
duke@435 4117
duke@435 4118 // return the blob
duke@435 4119 // frame_size_words or bytes??
duke@435 4120 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
duke@435 4121 }

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