Fri, 10 Apr 2015 15:27:05 -0700
8076968: PICL based initialization of L2 cache line size on some SPARC systems is incorrect
Summary: Chcek both l2-dcache-line-size and l2-cache-line-size properties to determine the size of the line
Reviewed-by: kvn
1.1 --- a/src/cpu/sparc/vm/vm_version_sparc.cpp Fri Apr 10 15:24:50 2015 -0700 1.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.cpp Fri Apr 10 15:27:05 2015 -0700 1.3 @@ -37,7 +37,7 @@ 1.4 1.5 int VM_Version::_features = VM_Version::unknown_m; 1.6 const char* VM_Version::_features_str = ""; 1.7 -unsigned int VM_Version::_L2_cache_line_size = 0; 1.8 +unsigned int VM_Version::_L2_data_cache_line_size = 0; 1.9 1.10 void VM_Version::initialize() { 1.11 _features = determine_features(); 1.12 @@ -363,7 +363,7 @@ 1.13 1.14 #ifndef PRODUCT 1.15 if (PrintMiscellaneous && Verbose) { 1.16 - tty->print_cr("L2 cache line size: %u", L2_cache_line_size()); 1.17 + tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); 1.18 tty->print("Allocation"); 1.19 if (AllocatePrefetchStyle <= 0) { 1.20 tty->print_cr(": no prefetching");
2.1 --- a/src/cpu/sparc/vm/vm_version_sparc.hpp Fri Apr 10 15:24:50 2015 -0700 2.2 +++ b/src/cpu/sparc/vm/vm_version_sparc.hpp Fri Apr 10 15:27:05 2015 -0700 2.3 @@ -96,8 +96,8 @@ 2.4 static int _features; 2.5 static const char* _features_str; 2.6 2.7 - static unsigned int _L2_cache_line_size; 2.8 - static unsigned int L2_cache_line_size() { return _L2_cache_line_size; } 2.9 + static unsigned int _L2_data_cache_line_size; 2.10 + static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; } 2.11 2.12 static void print_features(); 2.13 static int determine_features(); 2.14 @@ -171,7 +171,7 @@ 2.15 static const char* cpu_features() { return _features_str; } 2.16 2.17 // default prefetch block size on sparc 2.18 - static intx prefetch_data_size() { return L2_cache_line_size(); } 2.19 + static intx prefetch_data_size() { return L2_data_cache_line_size(); } 2.20 2.21 // Prefetch 2.22 static intx prefetch_copy_interval_in_bytes() {
3.1 --- a/src/os_cpu/solaris_sparc/vm/vm_version_solaris_sparc.cpp Fri Apr 10 15:24:50 2015 -0700 3.2 +++ b/src/os_cpu/solaris_sparc/vm/vm_version_solaris_sparc.cpp Fri Apr 10 15:27:05 2015 -0700 3.3 @@ -127,7 +127,7 @@ 3.4 bool is_inconsistent() { return _state == INCONSISTENT; } 3.5 void set_inconsistent() { _state = INCONSISTENT; } 3.6 3.7 - void visit(picl_nodehdl_t nodeh, const char* name) { 3.8 + bool visit(picl_nodehdl_t nodeh, const char* name) { 3.9 assert(!is_inconsistent(), "Precondition"); 3.10 int curr; 3.11 if (_picl->get_int_property(nodeh, name, &curr) == PICL_SUCCESS) { 3.12 @@ -136,7 +136,9 @@ 3.13 } else if (curr != value()) { // following iterations 3.14 set_inconsistent(); 3.15 } 3.16 + return true; 3.17 } 3.18 + return false; 3.19 } 3.20 }; 3.21 3.22 @@ -153,8 +155,19 @@ 3.23 if (!l1_visitor->is_inconsistent()) { 3.24 l1_visitor->visit(nodeh, "l1-dcache-line-size"); 3.25 } 3.26 - if (!l2_visitor->is_inconsistent()) { 3.27 - l2_visitor->visit(nodeh, "l2-cache-line-size"); 3.28 + static const char* l2_data_cache_line_property_name = NULL; 3.29 + // On the first visit determine the name of the l2 cache line size property and memoize it. 3.30 + if (l2_data_cache_line_property_name == NULL) { 3.31 + assert(!l2_visitor->is_inconsistent(), "First iteration cannot be inconsistent"); 3.32 + l2_data_cache_line_property_name = "l2-cache-line-size"; 3.33 + if (!l2_visitor->visit(nodeh, l2_data_cache_line_property_name)) { 3.34 + l2_data_cache_line_property_name = "l2-dcache-line-size"; 3.35 + l2_visitor->visit(nodeh, l2_data_cache_line_property_name); 3.36 + } 3.37 + } else { 3.38 + if (!l2_visitor->is_inconsistent()) { 3.39 + l2_visitor->visit(nodeh, l2_data_cache_line_property_name); 3.40 + } 3.41 } 3.42 3.43 if (l1_visitor->is_inconsistent() && l2_visitor->is_inconsistent()) { 3.44 @@ -170,13 +183,13 @@ 3.45 UniqueValueVisitor* l2_visitor() { return &_l2_visitor; } 3.46 }; 3.47 int _L1_data_cache_line_size; 3.48 - int _L2_cache_line_size; 3.49 + int _L2_data_cache_line_size; 3.50 public: 3.51 static int visit_cpu(picl_nodehdl_t nodeh, void *state) { 3.52 return CPUVisitor::visit(nodeh, state); 3.53 } 3.54 3.55 - PICL(bool is_fujitsu) : _L1_data_cache_line_size(0), _L2_cache_line_size(0), _dl_handle(NULL) { 3.56 + PICL(bool is_fujitsu) : _L1_data_cache_line_size(0), _L2_data_cache_line_size(0), _dl_handle(NULL) { 3.57 if (!open_library()) { 3.58 return; 3.59 } 3.60 @@ -194,7 +207,7 @@ 3.61 _L1_data_cache_line_size = cpu_visitor.l1_visitor()->value(); 3.62 } 3.63 if (cpu_visitor.l2_visitor()->is_assigned()) { 3.64 - _L2_cache_line_size = cpu_visitor.l2_visitor()->value(); 3.65 + _L2_data_cache_line_size = cpu_visitor.l2_visitor()->value(); 3.66 } 3.67 } 3.68 _picl_shutdown(); 3.69 @@ -203,7 +216,7 @@ 3.70 } 3.71 3.72 unsigned int L1_data_cache_line_size() const { return _L1_data_cache_line_size; } 3.73 - unsigned int L2_cache_line_size() const { return _L2_cache_line_size; } 3.74 + unsigned int L2_data_cache_line_size() const { return _L2_data_cache_line_size; } 3.75 }; 3.76 3.77 3.78 @@ -482,7 +495,7 @@ 3.79 3.80 // Figure out cache line sizes using PICL 3.81 PICL picl((features & sparc64_family_m) != 0); 3.82 - _L2_cache_line_size = picl.L2_cache_line_size(); 3.83 + _L2_data_cache_line_size = picl.L2_data_cache_line_size(); 3.84 3.85 return features; 3.86 }