Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
[C2] Redefine memory operands for MIPS.
Wed, 22 Mar 2017 07:13:07 -0400
- author
- fujie
- date
- Wed, 22 Mar 2017 07:13:07 -0400
- changeset 383
- d99ee21cd69f
- parent 382
- a0d5defa38f5
- child 384
- 2d935408fc69
[C2] Redefine memory operands for MIPS.
| src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Mar 22 04:54:35 2017 -0400 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Wed Mar 22 07:13:07 2017 -0400 1.3 @@ -5164,61 +5164,29 @@ 1.4 %} 1.5 1.6 //----------Memory Operands---------------------------------------------------- 1.7 -// Indirect Memory Operand 1.8 -operand indirect(mRegP reg) %{ 1.9 +operand baseOffset16(mRegP reg, immL16 off) 1.10 +%{ 1.11 constraint(ALLOC_IN_RC(p_reg)); 1.12 - match(reg); 1.13 - 1.14 - format %{ "[$reg] @ indirect" %} 1.15 + match(AddP reg off); 1.16 + 1.17 + op_cost(5); 1.18 + format %{ "[$reg + $off (16-bit)] @ baseOffset16" %} 1.19 interface(MEMORY_INTER) %{ 1.20 base($reg); 1.21 - index(0x0); /* NO_INDEX */ 1.22 - scale(0x0); 1.23 - disp(0x0); 1.24 - %} 1.25 -%} 1.26 - 1.27 -// Indirect Memory Plus Short Offset Operand 1.28 -operand indOffset8(mRegP reg, immL8 off) 1.29 -%{ 1.30 - constraint(ALLOC_IN_RC(p_reg)); 1.31 - match(AddP reg off); 1.32 - 1.33 - op_cost(10); 1.34 - format %{ "[$reg + $off (8-bit)] @ indOffset8" %} 1.35 - interface(MEMORY_INTER) %{ 1.36 - base($reg); 1.37 - index(0x0); /* NO_INDEX */ 1.38 + index(0x0); 1.39 scale(0x0); 1.40 disp($off); 1.41 %} 1.42 %} 1.43 1.44 -// Indirect Memory Times Scale Plus Index Register 1.45 -operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale) 1.46 -%{ 1.47 +operand gsBaseIndexOffset8(mRegP base, mRegL index, immL8 off) 1.48 +%{ 1.49 + predicate(UseLoongsonISA); 1.50 constraint(ALLOC_IN_RC(p_reg)); 1.51 - match(AddP reg (LShiftL lreg scale)); 1.52 - 1.53 - op_cost(10); 1.54 - format %{"[$reg + $lreg << $scale] @ indIndexScale" %} 1.55 - interface(MEMORY_INTER) %{ 1.56 - base($reg); 1.57 - index($lreg); 1.58 - scale($scale); 1.59 - disp(0x0); 1.60 - %} 1.61 -%} 1.62 - 1.63 - 1.64 -// [base + index + offset] 1.65 -operand baseIndexOffset8(mRegP base, mRegL index, immL8 off) 1.66 -%{ 1.67 - constraint(ALLOC_IN_RC(p_reg)); 1.68 + match(AddP (AddP base index) off); 1.69 + 1.70 op_cost(5); 1.71 - match(AddP (AddP base index) off); 1.72 - 1.73 - format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %} 1.74 + format %{ "[$base + $index + $off (8-bit)] @ gsBaseIndexOffset8" %} 1.75 interface(MEMORY_INTER) %{ 1.76 base($base); 1.77 index($index); 1.78 @@ -5227,14 +5195,14 @@ 1.79 %} 1.80 %} 1.81 1.82 -// [base + index + offset] 1.83 -operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off) 1.84 -%{ 1.85 +operand gsBaseIndexI2LOffset8(mRegP base, mRegI index, immL8 off) 1.86 +%{ 1.87 + predicate(UseLoongsonISA); 1.88 constraint(ALLOC_IN_RC(p_reg)); 1.89 + match(AddP (AddP base (ConvI2L index)) off); 1.90 + 1.91 op_cost(5); 1.92 - match(AddP (AddP base (ConvI2L index)) off); 1.93 - 1.94 - format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %} 1.95 + format %{ "[$base + $index + $off (8-bit)] @ gsBaseIndexI2LOffset8" %} 1.96 interface(MEMORY_INTER) %{ 1.97 base($base); 1.98 index($index); 1.99 @@ -5243,112 +5211,13 @@ 1.100 %} 1.101 %} 1.102 1.103 -// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 1.104 -operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale) 1.105 -%{ 1.106 - constraint(ALLOC_IN_RC(p_reg)); 1.107 - match(AddP (AddP reg (LShiftL lreg scale)) off); 1.108 - 1.109 - op_cost(10); 1.110 - format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %} 1.111 - interface(MEMORY_INTER) %{ 1.112 - base($reg); 1.113 - index($lreg); 1.114 - scale($scale); 1.115 - disp($off); 1.116 - %} 1.117 -%} 1.118 - 1.119 -operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale) 1.120 -%{ 1.121 - constraint(ALLOC_IN_RC(p_reg)); 1.122 - match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off); 1.123 - 1.124 - op_cost(10); 1.125 - format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %} 1.126 - interface(MEMORY_INTER) %{ 1.127 - base($reg); 1.128 - index($ireg); 1.129 - scale($scale); 1.130 - disp($off); 1.131 - %} 1.132 -%} 1.133 - 1.134 -// [base + index<<scale + offset] 1.135 -operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale) 1.136 -%{ 1.137 - constraint(ALLOC_IN_RC(p_reg)); 1.138 - //predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); 1.139 - op_cost(10); 1.140 - match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off); 1.141 - 1.142 - format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %} 1.143 - interface(MEMORY_INTER) %{ 1.144 - base($base); 1.145 - index($index); 1.146 - scale($scale); 1.147 - disp($off); 1.148 - %} 1.149 -%} 1.150 - 1.151 -// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 1.152 -operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale) 1.153 -%{ 1.154 - predicate(Universe::narrow_oop_shift() == 0); 1.155 - constraint(ALLOC_IN_RC(p_reg)); 1.156 - match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); 1.157 - 1.158 - op_cost(10); 1.159 - format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %} 1.160 - interface(MEMORY_INTER) %{ 1.161 - base($reg); 1.162 - index($lreg); 1.163 - scale($scale); 1.164 - disp($off); 1.165 - %} 1.166 -%} 1.167 - 1.168 -// [base + index<<scale + offset] for compressd Oops 1.169 -operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale) 1.170 -%{ 1.171 - constraint(ALLOC_IN_RC(p_reg)); 1.172 - //predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); 1.173 - predicate(Universe::narrow_oop_shift() == 0); 1.174 - op_cost(10); 1.175 - match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off); 1.176 - 1.177 - format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %} 1.178 - interface(MEMORY_INTER) %{ 1.179 - base($base); 1.180 - index($index); 1.181 - scale($scale); 1.182 - disp($off); 1.183 - %} 1.184 -%} 1.185 - 1.186 -//FIXME: I think it's better to limit the immI to be 16-bit at most! 1.187 -// Indirect Memory Plus Long Offset Operand 1.188 -operand indOffset32(mRegP reg, immL32 off) %{ 1.189 - constraint(ALLOC_IN_RC(p_reg)); 1.190 - op_cost(20); 1.191 - match(AddP reg off); 1.192 - 1.193 - format %{ "[$reg + $off (32-bit)] @ indOffset32" %} 1.194 - interface(MEMORY_INTER) %{ 1.195 - base($reg); 1.196 - index(0x0); /* NO_INDEX */ 1.197 - scale(0x0); 1.198 - disp($off); 1.199 - %} 1.200 -%} 1.201 - 1.202 -// Indirect Memory Plus Index Register 1.203 -operand indIndex(mRegP addr, mRegL index) %{ 1.204 +operand gsBaseIndexOffset0(mRegP addr, mRegL index) %{ 1.205 + predicate(UseLoongsonISA); 1.206 constraint(ALLOC_IN_RC(p_reg)); 1.207 match(AddP addr index); 1.208 1.209 - op_cost(20); 1.210 - format %{"[$addr + $index] @ indIndex" %} 1.211 + op_cost(10); 1.212 + format %{"[$addr + $index] @ gsBaseIndexOffset0" %} 1.213 interface(MEMORY_INTER) %{ 1.214 base($addr); 1.215 index($index); 1.216 @@ -5357,14 +5226,12 @@ 1.217 %} 1.218 %} 1.219 1.220 -operand indirectNarrowKlass(mRegN reg) 1.221 -%{ 1.222 - predicate(Universe::narrow_klass_shift() == 0); 1.223 +operand baseOffset0(mRegP reg) %{ 1.224 constraint(ALLOC_IN_RC(p_reg)); 1.225 op_cost(10); 1.226 - match(DecodeNKlass reg); 1.227 - 1.228 - format %{ "[$reg] @ indirectNarrowKlass" %} 1.229 + match(reg); 1.230 + 1.231 + format %{ "[$reg] @ baseOffset0" %} 1.232 interface(MEMORY_INTER) %{ 1.233 base($reg); 1.234 index(0x0); 1.235 @@ -5373,14 +5240,14 @@ 1.236 %} 1.237 %} 1.238 1.239 -operand indOffset8NarrowKlass(mRegN reg, immL8 off) 1.240 -%{ 1.241 - predicate(Universe::narrow_klass_shift() == 0); 1.242 +operand baseOffset16Narrow(mRegN reg, immL16 off) 1.243 +%{ 1.244 + predicate(Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0); 1.245 constraint(ALLOC_IN_RC(p_reg)); 1.246 - op_cost(10); 1.247 - match(AddP (DecodeNKlass reg) off); 1.248 - 1.249 - format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %} 1.250 + match(AddP (DecodeN reg) off); 1.251 + 1.252 + op_cost(5); 1.253 + format %{ "[$reg + $off (16-bit)] @ baseOffset16Narrow" %} 1.254 interface(MEMORY_INTER) %{ 1.255 base($reg); 1.256 index(0x0); 1.257 @@ -5389,14 +5256,46 @@ 1.258 %} 1.259 %} 1.260 1.261 -operand indOffset32NarrowKlass(mRegN reg, immL32 off) 1.262 -%{ 1.263 - predicate(Universe::narrow_klass_shift() == 0); 1.264 +operand gsBaseIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off) 1.265 +%{ 1.266 + predicate(UseLoongsonISA && Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0); 1.267 constraint(ALLOC_IN_RC(p_reg)); 1.268 + match(AddP (AddP (DecodeN reg) lreg) off); 1.269 + 1.270 + op_cost(5); 1.271 + format %{"[$reg + $off + $lreg] @ gsBaseIndexOffset8Narrow" %} 1.272 + interface(MEMORY_INTER) %{ 1.273 + base($reg); 1.274 + index($lreg); 1.275 + scale(0x0); 1.276 + disp($off); 1.277 + %} 1.278 +%} 1.279 + 1.280 +operand baseOffset0Narrow(mRegN reg) 1.281 +%{ 1.282 + predicate(Universe::narrow_oop_base() == 0 && Universe::narrow_oop_shift() == 0); 1.283 + constraint(ALLOC_IN_RC(p_reg)); 1.284 + match(DecodeN reg); 1.285 + 1.286 op_cost(10); 1.287 + format %{ "[$reg] @ baseOffset0Narrow" %} 1.288 + interface(MEMORY_INTER) %{ 1.289 + base($reg); 1.290 + index(0x0); 1.291 + scale(0x0); 1.292 + disp(0x0); 1.293 + %} 1.294 +%} 1.295 + 1.296 +operand baseOffset16NarrowKlass(mRegN reg, immL16 off) 1.297 +%{ 1.298 + predicate(Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0); 1.299 + constraint(ALLOC_IN_RC(p_reg)); 1.300 match(AddP (DecodeNKlass reg) off); 1.301 1.302 - format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %} 1.303 + op_cost(5); 1.304 + format %{ "[$reg + $off (16-bit)] @ baseOffset16NarrowKlass" %} 1.305 interface(MEMORY_INTER) %{ 1.306 base($reg); 1.307 index(0x0); 1.308 @@ -5405,14 +5304,30 @@ 1.309 %} 1.310 %} 1.311 1.312 -operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off) 1.313 -%{ 1.314 - predicate(Universe::narrow_klass_shift() == 0); 1.315 +operand baseOffset0NarrowKlass(mRegN reg) 1.316 +%{ 1.317 + predicate(Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0); 1.318 + constraint(ALLOC_IN_RC(p_reg)); 1.319 + match(DecodeNKlass reg); 1.320 + 1.321 + op_cost(10); 1.322 + format %{ "[$reg] @ baseOffset0NarrowKlass" %} 1.323 + interface(MEMORY_INTER) %{ 1.324 + base($reg); 1.325 + index(0x0); 1.326 + scale(0x0); 1.327 + disp(0x0); 1.328 + %} 1.329 +%} 1.330 + 1.331 +operand gsBaseIndexOffset8NarrowKlass(mRegN reg, mRegL lreg, immL8 off) 1.332 +%{ 1.333 + predicate(UseLoongsonISA && Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0); 1.334 constraint(ALLOC_IN_RC(p_reg)); 1.335 match(AddP (AddP (DecodeNKlass reg) lreg) off); 1.336 1.337 - op_cost(10); 1.338 - format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %} 1.339 + op_cost(5); 1.340 + format %{"[$reg + $off + $lreg] @ gsBaseIndexOffset8NarrowKlass" %} 1.341 interface(MEMORY_INTER) %{ 1.342 base($reg); 1.343 index($lreg); 1.344 @@ -5421,14 +5336,14 @@ 1.345 %} 1.346 %} 1.347 1.348 -operand indIndexNarrowKlass(mRegN reg, mRegL lreg) 1.349 -%{ 1.350 - predicate(Universe::narrow_klass_shift() == 0); 1.351 +operand gsBaseIndexOffset0NarrowKlass(mRegN reg, mRegL lreg) 1.352 +%{ 1.353 + predicate(UseLoongsonISA && Universe::narrow_klass_base() == 0 && Universe::narrow_klass_shift() == 0); 1.354 constraint(ALLOC_IN_RC(p_reg)); 1.355 match(AddP (DecodeNKlass reg) lreg); 1.356 1.357 op_cost(10); 1.358 - format %{"[$reg + $lreg] @ indIndexNarrowKlass" %} 1.359 + format %{"[$reg + $lreg] @ gsBaseIndexOffset0NarrowKlass" %} 1.360 interface(MEMORY_INTER) %{ 1.361 base($reg); 1.362 index($lreg); 1.363 @@ -5437,100 +5352,26 @@ 1.364 %} 1.365 %} 1.366 1.367 -// Indirect Memory Operand 1.368 -operand indirectNarrow(mRegN reg) 1.369 -%{ 1.370 - predicate(Universe::narrow_oop_shift() == 0); 1.371 - constraint(ALLOC_IN_RC(p_reg)); 1.372 - op_cost(10); 1.373 - match(DecodeN reg); 1.374 - 1.375 - format %{ "[$reg] @ indirectNarrow" %} 1.376 - interface(MEMORY_INTER) %{ 1.377 - base($reg); 1.378 - index(0x0); 1.379 - scale(0x0); 1.380 - disp(0x0); 1.381 - %} 1.382 -%} 1.383 - 1.384 -// Indirect Memory Plus Short Offset Operand 1.385 -operand indOffset8Narrow(mRegN reg, immL8 off) 1.386 -%{ 1.387 - predicate(Universe::narrow_oop_shift() == 0); 1.388 - constraint(ALLOC_IN_RC(p_reg)); 1.389 - op_cost(10); 1.390 - match(AddP (DecodeN reg) off); 1.391 - 1.392 - format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %} 1.393 - interface(MEMORY_INTER) %{ 1.394 - base($reg); 1.395 - index(0x0); 1.396 - scale(0x0); 1.397 - disp($off); 1.398 - %} 1.399 -%} 1.400 - 1.401 -// Indirect Memory Plus Index Register Plus Offset Operand 1.402 -operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off) 1.403 -%{ 1.404 - predicate(Universe::narrow_oop_shift() == 0); 1.405 - constraint(ALLOC_IN_RC(p_reg)); 1.406 - match(AddP (AddP (DecodeN reg) lreg) off); 1.407 - 1.408 - op_cost(10); 1.409 - format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %} 1.410 - interface(MEMORY_INTER) %{ 1.411 - base($reg); 1.412 - index($lreg); 1.413 - scale(0x0); 1.414 - disp($off); 1.415 - %} 1.416 -%} 1.417 - 1.418 -//----------Load Long Memory Operands------------------------------------------ 1.419 -// The load-long idiom will use it's address expression again after loading 1.420 -// the first word of the long. If the load-long destination overlaps with 1.421 -// registers used in the addressing expression, the 2nd half will be loaded 1.422 -// from a clobbered address. Fix this by requiring that load-long use 1.423 -// address registers that do not overlap with the load-long target. 1.424 - 1.425 -// load-long support 1.426 -operand load_long_RegP() %{ 1.427 - constraint(ALLOC_IN_RC(p_reg)); 1.428 - match(RegP); 1.429 - match(mRegP); 1.430 - op_cost(100); 1.431 - format %{ %} 1.432 - interface(REG_INTER); 1.433 -%} 1.434 - 1.435 -// Indirect Memory Operand Long 1.436 -operand load_long_indirect(load_long_RegP reg) %{ 1.437 - constraint(ALLOC_IN_RC(p_reg)); 1.438 - match(reg); 1.439 - 1.440 - format %{ "[$reg]" %} 1.441 - interface(MEMORY_INTER) %{ 1.442 - base($reg); 1.443 - index(0x0); 1.444 - scale(0x0); 1.445 - disp(0x0); 1.446 - %} 1.447 -%} 1.448 - 1.449 -// Indirect Memory Plus Long Offset Operand 1.450 -operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{ 1.451 - match(AddP reg off); 1.452 - 1.453 - format %{ "[$reg + $off]" %} 1.454 - interface(MEMORY_INTER) %{ 1.455 - base($reg); 1.456 - index(0x0); 1.457 - scale(0x0); 1.458 - disp($off); 1.459 - %} 1.460 -%} 1.461 + 1.462 +//------------------------OPERAND CLASSES-------------------------------------- 1.463 +opclass memory( 1.464 + baseOffset16, 1.465 + gsBaseIndexOffset8, 1.466 + gsBaseIndexI2LOffset8, 1.467 + gsBaseIndexOffset0, 1.468 + baseOffset0, 1.469 + 1.470 + baseOffset16Narrow, 1.471 + gsBaseIndexOffset8Narrow, 1.472 + baseOffset0Narrow, 1.473 + 1.474 + baseOffset16NarrowKlass, 1.475 + baseOffset0NarrowKlass, 1.476 + gsBaseIndexOffset8NarrowKlass, 1.477 + gsBaseIndexOffset0NarrowKlass 1.478 +); 1.479 + 1.480 + 1.481 1.482 //----------Conditional Branch Operands---------------------------------------- 1.483 // Comparison Op - This is the operation of the comparison, and is limited to 1.484 @@ -5584,55 +5425,6 @@ 1.485 %} 1.486 %} 1.487 1.488 -/* 1.489 -// Comparison Code, unsigned compare. Used by FP also, with 1.490 -// C2 (unordered) turned into GT or LT already. The other bits 1.491 -// C0 and C3 are turned into Carry & Zero flags. 1.492 -operand cmpOpU() %{ 1.493 - match(Bool); 1.494 - 1.495 - format %{ "" %} 1.496 - interface(COND_INTER) %{ 1.497 - equal(0x4); 1.498 - not_equal(0x5); 1.499 - less(0x2); 1.500 - greater_equal(0x3); 1.501 - less_equal(0x6); 1.502 - greater(0x7); 1.503 - %} 1.504 -%} 1.505 -*/ 1.506 -/* 1.507 -// Comparison Code for FP conditional move 1.508 -operand cmpOp_fcmov() %{ 1.509 - match(Bool); 1.510 - 1.511 - format %{ "" %} 1.512 - interface(COND_INTER) %{ 1.513 - equal (0x01); 1.514 - not_equal (0x02); 1.515 - greater (0x03); 1.516 - greater_equal(0x04); 1.517 - less (0x05); 1.518 - less_equal (0x06); 1.519 - %} 1.520 -%} 1.521 - 1.522 -// Comparision Code used in long compares 1.523 -operand cmpOp_commute() %{ 1.524 - match(Bool); 1.525 - 1.526 - format %{ "" %} 1.527 - interface(COND_INTER) %{ 1.528 - equal(0x4); 1.529 - not_equal(0x5); 1.530 - less(0xF); 1.531 - greater_equal(0xE); 1.532 - less_equal(0xD); 1.533 - greater(0xC); 1.534 - %} 1.535 -%} 1.536 -*/ 1.537 1.538 //----------Special Memory Operands-------------------------------------------- 1.539 // Stack Slot Operand - This operand is used for loading and storing temporary 1.540 @@ -5702,12 +5494,6 @@ 1.541 disp($reg); // Stack Offset 1.542 %} 1.543 %} 1.544 - 1.545 - 1.546 -//------------------------OPERAND CLASSES-------------------------------------- 1.547 -//opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset ); 1.548 -opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow); 1.549 - 1.550 1.551 //----------PIPELINE----------------------------------------------------------- 1.552 // Rules which define the behavior of the target architectures pipeline. 1.553 @@ -12779,72 +12565,6 @@ 1.554 ins_pipe( pipe_jump ); 1.555 %} 1.556 1.557 -instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem) 1.558 -%{ 1.559 - predicate(Universe::narrow_oop_shift() == 0); 1.560 - match(Set dst mem); 1.561 - 1.562 - ins_cost(110); 1.563 - format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %} 1.564 - ins_encode %{ 1.565 - Register dst = $dst$$Register; 1.566 - Register base = as_Register($mem$$base); 1.567 - int disp = $mem$$disp; 1.568 - 1.569 - __ daddiu(dst, base, disp); 1.570 - %} 1.571 - ins_pipe( ialu_regI_imm16 ); 1.572 -%} 1.573 - 1.574 -instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem) 1.575 -%{ 1.576 - match(Set dst mem); 1.577 - 1.578 - ins_cost(110); 1.579 - format %{ "leaq $dst, $mem\t# @ PosIdxScaleOff8" %} 1.580 - ins_encode %{ 1.581 - Register dst = $dst$$Register; 1.582 - Register base = as_Register($mem$$base); 1.583 - Register index = as_Register($mem$$index); 1.584 - int scale = $mem$$scale; 1.585 - int disp = $mem$$disp; 1.586 - 1.587 - if (scale == 0) { 1.588 - __ daddu(AT, base, index); 1.589 - __ daddiu(dst, AT, disp); 1.590 - } else { 1.591 - __ dsll(AT, index, scale); 1.592 - __ daddu(AT, base, AT); 1.593 - __ daddiu(dst, AT, disp); 1.594 - } 1.595 - %} 1.596 - 1.597 - ins_pipe( ialu_regI_imm16 ); 1.598 -%} 1.599 - 1.600 -instruct leaPIdxScale(mRegP dst, indIndexScale mem) 1.601 -%{ 1.602 - match(Set dst mem); 1.603 - 1.604 - ins_cost(110); 1.605 - format %{ "leaq $dst, $mem\t# @ leaPIdxScale" %} 1.606 - ins_encode %{ 1.607 - Register dst = $dst$$Register; 1.608 - Register base = as_Register($mem$$base); 1.609 - Register index = as_Register($mem$$index); 1.610 - int scale = $mem$$scale; 1.611 - 1.612 - if (scale == 0) { 1.613 - __ daddu(dst, base, index); 1.614 - } else { 1.615 - __ dsll(AT, index, scale); 1.616 - __ daddu(dst, base, AT); 1.617 - } 1.618 - %} 1.619 - 1.620 - ins_pipe( ialu_regI_imm16 ); 1.621 -%} 1.622 - 1.623 // Jump Direct Conditional - Label defines a relative address from Jcc+1 1.624 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{ 1.625 match(CountedLoopEnd cop (CmpI src1 src2));
