Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
[C2] Use gssbx in store_B_immI_enc_sync for Loongson CPUs.
Sun, 19 Feb 2017 08:52:27 +0800
- author
- chenhaoxuan
- date
- Sun, 19 Feb 2017 08:52:27 +0800
- changeset 352
- c16a383a79ba
- parent 351
- bbd3c1ebd3b1
- child 353
- 857a6ba055b2
[C2] Use gssbx in store_B_immI_enc_sync for Loongson CPUs.
| src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Sun Feb 19 07:25:00 2017 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Sun Feb 19 08:52:27 2017 +0800 1.3 @@ -2087,51 +2087,131 @@ 1.4 int value = $src$$constant; 1.5 1.6 if( index != 0 ) { 1.7 - if (scale == 0) { 1.8 - __ daddu(AT, as_Register(base), as_Register(index)); 1.9 - } else { 1.10 - __ dsll(AT, as_Register(index), scale); 1.11 - __ daddu(AT, as_Register(base), AT); 1.12 - } 1.13 - if( Assembler::is_simm16(disp) ) { 1.14 - if (value == 0) { 1.15 - __ sb(R0, AT, disp); 1.16 - } else { 1.17 - __ move(T9, value); 1.18 - __ sb(T9, AT, disp); 1.19 - } 1.20 - } else { 1.21 - if (value == 0) { 1.22 - __ move(T9, disp); 1.23 - __ daddu(AT, AT, T9); 1.24 - __ sb(R0, AT, 0); 1.25 - } else { 1.26 - __ move(T9, disp); 1.27 - __ daddu(AT, AT, T9); 1.28 - __ move(T9, value); 1.29 - __ sb(T9, AT, 0); 1.30 - } 1.31 - } 1.32 + if ( UseLoongsonISA ) { 1.33 + if ( Assembler::is_simm(disp,8) ) { 1.34 + if ( scale == 0 ) { 1.35 + if ( value == 0 ) { 1.36 + __ gssbx(R0, as_Register(base), as_Register(index), disp); 1.37 + } else { 1.38 + __ move(AT, value); 1.39 + __ gssbx(AT, as_Register(base), as_Register(index), disp); 1.40 + } 1.41 + } else { 1.42 + __ dsll(AT, as_Register(index), scale); 1.43 + if ( value == 0 ) { 1.44 + __ gssbx(R0, as_Register(base), AT, disp); 1.45 + } else { 1.46 + __ move(T9, value); 1.47 + __ gssbx(T9, as_Register(base), AT, disp); 1.48 + } 1.49 + } 1.50 + } else if ( Assembler::is_simm16(disp) ) { 1.51 + if ( scale == 0 ) { 1.52 + __ daddu(AT, as_Register(base), as_Register(index)); 1.53 + if ( value == 0 ){ 1.54 + __ sb(R0, AT, disp); 1.55 + } else { 1.56 + __ move(T9, value); 1.57 + __ sb(T9, AT, disp); 1.58 + } 1.59 + } else { 1.60 + __ dsll(AT, as_Register(index), scale); 1.61 + __ daddu(AT, as_Register(base), AT); 1.62 + if ( value == 0 ) { 1.63 + __ sb(R0, AT, disp); 1.64 + } else { 1.65 + __ move(T9, value); 1.66 + __ sb(T9, AT, disp); 1.67 + } 1.68 + } 1.69 + } else { 1.70 + if ( scale == 0 ) { 1.71 + __ move(AT, disp); 1.72 + __ daddu(AT, as_Register(index), AT); 1.73 + if ( value == 0 ) { 1.74 + __ gssbx(R0, as_Register(base), AT, 0); 1.75 + } else { 1.76 + __ move(T9, value); 1.77 + __ gssbx(T9, as_Register(base), AT, 0); 1.78 + } 1.79 + } else { 1.80 + __ dsll(AT, as_Register(index), scale); 1.81 + __ move(T9, disp); 1.82 + __ daddu(AT, AT, T9); 1.83 + if ( value == 0 ) { 1.84 + __ gssbx(R0, as_Register(base), AT, 0); 1.85 + } else { 1.86 + __ move(T9, value); 1.87 + __ gssbx(T9, as_Register(base), AT, 0); 1.88 + } 1.89 + } 1.90 + } 1.91 + } else { //not use loongson isa 1.92 + if (scale == 0) { 1.93 + __ daddu(AT, as_Register(base), as_Register(index)); 1.94 + } else { 1.95 + __ dsll(AT, as_Register(index), scale); 1.96 + __ daddu(AT, as_Register(base), AT); 1.97 + } 1.98 + if( Assembler::is_simm16(disp) ) { 1.99 + if (value == 0) { 1.100 + __ sb(R0, AT, disp); 1.101 + } else { 1.102 + __ move(T9, value); 1.103 + __ sb(T9, AT, disp); 1.104 + } 1.105 + } else { 1.106 + if (value == 0) { 1.107 + __ move(T9, disp); 1.108 + __ daddu(AT, AT, T9); 1.109 + __ sb(R0, AT, 0); 1.110 + } else { 1.111 + __ move(T9, disp); 1.112 + __ daddu(AT, AT, T9); 1.113 + __ move(T9, value); 1.114 + __ sb(T9, AT, 0); 1.115 + } 1.116 + } 1.117 + } 1.118 } else { 1.119 - if( Assembler::is_simm16(disp) ) { 1.120 - if (value == 0) { 1.121 - __ sb(R0, as_Register(base), disp); 1.122 - } else { 1.123 - __ move(AT, value); 1.124 - __ sb(AT, as_Register(base), disp); 1.125 - } 1.126 - } else { 1.127 - if (value == 0) { 1.128 - __ move(T9, disp); 1.129 - __ daddu(AT, as_Register(base), T9); 1.130 - __ sb(R0, AT, 0); 1.131 - } else { 1.132 - __ move(T9, disp); 1.133 - __ daddu(AT, as_Register(base), T9); 1.134 - __ move(T9, value); 1.135 - __ sb(T9, AT, 0); 1.136 - } 1.137 - } 1.138 + if ( UseLoongsonISA ){ 1.139 + if ( Assembler::is_simm16(disp) ){ 1.140 + if ( value == 0 ) { 1.141 + __ sb(R0, as_Register(base), disp); 1.142 + } else { 1.143 + __ move(AT, value); 1.144 + __ sb(AT, as_Register(base), disp); 1.145 + } 1.146 + } else { 1.147 + __ move(AT, disp); 1.148 + if ( value == 0 ) { 1.149 + __ gssbx(R0, as_Register(base), AT, 0); 1.150 + } else { 1.151 + __ move(T9, value); 1.152 + __ gssbx(T9, as_Register(base), AT, 0); 1.153 + } 1.154 + } 1.155 + } else { 1.156 + if( Assembler::is_simm16(disp) ) { 1.157 + if (value == 0) { 1.158 + __ sb(R0, as_Register(base), disp); 1.159 + } else { 1.160 + __ move(AT, value); 1.161 + __ sb(AT, as_Register(base), disp); 1.162 + } 1.163 + } else { 1.164 + if (value == 0) { 1.165 + __ move(T9, disp); 1.166 + __ daddu(AT, as_Register(base), T9); 1.167 + __ sb(R0, AT, 0); 1.168 + } else { 1.169 + __ move(T9, disp); 1.170 + __ daddu(AT, as_Register(base), T9); 1.171 + __ move(T9, value); 1.172 + __ sb(T9, AT, 0); 1.173 + } 1.174 + } 1.175 + } 1.176 } 1.177 1.178 __ sync();
