Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Sun Feb 19 08:52:27 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 09:17:43 2017 +0800
     1.3 @@ -2227,27 +2227,67 @@
     1.4       int  disp = $mem$$disp;
     1.5  
     1.6       if( index != 0 ) {
     1.7 -        if (scale == 0) {
     1.8 -           __ daddu(AT, as_Register(base), as_Register(index));
     1.9 -        } else {
    1.10 -           __ dsll(AT, as_Register(index), scale);
    1.11 -           __ daddu(AT, as_Register(base), AT);
    1.12 -        }
    1.13 -        if( Assembler::is_simm16(disp) ) { 
    1.14 -           __ lh(as_Register(dst), AT, disp);
    1.15 -        } else {
    1.16 -           __ move(T9, disp);
    1.17 -           __ addu(AT, AT, T9); 
    1.18 -           __ lh(as_Register(dst), AT, 0);
    1.19 -        }    
    1.20 -     } else {
    1.21 -        if( Assembler::is_simm16(disp) ) { 
    1.22 -           __ lh(as_Register(dst), as_Register(base), disp);
    1.23 -        } else {
    1.24 -           __ move(T9, disp);   
    1.25 -           __ addu(AT, as_Register(base), T9); 
    1.26 -           __ lh(as_Register(dst), AT, 0);
    1.27 -        }    
    1.28 +		 if ( UseLoongsonISA ) {
    1.29 +			if ( Assembler::is_simm(disp, 8) ) {
    1.30 +				if (scale == 0) {
    1.31 +					__ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
    1.32 +				} else {
    1.33 +					__ dsll(AT, as_Register(index), scale);
    1.34 +					__ gslhx(as_Register(dst), as_Register(base), AT, disp);
    1.35 +				}
    1.36 +			} else if ( Assembler::is_simm16(disp) ) {
    1.37 +				if (scale == 0) {
    1.38 +					__ daddu(AT, as_Register(base), as_Register(index));
    1.39 +					__ lh(as_Register(dst), AT, disp);
    1.40 +				} else {
    1.41 +					__ dsll(AT, as_Register(index), scale);
    1.42 +					__ daddu(AT, as_Register(base), AT);
    1.43 +					__ lh(as_Register(dst), AT, disp);
    1.44 +				}
    1.45 +			} else {
    1.46 +				if (scale == 0) {
    1.47 +					__ move(AT, disp);
    1.48 +					__ daddu(AT, as_Register(index), AT);
    1.49 +					__ gslhx(as_Register(dst), as_Register(base), AT, 0);
    1.50 +				} else {
    1.51 +					__ dsll(AT, as_Register(index), scale);
    1.52 +					__ move(T9, disp);
    1.53 +					__ daddu(AT, AT, T9);
    1.54 +					__ gslhx(as_Register(dst), as_Register(base), AT, 0);
    1.55 +				}
    1.56 +			}
    1.57 +		 } else { // not use loongson isa
    1.58 +		    if (scale == 0) {
    1.59 +			   __ daddu(AT, as_Register(base), as_Register(index));
    1.60 +		    } else {
    1.61 +			   __ dsll(AT, as_Register(index), scale);
    1.62 +		       __ daddu(AT, as_Register(base), AT);
    1.63 +			}
    1.64 +		    if( Assembler::is_simm16(disp) ) { 
    1.65 +		       __ lh(as_Register(dst), AT, disp);
    1.66 +	        } else {
    1.67 +	           __ move(T9, disp);
    1.68 +			   __ addu(AT, AT, T9); 
    1.69 +		       __ lh(as_Register(dst), AT, 0);
    1.70 +	        }    
    1.71 +		}
    1.72 +     } else { // index is 0
    1.73 +		 if ( UseLoongsonISA ) {
    1.74 +			if ( Assembler::is_simm16(disp) ) {
    1.75 +				__ lh(as_Register(dst), as_Register(base), disp);
    1.76 +			} else {
    1.77 +				__ move(T9, disp);
    1.78 +				__ gslhx(as_Register(dst), as_Register(base), T9, 0);
    1.79 +			}
    1.80 +		 } else { //not use loongson isa
    1.81 +		    if( Assembler::is_simm16(disp) ) { 
    1.82 +			   __ lh(as_Register(dst), as_Register(base), disp);
    1.83 +		    } else {
    1.84 +	           __ move(T9, disp);   
    1.85 +			   __ addu(AT, as_Register(base), T9); 
    1.86 +		       __ lh(as_Register(dst), AT, 0);
    1.87 +	        }    
    1.88 +		 }
    1.89       }
    1.90    %}
    1.91