1.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp Wed Feb 01 22:24:47 2017 +0800 1.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp Wed Feb 01 22:40:16 2017 +0800 1.3 @@ -1605,8 +1605,9 @@ 1.4 __ seh(FSR, FSR); 1.5 break; 1.6 case Bytecodes::_l2i: 1.7 - __ dsll32(FSR, FSR, 0); 1.8 - __ dsra32(FSR, FSR, 0); 1.9 + __ sll(FSR, FSR, 0); 1.10 + //__ dsll32(FSR, FSR, 0); 1.11 + //__ dsra32(FSR, FSR, 0); 1.12 break; 1.13 case Bytecodes::_l2f: 1.14 __ dmtc1(FSR, FSF);