src/cpu/mips/vm/templateTable_mips_64.cpp

changeset 257
bba1c817d040
parent 256
f64feaeca32f
child 362
e46417a01c32
     1.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Feb 01 22:24:47 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Feb 01 22:40:16 2017 +0800
     1.3 @@ -1605,8 +1605,9 @@
     1.4        __ seh(FSR, FSR);
     1.5        break;
     1.6      case Bytecodes::_l2i:
     1.7 -      __ dsll32(FSR, FSR, 0);
     1.8 -      __ dsra32(FSR, FSR, 0);
     1.9 +      __ sll(FSR, FSR, 0);
    1.10 +      //__ dsll32(FSR, FSR, 0);
    1.11 +      //__ dsra32(FSR, FSR, 0);
    1.12        break;
    1.13      case Bytecodes::_l2f:
    1.14        __ dmtc1(FSR, FSF);

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