Tue, 13 Nov 2018 16:56:02 +0800
#7877 range checking was added for the immediate field of mips instructions
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2017, 2018, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "gc_interface/collectedHeap.inline.hpp"
32 #include "interpreter/interpreter.hpp"
33 #include "memory/cardTableModRefBS.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "prims/methodHandles.hpp"
37 #include "runtime/biasedLocking.hpp"
38 #include "runtime/interfaceSupport.hpp"
39 #include "runtime/objectMonitor.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
46 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc_implementation/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
50 // Implementation of MacroAssembler
52 intptr_t MacroAssembler::i[32] = {0};
53 float MacroAssembler::f[32] = {0.0};
55 void MacroAssembler::print(outputStream *s) {
56 unsigned int k;
57 for(k=0; k<sizeof(i)/sizeof(i[0]); k++) {
58 s->print_cr("i%d = 0x%.16lx", k, i[k]);
59 }
60 s->cr();
62 for(k=0; k<sizeof(f)/sizeof(f[0]); k++) {
63 s->print_cr("f%d = %f", k, f[k]);
64 }
65 s->cr();
66 }
68 int MacroAssembler::i_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->i[k]; }
69 int MacroAssembler::f_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->f[k]; }
71 void MacroAssembler::save_registers(MacroAssembler *masm) {
72 #define __ masm->
73 for(int k=0; k<32; k++) {
74 __ sw (as_Register(k), A0, i_offset(k));
75 }
77 for(int k=0; k<32; k++) {
78 __ swc1 (as_FloatRegister(k), A0, f_offset(k));
79 }
80 #undef __
81 }
83 void MacroAssembler::restore_registers(MacroAssembler *masm) {
84 #define __ masm->
85 for(int k=0; k<32; k++) {
86 __ lw (as_Register(k), A0, i_offset(k));
87 }
89 for(int k=0; k<32; k++) {
90 __ lwc1 (as_FloatRegister(k), A0, f_offset(k));
91 }
92 #undef __
93 }
96 void MacroAssembler::pd_patch_instruction(address branch, address target) {
97 jint& stub_inst = *(jint*) branch;
98 jint *pc = (jint *)branch;
100 if((opcode(stub_inst) == special_op) && (special(stub_inst) == dadd_op)) {
101 //b_far:
102 // move(AT, RA); // dadd
103 // emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
104 // nop();
105 // lui(T9, 0); // to be patched
106 // ori(T9, 0);
107 // daddu(T9, T9, RA);
108 // move(RA, AT);
109 // jr(T9);
111 assert(opcode(pc[3]) == lui_op
112 && opcode(pc[4]) == ori_op
113 && special(pc[5]) == daddu_op, "Not a branch label patch");
114 if(!(opcode(pc[3]) == lui_op
115 && opcode(pc[4]) == ori_op
116 && special(pc[5]) == daddu_op)) { tty->print_cr("Not a branch label patch"); }
118 int offset = target - branch;
119 if (!is_simm16(offset)) {
120 pc[3] = (pc[3] & 0xffff0000) | high16(offset - 12);
121 pc[4] = (pc[4] & 0xffff0000) | low16(offset - 12);
122 } else {
123 /* revert to "beq + nop" */
124 CodeBuffer cb(branch, 4 * 10);
125 MacroAssembler masm(&cb);
126 #define __ masm.
127 __ b(target);
128 __ delayed()->nop();
129 __ nop();
130 __ nop();
131 __ nop();
132 __ nop();
133 __ nop();
134 __ nop();
135 }
136 return;
137 } else if (special(pc[4]) == jr_op
138 && opcode(pc[4]) == special_op
139 && (((opcode(pc[0]) == lui_op) || opcode(pc[0]) == daddiu_op) || (opcode(pc[0]) == ori_op))) {
140 //jmp_far:
141 // patchable_set48(T9, target);
142 // jr(T9);
143 // nop();
145 CodeBuffer cb(branch, 4 * 4);
146 MacroAssembler masm(&cb);
147 masm.patchable_set48(T9, (long)(target));
148 return;
149 }
151 #ifndef PRODUCT
152 if (!is_simm16((target - branch - 4) >> 2)) {
153 tty->print_cr("Illegal patching: branch = 0x%lx, target = 0x%lx", branch, target);
154 tty->print_cr("======= Start decoding at branch = 0x%lx =======", branch);
155 Disassembler::decode(branch - 4 * 16, branch + 4 * 16, tty);
156 tty->print_cr("======= End of decoding =======");
157 }
158 #endif
160 stub_inst = patched_branch(target - branch, stub_inst, 0);
161 }
163 static inline address first_cache_address() {
164 return CodeCache::low_bound() + sizeof(HeapBlock::Header);
165 }
167 static inline address last_cache_address() {
168 return CodeCache::high_bound() - Assembler::InstructionSize;
169 }
171 int MacroAssembler::call_size(address target, bool far, bool patchable) {
172 if (patchable) return 6 << Assembler::LogInstructionSize;
173 if (!far) return 2 << Assembler::LogInstructionSize; // jal + nop
174 return (insts_for_set64((jlong)target) + 2) << Assembler::LogInstructionSize;
175 }
177 // Can we reach target using jal/j from anywhere
178 // in the code cache (because code can be relocated)?
179 bool MacroAssembler::reachable_from_cache(address target) {
180 address cl = first_cache_address();
181 address ch = last_cache_address();
183 return (cl <= target) && (target <= ch) && fit_in_jal(cl, ch);
184 }
186 void MacroAssembler::general_jump(address target) {
187 if (reachable_from_cache(target)) {
188 j(target);
189 delayed()->nop();
190 } else {
191 set64(T9, (long)target);
192 jr(T9);
193 delayed()->nop();
194 }
195 }
197 int MacroAssembler::insts_for_general_jump(address target) {
198 if (reachable_from_cache(target)) {
199 //j(target);
200 //nop();
201 return 2;
202 } else {
203 //set64(T9, (long)target);
204 //jr(T9);
205 //nop();
206 return insts_for_set64((jlong)target) + 2;
207 }
208 }
210 void MacroAssembler::patchable_jump(address target) {
211 if (reachable_from_cache(target)) {
212 nop();
213 nop();
214 nop();
215 nop();
216 j(target);
217 delayed()->nop();
218 } else {
219 patchable_set48(T9, (long)target);
220 jr(T9);
221 delayed()->nop();
222 }
223 }
225 int MacroAssembler::insts_for_patchable_jump(address target) {
226 return 6;
227 }
229 void MacroAssembler::general_call(address target) {
230 if (reachable_from_cache(target)) {
231 jal(target);
232 delayed()->nop();
233 } else {
234 set64(T9, (long)target);
235 jalr(T9);
236 delayed()->nop();
237 }
238 }
240 int MacroAssembler::insts_for_general_call(address target) {
241 if (reachable_from_cache(target)) {
242 //jal(target);
243 //nop();
244 return 2;
245 } else {
246 //set64(T9, (long)target);
247 //jalr(T9);
248 //nop();
249 return insts_for_set64((jlong)target) + 2;
250 }
251 }
253 void MacroAssembler::patchable_call(address target) {
254 if (reachable_from_cache(target)) {
255 nop();
256 nop();
257 nop();
258 nop();
259 jal(target);
260 delayed()->nop();
261 } else {
262 patchable_set48(T9, (long)target);
263 jalr(T9);
264 delayed()->nop();
265 }
266 }
268 int MacroAssembler::insts_for_patchable_call(address target) {
269 return 6;
270 }
272 void MacroAssembler::beq_far(Register rs, Register rt, address entry) {
273 u_char * cur_pc = pc();
275 // Near/Far jump
276 if(is_simm16((entry - pc() - 4) / 4)) {
277 Assembler::beq(rs, rt, offset(entry));
278 } else {
279 Label not_jump;
280 bne(rs, rt, not_jump);
281 delayed()->nop();
283 b_far(entry);
284 delayed()->nop();
286 bind(not_jump);
287 has_delay_slot();
288 }
289 }
291 void MacroAssembler::beq_far(Register rs, Register rt, Label& L) {
292 if (L.is_bound()) {
293 beq_far(rs, rt, target(L));
294 } else {
295 u_char * cur_pc = pc();
296 Label not_jump;
297 bne(rs, rt, not_jump);
298 delayed()->nop();
300 b_far(L);
301 delayed()->nop();
303 bind(not_jump);
304 has_delay_slot();
305 }
306 }
308 void MacroAssembler::bne_far(Register rs, Register rt, address entry) {
309 u_char * cur_pc = pc();
311 //Near/Far jump
312 if(is_simm16((entry - pc() - 4) / 4)) {
313 Assembler::bne(rs, rt, offset(entry));
314 } else {
315 Label not_jump;
316 beq(rs, rt, not_jump);
317 delayed()->nop();
319 b_far(entry);
320 delayed()->nop();
322 bind(not_jump);
323 has_delay_slot();
324 }
325 }
327 void MacroAssembler::bne_far(Register rs, Register rt, Label& L) {
328 if (L.is_bound()) {
329 bne_far(rs, rt, target(L));
330 } else {
331 u_char * cur_pc = pc();
332 Label not_jump;
333 beq(rs, rt, not_jump);
334 delayed()->nop();
336 b_far(L);
337 delayed()->nop();
339 bind(not_jump);
340 has_delay_slot();
341 }
342 }
344 void MacroAssembler::beq_long(Register rs, Register rt, Label& L) {
345 Label not_taken;
347 bne(rs, rt, not_taken);
348 delayed()->nop();
350 jmp_far(L);
352 bind(not_taken);
353 }
355 void MacroAssembler::bne_long(Register rs, Register rt, Label& L) {
356 Label not_taken;
358 beq(rs, rt, not_taken);
359 delayed()->nop();
361 jmp_far(L);
363 bind(not_taken);
364 }
366 void MacroAssembler::bc1t_long(Label& L) {
367 Label not_taken;
369 bc1f(not_taken);
370 delayed()->nop();
372 jmp_far(L);
374 bind(not_taken);
375 }
377 void MacroAssembler::bc1f_long(Label& L) {
378 Label not_taken;
380 bc1t(not_taken);
381 delayed()->nop();
383 jmp_far(L);
385 bind(not_taken);
386 }
388 void MacroAssembler::b_far(Label& L) {
389 if (L.is_bound()) {
390 b_far(target(L));
391 } else {
392 volatile address dest = target(L);
393 /*
394 MacroAssembler::pd_patch_instruction branch=55651ed514, target=55651ef6d8
395 0x00000055651ed514: dadd at, ra, zero
396 0x00000055651ed518: [4110001]bgezal zero, 0x00000055651ed520
398 0x00000055651ed51c: sll zero, zero, 0
399 0x00000055651ed520: lui t9, 0x0
400 0x00000055651ed524: ori t9, t9, 0x21b8
401 0x00000055651ed528: daddu t9, t9, ra
402 0x00000055651ed52c: dadd ra, at, zero
403 0x00000055651ed530: jr t9
404 0x00000055651ed534: sll zero, zero, 0
405 */
406 move(AT, RA);
407 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
408 nop();
409 lui(T9, 0); // to be patched
410 ori(T9, T9, 0);
411 daddu(T9, T9, RA);
412 move(RA, AT);
413 jr(T9);
414 }
415 }
417 void MacroAssembler::b_far(address entry) {
418 u_char * cur_pc = pc();
420 // Near/Far jump
421 if(is_simm16((entry - pc() - 4) / 4)) {
422 b(offset(entry));
423 } else {
424 // address must be bounded
425 move(AT, RA);
426 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
427 nop();
428 li32(T9, entry - pc());
429 daddu(T9, T9, RA);
430 move(RA, AT);
431 jr(T9);
432 }
433 }
435 void MacroAssembler::ld_ptr(Register rt, Register offset, Register base) {
436 addu_long(AT, base, offset);
437 ld_ptr(rt, 0, AT);
438 }
440 void MacroAssembler::st_ptr(Register rt, Register offset, Register base) {
441 addu_long(AT, base, offset);
442 st_ptr(rt, 0, AT);
443 }
445 void MacroAssembler::ld_long(Register rt, Register offset, Register base) {
446 addu_long(AT, base, offset);
447 ld_long(rt, 0, AT);
448 }
450 void MacroAssembler::st_long(Register rt, Register offset, Register base) {
451 addu_long(AT, base, offset);
452 st_long(rt, 0, AT);
453 }
455 Address MacroAssembler::as_Address(AddressLiteral adr) {
456 return Address(adr.target(), adr.rspec());
457 }
459 Address MacroAssembler::as_Address(ArrayAddress adr) {
460 return Address::make_array(adr);
461 }
463 // tmp_reg1 and tmp_reg2 should be saved outside of atomic_inc32 (caller saved).
464 void MacroAssembler::atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2) {
465 Label again;
467 li(tmp_reg1, counter_addr);
468 bind(again);
469 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
470 ll(tmp_reg2, tmp_reg1, 0);
471 addi(tmp_reg2, tmp_reg2, inc);
472 sc(tmp_reg2, tmp_reg1, 0);
473 beq(tmp_reg2, R0, again);
474 delayed()->nop();
475 }
477 int MacroAssembler::biased_locking_enter(Register lock_reg,
478 Register obj_reg,
479 Register swap_reg,
480 Register tmp_reg,
481 bool swap_reg_contains_mark,
482 Label& done,
483 Label* slow_case,
484 BiasedLockingCounters* counters) {
485 assert(UseBiasedLocking, "why call this otherwise?");
486 bool need_tmp_reg = false;
487 if (tmp_reg == noreg) {
488 need_tmp_reg = true;
489 tmp_reg = T9;
490 }
491 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, AT);
492 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
493 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
494 Address saved_mark_addr(lock_reg, 0);
496 // Biased locking
497 // See whether the lock is currently biased toward our thread and
498 // whether the epoch is still valid
499 // Note that the runtime guarantees sufficient alignment of JavaThread
500 // pointers to allow age to be placed into low bits
501 // First check to see whether biasing is even enabled for this object
502 Label cas_label;
503 int null_check_offset = -1;
504 if (!swap_reg_contains_mark) {
505 null_check_offset = offset();
506 ld_ptr(swap_reg, mark_addr);
507 }
509 if (need_tmp_reg) {
510 push(tmp_reg);
511 }
512 move(tmp_reg, swap_reg);
513 andi(tmp_reg, tmp_reg, markOopDesc::biased_lock_mask_in_place);
514 #ifdef _LP64
515 daddi(AT, R0, markOopDesc::biased_lock_pattern);
516 dsub(AT, AT, tmp_reg);
517 #else
518 addi(AT, R0, markOopDesc::biased_lock_pattern);
519 sub(AT, AT, tmp_reg);
520 #endif
521 if (need_tmp_reg) {
522 pop(tmp_reg);
523 }
525 bne(AT, R0, cas_label);
526 delayed()->nop();
529 // The bias pattern is present in the object's header. Need to check
530 // whether the bias owner and the epoch are both still current.
531 // Note that because there is no current thread register on MIPS we
532 // need to store off the mark word we read out of the object to
533 // avoid reloading it and needing to recheck invariants below. This
534 // store is unfortunate but it makes the overall code shorter and
535 // simpler.
536 st_ptr(swap_reg, saved_mark_addr);
537 if (need_tmp_reg) {
538 push(tmp_reg);
539 }
540 if (swap_reg_contains_mark) {
541 null_check_offset = offset();
542 }
543 load_prototype_header(tmp_reg, obj_reg);
544 xorr(tmp_reg, tmp_reg, swap_reg);
545 get_thread(swap_reg);
546 xorr(swap_reg, swap_reg, tmp_reg);
548 move(AT, ~((int) markOopDesc::age_mask_in_place));
549 andr(swap_reg, swap_reg, AT);
551 if (PrintBiasedLockingStatistics) {
552 Label L;
553 bne(swap_reg, R0, L);
554 delayed()->nop();
555 push(tmp_reg);
556 push(A0);
557 atomic_inc32((address)BiasedLocking::biased_lock_entry_count_addr(), 1, A0, tmp_reg);
558 pop(A0);
559 pop(tmp_reg);
560 bind(L);
561 }
562 if (need_tmp_reg) {
563 pop(tmp_reg);
564 }
565 beq(swap_reg, R0, done);
566 delayed()->nop();
567 Label try_revoke_bias;
568 Label try_rebias;
570 // At this point we know that the header has the bias pattern and
571 // that we are not the bias owner in the current epoch. We need to
572 // figure out more details about the state of the header in order to
573 // know what operations can be legally performed on the object's
574 // header.
576 // If the low three bits in the xor result aren't clear, that means
577 // the prototype header is no longer biased and we have to revoke
578 // the bias on this object.
580 move(AT, markOopDesc::biased_lock_mask_in_place);
581 andr(AT, swap_reg, AT);
582 bne(AT, R0, try_revoke_bias);
583 delayed()->nop();
584 // Biasing is still enabled for this data type. See whether the
585 // epoch of the current bias is still valid, meaning that the epoch
586 // bits of the mark word are equal to the epoch bits of the
587 // prototype header. (Note that the prototype header's epoch bits
588 // only change at a safepoint.) If not, attempt to rebias the object
589 // toward the current thread. Note that we must be absolutely sure
590 // that the current epoch is invalid in order to do this because
591 // otherwise the manipulations it performs on the mark word are
592 // illegal.
594 move(AT, markOopDesc::epoch_mask_in_place);
595 andr(AT,swap_reg, AT);
596 bne(AT, R0, try_rebias);
597 delayed()->nop();
598 // The epoch of the current bias is still valid but we know nothing
599 // about the owner; it might be set or it might be clear. Try to
600 // acquire the bias of the object using an atomic operation. If this
601 // fails we will go in to the runtime to revoke the object's bias.
602 // Note that we first construct the presumed unbiased header so we
603 // don't accidentally blow away another thread's valid bias.
605 ld_ptr(swap_reg, saved_mark_addr);
607 move(AT, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
608 andr(swap_reg, swap_reg, AT);
610 if (need_tmp_reg) {
611 push(tmp_reg);
612 }
613 get_thread(tmp_reg);
614 orr(tmp_reg, tmp_reg, swap_reg);
615 //if (os::is_MP()) {
616 // sync();
617 //}
618 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
619 if (need_tmp_reg) {
620 pop(tmp_reg);
621 }
622 // If the biasing toward our thread failed, this means that
623 // another thread succeeded in biasing it toward itself and we
624 // need to revoke that bias. The revocation will occur in the
625 // interpreter runtime in the slow case.
626 if (PrintBiasedLockingStatistics) {
627 Label L;
628 bne(AT, R0, L);
629 delayed()->nop();
630 push(tmp_reg);
631 push(A0);
632 atomic_inc32((address)BiasedLocking::anonymously_biased_lock_entry_count_addr(), 1, A0, tmp_reg);
633 pop(A0);
634 pop(tmp_reg);
635 bind(L);
636 }
637 if (slow_case != NULL) {
638 beq_far(AT, R0, *slow_case);
639 delayed()->nop();
640 }
641 b(done);
642 delayed()->nop();
644 bind(try_rebias);
645 // At this point we know the epoch has expired, meaning that the
646 // current "bias owner", if any, is actually invalid. Under these
647 // circumstances _only_, we are allowed to use the current header's
648 // value as the comparison value when doing the cas to acquire the
649 // bias in the current epoch. In other words, we allow transfer of
650 // the bias from one thread to another directly in this situation.
651 //
652 // FIXME: due to a lack of registers we currently blow away the age
653 // bits in this situation. Should attempt to preserve them.
654 if (need_tmp_reg) {
655 push(tmp_reg);
656 }
657 load_prototype_header(tmp_reg, obj_reg);
658 get_thread(swap_reg);
659 orr(tmp_reg, tmp_reg, swap_reg);
660 ld_ptr(swap_reg, saved_mark_addr);
662 //if (os::is_MP()) {
663 // sync();
664 //}
665 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
666 if (need_tmp_reg) {
667 pop(tmp_reg);
668 }
669 // If the biasing toward our thread failed, then another thread
670 // succeeded in biasing it toward itself and we need to revoke that
671 // bias. The revocation will occur in the runtime in the slow case.
672 if (PrintBiasedLockingStatistics) {
673 Label L;
674 bne(AT, R0, L);
675 delayed()->nop();
676 push(AT);
677 push(tmp_reg);
678 atomic_inc32((address)BiasedLocking::rebiased_lock_entry_count_addr(), 1, AT, tmp_reg);
679 pop(tmp_reg);
680 pop(AT);
681 bind(L);
682 }
683 if (slow_case != NULL) {
684 beq_far(AT, R0, *slow_case);
685 delayed()->nop();
686 }
688 b(done);
689 delayed()->nop();
690 bind(try_revoke_bias);
691 // The prototype mark in the klass doesn't have the bias bit set any
692 // more, indicating that objects of this data type are not supposed
693 // to be biased any more. We are going to try to reset the mark of
694 // this object to the prototype value and fall through to the
695 // CAS-based locking scheme. Note that if our CAS fails, it means
696 // that another thread raced us for the privilege of revoking the
697 // bias of this particular object, so it's okay to continue in the
698 // normal locking code.
699 //
700 // FIXME: due to a lack of registers we currently blow away the age
701 // bits in this situation. Should attempt to preserve them.
702 ld_ptr(swap_reg, saved_mark_addr);
704 if (need_tmp_reg) {
705 push(tmp_reg);
706 }
707 load_prototype_header(tmp_reg, obj_reg);
708 //if (os::is_MP()) {
709 // lock();
710 //}
711 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
712 if (need_tmp_reg) {
713 pop(tmp_reg);
714 }
715 // Fall through to the normal CAS-based lock, because no matter what
716 // the result of the above CAS, some thread must have succeeded in
717 // removing the bias bit from the object's header.
718 if (PrintBiasedLockingStatistics) {
719 Label L;
720 bne(AT, R0, L);
721 delayed()->nop();
722 push(AT);
723 push(tmp_reg);
724 atomic_inc32((address)BiasedLocking::revoked_lock_entry_count_addr(), 1, AT, tmp_reg);
725 pop(tmp_reg);
726 pop(AT);
727 bind(L);
728 }
730 bind(cas_label);
731 return null_check_offset;
732 }
734 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
735 assert(UseBiasedLocking, "why call this otherwise?");
737 // Check for biased locking unlock case, which is a no-op
738 // Note: we do not have to check the thread ID for two reasons.
739 // First, the interpreter checks for IllegalMonitorStateException at
740 // a higher level. Second, if the bias was revoked while we held the
741 // lock, the object could not be rebiased toward another thread, so
742 // the bias bit would be clear.
743 #ifdef _LP64
744 ld(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
745 andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
746 daddi(AT, R0, markOopDesc::biased_lock_pattern);
747 #else
748 lw(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
749 andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
750 addi(AT, R0, markOopDesc::biased_lock_pattern);
751 #endif
753 beq(AT, temp_reg, done);
754 delayed()->nop();
755 }
757 // the stack pointer adjustment is needed. see InterpreterMacroAssembler::super_call_VM_leaf
758 // this method will handle the stack problem, you need not to preserve the stack space for the argument now
759 void MacroAssembler::call_VM_leaf_base(address entry_point, int number_of_arguments) {
760 Label L, E;
762 assert(number_of_arguments <= 4, "just check");
764 andi(AT, SP, 0xf);
765 beq(AT, R0, L);
766 delayed()->nop();
767 daddi(SP, SP, -8);
768 call(entry_point, relocInfo::runtime_call_type);
769 delayed()->nop();
770 daddi(SP, SP, 8);
771 b(E);
772 delayed()->nop();
774 bind(L);
775 call(entry_point, relocInfo::runtime_call_type);
776 delayed()->nop();
777 bind(E);
778 }
781 void MacroAssembler::jmp(address entry) {
782 patchable_set48(T9, (long)entry);
783 jr(T9);
784 }
786 void MacroAssembler::jmp(address entry, relocInfo::relocType rtype) {
787 switch (rtype) {
788 case relocInfo::runtime_call_type:
789 case relocInfo::none:
790 jmp(entry);
791 break;
792 default:
793 {
794 InstructionMark im(this);
795 relocate(rtype);
796 patchable_set48(T9, (long)entry);
797 jr(T9);
798 }
799 break;
800 }
801 }
803 void MacroAssembler::jmp_far(Label& L) {
804 if (L.is_bound()) {
805 address entry = target(L);
806 assert(entry != NULL, "jmp most probably wrong");
807 InstructionMark im(this);
809 relocate(relocInfo::internal_word_type);
810 patchable_set48(T9, (long)entry);
811 } else {
812 InstructionMark im(this);
813 L.add_patch_at(code(), locator());
815 relocate(relocInfo::internal_word_type);
816 patchable_set48(T9, (long)pc());
817 }
819 jr(T9);
820 delayed()->nop();
821 }
822 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
823 int oop_index;
824 if (obj) {
825 oop_index = oop_recorder()->find_index(obj);
826 } else {
827 oop_index = oop_recorder()->allocate_metadata_index(obj);
828 }
829 relocate(metadata_Relocation::spec(oop_index));
830 patchable_set48(AT, (long)obj);
831 sd(AT, dst);
832 }
834 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
835 int oop_index;
836 if (obj) {
837 oop_index = oop_recorder()->find_index(obj);
838 } else {
839 oop_index = oop_recorder()->allocate_metadata_index(obj);
840 }
841 relocate(metadata_Relocation::spec(oop_index));
842 patchable_set48(dst, (long)obj);
843 }
845 void MacroAssembler::call(address entry) {
846 // c/c++ code assume T9 is entry point, so we just always move entry to t9
847 // maybe there is some more graceful method to handle this. FIXME
848 // For more info, see class NativeCall.
849 #ifndef _LP64
850 move(T9, (int)entry);
851 #else
852 patchable_set48(T9, (long)entry);
853 #endif
854 jalr(T9);
855 }
857 void MacroAssembler::call(address entry, relocInfo::relocType rtype) {
858 switch (rtype) {
859 case relocInfo::runtime_call_type:
860 case relocInfo::none:
861 call(entry);
862 break;
863 default:
864 {
865 InstructionMark im(this);
866 relocate(rtype);
867 call(entry);
868 }
869 break;
870 }
871 }
873 void MacroAssembler::call(address entry, RelocationHolder& rh)
874 {
875 switch (rh.type()) {
876 case relocInfo::runtime_call_type:
877 case relocInfo::none:
878 call(entry);
879 break;
880 default:
881 {
882 InstructionMark im(this);
883 relocate(rh);
884 call(entry);
885 }
886 break;
887 }
888 }
890 void MacroAssembler::ic_call(address entry) {
891 RelocationHolder rh = virtual_call_Relocation::spec(pc());
892 patchable_set48(IC_Klass, (long)Universe::non_oop_word());
893 assert(entry != NULL, "call most probably wrong");
894 InstructionMark im(this);
895 relocate(rh);
896 patchable_call(entry);
897 }
899 void MacroAssembler::c2bool(Register r) {
900 Label L;
901 Assembler::beq(r, R0, L);
902 delayed()->nop();
903 move(r, 1);
904 bind(L);
905 }
907 #ifndef PRODUCT
908 extern "C" void findpc(intptr_t x);
909 #endif
911 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
912 // In order to get locks to work, we need to fake a in_VM state
913 JavaThread* thread = JavaThread::current();
914 JavaThreadState saved_state = thread->thread_state();
915 thread->set_thread_state(_thread_in_vm);
916 if (ShowMessageBoxOnError) {
917 JavaThread* thread = JavaThread::current();
918 JavaThreadState saved_state = thread->thread_state();
919 thread->set_thread_state(_thread_in_vm);
920 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
921 ttyLocker ttyl;
922 BytecodeCounter::print();
923 }
924 // To see where a verify_oop failed, get $ebx+40/X for this frame.
925 // This is the value of eip which points to where verify_oop will return.
926 if (os::message_box(msg, "Execution stopped, print registers?")) {
927 ttyLocker ttyl;
928 tty->print_cr("eip = 0x%08x", eip);
929 #ifndef PRODUCT
930 tty->cr();
931 findpc(eip);
932 tty->cr();
933 #endif
934 tty->print_cr("rax, = 0x%08x", rax);
935 tty->print_cr("rbx, = 0x%08x", rbx);
936 tty->print_cr("rcx = 0x%08x", rcx);
937 tty->print_cr("rdx = 0x%08x", rdx);
938 tty->print_cr("rdi = 0x%08x", rdi);
939 tty->print_cr("rsi = 0x%08x", rsi);
940 tty->print_cr("rbp, = 0x%08x", rbp);
941 tty->print_cr("rsp = 0x%08x", rsp);
942 BREAKPOINT;
943 }
944 } else {
945 ttyLocker ttyl;
946 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
947 assert(false, "DEBUG MESSAGE");
948 }
949 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
950 }
952 void MacroAssembler::debug(char* msg/*, RegistersForDebugging* regs*/) {
953 if ( ShowMessageBoxOnError ) {
954 JavaThreadState saved_state = JavaThread::current()->thread_state();
955 JavaThread::current()->set_thread_state(_thread_in_vm);
956 {
957 // In order to get locks work, we need to fake a in_VM state
958 ttyLocker ttyl;
959 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
960 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
961 BytecodeCounter::print();
962 }
964 // if (os::message_box(msg, "Execution stopped, print registers?"))
965 // regs->print(::tty);
966 }
967 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
968 }
969 else
970 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
971 }
974 void MacroAssembler::stop(const char* msg) {
975 li(A0, (long)msg);
976 #ifndef _LP64
977 //reserver space for argument.
978 addiu(SP, SP, - 1 * wordSize);
979 #endif
980 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
981 delayed()->nop();
982 #ifndef _LP64
983 //restore space for argument
984 addiu(SP, SP, 1 * wordSize);
985 #endif
986 brk(17);
987 }
989 void MacroAssembler::warn(const char* msg) {
990 #ifdef _LP64
991 pushad();
992 li(A0, (long)msg);
993 push(S2);
994 move(AT, -(StackAlignmentInBytes));
995 move(S2, SP); // use S2 as a sender SP holder
996 andr(SP, SP, AT); // align stack as required by ABI
997 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
998 delayed()->nop();
999 move(SP, S2); // use S2 as a sender SP holder
1000 pop(S2);
1001 popad();
1002 #else
1003 pushad();
1004 addi(SP, SP, -4);
1005 sw(A0, SP, -1 * wordSize);
1006 li(A0, (long)msg);
1007 addi(SP, SP, -1 * wordSize);
1008 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
1009 delayed()->nop();
1010 addi(SP, SP, 1 * wordSize);
1011 lw(A0, SP, -1 * wordSize);
1012 addi(SP, SP, 4);
1013 popad();
1014 #endif
1015 }
1017 void MacroAssembler::print_reg(Register reg) {
1018 /*
1019 char *s = getenv("PRINT_REG");
1020 if (s == NULL)
1021 return;
1022 if (strcmp(s, "1") != 0)
1023 return;
1024 */
1025 void * cur_pc = pc();
1026 pushad();
1027 NOT_LP64(push(FP);)
1029 li(A0, (long)reg->name());
1030 if (reg == SP)
1031 addiu(A1, SP, wordSize * 23); //23 registers saved in pushad()
1032 else if (reg == A0)
1033 ld(A1, SP, wordSize * 19); //A0 has been modified by li(A0, (long)reg->name()). Ugly Code!
1034 else
1035 move(A1, reg);
1036 li(A2, (long)cur_pc);
1037 push(S2);
1038 move(AT, -(StackAlignmentInBytes));
1039 move(S2, SP); // use S2 as a sender SP holder
1040 andr(SP, SP, AT); // align stack as required by ABI
1041 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_reg_with_pc),relocInfo::runtime_call_type);
1042 delayed()->nop();
1043 move(SP, S2); // use S2 as a sender SP holder
1044 pop(S2);
1045 NOT_LP64(pop(FP);)
1046 popad();
1048 /*
1049 pushad();
1050 #ifdef _LP64
1051 if (reg == SP)
1052 addiu(A0, SP, wordSize * 23); //23 registers saved in pushad()
1053 else
1054 move(A0, reg);
1055 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_long),relocInfo::runtime_call_type);
1056 delayed()->nop();
1057 #else
1058 push(FP);
1059 move(A0, reg);
1060 dsrl32(A1, reg, 0);
1061 //call(CAST_FROM_FN_PTR(address, SharedRuntime::print_int),relocInfo::runtime_call_type);
1062 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_long),relocInfo::runtime_call_type);
1063 delayed()->nop();
1064 pop(FP);
1065 #endif
1066 popad();
1067 pushad();
1068 NOT_LP64(push(FP);)
1069 char b[50];
1070 sprintf((char *)b, " pc: %p\n",cur_pc);
1071 li(A0, (long)(char *)b);
1072 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1073 delayed()->nop();
1074 NOT_LP64(pop(FP);)
1075 popad();
1076 */
1077 }
1079 void MacroAssembler::print_reg(FloatRegister reg) {
1080 void * cur_pc = pc();
1081 pushad();
1082 NOT_LP64(push(FP);)
1083 li(A0, (long)reg->name());
1084 push(S2);
1085 move(AT, -(StackAlignmentInBytes));
1086 move(S2, SP); // use S2 as a sender SP holder
1087 andr(SP, SP, AT); // align stack as required by ABI
1088 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1089 delayed()->nop();
1090 move(SP, S2); // use S2 as a sender SP holder
1091 pop(S2);
1092 NOT_LP64(pop(FP);)
1093 popad();
1095 pushad();
1096 NOT_LP64(push(FP);)
1097 #if 1
1098 move(FP, SP);
1099 move(AT, -(StackAlignmentInBytes));
1100 andr(SP , SP , AT);
1101 mov_d(F12, reg);
1102 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_double),relocInfo::runtime_call_type);
1103 delayed()->nop();
1104 move(SP, FP);
1105 #else
1106 mov_s(F12, reg);
1107 //call(CAST_FROM_FN_PTR(address, SharedRuntime::print_float),relocInfo::runtime_call_type);
1108 //delayed()->nop();
1109 #endif
1110 NOT_LP64(pop(FP);)
1111 popad();
1113 #if 0
1114 pushad();
1115 NOT_LP64(push(FP);)
1116 char* b = new char[50];
1117 sprintf(b, " pc: %p\n", cur_pc);
1118 li(A0, (long)b);
1119 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1120 delayed()->nop();
1121 NOT_LP64(pop(FP);)
1122 popad();
1123 #endif
1124 }
1126 void MacroAssembler::increment(Register reg, int imm) {
1127 if (!imm) return;
1128 if (is_simm16(imm)) {
1129 #ifdef _LP64
1130 daddiu(reg, reg, imm);
1131 #else
1132 addiu(reg, reg, imm);
1133 #endif
1134 } else {
1135 move(AT, imm);
1136 #ifdef _LP64
1137 daddu(reg, reg, AT);
1138 #else
1139 addu(reg, reg, AT);
1140 #endif
1141 }
1142 }
1144 void MacroAssembler::decrement(Register reg, int imm) {
1145 increment(reg, -imm);
1146 }
1149 void MacroAssembler::call_VM(Register oop_result,
1150 address entry_point,
1151 bool check_exceptions) {
1152 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1153 }
1155 void MacroAssembler::call_VM(Register oop_result,
1156 address entry_point,
1157 Register arg_1,
1158 bool check_exceptions) {
1159 if (arg_1!=A1) move(A1, arg_1);
1160 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1161 }
1163 void MacroAssembler::call_VM(Register oop_result,
1164 address entry_point,
1165 Register arg_1,
1166 Register arg_2,
1167 bool check_exceptions) {
1168 if (arg_1!=A1) move(A1, arg_1);
1169 if (arg_2!=A2) move(A2, arg_2);
1170 assert(arg_2 != A1, "smashed argument");
1171 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1172 }
1174 void MacroAssembler::call_VM(Register oop_result,
1175 address entry_point,
1176 Register arg_1,
1177 Register arg_2,
1178 Register arg_3,
1179 bool check_exceptions) {
1180 if (arg_1!=A1) move(A1, arg_1);
1181 if (arg_2!=A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1182 if (arg_3!=A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument");
1183 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1184 }
1186 void MacroAssembler::call_VM(Register oop_result,
1187 Register last_java_sp,
1188 address entry_point,
1189 int number_of_arguments,
1190 bool check_exceptions) {
1191 call_VM_base(oop_result, NOREG, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1192 }
1194 void MacroAssembler::call_VM(Register oop_result,
1195 Register last_java_sp,
1196 address entry_point,
1197 Register arg_1,
1198 bool check_exceptions) {
1199 if (arg_1 != A1) move(A1, arg_1);
1200 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1201 }
1203 void MacroAssembler::call_VM(Register oop_result,
1204 Register last_java_sp,
1205 address entry_point,
1206 Register arg_1,
1207 Register arg_2,
1208 bool check_exceptions) {
1209 if (arg_1 != A1) move(A1, arg_1);
1210 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1211 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1212 }
1214 void MacroAssembler::call_VM(Register oop_result,
1215 Register last_java_sp,
1216 address entry_point,
1217 Register arg_1,
1218 Register arg_2,
1219 Register arg_3,
1220 bool check_exceptions) {
1221 if (arg_1 != A1) move(A1, arg_1);
1222 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1223 if (arg_3 != A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument");
1224 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1225 }
1227 void MacroAssembler::call_VM_base(Register oop_result,
1228 Register java_thread,
1229 Register last_java_sp,
1230 address entry_point,
1231 int number_of_arguments,
1232 bool check_exceptions) {
1234 address before_call_pc;
1235 // determine java_thread register
1236 if (!java_thread->is_valid()) {
1237 #ifndef OPT_THREAD
1238 java_thread = T2;
1239 get_thread(java_thread);
1240 #else
1241 java_thread = TREG;
1242 #endif
1243 }
1244 // determine last_java_sp register
1245 if (!last_java_sp->is_valid()) {
1246 last_java_sp = SP;
1247 }
1248 // debugging support
1249 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1250 assert(number_of_arguments <= 4 , "cannot have negative number of arguments");
1251 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1252 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1254 assert(last_java_sp != FP, "this code doesn't work for last_java_sp == fp, which currently can't portably work anyway since C2 doesn't save ebp");
1256 // set last Java frame before call
1257 before_call_pc = (address)pc();
1258 set_last_Java_frame(java_thread, last_java_sp, FP, before_call_pc);
1260 // do the call
1261 move(A0, java_thread);
1262 call(entry_point, relocInfo::runtime_call_type);
1263 delayed()->nop();
1265 // restore the thread (cannot use the pushed argument since arguments
1266 // may be overwritten by C code generated by an optimizing compiler);
1267 // however can use the register value directly if it is callee saved.
1268 #ifndef OPT_THREAD
1269 get_thread(java_thread);
1270 #else
1271 #ifdef ASSERT
1272 {
1273 Label L;
1274 get_thread(AT);
1275 beq(java_thread, AT, L);
1276 delayed()->nop();
1277 stop("MacroAssembler::call_VM_base: TREG not callee saved?");
1278 bind(L);
1279 }
1280 #endif
1281 #endif
1283 // discard thread and arguments
1284 ld_ptr(SP, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1285 // reset last Java frame
1286 reset_last_Java_frame(java_thread, false);
1288 check_and_handle_popframe(java_thread);
1289 check_and_handle_earlyret(java_thread);
1290 if (check_exceptions) {
1291 // check for pending exceptions (java_thread is set upon return)
1292 Label L;
1293 #ifdef _LP64
1294 ld(AT, java_thread, in_bytes(Thread::pending_exception_offset()));
1295 #else
1296 lw(AT, java_thread, in_bytes(Thread::pending_exception_offset()));
1297 #endif
1298 beq(AT, R0, L);
1299 delayed()->nop();
1300 li(AT, before_call_pc);
1301 push(AT);
1302 jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1303 delayed()->nop();
1304 bind(L);
1305 }
1307 // get oop result if there is one and reset the value in the thread
1308 if (oop_result->is_valid()) {
1309 #ifdef _LP64
1310 ld(oop_result, java_thread, in_bytes(JavaThread::vm_result_offset()));
1311 sd(R0, java_thread, in_bytes(JavaThread::vm_result_offset()));
1312 #else
1313 lw(oop_result, java_thread, in_bytes(JavaThread::vm_result_offset()));
1314 sw(R0, java_thread, in_bytes(JavaThread::vm_result_offset()));
1315 #endif
1316 verify_oop(oop_result);
1317 }
1318 }
1320 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1322 move(V0, SP);
1323 //we also reserve space for java_thread here
1324 #ifndef _LP64
1325 daddi(SP, SP, (1 + number_of_arguments) * (- wordSize));
1326 #endif
1327 move(AT, -(StackAlignmentInBytes));
1328 andr(SP, SP, AT);
1329 call_VM_base(oop_result, NOREG, V0, entry_point, number_of_arguments, check_exceptions);
1331 }
1333 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1334 call_VM_leaf_base(entry_point, number_of_arguments);
1335 }
1337 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1338 if (arg_0 != A0) move(A0, arg_0);
1339 call_VM_leaf(entry_point, 1);
1340 }
1342 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1343 if (arg_0 != A0) move(A0, arg_0);
1344 if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument");
1345 call_VM_leaf(entry_point, 2);
1346 }
1348 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1349 if (arg_0 != A0) move(A0, arg_0);
1350 if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument");
1351 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A0 && arg_2 != A1, "smashed argument");
1352 call_VM_leaf(entry_point, 3);
1353 }
1354 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1355 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1356 }
1359 void MacroAssembler::super_call_VM_leaf(address entry_point,
1360 Register arg_1) {
1361 if (arg_1 != A0) move(A0, arg_1);
1362 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1363 }
1366 void MacroAssembler::super_call_VM_leaf(address entry_point,
1367 Register arg_1,
1368 Register arg_2) {
1369 if (arg_1 != A0) move(A0, arg_1);
1370 if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument");
1371 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1372 }
1373 void MacroAssembler::super_call_VM_leaf(address entry_point,
1374 Register arg_1,
1375 Register arg_2,
1376 Register arg_3) {
1377 if (arg_1 != A0) move(A0, arg_1);
1378 if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument");
1379 if (arg_3 != A2) move(A2, arg_3); assert(arg_3 != A0 && arg_3 != A1, "smashed argument");
1380 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1381 }
1383 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1384 }
1386 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1387 }
1389 void MacroAssembler::null_check(Register reg, int offset) {
1390 if (needs_explicit_null_check(offset)) {
1391 // provoke OS NULL exception if reg = NULL by
1392 // accessing M[reg] w/o changing any (non-CC) registers
1393 // NOTE: cmpl is plenty here to provoke a segv
1394 lw(AT, reg, 0);
1395 // Note: should probably use testl(rax, Address(reg, 0));
1396 // may be shorter code (however, this version of
1397 // testl needs to be implemented first)
1398 } else {
1399 // nothing to do, (later) access of M[reg + offset]
1400 // will provoke OS NULL exception if reg = NULL
1401 }
1402 }
1404 void MacroAssembler::enter() {
1405 push2(RA, FP);
1406 move(FP, SP);
1407 }
1409 void MacroAssembler::leave() {
1410 #ifndef _LP64
1411 //move(SP, FP);
1412 //pop2(FP, RA);
1413 addi(SP, FP, 2 * wordSize);
1414 lw(RA, SP, - 1 * wordSize);
1415 lw(FP, SP, - 2 * wordSize);
1416 #else
1417 daddi(SP, FP, 2 * wordSize);
1418 ld(RA, SP, - 1 * wordSize);
1419 ld(FP, SP, - 2 * wordSize);
1420 #endif
1421 }
1422 /*
1423 void MacroAssembler::os_breakpoint() {
1424 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
1425 // (e.g., MSVC can't call ps() otherwise)
1426 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
1427 }
1428 */
1429 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) {
1430 // determine java_thread register
1431 if (!java_thread->is_valid()) {
1432 #ifndef OPT_THREAD
1433 java_thread = T1;
1434 get_thread(java_thread);
1435 #else
1436 java_thread = TREG;
1437 #endif
1438 }
1439 // we must set sp to zero to clear frame
1440 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1441 // must clear fp, so that compiled frames are not confused; it is possible
1442 // that we need it only for debugging
1443 if(clear_fp) {
1444 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_fp_offset()));
1445 }
1447 // Always clear the pc because it could have been set by make_walkable()
1448 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_pc_offset()));
1449 }
1451 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
1452 Register thread = TREG;
1453 #ifndef OPT_THREAD
1454 get_thread(thread);
1455 #endif
1456 // we must set sp to zero to clear frame
1457 sd(R0, Address(thread, JavaThread::last_Java_sp_offset()));
1458 // must clear fp, so that compiled frames are not confused; it is
1459 // possible that we need it only for debugging
1460 if (clear_fp) {
1461 sd(R0, Address(thread, JavaThread::last_Java_fp_offset()));
1462 }
1464 // Always clear the pc because it could have been set by make_walkable()
1465 sd(R0, Address(thread, JavaThread::last_Java_pc_offset()));
1466 }
1468 // Write serialization page so VM thread can do a pseudo remote membar.
1469 // We use the current thread pointer to calculate a thread specific
1470 // offset to write to within the page. This minimizes bus traffic
1471 // due to cache line collision.
1472 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
1473 move(tmp, thread);
1474 srl(tmp, tmp,os::get_serialize_page_shift_count());
1475 move(AT, (os::vm_page_size() - sizeof(int)));
1476 andr(tmp, tmp,AT);
1477 sw(tmp,Address(tmp, (intptr_t)os::get_memory_serialize_page()));
1478 }
1480 // Calls to C land
1481 //
1482 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
1483 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
1484 // has to be reset to 0. This is required to allow proper stack traversal.
1485 void MacroAssembler::set_last_Java_frame(Register java_thread,
1486 Register last_java_sp,
1487 Register last_java_fp,
1488 address last_java_pc) {
1489 // determine java_thread register
1490 if (!java_thread->is_valid()) {
1491 #ifndef OPT_THREAD
1492 java_thread = T2;
1493 get_thread(java_thread);
1494 #else
1495 java_thread = TREG;
1496 #endif
1497 }
1498 // determine last_java_sp register
1499 if (!last_java_sp->is_valid()) {
1500 last_java_sp = SP;
1501 }
1503 // last_java_fp is optional
1504 if (last_java_fp->is_valid()) {
1505 st_ptr(last_java_fp, java_thread, in_bytes(JavaThread::last_Java_fp_offset()));
1506 }
1508 // last_java_pc is optional
1509 if (last_java_pc != NULL) {
1510 relocate(relocInfo::internal_word_type);
1511 patchable_set48(AT, (long)last_java_pc);
1512 st_ptr(AT, java_thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()));
1513 }
1514 st_ptr(last_java_sp, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1515 }
1517 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
1518 Register last_java_fp,
1519 address last_java_pc) {
1520 // determine last_java_sp register
1521 if (!last_java_sp->is_valid()) {
1522 last_java_sp = SP;
1523 }
1525 Register thread = TREG;
1526 #ifndef OPT_THREAD
1527 get_thread(thread);
1528 #endif
1529 // last_java_fp is optional
1530 if (last_java_fp->is_valid()) {
1531 sd(last_java_fp, Address(thread, JavaThread::last_Java_fp_offset()));
1532 }
1534 // last_java_pc is optional
1535 if (last_java_pc != NULL) {
1536 relocate(relocInfo::internal_word_type);
1537 patchable_set48(AT, (long)last_java_pc);
1538 st_ptr(AT, thread, in_bytes(JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()));
1539 }
1541 sd(last_java_sp, Address(thread, JavaThread::last_Java_sp_offset()));
1542 }
1544 //////////////////////////////////////////////////////////////////////////////////
1545 #if INCLUDE_ALL_GCS
1547 void MacroAssembler::g1_write_barrier_pre(Register obj,
1548 Register pre_val,
1549 Register thread,
1550 Register tmp,
1551 bool tosca_live,
1552 bool expand_call) {
1554 // If expand_call is true then we expand the call_VM_leaf macro
1555 // directly to skip generating the check by
1556 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
1558 #ifdef _LP64
1559 assert(thread == TREG, "must be");
1560 #endif // _LP64
1562 Label done;
1563 Label runtime;
1565 assert(pre_val != noreg, "check this code");
1567 if (obj != noreg) {
1568 assert_different_registers(obj, pre_val, tmp);
1569 assert(pre_val != V0, "check this code");
1570 }
1572 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1573 PtrQueue::byte_offset_of_active()));
1574 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1575 PtrQueue::byte_offset_of_index()));
1576 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1577 PtrQueue::byte_offset_of_buf()));
1580 // Is marking active?
1581 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
1582 lw(AT, in_progress);
1583 } else {
1584 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
1585 lb(AT, in_progress);
1586 }
1587 beq(AT, R0, done);
1588 delayed()->nop();
1590 // Do we need to load the previous value?
1591 if (obj != noreg) {
1592 load_heap_oop(pre_val, Address(obj, 0));
1593 }
1595 // Is the previous value null?
1596 beq(pre_val, R0, done);
1597 delayed()->nop();
1599 // Can we store original value in the thread's buffer?
1600 // Is index == 0?
1601 // (The index field is typed as size_t.)
1603 ld(tmp, index);
1604 beq(tmp, R0, runtime);
1605 delayed()->nop();
1607 daddiu(tmp, tmp, -1 * wordSize);
1608 sd(tmp, index);
1609 ld(AT, buffer);
1610 daddu(tmp, tmp, AT);
1612 // Record the previous value
1613 sd(pre_val, tmp, 0);
1614 beq(R0, R0, done);
1615 delayed()->nop();
1617 bind(runtime);
1618 // save the live input values
1619 if (tosca_live) push(V0);
1621 if (obj != noreg && obj != V0) push(obj);
1623 if (pre_val != V0) push(pre_val);
1625 // Calling the runtime using the regular call_VM_leaf mechanism generates
1626 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
1627 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
1628 //
1629 // If we care generating the pre-barrier without a frame (e.g. in the
1630 // intrinsified Reference.get() routine) then ebp might be pointing to
1631 // the caller frame and so this check will most likely fail at runtime.
1632 //
1633 // Expanding the call directly bypasses the generation of the check.
1634 // So when we do not have have a full interpreter frame on the stack
1635 // expand_call should be passed true.
1637 NOT_LP64( push(thread); )
1639 if (expand_call) {
1640 LP64_ONLY( assert(pre_val != A1, "smashed arg"); )
1641 if (thread != A1) move(A1, thread);
1642 if (pre_val != A0) move(A0, pre_val);
1643 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
1644 } else {
1645 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
1646 }
1648 NOT_LP64( pop(thread); )
1650 // save the live input values
1651 if (pre_val != V0)
1652 pop(pre_val);
1654 if (obj != noreg && obj != V0)
1655 pop(obj);
1657 if(tosca_live) pop(V0);
1659 bind(done);
1660 }
1662 void MacroAssembler::g1_write_barrier_post(Register store_addr,
1663 Register new_val,
1664 Register thread,
1665 Register tmp,
1666 Register tmp2) {
1667 assert(tmp != AT, "must be");
1668 assert(tmp2 != AT, "must be");
1669 #ifdef _LP64
1670 assert(thread == TREG, "must be");
1671 #endif // _LP64
1673 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1674 PtrQueue::byte_offset_of_index()));
1675 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1676 PtrQueue::byte_offset_of_buf()));
1678 BarrierSet* bs = Universe::heap()->barrier_set();
1679 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
1680 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1682 Label done;
1683 Label runtime;
1685 // Does store cross heap regions?
1686 xorr(AT, store_addr, new_val);
1687 dsrl(AT, AT, HeapRegion::LogOfHRGrainBytes);
1688 beq(AT, R0, done);
1689 delayed()->nop();
1692 // crosses regions, storing NULL?
1693 beq(new_val, R0, done);
1694 delayed()->nop();
1696 // storing region crossing non-NULL, is card already dirty?
1697 const Register card_addr = tmp;
1698 const Register cardtable = tmp2;
1700 move(card_addr, store_addr);
1701 dsrl(card_addr, card_addr, CardTableModRefBS::card_shift);
1702 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
1703 // a valid address and therefore is not properly handled by the relocation code.
1704 set64(cardtable, (intptr_t)ct->byte_map_base);
1705 daddu(card_addr, card_addr, cardtable);
1707 lb(AT, card_addr, 0);
1708 daddiu(AT, AT, -1 * (int)G1SATBCardTableModRefBS::g1_young_card_val());
1709 beq(AT, R0, done);
1710 delayed()->nop();
1712 sync();
1713 lb(AT, card_addr, 0);
1714 daddiu(AT, AT, -1 * (int)(int)CardTableModRefBS::dirty_card_val());
1715 beq(AT, R0, done);
1716 delayed()->nop();
1719 // storing a region crossing, non-NULL oop, card is clean.
1720 // dirty card and log.
1721 move(AT, (int)CardTableModRefBS::dirty_card_val());
1722 sb(AT, card_addr, 0);
1724 lw(AT, queue_index);
1725 beq(AT, R0, runtime);
1726 delayed()->nop();
1727 daddiu(AT, AT, -1 * wordSize);
1728 sw(AT, queue_index);
1729 ld(tmp2, buffer);
1730 #ifdef _LP64
1731 ld(AT, queue_index);
1732 daddu(tmp2, tmp2, AT);
1733 sd(card_addr, tmp2, 0);
1734 #else
1735 lw(AT, queue_index);
1736 addu32(tmp2, tmp2, AT);
1737 sw(card_addr, tmp2, 0);
1738 #endif
1739 beq(R0, R0, done);
1740 delayed()->nop();
1742 bind(runtime);
1743 // save the live input values
1744 push(store_addr);
1745 push(new_val);
1746 #ifdef _LP64
1747 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, TREG);
1748 #else
1749 push(thread);
1750 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
1751 pop(thread);
1752 #endif
1753 pop(new_val);
1754 pop(store_addr);
1756 bind(done);
1757 }
1759 #endif // INCLUDE_ALL_GCS
1760 //////////////////////////////////////////////////////////////////////////////////
1763 void MacroAssembler::store_check(Register obj) {
1764 // Does a store check for the oop in register obj. The content of
1765 // register obj is destroyed afterwards.
1766 store_check_part_1(obj);
1767 store_check_part_2(obj);
1768 }
1770 void MacroAssembler::store_check(Register obj, Address dst) {
1771 store_check(obj);
1772 }
1775 // split the store check operation so that other instructions can be scheduled inbetween
1776 void MacroAssembler::store_check_part_1(Register obj) {
1777 BarrierSet* bs = Universe::heap()->barrier_set();
1778 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
1779 #ifdef _LP64
1780 dsrl(obj, obj, CardTableModRefBS::card_shift);
1781 #else
1782 shr(obj, CardTableModRefBS::card_shift);
1783 #endif
1784 }
1786 void MacroAssembler::store_check_part_2(Register obj) {
1787 BarrierSet* bs = Universe::heap()->barrier_set();
1788 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
1789 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
1790 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1792 set64(AT, (long)ct->byte_map_base);
1793 #ifdef _LP64
1794 dadd(AT, AT, obj);
1795 #else
1796 add(AT, AT, obj);
1797 #endif
1798 if (UseConcMarkSweepGC) sync();
1799 sb(R0, AT, 0);
1800 }
1802 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
1803 void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
1804 Register t1, Register t2, Label& slow_case) {
1805 assert_different_registers(obj, var_size_in_bytes, t1, t2, AT);
1807 Register end = t2;
1808 #ifndef OPT_THREAD
1809 Register thread = t1;
1810 get_thread(thread);
1811 #else
1812 Register thread = TREG;
1813 #endif
1814 verify_tlab(t1, t2);//blows t1&t2
1816 ld_ptr(obj, thread, in_bytes(JavaThread::tlab_top_offset()));
1818 if (var_size_in_bytes == NOREG) {
1819 set64(AT, con_size_in_bytes);
1820 add(end, obj, AT);
1821 } else {
1822 add(end, obj, var_size_in_bytes);
1823 }
1825 ld_ptr(AT, thread, in_bytes(JavaThread::tlab_end_offset()));
1826 sltu(AT, AT, end);
1827 bne_far(AT, R0, slow_case);
1828 delayed()->nop();
1831 // update the tlab top pointer
1832 st_ptr(end, thread, in_bytes(JavaThread::tlab_top_offset()));
1834 verify_tlab(t1, t2);
1835 }
1837 // Defines obj, preserves var_size_in_bytes
1838 void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
1839 Register t1, Register t2, Label& slow_case) {
1840 assert_different_registers(obj, var_size_in_bytes, t1, AT);
1841 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
1842 // No allocation in the shared eden.
1843 b_far(slow_case);
1844 delayed()->nop();
1845 } else {
1847 #ifndef _LP64
1848 Address heap_top(t1, Assembler::split_low((intptr_t)Universe::heap()->top_addr()));
1849 lui(t1, split_high((intptr_t)Universe::heap()->top_addr()));
1850 #else
1851 Address heap_top(t1);
1852 li(t1, (long)Universe::heap()->top_addr());
1853 #endif
1854 ld_ptr(obj, heap_top);
1856 Register end = t2;
1857 Label retry;
1859 bind(retry);
1860 if (var_size_in_bytes == NOREG) {
1861 set64(AT, con_size_in_bytes);
1862 add(end, obj, AT);
1863 } else {
1864 add(end, obj, var_size_in_bytes);
1865 }
1866 // if end < obj then we wrapped around => object too long => slow case
1867 sltu(AT, end, obj);
1868 bne_far(AT, R0, slow_case);
1869 delayed()->nop();
1871 li(AT, (long)Universe::heap()->end_addr());
1872 ld_ptr(AT, AT, 0);
1873 sltu(AT, AT, end);
1874 bne_far(AT, R0, slow_case);
1875 delayed()->nop();
1876 // Compare obj with the top addr, and if still equal, store the new top addr in
1877 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
1878 // it otherwise. Use lock prefix for atomicity on MPs.
1879 //if (os::is_MP()) {
1880 // sync();
1881 //}
1883 // if someone beat us on the allocation, try again, otherwise continue
1884 cmpxchg(end, heap_top, obj);
1885 beq_far(AT, R0, retry);
1886 delayed()->nop();
1887 }
1888 }
1890 // C2 doesn't invoke this one.
1891 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
1892 Register top = T0;
1893 Register t1 = T1;
1894 Register t2 = T9;
1895 Register t3 = T3;
1896 Register thread_reg = T8;
1897 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ T2, A4);
1898 Label do_refill, discard_tlab;
1900 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
1901 // No allocation in the shared eden.
1902 b(slow_case);
1903 delayed()->nop();
1904 }
1906 get_thread(thread_reg);
1908 ld_ptr(top, thread_reg, in_bytes(JavaThread::tlab_top_offset()));
1909 ld_ptr(t1, thread_reg, in_bytes(JavaThread::tlab_end_offset()));
1911 // calculate amount of free space
1912 sub(t1, t1, top);
1913 shr(t1, LogHeapWordSize);
1915 // Retain tlab and allocate object in shared space if
1916 // the amount free in the tlab is too large to discard.
1917 ld_ptr(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
1918 slt(AT, t2, t1);
1919 beq(AT, R0, discard_tlab);
1920 delayed()->nop();
1922 // Retain
1923 #ifndef _LP64
1924 move(AT, ThreadLocalAllocBuffer::refill_waste_limit_increment());
1925 #else
1926 li(AT, ThreadLocalAllocBuffer::refill_waste_limit_increment());
1927 #endif
1928 add(t2, t2, AT);
1929 st_ptr(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
1931 if (TLABStats) {
1932 // increment number of slow_allocations
1933 lw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset()));
1934 addiu(AT, AT, 1);
1935 sw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset()));
1936 }
1937 b(try_eden);
1938 delayed()->nop();
1940 bind(discard_tlab);
1941 if (TLABStats) {
1942 // increment number of refills
1943 lw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset()));
1944 addi(AT, AT, 1);
1945 sw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset()));
1946 // accumulate wastage -- t1 is amount free in tlab
1947 lw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
1948 add(AT, AT, t1);
1949 sw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
1950 }
1952 // if tlab is currently allocated (top or end != null) then
1953 // fill [top, end + alignment_reserve) with array object
1954 beq(top, R0, do_refill);
1955 delayed()->nop();
1957 // set up the mark word
1958 li(AT, (long)markOopDesc::prototype()->copy_set_hash(0x2));
1959 st_ptr(AT, top, oopDesc::mark_offset_in_bytes());
1961 // set the length to the remaining space
1962 addi(t1, t1, - typeArrayOopDesc::header_size(T_INT));
1963 addi(t1, t1, ThreadLocalAllocBuffer::alignment_reserve());
1964 shl(t1, log2_intptr(HeapWordSize/sizeof(jint)));
1965 sw(t1, top, arrayOopDesc::length_offset_in_bytes());
1967 // set klass to intArrayKlass
1968 #ifndef _LP64
1969 lui(AT, split_high((intptr_t)Universe::intArrayKlassObj_addr()));
1970 lw(t1, AT, split_low((intptr_t)Universe::intArrayKlassObj_addr()));
1971 #else
1972 li(AT, (intptr_t)Universe::intArrayKlassObj_addr());
1973 ld_ptr(t1, AT, 0);
1974 #endif
1975 //st_ptr(t1, top, oopDesc::klass_offset_in_bytes());
1976 store_klass(top, t1);
1978 ld_ptr(t1, thread_reg, in_bytes(JavaThread::tlab_start_offset()));
1979 subu(t1, top, t1);
1980 incr_allocated_bytes(thread_reg, t1, 0);
1982 // refill the tlab with an eden allocation
1983 bind(do_refill);
1984 ld_ptr(t1, thread_reg, in_bytes(JavaThread::tlab_size_offset()));
1985 shl(t1, LogHeapWordSize);
1986 // add object_size ??
1987 eden_allocate(top, t1, 0, t2, t3, slow_case);
1989 // Check that t1 was preserved in eden_allocate.
1990 #ifdef ASSERT
1991 if (UseTLAB) {
1992 Label ok;
1993 assert_different_registers(thread_reg, t1);
1994 ld_ptr(AT, thread_reg, in_bytes(JavaThread::tlab_size_offset()));
1995 shl(AT, LogHeapWordSize);
1996 beq(AT, t1, ok);
1997 delayed()->nop();
1998 stop("assert(t1 != tlab size)");
1999 should_not_reach_here();
2001 bind(ok);
2002 }
2003 #endif
2004 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_start_offset()));
2005 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_top_offset()));
2006 add(top, top, t1);
2007 addi(top, top, - ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
2008 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_end_offset()));
2009 verify_tlab(t1, t2);
2010 b(retry);
2011 delayed()->nop();
2012 }
2014 void MacroAssembler::incr_allocated_bytes(Register thread,
2015 Register var_size_in_bytes,
2016 int con_size_in_bytes,
2017 Register t1) {
2018 if (!thread->is_valid()) {
2019 #ifndef OPT_THREAD
2020 assert(t1->is_valid(), "need temp reg");
2021 thread = t1;
2022 get_thread(thread);
2023 #else
2024 thread = TREG;
2025 #endif
2026 }
2028 ld_ptr(AT, thread, in_bytes(JavaThread::allocated_bytes_offset()));
2029 if (var_size_in_bytes->is_valid()) {
2030 addu(AT, AT, var_size_in_bytes);
2031 } else {
2032 addiu(AT, AT, con_size_in_bytes);
2033 }
2034 st_ptr(AT, thread, in_bytes(JavaThread::allocated_bytes_offset()));
2035 }
2037 static const double pi_4 = 0.7853981633974483;
2039 // the x86 version is to clumsy, i dont think we need that fuss. maybe i'm wrong, FIXME
2040 // must get argument(a double) in F12/F13
2041 //void MacroAssembler::trigfunc(char trig, bool preserve_cpu_regs, int num_fpu_regs_in_use) {
2042 //We need to preseve the register which maybe modified during the Call
2043 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
2044 //save all modified register here
2045 //FIXME, in the disassembly of tirgfunc, only used V0,V1,T9, SP,RA,so we ony save V0,V1,T9
2046 pushad();
2047 //we should preserve the stack space before we call
2048 addi(SP, SP, -wordSize * 2);
2049 switch (trig){
2050 case 's' :
2051 call( CAST_FROM_FN_PTR(address, SharedRuntime::dsin), relocInfo::runtime_call_type );
2052 delayed()->nop();
2053 break;
2054 case 'c':
2055 call( CAST_FROM_FN_PTR(address, SharedRuntime::dcos), relocInfo::runtime_call_type );
2056 delayed()->nop();
2057 break;
2058 case 't':
2059 call( CAST_FROM_FN_PTR(address, SharedRuntime::dtan), relocInfo::runtime_call_type );
2060 delayed()->nop();
2061 break;
2062 default:assert (false, "bad intrinsic");
2063 break;
2065 }
2067 addi(SP, SP, wordSize * 2);
2068 popad();
2069 }
2071 #ifdef _LP64
2072 void MacroAssembler::li(Register rd, long imm) {
2073 if (imm <= max_jint && imm >= min_jint) {
2074 li32(rd, (int)imm);
2075 } else if (julong(imm) <= 0xFFFFFFFF) {
2076 assert_not_delayed();
2077 // lui sign-extends, so we can't use that.
2078 ori(rd, R0, julong(imm) >> 16);
2079 dsll(rd, rd, 16);
2080 ori(rd, rd, split_low(imm));
2081 } else if ((imm > 0) && is_simm16(imm >> 32)) {
2082 /* A 48-bit address */
2083 li48(rd, imm);
2084 } else {
2085 li64(rd, imm);
2086 }
2087 }
2088 #else
2089 void MacroAssembler::li(Register rd, long imm) {
2090 li32(rd, (int)imm);
2091 }
2092 #endif
2094 void MacroAssembler::li32(Register reg, int imm) {
2095 if (is_simm16(imm)) {
2096 /* for imm < 0, we should use addi instead of addiu.
2097 *
2098 * java.lang.StringCoding$StringDecoder.decode(jobject, jint, jint)
2099 *
2100 * 78 move [int:-1|I] [a0|I]
2101 * : daddi a0, zero, 0xffffffff (correct)
2102 * : daddiu a0, zero, 0xffffffff (incorrect)
2103 */
2104 if (imm >= 0)
2105 addiu(reg, R0, imm);
2106 else
2107 addi(reg, R0, imm);
2108 } else {
2109 lui(reg, split_low(imm >> 16));
2110 if (split_low(imm))
2111 ori(reg, reg, split_low(imm));
2112 }
2113 }
2115 #ifdef _LP64
2116 void MacroAssembler::set64(Register d, jlong value) {
2117 assert_not_delayed();
2119 int hi = (int)(value >> 32);
2120 int lo = (int)(value & ~0);
2122 if (value == lo) { // 32-bit integer
2123 if (is_simm16(value)) {
2124 daddiu(d, R0, value);
2125 } else {
2126 lui(d, split_low(value >> 16));
2127 if (split_low(value)) {
2128 ori(d, d, split_low(value));
2129 }
2130 }
2131 } else if (hi == 0) { // hardware zero-extends to upper 32
2132 ori(d, R0, julong(value) >> 16);
2133 dsll(d, d, 16);
2134 if (split_low(value)) {
2135 ori(d, d, split_low(value));
2136 }
2137 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2138 // 4 insts
2139 li48(d, value);
2140 } else { // li64
2141 // 6 insts
2142 li64(d, value);
2143 }
2144 }
2147 int MacroAssembler::insts_for_set64(jlong value) {
2148 int hi = (int)(value >> 32);
2149 int lo = (int)(value & ~0);
2151 int count = 0;
2153 if (value == lo) { // 32-bit integer
2154 if (is_simm16(value)) {
2155 //daddiu(d, R0, value);
2156 count++;
2157 } else {
2158 //lui(d, split_low(value >> 16));
2159 count++;
2160 if (split_low(value)) {
2161 //ori(d, d, split_low(value));
2162 count++;
2163 }
2164 }
2165 } else if (hi == 0) { // hardware zero-extends to upper 32
2166 //ori(d, R0, julong(value) >> 16);
2167 //dsll(d, d, 16);
2168 count += 2;
2169 if (split_low(value)) {
2170 //ori(d, d, split_low(value));
2171 count++;
2172 }
2173 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2174 // 4 insts
2175 //li48(d, value);
2176 count += 4;
2177 } else { // li64
2178 // 6 insts
2179 //li64(d, value);
2180 count += 6;
2181 }
2183 return count;
2184 }
2186 void MacroAssembler::patchable_set48(Register d, jlong value) {
2187 assert_not_delayed();
2189 int hi = (int)(value >> 32);
2190 int lo = (int)(value & ~0);
2192 int count = 0;
2194 if (value == lo) { // 32-bit integer
2195 if (is_simm16(value)) {
2196 daddiu(d, R0, value);
2197 count += 1;
2198 } else {
2199 lui(d, split_low(value >> 16));
2200 count += 1;
2201 if (split_low(value)) {
2202 ori(d, d, split_low(value));
2203 count += 1;
2204 }
2205 }
2206 } else if (hi == 0) { // hardware zero-extends to upper 32
2207 ori(d, R0, julong(value) >> 16);
2208 dsll(d, d, 16);
2209 count += 2;
2210 if (split_low(value)) {
2211 ori(d, d, split_low(value));
2212 count += 1;
2213 }
2214 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2215 // 4 insts
2216 li48(d, value);
2217 count += 4;
2218 } else { // li64
2219 tty->print_cr("value = 0x%x", value);
2220 guarantee(false, "Not supported yet !");
2221 }
2223 while (count < 4) {
2224 nop();
2225 count++;
2226 }
2227 }
2229 void MacroAssembler::patchable_set32(Register d, jlong value) {
2230 assert_not_delayed();
2232 int hi = (int)(value >> 32);
2233 int lo = (int)(value & ~0);
2235 int count = 0;
2237 if (value == lo) { // 32-bit integer
2238 if (is_simm16(value)) {
2239 daddiu(d, R0, value);
2240 count += 1;
2241 } else {
2242 lui(d, split_low(value >> 16));
2243 count += 1;
2244 if (split_low(value)) {
2245 ori(d, d, split_low(value));
2246 count += 1;
2247 }
2248 }
2249 } else if (hi == 0) { // hardware zero-extends to upper 32
2250 ori(d, R0, julong(value) >> 16);
2251 dsll(d, d, 16);
2252 count += 2;
2253 if (split_low(value)) {
2254 ori(d, d, split_low(value));
2255 count += 1;
2256 }
2257 } else {
2258 tty->print_cr("value = 0x%x", value);
2259 guarantee(false, "Not supported yet !");
2260 }
2262 while (count < 3) {
2263 nop();
2264 count++;
2265 }
2266 }
2268 void MacroAssembler::patchable_call32(Register d, jlong value) {
2269 assert_not_delayed();
2271 int hi = (int)(value >> 32);
2272 int lo = (int)(value & ~0);
2274 int count = 0;
2276 if (value == lo) { // 32-bit integer
2277 if (is_simm16(value)) {
2278 daddiu(d, R0, value);
2279 count += 1;
2280 } else {
2281 lui(d, split_low(value >> 16));
2282 count += 1;
2283 if (split_low(value)) {
2284 ori(d, d, split_low(value));
2285 count += 1;
2286 }
2287 }
2288 } else {
2289 tty->print_cr("value = 0x%x", value);
2290 guarantee(false, "Not supported yet !");
2291 }
2293 while (count < 2) {
2294 nop();
2295 count++;
2296 }
2297 }
2299 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
2300 assert(UseCompressedClassPointers, "should only be used for compressed header");
2301 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2303 int klass_index = oop_recorder()->find_index(k);
2304 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2305 long narrowKlass = (long)Klass::encode_klass(k);
2307 relocate(rspec, Assembler::narrow_oop_operand);
2308 patchable_set48(dst, narrowKlass);
2309 }
2312 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
2313 assert(UseCompressedOops, "should only be used for compressed header");
2314 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2316 int oop_index = oop_recorder()->find_index(obj);
2317 RelocationHolder rspec = oop_Relocation::spec(oop_index);
2319 relocate(rspec, Assembler::narrow_oop_operand);
2320 patchable_set48(dst, oop_index);
2321 }
2323 void MacroAssembler::li64(Register rd, long imm) {
2324 assert_not_delayed();
2325 lui(rd, split_low(imm >> 48));
2326 ori(rd, rd, split_low(imm >> 32));
2327 dsll(rd, rd, 16);
2328 ori(rd, rd, split_low(imm >> 16));
2329 dsll(rd, rd, 16);
2330 ori(rd, rd, split_low(imm));
2331 }
2333 void MacroAssembler::li48(Register rd, long imm) {
2334 assert_not_delayed();
2335 assert(is_simm16(imm >> 32), "Not a 48-bit address");
2336 lui(rd, imm >> 32);
2337 ori(rd, rd, split_low(imm >> 16));
2338 dsll(rd, rd, 16);
2339 ori(rd, rd, split_low(imm));
2340 }
2341 #endif
2342 // NOTE: i dont push eax as i486.
2343 // the x86 save eax for it use eax as the jump register
2344 void MacroAssembler::verify_oop(Register reg, const char* s) {
2345 /*
2346 if (!VerifyOops) return;
2348 // Pass register number to verify_oop_subroutine
2349 char* b = new char[strlen(s) + 50];
2350 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
2351 push(rax); // save rax,
2352 push(reg); // pass register argument
2353 ExternalAddress buffer((address) b);
2354 // avoid using pushptr, as it modifies scratch registers
2355 // and our contract is not to modify anything
2356 movptr(rax, buffer.addr());
2357 push(rax);
2358 // call indirectly to solve generation ordering problem
2359 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2360 call(rax);
2361 */
2362 if (!VerifyOops) return;
2363 const char * b = NULL;
2364 stringStream ss;
2365 ss.print("verify_oop: %s: %s", reg->name(), s);
2366 b = code_string(ss.as_string());
2367 #ifdef _LP64
2368 pushad();
2369 move(A1, reg);
2370 li(A0, (long)b);
2371 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2372 ld(T9, AT, 0);
2373 jalr(T9);
2374 delayed()->nop();
2375 popad();
2376 #else
2377 // Pass register number to verify_oop_subroutine
2378 sw(T0, SP, - wordSize);
2379 sw(T1, SP, - 2*wordSize);
2380 sw(RA, SP, - 3*wordSize);
2381 sw(A0, SP ,- 4*wordSize);
2382 sw(A1, SP ,- 5*wordSize);
2383 sw(AT, SP ,- 6*wordSize);
2384 sw(T9, SP ,- 7*wordSize);
2385 addiu(SP, SP, - 7 * wordSize);
2386 move(A1, reg);
2387 li(A0, (long)b);
2388 // call indirectly to solve generation ordering problem
2389 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2390 lw(T9, AT, 0);
2391 jalr(T9);
2392 delayed()->nop();
2393 lw(T0, SP, 6* wordSize);
2394 lw(T1, SP, 5* wordSize);
2395 lw(RA, SP, 4* wordSize);
2396 lw(A0, SP, 3* wordSize);
2397 lw(A1, SP, 2* wordSize);
2398 lw(AT, SP, 1* wordSize);
2399 lw(T9, SP, 0* wordSize);
2400 addiu(SP, SP, 7 * wordSize);
2401 #endif
2402 }
2405 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
2406 if (!VerifyOops) {
2407 nop();
2408 return;
2409 }
2410 // Pass register number to verify_oop_subroutine
2411 const char * b = NULL;
2412 stringStream ss;
2413 ss.print("verify_oop_addr: %s", s);
2414 b = code_string(ss.as_string());
2416 st_ptr(T0, SP, - wordSize);
2417 st_ptr(T1, SP, - 2*wordSize);
2418 st_ptr(RA, SP, - 3*wordSize);
2419 st_ptr(A0, SP, - 4*wordSize);
2420 st_ptr(A1, SP, - 5*wordSize);
2421 st_ptr(AT, SP, - 6*wordSize);
2422 st_ptr(T9, SP, - 7*wordSize);
2423 ld_ptr(A1, addr); // addr may use SP, so load from it before change SP
2424 addiu(SP, SP, - 7 * wordSize);
2426 li(A0, (long)b);
2427 // call indirectly to solve generation ordering problem
2428 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2429 ld_ptr(T9, AT, 0);
2430 jalr(T9);
2431 delayed()->nop();
2432 ld_ptr(T0, SP, 6* wordSize);
2433 ld_ptr(T1, SP, 5* wordSize);
2434 ld_ptr(RA, SP, 4* wordSize);
2435 ld_ptr(A0, SP, 3* wordSize);
2436 ld_ptr(A1, SP, 2* wordSize);
2437 ld_ptr(AT, SP, 1* wordSize);
2438 ld_ptr(T9, SP, 0* wordSize);
2439 addiu(SP, SP, 7 * wordSize);
2440 }
2442 // used registers : T0, T1
2443 void MacroAssembler::verify_oop_subroutine() {
2444 // RA: ra
2445 // A0: char* error message
2446 // A1: oop object to verify
2448 Label exit, error;
2449 // increment counter
2450 li(T0, (long)StubRoutines::verify_oop_count_addr());
2451 lw(AT, T0, 0);
2452 #ifdef _LP64
2453 daddi(AT, AT, 1);
2454 #else
2455 addi(AT, AT, 1);
2456 #endif
2457 sw(AT, T0, 0);
2459 // make sure object is 'reasonable'
2460 beq(A1, R0, exit); // if obj is NULL it is ok
2461 delayed()->nop();
2463 // Check if the oop is in the right area of memory
2464 //const int oop_mask = Universe::verify_oop_mask();
2465 //const int oop_bits = Universe::verify_oop_bits();
2466 const uintptr_t oop_mask = Universe::verify_oop_mask();
2467 const uintptr_t oop_bits = Universe::verify_oop_bits();
2468 li(AT, oop_mask);
2469 andr(T0, A1, AT);
2470 li(AT, oop_bits);
2471 bne(T0, AT, error);
2472 delayed()->nop();
2474 // make sure klass is 'reasonable'
2475 //add for compressedoops
2476 reinit_heapbase();
2477 //add for compressedoops
2478 load_klass(T0, A1);
2479 beq(T0, R0, error); // if klass is NULL it is broken
2480 delayed()->nop();
2481 #if 0
2482 //FIXME:wuhui.
2483 // Check if the klass is in the right area of memory
2484 //const int klass_mask = Universe::verify_klass_mask();
2485 //const int klass_bits = Universe::verify_klass_bits();
2486 const uintptr_t klass_mask = Universe::verify_klass_mask();
2487 const uintptr_t klass_bits = Universe::verify_klass_bits();
2489 li(AT, klass_mask);
2490 andr(T1, T0, AT);
2491 li(AT, klass_bits);
2492 bne(T1, AT, error);
2493 delayed()->nop();
2494 // make sure klass' klass is 'reasonable'
2495 //add for compressedoops
2496 load_klass(T0, T0);
2497 beq(T0, R0, error); // if klass' klass is NULL it is broken
2498 delayed()->nop();
2500 li(AT, klass_mask);
2501 andr(T1, T0, AT);
2502 li(AT, klass_bits);
2503 bne(T1, AT, error);
2504 delayed()->nop(); // if klass not in right area of memory it is broken too.
2505 #endif
2506 // return if everything seems ok
2507 bind(exit);
2509 jr(RA);
2510 delayed()->nop();
2512 // handle errors
2513 bind(error);
2514 pushad();
2515 #ifndef _LP64
2516 addi(SP, SP, (-1) * wordSize);
2517 #endif
2518 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
2519 delayed()->nop();
2520 #ifndef _LP64
2521 addiu(SP, SP, 1 * wordSize);
2522 #endif
2523 popad();
2524 jr(RA);
2525 delayed()->nop();
2526 }
2528 void MacroAssembler::verify_tlab(Register t1, Register t2) {
2529 #ifdef ASSERT
2530 assert_different_registers(t1, t2, AT);
2531 if (UseTLAB && VerifyOops) {
2532 Label next, ok;
2534 get_thread(t1);
2536 ld_ptr(t2, t1, in_bytes(JavaThread::tlab_top_offset()));
2537 ld_ptr(AT, t1, in_bytes(JavaThread::tlab_start_offset()));
2538 sltu(AT, t2, AT);
2539 beq(AT, R0, next);
2540 delayed()->nop();
2542 stop("assert(top >= start)");
2544 bind(next);
2545 ld_ptr(AT, t1, in_bytes(JavaThread::tlab_end_offset()));
2546 sltu(AT, AT, t2);
2547 beq(AT, R0, ok);
2548 delayed()->nop();
2550 stop("assert(top <= end)");
2552 bind(ok);
2554 }
2555 #endif
2556 }
2557 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2558 Register tmp,
2559 int offset) {
2560 intptr_t value = *delayed_value_addr;
2561 if (value != 0)
2562 return RegisterOrConstant(value + offset);
2563 AddressLiteral a(delayed_value_addr);
2564 // load indirectly to solve generation ordering problem
2565 //movptr(tmp, ExternalAddress((address) delayed_value_addr));
2566 //ld(tmp, a);
2567 if (offset != 0)
2568 daddi(tmp,tmp, offset);
2570 return RegisterOrConstant(tmp);
2571 }
2573 void MacroAssembler::hswap(Register reg) {
2574 //short
2575 //andi(reg, reg, 0xffff);
2576 srl(AT, reg, 8);
2577 sll(reg, reg, 24);
2578 sra(reg, reg, 16);
2579 orr(reg, reg, AT);
2580 }
2582 void MacroAssembler::huswap(Register reg) {
2583 #ifdef _LP64
2584 dsrl(AT, reg, 8);
2585 dsll(reg, reg, 24);
2586 dsrl(reg, reg, 16);
2587 orr(reg, reg, AT);
2588 andi(reg, reg, 0xffff);
2589 #else
2590 //andi(reg, reg, 0xffff);
2591 srl(AT, reg, 8);
2592 sll(reg, reg, 24);
2593 srl(reg, reg, 16);
2594 orr(reg, reg, AT);
2595 #endif
2596 }
2598 // something funny to do this will only one more register AT
2599 // 32 bits
2600 void MacroAssembler::swap(Register reg) {
2601 srl(AT, reg, 8);
2602 sll(reg, reg, 24);
2603 orr(reg, reg, AT);
2604 //reg : 4 1 2 3
2605 srl(AT, AT, 16);
2606 xorr(AT, AT, reg);
2607 andi(AT, AT, 0xff);
2608 //AT : 0 0 0 1^3);
2609 xorr(reg, reg, AT);
2610 //reg : 4 1 2 1
2611 sll(AT, AT, 16);
2612 xorr(reg, reg, AT);
2613 //reg : 4 3 2 1
2614 }
2616 #ifdef _LP64
2618 /* do 32-bit CAS using MIPS64 lld/scd
2620 cas_int should only compare 32-bits of the memory value.
2621 However, lld/scd will do 64-bit operation, which violates the intention of cas_int.
2622 To simulate a 32-bit atomic operation, the value loaded with LLD should be split into
2623 tow halves, and only the low-32 bits is compared. If equals, the low-32 bits of newval,
2624 plus the high-32 bits or memory value, are stored togethor with SCD.
2626 Example:
2628 double d = 3.1415926;
2629 System.err.println("hello" + d);
2631 sun.misc.FloatingDecimal$1.<init>()
2632 |
2633 `- java.util.concurrent.atomic.AtomicInteger::compareAndSet()
2635 38 cas_int [a7a7|J] [a0|I] [a6|I]
2636 // a0: 0xffffffffe8ea9f63 pc: 0x55647f3354
2637 // a6: 0x4ab325aa
2639 again:
2640 0x00000055647f3c5c: lld at, 0x0(a7) ; 64-bit load, "0xe8ea9f63"
2642 0x00000055647f3c60: sll t9, at, 0 ; t9: low-32 bits (sign extended)
2643 0x00000055647f3c64: dsrl32 t8, at, 0 ; t8: high-32 bits
2644 0x00000055647f3c68: dsll32 t8, t8, 0
2645 0x00000055647f3c6c: bne t9, a0, 0x00000055647f3c9c ; goto nequal
2646 0x00000055647f3c70: sll zero, zero, 0
2648 0x00000055647f3c74: ori v1, zero, 0xffffffff ; v1: low-32 bits of newval (sign unextended)
2649 0x00000055647f3c78: dsll v1, v1, 16 ; v1 = a6 & 0xFFFFFFFF;
2650 0x00000055647f3c7c: ori v1, v1, 0xffffffff
2651 0x00000055647f3c80: and v1, a6, v1
2652 0x00000055647f3c84: or at, t8, v1
2653 0x00000055647f3c88: scd at, 0x0(a7)
2654 0x00000055647f3c8c: beq at, zero, 0x00000055647f3c5c ; goto again
2655 0x00000055647f3c90: sll zero, zero, 0
2656 0x00000055647f3c94: beq zero, zero, 0x00000055647f45ac ; goto done
2657 0x00000055647f3c98: sll zero, zero, 0
2658 nequal:
2659 0x00000055647f45a4: dadd a0, t9, zero
2660 0x00000055647f45a8: dadd at, zero, zero
2661 done:
2662 */
2664 void MacroAssembler::cmpxchg32(Register x_reg, Address dest, Register c_reg) {
2665 /* MIPS64 can use ll/sc for 32-bit atomic memory access */
2666 Label done, again, nequal;
2668 bind(again);
2670 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
2671 ll(AT, dest);
2672 bne(AT, c_reg, nequal);
2673 delayed()->nop();
2675 move(AT, x_reg);
2676 sc(AT, dest);
2677 beq(AT, R0, again);
2678 delayed()->nop();
2679 b(done);
2680 delayed()->nop();
2682 // not xchged
2683 bind(nequal);
2684 sync();
2685 move(c_reg, AT);
2686 move(AT, R0);
2688 bind(done);
2689 }
2690 #endif // cmpxchg32
2692 void MacroAssembler::cmpxchg(Register x_reg, Address dest, Register c_reg) {
2693 Label done, again, nequal;
2695 bind(again);
2696 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
2697 #ifdef _LP64
2698 lld(AT, dest);
2699 #else
2700 ll(AT, dest);
2701 #endif
2702 bne(AT, c_reg, nequal);
2703 delayed()->nop();
2705 move(AT, x_reg);
2706 #ifdef _LP64
2707 scd(AT, dest);
2708 #else
2709 sc(AT, dest);
2710 #endif
2711 beq(AT, R0, again);
2712 delayed()->nop();
2713 b(done);
2714 delayed()->nop();
2716 // not xchged
2717 bind(nequal);
2718 sync();
2719 move(c_reg, AT);
2720 move(AT, R0);
2722 bind(done);
2723 }
2725 void MacroAssembler::cmpxchg8(Register x_regLo, Register x_regHi, Address dest, Register c_regLo, Register c_regHi) {
2726 Label done, again, nequal;
2728 Register x_reg = x_regLo;
2729 dsll32(x_regHi, x_regHi, 0);
2730 dsll32(x_regLo, x_regLo, 0);
2731 dsrl32(x_regLo, x_regLo, 0);
2732 orr(x_reg, x_regLo, x_regHi);
2734 Register c_reg = c_regLo;
2735 dsll32(c_regHi, c_regHi, 0);
2736 dsll32(c_regLo, c_regLo, 0);
2737 dsrl32(c_regLo, c_regLo, 0);
2738 orr(c_reg, c_regLo, c_regHi);
2740 bind(again);
2742 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
2743 lld(AT, dest);
2744 bne(AT, c_reg, nequal);
2745 delayed()->nop();
2747 //move(AT, x_reg);
2748 dadd(AT, x_reg, R0);
2749 scd(AT, dest);
2750 beq(AT, R0, again);
2751 delayed()->nop();
2752 b(done);
2753 delayed()->nop();
2755 // not xchged
2756 bind(nequal);
2757 sync();
2758 //move(c_reg, AT);
2759 //move(AT, R0);
2760 dadd(c_reg, AT, R0);
2761 dadd(AT, R0, R0);
2762 bind(done);
2763 }
2765 // be sure the three register is different
2766 void MacroAssembler::rem_s(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
2767 assert_different_registers(tmp, fs, ft);
2768 div_s(tmp, fs, ft);
2769 trunc_l_s(tmp, tmp);
2770 cvt_s_l(tmp, tmp);
2771 mul_s(tmp, tmp, ft);
2772 sub_s(fd, fs, tmp);
2773 }
2775 // be sure the three register is different
2776 void MacroAssembler::rem_d(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
2777 assert_different_registers(tmp, fs, ft);
2778 div_d(tmp, fs, ft);
2779 trunc_l_d(tmp, tmp);
2780 cvt_d_l(tmp, tmp);
2781 mul_d(tmp, tmp, ft);
2782 sub_d(fd, fs, tmp);
2783 }
2785 // Fast_Lock and Fast_Unlock used by C2
2787 // Because the transitions from emitted code to the runtime
2788 // monitorenter/exit helper stubs are so slow it's critical that
2789 // we inline both the stack-locking fast-path and the inflated fast path.
2790 //
2791 // See also: cmpFastLock and cmpFastUnlock.
2792 //
2793 // What follows is a specialized inline transliteration of the code
2794 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2795 // another option would be to emit TrySlowEnter and TrySlowExit methods
2796 // at startup-time. These methods would accept arguments as
2797 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2798 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2799 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2800 // In practice, however, the # of lock sites is bounded and is usually small.
2801 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2802 // if the processor uses simple bimodal branch predictors keyed by EIP
2803 // Since the helper routines would be called from multiple synchronization
2804 // sites.
2805 //
2806 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2807 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2808 // to those specialized methods. That'd give us a mostly platform-independent
2809 // implementation that the JITs could optimize and inline at their pleasure.
2810 // Done correctly, the only time we'd need to cross to native could would be
2811 // to park() or unpark() threads. We'd also need a few more unsafe operators
2812 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2813 // (b) explicit barriers or fence operations.
2814 //
2815 // TODO:
2816 //
2817 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2818 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2819 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2820 // the lock operators would typically be faster than reifying Self.
2821 //
2822 // * Ideally I'd define the primitives as:
2823 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2824 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2825 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2826 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2827 // Furthermore the register assignments are overconstrained, possibly resulting in
2828 // sub-optimal code near the synchronization site.
2829 //
2830 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2831 // Alternately, use a better sp-proximity test.
2832 //
2833 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2834 // Either one is sufficient to uniquely identify a thread.
2835 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2836 //
2837 // * Intrinsify notify() and notifyAll() for the common cases where the
2838 // object is locked by the calling thread but the waitlist is empty.
2839 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2840 //
2841 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2842 // But beware of excessive branch density on AMD Opterons.
2843 //
2844 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2845 // or failure of the fast-path. If the fast-path fails then we pass
2846 // control to the slow-path, typically in C. In Fast_Lock and
2847 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2848 // will emit a conditional branch immediately after the node.
2849 // So we have branches to branches and lots of ICC.ZF games.
2850 // Instead, it might be better to have C2 pass a "FailureLabel"
2851 // into Fast_Lock and Fast_Unlock. In the case of success, control
2852 // will drop through the node. ICC.ZF is undefined at exit.
2853 // In the case of failure, the node will branch directly to the
2854 // FailureLabel
2857 // obj: object to lock
2858 // box: on-stack box address (displaced header location) - KILLED
2859 // rax,: tmp -- KILLED
2860 // scr: tmp -- KILLED
2861 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, Register scrReg) {
2863 // Ensure the register assignents are disjoint
2864 guarantee (objReg != boxReg, "") ;
2865 guarantee (objReg != tmpReg, "") ;
2866 guarantee (objReg != scrReg, "") ;
2867 guarantee (boxReg != tmpReg, "") ;
2868 guarantee (boxReg != scrReg, "") ;
2871 block_comment("FastLock");
2872 /*
2873 move(AT, 0x0);
2874 return;
2875 */
2876 if (PrintBiasedLockingStatistics) {
2877 push(tmpReg);
2878 atomic_inc32((address)BiasedLocking::total_entry_count_addr(), 1, AT, tmpReg);
2879 pop(tmpReg);
2880 }
2882 if (EmitSync & 1) {
2883 move(AT, 0x0);
2884 return;
2885 } else
2886 if (EmitSync & 2) {
2887 Label DONE_LABEL ;
2888 if (UseBiasedLocking) {
2889 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2890 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL);
2891 }
2893 ld(tmpReg, Address(objReg, 0)) ; // fetch markword
2894 ori(tmpReg, tmpReg, 0x1);
2895 sd(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS
2897 cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg
2898 bne(AT, R0, DONE_LABEL);
2899 delayed()->nop();
2901 // Recursive locking
2902 dsubu(tmpReg, tmpReg, SP);
2903 li(AT, (7 - os::vm_page_size() ));
2904 andr(tmpReg, tmpReg, AT);
2905 sd(tmpReg, Address(boxReg, 0));
2906 bind(DONE_LABEL) ;
2907 } else {
2908 // Possible cases that we'll encounter in fast_lock
2909 // ------------------------------------------------
2910 // * Inflated
2911 // -- unlocked
2912 // -- Locked
2913 // = by self
2914 // = by other
2915 // * biased
2916 // -- by Self
2917 // -- by other
2918 // * neutral
2919 // * stack-locked
2920 // -- by self
2921 // = sp-proximity test hits
2922 // = sp-proximity test generates false-negative
2923 // -- by other
2924 //
2926 Label IsInflated, DONE_LABEL, PopDone ;
2928 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
2929 // order to reduce the number of conditional branches in the most common cases.
2930 // Beware -- there's a subtle invariant that fetch of the markword
2931 // at [FETCH], below, will never observe a biased encoding (*101b).
2932 // If this invariant is not held we risk exclusion (safety) failure.
2933 if (UseBiasedLocking && !UseOptoBiasInlining) {
2934 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL);
2935 }
2937 ld(tmpReg, Address(objReg, 0)) ; //Fetch the markword of the object.
2938 andi(AT, tmpReg, markOopDesc::monitor_value);
2939 bne(AT, R0, IsInflated); // inflated vs stack-locked|neutral|bias
2940 delayed()->nop();
2942 // Attempt stack-locking ...
2943 ori (tmpReg, tmpReg, markOopDesc::unlocked_value);
2944 sd(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS
2945 //if (os::is_MP()) {
2946 // sync();
2947 //}
2949 cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg
2950 //AT == 1: unlocked
2952 if (PrintBiasedLockingStatistics) {
2953 Label L;
2954 beq(AT, R0, L);
2955 delayed()->nop();
2956 push(T0);
2957 push(T1);
2958 atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1);
2959 pop(T1);
2960 pop(T0);
2961 bind(L);
2962 }
2963 bne(AT, R0, DONE_LABEL);
2964 delayed()->nop();
2966 // Recursive locking
2967 // The object is stack-locked: markword contains stack pointer to BasicLock.
2968 // Locked by current thread if difference with current SP is less than one page.
2969 dsubu(tmpReg, tmpReg, SP);
2970 li(AT, 7 - os::vm_page_size() );
2971 andr(tmpReg, tmpReg, AT);
2972 sd(tmpReg, Address(boxReg, 0));
2973 if (PrintBiasedLockingStatistics) {
2974 Label L;
2975 // tmpReg == 0 => BiasedLocking::_fast_path_entry_count++
2976 bne(tmpReg, R0, L);
2977 delayed()->nop();
2978 push(T0);
2979 push(T1);
2980 atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1);
2981 pop(T1);
2982 pop(T0);
2983 bind(L);
2984 }
2985 sltiu(AT, tmpReg, 1); /* AT = (tmpReg == 0) ? 1 : 0 */
2987 b(DONE_LABEL) ;
2988 delayed()->nop();
2990 bind(IsInflated) ;
2991 // The object's monitor m is unlocked iff m->owner == NULL,
2992 // otherwise m->owner may contain a thread or a stack address.
2994 // TODO: someday avoid the ST-before-CAS penalty by
2995 // relocating (deferring) the following ST.
2996 // We should also think about trying a CAS without having
2997 // fetched _owner. If the CAS is successful we may
2998 // avoid an RTO->RTS upgrade on the $line.
2999 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3000 li(AT, (int32_t)intptr_t(markOopDesc::unused_mark()));
3001 sd(AT, Address(boxReg, 0));
3003 move(boxReg, tmpReg) ;
3004 ld(tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3005 // if (m->owner != 0) => AT = 0, goto slow path.
3006 move(AT, R0);
3007 bne(tmpReg, R0, DONE_LABEL);
3008 delayed()->nop();
3010 #ifndef OPT_THREAD
3011 get_thread (TREG) ;
3012 #endif
3013 // It's inflated and appears unlocked
3014 //if (os::is_MP()) {
3015 // sync();
3016 //}
3017 cmpxchg(TREG, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), tmpReg) ;
3018 // Intentional fall-through into DONE_LABEL ...
3021 // DONE_LABEL is a hot target - we'd really like to place it at the
3022 // start of cache line by padding with NOPs.
3023 // See the AMD and Intel software optimization manuals for the
3024 // most efficient "long" NOP encodings.
3025 // Unfortunately none of our alignment mechanisms suffice.
3026 bind(DONE_LABEL);
3028 // At DONE_LABEL the AT is set as follows ...
3029 // Fast_Unlock uses the same protocol.
3030 // AT == 1 -> Success
3031 // AT == 0 -> Failure - force control through the slow-path
3033 // Avoid branch-to-branch on AMD processors
3034 // This appears to be superstition.
3035 if (EmitSync & 32) nop() ;
3037 }
3038 }
3040 // obj: object to unlock
3041 // box: box address (displaced header location), killed. Must be EAX.
3042 // rbx,: killed tmp; cannot be obj nor box.
3043 //
3044 // Some commentary on balanced locking:
3045 //
3046 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3047 // Methods that don't have provably balanced locking are forced to run in the
3048 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3049 // The interpreter provides two properties:
3050 // I1: At return-time the interpreter automatically and quietly unlocks any
3051 // objects acquired the current activation (frame). Recall that the
3052 // interpreter maintains an on-stack list of locks currently held by
3053 // a frame.
3054 // I2: If a method attempts to unlock an object that is not held by the
3055 // the frame the interpreter throws IMSX.
3056 //
3057 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3058 // B() doesn't have provably balanced locking so it runs in the interpreter.
3059 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3060 // is still locked by A().
3061 //
3062 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3063 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3064 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3065 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3067 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg) {
3069 guarantee (objReg != boxReg, "") ;
3070 guarantee (objReg != tmpReg, "") ;
3071 guarantee (boxReg != tmpReg, "") ;
3075 block_comment("FastUnlock");
3078 if (EmitSync & 4) {
3079 // Disable - inhibit all inlining. Force control through the slow-path
3080 move(AT, 0x0);
3081 return;
3082 } else
3083 if (EmitSync & 8) {
3084 Label DONE_LABEL ;
3085 if (UseBiasedLocking) {
3086 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3087 }
3088 // classic stack-locking code ...
3089 ld(tmpReg, Address(boxReg, 0)) ;
3090 beq(tmpReg, R0, DONE_LABEL) ;
3091 move(AT, 0x1); // delay slot
3093 cmpxchg(tmpReg, Address(objReg, 0), boxReg); // Uses EAX which is box
3094 bind(DONE_LABEL);
3095 } else {
3096 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3098 // Critically, the biased locking test must have precedence over
3099 // and appear before the (box->dhw == 0) recursive stack-lock test.
3100 if (UseBiasedLocking && !UseOptoBiasInlining) {
3101 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3102 }
3104 ld(AT, Address(boxReg, 0)) ; // Examine the displaced header
3105 beq(AT, R0, DONE_LABEL) ; // 0 indicates recursive stack-lock
3106 delayed()->daddiu(AT, R0, 0x1);
3108 ld(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3109 andi(AT, tmpReg, markOopDesc::monitor_value) ; // Inflated?
3110 beq(AT, R0, Stacked) ; // Inflated?
3111 delayed()->nop();
3113 bind(Inflated) ;
3114 // It's inflated.
3115 // Despite our balanced locking property we still check that m->_owner == Self
3116 // as java routines or native JNI code called by this thread might
3117 // have released the lock.
3118 // Refer to the comments in synchronizer.cpp for how we might encode extra
3119 // state in _succ so we can avoid fetching EntryList|cxq.
3120 //
3121 // I'd like to add more cases in fast_lock() and fast_unlock() --
3122 // such as recursive enter and exit -- but we have to be wary of
3123 // I$ bloat, T$ effects and BP$ effects.
3124 //
3125 // If there's no contention try a 1-0 exit. That is, exit without
3126 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3127 // we detect and recover from the race that the 1-0 exit admits.
3128 //
3129 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3130 // before it STs null into _owner, releasing the lock. Updates
3131 // to data protected by the critical section must be visible before
3132 // we drop the lock (and thus before any other thread could acquire
3133 // the lock and observe the fields protected by the lock).
3134 // IA32's memory-model is SPO, so STs are ordered with respect to
3135 // each other and there's no need for an explicit barrier (fence).
3136 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3137 #ifndef OPT_THREAD
3138 get_thread (TREG) ;
3139 #endif
3141 // It's inflated
3142 ld(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3143 xorr(boxReg, boxReg, TREG);
3145 ld(AT, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3146 orr(boxReg, boxReg, AT);
3148 move(AT, R0);
3149 bne(boxReg, R0, DONE_LABEL);
3150 delayed()->nop();
3152 ld(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3153 ld(AT, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3154 orr(boxReg, boxReg, AT);
3156 move(AT, R0);
3157 bne(boxReg, R0, DONE_LABEL);
3158 delayed()->nop();
3160 sync();
3161 sd(R0, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3162 move(AT, 0x1);
3163 b(DONE_LABEL);
3164 delayed()->nop();
3166 bind (Stacked);
3167 ld(tmpReg, Address(boxReg, 0)) ;
3168 //if (os::is_MP()) { sync(); }
3169 cmpxchg(tmpReg, Address(objReg, 0), boxReg);
3171 if (EmitSync & 65536) {
3172 bind (CheckSucc);
3173 }
3175 bind(DONE_LABEL);
3177 // Avoid branch to branch on AMD processors
3178 if (EmitSync & 32768) { nop() ; }
3179 }
3180 }
3182 void MacroAssembler::align(int modulus) {
3183 while (offset() % modulus != 0) nop();
3184 }
3187 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3188 //Unimplemented();
3189 }
3191 #ifdef _LP64
3192 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3193 Register caller_saved_registers_except_v0[] = {AT, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3195 //In MIPS64, F0~23 are all caller-saved registers
3196 FloatRegister caller_saved_fpu_registers[] = {F0, F12, F13};
3197 #else
3198 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, T4, T5, T6, T7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3199 Register caller_saved_registers_except_v0[] = {AT, V1, A0, A1, A2, A3, T4, T5, T6, T7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3201 Register caller_saved_fpu_registers[] = {};
3202 #endif
3204 //We preserve all caller-saved register
3205 void MacroAssembler::pushad(){
3206 int i;
3208 /* Fixed-point registers */
3209 int len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]);
3210 daddi(SP, SP, -1 * len * wordSize);
3211 for (i = 0; i < len; i++)
3212 {
3213 #ifdef _LP64
3214 sd(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3215 #else
3216 sw(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3217 #endif
3218 }
3220 /* Floating-point registers */
3221 len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3222 daddi(SP, SP, -1 * len * wordSize);
3223 for (i = 0; i < len; i++)
3224 {
3225 #ifdef _LP64
3226 sdc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3227 #else
3228 swc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3229 #endif
3230 }
3231 };
3233 void MacroAssembler::popad(){
3234 int i;
3236 /* Floating-point registers */
3237 int len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3238 for (i = 0; i < len; i++)
3239 {
3240 #ifdef _LP64
3241 ldc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3242 #else
3243 lwc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3244 #endif
3245 }
3246 daddi(SP, SP, len * wordSize);
3248 /* Fixed-point registers */
3249 len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]);
3250 for (i = 0; i < len; i++)
3251 {
3252 #ifdef _LP64
3253 ld(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3254 #else
3255 lw(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3256 #endif
3257 }
3258 daddi(SP, SP, len * wordSize);
3259 };
3261 // We preserve all caller-saved register except V0
3262 void MacroAssembler::pushad_except_v0() {
3263 int i;
3265 /* Fixed-point registers */
3266 int len = sizeof(caller_saved_registers_except_v0) / sizeof(caller_saved_registers_except_v0[0]);
3267 daddi(SP, SP, -1 * len * wordSize);
3268 for (i = 0; i < len; i++) {
3269 #ifdef _LP64
3270 sd(caller_saved_registers_except_v0[i], SP, (len - i - 1) * wordSize);
3271 #else
3272 sw(caller_saved_registers_except_v0[i], SP, (len - i - 1) * wordSize);
3273 #endif
3274 }
3276 /* Floating-point registers */
3277 len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3278 daddi(SP, SP, -1 * len * wordSize);
3279 for (i = 0; i < len; i++) {
3280 #ifdef _LP64
3281 sdc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3282 #else
3283 swc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3284 #endif
3285 }
3286 }
3288 void MacroAssembler::popad_except_v0() {
3289 int i;
3291 /* Floating-point registers */
3292 int len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3293 for (i = 0; i < len; i++) {
3294 #ifdef _LP64
3295 ldc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3296 #else
3297 lwc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3298 #endif
3299 }
3300 daddi(SP, SP, len * wordSize);
3302 /* Fixed-point registers */
3303 len = sizeof(caller_saved_registers_except_v0) / sizeof(caller_saved_registers_except_v0[0]);
3304 for (i = 0; i < len; i++) {
3305 #ifdef _LP64
3306 ld(caller_saved_registers_except_v0[i], SP, (len - i - 1) * wordSize);
3307 #else
3308 lw(caller_saved_registers_except_v0[i], SP, (len - i - 1) * wordSize);
3309 #endif
3310 }
3311 daddi(SP, SP, len * wordSize);
3312 }
3314 void MacroAssembler::push2(Register reg1, Register reg2) {
3315 #ifdef _LP64
3316 daddi(SP, SP, -16);
3317 sd(reg2, SP, 0);
3318 sd(reg1, SP, 8);
3319 #else
3320 addi(SP, SP, -8);
3321 sw(reg2, SP, 0);
3322 sw(reg1, SP, 4);
3323 #endif
3324 }
3326 void MacroAssembler::pop2(Register reg1, Register reg2) {
3327 #ifdef _LP64
3328 ld(reg1, SP, 0);
3329 ld(reg2, SP, 8);
3330 daddi(SP, SP, 16);
3331 #else
3332 lw(reg1, SP, 0);
3333 lw(reg2, SP, 4);
3334 addi(SP, SP, 8);
3335 #endif
3336 }
3338 //for UseCompressedOops Option
3339 void MacroAssembler::load_klass(Register dst, Register src) {
3340 #ifdef _LP64
3341 if(UseCompressedClassPointers){
3342 lwu(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3343 decode_klass_not_null(dst);
3344 } else
3345 #endif
3346 ld(dst, src, oopDesc::klass_offset_in_bytes());
3347 }
3349 void MacroAssembler::store_klass(Register dst, Register src) {
3350 #ifdef _LP64
3351 if(UseCompressedClassPointers){
3352 encode_klass_not_null(src);
3353 sw(src, dst, oopDesc::klass_offset_in_bytes());
3354 } else {
3355 #endif
3356 sd(src, dst, oopDesc::klass_offset_in_bytes());
3357 }
3358 }
3360 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3361 load_klass(dst, src);
3362 ld(dst, Address(dst, Klass::prototype_header_offset()));
3363 }
3365 #ifdef _LP64
3366 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3367 if (UseCompressedClassPointers) {
3368 sw(src, dst, oopDesc::klass_gap_offset_in_bytes());
3369 }
3370 }
3372 void MacroAssembler::load_heap_oop(Register dst, Address src) {
3373 if(UseCompressedOops){
3374 lwu(dst, src);
3375 decode_heap_oop(dst);
3376 } else {
3377 ld(dst, src);
3378 }
3379 }
3381 void MacroAssembler::store_heap_oop(Address dst, Register src){
3382 if(UseCompressedOops){
3383 assert(!dst.uses(src), "not enough registers");
3384 encode_heap_oop(src);
3385 sw(src, dst);
3386 } else {
3387 sd(src, dst);
3388 }
3389 }
3391 void MacroAssembler::store_heap_oop_null(Address dst){
3392 if(UseCompressedOops){
3393 sw(R0, dst);
3394 } else {
3395 sd(R0, dst);
3396 }
3397 }
3399 #ifdef ASSERT
3400 void MacroAssembler::verify_heapbase(const char* msg) {
3401 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3402 assert (Universe::heap() != NULL, "java heap should be initialized");
3403 }
3404 #endif
3407 // Algorithm must match oop.inline.hpp encode_heap_oop.
3408 void MacroAssembler::encode_heap_oop(Register r) {
3409 #ifdef ASSERT
3410 verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?");
3411 #endif
3412 verify_oop(r, "broken oop in encode_heap_oop");
3413 if (Universe::narrow_oop_base() == NULL) {
3414 if (Universe::narrow_oop_shift() != 0) {
3415 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3416 shr(r, LogMinObjAlignmentInBytes);
3417 }
3418 return;
3419 }
3421 movz(r, S5_heapbase, r);
3422 dsub(r, r, S5_heapbase);
3423 if (Universe::narrow_oop_shift() != 0) {
3424 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3425 shr(r, LogMinObjAlignmentInBytes);
3426 }
3427 }
3429 void MacroAssembler::encode_heap_oop(Register dst, Register src) {
3430 #ifdef ASSERT
3431 verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?");
3432 #endif
3433 verify_oop(src, "broken oop in encode_heap_oop");
3434 if (Universe::narrow_oop_base() == NULL) {
3435 if (Universe::narrow_oop_shift() != 0) {
3436 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3437 dsrl(dst, src, LogMinObjAlignmentInBytes);
3438 } else {
3439 if (dst != src) move(dst, src);
3440 }
3441 } else {
3442 if (dst == src) {
3443 movz(dst, S5_heapbase, dst);
3444 dsub(dst, dst, S5_heapbase);
3445 if (Universe::narrow_oop_shift() != 0) {
3446 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3447 shr(dst, LogMinObjAlignmentInBytes);
3448 }
3449 } else {
3450 dsub(dst, src, S5_heapbase);
3451 if (Universe::narrow_oop_shift() != 0) {
3452 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3453 shr(dst, LogMinObjAlignmentInBytes);
3454 }
3455 movz(dst, R0, src);
3456 }
3457 }
3458 }
3460 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3461 assert (UseCompressedOops, "should be compressed");
3462 #ifdef ASSERT
3463 if (CheckCompressedOops) {
3464 Label ok;
3465 bne(r, R0, ok);
3466 delayed()->nop();
3467 stop("null oop passed to encode_heap_oop_not_null");
3468 bind(ok);
3469 }
3470 #endif
3471 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3472 if (Universe::narrow_oop_base() != NULL) {
3473 dsub(r, r, S5_heapbase);
3474 }
3475 if (Universe::narrow_oop_shift() != 0) {
3476 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3477 shr(r, LogMinObjAlignmentInBytes);
3478 }
3480 }
3482 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3483 assert (UseCompressedOops, "should be compressed");
3484 #ifdef ASSERT
3485 if (CheckCompressedOops) {
3486 Label ok;
3487 bne(src, R0, ok);
3488 delayed()->nop();
3489 stop("null oop passed to encode_heap_oop_not_null2");
3490 bind(ok);
3491 }
3492 #endif
3493 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3495 if (Universe::narrow_oop_base() != NULL) {
3496 dsub(dst, src, S5_heapbase);
3497 if (Universe::narrow_oop_shift() != 0) {
3498 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3499 shr(dst, LogMinObjAlignmentInBytes);
3500 }
3501 } else {
3502 if (Universe::narrow_oop_shift() != 0) {
3503 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3504 dsrl(dst, src, LogMinObjAlignmentInBytes);
3505 } else {
3506 if (dst != src) move(dst, src);
3507 }
3508 }
3509 }
3511 void MacroAssembler::decode_heap_oop(Register r) {
3512 #ifdef ASSERT
3513 verify_heapbase("MacroAssembler::decode_heap_oop corrupted?");
3514 #endif
3515 if (Universe::narrow_oop_base() == NULL) {
3516 if (Universe::narrow_oop_shift() != 0) {
3517 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3518 shl(r, LogMinObjAlignmentInBytes);
3519 }
3520 } else {
3521 move(AT, r);
3522 if (Universe::narrow_oop_shift() != 0) {
3523 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3524 shl(r, LogMinObjAlignmentInBytes);
3525 }
3526 dadd(r, r, S5_heapbase);
3527 movz(r, R0, AT);
3528 }
3529 verify_oop(r, "broken oop in decode_heap_oop");
3530 }
3532 void MacroAssembler::decode_heap_oop(Register dst, Register src) {
3533 #ifdef ASSERT
3534 verify_heapbase("MacroAssembler::decode_heap_oop corrupted?");
3535 #endif
3536 if (Universe::narrow_oop_base() == NULL) {
3537 if (Universe::narrow_oop_shift() != 0) {
3538 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3539 if (dst != src) nop(); // DON'T DELETE THIS GUY.
3540 dsll(dst, src, LogMinObjAlignmentInBytes);
3541 } else {
3542 if (dst != src) move(dst, src);
3543 }
3544 } else {
3545 if (dst == src) {
3546 move(AT, dst);
3547 if (Universe::narrow_oop_shift() != 0) {
3548 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3549 shl(dst, LogMinObjAlignmentInBytes);
3550 }
3551 dadd(dst, dst, S5_heapbase);
3552 movz(dst, R0, AT);
3553 } else {
3554 if (Universe::narrow_oop_shift() != 0) {
3555 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3556 dsll(dst, src, LogMinObjAlignmentInBytes);
3557 daddu(dst, dst, S5_heapbase);
3558 } else {
3559 daddu(dst, src, S5_heapbase);
3560 }
3561 movz(dst, R0, src);
3562 }
3563 }
3564 verify_oop(dst, "broken oop in decode_heap_oop");
3565 }
3567 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3568 // Note: it will change flags
3569 assert (UseCompressedOops, "should only be used for compressed headers");
3570 assert (Universe::heap() != NULL, "java heap should be initialized");
3571 // Cannot assert, unverified entry point counts instructions (see .ad file)
3572 // vtableStubs also counts instructions in pd_code_size_limit.
3573 // Also do not verify_oop as this is called by verify_oop.
3574 if (Universe::narrow_oop_shift() != 0) {
3575 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3576 shl(r, LogMinObjAlignmentInBytes);
3577 if (Universe::narrow_oop_base() != NULL) {
3578 daddu(r, r, S5_heapbase);
3579 }
3580 } else {
3581 assert (Universe::narrow_oop_base() == NULL, "sanity");
3582 }
3583 }
3585 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3586 assert (UseCompressedOops, "should only be used for compressed headers");
3587 assert (Universe::heap() != NULL, "java heap should be initialized");
3589 // Cannot assert, unverified entry point counts instructions (see .ad file)
3590 // vtableStubs also counts instructions in pd_code_size_limit.
3591 // Also do not verify_oop as this is called by verify_oop.
3592 //lea(dst, Address(S5_heapbase, src, Address::times_8, 0));
3593 if (Universe::narrow_oop_shift() != 0) {
3594 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3595 if (LogMinObjAlignmentInBytes == Address::times_8) {
3596 dsll(dst, src, LogMinObjAlignmentInBytes);
3597 daddu(dst, dst, S5_heapbase);
3598 } else {
3599 dsll(dst, src, LogMinObjAlignmentInBytes);
3600 if (Universe::narrow_oop_base() != NULL) {
3601 daddu(dst, dst, S5_heapbase);
3602 }
3603 }
3604 } else {
3605 assert (Universe::narrow_oop_base() == NULL, "sanity");
3606 if (dst != src) {
3607 move(dst, src);
3608 }
3609 }
3610 }
3612 void MacroAssembler::encode_klass_not_null(Register r) {
3613 if (Universe::narrow_klass_base() != NULL) {
3614 assert(r != AT, "Encoding a klass in AT");
3615 set64(AT, (int64_t)Universe::narrow_klass_base());
3616 dsub(r, r, AT);
3617 }
3618 if (Universe::narrow_klass_shift() != 0) {
3619 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3620 shr(r, LogKlassAlignmentInBytes);
3621 }
3622 }
3624 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3625 if (dst == src) {
3626 encode_klass_not_null(src);
3627 } else {
3628 if (Universe::narrow_klass_base() != NULL) {
3629 set64(dst, (int64_t)Universe::narrow_klass_base());
3630 dsub(dst, src, dst);
3631 if (Universe::narrow_klass_shift() != 0) {
3632 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3633 shr(dst, LogKlassAlignmentInBytes);
3634 }
3635 } else {
3636 if (Universe::narrow_klass_shift() != 0) {
3637 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3638 dsrl(dst, src, LogKlassAlignmentInBytes);
3639 } else {
3640 move(dst, src);
3641 }
3642 }
3643 }
3644 }
3646 // Function instr_size_for_decode_klass_not_null() counts the instructions
3647 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
3648 // when (Universe::heap() != NULL). Hence, if the instructions they
3649 // generate change, then this method needs to be updated.
3650 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3651 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
3652 if (Universe::narrow_klass_base() != NULL) {
3653 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
3654 return (Universe::narrow_klass_shift() == 0 ? 4 * 9 : 4 * 10);
3655 } else {
3656 // longest load decode klass function, mov64, leaq
3657 return (Universe::narrow_klass_shift() == 0 ? 4 * 0 : 4 * 1);
3658 }
3659 }
3661 void MacroAssembler::decode_klass_not_null(Register r) {
3662 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3663 assert(r != AT, "Decoding a klass in AT");
3664 // Cannot assert, unverified entry point counts instructions (see .ad file)
3665 // vtableStubs also counts instructions in pd_code_size_limit.
3666 // Also do not verify_oop as this is called by verify_oop.
3667 if (Universe::narrow_klass_shift() != 0) {
3668 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3669 shl(r, LogKlassAlignmentInBytes);
3670 }
3671 if (Universe::narrow_klass_base() != NULL) {
3672 set64(AT, (int64_t)Universe::narrow_klass_base());
3673 daddu(r, r, AT);
3674 //Not neccessary for MIPS at all.
3675 //reinit_heapbase();
3676 }
3677 }
3679 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3680 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3682 if (dst == src) {
3683 decode_klass_not_null(dst);
3684 } else {
3685 // Cannot assert, unverified entry point counts instructions (see .ad file)
3686 // vtableStubs also counts instructions in pd_code_size_limit.
3687 // Also do not verify_oop as this is called by verify_oop.
3688 set64(dst, (int64_t)Universe::narrow_klass_base());
3689 if (Universe::narrow_klass_shift() != 0) {
3690 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3691 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
3692 dsll(AT, src, Address::times_8);
3693 daddu(dst, dst, AT);
3694 } else {
3695 daddu(dst, src, dst);
3696 }
3697 }
3698 }
3700 void MacroAssembler::incrementl(Register reg, int value) {
3701 if (value == min_jint) {
3702 move(AT, value);
3703 LP64_ONLY(addu32(reg, reg, AT)) NOT_LP64(addu(reg, reg, AT));
3704 return;
3705 }
3706 if (value < 0) { decrementl(reg, -value); return; }
3707 if (value == 0) { ; return; }
3709 if(Assembler::is_simm16(value)) {
3710 NOT_LP64(addiu(reg, reg, value));
3711 LP64_ONLY(move(AT, value); addu32(reg, reg, AT));
3712 } else {
3713 move(AT, value);
3714 LP64_ONLY(addu32(reg, reg, AT)) NOT_LP64(addu(reg, reg, AT));
3715 }
3716 }
3718 void MacroAssembler::decrementl(Register reg, int value) {
3719 if (value == min_jint) {
3720 move(AT, value);
3721 LP64_ONLY(subu32(reg, reg, AT)) NOT_LP64(subu(reg, reg, AT));
3722 return;
3723 }
3724 if (value < 0) { incrementl(reg, -value); return; }
3725 if (value == 0) { ; return; }
3727 if (Assembler::is_simm16(value)) {
3728 NOT_LP64(addiu(reg, reg, -value));
3729 LP64_ONLY(move(AT, value); subu32(reg, reg, AT));
3730 } else {
3731 move(AT, value);
3732 LP64_ONLY(subu32(reg, reg, AT)) NOT_LP64(subu(reg, reg, AT));
3733 }
3734 }
3736 void MacroAssembler::reinit_heapbase() {
3737 if (UseCompressedOops || UseCompressedClassPointers) {
3738 if (Universe::heap() != NULL) {
3739 if (Universe::narrow_oop_base() == NULL) {
3740 move(S5_heapbase, R0);
3741 } else {
3742 set64(S5_heapbase, (int64_t)Universe::narrow_ptrs_base());
3743 }
3744 } else {
3745 set64(S5_heapbase, (intptr_t)Universe::narrow_ptrs_base_addr());
3746 ld(S5_heapbase, S5_heapbase, 0);
3747 }
3748 }
3749 }
3750 #endif // _LP64
3752 void MacroAssembler::check_klass_subtype(Register sub_klass,
3753 Register super_klass,
3754 Register temp_reg,
3755 Label& L_success) {
3756 //implement ind gen_subtype_check
3757 Label L_failure;
3758 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
3759 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3760 bind(L_failure);
3761 }
3763 SkipIfEqual::SkipIfEqual(
3764 MacroAssembler* masm, const bool* flag_addr, bool value) {
3765 _masm = masm;
3766 _masm->li(AT, (address)flag_addr);
3767 _masm->lb(AT,AT,0);
3768 _masm->addi(AT,AT,-value);
3769 _masm->beq(AT,R0,_label);
3770 _masm->delayed()->nop();
3771 }
3772 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3773 Register super_klass,
3774 Register temp_reg,
3775 Label* L_success,
3776 Label* L_failure,
3777 Label* L_slow_path,
3778 RegisterOrConstant super_check_offset) {
3779 assert_different_registers(sub_klass, super_klass, temp_reg);
3780 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3781 if (super_check_offset.is_register()) {
3782 assert_different_registers(sub_klass, super_klass,
3783 super_check_offset.as_register());
3784 } else if (must_load_sco) {
3785 assert(temp_reg != noreg, "supply either a temp or a register offset");
3786 }
3788 Label L_fallthrough;
3789 int label_nulls = 0;
3790 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3791 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3792 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3793 assert(label_nulls <= 1, "at most one NULL in the batch");
3795 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3796 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3797 // If the pointers are equal, we are done (e.g., String[] elements).
3798 // This self-check enables sharing of secondary supertype arrays among
3799 // non-primary types such as array-of-interface. Otherwise, each such
3800 // type would need its own customized SSA.
3801 // We move this check to the front of the fast path because many
3802 // type checks are in fact trivially successful in this manner,
3803 // so we get a nicely predicted branch right at the start of the check.
3804 beq(sub_klass, super_klass, *L_success);
3805 delayed()->nop();
3806 // Check the supertype display:
3807 if (must_load_sco) {
3808 // Positive movl does right thing on LP64.
3809 lwu(temp_reg, super_klass, sco_offset);
3810 super_check_offset = RegisterOrConstant(temp_reg);
3811 }
3812 dsll(AT, super_check_offset.register_or_noreg(), Address::times_1);
3813 daddu(AT, sub_klass, AT);
3814 ld(AT, AT, super_check_offset.constant_or_zero()*Address::times_1);
3816 // This check has worked decisively for primary supers.
3817 // Secondary supers are sought in the super_cache ('super_cache_addr').
3818 // (Secondary supers are interfaces and very deeply nested subtypes.)
3819 // This works in the same check above because of a tricky aliasing
3820 // between the super_cache and the primary super display elements.
3821 // (The 'super_check_addr' can address either, as the case requires.)
3822 // Note that the cache is updated below if it does not help us find
3823 // what we need immediately.
3824 // So if it was a primary super, we can just fail immediately.
3825 // Otherwise, it's the slow path for us (no success at this point).
3827 if (super_check_offset.is_register()) {
3828 beq(super_klass, AT, *L_success);
3829 delayed()->nop();
3830 addi(AT, super_check_offset.as_register(), -sc_offset);
3831 if (L_failure == &L_fallthrough) {
3832 beq(AT, R0, *L_slow_path);
3833 delayed()->nop();
3834 } else {
3835 bne_far(AT, R0, *L_failure);
3836 delayed()->nop();
3837 b(*L_slow_path);
3838 delayed()->nop();
3839 }
3840 } else if (super_check_offset.as_constant() == sc_offset) {
3841 // Need a slow path; fast failure is impossible.
3842 if (L_slow_path == &L_fallthrough) {
3843 beq(super_klass, AT, *L_success);
3844 delayed()->nop();
3845 } else {
3846 bne(super_klass, AT, *L_slow_path);
3847 delayed()->nop();
3848 b(*L_success);
3849 delayed()->nop();
3850 }
3851 } else {
3852 // No slow path; it's a fast decision.
3853 if (L_failure == &L_fallthrough) {
3854 beq(super_klass, AT, *L_success);
3855 delayed()->nop();
3856 } else {
3857 bne_far(super_klass, AT, *L_failure);
3858 delayed()->nop();
3859 b(*L_success);
3860 delayed()->nop();
3861 }
3862 }
3864 bind(L_fallthrough);
3866 }
3869 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3870 Register super_klass,
3871 Register temp_reg,
3872 Register temp2_reg,
3873 Label* L_success,
3874 Label* L_failure,
3875 bool set_cond_codes) {
3876 assert_different_registers(sub_klass, super_klass, temp_reg);
3877 if (temp2_reg != noreg)
3878 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
3879 else
3880 temp2_reg = T9;
3881 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
3883 Label L_fallthrough;
3884 int label_nulls = 0;
3885 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3886 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3887 assert(label_nulls <= 1, "at most one NULL in the batch");
3889 // a couple of useful fields in sub_klass:
3890 int ss_offset = in_bytes(Klass::secondary_supers_offset());
3891 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3892 Address secondary_supers_addr(sub_klass, ss_offset);
3893 Address super_cache_addr( sub_klass, sc_offset);
3895 // Do a linear scan of the secondary super-klass chain.
3896 // This code is rarely used, so simplicity is a virtue here.
3897 // The repne_scan instruction uses fixed registers, which we must spill.
3898 // Don't worry too much about pre-existing connections with the input regs.
3900 // Get super_klass value into rax (even if it was in rdi or rcx).
3901 #ifndef PRODUCT
3902 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
3903 ExternalAddress pst_counter_addr((address) pst_counter);
3904 NOT_LP64( incrementl(pst_counter_addr) );
3905 #endif //PRODUCT
3907 // We will consult the secondary-super array.
3908 ld(temp_reg, secondary_supers_addr);
3909 // Load the array length. (Positive movl does right thing on LP64.)
3910 lw(temp2_reg, Address(temp_reg, Array<Klass*>::length_offset_in_bytes()));
3911 // Skip to start of data.
3912 daddiu(temp_reg, temp_reg, Array<Klass*>::base_offset_in_bytes());
3914 // Scan RCX words at [RDI] for an occurrence of RAX.
3915 // Set NZ/Z based on last compare.
3916 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
3917 // not change flags (only scas instruction which is repeated sets flags).
3918 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
3920 // OpenJDK8 never compresses klass pointers in secondary-super array.
3921 Label Loop, subtype;
3922 bind(Loop);
3923 beq(temp2_reg, R0, *L_failure);
3924 delayed()->nop();
3925 ld(AT, temp_reg, 0);
3926 beq(AT, super_klass, subtype);
3927 delayed()->daddi(temp_reg, temp_reg, 1 * wordSize);
3928 b(Loop);
3929 delayed()->daddi(temp2_reg, temp2_reg, -1);
3931 bind(subtype);
3932 sd(super_klass, super_cache_addr);
3933 if (L_success != &L_fallthrough) {
3934 b(*L_success);
3935 delayed()->nop();
3936 }
3938 // Success. Cache the super we found and proceed in triumph.
3939 #undef IS_A_TEMP
3941 bind(L_fallthrough);
3942 }
3944 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
3945 ld(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
3946 sd(R0, Address(java_thread, JavaThread::vm_result_offset()));
3947 verify_oop(oop_result, "broken oop in call_VM_base");
3948 }
3950 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
3951 ld(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
3952 sd(R0, Address(java_thread, JavaThread::vm_result_2_offset()));
3953 }
3955 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
3956 int extra_slot_offset) {
3957 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
3958 int stackElementSize = Interpreter::stackElementSize;
3959 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
3960 #ifdef ASSERT
3961 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
3962 assert(offset1 - offset == stackElementSize, "correct arithmetic");
3963 #endif
3964 Register scale_reg = NOREG;
3965 Address::ScaleFactor scale_factor = Address::no_scale;
3966 if (arg_slot.is_constant()) {
3967 offset += arg_slot.as_constant() * stackElementSize;
3968 } else {
3969 scale_reg = arg_slot.as_register();
3970 scale_factor = Address::times_8;
3971 }
3972 // We don't push RA on stack in prepare_invoke.
3973 // offset += wordSize; // return PC is on stack
3974 if(scale_reg==NOREG) return Address(SP, offset);
3975 else {
3976 dsll(scale_reg, scale_reg, scale_factor);
3977 daddu(scale_reg, SP, scale_reg);
3978 return Address(scale_reg, offset);
3979 }
3980 }
3982 SkipIfEqual::~SkipIfEqual() {
3983 _masm->bind(_label);
3984 }
3986 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3987 switch (size_in_bytes) {
3988 #ifndef _LP64
3989 case 8:
3990 assert(dst2 != noreg, "second dest register required");
3991 lw(dst, src);
3992 lw(dst2, src.plus_disp(BytesPerInt));
3993 break;
3994 #else
3995 case 8: ld(dst, src); break;
3996 #endif
3997 case 4: lw(dst, src); break;
3998 case 2: is_signed ? lh(dst, src) : lhu(dst, src); break;
3999 case 1: is_signed ? lb( dst, src) : lbu( dst, src); break;
4000 default: ShouldNotReachHere();
4001 }
4002 }
4004 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
4005 switch (size_in_bytes) {
4006 #ifndef _LP64
4007 case 8:
4008 assert(src2 != noreg, "second source register required");
4009 sw(src, dst);
4010 sw(src2, dst.plus_disp(BytesPerInt));
4011 break;
4012 #else
4013 case 8: sd(src, dst); break;
4014 #endif
4015 case 4: sw(src, dst); break;
4016 case 2: sh(src, dst); break;
4017 case 1: sb(src, dst); break;
4018 default: ShouldNotReachHere();
4019 }
4020 }
4022 // Look up the method for a megamorphic invokeinterface call.
4023 // The target method is determined by <intf_klass, itable_index>.
4024 // The receiver klass is in recv_klass.
4025 // On success, the result will be in method_result, and execution falls through.
4026 // On failure, execution transfers to the given label.
4027 void MacroAssembler::lookup_interface_method(Register recv_klass,
4028 Register intf_klass,
4029 RegisterOrConstant itable_index,
4030 Register method_result,
4031 Register scan_temp,
4032 Label& L_no_such_interface,
4033 bool return_method) {
4034 assert_different_registers(recv_klass, intf_klass, scan_temp, AT);
4035 assert_different_registers(method_result, intf_klass, scan_temp, AT);
4036 assert(recv_klass != method_result || !return_method,
4037 "recv_klass can be destroyed when method isn't needed");
4039 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4040 "caller must use same register for non-constant itable index as for method");
4042 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4043 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4044 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4045 int scan_step = itableOffsetEntry::size() * wordSize;
4046 int vte_size = vtableEntry::size() * wordSize;
4047 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4048 assert(vte_size == wordSize, "else adjust times_vte_scale");
4050 lw(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4052 // %%% Could store the aligned, prescaled offset in the klassoop.
4053 dsll(scan_temp, scan_temp, times_vte_scale);
4054 daddu(scan_temp, recv_klass, scan_temp);
4055 daddiu(scan_temp, scan_temp, vtable_base);
4056 if (HeapWordsPerLong > 1) {
4057 // Round up to align_object_offset boundary
4058 // see code for InstanceKlass::start_of_itable!
4059 round_to(scan_temp, BytesPerLong);
4060 }
4062 if (return_method) {
4063 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4064 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4065 if (itable_index.is_constant()) {
4066 set64(AT, (int)itable_index.is_constant());
4067 dsll(AT, AT, (int)Address::times_ptr);
4068 } else {
4069 dsll(AT, itable_index.as_register(), (int)Address::times_ptr);
4070 }
4071 daddu(AT, AT, recv_klass);
4072 daddiu(recv_klass, AT, itentry_off);
4073 }
4075 Label search, found_method;
4077 for (int peel = 1; peel >= 0; peel--) {
4078 ld(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4080 if (peel) {
4081 beq(intf_klass, method_result, found_method);
4082 delayed()->nop();
4083 } else {
4084 bne(intf_klass, method_result, search);
4085 delayed()->nop();
4086 // (invert the test to fall through to found_method...)
4087 }
4089 if (!peel) break;
4091 bind(search);
4093 // Check that the previous entry is non-null. A null entry means that
4094 // the receiver class doesn't implement the interface, and wasn't the
4095 // same as when the caller was compiled.
4096 beq(method_result, R0, L_no_such_interface);
4097 delayed()->nop();
4098 daddiu(scan_temp, scan_temp, scan_step);
4099 }
4101 bind(found_method);
4103 if (return_method) {
4104 // Got a hit.
4105 lw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4106 if(UseLoongsonISA) {
4107 gsldx(method_result, recv_klass, scan_temp, 0);
4108 } else {
4109 daddu(AT, recv_klass, scan_temp);
4110 ld(method_result, AT);
4111 }
4112 }
4113 }
4115 // virtual method calling
4116 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4117 RegisterOrConstant vtable_index,
4118 Register method_result) {
4119 Register tmp = GP;
4120 push(tmp);
4122 if (vtable_index.is_constant()) {
4123 assert_different_registers(recv_klass, method_result, tmp);
4124 } else {
4125 assert_different_registers(recv_klass, method_result, vtable_index.as_register(), tmp);
4126 }
4127 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4128 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4129 /*
4130 Address vtable_entry_addr(recv_klass,
4131 vtable_index, Address::times_ptr,
4132 base + vtableEntry::method_offset_in_bytes());
4133 */
4134 if (vtable_index.is_constant()) {
4135 set64(AT, vtable_index.as_constant());
4136 dsll(AT, AT, (int)Address::times_ptr);
4137 } else {
4138 dsll(AT, vtable_index.as_register(), (int)Address::times_ptr);
4139 }
4140 set64(tmp, base + vtableEntry::method_offset_in_bytes());
4141 daddu(tmp, tmp, AT);
4142 daddu(tmp, tmp, recv_klass);
4143 ld(method_result, tmp, 0);
4145 pop(tmp);
4146 }
4148 void MacroAssembler::store_for_type_by_register(Register src_reg, Register tmp_reg, int disp, BasicType type, bool wide) {
4149 switch (type) {
4150 case T_LONG:
4151 st_ptr(src_reg, tmp_reg, disp);
4152 break;
4153 case T_ARRAY:
4154 case T_OBJECT:
4155 if (UseCompressedOops && !wide) {
4156 sw(src_reg, tmp_reg, disp);
4157 } else {
4158 st_ptr(src_reg, tmp_reg, disp);
4159 }
4160 break;
4161 case T_ADDRESS:
4162 st_ptr(src_reg, tmp_reg, disp);
4163 break;
4164 case T_INT:
4165 sw(src_reg, tmp_reg, disp);
4166 break;
4167 case T_CHAR:
4168 case T_SHORT:
4169 sh(src_reg, tmp_reg, disp);
4170 break;
4171 case T_BYTE:
4172 case T_BOOLEAN:
4173 sb(src_reg, tmp_reg, disp);
4174 break;
4175 default:
4176 ShouldNotReachHere();
4177 }
4178 }
4180 void MacroAssembler::store_for_type(Register src_reg, Address addr, BasicType type, bool wide) {
4181 Register tmp_reg = T9;
4182 Register index_reg = addr.index();
4183 if (index_reg == NOREG) {
4184 tmp_reg = NOREG;
4185 }
4187 int scale = addr.scale();
4188 if (tmp_reg != NOREG && scale >= 0) {
4189 dsll(tmp_reg, index_reg, scale);
4190 }
4192 int disp = addr.disp();
4193 bool disp_is_simm16 = true;
4194 if (!Assembler::is_simm16(disp)) {
4195 disp_is_simm16 = false;
4196 }
4198 Register base_reg = addr.base();
4199 if (tmp_reg != NOREG) {
4200 assert_different_registers(tmp_reg, base_reg, index_reg);
4201 }
4203 if (tmp_reg != NOREG) {
4204 daddu(tmp_reg, base_reg, tmp_reg);
4205 if (!disp_is_simm16) {
4206 move(tmp_reg, disp);
4207 daddu(tmp_reg, base_reg, tmp_reg);
4208 }
4209 store_for_type_by_register(src_reg, tmp_reg, disp_is_simm16 ? disp : 0, type, wide);
4210 } else {
4211 if (!disp_is_simm16) {
4212 tmp_reg = T9;
4213 assert_different_registers(tmp_reg, base_reg);
4214 move(tmp_reg, disp);
4215 daddu(tmp_reg, base_reg, tmp_reg);
4216 }
4217 store_for_type_by_register(src_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type, wide);
4218 }
4219 }
4221 void MacroAssembler::store_for_type_by_register(FloatRegister src_reg, Register tmp_reg, int disp, BasicType type) {
4222 switch (type) {
4223 case T_DOUBLE:
4224 sdc1(src_reg, tmp_reg, disp);
4225 break;
4226 case T_FLOAT:
4227 swc1(src_reg, tmp_reg, disp);
4228 break;
4229 default:
4230 ShouldNotReachHere();
4231 }
4232 }
4234 void MacroAssembler::store_for_type(FloatRegister src_reg, Address addr, BasicType type) {
4235 Register tmp_reg = T9;
4236 Register index_reg = addr.index();
4237 if (index_reg == NOREG) {
4238 tmp_reg = NOREG;
4239 }
4241 int scale = addr.scale();
4242 if (tmp_reg != NOREG && scale >= 0) {
4243 dsll(tmp_reg, index_reg, scale);
4244 }
4246 int disp = addr.disp();
4247 bool disp_is_simm16 = true;
4248 if (!Assembler::is_simm16(disp)) {
4249 disp_is_simm16 = false;
4250 }
4252 Register base_reg = addr.base();
4253 if (tmp_reg != NOREG) {
4254 assert_different_registers(tmp_reg, base_reg, index_reg);
4255 }
4257 if (tmp_reg != NOREG) {
4258 daddu(tmp_reg, base_reg, tmp_reg);
4259 if (!disp_is_simm16) {
4260 move(tmp_reg, disp);
4261 daddu(tmp_reg, base_reg, tmp_reg);
4262 }
4263 store_for_type_by_register(src_reg, tmp_reg, disp_is_simm16 ? disp : 0, type);
4264 } else {
4265 if (!disp_is_simm16) {
4266 tmp_reg = T9;
4267 assert_different_registers(tmp_reg, base_reg);
4268 move(tmp_reg, disp);
4269 daddu(tmp_reg, base_reg, tmp_reg);
4270 }
4271 store_for_type_by_register(src_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type);
4272 }
4273 }
4275 void MacroAssembler::load_for_type_by_register(Register dst_reg, Register tmp_reg, int disp, BasicType type, bool wide) {
4276 switch (type) {
4277 case T_LONG:
4278 ld_ptr(dst_reg, tmp_reg, disp);
4279 break;
4280 case T_ARRAY:
4281 case T_OBJECT:
4282 if (UseCompressedOops && !wide) {
4283 lwu(dst_reg, tmp_reg, disp);
4284 } else {
4285 ld_ptr(dst_reg, tmp_reg, disp);
4286 }
4287 break;
4288 case T_ADDRESS:
4289 if (UseCompressedClassPointers && disp == oopDesc::klass_offset_in_bytes()) {
4290 lwu(dst_reg, tmp_reg, disp);
4291 } else {
4292 ld_ptr(dst_reg, tmp_reg, disp);
4293 }
4294 break;
4295 case T_INT:
4296 lw(dst_reg, tmp_reg, disp);
4297 break;
4298 case T_CHAR:
4299 lhu(dst_reg, tmp_reg, disp);
4300 break;
4301 case T_SHORT:
4302 lh(dst_reg, tmp_reg, disp);
4303 break;
4304 case T_BYTE:
4305 case T_BOOLEAN:
4306 lb(dst_reg, tmp_reg, disp);
4307 break;
4308 default:
4309 ShouldNotReachHere();
4310 }
4311 }
4313 int MacroAssembler::load_for_type(Register dst_reg, Address addr, BasicType type, bool wide) {
4314 int code_offset = 0;
4315 Register tmp_reg = T9;
4316 Register index_reg = addr.index();
4317 if (index_reg == NOREG) {
4318 tmp_reg = NOREG;
4319 }
4321 int scale = addr.scale();
4322 if (tmp_reg != NOREG && scale >= 0) {
4323 dsll(tmp_reg, index_reg, scale);
4324 }
4326 int disp = addr.disp();
4327 bool disp_is_simm16 = true;
4328 if (!Assembler::is_simm16(disp)) {
4329 disp_is_simm16 = false;
4330 }
4332 Register base_reg = addr.base();
4333 if (tmp_reg != NOREG) {
4334 assert_different_registers(tmp_reg, base_reg, index_reg);
4335 }
4337 if (tmp_reg != NOREG) {
4338 daddu(tmp_reg, base_reg, tmp_reg);
4339 if (!disp_is_simm16) {
4340 move(tmp_reg, disp);
4341 daddu(tmp_reg, base_reg, tmp_reg);
4342 }
4343 code_offset = offset();
4344 load_for_type_by_register(dst_reg, tmp_reg, disp_is_simm16 ? disp : 0, type, wide);
4345 } else {
4346 if (!disp_is_simm16) {
4347 tmp_reg = T9;
4348 assert_different_registers(tmp_reg, base_reg);
4349 move(tmp_reg, disp);
4350 daddu(tmp_reg, base_reg, tmp_reg);
4351 }
4352 code_offset = offset();
4353 load_for_type_by_register(dst_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type, wide);
4354 }
4356 return code_offset;
4357 }
4359 void MacroAssembler::load_for_type_by_register(FloatRegister dst_reg, Register tmp_reg, int disp, BasicType type) {
4360 switch (type) {
4361 case T_DOUBLE:
4362 ldc1(dst_reg, tmp_reg, disp);
4363 break;
4364 case T_FLOAT:
4365 lwc1(dst_reg, tmp_reg, disp);
4366 break;
4367 default:
4368 ShouldNotReachHere();
4369 }
4370 }
4372 int MacroAssembler::load_for_type(FloatRegister dst_reg, Address addr, BasicType type) {
4373 int code_offset = 0;
4374 Register tmp_reg = T9;
4375 Register index_reg = addr.index();
4376 if (index_reg == NOREG) {
4377 tmp_reg = NOREG;
4378 }
4380 int scale = addr.scale();
4381 if (tmp_reg != NOREG && scale >= 0) {
4382 dsll(tmp_reg, index_reg, scale);
4383 }
4385 int disp = addr.disp();
4386 bool disp_is_simm16 = true;
4387 if (!Assembler::is_simm16(disp)) {
4388 disp_is_simm16 = false;
4389 }
4391 Register base_reg = addr.base();
4392 if (tmp_reg != NOREG) {
4393 assert_different_registers(tmp_reg, base_reg, index_reg);
4394 }
4396 if (tmp_reg != NOREG) {
4397 daddu(tmp_reg, base_reg, tmp_reg);
4398 if (!disp_is_simm16) {
4399 move(tmp_reg, disp);
4400 daddu(tmp_reg, base_reg, tmp_reg);
4401 }
4402 code_offset = offset();
4403 load_for_type_by_register(dst_reg, tmp_reg, disp_is_simm16 ? disp : 0, type);
4404 } else {
4405 if (!disp_is_simm16) {
4406 tmp_reg = T9;
4407 assert_different_registers(tmp_reg, base_reg);
4408 move(tmp_reg, disp);
4409 daddu(tmp_reg, base_reg, tmp_reg);
4410 }
4411 code_offset = offset();
4412 load_for_type_by_register(dst_reg, disp_is_simm16 ? base_reg : tmp_reg, disp_is_simm16 ? disp : 0, type);
4413 }
4415 return code_offset;
4416 }