[Interpreter] Optimize TemplateTable::ldc2_w.

Thu, 21 Sep 2017 11:09:31 +0800

author
fujie
date
Thu, 21 Sep 2017 11:09:31 +0800
changeset 6889
a1eb29ee98ab
parent 6888
b6a542947da3
child 6890
d911cc184106

[Interpreter] Optimize TemplateTable::ldc2_w.

src/cpu/mips/vm/templateTable_mips_64.cpp file | annotate | diff | comparison | revisions
     1.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Sep 20 11:08:18 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Thu Sep 21 11:09:31 2017 +0800
     1.3 @@ -380,8 +380,7 @@
     1.4    Label Long, Done;
     1.5  
     1.6    // get index in cpool
     1.7 -  __ get_2_byte_integer_at_bcp(T2, AT, 1);
     1.8 -  __ huswap(T2);
     1.9 +  __ get_unsigned_2_byte_index_at_bcp(T2, 1);
    1.10  
    1.11    __ get_cpool_and_tags(T3, T1);
    1.12  
    1.13 @@ -389,23 +388,36 @@
    1.14    const int tags_offset = Array<u1>::base_offset_in_bytes();
    1.15  
    1.16    // get type in T1
    1.17 -  __ dadd(AT, T1, T2);
    1.18 -  __ lb(T1, AT, tags_offset);
    1.19 +  if (UseLoongsonISA && Assembler::is_simm(tags_offset, 8)) {
    1.20 +    __ gslbx(T1, T1, T2, tags_offset);
    1.21 +  } else {
    1.22 +    __ dadd(AT, T1, T2);
    1.23 +    __ lb(T1, AT, tags_offset);
    1.24 +  }
    1.25  
    1.26    __ daddiu(AT, T1, - JVM_CONSTANT_Double);
    1.27    __ bne(AT, R0, Long);
    1.28    __ delayed()->dsll(T2, T2, Address::times_8);
    1.29 +
    1.30    // dtos
    1.31 -  __ daddu(AT, T3, T2);
    1.32 -  __ ldc1(FSF, AT, base_offset + 0 * wordSize);
    1.33 +  if (UseLoongsonISA && Assembler::is_simm(base_offset, 8)) {
    1.34 +    __ gsldxc1(FSF, T3, T2, base_offset);
    1.35 +  } else {
    1.36 +    __ daddu(AT, T3, T2);
    1.37 +    __ ldc1(FSF, AT, base_offset);
    1.38 +  }
    1.39    __ sdc1(FSF, SP, - 2 * wordSize);
    1.40    __ b(Done);
    1.41    __ delayed()->daddi(SP, SP, - 2 * wordSize);
    1.42  
    1.43    // ltos
    1.44    __ bind(Long);
    1.45 -  __ dadd(AT, T3, T2);
    1.46 -  __ ld(FSR, AT, base_offset + 0 * wordSize);
    1.47 +  if (UseLoongsonISA && Assembler::is_simm(base_offset, 8)) {
    1.48 +    __ gsldx(FSR, T3, T2, base_offset);
    1.49 +  } else {
    1.50 +    __ dadd(AT, T3, T2);
    1.51 +    __ ld(FSR, AT, base_offset);
    1.52 +  }
    1.53    __ push(ltos);
    1.54  
    1.55    __ bind(Done);
    1.56 @@ -489,7 +501,6 @@
    1.57    transition(vtos, ltos);
    1.58    locals_index(T2);
    1.59    __ ld(FSR, T2, -wordSize);
    1.60 -  __ ld(SSR, T2, 0);
    1.61  }
    1.62  
    1.63  // used register T2

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