Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/mips_64.ad	Mon Feb 20 13:00:42 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/mips_64.ad	Wed Mar 08 02:30:50 2017 +0800
     1.3 @@ -12496,28 +12496,67 @@
     1.4      __ cvt_d_w(F30, F30);
     1.5  
     1.6      if( index != 0 ) {
     1.7 -        if(scale != 0) {
     1.8 -           __ dsll(T9, as_Register(index), scale);
     1.9 -           __ addu(AT, as_Register(base), T9);
    1.10 -        } else {
    1.11 -           __ daddu(AT, as_Register(base), as_Register(index));
    1.12 -        }
    1.13 -       if( Assembler::is_simm16(disp) ) { 
    1.14 -          __ sdc1(F30, AT, disp);
    1.15 -       } else {
    1.16 -          __ move(T9, disp);
    1.17 -          __ addu(AT, AT, T9);
    1.18 -          __ sdc1(F30, AT, 0);
    1.19 -       }
    1.20 -
    1.21 -    } else {
    1.22 -       if( Assembler::is_simm16(disp) ) { 
    1.23 -          __ sdc1(F30, as_Register(base), disp);
    1.24 -       } else {
    1.25 -          __ move(T9, disp);
    1.26 -          __ addu(AT, as_Register(base), T9);
    1.27 -          __ sdc1(F30, AT, 0);
    1.28 -       }
    1.29 +		if ( UseLoongsonISA ) {
    1.30 +			if ( Assembler::is_simm(disp, 8) ) {
    1.31 +				if (scale == 0) {
    1.32 +					__ gssdxc1(F30, as_Register(base), as_Register(index), disp);
    1.33 +				} else {
    1.34 +					__ dsll(T9, as_Register(index), scale);
    1.35 +					__ gssdxc1(F30, as_Register(base), T9, disp);
    1.36 +				}
    1.37 +			} else if ( Assembler::is_simm16(disp) ) {
    1.38 +				if (scale == 0) {
    1.39 +					__ daddu(AT, as_Register(base), as_Register(index));
    1.40 +					__ sdc1(F30, AT, disp);
    1.41 +				} else {
    1.42 +					__ dsll(T9, as_Register(index), scale);
    1.43 +					__ daddu(AT, as_Register(base), T9);
    1.44 +					__ sdc1(F30, AT, disp);
    1.45 +				}
    1.46 +			} else {
    1.47 +				if (scale == 0) {
    1.48 +					__ move(T9, disp);
    1.49 +					__ daddu(AT, as_Register(index), T9);
    1.50 +					__ gssdxc1(F30, as_Register(base), AT, 0);
    1.51 +				} else {
    1.52 +					__ move(T9, disp);
    1.53 +					__ dsll(AT, as_Register(index), scale);
    1.54 +					__ daddu(AT, AT, T9);
    1.55 +					__ gssdxc1(F30, as_Register(base), AT, 0);
    1.56 +				}
    1.57 +			}
    1.58 +		} else { // not use loongson isa
    1.59 +		    if(scale != 0) {
    1.60 +		       __ dsll(T9, as_Register(index), scale);
    1.61 +		       __ daddu(AT, as_Register(base), T9);
    1.62 +		    } else {
    1.63 +		       __ daddu(AT, as_Register(base), as_Register(index));
    1.64 +		    }
    1.65 +		   if( Assembler::is_simm16(disp) ) { 
    1.66 +		      __ sdc1(F30, AT, disp);
    1.67 +		   } else {
    1.68 +		      __ move(T9, disp);
    1.69 +		      __ daddu(AT, AT, T9);
    1.70 +		      __ sdc1(F30, AT, 0);
    1.71 +		   }
    1.72 +		}
    1.73 +    } else {// index is 0
    1.74 +		if ( UseLoongsonISA ) {
    1.75 +			if ( Assembler::is_simm16(disp) ) {
    1.76 +				__ sdc1(F30, as_Register(base), disp);
    1.77 +			} else {
    1.78 +				__ move(T9, disp);
    1.79 +				__ gssdxc1(F30, as_Register(base), T9, 0);
    1.80 +			}
    1.81 +		} else {
    1.82 +		   if( Assembler::is_simm16(disp) ) { 
    1.83 +		      __ sdc1(F30, as_Register(base), disp);
    1.84 +		   } else {
    1.85 +		      __ move(T9, disp);
    1.86 +		      __ daddu(AT, as_Register(base), T9);
    1.87 +		      __ sdc1(F30, AT, 0);
    1.88 +		   }
    1.89 +		}
    1.90      }
    1.91    %}
    1.92    ins_pipe( ialu_storeI );