Wed, 08 Mar 2017 05:19:55 +0800
[C2] adjust some format.
src/cpu/mips/vm/mips_64.ad | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Mar 08 02:30:50 2017 +0800 1.2 +++ b/src/cpu/mips/vm/mips_64.ad Wed Mar 08 05:19:55 2017 +0800 1.3 @@ -2267,7 +2267,7 @@ 1.4 __ lh(as_Register(dst), AT, disp); 1.5 } else { 1.6 __ move(T9, disp); 1.7 - __ addu(AT, AT, T9); 1.8 + __ daddu(AT, AT, T9); 1.9 __ lh(as_Register(dst), AT, 0); 1.10 } 1.11 } 1.12 @@ -2284,7 +2284,7 @@ 1.13 __ lh(as_Register(dst), as_Register(base), disp); 1.14 } else { 1.15 __ move(T9, disp); 1.16 - __ addu(AT, as_Register(base), T9); 1.17 + __ daddu(AT, as_Register(base), T9); 1.18 __ lh(as_Register(dst), AT, 0); 1.19 } 1.20 } 1.21 @@ -2558,91 +2558,91 @@ 1.22 int value = $src$$constant; 1.23 1.24 if( index != 0 ) { 1.25 - if ( UseLoongsonISA ) { 1.26 - if ( Assembler::is_simm(disp, 8) ) { 1.27 - if ( scale == 0 ) { 1.28 - if ( value == 0 ) { 1.29 - __ gsswx(R0, as_Register(base), as_Register(index), disp); 1.30 - } else { 1.31 - __ move(T9, value); 1.32 - __ gsswx(T9, as_Register(base), as_Register(index), disp); 1.33 - } 1.34 - } else { 1.35 - __ dsll(AT, as_Register(index), scale); 1.36 - if ( value == 0 ) { 1.37 - __ gsswx(R0, as_Register(base), AT, disp); 1.38 - } else { 1.39 - __ move(T9, value); 1.40 - __ gsswx(T9, as_Register(base), AT, disp); 1.41 - } 1.42 - } 1.43 - } else if ( Assembler::is_simm16(disp) ) { 1.44 - if ( scale == 0 ) { 1.45 - __ daddu(AT, as_Register(base), as_Register(index)); 1.46 - if ( value == 0 ) { 1.47 - __ sw(R0, AT, disp); 1.48 - } else { 1.49 - __ move(T9, value); 1.50 - __ sw(T9, AT, disp); 1.51 - } 1.52 - } else { 1.53 - __ dsll(AT, as_Register(index), scale); 1.54 - __ daddu(AT, as_Register(base), AT); 1.55 - if ( value == 0 ) { 1.56 - __ sw(R0, AT, disp); 1.57 - } else { 1.58 - __ move(T9, value); 1.59 - __ sw(T9, AT, disp); 1.60 - } 1.61 + if ( UseLoongsonISA ) { 1.62 + if ( Assembler::is_simm(disp, 8) ) { 1.63 + if ( scale == 0 ) { 1.64 + if ( value == 0 ) { 1.65 + __ gsswx(R0, as_Register(base), as_Register(index), disp); 1.66 + } else { 1.67 + __ move(T9, value); 1.68 + __ gsswx(T9, as_Register(base), as_Register(index), disp); 1.69 + } 1.70 + } else { 1.71 + __ dsll(AT, as_Register(index), scale); 1.72 + if ( value == 0 ) { 1.73 + __ gsswx(R0, as_Register(base), AT, disp); 1.74 + } else { 1.75 + __ move(T9, value); 1.76 + __ gsswx(T9, as_Register(base), AT, disp); 1.77 + } 1.78 + } 1.79 + } else if ( Assembler::is_simm16(disp) ) { 1.80 + if ( scale == 0 ) { 1.81 + __ daddu(AT, as_Register(base), as_Register(index)); 1.82 + if ( value == 0 ) { 1.83 + __ sw(R0, AT, disp); 1.84 + } else { 1.85 + __ move(T9, value); 1.86 + __ sw(T9, AT, disp); 1.87 + } 1.88 + } else { 1.89 + __ dsll(AT, as_Register(index), scale); 1.90 + __ daddu(AT, as_Register(base), AT); 1.91 + if ( value == 0 ) { 1.92 + __ sw(R0, AT, disp); 1.93 + } else { 1.94 + __ move(T9, value); 1.95 + __ sw(T9, AT, disp); 1.96 + } 1.97 } 1.98 } else { 1.99 - if ( scale == 0 ) { 1.100 - __ move(T9, disp); 1.101 - __ daddu(AT, as_Register(index), T9); 1.102 - if ( value ==0 ) { 1.103 - __ gsswx(R0, as_Register(base), AT, 0); 1.104 - } else { 1.105 - __ move(T9, value); 1.106 - __ gsswx(T9, as_Register(base), AT, 0); 1.107 + if ( scale == 0 ) { 1.108 + __ move(T9, disp); 1.109 + __ daddu(AT, as_Register(index), T9); 1.110 + if ( value ==0 ) { 1.111 + __ gsswx(R0, as_Register(base), AT, 0); 1.112 + } else { 1.113 + __ move(T9, value); 1.114 + __ gsswx(T9, as_Register(base), AT, 0); 1.115 } 1.116 - } else { 1.117 - __ dsll(AT, as_Register(index), scale); 1.118 - __ move(T9, disp); 1.119 - __ daddu(AT, AT, T9); 1.120 - if ( value == 0 ) { 1.121 - __ gsswx(R0, as_Register(base), AT, 0); 1.122 - } else { 1.123 - __ move(T9, value); 1.124 - __ gsswx(T9, as_Register(base), AT, 0); 1.125 - } 1.126 - } 1.127 + } else { 1.128 + __ dsll(AT, as_Register(index), scale); 1.129 + __ move(T9, disp); 1.130 + __ daddu(AT, AT, T9); 1.131 + if ( value == 0 ) { 1.132 + __ gsswx(R0, as_Register(base), AT, 0); 1.133 + } else { 1.134 + __ move(T9, value); 1.135 + __ gsswx(T9, as_Register(base), AT, 0); 1.136 + } 1.137 + } 1.138 } 1.139 } else { //not use loongson isa 1.140 - if (scale == 0) { 1.141 - __ daddu(AT, as_Register(base), as_Register(index)); 1.142 - } else { 1.143 - __ dsll(AT, as_Register(index), scale); 1.144 - __ daddu(AT, as_Register(base), AT); 1.145 - } 1.146 - if( Assembler::is_simm16(disp) ) { 1.147 - if (value == 0) { 1.148 - __ sw(R0, AT, disp); 1.149 - } else { 1.150 - __ move(T9, value); 1.151 - __ sw(T9, AT, disp); 1.152 - } 1.153 - } else { 1.154 - if (value == 0) { 1.155 - __ move(T9, disp); 1.156 - __ addu(AT, AT, T9); 1.157 - __ sw(R0, AT, 0); 1.158 - } else { 1.159 - __ move(T9, disp); 1.160 - __ addu(AT, AT, T9); 1.161 - __ move(T9, value); 1.162 - __ sw(T9, AT, 0); 1.163 - } 1.164 - } 1.165 + if (scale == 0) { 1.166 + __ daddu(AT, as_Register(base), as_Register(index)); 1.167 + } else { 1.168 + __ dsll(AT, as_Register(index), scale); 1.169 + __ daddu(AT, as_Register(base), AT); 1.170 + } 1.171 + if( Assembler::is_simm16(disp) ) { 1.172 + if (value == 0) { 1.173 + __ sw(R0, AT, disp); 1.174 + } else { 1.175 + __ move(T9, value); 1.176 + __ sw(T9, AT, disp); 1.177 + } 1.178 + } else { 1.179 + if (value == 0) { 1.180 + __ move(T9, disp); 1.181 + __ daddu(AT, AT, T9); 1.182 + __ sw(R0, AT, 0); 1.183 + } else { 1.184 + __ move(T9, disp); 1.185 + __ daddu(AT, AT, T9); 1.186 + __ move(T9, value); 1.187 + __ sw(T9, AT, 0); 1.188 + } 1.189 + } 1.190 } 1.191 } else { 1.192 if ( UseLoongsonISA ) { 1.193 @@ -2673,11 +2673,11 @@ 1.194 } else { 1.195 if (value == 0) { 1.196 __ move(T9, disp); 1.197 - __ addu(AT, as_Register(base), T9); 1.198 + __ daddu(AT, as_Register(base), T9); 1.199 __ sw(R0, AT, 0); 1.200 } else { 1.201 __ move(T9, disp); 1.202 - __ addu(AT, as_Register(base), T9); 1.203 + __ daddu(AT, as_Register(base), T9); 1.204 __ move(T9, value); 1.205 __ sw(T9, AT, 0); 1.206 } 1.207 @@ -2734,15 +2734,15 @@ 1.208 assert(disp_reloc == relocInfo::none, "cannot have disp"); 1.209 1.210 if( index != 0 ) { 1.211 - if ( UseLoongsonISA ) { 1.212 - if ( Assembler::is_simm(disp, 8) ) { 1.213 - if ( scale != 0 ) { 1.214 + if ( UseLoongsonISA ) { 1.215 + if ( Assembler::is_simm(disp, 8) ) { 1.216 + if ( scale != 0 ) { 1.217 __ dsll(AT, as_Register(index), scale); 1.218 - __ gsldx(as_Register(dst), as_Register(base), AT, disp); 1.219 - } else { 1.220 - __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp); 1.221 + __ gsldx(as_Register(dst), as_Register(base), AT, disp); 1.222 + } else { 1.223 + __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp); 1.224 } 1.225 - } else if ( Assembler::is_simm16(disp) ){ 1.226 + } else if ( Assembler::is_simm16(disp) ){ 1.227 if ( scale != 0 ) { 1.228 __ dsll(AT, as_Register(index), scale); 1.229 __ daddu(AT, AT, as_Register(base)); 1.230 @@ -2751,7 +2751,7 @@ 1.231 } 1.232 __ ld(as_Register(dst), AT, disp); 1.233 } else { 1.234 - if ( scale != 0 ) { 1.235 + if ( scale != 0 ) { 1.236 __ dsll(AT, as_Register(index), scale); 1.237 __ move(T9, disp); 1.238 __ daddu(AT, AT, T9); 1.239 @@ -2760,39 +2760,39 @@ 1.240 __ daddu(AT, as_Register(index), T9); 1.241 } 1.242 __ gsldx(as_Register(dst), as_Register(base), AT, 0); 1.243 - } 1.244 - } else { //not use loongson isa 1.245 - if (scale == 0) { 1.246 - __ daddu(AT, as_Register(base), as_Register(index)); 1.247 - } else { 1.248 - __ dsll(AT, as_Register(index), scale); 1.249 - __ daddu(AT, as_Register(base), AT); 1.250 - } 1.251 - if( Assembler::is_simm16(disp) ) { 1.252 - __ ld(as_Register(dst), AT, disp); 1.253 - } else { 1.254 - __ li(T9, disp); 1.255 - __ daddu(AT, AT, T9); 1.256 - __ ld(as_Register(dst), AT, 0); 1.257 - } 1.258 - } 1.259 + } 1.260 + } else { //not use loongson isa 1.261 + if (scale == 0) { 1.262 + __ daddu(AT, as_Register(base), as_Register(index)); 1.263 + } else { 1.264 + __ dsll(AT, as_Register(index), scale); 1.265 + __ daddu(AT, as_Register(base), AT); 1.266 + } 1.267 + if( Assembler::is_simm16(disp) ) { 1.268 + __ ld(as_Register(dst), AT, disp); 1.269 + } else { 1.270 + __ li(T9, disp); 1.271 + __ daddu(AT, AT, T9); 1.272 + __ ld(as_Register(dst), AT, 0); 1.273 + } 1.274 + } 1.275 } else { 1.276 - if ( UseLoongsonISA ) { 1.277 - if ( Assembler::is_simm16(disp) ){ 1.278 - __ ld(as_Register(dst), as_Register(base), disp); 1.279 - } else { 1.280 - __ li(T9, disp); 1.281 - __ gsldx(as_Register(dst), as_Register(base), T9, 0); 1.282 - } 1.283 - } else { //not use loongson isa 1.284 - if( Assembler::is_simm16(disp) ) { 1.285 - __ ld(as_Register(dst), as_Register(base), disp); 1.286 - } else { 1.287 - __ li(T9, disp); 1.288 - __ daddu(AT, as_Register(base), T9); 1.289 - __ ld(as_Register(dst), AT, 0); 1.290 - } 1.291 - } 1.292 + if ( UseLoongsonISA ) { 1.293 + if ( Assembler::is_simm16(disp) ){ 1.294 + __ ld(as_Register(dst), as_Register(base), disp); 1.295 + } else { 1.296 + __ li(T9, disp); 1.297 + __ gsldx(as_Register(dst), as_Register(base), T9, 0); 1.298 + } 1.299 + } else { //not use loongson isa 1.300 + if( Assembler::is_simm16(disp) ) { 1.301 + __ ld(as_Register(dst), as_Register(base), disp); 1.302 + } else { 1.303 + __ li(T9, disp); 1.304 + __ daddu(AT, as_Register(base), T9); 1.305 + __ ld(as_Register(dst), AT, 0); 1.306 + } 1.307 + } 1.308 } 1.309 // if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0); 1.310 %} 1.311 @@ -2806,34 +2806,34 @@ 1.312 int disp = $mem$$disp; 1.313 1.314 if( index != 0 ) { 1.315 - if ( UseLoongsonISA ){ 1.316 - if ( Assembler::is_simm(disp, 8) ) { 1.317 - if ( scale == 0 ) { 1.318 - __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp); 1.319 - } else { 1.320 - __ dsll(AT, as_Register(index), scale); 1.321 - __ gssdx(as_Register(src), as_Register(base), AT, disp); 1.322 - } 1.323 - } else if ( Assembler::is_simm16(disp) ) { 1.324 - if ( scale == 0 ) { 1.325 - __ daddu(AT, as_Register(base), as_Register(index)); 1.326 - } else { 1.327 + if ( UseLoongsonISA ){ 1.328 + if ( Assembler::is_simm(disp, 8) ) { 1.329 + if ( scale == 0 ) { 1.330 + __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp); 1.331 + } else { 1.332 + __ dsll(AT, as_Register(index), scale); 1.333 + __ gssdx(as_Register(src), as_Register(base), AT, disp); 1.334 + } 1.335 + } else if ( Assembler::is_simm16(disp) ) { 1.336 + if ( scale == 0 ) { 1.337 + __ daddu(AT, as_Register(base), as_Register(index)); 1.338 + } else { 1.339 __ dsll(AT, as_Register(index), scale); 1.340 __ daddu(AT, as_Register(base), AT); 1.341 - } 1.342 + } 1.343 __ sd(as_Register(src), AT, disp); 1.344 - } else { 1.345 - if ( scale == 0 ) { 1.346 - __ move(T9, disp); 1.347 - __ daddu(AT, as_Register(index), T9); 1.348 - } else { 1.349 - __ dsll(AT, as_Register(index), scale); 1.350 - __ move(T9, disp); 1.351 - __ daddu(AT, AT, T9); 1.352 - } 1.353 - __ gssdx(as_Register(src), as_Register(base), AT, 0); 1.354 + } else { 1.355 + if ( scale == 0 ) { 1.356 + __ move(T9, disp); 1.357 + __ daddu(AT, as_Register(index), T9); 1.358 + } else { 1.359 + __ dsll(AT, as_Register(index), scale); 1.360 + __ move(T9, disp); 1.361 + __ daddu(AT, AT, T9); 1.362 + } 1.363 + __ gssdx(as_Register(src), as_Register(base), AT, 0); 1.364 } 1.365 - } else { //not use loongson isa 1.366 + } else { //not use loongson isa 1.367 if (scale == 0) { 1.368 __ daddu(AT, as_Register(base), as_Register(index)); 1.369 } else { 1.370 @@ -2847,24 +2847,24 @@ 1.371 __ daddu(AT, AT, T9); 1.372 __ sd(as_Register(src), AT, 0); 1.373 } 1.374 - } 1.375 + } 1.376 } else { 1.377 - if ( UseLoongsonISA ) { 1.378 - if ( Assembler::is_simm16(disp) ) { 1.379 - __ sd(as_Register(src), as_Register(base), disp); 1.380 - } else { 1.381 - __ move(T9, disp); 1.382 - __ gssdx(as_Register(src), as_Register(base), T9, 0); 1.383 - } 1.384 - } else { 1.385 - if( Assembler::is_simm16(disp) ) { 1.386 - __ sd(as_Register(src), as_Register(base), disp); 1.387 - } else { 1.388 - __ move(T9, disp); 1.389 - __ daddu(AT, as_Register(base), T9); 1.390 - __ sd(as_Register(src), AT, 0); 1.391 - } 1.392 - } 1.393 + if ( UseLoongsonISA ) { 1.394 + if ( Assembler::is_simm16(disp) ) { 1.395 + __ sd(as_Register(src), as_Register(base), disp); 1.396 + } else { 1.397 + __ move(T9, disp); 1.398 + __ gssdx(as_Register(src), as_Register(base), T9, 0); 1.399 + } 1.400 + } else { 1.401 + if( Assembler::is_simm16(disp) ) { 1.402 + __ sd(as_Register(src), as_Register(base), disp); 1.403 + } else { 1.404 + __ move(T9, disp); 1.405 + __ daddu(AT, as_Register(base), T9); 1.406 + __ sd(as_Register(src), AT, 0); 1.407 + } 1.408 + } 1.409 } 1.410 %} 1.411 1.412 @@ -2877,35 +2877,35 @@ 1.413 int disp = $mem$$disp; 1.414 1.415 if( index != 0 ) { 1.416 - if ( UseLoongsonISA ){ 1.417 - if ( Assembler::is_simm(disp, 8) ) { 1.418 - if ( scale == 0 ) { 1.419 - __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp); 1.420 - } else { 1.421 + if ( UseLoongsonISA ){ 1.422 + if ( Assembler::is_simm(disp, 8) ) { 1.423 + if ( scale == 0 ) { 1.424 + __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp); 1.425 + } else { 1.426 __ dsll(AT, as_Register(index), scale); 1.427 __ gsswx(as_Register(src), as_Register(base), AT, disp); 1.428 - } 1.429 - } else if ( Assembler::is_simm16(disp) ) { 1.430 + } 1.431 + } else if ( Assembler::is_simm16(disp) ) { 1.432 if ( scale == 0 ) { 1.433 __ daddu(AT, as_Register(base), as_Register(index)); 1.434 - } else { 1.435 - __ dsll(AT, as_Register(index), scale); 1.436 - __ daddu(AT, as_Register(base), AT); 1.437 - } 1.438 - __ sw(as_Register(src), AT, disp); 1.439 - } else { 1.440 - if ( scale == 0 ) { 1.441 - __ move(T9, disp); 1.442 + } else { 1.443 + __ dsll(AT, as_Register(index), scale); 1.444 + __ daddu(AT, as_Register(base), AT); 1.445 + } 1.446 + __ sw(as_Register(src), AT, disp); 1.447 + } else { 1.448 + if ( scale == 0 ) { 1.449 + __ move(T9, disp); 1.450 __ daddu(AT, as_Register(index), T9); 1.451 - } else { 1.452 + } else { 1.453 __ dsll(AT, as_Register(index), scale); 1.454 - __ move(T9, disp); 1.455 + __ move(T9, disp); 1.456 __ daddu(AT, AT, T9); 1.457 - } 1.458 - __ gsswx(as_Register(src), as_Register(base), AT, 0); 1.459 - } 1.460 - } else { //not use loongson isa 1.461 - if (scale == 0) { 1.462 + } 1.463 + __ gsswx(as_Register(src), as_Register(base), AT, 0); 1.464 + } 1.465 + } else { //not use loongson isa 1.466 + if (scale == 0) { 1.467 __ daddu(AT, as_Register(base), as_Register(index)); 1.468 } else { 1.469 __ dsll(AT, as_Register(index), scale); 1.470 @@ -2915,27 +2915,27 @@ 1.471 __ sw(as_Register(src), AT, disp); 1.472 } else { 1.473 __ move(T9, disp); 1.474 - __ addu(AT, AT, T9); 1.475 + __ daddu(AT, AT, T9); 1.476 __ sw(as_Register(src), AT, 0); 1.477 } 1.478 - } 1.479 + } 1.480 } else { 1.481 - if ( UseLoongsonISA ) { 1.482 - if ( Assembler::is_simm16(disp) ) { 1.483 - __ sw(as_Register(src), as_Register(base), disp); 1.484 - } else { 1.485 - __ move(T9, disp); 1.486 - __ gsswx(as_Register(src), as_Register(base), T9, 0); 1.487 - } 1.488 - } else { 1.489 + if ( UseLoongsonISA ) { 1.490 + if ( Assembler::is_simm16(disp) ) { 1.491 + __ sw(as_Register(src), as_Register(base), disp); 1.492 + } else { 1.493 + __ move(T9, disp); 1.494 + __ gsswx(as_Register(src), as_Register(base), T9, 0); 1.495 + } 1.496 + } else { 1.497 if( Assembler::is_simm16(disp) ) { 1.498 __ sw(as_Register(src), as_Register(base), disp); 1.499 } else { 1.500 __ move(T9, disp); 1.501 - __ addu(AT, as_Register(base), T9); 1.502 + __ daddu(AT, as_Register(base), T9); 1.503 __ sw(as_Register(src), AT, 0); 1.504 } 1.505 - } 1.506 + } 1.507 } 1.508 %} 1.509