Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp	Wed Oct 14 17:44:48 2020 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp	Fri Oct 23 18:04:23 2020 +0800
     1.3 @@ -1,6 +1,6 @@
     1.4  /*
     1.5   * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
     1.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
     1.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     1.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     1.9   *
    1.10   * This code is free software; you can redistribute it and/or modify it
    1.11 @@ -82,6 +82,21 @@
    1.12  }
    1.13  
    1.14  
    1.15 +#define A0 RA0
    1.16 +#define A1 RA1
    1.17 +#define A2 RA2
    1.18 +#define A3 RA3
    1.19 +#define A4 RA4
    1.20 +#define A5 RA5
    1.21 +#define A6 RA6
    1.22 +#define A7 RA7
    1.23 +#define T0 RT0
    1.24 +#define T1 RT1
    1.25 +#define T2 RT2
    1.26 +#define T3 RT3
    1.27 +#define T8 RT8
    1.28 +#define T9 RT9
    1.29 +
    1.30  // Implementation of Assembler
    1.31  const char *Assembler::ops_name[] = {
    1.32    "special",  "regimm",   "j",      "jal",    "beq",      "bne",      "blez",   "bgtz",

     2.1 --- a/src/cpu/mips/vm/assembler_mips.hpp	Wed Oct 14 17:44:48 2020 +0800
     2.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp	Fri Oct 23 18:04:23 2020 +0800
     2.3 @@ -1,6 +1,6 @@
     2.4  /*
     2.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
     2.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
     2.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     2.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     2.9   *
    2.10   * This code is free software; you can redistribute it and/or modify it
    2.11 @@ -165,7 +165,7 @@
    2.12  
    2.13    Register as_Register()const {
    2.14      assert(is_Register(), "must be a register argument");
    2.15 -    return ::as_Register(A0->encoding() + _number);
    2.16 +    return ::as_Register(RA0->encoding() + _number);
    2.17    }
    2.18    FloatRegister  as_FloatRegister()const {
    2.19      assert(is_FloatRegister(), "must be a float register argument");
    2.20 @@ -1188,7 +1188,7 @@
    2.21  
    2.22    void jalr(Register rd, Register rs) { emit_long( ((int)rs->encoding()<<21) | ((int)rd->encoding()<<11) | jalr_op); has_delay_slot(); }
    2.23    void jalr(Register rs)              { jalr(RA, rs); }
    2.24 -  void jalr()                         { jalr(T9); }
    2.25 +  void jalr()                         { jalr(RT9); }
    2.26  
    2.27    void jr(Register rs) { emit_long(((int)rs->encoding()<<21) | jr_op); has_delay_slot(); }
    2.28  

     3.1 --- a/src/cpu/mips/vm/icBuffer_mips.cpp	Wed Oct 14 17:44:48 2020 +0800
     3.2 +++ b/src/cpu/mips/vm/icBuffer_mips.cpp	Fri Oct 23 18:04:23 2020 +0800
     3.3 @@ -1,6 +1,6 @@
     3.4  /*
     3.5   * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
     3.6 - * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
     3.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     3.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     3.9   *
    3.10   * This code is free software; you can redistribute it and/or modify it
    3.11 @@ -34,6 +34,21 @@
    3.12  #include "oops/oop.inline.hpp"
    3.13  #include "oops/oop.inline2.hpp"
    3.14  
    3.15 +#define A0 RA0
    3.16 +#define A1 RA1
    3.17 +#define A2 RA2
    3.18 +#define A3 RA3
    3.19 +#define A4 RA4
    3.20 +#define A5 RA5
    3.21 +#define A6 RA6
    3.22 +#define A7 RA7
    3.23 +#define T0 RT0
    3.24 +#define T1 RT1
    3.25 +#define T2 RT2
    3.26 +#define T3 RT3
    3.27 +#define T8 RT8
    3.28 +#define T9 RT9
    3.29 +
    3.30  int InlineCacheBuffer::ic_stub_code_size() {
    3.31    return NativeMovConstReg::instruction_size +
    3.32           NativeGeneralJump::instruction_size +

     4.1 --- a/src/cpu/mips/vm/interp_masm_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
     4.2 +++ b/src/cpu/mips/vm/interp_masm_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
     4.3 @@ -1,6 +1,6 @@
     4.4  /*
     4.5   * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
     4.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
     4.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     4.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     4.9   *
    4.10   * This code is free software; you can redistribute it and/or modify it
    4.11 @@ -39,6 +39,20 @@
    4.12  #include "runtime/sharedRuntime.hpp"
    4.13  #include "runtime/thread.inline.hpp"
    4.14  
    4.15 +#define A0 RA0
    4.16 +#define A1 RA1
    4.17 +#define A2 RA2
    4.18 +#define A3 RA3
    4.19 +#define A4 RA4
    4.20 +#define A5 RA5
    4.21 +#define A6 RA6
    4.22 +#define A7 RA7
    4.23 +#define T0 RT0
    4.24 +#define T1 RT1
    4.25 +#define T2 RT2
    4.26 +#define T3 RT3
    4.27 +#define T8 RT8
    4.28 +#define T9 RT9
    4.29  
    4.30  // Implementation of InterpreterMacroAssembler
    4.31  

     5.1 --- a/src/cpu/mips/vm/interpreterRT_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
     5.2 +++ b/src/cpu/mips/vm/interpreterRT_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
     5.3 @@ -1,6 +1,6 @@
     5.4  /*
     5.5   * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved.
     5.6 - * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved.
     5.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     5.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5.9   *
    5.10   * This code is free software; you can redistribute it and/or modify it
    5.11 @@ -37,6 +37,21 @@
    5.12  
    5.13  #define __ _masm->
    5.14  
    5.15 +#define A0 RA0
    5.16 +#define A1 RA1
    5.17 +#define A2 RA2
    5.18 +#define A3 RA3
    5.19 +#define A4 RA4
    5.20 +#define A5 RA5
    5.21 +#define A6 RA6
    5.22 +#define A7 RA7
    5.23 +#define T0 RT0
    5.24 +#define T1 RT1
    5.25 +#define T2 RT2
    5.26 +#define T3 RT3
    5.27 +#define T8 RT8
    5.28 +#define T9 RT9
    5.29 +
    5.30  // Implementation of SignatureHandlerGenerator
    5.31  
    5.32  void InterpreterRuntime::SignatureHandlerGenerator::move(int from_offset, int to_offset) {
    5.33 @@ -122,7 +137,7 @@
    5.34  
    5.35  Register InterpreterRuntime::SignatureHandlerGenerator::from()       { return LVP; }
    5.36  Register InterpreterRuntime::SignatureHandlerGenerator::to()         { return SP; }
    5.37 -Register InterpreterRuntime::SignatureHandlerGenerator::temp()       { return RT4; }
    5.38 +Register InterpreterRuntime::SignatureHandlerGenerator::temp()       { return T8; }
    5.39  
    5.40  // Implementation of SignatureHandlerLibrary
    5.41  

     6.1 --- a/src/cpu/mips/vm/interpreter_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
     6.2 +++ b/src/cpu/mips/vm/interpreter_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
     6.3 @@ -1,6 +1,6 @@
     6.4  /*
     6.5   * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
     6.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
     6.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     6.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     6.9   *
    6.10   * This code is free software; you can redistribute it and/or modify it
    6.11 @@ -52,6 +52,21 @@
    6.12  
    6.13  #define __ _masm->
    6.14  
    6.15 +#define A0 RA0
    6.16 +#define A1 RA1
    6.17 +#define A2 RA2
    6.18 +#define A3 RA3
    6.19 +#define A4 RA4
    6.20 +#define A5 RA5
    6.21 +#define A6 RA6
    6.22 +#define A7 RA7
    6.23 +#define T0 RT0
    6.24 +#define T1 RT1
    6.25 +#define T2 RT2
    6.26 +#define T3 RT3
    6.27 +#define T8 RT8
    6.28 +#define T9 RT9
    6.29 +
    6.30  
    6.31  address AbstractInterpreterGenerator::generate_slow_signature_handler() {
    6.32    address entry = __ pc();

     7.1 --- a/src/cpu/mips/vm/jniFastGetField_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
     7.2 +++ b/src/cpu/mips/vm/jniFastGetField_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
     7.3 @@ -1,6 +1,6 @@
     7.4  /*
     7.5   * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
     7.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
     7.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     7.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     7.9   *
    7.10   * This code is free software; you can redistribute it and/or modify it
    7.11 @@ -32,6 +32,21 @@
    7.12  
    7.13  #define __ masm->
    7.14  
    7.15 +#define A0 RA0
    7.16 +#define A1 RA1
    7.17 +#define A2 RA2
    7.18 +#define A3 RA3
    7.19 +#define A4 RA4
    7.20 +#define A5 RA5
    7.21 +#define A6 RA6
    7.22 +#define A7 RA7
    7.23 +#define T0 RT0
    7.24 +#define T1 RT1
    7.25 +#define T2 RT2
    7.26 +#define T3 RT3
    7.27 +#define T8 RT8
    7.28 +#define T9 RT9
    7.29 +
    7.30  #define BUFFER_SIZE 30*wordSize
    7.31  
    7.32  // Instead of issuing lfence for LoadLoad barrier, we create data dependency

     8.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp	Wed Oct 14 17:44:48 2020 +0800
     8.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp	Fri Oct 23 18:04:23 2020 +0800
     8.3 @@ -47,6 +47,21 @@
     8.4  #include "gc_implementation/g1/heapRegion.hpp"
     8.5  #endif // INCLUDE_ALL_GCS
     8.6  
     8.7 +#define A0 RA0
     8.8 +#define A1 RA1
     8.9 +#define A2 RA2
    8.10 +#define A3 RA3
    8.11 +#define A4 RA4
    8.12 +#define A5 RA5
    8.13 +#define A6 RA6
    8.14 +#define A7 RA7
    8.15 +#define T0 RT0
    8.16 +#define T1 RT1
    8.17 +#define T2 RT2
    8.18 +#define T3 RT3
    8.19 +#define T8 RT8
    8.20 +#define T9 RT9
    8.21 +
    8.22  // Implementation of MacroAssembler
    8.23  
    8.24  intptr_t MacroAssembler::i[32] = {0};

     9.1 --- a/src/cpu/mips/vm/macroAssembler_mips.hpp	Wed Oct 14 17:44:48 2020 +0800
     9.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.hpp	Fri Oct 23 18:04:23 2020 +0800
     9.3 @@ -1,6 +1,6 @@
     9.4  /*
     9.5   * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
     9.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
     9.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
     9.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     9.9   *
    9.10   * This code is free software; you can redistribute it and/or modify it
    9.11 @@ -409,7 +409,7 @@
    9.12      // stack grows down, caller passes positive offset
    9.13      assert(offset > 0, "must bang with negative offset");
    9.14      if (offset <= 32768) {
    9.15 -      sw(A0, SP, -offset);
    9.16 +      sw(RA0, SP, -offset);
    9.17      } else {
    9.18  #ifdef _LP64
    9.19        li(AT, offset);
    9.20 @@ -418,7 +418,7 @@
    9.21        move(AT, offset);
    9.22        sub(AT, SP, AT);
    9.23  #endif
    9.24 -      sw(A0, AT, 0);
    9.25 +      sw(RA0, AT, 0);
    9.26      }
    9.27    }
    9.28  

    10.1 --- a/src/cpu/mips/vm/metaspaceShared_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
    10.2 +++ b/src/cpu/mips/vm/metaspaceShared_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
    10.3 @@ -1,6 +1,6 @@
    10.4  /*
    10.5   * Copyright (c) 2004, 2012, Oracle and/or its affiliates. All rights reserved.
    10.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    10.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    10.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    10.9   *
   10.10   * This code is free software; you can redistribute it and/or modify it
   10.11 @@ -52,6 +52,21 @@
   10.12  
   10.13  #define __ masm->
   10.14  
   10.15 +#define A0 RA0
   10.16 +#define A1 RA1
   10.17 +#define A2 RA2
   10.18 +#define A3 RA3
   10.19 +#define A4 RA4
   10.20 +#define A5 RA5
   10.21 +#define A6 RA6
   10.22 +#define A7 RA7
   10.23 +#define T0 RT0
   10.24 +#define T1 RT1
   10.25 +#define T2 RT2
   10.26 +#define T3 RT3
   10.27 +#define T8 RT8
   10.28 +#define T9 RT9
   10.29 +
   10.30  void MetaspaceShared::generate_vtable_methods(void** vtbl_list,
   10.31                                                     void** vtable,
   10.32                                                     char** md_top,

    11.1 --- a/src/cpu/mips/vm/methodHandles_mips.cpp	Wed Oct 14 17:44:48 2020 +0800
    11.2 +++ b/src/cpu/mips/vm/methodHandles_mips.cpp	Fri Oct 23 18:04:23 2020 +0800
    11.3 @@ -1,6 +1,6 @@
    11.4  /*
    11.5   * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
    11.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    11.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    11.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    11.9   *
   11.10   * This code is free software; you can redistribute it and/or modify it
   11.11 @@ -32,6 +32,21 @@
   11.12  
   11.13  #define __ _masm->
   11.14  
   11.15 +#define A0 RA0
   11.16 +#define A1 RA1
   11.17 +#define A2 RA2
   11.18 +#define A3 RA3
   11.19 +#define A4 RA4
   11.20 +#define A5 RA5
   11.21 +#define A6 RA6
   11.22 +#define A7 RA7
   11.23 +#define T0 RT0
   11.24 +#define T1 RT1
   11.25 +#define T2 RT2
   11.26 +#define T3 RT3
   11.27 +#define T8 RT8
   11.28 +#define T9 RT9
   11.29 +
   11.30  #ifdef PRODUCT
   11.31  #define BLOCK_COMMENT(str) /* nothing */
   11.32  #define STOP(error) stop(error)

    12.1 --- a/src/cpu/mips/vm/mips_64.ad	Wed Oct 14 17:44:48 2020 +0800
    12.2 +++ b/src/cpu/mips/vm/mips_64.ad	Fri Oct 23 18:04:23 2020 +0800
    12.3 @@ -1,6 +1,6 @@
    12.4  //
    12.5  // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
    12.6 -// Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    12.7 +// Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    12.8  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    12.9  //
   12.10  // This code is free software; you can redistribute it and/or modify it
   12.11 @@ -529,6 +529,21 @@
   12.12  
   12.13  #define __ _masm.
   12.14  
   12.15 +#define A0 RA0
   12.16 +#define A1 RA1
   12.17 +#define A2 RA2
   12.18 +#define A3 RA3
   12.19 +#define A4 RA4
   12.20 +#define A5 RA5
   12.21 +#define A6 RA6
   12.22 +#define A7 RA7
   12.23 +#define T0 RT0
   12.24 +#define T1 RT1
   12.25 +#define T2 RT2
   12.26 +#define T3 RT3
   12.27 +#define T8 RT8
   12.28 +#define T9 RT9
   12.29 +
   12.30  
   12.31  // Emit exception handler code.
   12.32  // Stuff framesize into a register and call a VM stub routine.

    13.1 --- a/src/cpu/mips/vm/nativeInst_mips.cpp	Wed Oct 14 17:44:48 2020 +0800
    13.2 +++ b/src/cpu/mips/vm/nativeInst_mips.cpp	Fri Oct 23 18:04:23 2020 +0800
    13.3 @@ -1,6 +1,6 @@
    13.4  /*
    13.5   * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
    13.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    13.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    13.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    13.9   *
   13.10   * This code is free software; you can redistribute it and/or modify it
   13.11 @@ -38,6 +38,21 @@
   13.12  
   13.13  #include <sys/mman.h>
   13.14  
   13.15 +#define A0 RA0
   13.16 +#define A1 RA1
   13.17 +#define A2 RA2
   13.18 +#define A3 RA3
   13.19 +#define A4 RA4
   13.20 +#define A5 RA5
   13.21 +#define A6 RA6
   13.22 +#define A7 RA7
   13.23 +#define T0 RT0
   13.24 +#define T1 RT1
   13.25 +#define T2 RT2
   13.26 +#define T3 RT3
   13.27 +#define T8 RT8
   13.28 +#define T9 RT9
   13.29 +
   13.30  void NativeInstruction::wrote(int offset) {
   13.31    ICache::invalidate_word(addr_at(offset));
   13.32  }

    14.1 --- a/src/cpu/mips/vm/register_mips.hpp	Wed Oct 14 17:44:48 2020 +0800
    14.2 +++ b/src/cpu/mips/vm/register_mips.hpp	Fri Oct 23 18:04:23 2020 +0800
    14.3 @@ -1,6 +1,6 @@
    14.4  /*
    14.5   * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
    14.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    14.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    14.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    14.9   *
   14.10   * This code is free software; you can redistribute it and/or modify it
   14.11 @@ -178,18 +178,18 @@
   14.12  #define AT ((Register)(i1_RegisterEnumValue))
   14.13  #define V0 ((Register)(i2_RegisterEnumValue))
   14.14  #define V1 ((Register)(i3_RegisterEnumValue))
   14.15 -#define A0 ((Register)(i4_RegisterEnumValue))
   14.16 -#define A1 ((Register)(i5_RegisterEnumValue))
   14.17 -#define A2 ((Register)(i6_RegisterEnumValue))
   14.18 -#define A3 ((Register)(i7_RegisterEnumValue))
   14.19 -#define A4 ((Register)(i8_RegisterEnumValue))
   14.20 -#define A5 ((Register)(i9_RegisterEnumValue))
   14.21 -#define A6 ((Register)(i10_RegisterEnumValue))
   14.22 -#define A7 ((Register)(i11_RegisterEnumValue))
   14.23 -#define T0 ((Register)(i12_RegisterEnumValue))
   14.24 -#define T1 ((Register)(i13_RegisterEnumValue))
   14.25 -#define T2 ((Register)(i14_RegisterEnumValue))
   14.26 -#define T3 ((Register)(i15_RegisterEnumValue))
   14.27 +#define RA0 ((Register)(i4_RegisterEnumValue))
   14.28 +#define RA1 ((Register)(i5_RegisterEnumValue))
   14.29 +#define RA2 ((Register)(i6_RegisterEnumValue))
   14.30 +#define RA3 ((Register)(i7_RegisterEnumValue))
   14.31 +#define RA4 ((Register)(i8_RegisterEnumValue))
   14.32 +#define RA5 ((Register)(i9_RegisterEnumValue))
   14.33 +#define RA6 ((Register)(i10_RegisterEnumValue))
   14.34 +#define RA7 ((Register)(i11_RegisterEnumValue))
   14.35 +#define RT0 ((Register)(i12_RegisterEnumValue))
   14.36 +#define RT1 ((Register)(i13_RegisterEnumValue))
   14.37 +#define RT2 ((Register)(i14_RegisterEnumValue))
   14.38 +#define RT3 ((Register)(i15_RegisterEnumValue))
   14.39  #define S0 ((Register)(i16_RegisterEnumValue))
   14.40  #define S1 ((Register)(i17_RegisterEnumValue))
   14.41  #define S2 ((Register)(i18_RegisterEnumValue))
   14.42 @@ -198,8 +198,8 @@
   14.43  #define S5 ((Register)(i21_RegisterEnumValue))
   14.44  #define S6 ((Register)(i22_RegisterEnumValue))
   14.45  #define S7 ((Register)(i23_RegisterEnumValue))
   14.46 -#define T8 ((Register)(i24_RegisterEnumValue))
   14.47 -#define T9 ((Register)(i25_RegisterEnumValue))
   14.48 +#define RT8 ((Register)(i24_RegisterEnumValue))
   14.49 +#define RT9 ((Register)(i25_RegisterEnumValue))
   14.50  #define K0 ((Register)(i26_RegisterEnumValue))
   14.51  #define K1 ((Register)(i27_RegisterEnumValue))
   14.52  #define GP ((Register)(i28_RegisterEnumValue))
   14.53 @@ -208,18 +208,20 @@
   14.54  #define S8 ((Register)(i30_RegisterEnumValue))
   14.55  #define RA ((Register)(i31_RegisterEnumValue))
   14.56  
   14.57 -#define c_rarg0       T0
   14.58 -#define c_rarg1       T1
   14.59 +#define c_rarg0       RT0
   14.60 +#define c_rarg1       RT1
   14.61  #define Rmethod       S3
   14.62  #define Rsender       S4
   14.63  #define Rnext         S1
   14.64  
   14.65 +/*
   14.66  #define RT0       T0
   14.67  #define RT1       T1
   14.68  #define RT2       T2
   14.69  #define RT3       T3
   14.70  #define RT4       T8
   14.71  #define RT5       T9
   14.72 +*/
   14.73  #endif //_LP64
   14.74  
   14.75  

    15.1 --- a/src/cpu/mips/vm/runtime_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
    15.2 +++ b/src/cpu/mips/vm/runtime_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
    15.3 @@ -1,6 +1,6 @@
    15.4  /*
    15.5   * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
    15.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    15.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    15.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    15.9   *
   15.10   * This code is free software; you can redistribute it and/or modify it
   15.11 @@ -41,6 +41,21 @@
   15.12  
   15.13  #define __ masm->
   15.14  
   15.15 +#define A0 RA0
   15.16 +#define A1 RA1
   15.17 +#define A2 RA2
   15.18 +#define A3 RA3
   15.19 +#define A4 RA4
   15.20 +#define A5 RA5
   15.21 +#define A6 RA6
   15.22 +#define A7 RA7
   15.23 +#define T0 RT0
   15.24 +#define T1 RT1
   15.25 +#define T2 RT2
   15.26 +#define T3 RT3
   15.27 +#define T8 RT8
   15.28 +#define T9 RT9
   15.29 +
   15.30  //-------------- generate_exception_blob -----------
   15.31  // creates _exception_blob.
   15.32  // The exception blob is jumped to from a compiled method.

    16.1 --- a/src/cpu/mips/vm/sharedRuntime_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
    16.2 +++ b/src/cpu/mips/vm/sharedRuntime_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
    16.3 @@ -1,6 +1,6 @@
    16.4  /*
    16.5   * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
    16.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    16.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    16.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    16.9   *
   16.10   * This code is free software; you can redistribute it and/or modify it
   16.11 @@ -46,6 +46,21 @@
   16.12  
   16.13  #define __ masm->
   16.14  
   16.15 +#define A0 RA0
   16.16 +#define A1 RA1
   16.17 +#define A2 RA2
   16.18 +#define A3 RA3
   16.19 +#define A4 RA4
   16.20 +#define A5 RA5
   16.21 +#define A6 RA6
   16.22 +#define A7 RA7
   16.23 +#define T0 RT0
   16.24 +#define T1 RT1
   16.25 +#define T2 RT2
   16.26 +#define T3 RT3
   16.27 +#define T8 RT8
   16.28 +#define T9 RT9
   16.29 +
   16.30  const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
   16.31  
   16.32  class RegisterSaver {

    17.1 --- a/src/cpu/mips/vm/stubGenerator_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
    17.2 +++ b/src/cpu/mips/vm/stubGenerator_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
    17.3 @@ -1,6 +1,6 @@
    17.4  /*
    17.5   * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
    17.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    17.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    17.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    17.9   *
   17.10   * This code is free software; you can redistribute it and/or modify it
   17.11 @@ -49,6 +49,22 @@
   17.12  // see the comment in stubRoutines.hpp
   17.13  
   17.14  #define __ _masm->
   17.15 +
   17.16 +#define A0 RA0
   17.17 +#define A1 RA1
   17.18 +#define A2 RA2
   17.19 +#define A3 RA3
   17.20 +#define A4 RA4
   17.21 +#define A5 RA5
   17.22 +#define A6 RA6
   17.23 +#define A7 RA7
   17.24 +#define T0 RT0
   17.25 +#define T1 RT1
   17.26 +#define T2 RT2
   17.27 +#define T3 RT3
   17.28 +#define T8 RT8
   17.29 +#define T9 RT9
   17.30 +
   17.31  #define TIMES_OOP (UseCompressedOops ? Address::times_4 : Address::times_8)
   17.32  //#define a__ ((Assembler*)_masm)->
   17.33  

    18.1 --- a/src/cpu/mips/vm/templateInterpreter_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
    18.2 +++ b/src/cpu/mips/vm/templateInterpreter_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
    18.3 @@ -48,6 +48,21 @@
    18.4  
    18.5  #define __ _masm->
    18.6  
    18.7 +#define A0 RA0
    18.8 +#define A1 RA1
    18.9 +#define A2 RA2
   18.10 +#define A3 RA3
   18.11 +#define A4 RA4
   18.12 +#define A5 RA5
   18.13 +#define A6 RA6
   18.14 +#define A7 RA7
   18.15 +#define T0 RT0
   18.16 +#define T1 RT1
   18.17 +#define T2 RT2
   18.18 +#define T3 RT3
   18.19 +#define T8 RT8
   18.20 +#define T9 RT9
   18.21 +
   18.22  #ifndef CC_INTERP
   18.23  
   18.24  // asm based interpreter deoptimization helpers
   18.25 @@ -1046,7 +1061,7 @@
   18.26    // work registers
   18.27    const Register method = Rmethod;
   18.28    //const Register thread = T2;
   18.29 -  const Register t      = RT4;
   18.30 +  const Register t      = T8;
   18.31  
   18.32    __ get_method(method);
   18.33    __ verify_oop(method);

    19.1 --- a/src/cpu/mips/vm/templateTable_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
    19.2 +++ b/src/cpu/mips/vm/templateTable_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
    19.3 @@ -1,6 +1,6 @@
    19.4  /*
    19.5   * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
    19.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    19.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    19.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    19.9   *
   19.10   * This code is free software; you can redistribute it and/or modify it
   19.11 @@ -43,6 +43,21 @@
   19.12  
   19.13  #define __ _masm->
   19.14  
   19.15 +#define A0 RA0
   19.16 +#define A1 RA1
   19.17 +#define A2 RA2
   19.18 +#define A3 RA3
   19.19 +#define A4 RA4
   19.20 +#define A5 RA5
   19.21 +#define A6 RA6
   19.22 +#define A7 RA7
   19.23 +#define T0 RT0
   19.24 +#define T1 RT1
   19.25 +#define T2 RT2
   19.26 +#define T3 RT3
   19.27 +#define T8 RT8
   19.28 +#define T9 RT9
   19.29 +
   19.30  // Platform-dependent initialization
   19.31  
   19.32  void TemplateTable::pd_initialize() {

    20.1 --- a/src/cpu/mips/vm/vm_version_mips.cpp	Wed Oct 14 17:44:48 2020 +0800
    20.2 +++ b/src/cpu/mips/vm/vm_version_mips.cpp	Fri Oct 23 18:04:23 2020 +0800
    20.3 @@ -34,6 +34,8 @@
    20.4  # include "os_linux.inline.hpp"
    20.5  #endif
    20.6  
    20.7 +#define A0 RA0
    20.8 +
    20.9  int VM_Version::_cpuFeatures;
   20.10  const char* VM_Version::_features_str = "";
   20.11  VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };

    21.1 --- a/src/cpu/mips/vm/vtableStubs_mips_64.cpp	Wed Oct 14 17:44:48 2020 +0800
    21.2 +++ b/src/cpu/mips/vm/vtableStubs_mips_64.cpp	Fri Oct 23 18:04:23 2020 +0800
    21.3 @@ -1,6 +1,6 @@
    21.4  /*
    21.5   * Copyright (c) 2003, 2014, Oracle and/or its affiliates. All rights reserved.
    21.6 - * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
    21.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    21.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    21.9   *
   21.10   * This code is free software; you can redistribute it and/or modify it
   21.11 @@ -42,6 +42,21 @@
   21.12  
   21.13  #define __ masm->
   21.14  
   21.15 +#define A0 RA0
   21.16 +#define A1 RA1
   21.17 +#define A2 RA2
   21.18 +#define A3 RA3
   21.19 +#define A4 RA4
   21.20 +#define A5 RA5
   21.21 +#define A6 RA6
   21.22 +#define A7 RA7
   21.23 +#define T0 RT0
   21.24 +#define T1 RT1
   21.25 +#define T2 RT2
   21.26 +#define T3 RT3
   21.27 +#define T8 RT8
   21.28 +#define T9 RT9
   21.29 +
   21.30  #ifndef PRODUCT
   21.31  extern "C" void bad_compiled_vtable_index(JavaThread* thread,
   21.32                                            oop receiver,

    22.1 --- a/src/os_cpu/linux_mips/vm/assembler_linux_mips.cpp	Wed Oct 14 17:44:48 2020 +0800
    22.2 +++ b/src/os_cpu/linux_mips/vm/assembler_linux_mips.cpp	Fri Oct 23 18:04:23 2020 +0800
    22.3 @@ -1,6 +1,6 @@
    22.4  /*
    22.5   * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
    22.6 - * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved.
    22.7 + * Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
    22.8   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    22.9   *
   22.10   * This code is free software; you can redistribute it and/or modify it
   22.11 @@ -29,6 +29,21 @@
   22.12  #include "runtime/os.hpp"
   22.13  #include "runtime/threadLocalStorage.hpp"
   22.14  
   22.15 +#define A0 RA0
   22.16 +#define A1 RA1
   22.17 +#define A2 RA2
   22.18 +#define A3 RA3
   22.19 +#define A4 RA4
   22.20 +#define A5 RA5
   22.21 +#define A6 RA6
   22.22 +#define A7 RA7
   22.23 +#define T0 RT0
   22.24 +#define T1 RT1
   22.25 +#define T2 RT2
   22.26 +#define T3 RT3
   22.27 +#define T8 RT8
   22.28 +#define T9 RT9
   22.29 +
   22.30  void MacroAssembler::int3() {
   22.31  #ifndef _LP64
   22.32    int imm = (intptr_t)CAST_FROM_FN_PTR(address, os::breakpoint);