1.1 --- a/src/cpu/mips/vm/mips_64.ad Wed Oct 14 17:44:48 2020 +0800
1.2 +++ b/src/cpu/mips/vm/mips_64.ad Fri Oct 23 18:04:23 2020 +0800
1.3 @@ -1,6 +1,6 @@
1.4 //
1.5 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 -// Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
1.7 +// Copyright (c) 2015, 2020, Loongson Technology. All rights reserved.
1.8 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.9 //
1.10 // This code is free software; you can redistribute it and/or modify it
1.11 @@ -529,6 +529,21 @@
1.12
1.13 #define __ _masm.
1.14
1.15 +#define A0 RA0
1.16 +#define A1 RA1
1.17 +#define A2 RA2
1.18 +#define A3 RA3
1.19 +#define A4 RA4
1.20 +#define A5 RA5
1.21 +#define A6 RA6
1.22 +#define A7 RA7
1.23 +#define T0 RT0
1.24 +#define T1 RT1
1.25 +#define T2 RT2
1.26 +#define T3 RT3
1.27 +#define T8 RT8
1.28 +#define T9 RT9
1.29 +
1.30
1.31 // Emit exception handler code.
1.32 // Stuff framesize into a register and call a VM stub routine.
