Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/sparc/vm/sparc.ad	Mon Oct 01 14:50:10 2012 -0700
     1.2 +++ b/src/cpu/sparc/vm/sparc.ad	Tue Oct 02 12:25:13 2012 -0700
     1.3 @@ -1870,6 +1870,11 @@
     1.4    return Op_RegD;
     1.5  }
     1.6  
     1.7 +const int Matcher::vector_shift_count_ideal_reg(int size) {
     1.8 +  fatal("vector shift is not supported");
     1.9 +  return Node::NotAMachineReg;
    1.10 +}
    1.11 +
    1.12  // Limits on vector size (number of elements) loaded into vector.
    1.13  const int Matcher::max_vector_size(const BasicType bt) {
    1.14    assert(is_java_primitive(bt), "only primitive type vectors");

     2.1 --- a/src/cpu/x86/vm/x86.ad	Mon Oct 01 14:50:10 2012 -0700
     2.2 +++ b/src/cpu/x86/vm/x86.ad	Tue Oct 02 12:25:13 2012 -0700
     2.3 @@ -571,6 +571,11 @@
     2.4    return 0;
     2.5  }
     2.6  
     2.7 +// Only lowest bits of xmm reg are used for vector shift count.
     2.8 +const int Matcher::vector_shift_count_ideal_reg(int size) {
     2.9 +  return Op_VecS;
    2.10 +}
    2.11 +
    2.12  // x86 supports misaligned vectors store/load.
    2.13  const bool Matcher::misaligned_vectors_ok() {
    2.14    return !AlignVector; // can be changed by flag
    2.15 @@ -3758,10 +3763,24 @@
    2.16    ins_pipe( pipe_slow );
    2.17  %}
    2.18  
    2.19 +// ------------------------------ Shift ---------------------------------------
    2.20 +
    2.21 +// Left and right shift count vectors are the same on x86
    2.22 +// (only lowest bits of xmm reg are used for count).
    2.23 +instruct vshiftcnt(vecS dst, rRegI cnt) %{
    2.24 +  match(Set dst (LShiftCntV cnt));
    2.25 +  match(Set dst (RShiftCntV cnt));
    2.26 +  format %{ "movd    $dst,$cnt\t! load shift count" %}
    2.27 +  ins_encode %{
    2.28 +    __ movdl($dst$$XMMRegister, $cnt$$Register);
    2.29 +  %}
    2.30 +  ins_pipe( pipe_slow );
    2.31 +%}
    2.32 +
    2.33  // ------------------------------ LeftShift -----------------------------------
    2.34  
    2.35  // Shorts/Chars vector left shift
    2.36 -instruct vsll2S(vecS dst, regF shift) %{
    2.37 +instruct vsll2S(vecS dst, vecS shift) %{
    2.38    predicate(n->as_Vector()->length() == 2);
    2.39    match(Set dst (LShiftVS dst shift));
    2.40    format %{ "psllw   $dst,$shift\t! left shift packed2S" %}
    2.41 @@ -3781,7 +3800,7 @@
    2.42    ins_pipe( pipe_slow );
    2.43  %}
    2.44  
    2.45 -instruct vsll2S_reg(vecS dst, vecS src, regF shift) %{
    2.46 +instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{
    2.47    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
    2.48    match(Set dst (LShiftVS src shift));
    2.49    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed2S" %}
    2.50 @@ -3803,7 +3822,7 @@
    2.51    ins_pipe( pipe_slow );
    2.52  %}
    2.53  
    2.54 -instruct vsll4S(vecD dst, regF shift) %{
    2.55 +instruct vsll4S(vecD dst, vecS shift) %{
    2.56    predicate(n->as_Vector()->length() == 4);
    2.57    match(Set dst (LShiftVS dst shift));
    2.58    format %{ "psllw   $dst,$shift\t! left shift packed4S" %}
    2.59 @@ -3823,7 +3842,7 @@
    2.60    ins_pipe( pipe_slow );
    2.61  %}
    2.62  
    2.63 -instruct vsll4S_reg(vecD dst, vecD src, regF shift) %{
    2.64 +instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{
    2.65    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
    2.66    match(Set dst (LShiftVS src shift));
    2.67    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed4S" %}
    2.68 @@ -3845,7 +3864,7 @@
    2.69    ins_pipe( pipe_slow );
    2.70  %}
    2.71  
    2.72 -instruct vsll8S(vecX dst, regF shift) %{
    2.73 +instruct vsll8S(vecX dst, vecS shift) %{
    2.74    predicate(n->as_Vector()->length() == 8);
    2.75    match(Set dst (LShiftVS dst shift));
    2.76    format %{ "psllw   $dst,$shift\t! left shift packed8S" %}
    2.77 @@ -3865,7 +3884,7 @@
    2.78    ins_pipe( pipe_slow );
    2.79  %}
    2.80  
    2.81 -instruct vsll8S_reg(vecX dst, vecX src, regF shift) %{
    2.82 +instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{
    2.83    predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
    2.84    match(Set dst (LShiftVS src shift));
    2.85    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed8S" %}
    2.86 @@ -3887,7 +3906,7 @@
    2.87    ins_pipe( pipe_slow );
    2.88  %}
    2.89  
    2.90 -instruct vsll16S_reg(vecY dst, vecY src, regF shift) %{
    2.91 +instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{
    2.92    predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
    2.93    match(Set dst (LShiftVS src shift));
    2.94    format %{ "vpsllw  $dst,$src,$shift\t! left shift packed16S" %}
    2.95 @@ -3910,7 +3929,7 @@
    2.96  %}
    2.97  
    2.98  // Integers vector left shift
    2.99 -instruct vsll2I(vecD dst, regF shift) %{
   2.100 +instruct vsll2I(vecD dst, vecS shift) %{
   2.101    predicate(n->as_Vector()->length() == 2);
   2.102    match(Set dst (LShiftVI dst shift));
   2.103    format %{ "pslld   $dst,$shift\t! left shift packed2I" %}
   2.104 @@ -3930,7 +3949,7 @@
   2.105    ins_pipe( pipe_slow );
   2.106  %}
   2.107  
   2.108 -instruct vsll2I_reg(vecD dst, vecD src, regF shift) %{
   2.109 +instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{
   2.110    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   2.111    match(Set dst (LShiftVI src shift));
   2.112    format %{ "vpslld  $dst,$src,$shift\t! left shift packed2I" %}
   2.113 @@ -3952,7 +3971,7 @@
   2.114    ins_pipe( pipe_slow );
   2.115  %}
   2.116  
   2.117 -instruct vsll4I(vecX dst, regF shift) %{
   2.118 +instruct vsll4I(vecX dst, vecS shift) %{
   2.119    predicate(n->as_Vector()->length() == 4);
   2.120    match(Set dst (LShiftVI dst shift));
   2.121    format %{ "pslld   $dst,$shift\t! left shift packed4I" %}
   2.122 @@ -3972,7 +3991,7 @@
   2.123    ins_pipe( pipe_slow );
   2.124  %}
   2.125  
   2.126 -instruct vsll4I_reg(vecX dst, vecX src, regF shift) %{
   2.127 +instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{
   2.128    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   2.129    match(Set dst (LShiftVI src shift));
   2.130    format %{ "vpslld  $dst,$src,$shift\t! left shift packed4I" %}
   2.131 @@ -3994,7 +4013,7 @@
   2.132    ins_pipe( pipe_slow );
   2.133  %}
   2.134  
   2.135 -instruct vsll8I_reg(vecY dst, vecY src, regF shift) %{
   2.136 +instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{
   2.137    predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
   2.138    match(Set dst (LShiftVI src shift));
   2.139    format %{ "vpslld  $dst,$src,$shift\t! left shift packed8I" %}
   2.140 @@ -4017,7 +4036,7 @@
   2.141  %}
   2.142  
   2.143  // Longs vector left shift
   2.144 -instruct vsll2L(vecX dst, regF shift) %{
   2.145 +instruct vsll2L(vecX dst, vecS shift) %{
   2.146    predicate(n->as_Vector()->length() == 2);
   2.147    match(Set dst (LShiftVL dst shift));
   2.148    format %{ "psllq   $dst,$shift\t! left shift packed2L" %}
   2.149 @@ -4037,7 +4056,7 @@
   2.150    ins_pipe( pipe_slow );
   2.151  %}
   2.152  
   2.153 -instruct vsll2L_reg(vecX dst, vecX src, regF shift) %{
   2.154 +instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{
   2.155    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   2.156    match(Set dst (LShiftVL src shift));
   2.157    format %{ "vpsllq  $dst,$src,$shift\t! left shift packed2L" %}
   2.158 @@ -4059,7 +4078,7 @@
   2.159    ins_pipe( pipe_slow );
   2.160  %}
   2.161  
   2.162 -instruct vsll4L_reg(vecY dst, vecY src, regF shift) %{
   2.163 +instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{
   2.164    predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
   2.165    match(Set dst (LShiftVL src shift));
   2.166    format %{ "vpsllq  $dst,$src,$shift\t! left shift packed4L" %}
   2.167 @@ -4088,7 +4107,7 @@
   2.168  // sign extension before a shift.
   2.169  
   2.170  // Integers vector logical right shift
   2.171 -instruct vsrl2I(vecD dst, regF shift) %{
   2.172 +instruct vsrl2I(vecD dst, vecS shift) %{
   2.173    predicate(n->as_Vector()->length() == 2);
   2.174    match(Set dst (URShiftVI dst shift));
   2.175    format %{ "psrld   $dst,$shift\t! logical right shift packed2I" %}
   2.176 @@ -4108,7 +4127,7 @@
   2.177    ins_pipe( pipe_slow );
   2.178  %}
   2.179  
   2.180 -instruct vsrl2I_reg(vecD dst, vecD src, regF shift) %{
   2.181 +instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{
   2.182    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   2.183    match(Set dst (URShiftVI src shift));
   2.184    format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed2I" %}
   2.185 @@ -4130,7 +4149,7 @@
   2.186    ins_pipe( pipe_slow );
   2.187  %}
   2.188  
   2.189 -instruct vsrl4I(vecX dst, regF shift) %{
   2.190 +instruct vsrl4I(vecX dst, vecS shift) %{
   2.191    predicate(n->as_Vector()->length() == 4);
   2.192    match(Set dst (URShiftVI dst shift));
   2.193    format %{ "psrld   $dst,$shift\t! logical right shift packed4I" %}
   2.194 @@ -4150,7 +4169,7 @@
   2.195    ins_pipe( pipe_slow );
   2.196  %}
   2.197  
   2.198 -instruct vsrl4I_reg(vecX dst, vecX src, regF shift) %{
   2.199 +instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{
   2.200    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   2.201    match(Set dst (URShiftVI src shift));
   2.202    format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed4I" %}
   2.203 @@ -4172,7 +4191,7 @@
   2.204    ins_pipe( pipe_slow );
   2.205  %}
   2.206  
   2.207 -instruct vsrl8I_reg(vecY dst, vecY src, regF shift) %{
   2.208 +instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{
   2.209    predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
   2.210    match(Set dst (URShiftVI src shift));
   2.211    format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed8I" %}
   2.212 @@ -4195,7 +4214,7 @@
   2.213  %}
   2.214  
   2.215  // Longs vector logical right shift
   2.216 -instruct vsrl2L(vecX dst, regF shift) %{
   2.217 +instruct vsrl2L(vecX dst, vecS shift) %{
   2.218    predicate(n->as_Vector()->length() == 2);
   2.219    match(Set dst (URShiftVL dst shift));
   2.220    format %{ "psrlq   $dst,$shift\t! logical right shift packed2L" %}
   2.221 @@ -4215,7 +4234,7 @@
   2.222    ins_pipe( pipe_slow );
   2.223  %}
   2.224  
   2.225 -instruct vsrl2L_reg(vecX dst, vecX src, regF shift) %{
   2.226 +instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{
   2.227    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   2.228    match(Set dst (URShiftVL src shift));
   2.229    format %{ "vpsrlq  $dst,$src,$shift\t! logical right shift packed2L" %}
   2.230 @@ -4237,7 +4256,7 @@
   2.231    ins_pipe( pipe_slow );
   2.232  %}
   2.233  
   2.234 -instruct vsrl4L_reg(vecY dst, vecY src, regF shift) %{
   2.235 +instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{
   2.236    predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
   2.237    match(Set dst (URShiftVL src shift));
   2.238    format %{ "vpsrlq  $dst,$src,$shift\t! logical right shift packed4L" %}
   2.239 @@ -4262,7 +4281,7 @@
   2.240  // ------------------- ArithmeticRightShift -----------------------------------
   2.241  
   2.242  // Shorts/Chars vector arithmetic right shift
   2.243 -instruct vsra2S(vecS dst, regF shift) %{
   2.244 +instruct vsra2S(vecS dst, vecS shift) %{
   2.245    predicate(n->as_Vector()->length() == 2);
   2.246    match(Set dst (RShiftVS dst shift));
   2.247    format %{ "psraw   $dst,$shift\t! arithmetic right shift packed2S" %}
   2.248 @@ -4282,7 +4301,7 @@
   2.249    ins_pipe( pipe_slow );
   2.250  %}
   2.251  
   2.252 -instruct vsra2S_reg(vecS dst, vecS src, regF shift) %{
   2.253 +instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{
   2.254    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   2.255    match(Set dst (RShiftVS src shift));
   2.256    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed2S" %}
   2.257 @@ -4304,7 +4323,7 @@
   2.258    ins_pipe( pipe_slow );
   2.259  %}
   2.260  
   2.261 -instruct vsra4S(vecD dst, regF shift) %{
   2.262 +instruct vsra4S(vecD dst, vecS shift) %{
   2.263    predicate(n->as_Vector()->length() == 4);
   2.264    match(Set dst (RShiftVS dst shift));
   2.265    format %{ "psraw   $dst,$shift\t! arithmetic right shift packed4S" %}
   2.266 @@ -4324,7 +4343,7 @@
   2.267    ins_pipe( pipe_slow );
   2.268  %}
   2.269  
   2.270 -instruct vsra4S_reg(vecD dst, vecD src, regF shift) %{
   2.271 +instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{
   2.272    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   2.273    match(Set dst (RShiftVS src shift));
   2.274    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed4S" %}
   2.275 @@ -4346,7 +4365,7 @@
   2.276    ins_pipe( pipe_slow );
   2.277  %}
   2.278  
   2.279 -instruct vsra8S(vecX dst, regF shift) %{
   2.280 +instruct vsra8S(vecX dst, vecS shift) %{
   2.281    predicate(n->as_Vector()->length() == 8);
   2.282    match(Set dst (RShiftVS dst shift));
   2.283    format %{ "psraw   $dst,$shift\t! arithmetic right shift packed8S" %}
   2.284 @@ -4366,7 +4385,7 @@
   2.285    ins_pipe( pipe_slow );
   2.286  %}
   2.287  
   2.288 -instruct vsra8S_reg(vecX dst, vecX src, regF shift) %{
   2.289 +instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{
   2.290    predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
   2.291    match(Set dst (RShiftVS src shift));
   2.292    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed8S" %}
   2.293 @@ -4388,7 +4407,7 @@
   2.294    ins_pipe( pipe_slow );
   2.295  %}
   2.296  
   2.297 -instruct vsra16S_reg(vecY dst, vecY src, regF shift) %{
   2.298 +instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{
   2.299    predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
   2.300    match(Set dst (RShiftVS src shift));
   2.301    format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed16S" %}
   2.302 @@ -4411,7 +4430,7 @@
   2.303  %}
   2.304  
   2.305  // Integers vector arithmetic right shift
   2.306 -instruct vsra2I(vecD dst, regF shift) %{
   2.307 +instruct vsra2I(vecD dst, vecS shift) %{
   2.308    predicate(n->as_Vector()->length() == 2);
   2.309    match(Set dst (RShiftVI dst shift));
   2.310    format %{ "psrad   $dst,$shift\t! arithmetic right shift packed2I" %}
   2.311 @@ -4431,7 +4450,7 @@
   2.312    ins_pipe( pipe_slow );
   2.313  %}
   2.314  
   2.315 -instruct vsra2I_reg(vecD dst, vecD src, regF shift) %{
   2.316 +instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{
   2.317    predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   2.318    match(Set dst (RShiftVI src shift));
   2.319    format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed2I" %}
   2.320 @@ -4453,7 +4472,7 @@
   2.321    ins_pipe( pipe_slow );
   2.322  %}
   2.323  
   2.324 -instruct vsra4I(vecX dst, regF shift) %{
   2.325 +instruct vsra4I(vecX dst, vecS shift) %{
   2.326    predicate(n->as_Vector()->length() == 4);
   2.327    match(Set dst (RShiftVI dst shift));
   2.328    format %{ "psrad   $dst,$shift\t! arithmetic right shift packed4I" %}
   2.329 @@ -4473,7 +4492,7 @@
   2.330    ins_pipe( pipe_slow );
   2.331  %}
   2.332  
   2.333 -instruct vsra4I_reg(vecX dst, vecX src, regF shift) %{
   2.334 +instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{
   2.335    predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   2.336    match(Set dst (RShiftVI src shift));
   2.337    format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed4I" %}
   2.338 @@ -4495,7 +4514,7 @@
   2.339    ins_pipe( pipe_slow );
   2.340  %}
   2.341  
   2.342 -instruct vsra8I_reg(vecY dst, vecY src, regF shift) %{
   2.343 +instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{
   2.344    predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
   2.345    match(Set dst (RShiftVI src shift));
   2.346    format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed8I" %}

     3.1 --- a/src/share/vm/adlc/formssel.cpp	Mon Oct 01 14:50:10 2012 -0700
     3.2 +++ b/src/share/vm/adlc/formssel.cpp	Tue Oct 02 12:25:13 2012 -0700
     3.3 @@ -4049,6 +4049,7 @@
     3.4      "MulVS","MulVI","MulVF","MulVD",
     3.5      "DivVF","DivVD",
     3.6      "AndV" ,"XorV" ,"OrV",
     3.7 +    "LShiftCntV","RShiftCntV",
     3.8      "LShiftVB","LShiftVS","LShiftVI","LShiftVL",
     3.9      "RShiftVB","RShiftVS","RShiftVI","RShiftVL",
    3.10      "URShiftVB","URShiftVS","URShiftVI","URShiftVL",

     4.1 --- a/src/share/vm/opto/classes.hpp	Mon Oct 01 14:50:10 2012 -0700
     4.2 +++ b/src/share/vm/opto/classes.hpp	Tue Oct 02 12:25:13 2012 -0700
     4.3 @@ -268,6 +268,8 @@
     4.4  macro(MulVD)
     4.5  macro(DivVF)
     4.6  macro(DivVD)
     4.7 +macro(LShiftCntV)
     4.8 +macro(RShiftCntV)
     4.9  macro(LShiftVB)
    4.10  macro(LShiftVS)
    4.11  macro(LShiftVI)

     5.1 --- a/src/share/vm/opto/matcher.hpp	Mon Oct 01 14:50:10 2012 -0700
     5.2 +++ b/src/share/vm/opto/matcher.hpp	Tue Oct 02 12:25:13 2012 -0700
     5.3 @@ -261,6 +261,7 @@
     5.4  
     5.5    // Vector ideal reg
     5.6    static const int vector_ideal_reg(int len);
     5.7 +  static const int vector_shift_count_ideal_reg(int len);
     5.8  
     5.9    // CPU supports misaligned vectors store/load.
    5.10    static const bool misaligned_vectors_ok();

     6.1 --- a/src/share/vm/opto/superword.cpp	Mon Oct 01 14:50:10 2012 -0700
     6.2 +++ b/src/share/vm/opto/superword.cpp	Tue Oct 02 12:25:13 2012 -0700
     6.3 @@ -1436,10 +1436,9 @@
     6.4        return opd; // input is matching vector
     6.5      }
     6.6      if ((opd_idx == 2) && VectorNode::is_shift(p0)) {
     6.7 -      // No vector is needed for shift count.
     6.8 -      // Vector instructions do not mask shift count, do it here.
     6.9        Compile* C = _phase->C;
    6.10        Node* cnt = opd;
    6.11 +      // Vector instructions do not mask shift count, do it here.
    6.12        juint mask = (p0->bottom_type() == TypeInt::INT) ? (BitsPerInt - 1) : (BitsPerLong - 1);
    6.13        const TypeInt* t = opd->find_int_type();
    6.14        if (t != NULL && t->is_con()) {
    6.15 @@ -1456,8 +1455,8 @@
    6.16            _phase->set_ctrl(cnt, _phase->get_ctrl(opd));
    6.17          }
    6.18          assert(opd->bottom_type()->isa_int(), "int type only");
    6.19 -        // Move non constant shift count into XMM register.
    6.20 -        cnt = new (C) MoveI2FNode(cnt);
    6.21 +        // Move non constant shift count into vector register.
    6.22 +        cnt = VectorNode::shift_count(C, p0, cnt, vlen, velt_basic_type(p0));
    6.23        }
    6.24        if (cnt != opd) {
    6.25          _igvn.register_new_node_with_optimizer(cnt);

     7.1 --- a/src/share/vm/opto/vectornode.cpp	Mon Oct 01 14:50:10 2012 -0700
     7.2 +++ b/src/share/vm/opto/vectornode.cpp	Tue Oct 02 12:25:13 2012 -0700
     7.3 @@ -243,6 +243,8 @@
     7.4  VectorNode* VectorNode::make(Compile* C, int opc, Node* n1, Node* n2, uint vlen, BasicType bt) {
     7.5    const TypeVect* vt = TypeVect::make(bt, vlen);
     7.6    int vopc = VectorNode::opcode(opc, bt);
     7.7 +  // This method should not be called for unimplemented vectors.
     7.8 +  guarantee(vopc > 0, err_msg_res("Vector for '%s' is not implemented", NodeClassNames[opc]));
     7.9  
    7.10    switch (vopc) {
    7.11    case Op_AddVB: return new (C) AddVBNode(n1, n2, vt);
    7.12 @@ -286,7 +288,7 @@
    7.13    case Op_OrV:  return new (C) OrVNode (n1, n2, vt);
    7.14    case Op_XorV: return new (C) XorVNode(n1, n2, vt);
    7.15    }
    7.16 -  ShouldNotReachHere();
    7.17 +  fatal(err_msg_res("Missed vector creation for '%s'", NodeClassNames[vopc]));
    7.18    return NULL;
    7.19  
    7.20  }
    7.21 @@ -312,7 +314,25 @@
    7.22    case T_DOUBLE:
    7.23      return new (C) ReplicateDNode(s, vt);
    7.24    }
    7.25 -  ShouldNotReachHere();
    7.26 +  fatal(err_msg_res("Type '%s' is not supported for vectors", type2name(bt)));
    7.27 +  return NULL;
    7.28 +}
    7.29 +
    7.30 +VectorNode* VectorNode::shift_count(Compile* C, Node* shift, Node* cnt, uint vlen, BasicType bt) {
    7.31 +  assert(VectorNode::is_shift(shift) && !cnt->is_Con(), "only variable shift count");
    7.32 +  // Match shift count type with shift vector type.
    7.33 +  const TypeVect* vt = TypeVect::make(bt, vlen);
    7.34 +  switch (shift->Opcode()) {
    7.35 +  case Op_LShiftI:
    7.36 +  case Op_LShiftL:
    7.37 +    return new (C) LShiftCntVNode(cnt, vt);
    7.38 +  case Op_RShiftI:
    7.39 +  case Op_RShiftL:
    7.40 +  case Op_URShiftI:
    7.41 +  case Op_URShiftL:
    7.42 +    return new (C) RShiftCntVNode(cnt, vt);
    7.43 +  }
    7.44 +  fatal(err_msg_res("Missed vector creation for '%s'", NodeClassNames[shift->Opcode()]));
    7.45    return NULL;
    7.46  }
    7.47  
    7.48 @@ -335,7 +355,7 @@
    7.49    case T_DOUBLE:
    7.50      return new (C) PackDNode(s, vt);
    7.51    }
    7.52 -  ShouldNotReachHere();
    7.53 +  fatal(err_msg_res("Type '%s' is not supported for vectors", type2name(bt)));
    7.54    return NULL;
    7.55  }
    7.56  
    7.57 @@ -371,7 +391,7 @@
    7.58      case T_DOUBLE:
    7.59        return new (C) Pack2DNode(n1, n2, TypeVect::make(T_DOUBLE, 2));
    7.60      }
    7.61 -    ShouldNotReachHere();
    7.62 +    fatal(err_msg_res("Type '%s' is not supported for vectors", type2name(bt)));
    7.63    }
    7.64    return NULL;
    7.65  }
    7.66 @@ -381,7 +401,6 @@
    7.67                                       Node* adr, const TypePtr* atyp, uint vlen, BasicType bt) {
    7.68    const TypeVect* vt = TypeVect::make(bt, vlen);
    7.69    return new (C) LoadVectorNode(ctl, mem, adr, atyp, vt);
    7.70 -  return NULL;
    7.71  }
    7.72  
    7.73  // Return the vector version of a scalar store node.
    7.74 @@ -413,7 +432,7 @@
    7.75    case T_DOUBLE:
    7.76      return new (C) ExtractDNode(v, pos);
    7.77    }
    7.78 -  ShouldNotReachHere();
    7.79 +  fatal(err_msg_res("Type '%s' is not supported for vectors", type2name(bt)));
    7.80    return NULL;
    7.81  }
    7.82  

     8.1 --- a/src/share/vm/opto/vectornode.hpp	Mon Oct 01 14:50:10 2012 -0700
     8.2 +++ b/src/share/vm/opto/vectornode.hpp	Tue Oct 02 12:25:13 2012 -0700
     8.3 @@ -29,7 +29,7 @@
     8.4  #include "opto/node.hpp"
     8.5  #include "opto/opcodes.hpp"
     8.6  
     8.7 -//------------------------------VectorNode--------------------------------------
     8.8 +//------------------------------VectorNode-------------------------------------
     8.9  // Vector Operation
    8.10  class VectorNode : public TypeNode {
    8.11   public:
    8.12 @@ -53,7 +53,7 @@
    8.13    virtual uint ideal_reg() const { return Matcher::vector_ideal_reg(vect_type()->length_in_bytes()); }
    8.14  
    8.15    static VectorNode* scalar2vector(Compile* C, Node* s, uint vlen, const Type* opd_t);
    8.16 -
    8.17 +  static VectorNode* shift_count(Compile* C, Node* shift, Node* cnt, uint vlen, BasicType bt);
    8.18    static VectorNode* make(Compile* C, int opc, Node* n1, Node* n2, uint vlen, BasicType bt);
    8.19  
    8.20    static int  opcode(int opc, BasicType bt);
    8.21 @@ -64,9 +64,9 @@
    8.22    static void vector_operands(Node* n, uint* start, uint* end);
    8.23  };
    8.24  
    8.25 -//===========================Vector=ALU=Operations====================================
    8.26 +//===========================Vector=ALU=Operations=============================
    8.27  
    8.28 -//------------------------------AddVBNode---------------------------------------
    8.29 +//------------------------------AddVBNode--------------------------------------
    8.30  // Vector add byte
    8.31  class AddVBNode : public VectorNode {
    8.32   public:
    8.33 @@ -74,7 +74,7 @@
    8.34    virtual int Opcode() const;
    8.35  };
    8.36  
    8.37 -//------------------------------AddVSNode---------------------------------------
    8.38 +//------------------------------AddVSNode--------------------------------------
    8.39  // Vector add char/short
    8.40  class AddVSNode : public VectorNode {
    8.41   public:
    8.42 @@ -82,7 +82,7 @@
    8.43    virtual int Opcode() const;
    8.44  };
    8.45  
    8.46 -//------------------------------AddVINode---------------------------------------
    8.47 +//------------------------------AddVINode--------------------------------------
    8.48  // Vector add int
    8.49  class AddVINode : public VectorNode {
    8.50   public:
    8.51 @@ -90,7 +90,7 @@
    8.52    virtual int Opcode() const;
    8.53  };
    8.54  
    8.55 -//------------------------------AddVLNode---------------------------------------
    8.56 +//------------------------------AddVLNode--------------------------------------
    8.57  // Vector add long
    8.58  class AddVLNode : public VectorNode {
    8.59   public:
    8.60 @@ -98,7 +98,7 @@
    8.61    virtual int Opcode() const;
    8.62  };
    8.63  
    8.64 -//------------------------------AddVFNode---------------------------------------
    8.65 +//------------------------------AddVFNode--------------------------------------
    8.66  // Vector add float
    8.67  class AddVFNode : public VectorNode {
    8.68   public:
    8.69 @@ -106,7 +106,7 @@
    8.70    virtual int Opcode() const;
    8.71  };
    8.72  
    8.73 -//------------------------------AddVDNode---------------------------------------
    8.74 +//------------------------------AddVDNode--------------------------------------
    8.75  // Vector add double
    8.76  class AddVDNode : public VectorNode {
    8.77   public:
    8.78 @@ -114,7 +114,7 @@
    8.79    virtual int Opcode() const;
    8.80  };
    8.81  
    8.82 -//------------------------------SubVBNode---------------------------------------
    8.83 +//------------------------------SubVBNode--------------------------------------
    8.84  // Vector subtract byte
    8.85  class SubVBNode : public VectorNode {
    8.86   public:
    8.87 @@ -122,7 +122,7 @@
    8.88    virtual int Opcode() const;
    8.89  };
    8.90  
    8.91 -//------------------------------SubVSNode---------------------------------------
    8.92 +//------------------------------SubVSNode--------------------------------------
    8.93  // Vector subtract short
    8.94  class SubVSNode : public VectorNode {
    8.95   public:
    8.96 @@ -130,7 +130,7 @@
    8.97    virtual int Opcode() const;
    8.98  };
    8.99  
   8.100 -//------------------------------SubVINode---------------------------------------
   8.101 +//------------------------------SubVINode--------------------------------------
   8.102  // Vector subtract int
   8.103  class SubVINode : public VectorNode {
   8.104   public:
   8.105 @@ -138,7 +138,7 @@
   8.106    virtual int Opcode() const;
   8.107  };
   8.108  
   8.109 -//------------------------------SubVLNode---------------------------------------
   8.110 +//------------------------------SubVLNode--------------------------------------
   8.111  // Vector subtract long
   8.112  class SubVLNode : public VectorNode {
   8.113   public:
   8.114 @@ -146,7 +146,7 @@
   8.115    virtual int Opcode() const;
   8.116  };
   8.117  
   8.118 -//------------------------------SubVFNode---------------------------------------
   8.119 +//------------------------------SubVFNode--------------------------------------
   8.120  // Vector subtract float
   8.121  class SubVFNode : public VectorNode {
   8.122   public:
   8.123 @@ -154,7 +154,7 @@
   8.124    virtual int Opcode() const;
   8.125  };
   8.126  
   8.127 -//------------------------------SubVDNode---------------------------------------
   8.128 +//------------------------------SubVDNode--------------------------------------
   8.129  // Vector subtract double
   8.130  class SubVDNode : public VectorNode {
   8.131   public:
   8.132 @@ -162,7 +162,7 @@
   8.133    virtual int Opcode() const;
   8.134  };
   8.135  
   8.136 -//------------------------------MulVSNode---------------------------------------
   8.137 +//------------------------------MulVSNode--------------------------------------
   8.138  // Vector multiply short
   8.139  class MulVSNode : public VectorNode {
   8.140   public:
   8.141 @@ -170,7 +170,7 @@
   8.142    virtual int Opcode() const;
   8.143  };
   8.144  
   8.145 -//------------------------------MulVINode---------------------------------------
   8.146 +//------------------------------MulVINode--------------------------------------
   8.147  // Vector multiply int
   8.148  class MulVINode : public VectorNode {
   8.149   public:
   8.150 @@ -178,7 +178,7 @@
   8.151    virtual int Opcode() const;
   8.152  };
   8.153  
   8.154 -//------------------------------MulVFNode---------------------------------------
   8.155 +//------------------------------MulVFNode--------------------------------------
   8.156  // Vector multiply float
   8.157  class MulVFNode : public VectorNode {
   8.158   public:
   8.159 @@ -186,7 +186,7 @@
   8.160    virtual int Opcode() const;
   8.161  };
   8.162  
   8.163 -//------------------------------MulVDNode---------------------------------------
   8.164 +//------------------------------MulVDNode--------------------------------------
   8.165  // Vector multiply double
   8.166  class MulVDNode : public VectorNode {
   8.167   public:
   8.168 @@ -194,7 +194,7 @@
   8.169    virtual int Opcode() const;
   8.170  };
   8.171  
   8.172 -//------------------------------DivVFNode---------------------------------------
   8.173 +//------------------------------DivVFNode--------------------------------------
   8.174  // Vector divide float
   8.175  class DivVFNode : public VectorNode {
   8.176   public:
   8.177 @@ -202,7 +202,7 @@
   8.178    virtual int Opcode() const;
   8.179  };
   8.180  
   8.181 -//------------------------------DivVDNode---------------------------------------
   8.182 +//------------------------------DivVDNode--------------------------------------
   8.183  // Vector Divide double
   8.184  class DivVDNode : public VectorNode {
   8.185   public:
   8.186 @@ -210,7 +210,7 @@
   8.187    virtual int Opcode() const;
   8.188  };
   8.189  
   8.190 -//------------------------------LShiftVBNode---------------------------------------
   8.191 +//------------------------------LShiftVBNode-----------------------------------
   8.192  // Vector left shift bytes
   8.193  class LShiftVBNode : public VectorNode {
   8.194   public:
   8.195 @@ -218,7 +218,7 @@
   8.196    virtual int Opcode() const;
   8.197  };
   8.198  
   8.199 -//------------------------------LShiftVSNode---------------------------------------
   8.200 +//------------------------------LShiftVSNode-----------------------------------
   8.201  // Vector left shift shorts
   8.202  class LShiftVSNode : public VectorNode {
   8.203   public:
   8.204 @@ -226,7 +226,7 @@
   8.205    virtual int Opcode() const;
   8.206  };
   8.207  
   8.208 -//------------------------------LShiftVINode---------------------------------------
   8.209 +//------------------------------LShiftVINode-----------------------------------
   8.210  // Vector left shift ints
   8.211  class LShiftVINode : public VectorNode {
   8.212   public:
   8.213 @@ -234,7 +234,7 @@
   8.214    virtual int Opcode() const;
   8.215  };
   8.216  
   8.217 -//------------------------------LShiftVLNode---------------------------------------
   8.218 +//------------------------------LShiftVLNode-----------------------------------
   8.219  // Vector left shift longs
   8.220  class LShiftVLNode : public VectorNode {
   8.221   public:
   8.222 @@ -242,7 +242,7 @@
   8.223    virtual int Opcode() const;
   8.224  };
   8.225  
   8.226 -//------------------------------RShiftVBNode---------------------------------------
   8.227 +//------------------------------RShiftVBNode-----------------------------------
   8.228  // Vector right arithmetic (signed) shift bytes
   8.229  class RShiftVBNode : public VectorNode {
   8.230   public:
   8.231 @@ -250,7 +250,7 @@
   8.232    virtual int Opcode() const;
   8.233  };
   8.234  
   8.235 -//------------------------------RShiftVSNode---------------------------------------
   8.236 +//------------------------------RShiftVSNode-----------------------------------
   8.237  // Vector right arithmetic (signed) shift shorts
   8.238  class RShiftVSNode : public VectorNode {
   8.239   public:
   8.240 @@ -258,7 +258,7 @@
   8.241    virtual int Opcode() const;
   8.242  };
   8.243  
   8.244 -//------------------------------RShiftVINode---------------------------------------
   8.245 +//------------------------------RShiftVINode-----------------------------------
   8.246  // Vector right arithmetic (signed) shift ints
   8.247  class RShiftVINode : public VectorNode {
   8.248   public:
   8.249 @@ -266,7 +266,7 @@
   8.250    virtual int Opcode() const;
   8.251  };
   8.252  
   8.253 -//------------------------------RShiftVLNode---------------------------------------
   8.254 +//------------------------------RShiftVLNode-----------------------------------
   8.255  // Vector right arithmetic (signed) shift longs
   8.256  class RShiftVLNode : public VectorNode {
   8.257   public:
   8.258 @@ -274,7 +274,7 @@
   8.259    virtual int Opcode() const;
   8.260  };
   8.261  
   8.262 -//------------------------------URShiftVBNode---------------------------------------
   8.263 +//------------------------------URShiftVBNode----------------------------------
   8.264  // Vector right logical (unsigned) shift bytes
   8.265  class URShiftVBNode : public VectorNode {
   8.266   public:
   8.267 @@ -282,7 +282,7 @@
   8.268    virtual int Opcode() const;
   8.269  };
   8.270  
   8.271 -//------------------------------URShiftVSNode---------------------------------------
   8.272 +//------------------------------URShiftVSNode----------------------------------
   8.273  // Vector right logical (unsigned) shift shorts
   8.274  class URShiftVSNode : public VectorNode {
   8.275   public:
   8.276 @@ -290,7 +290,7 @@
   8.277    virtual int Opcode() const;
   8.278  };
   8.279  
   8.280 -//------------------------------URShiftVINode---------------------------------------
   8.281 +//------------------------------URShiftVINode----------------------------------
   8.282  // Vector right logical (unsigned) shift ints
   8.283  class URShiftVINode : public VectorNode {
   8.284   public:
   8.285 @@ -298,7 +298,7 @@
   8.286    virtual int Opcode() const;
   8.287  };
   8.288  
   8.289 -//------------------------------URShiftVLNode---------------------------------------
   8.290 +//------------------------------URShiftVLNode----------------------------------
   8.291  // Vector right logical (unsigned) shift longs
   8.292  class URShiftVLNode : public VectorNode {
   8.293   public:
   8.294 @@ -306,6 +306,24 @@
   8.295    virtual int Opcode() const;
   8.296  };
   8.297  
   8.298 +//------------------------------LShiftCntVNode---------------------------------
   8.299 +// Vector left shift count
   8.300 +class LShiftCntVNode : public VectorNode {
   8.301 + public:
   8.302 +  LShiftCntVNode(Node* cnt, const TypeVect* vt) : VectorNode(cnt,vt) {}
   8.303 +  virtual int Opcode() const;
   8.304 +  virtual uint ideal_reg() const { return Matcher::vector_shift_count_ideal_reg(vect_type()->length_in_bytes()); }
   8.305 +};
   8.306 +
   8.307 +//------------------------------RShiftCntVNode---------------------------------
   8.308 +// Vector right shift count
   8.309 +class RShiftCntVNode : public VectorNode {
   8.310 + public:
   8.311 +  RShiftCntVNode(Node* cnt, const TypeVect* vt) : VectorNode(cnt,vt) {}
   8.312 +  virtual int Opcode() const;
   8.313 +  virtual uint ideal_reg() const { return Matcher::vector_shift_count_ideal_reg(vect_type()->length_in_bytes()); }
   8.314 +};
   8.315 +
   8.316  
   8.317  //------------------------------AndVNode---------------------------------------
   8.318  // Vector and integer
   8.319 @@ -452,7 +470,7 @@
   8.320    static PackNode* make(Compile* C, Node* s, uint vlen, BasicType bt);
   8.321  };
   8.322  
   8.323 -//------------------------------PackBNode---------------------------------------
   8.324 +//------------------------------PackBNode--------------------------------------
   8.325  // Pack byte scalars into vector
   8.326  class PackBNode : public PackNode {
   8.327   public:
   8.328 @@ -460,7 +478,7 @@
   8.329    virtual int Opcode() const;
   8.330  };
   8.331  
   8.332 -//------------------------------PackSNode---------------------------------------
   8.333 +//------------------------------PackSNode--------------------------------------
   8.334  // Pack short scalars into a vector
   8.335  class PackSNode : public PackNode {
   8.336   public:
   8.337 @@ -469,7 +487,7 @@
   8.338    virtual int Opcode() const;
   8.339  };
   8.340  
   8.341 -//------------------------------PackINode---------------------------------------
   8.342 +//------------------------------PackINode--------------------------------------
   8.343  // Pack integer scalars into a vector
   8.344  class PackINode : public PackNode {
   8.345   public:
   8.346 @@ -478,7 +496,7 @@
   8.347    virtual int Opcode() const;
   8.348  };
   8.349  
   8.350 -//------------------------------PackLNode---------------------------------------
   8.351 +//------------------------------PackLNode--------------------------------------
   8.352  // Pack long scalars into a vector
   8.353  class PackLNode : public PackNode {
   8.354   public:
   8.355 @@ -487,7 +505,7 @@
   8.356    virtual int Opcode() const;
   8.357  };
   8.358  
   8.359 -//------------------------------Pack2LNode--------------------------------------
   8.360 +//------------------------------Pack2LNode-------------------------------------
   8.361  // Pack 2 long scalars into a vector
   8.362  class Pack2LNode : public PackNode {
   8.363   public:
   8.364 @@ -495,7 +513,7 @@
   8.365    virtual int Opcode() const;
   8.366  };
   8.367  
   8.368 -//------------------------------PackFNode---------------------------------------
   8.369 +//------------------------------PackFNode--------------------------------------
   8.370  // Pack float scalars into vector
   8.371  class PackFNode : public PackNode {
   8.372   public:
   8.373 @@ -504,7 +522,7 @@
   8.374    virtual int Opcode() const;
   8.375  };
   8.376  
   8.377 -//------------------------------PackDNode---------------------------------------
   8.378 +//------------------------------PackDNode--------------------------------------
   8.379  // Pack double scalars into a vector
   8.380  class PackDNode : public PackNode {
   8.381   public:
   8.382 @@ -513,7 +531,7 @@
   8.383    virtual int Opcode() const;
   8.384  };
   8.385  
   8.386 -//------------------------------Pack2DNode--------------------------------------
   8.387 +//------------------------------Pack2DNode-------------------------------------
   8.388  // Pack 2 double scalars into a vector
   8.389  class Pack2DNode : public PackNode {
   8.390   public:
   8.391 @@ -522,9 +540,9 @@
   8.392  };
   8.393  
   8.394  
   8.395 -//========================Extract_Scalar_from_Vector===============================
   8.396 +//========================Extract_Scalar_from_Vector===========================
   8.397  
   8.398 -//------------------------------ExtractNode---------------------------------------
   8.399 +//------------------------------ExtractNode------------------------------------
   8.400  // Extract a scalar from a vector at position "pos"
   8.401  class ExtractNode : public Node {
   8.402   public:
   8.403 @@ -537,7 +555,7 @@
   8.404    static Node* make(Compile* C, Node* v, uint position, BasicType bt);
   8.405  };
   8.406  
   8.407 -//------------------------------ExtractBNode---------------------------------------
   8.408 +//------------------------------ExtractBNode-----------------------------------
   8.409  // Extract a byte from a vector at position "pos"
   8.410  class ExtractBNode : public ExtractNode {
   8.411   public:
   8.412 @@ -547,7 +565,7 @@
   8.413    virtual uint ideal_reg() const { return Op_RegI; }
   8.414  };
   8.415  
   8.416 -//------------------------------ExtractUBNode--------------------------------------
   8.417 +//------------------------------ExtractUBNode----------------------------------
   8.418  // Extract a boolean from a vector at position "pos"
   8.419  class ExtractUBNode : public ExtractNode {
   8.420   public:
   8.421 @@ -557,7 +575,7 @@
   8.422    virtual uint ideal_reg() const { return Op_RegI; }
   8.423  };
   8.424  
   8.425 -//------------------------------ExtractCNode---------------------------------------
   8.426 +//------------------------------ExtractCNode-----------------------------------
   8.427  // Extract a char from a vector at position "pos"
   8.428  class ExtractCNode : public ExtractNode {
   8.429   public:
   8.430 @@ -567,7 +585,7 @@
   8.431    virtual uint ideal_reg() const { return Op_RegI; }
   8.432  };
   8.433  
   8.434 -//------------------------------ExtractSNode---------------------------------------
   8.435 +//------------------------------ExtractSNode-----------------------------------
   8.436  // Extract a short from a vector at position "pos"
   8.437  class ExtractSNode : public ExtractNode {
   8.438   public:
   8.439 @@ -577,7 +595,7 @@
   8.440    virtual uint ideal_reg() const { return Op_RegI; }
   8.441  };
   8.442  
   8.443 -//------------------------------ExtractINode---------------------------------------
   8.444 +//------------------------------ExtractINode-----------------------------------
   8.445  // Extract an int from a vector at position "pos"
   8.446  class ExtractINode : public ExtractNode {
   8.447   public:
   8.448 @@ -587,7 +605,7 @@
   8.449    virtual uint ideal_reg() const { return Op_RegI; }
   8.450  };
   8.451  
   8.452 -//------------------------------ExtractLNode---------------------------------------
   8.453 +//------------------------------ExtractLNode-----------------------------------
   8.454  // Extract a long from a vector at position "pos"
   8.455  class ExtractLNode : public ExtractNode {
   8.456   public:
   8.457 @@ -597,7 +615,7 @@
   8.458    virtual uint ideal_reg() const { return Op_RegL; }
   8.459  };
   8.460  
   8.461 -//------------------------------ExtractFNode---------------------------------------
   8.462 +//------------------------------ExtractFNode-----------------------------------
   8.463  // Extract a float from a vector at position "pos"
   8.464  class ExtractFNode : public ExtractNode {
   8.465   public:
   8.466 @@ -607,7 +625,7 @@
   8.467    virtual uint ideal_reg() const { return Op_RegF; }
   8.468  };
   8.469  
   8.470 -//------------------------------ExtractDNode---------------------------------------
   8.471 +//------------------------------ExtractDNode-----------------------------------
   8.472  // Extract a double from a vector at position "pos"
   8.473  class ExtractDNode : public ExtractNode {
   8.474   public:

     9.1 --- a/test/compiler/7200264/Test7200264.sh	Mon Oct 01 14:50:10 2012 -0700
     9.2 +++ b/test/compiler/7200264/Test7200264.sh	Tue Oct 02 12:25:13 2012 -0700
     9.3 @@ -77,6 +77,16 @@
     9.4      exit 0
     9.5  fi
     9.6  
     9.7 +# grep for support integer multiply vectors (cpu with SSE4.1)
     9.8 +${TESTJAVA}${FS}bin${FS}java ${TESTVMOPTS} -XX:+PrintMiscellaneous -XX:+Verbose -version | grep "cores per cpu" | grep "sse4.1"
     9.9 +
    9.10 +if [ $? != 0 ]
    9.11 +then
    9.12 +    SSE=2
    9.13 +else
    9.14 +    SSE=4
    9.15 +fi
    9.16 +
    9.17  cp ${TESTSRC}${FS}TestIntVect.java .
    9.18  ${TESTJAVA}${FS}bin${FS}javac -d . TestIntVect.java
    9.19  
    9.20 @@ -97,6 +107,9 @@
    9.21      exit 1
    9.22  fi
    9.23  
    9.24 +# MulVI is only supported with SSE4.1.
    9.25 +if [ $SSE -gt 3 ]
    9.26 +then
    9.27  # LShiftVI+SubVI is generated for test_mulc
    9.28  COUNT=`grep MulVI test.out | wc -l | awk '{print $1}'`
    9.29  if [ $COUNT -lt 2 ]
    9.30 @@ -104,6 +117,7 @@
    9.31      echo "Test Failed: MulVI $COUNT < 2"
    9.32      exit 1
    9.33  fi
    9.34 +fi
    9.35  
    9.36  COUNT=`grep AndV test.out | wc -l | awk '{print $1}'`
    9.37  if [ $COUNT -lt 3 ]
    9.38 @@ -126,6 +140,7 @@
    9.39      exit 1
    9.40  fi
    9.41  
    9.42 +# LShiftVI+SubVI is generated for test_mulc
    9.43  COUNT=`grep LShiftVI test.out | wc -l | awk '{print $1}'`
    9.44  if [ $COUNT -lt 5 ]
    9.45  then
    9.46 @@ -133,11 +148,10 @@
    9.47      exit 1
    9.48  fi
    9.49  
    9.50 -# RShiftVI + URShiftVI
    9.51 -COUNT=`grep RShiftVI test.out | wc -l | awk '{print $1}'`
    9.52 -if [ $COUNT -lt 6 ]
    9.53 +COUNT=`grep RShiftVI test.out | sed '/URShiftVI/d' | wc -l | awk '{print $1}'`
    9.54 +if [ $COUNT -lt 3 ]
    9.55  then
    9.56 -    echo "Test Failed: RShiftVI $COUNT < 6"
    9.57 +    echo "Test Failed: RShiftVI $COUNT < 3"
    9.58      exit 1
    9.59  fi
    9.60