Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
8185969: PPC64: Improve VSR support to use up to 64 registers
Mon, 03 Jun 2019 17:16:58 -0400
- author
- gromero
- date
- Mon, 03 Jun 2019 17:16:58 -0400
- changeset 9687
- 846245a33793
- parent 9686
- 025ce746a942
- child 9688
- 54e5e3c816d4
8185969: PPC64: Improve VSR support to use up to 64 registers
Reviewed-by: mdoerr, goetz
Contributed-by: Gustavo Serra Scalet <gustavo.scalet@eldorado.org.br>, Kazunori Ogata <ogatak@jp.ibm.com>
1.1 --- a/src/cpu/ppc/vm/assembler_ppc.hpp Wed May 01 22:02:48 2019 +0530 1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.hpp Mon Jun 03 17:16:58 2019 -0400 1.3 @@ -472,7 +472,12 @@ 1.4 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1), 1.5 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1), 1.6 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1), 1.7 + MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1), 1.8 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1), 1.9 + MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1), 1.10 + XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3), 1.11 + XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3), 1.12 + XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3), 1.13 1.14 // Vector Permute and Formatting 1.15 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 1.16 @@ -522,6 +527,7 @@ 1.17 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), 1.18 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), 1.19 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), 1.20 + VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ), 1.21 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), 1.22 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), 1.23 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), 1.24 @@ -1056,16 +1062,19 @@ 1.25 static int vrs( VectorRegister r) { return vrs(r->encoding());} 1.26 static int vrt( VectorRegister r) { return vrt(r->encoding());} 1.27 1.28 + // Only used on SHA sigma instructions (VX-form) 1.29 + static int vst( int x) { return opp_u_field(x, 16, 16); } 1.30 + static int vsix( int x) { return opp_u_field(x, 20, 17); } 1.31 + 1.32 // Support Vector-Scalar (VSX) instructions. 1.33 - static int vsra( int x) { return opp_u_field(x, 15, 11); } 1.34 - static int vsrb( int x) { return opp_u_field(x, 20, 16); } 1.35 - static int vsrc( int x) { return opp_u_field(x, 25, 21); } 1.36 - static int vsrs( int x) { return opp_u_field(x, 10, 6); } 1.37 - static int vsrt( int x) { return opp_u_field(x, 10, 6); } 1.38 + static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); } 1.39 + static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); } 1.40 + static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); } 1.41 + static int vsrt( int x) { return vsrs(x); } 1.42 + static int vsdm( int x) { return opp_u_field(x, 23, 22); } 1.43 1.44 static int vsra( VectorSRegister r) { return vsra(r->encoding());} 1.45 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());} 1.46 - static int vsrc( VectorSRegister r) { return vsrc(r->encoding());} 1.47 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());} 1.48 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());} 1.49 1.50 @@ -1869,6 +1878,7 @@ 1.51 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); 1.52 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); 1.53 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); 1.54 + inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b); 1.55 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); 1.56 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); 1.57 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); 1.58 @@ -1944,6 +1954,7 @@ 1.59 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); 1.60 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); 1.61 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); 1.62 + inline void vmr( VectorRegister d, VectorRegister a); 1.63 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); 1.64 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b); 1.65 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); 1.66 @@ -1967,8 +1978,19 @@ 1.67 inline void lxvd2x( VectorSRegister d, Register a, Register b); 1.68 inline void stxvd2x( VectorSRegister d, Register a); 1.69 inline void stxvd2x( VectorSRegister d, Register a, Register b); 1.70 + inline void mtvrwz( VectorRegister d, Register a); 1.71 + inline void mfvrwz( Register a, VectorRegister d); 1.72 inline void mtvrd( VectorRegister d, Register a); 1.73 inline void mfvrd( Register a, VectorRegister d); 1.74 + inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm); 1.75 + inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1.76 + inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1.77 + 1.78 + // VSX Extended Mnemonics 1.79 + inline void xxspltd( VectorSRegister d, VectorSRegister a, int x); 1.80 + inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1.81 + inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b); 1.82 + inline void xxswapd( VectorSRegister d, VectorSRegister a); 1.83 1.84 // AES (introduced with Power 8) 1.85 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2.1 --- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp Wed May 01 22:02:48 2019 +0530 2.2 +++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp Mon Jun 03 17:16:58 2019 -0400 2.3 @@ -627,12 +627,23 @@ 2.4 inline void Assembler::lvsr( VectorRegister d, Register s1, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); } 2.5 2.6 // Vector-Scalar (VSX) instructions. 2.7 -inline void Assembler::lxvd2x (VectorSRegister d, Register s1) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); } 2.8 -inline void Assembler::lxvd2x (VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); } 2.9 -inline void Assembler::stxvd2x(VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); } 2.10 -inline void Assembler::stxvd2x(VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); } 2.11 -inline void Assembler::mtvrd( VectorRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vrt(d) | ra(a) | 1u); } // 1u: d is treated as Vector (VMX/Altivec). 2.12 -inline void Assembler::mfvrd( Register a, VectorRegister d) { emit_int32( MFVSRD_OPCODE | vrt(d) | ra(a) | 1u); } // 1u: d is treated as Vector (VMX/Altivec). 2.13 +inline void Assembler::lxvd2x( VectorSRegister d, Register s1) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); } 2.14 +inline void Assembler::lxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); } 2.15 +inline void Assembler::stxvd2x( VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); } 2.16 +inline void Assembler::stxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); } 2.17 +inline void Assembler::mtvrd( VectorRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); } 2.18 +inline void Assembler::mfvrd( Register a, VectorRegister d) { emit_int32( MFVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); } 2.19 +inline void Assembler::mtvrwz( VectorRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); } 2.20 +inline void Assembler::mfvrwz( Register a, VectorRegister d) { emit_int32( MFVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); } 2.21 +inline void Assembler::xxpermdi(VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm) { emit_int32( XXPERMDI_OPCODE | vsrt(d) | vsra(a) | vsrb(b) | vsdm(dm)); } 2.22 +inline void Assembler::xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); } 2.23 +inline void Assembler::xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); } 2.24 + 2.25 +// VSX Extended Mnemonics 2.26 +inline void Assembler::xxspltd( VectorSRegister d, VectorSRegister a, int x) { xxpermdi(d, a, a, x ? 3 : 0); } 2.27 +inline void Assembler::xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b) { xxpermdi(d, a, b, 0); } 2.28 +inline void Assembler::xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b) { xxpermdi(d, a, b, 3); } 2.29 +inline void Assembler::xxswapd( VectorSRegister d, VectorSRegister a) { xxpermdi(d, a, a, 2); } 2.30 2.31 inline void Assembler::vpkpx( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKPX_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.32 inline void Assembler::vpkshss( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSHSS_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.33 @@ -675,6 +686,7 @@ 2.34 inline void Assembler::vaddubm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUBM_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.35 inline void Assembler::vadduwm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUWM_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.36 inline void Assembler::vadduhm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUHM_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.37 +inline void Assembler::vaddudm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUDM_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.38 inline void Assembler::vaddubs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUBS_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.39 inline void Assembler::vadduws( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUWS_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.40 inline void Assembler::vadduhs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUHS_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.41 @@ -751,6 +763,7 @@ 2.42 inline void Assembler::vandc( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VANDC_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.43 inline void Assembler::vnor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNOR_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.44 inline void Assembler::vor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VOR_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.45 +inline void Assembler::vmr( VectorRegister d, VectorRegister a) { emit_int32( VOR_OPCODE | vrt(d) | vra(a) | vrb(a)); } 2.46 inline void Assembler::vxor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VXOR_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.47 inline void Assembler::vrld( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLD_OPCODE | vrt(d) | vra(a) | vrb(b)); } 2.48 inline void Assembler::vrlb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
3.1 --- a/src/cpu/ppc/vm/register_ppc.cpp Wed May 01 22:02:48 2019 +0530 3.2 +++ b/src/cpu/ppc/vm/register_ppc.cpp Mon Jun 03 17:16:58 2019 -0400 3.3 @@ -81,8 +81,17 @@ 3.4 "VSR0", "VSR1", "VSR2", "VSR3", "VSR4", "VSR5", "VSR6", "VSR7", 3.5 "VSR8", "VSR9", "VSR10", "VSR11", "VSR12", "VSR13", "VSR14", "VSR15", 3.6 "VSR16", "VSR17", "VSR18", "VSR19", "VSR20", "VSR21", "VSR22", "VSR23", 3.7 - "VSR24", "VSR25", "VSR26", "VSR27", "VSR28", "VSR29", "VSR30", "VSR31" 3.8 + "VSR24", "VSR25", "VSR26", "VSR27", "VSR28", "VSR29", "VSR30", "VSR31", 3.9 + "VSR32", "VSR33", "VSR34", "VSR35", "VSR36", "VSR37", "VSR38", "VSR39", 3.10 + "VSR40", "VSR41", "VSR42", "VSR43", "VSR44", "VSR45", "VSR46", "VSR47", 3.11 + "VSR48", "VSR49", "VSR50", "VSR51", "VSR52", "VSR53", "VSR54", "VSR55", 3.12 + "VSR56", "VSR57", "VSR58", "VSR59", "VSR60", "VSR61", "VSR62", "VSR63" 3.13 }; 3.14 return is_valid() ? names[encoding()] : "vsnoreg"; 3.15 } 3.16 3.17 +// Method to convert a VectorRegister to a Vector-Scalar Register (VectorSRegister) 3.18 +VectorSRegister VectorRegisterImpl::to_vsr() const { 3.19 + if (this == vnoreg) { return vsnoregi; } 3.20 + return as_VectorSRegister(encoding() + 32); 3.21 +}
4.1 --- a/src/cpu/ppc/vm/register_ppc.hpp Wed May 01 22:02:48 2019 +0530 4.2 +++ b/src/cpu/ppc/vm/register_ppc.hpp Mon Jun 03 17:16:58 2019 -0400 4.3 @@ -399,6 +399,11 @@ 4.4 return (VectorRegister)(intptr_t)encoding; 4.5 } 4.6 4.7 +// Forward declaration 4.8 +// Use VectorSRegister as a shortcut. 4.9 +class VectorSRegisterImpl; 4.10 +typedef VectorSRegisterImpl* VectorSRegister; 4.11 + 4.12 // The implementation of vector registers for the Power architecture 4.13 class VectorRegisterImpl: public AbstractRegisterImpl { 4.14 public: 4.15 @@ -416,6 +421,9 @@ 4.16 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } 4.17 4.18 const char* name() const; 4.19 + 4.20 + // convert to VSR 4.21 + VectorSRegister to_vsr() const; 4.22 }; 4.23 4.24 // The Vector registers of the Power architecture 4.25 @@ -492,10 +500,6 @@ 4.26 #endif // DONT_USE_REGISTER_DEFINES 4.27 4.28 4.29 -// Use VectorSRegister as a shortcut. 4.30 -class VectorSRegisterImpl; 4.31 -typedef VectorSRegisterImpl* VectorSRegister; 4.32 - 4.33 inline VectorSRegister as_VectorSRegister(int encoding) { 4.34 return (VectorSRegister)(intptr_t)encoding; 4.35 } 4.36 @@ -504,7 +508,7 @@ 4.37 class VectorSRegisterImpl: public AbstractRegisterImpl { 4.38 public: 4.39 enum { 4.40 - number_of_registers = 32 4.41 + number_of_registers = 64 4.42 }; 4.43 4.44 // construction 4.45 @@ -555,6 +559,38 @@ 4.46 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR29, (29)); 4.47 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR30, (30)); 4.48 CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR31, (31)); 4.49 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR32, (32)); 4.50 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR33, (33)); 4.51 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR34, (34)); 4.52 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR35, (35)); 4.53 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR36, (36)); 4.54 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR37, (37)); 4.55 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR38, (38)); 4.56 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR39, (39)); 4.57 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR40, (40)); 4.58 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR41, (41)); 4.59 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR42, (42)); 4.60 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR43, (43)); 4.61 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR44, (44)); 4.62 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR45, (45)); 4.63 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR46, (46)); 4.64 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR47, (47)); 4.65 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR48, (48)); 4.66 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR49, (49)); 4.67 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR50, (50)); 4.68 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR51, (51)); 4.69 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR52, (52)); 4.70 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR53, (53)); 4.71 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR54, (54)); 4.72 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR55, (55)); 4.73 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR56, (56)); 4.74 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR57, (57)); 4.75 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR58, (58)); 4.76 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR59, (59)); 4.77 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR60, (60)); 4.78 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR61, (61)); 4.79 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR62, (62)); 4.80 +CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR63, (63)); 4.81 4.82 #ifndef DONT_USE_REGISTER_DEFINES 4.83 #define vsnoregi ((VectorSRegister)(vsnoreg_VectorSRegisterEnumValue)) 4.84 @@ -590,6 +626,38 @@ 4.85 #define VSR29 ((VectorSRegister)( VSR29_VectorSRegisterEnumValue)) 4.86 #define VSR30 ((VectorSRegister)( VSR30_VectorSRegisterEnumValue)) 4.87 #define VSR31 ((VectorSRegister)( VSR31_VectorSRegisterEnumValue)) 4.88 +#define VSR32 ((VectorSRegister)( VSR32_VectorSRegisterEnumValue)) 4.89 +#define VSR33 ((VectorSRegister)( VSR33_VectorSRegisterEnumValue)) 4.90 +#define VSR34 ((VectorSRegister)( VSR34_VectorSRegisterEnumValue)) 4.91 +#define VSR35 ((VectorSRegister)( VSR35_VectorSRegisterEnumValue)) 4.92 +#define VSR36 ((VectorSRegister)( VSR36_VectorSRegisterEnumValue)) 4.93 +#define VSR37 ((VectorSRegister)( VSR37_VectorSRegisterEnumValue)) 4.94 +#define VSR38 ((VectorSRegister)( VSR38_VectorSRegisterEnumValue)) 4.95 +#define VSR39 ((VectorSRegister)( VSR39_VectorSRegisterEnumValue)) 4.96 +#define VSR40 ((VectorSRegister)( VSR40_VectorSRegisterEnumValue)) 4.97 +#define VSR41 ((VectorSRegister)( VSR41_VectorSRegisterEnumValue)) 4.98 +#define VSR42 ((VectorSRegister)( VSR42_VectorSRegisterEnumValue)) 4.99 +#define VSR43 ((VectorSRegister)( VSR43_VectorSRegisterEnumValue)) 4.100 +#define VSR44 ((VectorSRegister)( VSR44_VectorSRegisterEnumValue)) 4.101 +#define VSR45 ((VectorSRegister)( VSR45_VectorSRegisterEnumValue)) 4.102 +#define VSR46 ((VectorSRegister)( VSR46_VectorSRegisterEnumValue)) 4.103 +#define VSR47 ((VectorSRegister)( VSR47_VectorSRegisterEnumValue)) 4.104 +#define VSR48 ((VectorSRegister)( VSR48_VectorSRegisterEnumValue)) 4.105 +#define VSR49 ((VectorSRegister)( VSR49_VectorSRegisterEnumValue)) 4.106 +#define VSR50 ((VectorSRegister)( VSR50_VectorSRegisterEnumValue)) 4.107 +#define VSR51 ((VectorSRegister)( VSR51_VectorSRegisterEnumValue)) 4.108 +#define VSR52 ((VectorSRegister)( VSR52_VectorSRegisterEnumValue)) 4.109 +#define VSR53 ((VectorSRegister)( VSR53_VectorSRegisterEnumValue)) 4.110 +#define VSR54 ((VectorSRegister)( VSR54_VectorSRegisterEnumValue)) 4.111 +#define VSR55 ((VectorSRegister)( VSR55_VectorSRegisterEnumValue)) 4.112 +#define VSR56 ((VectorSRegister)( VSR56_VectorSRegisterEnumValue)) 4.113 +#define VSR57 ((VectorSRegister)( VSR57_VectorSRegisterEnumValue)) 4.114 +#define VSR58 ((VectorSRegister)( VSR58_VectorSRegisterEnumValue)) 4.115 +#define VSR59 ((VectorSRegister)( VSR59_VectorSRegisterEnumValue)) 4.116 +#define VSR60 ((VectorSRegister)( VSR60_VectorSRegisterEnumValue)) 4.117 +#define VSR61 ((VectorSRegister)( VSR61_VectorSRegisterEnumValue)) 4.118 +#define VSR62 ((VectorSRegister)( VSR62_VectorSRegisterEnumValue)) 4.119 +#define VSR63 ((VectorSRegister)( VSR63_VectorSRegisterEnumValue)) 4.120 #endif // DONT_USE_REGISTER_DEFINES 4.121 4.122 // Maximum number of incoming arguments that can be passed in i registers. 4.123 @@ -610,7 +678,7 @@ 4.124 * 2 // register halves 4.125 + ConditionRegisterImpl::number_of_registers // condition code registers 4.126 + SpecialRegisterImpl::number_of_registers // special registers 4.127 - + VectorRegisterImpl::number_of_registers // vector registers 4.128 + + VectorRegisterImpl::number_of_registers // VSX registers 4.129 }; 4.130 4.131 static const int max_gpr;
