1.1 --- a/src/cpu/ppc/vm/assembler_ppc.hpp Wed May 01 22:02:48 2019 +0530
1.2 +++ b/src/cpu/ppc/vm/assembler_ppc.hpp Mon Jun 03 17:16:58 2019 -0400
1.3 @@ -472,7 +472,12 @@
1.4 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
1.5 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
1.6 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
1.7 + MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
1.8 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
1.9 + MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1),
1.10 + XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3),
1.11 + XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
1.12 + XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
1.13
1.14 // Vector Permute and Formatting
1.15 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
1.16 @@ -522,6 +527,7 @@
1.17 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
1.18 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
1.19 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
1.20 + VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ),
1.21 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
1.22 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
1.23 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
1.24 @@ -1056,16 +1062,19 @@
1.25 static int vrs( VectorRegister r) { return vrs(r->encoding());}
1.26 static int vrt( VectorRegister r) { return vrt(r->encoding());}
1.27
1.28 + // Only used on SHA sigma instructions (VX-form)
1.29 + static int vst( int x) { return opp_u_field(x, 16, 16); }
1.30 + static int vsix( int x) { return opp_u_field(x, 20, 17); }
1.31 +
1.32 // Support Vector-Scalar (VSX) instructions.
1.33 - static int vsra( int x) { return opp_u_field(x, 15, 11); }
1.34 - static int vsrb( int x) { return opp_u_field(x, 20, 16); }
1.35 - static int vsrc( int x) { return opp_u_field(x, 25, 21); }
1.36 - static int vsrs( int x) { return opp_u_field(x, 10, 6); }
1.37 - static int vsrt( int x) { return opp_u_field(x, 10, 6); }
1.38 + static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
1.39 + static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
1.40 + static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
1.41 + static int vsrt( int x) { return vsrs(x); }
1.42 + static int vsdm( int x) { return opp_u_field(x, 23, 22); }
1.43
1.44 static int vsra( VectorSRegister r) { return vsra(r->encoding());}
1.45 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
1.46 - static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
1.47 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
1.48 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
1.49
1.50 @@ -1869,6 +1878,7 @@
1.51 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
1.52 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
1.53 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
1.54 + inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b);
1.55 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
1.56 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
1.57 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
1.58 @@ -1944,6 +1954,7 @@
1.59 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
1.60 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
1.61 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
1.62 + inline void vmr( VectorRegister d, VectorRegister a);
1.63 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
1.64 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
1.65 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
1.66 @@ -1967,8 +1978,19 @@
1.67 inline void lxvd2x( VectorSRegister d, Register a, Register b);
1.68 inline void stxvd2x( VectorSRegister d, Register a);
1.69 inline void stxvd2x( VectorSRegister d, Register a, Register b);
1.70 + inline void mtvrwz( VectorRegister d, Register a);
1.71 + inline void mfvrwz( Register a, VectorRegister d);
1.72 inline void mtvrd( VectorRegister d, Register a);
1.73 inline void mfvrd( Register a, VectorRegister d);
1.74 + inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
1.75 + inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
1.76 + inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
1.77 +
1.78 + // VSX Extended Mnemonics
1.79 + inline void xxspltd( VectorSRegister d, VectorSRegister a, int x);
1.80 + inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b);
1.81 + inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b);
1.82 + inline void xxswapd( VectorSRegister d, VectorSRegister a);
1.83
1.84 // AES (introduced with Power 8)
1.85 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
