Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
8042309: Some bugfixes for the ppc64 port.
Fri, 02 May 2014 14:53:06 +0200
- author
- goetz
- date
- Fri, 02 May 2014 14:53:06 +0200
- changeset 6660
- 63c5920a038d
- parent 6659
- 34862ced4a87
- child 6661
- 28bbbecff5f0
8042309: Some bugfixes for the ppc64 port.
Reviewed-by: kvn
1.1 --- a/src/cpu/ppc/vm/cppInterpreter_ppc.cpp Thu May 08 11:05:02 2014 +0200 1.2 +++ b/src/cpu/ppc/vm/cppInterpreter_ppc.cpp Fri May 02 14:53:06 2014 +0200 1.3 @@ -1,3 +1,4 @@ 1.4 + 1.5 /* 1.6 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 1.7 * Copyright 2012, 2013 SAP AG. All rights reserved. 1.8 @@ -403,7 +404,7 @@ 1.9 BLOCK_COMMENT("compute_interpreter_state {"); 1.10 1.11 // access_flags = method->access_flags(); 1.12 - // TODO: PPC port: assert(4 == methodOopDesc::sz_access_flags(), "unexpected field size"); 1.13 + // TODO: PPC port: assert(4 == sizeof(AccessFlags), "unexpected field size"); 1.14 __ lwa(access_flags, method_(access_flags)); 1.15 1.16 // parameter_count = method->constMethod->size_of_parameters(); 1.17 @@ -1055,7 +1056,7 @@ 1.18 assert(access_flags->is_nonvolatile(), 1.19 "access_flags must be in a non-volatile register"); 1.20 // Type check. 1.21 - // TODO: PPC port: assert(4 == methodOopDesc::sz_access_flags(), "unexpected field size"); 1.22 + // TODO: PPC port: assert(4 == sizeof(AccessFlags), "unexpected field size"); 1.23 __ lwz(access_flags, method_(access_flags)); 1.24 1.25 // We don't want to reload R19_method and access_flags after calls 1.26 @@ -1838,7 +1839,7 @@ 1.27 // Interpreter state fields. 1.28 const Register msg = R24_tmp4; 1.29 1.30 - // MethodOop fields. 1.31 + // Method fields. 1.32 const Register parameter_count = R25_tmp5; 1.33 const Register result_index = R26_tmp6; 1.34 1.35 @@ -2023,7 +2024,7 @@ 1.36 __ add(R17_tos, R17_tos, parameter_count); 1.37 1.38 // Result stub address array index 1.39 - // TODO: PPC port: assert(4 == methodOopDesc::sz_result_index(), "unexpected field size"); 1.40 + // TODO: PPC port: assert(4 == sizeof(AccessFlags), "unexpected field size"); 1.41 __ lwa(result_index, method_(result_index)); 1.42 1.43 __ li(msg, BytecodeInterpreter::method_resume); 1.44 @@ -2709,7 +2710,7 @@ 1.45 __ ld(R3_ARG1, state_(_result._osr._osr_buf)); 1.46 __ mtctr(R12_scratch2); 1.47 1.48 - // Load method oop, gc may move it during execution of osr'd method. 1.49 + // Load method, gc may move it during execution of osr'd method. 1.50 __ ld(R22_tmp2, state_(_method)); 1.51 // Load message 'call_method'. 1.52 __ li(R23_tmp3, BytecodeInterpreter::call_method);
2.1 --- a/src/cpu/ppc/vm/frame_ppc.inline.hpp Thu May 08 11:05:02 2014 +0200 2.2 +++ b/src/cpu/ppc/vm/frame_ppc.inline.hpp Fri May 02 14:53:06 2014 +0200 2.3 @@ -26,6 +26,8 @@ 2.4 #ifndef CPU_PPC_VM_FRAME_PPC_INLINE_HPP 2.5 #define CPU_PPC_VM_FRAME_PPC_INLINE_HPP 2.6 2.7 +#include "code/codeCache.hpp" 2.8 + 2.9 // Inline functions for ppc64 frames: 2.10 2.11 // Find codeblob and set deopt_state.
3.1 --- a/src/cpu/ppc/vm/interp_masm_ppc_64.hpp Thu May 08 11:05:02 2014 +0200 3.2 +++ b/src/cpu/ppc/vm/interp_masm_ppc_64.hpp Fri May 02 14:53:06 2014 +0200 3.3 @@ -26,7 +26,7 @@ 3.4 #ifndef CPU_PPC_VM_INTERP_MASM_PPC_64_HPP 3.5 #define CPU_PPC_VM_INTERP_MASM_PPC_64_HPP 3.6 3.7 -#include "assembler_ppc.inline.hpp" 3.8 +#include "asm/macroAssembler.hpp" 3.9 #include "interpreter/invocationCounter.hpp" 3.10 3.11 // This file specializes the assembler with interpreter-specific macros.
4.1 --- a/src/cpu/ppc/vm/interpreterRT_ppc.cpp Thu May 08 11:05:02 2014 +0200 4.2 +++ b/src/cpu/ppc/vm/interpreterRT_ppc.cpp Fri May 02 14:53:06 2014 +0200 4.3 @@ -24,6 +24,7 @@ 4.4 */ 4.5 4.6 #include "precompiled.hpp" 4.7 +#include "asm/assembler.inline.hpp" 4.8 #include "interpreter/interpreter.hpp" 4.9 #include "interpreter/interpreterRuntime.hpp" 4.10 #include "memory/allocation.inline.hpp"
5.1 --- a/src/cpu/ppc/vm/interpreter_ppc.cpp Thu May 08 11:05:02 2014 +0200 5.2 +++ b/src/cpu/ppc/vm/interpreter_ppc.cpp Fri May 02 14:53:06 2014 +0200 5.3 @@ -139,32 +139,16 @@ 5.4 // Signature is in R3_RET. Signature is callee saved. 5.5 __ mr(signature, R3_RET); 5.6 5.7 - // Reload method, it may have moved. 5.8 -#ifdef CC_INTERP 5.9 - __ ld(R19_method, state_(_method)); 5.10 -#else 5.11 - __ ld(R19_method, 0, target_sp); 5.12 - __ ld(R19_method, _ijava_state_neg(method), R19_method); 5.13 -#endif 5.14 - 5.15 // Get the result handler. 5.16 __ call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::get_result_handler), R16_thread, R19_method); 5.17 5.18 - // Reload method, it may have moved. 5.19 -#ifdef CC_INTERP 5.20 - __ ld(R19_method, state_(_method)); 5.21 -#else 5.22 - __ ld(R19_method, 0, target_sp); 5.23 - __ ld(R19_method, _ijava_state_neg(method), R19_method); 5.24 -#endif 5.25 - 5.26 { 5.27 Label L; 5.28 // test if static 5.29 // _access_flags._flags must be at offset 0. 5.30 // TODO PPC port: requires change in shared code. 5.31 //assert(in_bytes(AccessFlags::flags_offset()) == 0, 5.32 - // "MethodOopDesc._access_flags == MethodOopDesc._access_flags._flags"); 5.33 + // "MethodDesc._access_flags == MethodDesc._access_flags._flags"); 5.34 // _access_flags must be a 32 bit value. 5.35 assert(sizeof(AccessFlags) == 4, "wrong size"); 5.36 __ lwa(R11_scratch1/*access_flags*/, method_(access_flags));
6.1 --- a/src/cpu/ppc/vm/jniFastGetField_ppc.cpp Thu May 08 11:05:02 2014 +0200 6.2 +++ b/src/cpu/ppc/vm/jniFastGetField_ppc.cpp Fri May 02 14:53:06 2014 +0200 6.3 @@ -32,7 +32,7 @@ 6.4 6.5 6.6 address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) { 6.7 - // we don't have fast jni accessors. 6.8 + // We don't have fast jni accessors. 6.9 return (address) -1; 6.10 } 6.11 6.12 @@ -57,12 +57,12 @@ 6.13 } 6.14 6.15 address JNI_FastGetField::generate_fast_get_long_field() { 6.16 - // we don't have fast jni accessors. 6.17 + // We don't have fast jni accessors. 6.18 return (address) -1; 6.19 } 6.20 6.21 address JNI_FastGetField::generate_fast_get_float_field0(BasicType type) { 6.22 - // e don't have fast jni accessors. 6.23 + // We don't have fast jni accessors. 6.24 return (address) -1; 6.25 } 6.26
7.1 --- a/src/cpu/ppc/vm/ppc.ad Thu May 08 11:05:02 2014 +0200 7.2 +++ b/src/cpu/ppc/vm/ppc.ad Fri May 02 14:53:06 2014 +0200 7.3 @@ -898,7 +898,7 @@ 7.4 // To keep related declarations/definitions/uses close together, 7.5 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 7.6 7.7 - // Returns true if Node n is followed by a MemBar node that 7.8 + // Returns true if Node n is followed by a MemBar node that 7.9 // will do an acquire. If so, this node must not do the acquire 7.10 // operation. 7.11 bool followed_by_acquire(const Node *n); 7.12 @@ -908,7 +908,7 @@ 7.13 7.14 // Optimize load-acquire. 7.15 // 7.16 -// Check if acquire is unnecessary due to following operation that does 7.17 +// Check if acquire is unnecessary due to following operation that does 7.18 // acquire anyways. 7.19 // Walk the pattern: 7.20 // 7.21 @@ -919,12 +919,12 @@ 7.22 // Proj(ctrl) Proj(mem) 7.23 // | | 7.24 // MemBarRelease/Volatile 7.25 -// 7.26 +// 7.27 bool followed_by_acquire(const Node *load) { 7.28 assert(load->is_Load(), "So far implemented only for loads."); 7.29 7.30 // Find MemBarAcquire. 7.31 - const Node *mba = NULL; 7.32 + const Node *mba = NULL; 7.33 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 7.34 const Node *out = load->fast_out(i); 7.35 if (out->Opcode() == Op_MemBarAcquire) { 7.36 @@ -937,7 +937,7 @@ 7.37 7.38 // Find following MemBar node. 7.39 // 7.40 - // The following node must be reachable by control AND memory 7.41 + // The following node must be reachable by control AND memory 7.42 // edge to assure no other operations are in between the two nodes. 7.43 // 7.44 // So first get the Proj node, mem_proj, to use it to iterate forward. 7.45 @@ -1135,6 +1135,7 @@ 7.46 7.47 public: 7.48 7.49 + // Emit call stub, compiled java to interpreter. 7.50 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 7.51 7.52 // Size of call trampoline stub. 7.53 @@ -2752,7 +2753,7 @@ 7.54 // inputs for new nodes 7.55 m1->add_req(NULL, n_toc); 7.56 m2->add_req(NULL, m1); 7.57 - 7.58 + 7.59 // operands for new nodes 7.60 m1->_opnds[0] = new (C) iRegPdstOper(); // dst 7.61 m1->_opnds[1] = op_src; // src 7.62 @@ -2760,29 +2761,29 @@ 7.63 m2->_opnds[0] = new (C) iRegPdstOper(); // dst 7.64 m2->_opnds[1] = op_src; // src 7.65 m2->_opnds[2] = new (C) iRegLdstOper(); // base 7.66 - 7.67 + 7.68 // Initialize ins_attrib TOC fields. 7.69 m1->_const_toc_offset = -1; 7.70 m2->_const_toc_offset_hi_node = m1; 7.71 - 7.72 + 7.73 // Register allocation for new nodes. 7.74 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.75 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.76 - 7.77 + 7.78 nodes->push(m1); 7.79 nodes->push(m2); 7.80 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 7.81 } else { 7.82 loadConPNode *m2 = new (C) loadConPNode(); 7.83 - 7.84 + 7.85 // inputs for new nodes 7.86 m2->add_req(NULL, n_toc); 7.87 - 7.88 + 7.89 // operands for new nodes 7.90 m2->_opnds[0] = new (C) iRegPdstOper(); // dst 7.91 m2->_opnds[1] = op_src; // src 7.92 m2->_opnds[2] = new (C) iRegPdstOper(); // toc 7.93 - 7.94 + 7.95 // Register allocation for new nodes. 7.96 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.97 7.98 @@ -2974,17 +2975,17 @@ 7.99 n_sub_base->_opnds[1] = op_crx; 7.100 n_sub_base->_opnds[2] = op_src; 7.101 n_sub_base->_bottom_type = _bottom_type; 7.102 - 7.103 + 7.104 n_shift->add_req(n_region, n_sub_base); 7.105 n_shift->_opnds[0] = op_dst; 7.106 n_shift->_opnds[1] = op_dst; 7.107 n_shift->_bottom_type = _bottom_type; 7.108 - 7.109 + 7.110 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.111 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 7.112 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.113 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.114 - 7.115 + 7.116 nodes->push(n_move); 7.117 nodes->push(n_compare); 7.118 nodes->push(n_sub_base); 7.119 @@ -3061,20 +3062,20 @@ 7.120 } else { 7.121 // before Power 7 7.122 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode(); 7.123 - 7.124 + 7.125 n_add_base->add_req(n_region, n_compare, n_shift); 7.126 n_add_base->_opnds[0] = op_dst; 7.127 n_add_base->_opnds[1] = op_crx; 7.128 n_add_base->_opnds[2] = op_dst; 7.129 n_add_base->_bottom_type = _bottom_type; 7.130 - 7.131 + 7.132 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 7.133 ra_->set_oop(n_add_base, true); 7.134 - 7.135 + 7.136 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.137 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 7.138 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7.139 - 7.140 + 7.141 nodes->push(n_compare); 7.142 nodes->push(n_shift); 7.143 nodes->push(n_add_base); 7.144 @@ -3631,11 +3632,11 @@ 7.145 // Req... 7.146 for (uint i = 0; i < req(); ++i) { 7.147 // The expanded node does not need toc any more. 7.148 - // Add the inline cache constant here instead. This expresses the 7.149 + // Add the inline cache constant here instead. This expresses the 7.150 // register of the inline cache must be live at the call. 7.151 // Else we would have to adapt JVMState by -1. 7.152 if (i == mach_constant_base_node_input()) { 7.153 - call->add_req(loadConLNodes_IC._last); 7.154 + call->add_req(loadConLNodes_IC._last); 7.155 } else { 7.156 call->add_req(in(i)); 7.157 } 7.158 @@ -3663,6 +3664,8 @@ 7.159 %} 7.160 7.161 // Compound version of call dynamic 7.162 + // Toc is only passed so that it can be used in ins_encode statement. 7.163 + // In the code we have to use $constanttablebase. 7.164 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 7.165 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.166 MacroAssembler _masm(&cbuf); 7.167 @@ -3670,14 +3673,17 @@ 7.168 7.169 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 7.170 #if 0 7.171 + int vtable_index = this->_vtable_index; 7.172 if (_vtable_index < 0) { 7.173 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 7.174 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 7.175 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 7.176 - AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word()); 7.177 - 7.178 + 7.179 + // Virtual call relocation will point to ic load. 7.180 address virtual_call_meta_addr = __ pc(); 7.181 - __ load_const_from_method_toc(ic_reg, meta, Rtoc); 7.182 + // Load a clear inline cache. 7.183 + AddressLiteral empty_ic((address) Universe::non_oop_word()); 7.184 + __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc); 7.185 // CALL to fixup routine. Fixup routine uses ScopeDesc info 7.186 // to determine who we intended to call. 7.187 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 7.188 @@ -3710,7 +3716,6 @@ 7.189 "Fix constant in ret_addr_offset()"); 7.190 } 7.191 #endif 7.192 - guarantee(0, "Fix handling of toc edge: messes up derived/base pairs."); 7.193 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 7.194 %} 7.195 7.196 @@ -5436,7 +5441,7 @@ 7.197 ins_pipe(pipe_class_memory); 7.198 %} 7.199 7.200 -// Match loading integer and casting it to unsigned int in 7.201 +// Match loading integer and casting it to unsigned int in 7.202 // long register. 7.203 // LoadI + ConvI2L + AndL 0xffffffff. 7.204 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 7.205 @@ -6078,7 +6083,7 @@ 7.206 ins_pipe(pipe_class_default); 7.207 %} 7.208 7.209 -// This needs a match rule so that build_oop_map knows this is 7.210 +// This needs a match rule so that build_oop_map knows this is 7.211 // not a narrow oop. 7.212 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 7.213 match(Set dst src1); 7.214 @@ -6702,7 +6707,7 @@ 7.215 size(4); 7.216 ins_encode %{ 7.217 // This is a Power7 instruction for which no machine description exists. 7.218 - // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.219 + // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.220 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 7.221 %} 7.222 ins_pipe(pipe_class_default); 7.223 @@ -6847,7 +6852,7 @@ 7.224 size(4); 7.225 ins_encode %{ 7.226 // This is a Power7 instruction for which no machine description exists. 7.227 - // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.228 + // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.229 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 7.230 %} 7.231 ins_pipe(pipe_class_default); 7.232 @@ -7064,7 +7069,7 @@ 7.233 n1->_bottom_type = _bottom_type; 7.234 7.235 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode(); 7.236 - n2->add_req(n_region, n2); 7.237 + n2->add_req(n_region, n1); 7.238 n2->_opnds[0] = op_dst; 7.239 n2->_opnds[1] = op_dst; 7.240 n2->_bottom_type = _bottom_type; 7.241 @@ -7199,7 +7204,7 @@ 7.242 // inline_unsafe_load_store). 7.243 // 7.244 // Add this node again if we found a good solution for inline_unsafe_load_store(). 7.245 -// Don't forget to look at the implementation of post_store_load_barrier again, 7.246 +// Don't forget to look at the implementation of post_store_load_barrier again, 7.247 // we did other fixes in that method. 7.248 //instruct unnecessary_membar_volatile() %{ 7.249 // match(MemBarVolatile); 7.250 @@ -7237,7 +7242,7 @@ 7.251 // exists. Anyways, the scheduler should be off on Power7. 7.252 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.253 int cc = $cmp$$cmpcode; 7.254 - __ isel($dst$$Register, $crx$$CondRegister, 7.255 + __ isel($dst$$Register, $crx$$CondRegister, 7.256 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7.257 %} 7.258 ins_pipe(pipe_class_default); 7.259 @@ -7283,7 +7288,7 @@ 7.260 // exists. Anyways, the scheduler should be off on Power7. 7.261 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.262 int cc = $cmp$$cmpcode; 7.263 - __ isel($dst$$Register, $crx$$CondRegister, 7.264 + __ isel($dst$$Register, $crx$$CondRegister, 7.265 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7.266 %} 7.267 ins_pipe(pipe_class_default); 7.268 @@ -7329,7 +7334,7 @@ 7.269 // exists. Anyways, the scheduler should be off on Power7. 7.270 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.271 int cc = $cmp$$cmpcode; 7.272 - __ isel($dst$$Register, $crx$$CondRegister, 7.273 + __ isel($dst$$Register, $crx$$CondRegister, 7.274 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7.275 %} 7.276 ins_pipe(pipe_class_default); 7.277 @@ -7376,7 +7381,7 @@ 7.278 // exists. Anyways, the scheduler should be off on Power7. 7.279 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.280 int cc = $cmp$$cmpcode; 7.281 - __ isel($dst$$Register, $crx$$CondRegister, 7.282 + __ isel($dst$$Register, $crx$$CondRegister, 7.283 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7.284 %} 7.285 ins_pipe(pipe_class_default); 7.286 @@ -7522,8 +7527,8 @@ 7.287 ins_encode %{ 7.288 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.289 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7.290 - __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7.291 - MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7.292 + __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7.293 + MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7.294 $res$$Register, true); 7.295 %} 7.296 ins_pipe(pipe_class_default); 7.297 @@ -7929,7 +7934,23 @@ 7.298 7.299 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7.300 // positive longs and 0xF...F for negative ones. 7.301 -instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{ 7.302 +instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 7.303 + // no match-rule, false predicate 7.304 + effect(DEF dst, USE src); 7.305 + predicate(false); 7.306 + 7.307 + format %{ "SRADI $dst, $src, #63" %} 7.308 + size(4); 7.309 + ins_encode %{ 7.310 + // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7.311 + __ sradi($dst$$Register, $src$$Register, 0x3f); 7.312 + %} 7.313 + ins_pipe(pipe_class_default); 7.314 +%} 7.315 + 7.316 +// Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7.317 +// positive longs and 0xF...F for negative ones. 7.318 +instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 7.319 // no match-rule, false predicate 7.320 effect(DEF dst, USE src); 7.321 predicate(false); 7.322 @@ -8893,7 +8914,7 @@ 7.323 size(4); 7.324 ins_encode %{ 7.325 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 7.326 - __ rlwinm($dst$$Register, $src1$$Register, 0, 7.327 + __ rlwinm($dst$$Register, $src1$$Register, 0, 7.328 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 7.329 %} 7.330 ins_pipe(pipe_class_default); 7.331 @@ -9619,14 +9640,14 @@ 7.332 ins_cost(DEFAULT_COST*4); 7.333 7.334 expand %{ 7.335 - iRegIdst src1s; 7.336 - iRegIdst src2s; 7.337 - iRegIdst diff; 7.338 - sxtI_reg(src1s, src1); // ensure proper sign extention 7.339 - sxtI_reg(src2s, src2); // ensure proper sign extention 7.340 - subI_reg_reg(diff, src1s, src2s); 7.341 + iRegLdst src1s; 7.342 + iRegLdst src2s; 7.343 + iRegLdst diff; 7.344 + convI2L_reg(src1s, src1); // Ensure proper sign extension. 7.345 + convI2L_reg(src2s, src2); // Ensure proper sign extension. 7.346 + subL_reg_reg(diff, src1s, src2s); 7.347 // Need to consider >=33 bit result, therefore we need signmaskL. 7.348 - signmask64I_regI(dst, diff); 7.349 + signmask64I_regL(dst, diff); 7.350 %} 7.351 %} 7.352 7.353 @@ -10863,7 +10884,7 @@ 7.354 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 7.355 ins_encode %{ 7.356 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7.357 - __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 7.358 + __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 7.359 $tmp_klass$$Register, NULL, $result$$Register); 7.360 %} 7.361 ins_pipe(pipe_class_default); 7.362 @@ -11178,18 +11199,18 @@ 7.363 ins_cost(DEFAULT_COST*6); 7.364 7.365 expand %{ 7.366 - iRegIdst src1s; 7.367 - iRegIdst src2s; 7.368 - iRegIdst diff; 7.369 - iRegIdst sm; 7.370 - iRegIdst doz; // difference or zero 7.371 - sxtI_reg(src1s, src1); // Ensure proper sign extention. 7.372 - sxtI_reg(src2s, src2); // Ensure proper sign extention. 7.373 - subI_reg_reg(diff, src2s, src1s); 7.374 + iRegLdst src1s; 7.375 + iRegLdst src2s; 7.376 + iRegLdst diff; 7.377 + iRegLdst sm; 7.378 + iRegLdst doz; // difference or zero 7.379 + convI2L_reg(src1s, src1); // Ensure proper sign extension. 7.380 + convI2L_reg(src2s, src2); // Ensure proper sign extension. 7.381 + subL_reg_reg(diff, src2s, src1s); 7.382 // Need to consider >=33 bit result, therefore we need signmaskL. 7.383 - signmask64I_regI(sm, diff); 7.384 - andI_reg_reg(doz, diff, sm); // <=0 7.385 - addI_reg_reg(dst, doz, src1s); 7.386 + signmask64L_regL(sm, diff); 7.387 + andL_reg_reg(doz, diff, sm); // <=0 7.388 + addI_regL_regL(dst, doz, src1s); 7.389 %} 7.390 %} 7.391 7.392 @@ -11198,19 +11219,18 @@ 7.393 ins_cost(DEFAULT_COST*6); 7.394 7.395 expand %{ 7.396 - immI_minus1 m1 %{ -1 %} 7.397 - iRegIdst src1s; 7.398 - iRegIdst src2s; 7.399 - iRegIdst diff; 7.400 - iRegIdst sm; 7.401 - iRegIdst doz; // difference or zero 7.402 - sxtI_reg(src1s, src1); // Ensure proper sign extention. 7.403 - sxtI_reg(src2s, src2); // Ensure proper sign extention. 7.404 - subI_reg_reg(diff, src2s, src1s); 7.405 + iRegLdst src1s; 7.406 + iRegLdst src2s; 7.407 + iRegLdst diff; 7.408 + iRegLdst sm; 7.409 + iRegLdst doz; // difference or zero 7.410 + convI2L_reg(src1s, src1); // Ensure proper sign extension. 7.411 + convI2L_reg(src2s, src2); // Ensure proper sign extension. 7.412 + subL_reg_reg(diff, src2s, src1s); 7.413 // Need to consider >=33 bit result, therefore we need signmaskL. 7.414 - signmask64I_regI(sm, diff); 7.415 - andcI_reg_reg(doz, sm, m1, diff); // >=0 7.416 - addI_reg_reg(dst, doz, src1s); 7.417 + signmask64L_regL(sm, diff); 7.418 + andcL_reg_reg(doz, diff, sm); // >=0 7.419 + addI_regL_regL(dst, doz, src1s); 7.420 %} 7.421 %} 7.422
8.1 --- a/src/cpu/ppc/vm/templateInterpreter_ppc.cpp Thu May 08 11:05:02 2014 +0200 8.2 +++ b/src/cpu/ppc/vm/templateInterpreter_ppc.cpp Fri May 02 14:53:06 2014 +0200 8.3 @@ -81,24 +81,18 @@ 8.4 #if 0 8.5 // Call special ClassCastException constructor taking object to cast 8.6 // and target class as arguments. 8.7 -address TemplateInterpreterGenerator::generate_ClassCastException_verbose_handler(const char* name) { 8.8 +address TemplateInterpreterGenerator::generate_ClassCastException_verbose_handler() { 8.9 address entry = __ pc(); 8.10 8.11 - // Target class oop is in register R6_ARG4 by convention! 8.12 - 8.13 // Expression stack must be empty before entering the VM if an 8.14 // exception happened. 8.15 __ empty_expression_stack(); 8.16 - // Setup parameters. 8.17 + 8.18 // Thread will be loaded to R3_ARG1. 8.19 - __ load_const_optimized(R4_ARG2, (address) name); 8.20 - __ mr(R5_ARG3, R17_tos); 8.21 - // R6_ARG4 contains specified class. 8.22 - __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_ClassCastException_verbose)); 8.23 -#ifdef ASSERT 8.24 + // Target class oop is in register R5_ARG3 by convention! 8.25 + __ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_ClassCastException_verbose, R17_tos, R5_ARG3)); 8.26 // Above call must not return here since exception pending. 8.27 - __ should_not_reach_here(); 8.28 -#endif 8.29 + DEBUG_ONLY(__ should_not_reach_here();) 8.30 return entry; 8.31 } 8.32 #endif 8.33 @@ -1535,14 +1529,32 @@ 8.34 __ stw(R0, in_bytes(JavaThread::popframe_condition_offset()), R16_thread); 8.35 8.36 // Get out of the current method and re-execute the call that called us. 8.37 - __ merge_frames(/*top_frame_sp*/ R21_sender_SP, /*return_pc*/ return_pc, R11_scratch1, R12_scratch2); 8.38 + __ merge_frames(/*top_frame_sp*/ R21_sender_SP, /*return_pc*/ noreg, R11_scratch1, R12_scratch2); 8.39 __ restore_interpreter_state(R11_scratch1); 8.40 __ ld(R12_scratch2, _ijava_state_neg(top_frame_sp), R11_scratch1); 8.41 __ resize_frame_absolute(R12_scratch2, R11_scratch1, R0); 8.42 - __ mtlr(return_pc); 8.43 if (ProfileInterpreter) { 8.44 __ set_method_data_pointer_for_bcp(); 8.45 } 8.46 +#if INCLUDE_JVMTI 8.47 + Label L_done; 8.48 + 8.49 + __ lbz(R11_scratch1, 0, R14_bcp); 8.50 + __ cmpwi(CCR0, R11_scratch1, Bytecodes::_invokestatic); 8.51 + __ bne(CCR0, L_done); 8.52 + 8.53 + // The member name argument must be restored if _invokestatic is re-executed after a PopFrame call. 8.54 + // Detect such a case in the InterpreterRuntime function and return the member name argument, or NULL. 8.55 + __ ld(R4_ARG2, 0, R18_locals); 8.56 + __ call_VM(R11_scratch1, CAST_FROM_FN_PTR(address, InterpreterRuntime::member_name_arg_or_null), 8.57 + R4_ARG2, R19_method, R14_bcp); 8.58 + 8.59 + __ cmpdi(CCR0, R11_scratch1, 0); 8.60 + __ beq(CCR0, L_done); 8.61 + 8.62 + __ std(R11_scratch1, wordSize, R15_esp); 8.63 + __ bind(L_done); 8.64 +#endif // INCLUDE_JVMTI 8.65 __ dispatch_next(vtos); 8.66 } 8.67 // end of JVMTI PopFrame support
9.1 --- a/src/cpu/ppc/vm/templateTable_ppc_64.cpp Thu May 08 11:05:02 2014 +0200 9.2 +++ b/src/cpu/ppc/vm/templateTable_ppc_64.cpp Fri May 02 14:53:06 2014 +0200 9.3 @@ -64,7 +64,7 @@ 9.4 assert_different_registers(Rtmp1, Rtmp2, Rtmp3, Rval, Rbase); 9.5 9.6 switch (barrier) { 9.7 -#ifndef SERIALGC 9.8 +#if INCLUDE_ALL_GCS 9.9 case BarrierSet::G1SATBCT: 9.10 case BarrierSet::G1SATBCTLogging: 9.11 { 9.12 @@ -104,7 +104,7 @@ 9.13 __ bind(Ldone); 9.14 } 9.15 break; 9.16 -#endif // SERIALGC 9.17 +#endif // INCLUDE_ALL_GCS 9.18 case BarrierSet::CardTableModRef: 9.19 case BarrierSet::CardTableExtension: 9.20 { 9.21 @@ -259,17 +259,17 @@ 9.22 switch (value) { 9.23 default: ShouldNotReachHere(); 9.24 case 0: { 9.25 - int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0); 9.26 + int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0, true); 9.27 __ lfs(F15_ftos, simm16_offset, R11_scratch1); 9.28 break; 9.29 } 9.30 case 1: { 9.31 - int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0); 9.32 + int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0, true); 9.33 __ lfs(F15_ftos, simm16_offset, R11_scratch1); 9.34 break; 9.35 } 9.36 case 2: { 9.37 - int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&two, R0); 9.38 + int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&two, R0, true); 9.39 __ lfs(F15_ftos, simm16_offset, R11_scratch1); 9.40 break; 9.41 } 9.42 @@ -282,12 +282,12 @@ 9.43 static double one = 1.0; 9.44 switch (value) { 9.45 case 0: { 9.46 - int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0); 9.47 + int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0, true); 9.48 __ lfd(F15_ftos, simm16_offset, R11_scratch1); 9.49 break; 9.50 } 9.51 case 1: { 9.52 - int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0); 9.53 + int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0, true); 9.54 __ lfd(F15_ftos, simm16_offset, R11_scratch1); 9.55 break; 9.56 } 9.57 @@ -3728,9 +3728,9 @@ 9.58 transition(atos, atos); 9.59 9.60 Label Ldone, Lis_null, Lquicked, Lresolved; 9.61 - Register Roffset = R5_ARG3, 9.62 + Register Roffset = R6_ARG4, 9.63 RobjKlass = R4_ARG2, 9.64 - RspecifiedKlass = R6_ARG4, // Generate_ClassCastException_verbose_handler will expect this register. 9.65 + RspecifiedKlass = R5_ARG3, // Generate_ClassCastException_verbose_handler will read value from this register. 9.66 Rcpool = R11_scratch1, 9.67 Rtags = R12_scratch2; 9.68
10.1 --- a/src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp Thu May 08 11:05:02 2014 +0200 10.2 +++ b/src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp Fri May 02 14:53:06 2014 +0200 10.3 @@ -53,41 +53,41 @@ 10.4 10.5 inline jlong Atomic::load(volatile jlong* src) { return *src; } 10.6 10.7 -/* 10.8 - machine barrier instructions: 10.9 - 10.10 - - sync two-way memory barrier, aka fence 10.11 - - lwsync orders Store|Store, 10.12 - Load|Store, 10.13 - Load|Load, 10.14 - but not Store|Load 10.15 - - eieio orders memory accesses for device memory (only) 10.16 - - isync invalidates speculatively executed instructions 10.17 - From the POWER ISA 2.06 documentation: 10.18 - "[...] an isync instruction prevents the execution of 10.19 - instructions following the isync until instructions 10.20 - preceding the isync have completed, [...]" 10.21 - From IBM's AIX assembler reference: 10.22 - "The isync [...] instructions causes the processor to 10.23 - refetch any instructions that might have been fetched 10.24 - prior to the isync instruction. The instruction isync 10.25 - causes the processor to wait for all previous instructions 10.26 - to complete. Then any instructions already fetched are 10.27 - discarded and instruction processing continues in the 10.28 - environment established by the previous instructions." 10.29 - 10.30 - semantic barrier instructions: 10.31 - (as defined in orderAccess.hpp) 10.32 - 10.33 - - release orders Store|Store, (maps to lwsync) 10.34 - Load|Store 10.35 - - acquire orders Load|Store, (maps to lwsync) 10.36 - Load|Load 10.37 - - fence orders Store|Store, (maps to sync) 10.38 - Load|Store, 10.39 - Load|Load, 10.40 - Store|Load 10.41 -*/ 10.42 +// 10.43 +// machine barrier instructions: 10.44 +// 10.45 +// - sync two-way memory barrier, aka fence 10.46 +// - lwsync orders Store|Store, 10.47 +// Load|Store, 10.48 +// Load|Load, 10.49 +// but not Store|Load 10.50 +// - eieio orders memory accesses for device memory (only) 10.51 +// - isync invalidates speculatively executed instructions 10.52 +// From the POWER ISA 2.06 documentation: 10.53 +// "[...] an isync instruction prevents the execution of 10.54 +// instructions following the isync until instructions 10.55 +// preceding the isync have completed, [...]" 10.56 +// From IBM's AIX assembler reference: 10.57 +// "The isync [...] instructions causes the processor to 10.58 +// refetch any instructions that might have been fetched 10.59 +// prior to the isync instruction. The instruction isync 10.60 +// causes the processor to wait for all previous instructions 10.61 +// to complete. Then any instructions already fetched are 10.62 +// discarded and instruction processing continues in the 10.63 +// environment established by the previous instructions." 10.64 +// 10.65 +// semantic barrier instructions: 10.66 +// (as defined in orderAccess.hpp) 10.67 +// 10.68 +// - release orders Store|Store, (maps to lwsync) 10.69 +// Load|Store 10.70 +// - acquire orders Load|Store, (maps to lwsync) 10.71 +// Load|Load 10.72 +// - fence orders Store|Store, (maps to sync) 10.73 +// Load|Store, 10.74 +// Load|Load, 10.75 +// Store|Load 10.76 +// 10.77 10.78 #define strasm_sync "\n sync \n" 10.79 #define strasm_lwsync "\n lwsync \n"
