Fri, 02 May 2014 14:53:06 +0200
8042309: Some bugfixes for the ppc64 port.
Reviewed-by: kvn
1 //
2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2013 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 //
27 // PPC64 Architecture Description File
28 //
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
79 // PPC64 has 32 64-bit integer registers.
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
233 // Condition Codes Flag Registers
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
248 // Special registers of PPC64
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
267 // It's worth about 1% on SPEC geomean to get this right.
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
335 // scratch register
336 F0, F0_H,
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
398 //-------Architecture Description Register Classes-----------------------
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
560 reg_class r19_bits64_reg(R19_H, R19);
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
861 %}
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
907 source %{
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
977 return false;
978 }
980 #define __ _masm.
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
985 // ****************************************************************************
987 // REQUIRED FUNCTIONALITY
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
993 // PPC port: Removed use of lazy constant construct.
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1025 //=============================================================================
1027 // condition code conversions
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1041 //=============================================================================
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1080 //=============================================================================
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1088 //=============================================================================
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1110 //=============================================================================
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1122 //=============================================================================
1124 %} // interrupt source
1126 source_hpp %{ // Header information of the source block.
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1134 class CallStubImpl {
1136 public:
1138 // Emit call stub, compiled java to interpreter.
1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1141 // Size of call trampoline stub.
1142 // This doesn't need to be accurate to the byte, but it
1143 // must be larger than or equal to the real size of the stub.
1144 static uint size_call_trampoline() {
1145 return trampoline_stub_size;
1146 }
1148 // number of relocations needed by a call trampoline stub
1149 static uint reloc_call_trampoline() {
1150 return 5;
1151 }
1153 };
1155 %} // end source_hpp
1157 source %{
1159 // Emit a trampoline stub for a call to a target which is too far away.
1160 //
1161 // code sequences:
1162 //
1163 // call-site:
1164 // branch-and-link to <destination> or <trampoline stub>
1165 //
1166 // Related trampoline stub for this call-site in the stub section:
1167 // load the call target from the constant pool
1168 // branch via CTR (LR/link still points to the call-site above)
1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1171 // Start the stub.
1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1173 if (stub == NULL) {
1174 Compile::current()->env()->record_out_of_memory_failure();
1175 return;
1176 }
1178 // For java_to_interp stubs we use R11_scratch1 as scratch register
1179 // and in call trampoline stubs we use R12_scratch2. This way we
1180 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1181 Register reg_scratch = R12_scratch2;
1183 // Create a trampoline stub relocation which relates this trampoline stub
1184 // with the call instruction at insts_call_instruction_offset in the
1185 // instructions code-section.
1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1187 const int stub_start_offset = __ offset();
1189 // Now, create the trampoline stub's code:
1190 // - load the TOC
1191 // - load the call target from the constant pool
1192 // - call
1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1195 __ mtctr(reg_scratch);
1196 __ bctr();
1198 const address stub_start_addr = __ addr_at(stub_start_offset);
1200 // FIXME: Assert that the trampoline stub can be identified and patched.
1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1204 "encoded offset into the constant pool must match");
1205 // Trampoline_stub_size should be good.
1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1209 // End the stub.
1210 __ end_a_stub();
1211 }
1213 //=============================================================================
1215 // Emit an inline branch-and-link call and a related trampoline stub.
1216 //
1217 // code sequences:
1218 //
1219 // call-site:
1220 // branch-and-link to <destination> or <trampoline stub>
1221 //
1222 // Related trampoline stub for this call-site in the stub section:
1223 // load the call target from the constant pool
1224 // branch via CTR (LR/link still points to the call-site above)
1225 //
1227 typedef struct {
1228 int insts_call_instruction_offset;
1229 int ret_addr_offset;
1230 } EmitCallOffsets;
1232 // Emit a branch-and-link instruction that branches to a trampoline.
1233 // - Remember the offset of the branch-and-link instruction.
1234 // - Add a relocation at the branch-and-link instruction.
1235 // - Emit a branch-and-link.
1236 // - Remember the return pc offset.
1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1238 EmitCallOffsets offsets = { -1, -1 };
1239 const int start_offset = __ offset();
1240 offsets.insts_call_instruction_offset = __ offset();
1242 // No entry point given, use the current pc.
1243 if (entry_point == NULL) entry_point = __ pc();
1245 if (!Compile::current()->in_scratch_emit_size()) {
1246 // Put the entry point as a constant into the constant pool.
1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1250 // Emit the trampoline stub which will be related to the branch-and-link below.
1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1252 __ relocate(rtype);
1253 }
1255 // Note: At this point we do not have the address of the trampoline
1256 // stub, and the entry point might be too far away for bl, so __ pc()
1257 // serves as dummy and the bl will be patched later.
1258 __ bl((address) __ pc());
1260 offsets.ret_addr_offset = __ offset() - start_offset;
1262 return offsets;
1263 }
1265 //=============================================================================
1267 // Factory for creating loadConL* nodes for large/small constant pool.
1269 static inline jlong replicate_immF(float con) {
1270 // Replicate float con 2 times and pack into vector.
1271 int val = *((int*)&con);
1272 jlong lval = val;
1273 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1274 return lval;
1275 }
1277 //=============================================================================
1279 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1280 int Compile::ConstantTable::calculate_table_base_offset() const {
1281 return 0; // absolute addressing, no offset
1282 }
1284 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1285 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1286 Compile *C = ra_->C;
1288 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1289 MachNode *m1 = new (C) loadToc_hiNode();
1290 MachNode *m2 = new (C) loadToc_loNode();
1292 m1->add_req(NULL);
1293 m2->add_req(NULL, m1);
1294 m1->_opnds[0] = op_dst;
1295 m2->_opnds[0] = op_dst;
1296 m2->_opnds[1] = op_dst;
1297 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1298 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1299 nodes->push(m1);
1300 nodes->push(m2);
1301 }
1303 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1304 // Is postalloc expanded.
1305 ShouldNotReachHere();
1306 }
1308 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1309 return 0;
1310 }
1312 #ifndef PRODUCT
1313 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1314 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1315 }
1316 #endif
1318 //=============================================================================
1320 #ifndef PRODUCT
1321 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1322 Compile* C = ra_->C;
1323 const long framesize = C->frame_slots() << LogBytesPerInt;
1325 st->print("PROLOG\n\t");
1326 if (C->need_stack_bang(framesize)) {
1327 st->print("stack_overflow_check\n\t");
1328 }
1330 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1331 st->print("save return pc\n\t");
1332 st->print("push frame %d\n\t", -framesize);
1333 }
1334 }
1335 #endif
1337 // Macro used instead of the common __ to emulate the pipes of PPC.
1338 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1339 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1340 // still no scheduling of this code is possible, the micro scheduler is aware of the
1341 // code and can update its internal data. The following mechanism is used to achieve this:
1342 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1343 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1344 #if 0 // TODO: PPC port
1345 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1346 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1347 _masm.
1348 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1349 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1350 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1351 C->hb_scheduling()->_pdScheduling->advance_offset
1352 #else
1353 #define ___(op) if (UsePower6SchedulerPPC64) \
1354 Unimplemented(); \
1355 _masm.
1356 #define ___stop if (UsePower6SchedulerPPC64) \
1357 Unimplemented()
1358 #define ___advance if (UsePower6SchedulerPPC64) \
1359 Unimplemented()
1360 #endif
1362 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1363 Compile* C = ra_->C;
1364 MacroAssembler _masm(&cbuf);
1366 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1367 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1369 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1371 const Register return_pc = R20; // Must match return_addr() in frame section.
1372 const Register callers_sp = R21;
1373 const Register push_frame_temp = R22;
1374 const Register toc_temp = R23;
1375 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1377 if (method_is_frameless) {
1378 // Add nop at beginning of all frameless methods to prevent any
1379 // oop instructions from getting overwritten by make_not_entrant
1380 // (patching attempt would fail).
1381 ___(nop) nop();
1382 } else {
1383 // Get return pc.
1384 ___(mflr) mflr(return_pc);
1385 }
1387 // Calls to C2R adapters often do not accept exceptional returns.
1388 // We require that their callers must bang for them. But be
1389 // careful, because some VM calls (such as call site linkage) can
1390 // use several kilobytes of stack. But the stack safety zone should
1391 // account for that. See bugs 4446381, 4468289, 4497237.
1392 if (C->need_stack_bang(framesize) && UseStackBanging) {
1393 // Unfortunately we cannot use the function provided in
1394 // assembler.cpp as we have to emulate the pipes. So I had to
1395 // insert the code of generate_stack_overflow_check(), see
1396 // assembler.cpp for some illuminative comments.
1397 const int page_size = os::vm_page_size();
1398 int bang_end = StackShadowPages*page_size;
1400 // This is how far the previous frame's stack banging extended.
1401 const int bang_end_safe = bang_end;
1403 if (framesize > page_size) {
1404 bang_end += framesize;
1405 }
1407 int bang_offset = bang_end_safe;
1409 while (bang_offset <= bang_end) {
1410 // Need at least one stack bang at end of shadow zone.
1412 // Again I had to copy code, this time from assembler_ppc64.cpp,
1413 // bang_stack_with_offset - see there for comments.
1415 // Stack grows down, caller passes positive offset.
1416 assert(bang_offset > 0, "must bang with positive offset");
1418 long stdoffset = -bang_offset;
1420 if (Assembler::is_simm(stdoffset, 16)) {
1421 // Signed 16 bit offset, a simple std is ok.
1422 if (UseLoadInstructionsForStackBangingPPC64) {
1423 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1424 } else {
1425 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1426 }
1427 } else if (Assembler::is_simm(stdoffset, 31)) {
1428 // Use largeoffset calculations for addis & ld/std.
1429 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1430 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1432 Register tmp = R11;
1433 ___(addis) addis(tmp, R1_SP, hi);
1434 if (UseLoadInstructionsForStackBangingPPC64) {
1435 ___(ld) ld(R0, lo, tmp);
1436 } else {
1437 ___(std) std(R0, lo, tmp);
1438 }
1439 } else {
1440 ShouldNotReachHere();
1441 }
1443 bang_offset += page_size;
1444 }
1445 // R11 trashed
1446 } // C->need_stack_bang(framesize) && UseStackBanging
1448 unsigned int bytes = (unsigned int)framesize;
1449 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1450 ciMethod *currMethod = C -> method();
1452 // Optimized version for most common case.
1453 if (UsePower6SchedulerPPC64 &&
1454 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1455 !(false /* ConstantsALot TODO: PPC port*/)) {
1456 ___(or) mr(callers_sp, R1_SP);
1457 ___(std) std(return_pc, _abi(lr), R1_SP);
1458 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1459 return;
1460 }
1462 if (!method_is_frameless) {
1463 // Get callers sp.
1464 ___(or) mr(callers_sp, R1_SP);
1466 // Push method's frame, modifies SP.
1467 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1468 // The ABI is already accounted for in 'framesize' via the
1469 // 'out_preserve' area.
1470 Register tmp = push_frame_temp;
1471 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1472 if (Assembler::is_simm(-offset, 16)) {
1473 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1474 } else {
1475 long x = -offset;
1476 // Had to insert load_const(tmp, -offset).
1477 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1478 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1479 ___(rldicr) sldi(tmp, tmp, 32);
1480 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1481 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1483 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1484 }
1485 }
1486 #if 0 // TODO: PPC port
1487 // For testing large constant pools, emit a lot of constants to constant pool.
1488 // "Randomize" const_size.
1489 if (ConstantsALot) {
1490 const int num_consts = const_size();
1491 for (int i = 0; i < num_consts; i++) {
1492 __ long_constant(0xB0B5B00BBABE);
1493 }
1494 }
1495 #endif
1496 if (!method_is_frameless) {
1497 // Save return pc.
1498 ___(std) std(return_pc, _abi(lr), callers_sp);
1499 }
1500 }
1501 #undef ___
1502 #undef ___stop
1503 #undef ___advance
1505 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1506 // Variable size. determine dynamically.
1507 return MachNode::size(ra_);
1508 }
1510 int MachPrologNode::reloc() const {
1511 // Return number of relocatable values contained in this instruction.
1512 return 1; // 1 reloc entry for load_const(toc).
1513 }
1515 //=============================================================================
1517 #ifndef PRODUCT
1518 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1519 Compile* C = ra_->C;
1521 st->print("EPILOG\n\t");
1522 st->print("restore return pc\n\t");
1523 st->print("pop frame\n\t");
1525 if (do_polling() && C->is_method_compilation()) {
1526 st->print("touch polling page\n\t");
1527 }
1528 }
1529 #endif
1531 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1532 Compile* C = ra_->C;
1533 MacroAssembler _masm(&cbuf);
1535 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1536 assert(framesize >= 0, "negative frame-size?");
1538 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1539 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1540 const Register return_pc = R11;
1541 const Register polling_page = R12;
1543 if (!method_is_frameless) {
1544 // Restore return pc relative to callers' sp.
1545 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1546 }
1548 if (method_needs_polling) {
1549 if (LoadPollAddressFromThread) {
1550 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1551 Unimplemented();
1552 } else {
1553 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1554 }
1555 }
1557 if (!method_is_frameless) {
1558 // Move return pc to LR.
1559 __ mtlr(return_pc);
1560 // Pop frame (fixed frame-size).
1561 __ addi(R1_SP, R1_SP, (int)framesize);
1562 }
1564 if (method_needs_polling) {
1565 // We need to mark the code position where the load from the safepoint
1566 // polling page was emitted as relocInfo::poll_return_type here.
1567 __ relocate(relocInfo::poll_return_type);
1568 __ load_from_polling_page(polling_page);
1569 }
1570 }
1572 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1573 // Variable size. Determine dynamically.
1574 return MachNode::size(ra_);
1575 }
1577 int MachEpilogNode::reloc() const {
1578 // Return number of relocatable values contained in this instruction.
1579 return 1; // 1 for load_from_polling_page.
1580 }
1582 const Pipeline * MachEpilogNode::pipeline() const {
1583 return MachNode::pipeline_class();
1584 }
1586 // This method seems to be obsolete. It is declared in machnode.hpp
1587 // and defined in all *.ad files, but it is never called. Should we
1588 // get rid of it?
1589 int MachEpilogNode::safepoint_offset() const {
1590 assert(do_polling(), "no return for this epilog node");
1591 return 0;
1592 }
1594 #if 0 // TODO: PPC port
1595 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1596 MacroAssembler _masm(&cbuf);
1597 if (LoadPollAddressFromThread) {
1598 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1599 } else {
1600 _masm.nop();
1601 }
1602 }
1604 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1605 if (LoadPollAddressFromThread) {
1606 return 4;
1607 } else {
1608 return 4;
1609 }
1610 }
1612 #ifndef PRODUCT
1613 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1614 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1615 }
1616 #endif
1618 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1619 return RSCRATCH1_BITS64_REG_mask();
1620 }
1621 #endif // PPC port
1623 // =============================================================================
1625 // Figure out which register class each belongs in: rc_int, rc_float or
1626 // rc_stack.
1627 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1629 static enum RC rc_class(OptoReg::Name reg) {
1630 // Return the register class for the given register. The given register
1631 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1632 // enumeration in adGlobals_ppc64.hpp.
1634 if (reg == OptoReg::Bad) return rc_bad;
1636 // We have 64 integer register halves, starting at index 0.
1637 if (reg < 64) return rc_int;
1639 // We have 64 floating-point register halves, starting at index 64.
1640 if (reg < 64+64) return rc_float;
1642 // Between float regs & stack are the flags regs.
1643 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1645 return rc_stack;
1646 }
1648 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1649 bool do_print, Compile* C, outputStream *st) {
1651 assert(opcode == Assembler::LD_OPCODE ||
1652 opcode == Assembler::STD_OPCODE ||
1653 opcode == Assembler::LWZ_OPCODE ||
1654 opcode == Assembler::STW_OPCODE ||
1655 opcode == Assembler::LFD_OPCODE ||
1656 opcode == Assembler::STFD_OPCODE ||
1657 opcode == Assembler::LFS_OPCODE ||
1658 opcode == Assembler::STFS_OPCODE,
1659 "opcode not supported");
1661 if (cbuf) {
1662 int d =
1663 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1664 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1665 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1666 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1667 }
1668 #ifndef PRODUCT
1669 else if (do_print) {
1670 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1671 op_str,
1672 Matcher::regName[reg],
1673 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1674 }
1675 #endif
1676 return 4; // size
1677 }
1679 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1680 Compile* C = ra_->C;
1682 // Get registers to move.
1683 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1684 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1685 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1686 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1688 enum RC src_hi_rc = rc_class(src_hi);
1689 enum RC src_lo_rc = rc_class(src_lo);
1690 enum RC dst_hi_rc = rc_class(dst_hi);
1691 enum RC dst_lo_rc = rc_class(dst_lo);
1693 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1694 if (src_hi != OptoReg::Bad)
1695 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1696 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1697 "expected aligned-adjacent pairs");
1698 // Generate spill code!
1699 int size = 0;
1701 if (src_lo == dst_lo && src_hi == dst_hi)
1702 return size; // Self copy, no move.
1704 // --------------------------------------
1705 // Memory->Memory Spill. Use R0 to hold the value.
1706 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1707 int src_offset = ra_->reg2offset(src_lo);
1708 int dst_offset = ra_->reg2offset(dst_lo);
1709 if (src_hi != OptoReg::Bad) {
1710 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1711 "expected same type of move for high parts");
1712 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1713 if (!cbuf && !do_size) st->print("\n\t");
1714 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1715 } else {
1716 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1717 if (!cbuf && !do_size) st->print("\n\t");
1718 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1719 }
1720 return size;
1721 }
1723 // --------------------------------------
1724 // Check for float->int copy; requires a trip through memory.
1725 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1726 Unimplemented();
1727 }
1729 // --------------------------------------
1730 // Check for integer reg-reg copy.
1731 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1732 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1733 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1734 size = (Rsrc != Rdst) ? 4 : 0;
1736 if (cbuf) {
1737 MacroAssembler _masm(cbuf);
1738 if (size) {
1739 __ mr(Rdst, Rsrc);
1740 }
1741 }
1742 #ifndef PRODUCT
1743 else if (!do_size) {
1744 if (size) {
1745 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1746 } else {
1747 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1748 }
1749 }
1750 #endif
1751 return size;
1752 }
1754 // Check for integer store.
1755 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1756 int dst_offset = ra_->reg2offset(dst_lo);
1757 if (src_hi != OptoReg::Bad) {
1758 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1759 "expected same type of move for high parts");
1760 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1761 } else {
1762 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1763 }
1764 return size;
1765 }
1767 // Check for integer load.
1768 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1769 int src_offset = ra_->reg2offset(src_lo);
1770 if (src_hi != OptoReg::Bad) {
1771 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1772 "expected same type of move for high parts");
1773 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1774 } else {
1775 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1776 }
1777 return size;
1778 }
1780 // Check for float reg-reg copy.
1781 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1782 if (cbuf) {
1783 MacroAssembler _masm(cbuf);
1784 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1785 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1786 __ fmr(Rdst, Rsrc);
1787 }
1788 #ifndef PRODUCT
1789 else if (!do_size) {
1790 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1791 }
1792 #endif
1793 return 4;
1794 }
1796 // Check for float store.
1797 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1798 int dst_offset = ra_->reg2offset(dst_lo);
1799 if (src_hi != OptoReg::Bad) {
1800 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1801 "expected same type of move for high parts");
1802 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1803 } else {
1804 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1805 }
1806 return size;
1807 }
1809 // Check for float load.
1810 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1811 int src_offset = ra_->reg2offset(src_lo);
1812 if (src_hi != OptoReg::Bad) {
1813 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1814 "expected same type of move for high parts");
1815 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1816 } else {
1817 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1818 }
1819 return size;
1820 }
1822 // --------------------------------------------------------------------
1823 // Check for hi bits still needing moving. Only happens for misaligned
1824 // arguments to native calls.
1825 if (src_hi == dst_hi)
1826 return size; // Self copy; no move.
1828 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1829 ShouldNotReachHere(); // Unimplemented
1830 return 0;
1831 }
1833 #ifndef PRODUCT
1834 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1835 if (!ra_)
1836 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1837 else
1838 implementation(NULL, ra_, false, st);
1839 }
1840 #endif
1842 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1843 implementation(&cbuf, ra_, false, NULL);
1844 }
1846 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1847 return implementation(NULL, ra_, true, NULL);
1848 }
1850 #if 0 // TODO: PPC port
1851 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1852 #ifndef PRODUCT
1853 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1854 #endif
1855 assert(ra_->node_regs_max_index() != 0, "");
1857 // Get registers to move.
1858 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1859 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1860 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1861 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1863 enum RC src_lo_rc = rc_class(src_lo);
1864 enum RC dst_lo_rc = rc_class(dst_lo);
1866 if (src_lo == dst_lo && src_hi == dst_hi)
1867 return ppc64Opcode_none; // Self copy, no move.
1869 // --------------------------------------
1870 // Memory->Memory Spill. Use R0 to hold the value.
1871 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1872 return ppc64Opcode_compound;
1873 }
1875 // --------------------------------------
1876 // Check for float->int copy; requires a trip through memory.
1877 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1878 Unimplemented();
1879 }
1881 // --------------------------------------
1882 // Check for integer reg-reg copy.
1883 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1884 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1885 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1886 if (Rsrc == Rdst) {
1887 return ppc64Opcode_none;
1888 } else {
1889 return ppc64Opcode_or;
1890 }
1891 }
1893 // Check for integer store.
1894 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1895 if (src_hi != OptoReg::Bad) {
1896 return ppc64Opcode_std;
1897 } else {
1898 return ppc64Opcode_stw;
1899 }
1900 }
1902 // Check for integer load.
1903 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1904 if (src_hi != OptoReg::Bad) {
1905 return ppc64Opcode_ld;
1906 } else {
1907 return ppc64Opcode_lwz;
1908 }
1909 }
1911 // Check for float reg-reg copy.
1912 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1913 return ppc64Opcode_fmr;
1914 }
1916 // Check for float store.
1917 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1918 if (src_hi != OptoReg::Bad) {
1919 return ppc64Opcode_stfd;
1920 } else {
1921 return ppc64Opcode_stfs;
1922 }
1923 }
1925 // Check for float load.
1926 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1927 if (src_hi != OptoReg::Bad) {
1928 return ppc64Opcode_lfd;
1929 } else {
1930 return ppc64Opcode_lfs;
1931 }
1932 }
1934 // --------------------------------------------------------------------
1935 // Check for hi bits still needing moving. Only happens for misaligned
1936 // arguments to native calls.
1937 if (src_hi == dst_hi)
1938 return ppc64Opcode_none; // Self copy; no move.
1940 ShouldNotReachHere();
1941 return ppc64Opcode_undefined;
1942 }
1943 #endif // PPC port
1945 #ifndef PRODUCT
1946 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1947 st->print("NOP \t// %d nops to pad for loops.", _count);
1948 }
1949 #endif
1951 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1952 MacroAssembler _masm(&cbuf);
1953 // _count contains the number of nops needed for padding.
1954 for (int i = 0; i < _count; i++) {
1955 __ nop();
1956 }
1957 }
1959 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1960 return _count * 4;
1961 }
1963 #ifndef PRODUCT
1964 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1965 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1966 int reg = ra_->get_reg_first(this);
1967 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset);
1968 }
1969 #endif
1971 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1972 MacroAssembler _masm(&cbuf);
1974 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1975 int reg = ra_->get_encode(this);
1977 if (Assembler::is_simm(offset, 16)) {
1978 __ addi(as_Register(reg), R1, offset);
1979 } else {
1980 ShouldNotReachHere();
1981 }
1982 }
1984 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1985 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1986 return 4;
1987 }
1989 #ifndef PRODUCT
1990 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1991 st->print_cr("---- MachUEPNode ----");
1992 st->print_cr("...");
1993 }
1994 #endif
1996 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1997 // This is the unverified entry point.
1998 MacroAssembler _masm(&cbuf);
2000 // Inline_cache contains a klass.
2001 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2002 Register receiver_klass = R0; // tmp
2004 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2005 assert(R11_scratch1 == R11, "need prologue scratch register");
2007 // Check for NULL argument if we don't have implicit null checks.
2008 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2009 if (TrapBasedNullChecks) {
2010 __ trap_null_check(R3_ARG1);
2011 } else {
2012 Label valid;
2013 __ cmpdi(CCR0, R3_ARG1, 0);
2014 __ bne_predict_taken(CCR0, valid);
2015 // We have a null argument, branch to ic_miss_stub.
2016 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2017 relocInfo::runtime_call_type);
2018 __ bind(valid);
2019 }
2020 }
2021 // Assume argument is not NULL, load klass from receiver.
2022 __ load_klass(receiver_klass, R3_ARG1);
2024 if (TrapBasedICMissChecks) {
2025 __ trap_ic_miss_check(receiver_klass, ic_klass);
2026 } else {
2027 Label valid;
2028 __ cmpd(CCR0, receiver_klass, ic_klass);
2029 __ beq_predict_taken(CCR0, valid);
2030 // We have an unexpected klass, branch to ic_miss_stub.
2031 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2032 relocInfo::runtime_call_type);
2033 __ bind(valid);
2034 }
2036 // Argument is valid and klass is as expected, continue.
2037 }
2039 #if 0 // TODO: PPC port
2040 // Optimize UEP code on z (save a load_const() call in main path).
2041 int MachUEPNode::ep_offset() {
2042 return 0;
2043 }
2044 #endif
2046 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2047 // Variable size. Determine dynamically.
2048 return MachNode::size(ra_);
2049 }
2051 //=============================================================================
2053 %} // interrupt source
2055 source_hpp %{ // Header information of the source block.
2057 class HandlerImpl {
2059 public:
2061 static int emit_exception_handler(CodeBuffer &cbuf);
2062 static int emit_deopt_handler(CodeBuffer& cbuf);
2064 static uint size_exception_handler() {
2065 // The exception_handler is a b64_patchable.
2066 return MacroAssembler::b64_patchable_size;
2067 }
2069 static uint size_deopt_handler() {
2070 // The deopt_handler is a bl64_patchable.
2071 return MacroAssembler::bl64_patchable_size;
2072 }
2074 };
2076 %} // end source_hpp
2078 source %{
2080 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2081 MacroAssembler _masm(&cbuf);
2083 address base = __ start_a_stub(size_exception_handler());
2084 if (base == NULL) return 0; // CodeBuffer::expand failed
2086 int offset = __ offset();
2087 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2088 relocInfo::runtime_call_type);
2089 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2090 __ end_a_stub();
2092 return offset;
2093 }
2095 // The deopt_handler is like the exception handler, but it calls to
2096 // the deoptimization blob instead of jumping to the exception blob.
2097 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2098 MacroAssembler _masm(&cbuf);
2100 address base = __ start_a_stub(size_deopt_handler());
2101 if (base == NULL) return 0; // CodeBuffer::expand failed
2103 int offset = __ offset();
2104 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2105 relocInfo::runtime_call_type);
2106 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2107 __ end_a_stub();
2109 return offset;
2110 }
2112 //=============================================================================
2114 // Use a frame slots bias for frameless methods if accessing the stack.
2115 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2116 if (as_Register(reg_enc) == R1_SP) {
2117 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2118 }
2119 return 0;
2120 }
2122 const bool Matcher::match_rule_supported(int opcode) {
2123 if (!has_match_rule(opcode))
2124 return false;
2126 switch (opcode) {
2127 case Op_SqrtD:
2128 return VM_Version::has_fsqrt();
2129 case Op_CountLeadingZerosI:
2130 case Op_CountLeadingZerosL:
2131 case Op_CountTrailingZerosI:
2132 case Op_CountTrailingZerosL:
2133 if (!UseCountLeadingZerosInstructionsPPC64)
2134 return false;
2135 break;
2137 case Op_PopCountI:
2138 case Op_PopCountL:
2139 return (UsePopCountInstruction && VM_Version::has_popcntw());
2141 case Op_StrComp:
2142 return SpecialStringCompareTo;
2143 case Op_StrEquals:
2144 return SpecialStringEquals;
2145 case Op_StrIndexOf:
2146 return SpecialStringIndexOf;
2147 }
2149 return true; // Per default match rules are supported.
2150 }
2152 int Matcher::regnum_to_fpu_offset(int regnum) {
2153 // No user for this method?
2154 Unimplemented();
2155 return 999;
2156 }
2158 const bool Matcher::convL2FSupported(void) {
2159 // fcfids can do the conversion (>= Power7).
2160 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2161 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2162 }
2164 // Vector width in bytes.
2165 const int Matcher::vector_width_in_bytes(BasicType bt) {
2166 assert(MaxVectorSize == 8, "");
2167 return 8;
2168 }
2170 // Vector ideal reg.
2171 const int Matcher::vector_ideal_reg(int size) {
2172 assert(MaxVectorSize == 8 && size == 8, "");
2173 return Op_RegL;
2174 }
2176 const int Matcher::vector_shift_count_ideal_reg(int size) {
2177 fatal("vector shift is not supported");
2178 return Node::NotAMachineReg;
2179 }
2181 // Limits on vector size (number of elements) loaded into vector.
2182 const int Matcher::max_vector_size(const BasicType bt) {
2183 assert(is_java_primitive(bt), "only primitive type vectors");
2184 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2185 }
2187 const int Matcher::min_vector_size(const BasicType bt) {
2188 return max_vector_size(bt); // Same as max.
2189 }
2191 // PPC doesn't support misaligned vectors store/load.
2192 const bool Matcher::misaligned_vectors_ok() {
2193 return false;
2194 }
2196 // PPC AES support not yet implemented
2197 const bool Matcher::pass_original_key_for_aes() {
2198 return false;
2199 }
2201 // RETURNS: whether this branch offset is short enough that a short
2202 // branch can be used.
2203 //
2204 // If the platform does not provide any short branch variants, then
2205 // this method should return `false' for offset 0.
2206 //
2207 // `Compile::Fill_buffer' will decide on basis of this information
2208 // whether to do the pass `Compile::Shorten_branches' at all.
2209 //
2210 // And `Compile::Shorten_branches' will decide on basis of this
2211 // information whether to replace particular branch sites by short
2212 // ones.
2213 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2214 // Is the offset within the range of a ppc64 pc relative branch?
2215 bool b;
2217 const int safety_zone = 3 * BytesPerInstWord;
2218 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2219 29 - 16 + 1 + 2);
2220 return b;
2221 }
2223 const bool Matcher::isSimpleConstant64(jlong value) {
2224 // Probably always true, even if a temp register is required.
2225 return true;
2226 }
2227 /* TODO: PPC port
2228 // Make a new machine dependent decode node (with its operands).
2229 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2230 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2231 "This method is only implemented for unscaled cOops mode so far");
2232 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2233 decode->set_opnd_array(0, new (C) iRegPdstOper());
2234 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2235 return decode;
2236 }
2237 */
2238 // Threshold size for cleararray.
2239 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2241 // false => size gets scaled to BytesPerLong, ok.
2242 const bool Matcher::init_array_count_is_in_bytes = false;
2244 // Use conditional move (CMOVL) on Power7.
2245 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2247 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2248 // fsel doesn't accept a condition register as input, so this would be slightly different.
2249 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2251 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2252 const bool Matcher::require_postalloc_expand = true;
2254 // Should the Matcher clone shifts on addressing modes, expecting them to
2255 // be subsumed into complex addressing expressions or compute them into
2256 // registers? True for Intel but false for most RISCs.
2257 const bool Matcher::clone_shift_expressions = false;
2259 // Do we need to mask the count passed to shift instructions or does
2260 // the cpu only look at the lower 5/6 bits anyway?
2261 // Off, as masks are generated in expand rules where required.
2262 // Constant shift counts are handled in Ideal phase.
2263 const bool Matcher::need_masked_shift_count = false;
2265 // This affects two different things:
2266 // - how Decode nodes are matched
2267 // - how ImplicitNullCheck opportunities are recognized
2268 // If true, the matcher will try to remove all Decodes and match them
2269 // (as operands) into nodes. NullChecks are not prepared to deal with
2270 // Decodes by final_graph_reshaping().
2271 // If false, final_graph_reshaping() forces the decode behind the Cmp
2272 // for a NullCheck. The matcher matches the Decode node into a register.
2273 // Implicit_null_check optimization moves the Decode along with the
2274 // memory operation back up before the NullCheck.
2275 bool Matcher::narrow_oop_use_complex_address() {
2276 // TODO: PPC port if (MatchDecodeNodes) return true;
2277 return false;
2278 }
2280 bool Matcher::narrow_klass_use_complex_address() {
2281 NOT_LP64(ShouldNotCallThis());
2282 assert(UseCompressedClassPointers, "only for compressed klass code");
2283 // TODO: PPC port if (MatchDecodeNodes) return true;
2284 return false;
2285 }
2287 // Is it better to copy float constants, or load them directly from memory?
2288 // Intel can load a float constant from a direct address, requiring no
2289 // extra registers. Most RISCs will have to materialize an address into a
2290 // register first, so they would do better to copy the constant from stack.
2291 const bool Matcher::rematerialize_float_constants = false;
2293 // If CPU can load and store mis-aligned doubles directly then no fixup is
2294 // needed. Else we split the double into 2 integer pieces and move it
2295 // piece-by-piece. Only happens when passing doubles into C code as the
2296 // Java calling convention forces doubles to be aligned.
2297 const bool Matcher::misaligned_doubles_ok = true;
2299 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2300 Unimplemented();
2301 }
2303 // Advertise here if the CPU requires explicit rounding operations
2304 // to implement the UseStrictFP mode.
2305 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2307 // Do floats take an entire double register or just half?
2308 //
2309 // A float occupies a ppc64 double register. For the allocator, a
2310 // ppc64 double register appears as a pair of float registers.
2311 bool Matcher::float_in_double() { return true; }
2313 // Do ints take an entire long register or just half?
2314 // The relevant question is how the int is callee-saved:
2315 // the whole long is written but de-opt'ing will have to extract
2316 // the relevant 32 bits.
2317 const bool Matcher::int_in_long = true;
2319 // Constants for c2c and c calling conventions.
2321 const MachRegisterNumbers iarg_reg[8] = {
2322 R3_num, R4_num, R5_num, R6_num,
2323 R7_num, R8_num, R9_num, R10_num
2324 };
2326 const MachRegisterNumbers farg_reg[13] = {
2327 F1_num, F2_num, F3_num, F4_num,
2328 F5_num, F6_num, F7_num, F8_num,
2329 F9_num, F10_num, F11_num, F12_num,
2330 F13_num
2331 };
2333 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2335 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2337 // Return whether or not this register is ever used as an argument. This
2338 // function is used on startup to build the trampoline stubs in generateOptoStub.
2339 // Registers not mentioned will be killed by the VM call in the trampoline, and
2340 // arguments in those registers not be available to the callee.
2341 bool Matcher::can_be_java_arg(int reg) {
2342 // We return true for all registers contained in iarg_reg[] and
2343 // farg_reg[] and their virtual halves.
2344 // We must include the virtual halves in order to get STDs and LDs
2345 // instead of STWs and LWs in the trampoline stubs.
2347 if ( reg == R3_num || reg == R3_H_num
2348 || reg == R4_num || reg == R4_H_num
2349 || reg == R5_num || reg == R5_H_num
2350 || reg == R6_num || reg == R6_H_num
2351 || reg == R7_num || reg == R7_H_num
2352 || reg == R8_num || reg == R8_H_num
2353 || reg == R9_num || reg == R9_H_num
2354 || reg == R10_num || reg == R10_H_num)
2355 return true;
2357 if ( reg == F1_num || reg == F1_H_num
2358 || reg == F2_num || reg == F2_H_num
2359 || reg == F3_num || reg == F3_H_num
2360 || reg == F4_num || reg == F4_H_num
2361 || reg == F5_num || reg == F5_H_num
2362 || reg == F6_num || reg == F6_H_num
2363 || reg == F7_num || reg == F7_H_num
2364 || reg == F8_num || reg == F8_H_num
2365 || reg == F9_num || reg == F9_H_num
2366 || reg == F10_num || reg == F10_H_num
2367 || reg == F11_num || reg == F11_H_num
2368 || reg == F12_num || reg == F12_H_num
2369 || reg == F13_num || reg == F13_H_num)
2370 return true;
2372 return false;
2373 }
2375 bool Matcher::is_spillable_arg(int reg) {
2376 return can_be_java_arg(reg);
2377 }
2379 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2380 return false;
2381 }
2383 // Register for DIVI projection of divmodI.
2384 RegMask Matcher::divI_proj_mask() {
2385 ShouldNotReachHere();
2386 return RegMask();
2387 }
2389 // Register for MODI projection of divmodI.
2390 RegMask Matcher::modI_proj_mask() {
2391 ShouldNotReachHere();
2392 return RegMask();
2393 }
2395 // Register for DIVL projection of divmodL.
2396 RegMask Matcher::divL_proj_mask() {
2397 ShouldNotReachHere();
2398 return RegMask();
2399 }
2401 // Register for MODL projection of divmodL.
2402 RegMask Matcher::modL_proj_mask() {
2403 ShouldNotReachHere();
2404 return RegMask();
2405 }
2407 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2408 return RegMask();
2409 }
2411 %}
2413 //----------ENCODING BLOCK-----------------------------------------------------
2414 // This block specifies the encoding classes used by the compiler to output
2415 // byte streams. Encoding classes are parameterized macros used by
2416 // Machine Instruction Nodes in order to generate the bit encoding of the
2417 // instruction. Operands specify their base encoding interface with the
2418 // interface keyword. There are currently supported four interfaces,
2419 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2420 // operand to generate a function which returns its register number when
2421 // queried. CONST_INTER causes an operand to generate a function which
2422 // returns the value of the constant when queried. MEMORY_INTER causes an
2423 // operand to generate four functions which return the Base Register, the
2424 // Index Register, the Scale Value, and the Offset Value of the operand when
2425 // queried. COND_INTER causes an operand to generate six functions which
2426 // return the encoding code (ie - encoding bits for the instruction)
2427 // associated with each basic boolean condition for a conditional instruction.
2428 //
2429 // Instructions specify two basic values for encoding. Again, a function
2430 // is available to check if the constant displacement is an oop. They use the
2431 // ins_encode keyword to specify their encoding classes (which must be
2432 // a sequence of enc_class names, and their parameters, specified in
2433 // the encoding block), and they use the
2434 // opcode keyword to specify, in order, their primary, secondary, and
2435 // tertiary opcode. Only the opcode sections which a particular instruction
2436 // needs for encoding need to be specified.
2437 encode %{
2438 enc_class enc_unimplemented %{
2439 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2440 MacroAssembler _masm(&cbuf);
2441 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2442 %}
2444 enc_class enc_untested %{
2445 #ifdef ASSERT
2446 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2447 MacroAssembler _masm(&cbuf);
2448 __ untested("Untested mach node encoding in AD file.");
2449 #else
2450 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2451 #endif
2452 %}
2454 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2455 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2456 MacroAssembler _masm(&cbuf);
2457 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2458 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2459 %}
2461 // Load acquire.
2462 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2463 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2464 MacroAssembler _masm(&cbuf);
2465 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2466 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2467 __ twi_0($dst$$Register);
2468 __ isync();
2469 %}
2471 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2472 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2474 MacroAssembler _masm(&cbuf);
2475 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2476 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2477 %}
2479 // Load acquire.
2480 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2481 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2483 MacroAssembler _masm(&cbuf);
2484 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2485 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2486 __ twi_0($dst$$Register);
2487 __ isync();
2488 %}
2490 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2491 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2493 MacroAssembler _masm(&cbuf);
2494 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2495 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2496 %}
2498 // Load acquire.
2499 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2500 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2502 MacroAssembler _masm(&cbuf);
2503 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2504 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2505 __ twi_0($dst$$Register);
2506 __ isync();
2507 %}
2509 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2510 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2511 MacroAssembler _masm(&cbuf);
2512 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2513 // Operand 'ds' requires 4-alignment.
2514 assert((Idisp & 0x3) == 0, "unaligned offset");
2515 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2516 %}
2518 // Load acquire.
2519 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2520 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2521 MacroAssembler _masm(&cbuf);
2522 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2523 // Operand 'ds' requires 4-alignment.
2524 assert((Idisp & 0x3) == 0, "unaligned offset");
2525 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2526 __ twi_0($dst$$Register);
2527 __ isync();
2528 %}
2530 enc_class enc_lfd(RegF dst, memory mem) %{
2531 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2532 MacroAssembler _masm(&cbuf);
2533 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2534 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2535 %}
2537 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2538 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2540 MacroAssembler _masm(&cbuf);
2541 int toc_offset = 0;
2543 if (!ra_->C->in_scratch_emit_size()) {
2544 address const_toc_addr;
2545 // Create a non-oop constant, no relocation needed.
2546 // If it is an IC, it has a virtual_call_Relocation.
2547 const_toc_addr = __ long_constant((jlong)$src$$constant);
2549 // Get the constant's TOC offset.
2550 toc_offset = __ offset_to_method_toc(const_toc_addr);
2552 // Keep the current instruction offset in mind.
2553 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2554 }
2556 __ ld($dst$$Register, toc_offset, $toc$$Register);
2557 %}
2559 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2560 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2562 MacroAssembler _masm(&cbuf);
2564 if (!ra_->C->in_scratch_emit_size()) {
2565 address const_toc_addr;
2566 // Create a non-oop constant, no relocation needed.
2567 // If it is an IC, it has a virtual_call_Relocation.
2568 const_toc_addr = __ long_constant((jlong)$src$$constant);
2570 // Get the constant's TOC offset.
2571 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2572 // Store the toc offset of the constant.
2573 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2575 // Also keep the current instruction offset in mind.
2576 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2577 }
2579 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2580 %}
2582 %} // encode
2584 source %{
2586 typedef struct {
2587 loadConL_hiNode *_large_hi;
2588 loadConL_loNode *_large_lo;
2589 loadConLNode *_small;
2590 MachNode *_last;
2591 } loadConLNodesTuple;
2593 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2594 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2595 loadConLNodesTuple nodes;
2597 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2598 if (large_constant_pool) {
2599 // Create new nodes.
2600 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2601 loadConL_loNode *m2 = new (C) loadConL_loNode();
2603 // inputs for new nodes
2604 m1->add_req(NULL, toc);
2605 m2->add_req(NULL, m1);
2607 // operands for new nodes
2608 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2609 m1->_opnds[1] = immSrc; // src
2610 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2611 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2612 m2->_opnds[1] = immSrc; // src
2613 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2615 // Initialize ins_attrib TOC fields.
2616 m1->_const_toc_offset = -1;
2617 m2->_const_toc_offset_hi_node = m1;
2619 // Initialize ins_attrib instruction offset.
2620 m1->_cbuf_insts_offset = -1;
2622 // register allocation for new nodes
2623 ra_->set_pair(m1->_idx, reg_second, reg_first);
2624 ra_->set_pair(m2->_idx, reg_second, reg_first);
2626 // Create result.
2627 nodes._large_hi = m1;
2628 nodes._large_lo = m2;
2629 nodes._small = NULL;
2630 nodes._last = nodes._large_lo;
2631 assert(m2->bottom_type()->isa_long(), "must be long");
2632 } else {
2633 loadConLNode *m2 = new (C) loadConLNode();
2635 // inputs for new nodes
2636 m2->add_req(NULL, toc);
2638 // operands for new nodes
2639 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2640 m2->_opnds[1] = immSrc; // src
2641 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2643 // Initialize ins_attrib instruction offset.
2644 m2->_cbuf_insts_offset = -1;
2646 // register allocation for new nodes
2647 ra_->set_pair(m2->_idx, reg_second, reg_first);
2649 // Create result.
2650 nodes._large_hi = NULL;
2651 nodes._large_lo = NULL;
2652 nodes._small = m2;
2653 nodes._last = nodes._small;
2654 assert(m2->bottom_type()->isa_long(), "must be long");
2655 }
2657 return nodes;
2658 }
2660 %} // source
2662 encode %{
2663 // Postalloc expand emitter for loading a long constant from the method's TOC.
2664 // Enc_class needed as consttanttablebase is not supported by postalloc
2665 // expand.
2666 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2667 // Create new nodes.
2668 loadConLNodesTuple loadConLNodes =
2669 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2670 ra_->get_reg_second(this), ra_->get_reg_first(this));
2672 // Push new nodes.
2673 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2674 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2676 // some asserts
2677 assert(nodes->length() >= 1, "must have created at least 1 node");
2678 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2679 %}
2681 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2682 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2684 MacroAssembler _masm(&cbuf);
2685 int toc_offset = 0;
2687 if (!ra_->C->in_scratch_emit_size()) {
2688 intptr_t val = $src$$constant;
2689 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2690 address const_toc_addr;
2691 if (constant_reloc == relocInfo::oop_type) {
2692 // Create an oop constant and a corresponding relocation.
2693 AddressLiteral a = __ allocate_oop_address((jobject)val);
2694 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2695 __ relocate(a.rspec());
2696 } else if (constant_reloc == relocInfo::metadata_type) {
2697 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2698 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2699 __ relocate(a.rspec());
2700 } else {
2701 // Create a non-oop constant, no relocation needed.
2702 const_toc_addr = __ long_constant((jlong)$src$$constant);
2703 }
2705 // Get the constant's TOC offset.
2706 toc_offset = __ offset_to_method_toc(const_toc_addr);
2707 }
2709 __ ld($dst$$Register, toc_offset, $toc$$Register);
2710 %}
2712 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2713 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2715 MacroAssembler _masm(&cbuf);
2716 if (!ra_->C->in_scratch_emit_size()) {
2717 intptr_t val = $src$$constant;
2718 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2719 address const_toc_addr;
2720 if (constant_reloc == relocInfo::oop_type) {
2721 // Create an oop constant and a corresponding relocation.
2722 AddressLiteral a = __ allocate_oop_address((jobject)val);
2723 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2724 __ relocate(a.rspec());
2725 } else if (constant_reloc == relocInfo::metadata_type) {
2726 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2727 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2728 __ relocate(a.rspec());
2729 } else { // non-oop pointers, e.g. card mark base, heap top
2730 // Create a non-oop constant, no relocation needed.
2731 const_toc_addr = __ long_constant((jlong)$src$$constant);
2732 }
2734 // Get the constant's TOC offset.
2735 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2736 // Store the toc offset of the constant.
2737 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2738 }
2740 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2741 %}
2743 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2744 // Enc_class needed as consttanttablebase is not supported by postalloc
2745 // expand.
2746 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2747 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2748 if (large_constant_pool) {
2749 // Create new nodes.
2750 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2751 loadConP_loNode *m2 = new (C) loadConP_loNode();
2753 // inputs for new nodes
2754 m1->add_req(NULL, n_toc);
2755 m2->add_req(NULL, m1);
2757 // operands for new nodes
2758 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2759 m1->_opnds[1] = op_src; // src
2760 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2761 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2762 m2->_opnds[1] = op_src; // src
2763 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2765 // Initialize ins_attrib TOC fields.
2766 m1->_const_toc_offset = -1;
2767 m2->_const_toc_offset_hi_node = m1;
2769 // Register allocation for new nodes.
2770 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2771 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2773 nodes->push(m1);
2774 nodes->push(m2);
2775 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2776 } else {
2777 loadConPNode *m2 = new (C) loadConPNode();
2779 // inputs for new nodes
2780 m2->add_req(NULL, n_toc);
2782 // operands for new nodes
2783 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2784 m2->_opnds[1] = op_src; // src
2785 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2787 // Register allocation for new nodes.
2788 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2790 nodes->push(m2);
2791 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2792 }
2793 %}
2795 // Enc_class needed as consttanttablebase is not supported by postalloc
2796 // expand.
2797 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2798 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2800 MachNode *m2;
2801 if (large_constant_pool) {
2802 m2 = new (C) loadConFCompNode();
2803 } else {
2804 m2 = new (C) loadConFNode();
2805 }
2806 // inputs for new nodes
2807 m2->add_req(NULL, n_toc);
2809 // operands for new nodes
2810 m2->_opnds[0] = op_dst;
2811 m2->_opnds[1] = op_src;
2812 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2814 // register allocation for new nodes
2815 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2816 nodes->push(m2);
2817 %}
2819 // Enc_class needed as consttanttablebase is not supported by postalloc
2820 // expand.
2821 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2822 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2824 MachNode *m2;
2825 if (large_constant_pool) {
2826 m2 = new (C) loadConDCompNode();
2827 } else {
2828 m2 = new (C) loadConDNode();
2829 }
2830 // inputs for new nodes
2831 m2->add_req(NULL, n_toc);
2833 // operands for new nodes
2834 m2->_opnds[0] = op_dst;
2835 m2->_opnds[1] = op_src;
2836 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2838 // register allocation for new nodes
2839 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2840 nodes->push(m2);
2841 %}
2843 enc_class enc_stw(iRegIsrc src, memory mem) %{
2844 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2845 MacroAssembler _masm(&cbuf);
2846 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2847 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2848 %}
2850 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2851 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2852 MacroAssembler _masm(&cbuf);
2853 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2854 // Operand 'ds' requires 4-alignment.
2855 assert((Idisp & 0x3) == 0, "unaligned offset");
2856 __ std($src$$Register, Idisp, $mem$$base$$Register);
2857 %}
2859 enc_class enc_stfs(RegF src, memory mem) %{
2860 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2861 MacroAssembler _masm(&cbuf);
2862 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2863 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2864 %}
2866 enc_class enc_stfd(RegF src, memory mem) %{
2867 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2868 MacroAssembler _masm(&cbuf);
2869 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2870 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2871 %}
2873 // Use release_store for card-marking to ensure that previous
2874 // oop-stores are visible before the card-mark change.
2875 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2876 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2877 // FIXME: Implement this as a cmove and use a fixed condition code
2878 // register which is written on every transition to compiled code,
2879 // e.g. in call-stub and when returning from runtime stubs.
2880 //
2881 // Proposed code sequence for the cmove implementation:
2882 //
2883 // Label skip_release;
2884 // __ beq(CCRfixed, skip_release);
2885 // __ release();
2886 // __ bind(skip_release);
2887 // __ stb(card mark);
2889 MacroAssembler _masm(&cbuf);
2890 Label skip_storestore;
2892 #if 0 // TODO: PPC port
2893 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2894 // StoreStore barrier conditionally.
2895 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2896 __ cmpwi(CCR0, R0, 0);
2897 __ beq_predict_taken(CCR0, skip_storestore);
2898 #endif
2899 __ li(R0, 0);
2900 __ membar(Assembler::StoreStore);
2901 #if 0 // TODO: PPC port
2902 __ bind(skip_storestore);
2903 #endif
2905 // Do the store.
2906 if ($mem$$index == 0) {
2907 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2908 } else {
2909 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2910 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2911 }
2912 %}
2914 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2916 if (VM_Version::has_isel()) {
2917 // use isel instruction with Power 7
2918 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2919 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2920 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2921 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2923 n_compare->add_req(n_region, n_src);
2924 n_compare->_opnds[0] = op_crx;
2925 n_compare->_opnds[1] = op_src;
2926 n_compare->_opnds[2] = new (C) immL16Oper(0);
2928 n_sub_base->add_req(n_region, n_src);
2929 n_sub_base->_opnds[0] = op_dst;
2930 n_sub_base->_opnds[1] = op_src;
2931 n_sub_base->_bottom_type = _bottom_type;
2933 n_shift->add_req(n_region, n_sub_base);
2934 n_shift->_opnds[0] = op_dst;
2935 n_shift->_opnds[1] = op_dst;
2936 n_shift->_bottom_type = _bottom_type;
2938 n_cond_set->add_req(n_region, n_compare, n_shift);
2939 n_cond_set->_opnds[0] = op_dst;
2940 n_cond_set->_opnds[1] = op_crx;
2941 n_cond_set->_opnds[2] = op_dst;
2942 n_cond_set->_bottom_type = _bottom_type;
2944 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2945 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2946 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2947 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2949 nodes->push(n_compare);
2950 nodes->push(n_sub_base);
2951 nodes->push(n_shift);
2952 nodes->push(n_cond_set);
2954 } else {
2955 // before Power 7
2956 moveRegNode *n_move = new (C) moveRegNode();
2957 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2958 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2959 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2961 n_move->add_req(n_region, n_src);
2962 n_move->_opnds[0] = op_dst;
2963 n_move->_opnds[1] = op_src;
2964 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2966 n_compare->add_req(n_region, n_src);
2967 n_compare->add_prec(n_move);
2969 n_compare->_opnds[0] = op_crx;
2970 n_compare->_opnds[1] = op_src;
2971 n_compare->_opnds[2] = new (C) immL16Oper(0);
2973 n_sub_base->add_req(n_region, n_compare, n_src);
2974 n_sub_base->_opnds[0] = op_dst;
2975 n_sub_base->_opnds[1] = op_crx;
2976 n_sub_base->_opnds[2] = op_src;
2977 n_sub_base->_bottom_type = _bottom_type;
2979 n_shift->add_req(n_region, n_sub_base);
2980 n_shift->_opnds[0] = op_dst;
2981 n_shift->_opnds[1] = op_dst;
2982 n_shift->_bottom_type = _bottom_type;
2984 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2985 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2986 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2987 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2989 nodes->push(n_move);
2990 nodes->push(n_compare);
2991 nodes->push(n_sub_base);
2992 nodes->push(n_shift);
2993 }
2995 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2996 %}
2998 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3000 encodeP_subNode *n1 = new (C) encodeP_subNode();
3001 n1->add_req(n_region, n_src);
3002 n1->_opnds[0] = op_dst;
3003 n1->_opnds[1] = op_src;
3004 n1->_bottom_type = _bottom_type;
3006 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
3007 n2->add_req(n_region, n1);
3008 n2->_opnds[0] = op_dst;
3009 n2->_opnds[1] = op_dst;
3010 n2->_bottom_type = _bottom_type;
3011 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3012 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3014 nodes->push(n1);
3015 nodes->push(n2);
3016 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3017 %}
3019 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3020 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
3021 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
3023 n_compare->add_req(n_region, n_src);
3024 n_compare->_opnds[0] = op_crx;
3025 n_compare->_opnds[1] = op_src;
3026 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
3028 n_shift->add_req(n_region, n_src);
3029 n_shift->_opnds[0] = op_dst;
3030 n_shift->_opnds[1] = op_src;
3031 n_shift->_bottom_type = _bottom_type;
3033 if (VM_Version::has_isel()) {
3034 // use isel instruction with Power 7
3036 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
3037 n_add_base->add_req(n_region, n_shift);
3038 n_add_base->_opnds[0] = op_dst;
3039 n_add_base->_opnds[1] = op_dst;
3040 n_add_base->_bottom_type = _bottom_type;
3042 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3043 n_cond_set->add_req(n_region, n_compare, n_add_base);
3044 n_cond_set->_opnds[0] = op_dst;
3045 n_cond_set->_opnds[1] = op_crx;
3046 n_cond_set->_opnds[2] = op_dst;
3047 n_cond_set->_bottom_type = _bottom_type;
3049 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3050 ra_->set_oop(n_cond_set, true);
3052 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3053 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3054 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3055 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3057 nodes->push(n_compare);
3058 nodes->push(n_shift);
3059 nodes->push(n_add_base);
3060 nodes->push(n_cond_set);
3062 } else {
3063 // before Power 7
3064 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3066 n_add_base->add_req(n_region, n_compare, n_shift);
3067 n_add_base->_opnds[0] = op_dst;
3068 n_add_base->_opnds[1] = op_crx;
3069 n_add_base->_opnds[2] = op_dst;
3070 n_add_base->_bottom_type = _bottom_type;
3072 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3073 ra_->set_oop(n_add_base, true);
3075 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3076 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3077 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3079 nodes->push(n_compare);
3080 nodes->push(n_shift);
3081 nodes->push(n_add_base);
3082 }
3083 %}
3085 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3086 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3087 n1->add_req(n_region, n_src);
3088 n1->_opnds[0] = op_dst;
3089 n1->_opnds[1] = op_src;
3090 n1->_bottom_type = _bottom_type;
3092 decodeN_addNode *n2 = new (C) decodeN_addNode();
3093 n2->add_req(n_region, n1);
3094 n2->_opnds[0] = op_dst;
3095 n2->_opnds[1] = op_dst;
3096 n2->_bottom_type = _bottom_type;
3097 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3098 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3100 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3101 ra_->set_oop(n2, true);
3103 nodes->push(n1);
3104 nodes->push(n2);
3105 %}
3107 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3108 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3110 MacroAssembler _masm(&cbuf);
3111 int cc = $cmp$$cmpcode;
3112 int flags_reg = $crx$$reg;
3113 Label done;
3114 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3115 // Branch if not (cmp crx).
3116 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3117 __ mr($dst$$Register, $src$$Register);
3118 // TODO PPC port __ endgroup_if_needed(_size == 12);
3119 __ bind(done);
3120 %}
3122 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3123 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3125 MacroAssembler _masm(&cbuf);
3126 Label done;
3127 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3128 // Branch if not (cmp crx).
3129 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3130 __ li($dst$$Register, $src$$constant);
3131 // TODO PPC port __ endgroup_if_needed(_size == 12);
3132 __ bind(done);
3133 %}
3135 // New atomics.
3136 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3137 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3139 MacroAssembler _masm(&cbuf);
3140 Register Rtmp = R0;
3141 Register Rres = $res$$Register;
3142 Register Rsrc = $src$$Register;
3143 Register Rptr = $mem_ptr$$Register;
3144 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3145 Register Rold = RegCollision ? Rtmp : Rres;
3147 Label Lretry;
3148 __ bind(Lretry);
3149 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3150 __ add(Rtmp, Rsrc, Rold);
3151 __ stwcx_(Rtmp, Rptr);
3152 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3153 __ bne_predict_not_taken(CCR0, Lretry);
3154 } else {
3155 __ bne( CCR0, Lretry);
3156 }
3157 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3158 __ fence();
3159 %}
3161 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3162 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3164 MacroAssembler _masm(&cbuf);
3165 Register Rtmp = R0;
3166 Register Rres = $res$$Register;
3167 Register Rsrc = $src$$Register;
3168 Register Rptr = $mem_ptr$$Register;
3169 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3170 Register Rold = RegCollision ? Rtmp : Rres;
3172 Label Lretry;
3173 __ bind(Lretry);
3174 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3175 __ add(Rtmp, Rsrc, Rold);
3176 __ stdcx_(Rtmp, Rptr);
3177 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3178 __ bne_predict_not_taken(CCR0, Lretry);
3179 } else {
3180 __ bne( CCR0, Lretry);
3181 }
3182 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3183 __ fence();
3184 %}
3186 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3187 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3189 MacroAssembler _masm(&cbuf);
3190 Register Rtmp = R0;
3191 Register Rres = $res$$Register;
3192 Register Rsrc = $src$$Register;
3193 Register Rptr = $mem_ptr$$Register;
3194 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3195 Register Rold = RegCollision ? Rtmp : Rres;
3197 Label Lretry;
3198 __ bind(Lretry);
3199 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3200 __ stwcx_(Rsrc, Rptr);
3201 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3202 __ bne_predict_not_taken(CCR0, Lretry);
3203 } else {
3204 __ bne( CCR0, Lretry);
3205 }
3206 if (RegCollision) __ mr(Rres, Rtmp);
3207 __ fence();
3208 %}
3210 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3211 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3213 MacroAssembler _masm(&cbuf);
3214 Register Rtmp = R0;
3215 Register Rres = $res$$Register;
3216 Register Rsrc = $src$$Register;
3217 Register Rptr = $mem_ptr$$Register;
3218 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3219 Register Rold = RegCollision ? Rtmp : Rres;
3221 Label Lretry;
3222 __ bind(Lretry);
3223 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3224 __ stdcx_(Rsrc, Rptr);
3225 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3226 __ bne_predict_not_taken(CCR0, Lretry);
3227 } else {
3228 __ bne( CCR0, Lretry);
3229 }
3230 if (RegCollision) __ mr(Rres, Rtmp);
3231 __ fence();
3232 %}
3234 // This enc_class is needed so that scheduler gets proper
3235 // input mapping for latency computation.
3236 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3237 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3238 MacroAssembler _masm(&cbuf);
3239 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3240 %}
3242 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3243 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3245 MacroAssembler _masm(&cbuf);
3247 Label done;
3248 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3249 __ li($dst$$Register, $zero$$constant);
3250 __ beq($crx$$CondRegister, done);
3251 __ li($dst$$Register, $notzero$$constant);
3252 __ bind(done);
3253 %}
3255 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3256 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3258 MacroAssembler _masm(&cbuf);
3260 Label done;
3261 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3262 __ li($dst$$Register, $zero$$constant);
3263 __ beq($crx$$CondRegister, done);
3264 __ li($dst$$Register, $notzero$$constant);
3265 __ bind(done);
3266 %}
3268 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3269 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3271 MacroAssembler _masm(&cbuf);
3272 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3273 Label done;
3274 __ bso($crx$$CondRegister, done);
3275 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3276 // TODO PPC port __ endgroup_if_needed(_size == 12);
3277 __ bind(done);
3278 %}
3280 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3281 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3283 MacroAssembler _masm(&cbuf);
3284 Label d; // dummy
3285 __ bind(d);
3286 Label* p = ($lbl$$label);
3287 // `p' is `NULL' when this encoding class is used only to
3288 // determine the size of the encoded instruction.
3289 Label& l = (NULL == p)? d : *(p);
3290 int cc = $cmp$$cmpcode;
3291 int flags_reg = $crx$$reg;
3292 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3293 int bhint = Assembler::bhintNoHint;
3295 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3296 if (_prob <= PROB_NEVER) {
3297 bhint = Assembler::bhintIsNotTaken;
3298 } else if (_prob >= PROB_ALWAYS) {
3299 bhint = Assembler::bhintIsTaken;
3300 }
3301 }
3303 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3304 cc_to_biint(cc, flags_reg),
3305 l);
3306 %}
3308 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3309 // The scheduler doesn't know about branch shortening, so we set the opcode
3310 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3311 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3313 MacroAssembler _masm(&cbuf);
3314 Label d; // dummy
3315 __ bind(d);
3316 Label* p = ($lbl$$label);
3317 // `p' is `NULL' when this encoding class is used only to
3318 // determine the size of the encoded instruction.
3319 Label& l = (NULL == p)? d : *(p);
3320 int cc = $cmp$$cmpcode;
3321 int flags_reg = $crx$$reg;
3322 int bhint = Assembler::bhintNoHint;
3324 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3325 if (_prob <= PROB_NEVER) {
3326 bhint = Assembler::bhintIsNotTaken;
3327 } else if (_prob >= PROB_ALWAYS) {
3328 bhint = Assembler::bhintIsTaken;
3329 }
3330 }
3332 // Tell the conditional far branch to optimize itself when being relocated.
3333 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3334 cc_to_biint(cc, flags_reg),
3335 l,
3336 MacroAssembler::bc_far_optimize_on_relocate);
3337 %}
3339 // Branch used with Power6 scheduling (can be shortened without changing the node).
3340 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3341 // The scheduler doesn't know about branch shortening, so we set the opcode
3342 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3343 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3345 MacroAssembler _masm(&cbuf);
3346 Label d; // dummy
3347 __ bind(d);
3348 Label* p = ($lbl$$label);
3349 // `p' is `NULL' when this encoding class is used only to
3350 // determine the size of the encoded instruction.
3351 Label& l = (NULL == p)? d : *(p);
3352 int cc = $cmp$$cmpcode;
3353 int flags_reg = $crx$$reg;
3354 int bhint = Assembler::bhintNoHint;
3356 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3357 if (_prob <= PROB_NEVER) {
3358 bhint = Assembler::bhintIsNotTaken;
3359 } else if (_prob >= PROB_ALWAYS) {
3360 bhint = Assembler::bhintIsTaken;
3361 }
3362 }
3364 #if 0 // TODO: PPC port
3365 if (_size == 8) {
3366 // Tell the conditional far branch to optimize itself when being relocated.
3367 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3368 cc_to_biint(cc, flags_reg),
3369 l,
3370 MacroAssembler::bc_far_optimize_on_relocate);
3371 } else {
3372 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3373 cc_to_biint(cc, flags_reg),
3374 l);
3375 }
3376 #endif
3377 Unimplemented();
3378 %}
3380 // Postalloc expand emitter for loading a replicatef float constant from
3381 // the method's TOC.
3382 // Enc_class needed as consttanttablebase is not supported by postalloc
3383 // expand.
3384 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3385 // Create new nodes.
3387 // Make an operand with the bit pattern to load as float.
3388 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3390 loadConLNodesTuple loadConLNodes =
3391 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3392 ra_->get_reg_second(this), ra_->get_reg_first(this));
3394 // Push new nodes.
3395 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3396 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3398 assert(nodes->length() >= 1, "must have created at least 1 node");
3399 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3400 %}
3402 // This enc_class is needed so that scheduler gets proper
3403 // input mapping for latency computation.
3404 enc_class enc_poll(immI dst, iRegLdst poll) %{
3405 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3406 // Fake operand dst needed for PPC scheduler.
3407 assert($dst$$constant == 0x0, "dst must be 0x0");
3409 MacroAssembler _masm(&cbuf);
3410 // Mark the code position where the load from the safepoint
3411 // polling page was emitted as relocInfo::poll_type.
3412 __ relocate(relocInfo::poll_type);
3413 __ load_from_polling_page($poll$$Register);
3414 %}
3416 // A Java static call or a runtime call.
3417 //
3418 // Branch-and-link relative to a trampoline.
3419 // The trampoline loads the target address and does a long branch to there.
3420 // In case we call java, the trampoline branches to a interpreter_stub
3421 // which loads the inline cache and the real call target from the constant pool.
3422 //
3423 // This basically looks like this:
3424 //
3425 // >>>> consts -+ -+
3426 // | |- offset1
3427 // [call target1] | <-+
3428 // [IC cache] |- offset2
3429 // [call target2] <--+
3430 //
3431 // <<<< consts
3432 // >>>> insts
3433 //
3434 // bl offset16 -+ -+ ??? // How many bits available?
3435 // | |
3436 // <<<< insts | |
3437 // >>>> stubs | |
3438 // | |- trampoline_stub_Reloc
3439 // trampoline stub: | <-+
3440 // r2 = toc |
3441 // r2 = [r2 + offset1] | // Load call target1 from const section
3442 // mtctr r2 |
3443 // bctr |- static_stub_Reloc
3444 // comp_to_interp_stub: <---+
3445 // r1 = toc
3446 // ICreg = [r1 + IC_offset] // Load IC from const section
3447 // r1 = [r1 + offset2] // Load call target2 from const section
3448 // mtctr r1
3449 // bctr
3450 //
3451 // <<<< stubs
3452 //
3453 // The call instruction in the code either
3454 // - Branches directly to a compiled method if the offset is encodable in instruction.
3455 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3456 // - Branches to the compiled_to_interp stub if the target is interpreted.
3457 //
3458 // Further there are three relocations from the loads to the constants in
3459 // the constant section.
3460 //
3461 // Usage of r1 and r2 in the stubs allows to distinguish them.
3462 enc_class enc_java_static_call(method meth) %{
3463 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3465 MacroAssembler _masm(&cbuf);
3466 address entry_point = (address)$meth$$method;
3468 if (!_method) {
3469 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3470 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3471 } else {
3472 // Remember the offset not the address.
3473 const int start_offset = __ offset();
3474 // The trampoline stub.
3475 if (!Compile::current()->in_scratch_emit_size()) {
3476 // No entry point given, use the current pc.
3477 // Make sure branch fits into
3478 if (entry_point == 0) entry_point = __ pc();
3480 // Put the entry point as a constant into the constant pool.
3481 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3482 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3484 // Emit the trampoline stub which will be related to the branch-and-link below.
3485 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3486 __ relocate(_optimized_virtual ?
3487 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3488 }
3490 // The real call.
3491 // Note: At this point we do not have the address of the trampoline
3492 // stub, and the entry point might be too far away for bl, so __ pc()
3493 // serves as dummy and the bl will be patched later.
3494 cbuf.set_insts_mark();
3495 __ bl(__ pc()); // Emits a relocation.
3497 // The stub for call to interpreter.
3498 CompiledStaticCall::emit_to_interp_stub(cbuf);
3499 }
3500 %}
3502 // Emit a method handle call.
3503 //
3504 // Method handle calls from compiled to compiled are going thru a
3505 // c2i -> i2c adapter, extending the frame for their arguments. The
3506 // caller however, returns directly to the compiled callee, that has
3507 // to cope with the extended frame. We restore the original frame by
3508 // loading the callers sp and adding the calculated framesize.
3509 enc_class enc_java_handle_call(method meth) %{
3510 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3512 MacroAssembler _masm(&cbuf);
3513 address entry_point = (address)$meth$$method;
3515 // Remember the offset not the address.
3516 const int start_offset = __ offset();
3517 // The trampoline stub.
3518 if (!ra_->C->in_scratch_emit_size()) {
3519 // No entry point given, use the current pc.
3520 // Make sure branch fits into
3521 if (entry_point == 0) entry_point = __ pc();
3523 // Put the entry point as a constant into the constant pool.
3524 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3525 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3527 // Emit the trampoline stub which will be related to the branch-and-link below.
3528 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3529 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3530 __ relocate(relocInfo::opt_virtual_call_type);
3531 }
3533 // The real call.
3534 // Note: At this point we do not have the address of the trampoline
3535 // stub, and the entry point might be too far away for bl, so __ pc()
3536 // serves as dummy and the bl will be patched later.
3537 cbuf.set_insts_mark();
3538 __ bl(__ pc()); // Emits a relocation.
3540 assert(_method, "execute next statement conditionally");
3541 // The stub for call to interpreter.
3542 CompiledStaticCall::emit_to_interp_stub(cbuf);
3544 // Restore original sp.
3545 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3546 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3547 unsigned int bytes = (unsigned int)framesize;
3548 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3549 if (Assembler::is_simm(-offset, 16)) {
3550 __ addi(R1_SP, R11_scratch1, -offset);
3551 } else {
3552 __ load_const_optimized(R12_scratch2, -offset);
3553 __ add(R1_SP, R11_scratch1, R12_scratch2);
3554 }
3555 #ifdef ASSERT
3556 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3557 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3558 __ asm_assert_eq("backlink changed", 0x8000);
3559 #endif
3560 // If fails should store backlink before unextending.
3562 if (ra_->C->env()->failing()) {
3563 return;
3564 }
3565 %}
3567 // Second node of expanded dynamic call - the call.
3568 enc_class enc_java_dynamic_call_sched(method meth) %{
3569 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3571 MacroAssembler _masm(&cbuf);
3573 if (!ra_->C->in_scratch_emit_size()) {
3574 // Create a call trampoline stub for the given method.
3575 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3576 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3577 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3578 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3580 if (ra_->C->env()->failing())
3581 return;
3583 // Build relocation at call site with ic position as data.
3584 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3585 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3586 "must have one, but can't have both");
3587 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3588 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3589 "must contain instruction offset");
3590 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3591 ? _load_ic_hi_node->_cbuf_insts_offset
3592 : _load_ic_node->_cbuf_insts_offset;
3593 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3594 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3595 "should be load from TOC");
3597 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3598 }
3600 // At this point I do not have the address of the trampoline stub,
3601 // and the entry point might be too far away for bl. Pc() serves
3602 // as dummy and bl will be patched later.
3603 __ bl((address) __ pc());
3604 %}
3606 // postalloc expand emitter for virtual calls.
3607 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3609 // Create the nodes for loading the IC from the TOC.
3610 loadConLNodesTuple loadConLNodes_IC =
3611 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3612 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3614 // Create the call node.
3615 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3616 call->_method_handle_invoke = _method_handle_invoke;
3617 call->_vtable_index = _vtable_index;
3618 call->_method = _method;
3619 call->_bci = _bci;
3620 call->_optimized_virtual = _optimized_virtual;
3621 call->_tf = _tf;
3622 call->_entry_point = _entry_point;
3623 call->_cnt = _cnt;
3624 call->_argsize = _argsize;
3625 call->_oop_map = _oop_map;
3626 call->_jvms = _jvms;
3627 call->_jvmadj = _jvmadj;
3628 call->_in_rms = _in_rms;
3629 call->_nesting = _nesting;
3631 // New call needs all inputs of old call.
3632 // Req...
3633 for (uint i = 0; i < req(); ++i) {
3634 // The expanded node does not need toc any more.
3635 // Add the inline cache constant here instead. This expresses the
3636 // register of the inline cache must be live at the call.
3637 // Else we would have to adapt JVMState by -1.
3638 if (i == mach_constant_base_node_input()) {
3639 call->add_req(loadConLNodes_IC._last);
3640 } else {
3641 call->add_req(in(i));
3642 }
3643 }
3644 // ...as well as prec
3645 for (uint i = req(); i < len(); ++i) {
3646 call->add_prec(in(i));
3647 }
3649 // Remember nodes loading the inline cache into r19.
3650 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3651 call->_load_ic_node = loadConLNodes_IC._small;
3653 // Operands for new nodes.
3654 call->_opnds[0] = _opnds[0];
3655 call->_opnds[1] = _opnds[1];
3657 // Only the inline cache is associated with a register.
3658 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3660 // Push new nodes.
3661 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3662 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3663 nodes->push(call);
3664 %}
3666 // Compound version of call dynamic
3667 // Toc is only passed so that it can be used in ins_encode statement.
3668 // In the code we have to use $constanttablebase.
3669 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3670 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3671 MacroAssembler _masm(&cbuf);
3672 int start_offset = __ offset();
3674 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3675 #if 0
3676 int vtable_index = this->_vtable_index;
3677 if (_vtable_index < 0) {
3678 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3679 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3680 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3682 // Virtual call relocation will point to ic load.
3683 address virtual_call_meta_addr = __ pc();
3684 // Load a clear inline cache.
3685 AddressLiteral empty_ic((address) Universe::non_oop_word());
3686 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3687 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3688 // to determine who we intended to call.
3689 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3690 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3691 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3692 "Fix constant in ret_addr_offset()");
3693 } else {
3694 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3695 // Go thru the vtable. Get receiver klass. Receiver already
3696 // checked for non-null. If we'll go thru a C2I adapter, the
3697 // interpreter expects method in R19_method.
3699 __ load_klass(R11_scratch1, R3);
3701 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3702 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3703 __ li(R19_method, v_off);
3704 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3705 // NOTE: for vtable dispatches, the vtable entry will never be
3706 // null. However it may very well end up in handle_wrong_method
3707 // if the method is abstract for the particular class.
3708 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3709 // Call target. Either compiled code or C2I adapter.
3710 __ mtctr(R11_scratch1);
3711 __ bctrl();
3712 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3713 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3714 }
3715 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3716 "Fix constant in ret_addr_offset()");
3717 }
3718 #endif
3719 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3720 %}
3722 // a runtime call
3723 enc_class enc_java_to_runtime_call (method meth) %{
3724 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3726 MacroAssembler _masm(&cbuf);
3727 const address start_pc = __ pc();
3729 #if defined(ABI_ELFv2)
3730 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3731 __ call_c(entry, relocInfo::runtime_call_type);
3732 #else
3733 // The function we're going to call.
3734 FunctionDescriptor fdtemp;
3735 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3737 Register Rtoc = R12_scratch2;
3738 // Calculate the method's TOC.
3739 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3740 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3741 // pool entries; call_c_using_toc will optimize the call.
3742 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3743 #endif
3745 // Check the ret_addr_offset.
3746 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3747 "Fix constant in ret_addr_offset()");
3748 %}
3750 // Move to ctr for leaf call.
3751 // This enc_class is needed so that scheduler gets proper
3752 // input mapping for latency computation.
3753 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3754 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3755 MacroAssembler _masm(&cbuf);
3756 __ mtctr($src$$Register);
3757 %}
3759 // Postalloc expand emitter for runtime leaf calls.
3760 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3761 loadConLNodesTuple loadConLNodes_Entry;
3762 #if defined(ABI_ELFv2)
3763 jlong entry_address = (jlong) this->entry_point();
3764 assert(entry_address, "need address here");
3765 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3766 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3767 #else
3768 // Get the struct that describes the function we are about to call.
3769 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3770 assert(fd, "need fd here");
3771 jlong entry_address = (jlong) fd->entry();
3772 // new nodes
3773 loadConLNodesTuple loadConLNodes_Env;
3774 loadConLNodesTuple loadConLNodes_Toc;
3776 // Create nodes and operands for loading the entry point.
3777 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3778 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3781 // Create nodes and operands for loading the env pointer.
3782 if (fd->env() != NULL) {
3783 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3784 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3785 } else {
3786 loadConLNodes_Env._large_hi = NULL;
3787 loadConLNodes_Env._large_lo = NULL;
3788 loadConLNodes_Env._small = NULL;
3789 loadConLNodes_Env._last = new (C) loadConL16Node();
3790 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3791 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3792 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3793 }
3795 // Create nodes and operands for loading the Toc point.
3796 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3797 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3798 #endif // ABI_ELFv2
3799 // mtctr node
3800 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode();
3802 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3803 mtctr->add_req(0, loadConLNodes_Entry._last);
3805 mtctr->_opnds[0] = new (C) iRegLdstOper();
3806 mtctr->_opnds[1] = new (C) iRegLdstOper();
3808 // call node
3809 MachCallLeafNode *call = new (C) CallLeafDirectNode();
3811 call->_opnds[0] = _opnds[0];
3812 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later.
3814 // Make the new call node look like the old one.
3815 call->_name = _name;
3816 call->_tf = _tf;
3817 call->_entry_point = _entry_point;
3818 call->_cnt = _cnt;
3819 call->_argsize = _argsize;
3820 call->_oop_map = _oop_map;
3821 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3822 call->_jvms = NULL;
3823 call->_jvmadj = _jvmadj;
3824 call->_in_rms = _in_rms;
3825 call->_nesting = _nesting;
3828 // New call needs all inputs of old call.
3829 // Req...
3830 for (uint i = 0; i < req(); ++i) {
3831 if (i != mach_constant_base_node_input()) {
3832 call->add_req(in(i));
3833 }
3834 }
3836 // These must be reqired edges, as the registers are live up to
3837 // the call. Else the constants are handled as kills.
3838 call->add_req(mtctr);
3839 #if !defined(ABI_ELFv2)
3840 call->add_req(loadConLNodes_Env._last);
3841 call->add_req(loadConLNodes_Toc._last);
3842 #endif
3844 // ...as well as prec
3845 for (uint i = req(); i < len(); ++i) {
3846 call->add_prec(in(i));
3847 }
3849 // registers
3850 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3852 // Insert the new nodes.
3853 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3854 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3855 #if !defined(ABI_ELFv2)
3856 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3857 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3858 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3859 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3860 #endif
3861 nodes->push(mtctr);
3862 nodes->push(call);
3863 %}
3864 %}
3866 //----------FRAME--------------------------------------------------------------
3867 // Definition of frame structure and management information.
3869 frame %{
3870 // What direction does stack grow in (assumed to be same for native & Java).
3871 stack_direction(TOWARDS_LOW);
3873 // These two registers define part of the calling convention between
3874 // compiled code and the interpreter.
3876 // Inline Cache Register or method for I2C.
3877 inline_cache_reg(R19); // R19_method
3879 // Method Oop Register when calling interpreter.
3880 interpreter_method_oop_reg(R19); // R19_method
3882 // Optional: name the operand used by cisc-spilling to access
3883 // [stack_pointer + offset].
3884 cisc_spilling_operand_name(indOffset);
3886 // Number of stack slots consumed by a Monitor enter.
3887 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3889 // Compiled code's Frame Pointer.
3890 frame_pointer(R1); // R1_SP
3892 // Interpreter stores its frame pointer in a register which is
3893 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3894 // interpreted java to compiled java.
3895 //
3896 // R14_state holds pointer to caller's cInterpreter.
3897 interpreter_frame_pointer(R14); // R14_state
3899 stack_alignment(frame::alignment_in_bytes);
3901 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3903 // Number of outgoing stack slots killed above the
3904 // out_preserve_stack_slots for calls to C. Supports the var-args
3905 // backing area for register parms.
3906 //
3907 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3909 // The after-PROLOG location of the return address. Location of
3910 // return address specifies a type (REG or STACK) and a number
3911 // representing the register number (i.e. - use a register name) or
3912 // stack slot.
3913 //
3914 // A: Link register is stored in stack slot ...
3915 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3916 // J: Therefore, we make sure that the link register is also in R11_scratch1
3917 // at the end of the prolog.
3918 // B: We use R20, now.
3919 //return_addr(REG R20);
3921 // G: After reading the comments made by all the luminaries on their
3922 // failure to tell the compiler where the return address really is,
3923 // I hardly dare to try myself. However, I'm convinced it's in slot
3924 // 4 what apparently works and saves us some spills.
3925 return_addr(STACK 4);
3927 // This is the body of the function
3928 //
3929 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3930 // uint length, // length of array
3931 // bool is_outgoing)
3932 //
3933 // The `sig' array is to be updated. sig[j] represents the location
3934 // of the j-th argument, either a register or a stack slot.
3936 // Comment taken from i486.ad:
3937 // Body of function which returns an integer array locating
3938 // arguments either in registers or in stack slots. Passed an array
3939 // of ideal registers called "sig" and a "length" count. Stack-slot
3940 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3941 // arguments for a CALLEE. Incoming stack arguments are
3942 // automatically biased by the preserve_stack_slots field above.
3943 calling_convention %{
3944 // No difference between ingoing/outgoing. Just pass false.
3945 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3946 %}
3948 // Comment taken from i486.ad:
3949 // Body of function which returns an integer array locating
3950 // arguments either in registers or in stack slots. Passed an array
3951 // of ideal registers called "sig" and a "length" count. Stack-slot
3952 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3953 // arguments for a CALLEE. Incoming stack arguments are
3954 // automatically biased by the preserve_stack_slots field above.
3955 c_calling_convention %{
3956 // This is obviously always outgoing.
3957 // C argument in register AND stack slot.
3958 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3959 %}
3961 // Location of native (C/C++) and interpreter return values. This
3962 // is specified to be the same as Java. In the 32-bit VM, long
3963 // values are actually returned from native calls in O0:O1 and
3964 // returned to the interpreter in I0:I1. The copying to and from
3965 // the register pairs is done by the appropriate call and epilog
3966 // opcodes. This simplifies the register allocator.
3967 c_return_value %{
3968 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3969 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3970 "only return normal values");
3971 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3972 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3973 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3974 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3975 %}
3977 // Location of compiled Java return values. Same as C
3978 return_value %{
3979 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3980 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3981 "only return normal values");
3982 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3983 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3984 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3985 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3986 %}
3987 %}
3990 //----------ATTRIBUTES---------------------------------------------------------
3992 //----------Operand Attributes-------------------------------------------------
3993 op_attrib op_cost(1); // Required cost attribute.
3995 //----------Instruction Attributes---------------------------------------------
3997 // Cost attribute. required.
3998 ins_attrib ins_cost(DEFAULT_COST);
4000 // Is this instruction a non-matching short branch variant of some
4001 // long branch? Not required.
4002 ins_attrib ins_short_branch(0);
4004 ins_attrib ins_is_TrapBasedCheckNode(true);
4006 // Number of constants.
4007 // This instruction uses the given number of constants
4008 // (optional attribute).
4009 // This is needed to determine in time whether the constant pool will
4010 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4011 // is determined. It's also used to compute the constant pool size
4012 // in Output().
4013 ins_attrib ins_num_consts(0);
4015 // Required alignment attribute (must be a power of 2) specifies the
4016 // alignment that some part of the instruction (not necessarily the
4017 // start) requires. If > 1, a compute_padding() function must be
4018 // provided for the instruction.
4019 ins_attrib ins_alignment(1);
4021 // Enforce/prohibit rematerializations.
4022 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4023 // then rematerialization of that instruction is prohibited and the
4024 // instruction's value will be spilled if necessary.
4025 // Causes that MachNode::rematerialize() returns false.
4026 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4027 // then rematerialization should be enforced and a copy of the instruction
4028 // should be inserted if possible; rematerialization is not guaranteed.
4029 // Note: this may result in rematerializations in front of every use.
4030 // Causes that MachNode::rematerialize() can return true.
4031 // (optional attribute)
4032 ins_attrib ins_cannot_rematerialize(false);
4033 ins_attrib ins_should_rematerialize(false);
4035 // Instruction has variable size depending on alignment.
4036 ins_attrib ins_variable_size_depending_on_alignment(false);
4038 // Instruction is a nop.
4039 ins_attrib ins_is_nop(false);
4041 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4042 ins_attrib ins_use_mach_if_fast_lock_node(false);
4044 // Field for the toc offset of a constant.
4045 //
4046 // This is needed if the toc offset is not encodable as an immediate in
4047 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4048 // added to the toc, and from this a load with immediate is performed.
4049 // With postalloc expand, we get two nodes that require the same offset
4050 // but which don't know about each other. The offset is only known
4051 // when the constant is added to the constant pool during emitting.
4052 // It is generated in the 'hi'-node adding the upper bits, and saved
4053 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4054 // the offset from there when it gets encoded.
4055 ins_attrib ins_field_const_toc_offset(0);
4056 ins_attrib ins_field_const_toc_offset_hi_node(0);
4058 // A field that can hold the instructions offset in the code buffer.
4059 // Set in the nodes emitter.
4060 ins_attrib ins_field_cbuf_insts_offset(-1);
4062 // Fields for referencing a call's load-IC-node.
4063 // If the toc offset can not be encoded as an immediate in a load, we
4064 // use two nodes.
4065 ins_attrib ins_field_load_ic_hi_node(0);
4066 ins_attrib ins_field_load_ic_node(0);
4068 //----------OPERANDS-----------------------------------------------------------
4069 // Operand definitions must precede instruction definitions for correct
4070 // parsing in the ADLC because operands constitute user defined types
4071 // which are used in instruction definitions.
4072 //
4073 // Formats are generated automatically for constants and base registers.
4075 //----------Simple Operands----------------------------------------------------
4076 // Immediate Operands
4078 // Integer Immediate: 32-bit
4079 operand immI() %{
4080 match(ConI);
4081 op_cost(40);
4082 format %{ %}
4083 interface(CONST_INTER);
4084 %}
4086 operand immI8() %{
4087 predicate(Assembler::is_simm(n->get_int(), 8));
4088 op_cost(0);
4089 match(ConI);
4090 format %{ %}
4091 interface(CONST_INTER);
4092 %}
4094 // Integer Immediate: 16-bit
4095 operand immI16() %{
4096 predicate(Assembler::is_simm(n->get_int(), 16));
4097 op_cost(0);
4098 match(ConI);
4099 format %{ %}
4100 interface(CONST_INTER);
4101 %}
4103 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4104 operand immIhi16() %{
4105 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4106 match(ConI);
4107 op_cost(0);
4108 format %{ %}
4109 interface(CONST_INTER);
4110 %}
4112 operand immInegpow2() %{
4113 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4114 match(ConI);
4115 op_cost(0);
4116 format %{ %}
4117 interface(CONST_INTER);
4118 %}
4120 operand immIpow2minus1() %{
4121 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4122 match(ConI);
4123 op_cost(0);
4124 format %{ %}
4125 interface(CONST_INTER);
4126 %}
4128 operand immIpowerOf2() %{
4129 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4130 match(ConI);
4131 op_cost(0);
4132 format %{ %}
4133 interface(CONST_INTER);
4134 %}
4136 // Unsigned Integer Immediate: the values 0-31
4137 operand uimmI5() %{
4138 predicate(Assembler::is_uimm(n->get_int(), 5));
4139 match(ConI);
4140 op_cost(0);
4141 format %{ %}
4142 interface(CONST_INTER);
4143 %}
4145 // Unsigned Integer Immediate: 6-bit
4146 operand uimmI6() %{
4147 predicate(Assembler::is_uimm(n->get_int(), 6));
4148 match(ConI);
4149 op_cost(0);
4150 format %{ %}
4151 interface(CONST_INTER);
4152 %}
4154 // Unsigned Integer Immediate: 6-bit int, greater than 32
4155 operand uimmI6_ge32() %{
4156 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4157 match(ConI);
4158 op_cost(0);
4159 format %{ %}
4160 interface(CONST_INTER);
4161 %}
4163 // Unsigned Integer Immediate: 15-bit
4164 operand uimmI15() %{
4165 predicate(Assembler::is_uimm(n->get_int(), 15));
4166 match(ConI);
4167 op_cost(0);
4168 format %{ %}
4169 interface(CONST_INTER);
4170 %}
4172 // Unsigned Integer Immediate: 16-bit
4173 operand uimmI16() %{
4174 predicate(Assembler::is_uimm(n->get_int(), 16));
4175 match(ConI);
4176 op_cost(0);
4177 format %{ %}
4178 interface(CONST_INTER);
4179 %}
4181 // constant 'int 0'.
4182 operand immI_0() %{
4183 predicate(n->get_int() == 0);
4184 match(ConI);
4185 op_cost(0);
4186 format %{ %}
4187 interface(CONST_INTER);
4188 %}
4190 // constant 'int 1'.
4191 operand immI_1() %{
4192 predicate(n->get_int() == 1);
4193 match(ConI);
4194 op_cost(0);
4195 format %{ %}
4196 interface(CONST_INTER);
4197 %}
4199 // constant 'int -1'.
4200 operand immI_minus1() %{
4201 predicate(n->get_int() == -1);
4202 match(ConI);
4203 op_cost(0);
4204 format %{ %}
4205 interface(CONST_INTER);
4206 %}
4208 // int value 16.
4209 operand immI_16() %{
4210 predicate(n->get_int() == 16);
4211 match(ConI);
4212 op_cost(0);
4213 format %{ %}
4214 interface(CONST_INTER);
4215 %}
4217 // int value 24.
4218 operand immI_24() %{
4219 predicate(n->get_int() == 24);
4220 match(ConI);
4221 op_cost(0);
4222 format %{ %}
4223 interface(CONST_INTER);
4224 %}
4226 // Compressed oops constants
4227 // Pointer Immediate
4228 operand immN() %{
4229 match(ConN);
4231 op_cost(10);
4232 format %{ %}
4233 interface(CONST_INTER);
4234 %}
4236 // NULL Pointer Immediate
4237 operand immN_0() %{
4238 predicate(n->get_narrowcon() == 0);
4239 match(ConN);
4241 op_cost(0);
4242 format %{ %}
4243 interface(CONST_INTER);
4244 %}
4246 // Compressed klass constants
4247 operand immNKlass() %{
4248 match(ConNKlass);
4250 op_cost(0);
4251 format %{ %}
4252 interface(CONST_INTER);
4253 %}
4255 // This operand can be used to avoid matching of an instruct
4256 // with chain rule.
4257 operand immNKlass_NM() %{
4258 match(ConNKlass);
4259 predicate(false);
4260 op_cost(0);
4261 format %{ %}
4262 interface(CONST_INTER);
4263 %}
4265 // Pointer Immediate: 64-bit
4266 operand immP() %{
4267 match(ConP);
4268 op_cost(0);
4269 format %{ %}
4270 interface(CONST_INTER);
4271 %}
4273 // Operand to avoid match of loadConP.
4274 // This operand can be used to avoid matching of an instruct
4275 // with chain rule.
4276 operand immP_NM() %{
4277 match(ConP);
4278 predicate(false);
4279 op_cost(0);
4280 format %{ %}
4281 interface(CONST_INTER);
4282 %}
4284 // costant 'pointer 0'.
4285 operand immP_0() %{
4286 predicate(n->get_ptr() == 0);
4287 match(ConP);
4288 op_cost(0);
4289 format %{ %}
4290 interface(CONST_INTER);
4291 %}
4293 // pointer 0x0 or 0x1
4294 operand immP_0or1() %{
4295 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4296 match(ConP);
4297 op_cost(0);
4298 format %{ %}
4299 interface(CONST_INTER);
4300 %}
4302 operand immL() %{
4303 match(ConL);
4304 op_cost(40);
4305 format %{ %}
4306 interface(CONST_INTER);
4307 %}
4309 // Long Immediate: 16-bit
4310 operand immL16() %{
4311 predicate(Assembler::is_simm(n->get_long(), 16));
4312 match(ConL);
4313 op_cost(0);
4314 format %{ %}
4315 interface(CONST_INTER);
4316 %}
4318 // Long Immediate: 16-bit, 4-aligned
4319 operand immL16Alg4() %{
4320 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4321 match(ConL);
4322 op_cost(0);
4323 format %{ %}
4324 interface(CONST_INTER);
4325 %}
4327 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4328 operand immL32hi16() %{
4329 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4330 match(ConL);
4331 op_cost(0);
4332 format %{ %}
4333 interface(CONST_INTER);
4334 %}
4336 // Long Immediate: 32-bit
4337 operand immL32() %{
4338 predicate(Assembler::is_simm(n->get_long(), 32));
4339 match(ConL);
4340 op_cost(0);
4341 format %{ %}
4342 interface(CONST_INTER);
4343 %}
4345 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4346 operand immLhighest16() %{
4347 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4348 match(ConL);
4349 op_cost(0);
4350 format %{ %}
4351 interface(CONST_INTER);
4352 %}
4354 operand immLnegpow2() %{
4355 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4356 match(ConL);
4357 op_cost(0);
4358 format %{ %}
4359 interface(CONST_INTER);
4360 %}
4362 operand immLpow2minus1() %{
4363 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4364 (n->get_long() != (jlong)0xffffffffffffffffL));
4365 match(ConL);
4366 op_cost(0);
4367 format %{ %}
4368 interface(CONST_INTER);
4369 %}
4371 // constant 'long 0'.
4372 operand immL_0() %{
4373 predicate(n->get_long() == 0L);
4374 match(ConL);
4375 op_cost(0);
4376 format %{ %}
4377 interface(CONST_INTER);
4378 %}
4380 // constat ' long -1'.
4381 operand immL_minus1() %{
4382 predicate(n->get_long() == -1L);
4383 match(ConL);
4384 op_cost(0);
4385 format %{ %}
4386 interface(CONST_INTER);
4387 %}
4389 // Long Immediate: low 32-bit mask
4390 operand immL_32bits() %{
4391 predicate(n->get_long() == 0xFFFFFFFFL);
4392 match(ConL);
4393 op_cost(0);
4394 format %{ %}
4395 interface(CONST_INTER);
4396 %}
4398 // Unsigned Long Immediate: 16-bit
4399 operand uimmL16() %{
4400 predicate(Assembler::is_uimm(n->get_long(), 16));
4401 match(ConL);
4402 op_cost(0);
4403 format %{ %}
4404 interface(CONST_INTER);
4405 %}
4407 // Float Immediate
4408 operand immF() %{
4409 match(ConF);
4410 op_cost(40);
4411 format %{ %}
4412 interface(CONST_INTER);
4413 %}
4415 // constant 'float +0.0'.
4416 operand immF_0() %{
4417 predicate((n->getf() == 0) &&
4418 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0));
4419 match(ConF);
4420 op_cost(0);
4421 format %{ %}
4422 interface(CONST_INTER);
4423 %}
4425 // Double Immediate
4426 operand immD() %{
4427 match(ConD);
4428 op_cost(40);
4429 format %{ %}
4430 interface(CONST_INTER);
4431 %}
4433 // Integer Register Operands
4434 // Integer Destination Register
4435 // See definition of reg_class bits32_reg_rw.
4436 operand iRegIdst() %{
4437 constraint(ALLOC_IN_RC(bits32_reg_rw));
4438 match(RegI);
4439 match(rscratch1RegI);
4440 match(rscratch2RegI);
4441 match(rarg1RegI);
4442 match(rarg2RegI);
4443 match(rarg3RegI);
4444 match(rarg4RegI);
4445 format %{ %}
4446 interface(REG_INTER);
4447 %}
4449 // Integer Source Register
4450 // See definition of reg_class bits32_reg_ro.
4451 operand iRegIsrc() %{
4452 constraint(ALLOC_IN_RC(bits32_reg_ro));
4453 match(RegI);
4454 match(rscratch1RegI);
4455 match(rscratch2RegI);
4456 match(rarg1RegI);
4457 match(rarg2RegI);
4458 match(rarg3RegI);
4459 match(rarg4RegI);
4460 format %{ %}
4461 interface(REG_INTER);
4462 %}
4464 operand rscratch1RegI() %{
4465 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4466 match(iRegIdst);
4467 format %{ %}
4468 interface(REG_INTER);
4469 %}
4471 operand rscratch2RegI() %{
4472 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4473 match(iRegIdst);
4474 format %{ %}
4475 interface(REG_INTER);
4476 %}
4478 operand rarg1RegI() %{
4479 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4480 match(iRegIdst);
4481 format %{ %}
4482 interface(REG_INTER);
4483 %}
4485 operand rarg2RegI() %{
4486 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4487 match(iRegIdst);
4488 format %{ %}
4489 interface(REG_INTER);
4490 %}
4492 operand rarg3RegI() %{
4493 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4494 match(iRegIdst);
4495 format %{ %}
4496 interface(REG_INTER);
4497 %}
4499 operand rarg4RegI() %{
4500 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4501 match(iRegIdst);
4502 format %{ %}
4503 interface(REG_INTER);
4504 %}
4506 operand rarg1RegL() %{
4507 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4508 match(iRegLdst);
4509 format %{ %}
4510 interface(REG_INTER);
4511 %}
4513 operand rarg2RegL() %{
4514 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4515 match(iRegLdst);
4516 format %{ %}
4517 interface(REG_INTER);
4518 %}
4520 operand rarg3RegL() %{
4521 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4522 match(iRegLdst);
4523 format %{ %}
4524 interface(REG_INTER);
4525 %}
4527 operand rarg4RegL() %{
4528 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4529 match(iRegLdst);
4530 format %{ %}
4531 interface(REG_INTER);
4532 %}
4534 // Pointer Destination Register
4535 // See definition of reg_class bits64_reg_rw.
4536 operand iRegPdst() %{
4537 constraint(ALLOC_IN_RC(bits64_reg_rw));
4538 match(RegP);
4539 match(rscratch1RegP);
4540 match(rscratch2RegP);
4541 match(rarg1RegP);
4542 match(rarg2RegP);
4543 match(rarg3RegP);
4544 match(rarg4RegP);
4545 format %{ %}
4546 interface(REG_INTER);
4547 %}
4549 // Pointer Destination Register
4550 // Operand not using r11 and r12 (killed in epilog).
4551 operand iRegPdstNoScratch() %{
4552 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4553 match(RegP);
4554 match(rarg1RegP);
4555 match(rarg2RegP);
4556 match(rarg3RegP);
4557 match(rarg4RegP);
4558 format %{ %}
4559 interface(REG_INTER);
4560 %}
4562 // Pointer Source Register
4563 // See definition of reg_class bits64_reg_ro.
4564 operand iRegPsrc() %{
4565 constraint(ALLOC_IN_RC(bits64_reg_ro));
4566 match(RegP);
4567 match(iRegPdst);
4568 match(rscratch1RegP);
4569 match(rscratch2RegP);
4570 match(rarg1RegP);
4571 match(rarg2RegP);
4572 match(rarg3RegP);
4573 match(rarg4RegP);
4574 match(threadRegP);
4575 format %{ %}
4576 interface(REG_INTER);
4577 %}
4579 // Thread operand.
4580 operand threadRegP() %{
4581 constraint(ALLOC_IN_RC(thread_bits64_reg));
4582 match(iRegPdst);
4583 format %{ "R16" %}
4584 interface(REG_INTER);
4585 %}
4587 operand rscratch1RegP() %{
4588 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4589 match(iRegPdst);
4590 format %{ "R11" %}
4591 interface(REG_INTER);
4592 %}
4594 operand rscratch2RegP() %{
4595 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4596 match(iRegPdst);
4597 format %{ %}
4598 interface(REG_INTER);
4599 %}
4601 operand rarg1RegP() %{
4602 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4603 match(iRegPdst);
4604 format %{ %}
4605 interface(REG_INTER);
4606 %}
4608 operand rarg2RegP() %{
4609 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4610 match(iRegPdst);
4611 format %{ %}
4612 interface(REG_INTER);
4613 %}
4615 operand rarg3RegP() %{
4616 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4617 match(iRegPdst);
4618 format %{ %}
4619 interface(REG_INTER);
4620 %}
4622 operand rarg4RegP() %{
4623 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4624 match(iRegPdst);
4625 format %{ %}
4626 interface(REG_INTER);
4627 %}
4629 operand iRegNsrc() %{
4630 constraint(ALLOC_IN_RC(bits32_reg_ro));
4631 match(RegN);
4632 match(iRegNdst);
4634 format %{ %}
4635 interface(REG_INTER);
4636 %}
4638 operand iRegNdst() %{
4639 constraint(ALLOC_IN_RC(bits32_reg_rw));
4640 match(RegN);
4642 format %{ %}
4643 interface(REG_INTER);
4644 %}
4646 // Long Destination Register
4647 // See definition of reg_class bits64_reg_rw.
4648 operand iRegLdst() %{
4649 constraint(ALLOC_IN_RC(bits64_reg_rw));
4650 match(RegL);
4651 match(rscratch1RegL);
4652 match(rscratch2RegL);
4653 format %{ %}
4654 interface(REG_INTER);
4655 %}
4657 // Long Source Register
4658 // See definition of reg_class bits64_reg_ro.
4659 operand iRegLsrc() %{
4660 constraint(ALLOC_IN_RC(bits64_reg_ro));
4661 match(RegL);
4662 match(iRegLdst);
4663 match(rscratch1RegL);
4664 match(rscratch2RegL);
4665 format %{ %}
4666 interface(REG_INTER);
4667 %}
4669 // Special operand for ConvL2I.
4670 operand iRegL2Isrc(iRegLsrc reg) %{
4671 constraint(ALLOC_IN_RC(bits64_reg_ro));
4672 match(ConvL2I reg);
4673 format %{ "ConvL2I($reg)" %}
4674 interface(REG_INTER)
4675 %}
4677 operand rscratch1RegL() %{
4678 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4679 match(RegL);
4680 format %{ %}
4681 interface(REG_INTER);
4682 %}
4684 operand rscratch2RegL() %{
4685 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4686 match(RegL);
4687 format %{ %}
4688 interface(REG_INTER);
4689 %}
4691 // Condition Code Flag Registers
4692 operand flagsReg() %{
4693 constraint(ALLOC_IN_RC(int_flags));
4694 match(RegFlags);
4695 format %{ %}
4696 interface(REG_INTER);
4697 %}
4699 // Condition Code Flag Register CR0
4700 operand flagsRegCR0() %{
4701 constraint(ALLOC_IN_RC(int_flags_CR0));
4702 match(RegFlags);
4703 format %{ "CR0" %}
4704 interface(REG_INTER);
4705 %}
4707 operand flagsRegCR1() %{
4708 constraint(ALLOC_IN_RC(int_flags_CR1));
4709 match(RegFlags);
4710 format %{ "CR1" %}
4711 interface(REG_INTER);
4712 %}
4714 operand flagsRegCR6() %{
4715 constraint(ALLOC_IN_RC(int_flags_CR6));
4716 match(RegFlags);
4717 format %{ "CR6" %}
4718 interface(REG_INTER);
4719 %}
4721 operand regCTR() %{
4722 constraint(ALLOC_IN_RC(ctr_reg));
4723 // RegFlags should work. Introducing a RegSpecial type would cause a
4724 // lot of changes.
4725 match(RegFlags);
4726 format %{"SR_CTR" %}
4727 interface(REG_INTER);
4728 %}
4730 operand regD() %{
4731 constraint(ALLOC_IN_RC(dbl_reg));
4732 match(RegD);
4733 format %{ %}
4734 interface(REG_INTER);
4735 %}
4737 operand regF() %{
4738 constraint(ALLOC_IN_RC(flt_reg));
4739 match(RegF);
4740 format %{ %}
4741 interface(REG_INTER);
4742 %}
4744 // Special Registers
4746 // Method Register
4747 operand inline_cache_regP(iRegPdst reg) %{
4748 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4749 match(reg);
4750 format %{ %}
4751 interface(REG_INTER);
4752 %}
4754 operand compiler_method_oop_regP(iRegPdst reg) %{
4755 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4756 match(reg);
4757 format %{ %}
4758 interface(REG_INTER);
4759 %}
4761 operand interpreter_method_oop_regP(iRegPdst reg) %{
4762 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4763 match(reg);
4764 format %{ %}
4765 interface(REG_INTER);
4766 %}
4768 // Operands to remove register moves in unscaled mode.
4769 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4770 operand iRegP2N(iRegPsrc reg) %{
4771 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4772 constraint(ALLOC_IN_RC(bits64_reg_ro));
4773 match(EncodeP reg);
4774 format %{ "$reg" %}
4775 interface(REG_INTER)
4776 %}
4778 operand iRegN2P(iRegNsrc reg) %{
4779 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4780 constraint(ALLOC_IN_RC(bits32_reg_ro));
4781 match(DecodeN reg);
4782 match(DecodeNKlass reg);
4783 format %{ "$reg" %}
4784 interface(REG_INTER)
4785 %}
4787 //----------Complex Operands---------------------------------------------------
4788 // Indirect Memory Reference
4789 operand indirect(iRegPsrc reg) %{
4790 constraint(ALLOC_IN_RC(bits64_reg_ro));
4791 match(reg);
4792 op_cost(100);
4793 format %{ "[$reg]" %}
4794 interface(MEMORY_INTER) %{
4795 base($reg);
4796 index(0x0);
4797 scale(0x0);
4798 disp(0x0);
4799 %}
4800 %}
4802 // Indirect with Offset
4803 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4804 constraint(ALLOC_IN_RC(bits64_reg_ro));
4805 match(AddP reg offset);
4806 op_cost(100);
4807 format %{ "[$reg + $offset]" %}
4808 interface(MEMORY_INTER) %{
4809 base($reg);
4810 index(0x0);
4811 scale(0x0);
4812 disp($offset);
4813 %}
4814 %}
4816 // Indirect with 4-aligned Offset
4817 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4818 constraint(ALLOC_IN_RC(bits64_reg_ro));
4819 match(AddP reg offset);
4820 op_cost(100);
4821 format %{ "[$reg + $offset]" %}
4822 interface(MEMORY_INTER) %{
4823 base($reg);
4824 index(0x0);
4825 scale(0x0);
4826 disp($offset);
4827 %}
4828 %}
4830 //----------Complex Operands for Compressed OOPs-------------------------------
4831 // Compressed OOPs with narrow_oop_shift == 0.
4833 // Indirect Memory Reference, compressed OOP
4834 operand indirectNarrow(iRegNsrc reg) %{
4835 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4836 constraint(ALLOC_IN_RC(bits64_reg_ro));
4837 match(DecodeN reg);
4838 match(DecodeNKlass reg);
4839 op_cost(100);
4840 format %{ "[$reg]" %}
4841 interface(MEMORY_INTER) %{
4842 base($reg);
4843 index(0x0);
4844 scale(0x0);
4845 disp(0x0);
4846 %}
4847 %}
4849 // Indirect with Offset, compressed OOP
4850 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4851 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4852 constraint(ALLOC_IN_RC(bits64_reg_ro));
4853 match(AddP (DecodeN reg) offset);
4854 match(AddP (DecodeNKlass reg) offset);
4855 op_cost(100);
4856 format %{ "[$reg + $offset]" %}
4857 interface(MEMORY_INTER) %{
4858 base($reg);
4859 index(0x0);
4860 scale(0x0);
4861 disp($offset);
4862 %}
4863 %}
4865 // Indirect with 4-aligned Offset, compressed OOP
4866 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4867 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4868 constraint(ALLOC_IN_RC(bits64_reg_ro));
4869 match(AddP (DecodeN reg) offset);
4870 match(AddP (DecodeNKlass reg) offset);
4871 op_cost(100);
4872 format %{ "[$reg + $offset]" %}
4873 interface(MEMORY_INTER) %{
4874 base($reg);
4875 index(0x0);
4876 scale(0x0);
4877 disp($offset);
4878 %}
4879 %}
4881 //----------Special Memory Operands--------------------------------------------
4882 // Stack Slot Operand
4883 //
4884 // This operand is used for loading and storing temporary values on
4885 // the stack where a match requires a value to flow through memory.
4886 operand stackSlotI(sRegI reg) %{
4887 constraint(ALLOC_IN_RC(stack_slots));
4888 op_cost(100);
4889 //match(RegI);
4890 format %{ "[sp+$reg]" %}
4891 interface(MEMORY_INTER) %{
4892 base(0x1); // R1_SP
4893 index(0x0);
4894 scale(0x0);
4895 disp($reg); // Stack Offset
4896 %}
4897 %}
4899 operand stackSlotL(sRegL reg) %{
4900 constraint(ALLOC_IN_RC(stack_slots));
4901 op_cost(100);
4902 //match(RegL);
4903 format %{ "[sp+$reg]" %}
4904 interface(MEMORY_INTER) %{
4905 base(0x1); // R1_SP
4906 index(0x0);
4907 scale(0x0);
4908 disp($reg); // Stack Offset
4909 %}
4910 %}
4912 operand stackSlotP(sRegP reg) %{
4913 constraint(ALLOC_IN_RC(stack_slots));
4914 op_cost(100);
4915 //match(RegP);
4916 format %{ "[sp+$reg]" %}
4917 interface(MEMORY_INTER) %{
4918 base(0x1); // R1_SP
4919 index(0x0);
4920 scale(0x0);
4921 disp($reg); // Stack Offset
4922 %}
4923 %}
4925 operand stackSlotF(sRegF reg) %{
4926 constraint(ALLOC_IN_RC(stack_slots));
4927 op_cost(100);
4928 //match(RegF);
4929 format %{ "[sp+$reg]" %}
4930 interface(MEMORY_INTER) %{
4931 base(0x1); // R1_SP
4932 index(0x0);
4933 scale(0x0);
4934 disp($reg); // Stack Offset
4935 %}
4936 %}
4938 operand stackSlotD(sRegD reg) %{
4939 constraint(ALLOC_IN_RC(stack_slots));
4940 op_cost(100);
4941 //match(RegD);
4942 format %{ "[sp+$reg]" %}
4943 interface(MEMORY_INTER) %{
4944 base(0x1); // R1_SP
4945 index(0x0);
4946 scale(0x0);
4947 disp($reg); // Stack Offset
4948 %}
4949 %}
4951 // Operands for expressing Control Flow
4952 // NOTE: Label is a predefined operand which should not be redefined in
4953 // the AD file. It is generically handled within the ADLC.
4955 //----------Conditional Branch Operands----------------------------------------
4956 // Comparison Op
4957 //
4958 // This is the operation of the comparison, and is limited to the
4959 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4960 // (!=).
4961 //
4962 // Other attributes of the comparison, such as unsignedness, are specified
4963 // by the comparison instruction that sets a condition code flags register.
4964 // That result is represented by a flags operand whose subtype is appropriate
4965 // to the unsignedness (etc.) of the comparison.
4966 //
4967 // Later, the instruction which matches both the Comparison Op (a Bool) and
4968 // the flags (produced by the Cmp) specifies the coding of the comparison op
4969 // by matching a specific subtype of Bool operand below.
4971 // When used for floating point comparisons: unordered same as less.
4972 operand cmpOp() %{
4973 match(Bool);
4974 format %{ "" %}
4975 interface(COND_INTER) %{
4976 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4977 // BO & BI
4978 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4979 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4980 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4981 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4982 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4983 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4984 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4985 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4986 %}
4987 %}
4989 //----------OPERAND CLASSES----------------------------------------------------
4990 // Operand Classes are groups of operands that are used to simplify
4991 // instruction definitions by not requiring the AD writer to specify
4992 // seperate instructions for every form of operand when the
4993 // instruction accepts multiple operand types with the same basic
4994 // encoding and format. The classic case of this is memory operands.
4995 // Indirect is not included since its use is limited to Compare & Swap.
4997 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
4998 // Memory operand where offsets are 4-aligned. Required for ld, std.
4999 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
5000 opclass indirectMemory(indirect, indirectNarrow);
5002 // Special opclass for I and ConvL2I.
5003 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5005 // Operand classes to match encode and decode. iRegN_P2N is only used
5006 // for storeN. I have never seen an encode node elsewhere.
5007 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5008 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5010 //----------PIPELINE-----------------------------------------------------------
5012 pipeline %{
5014 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5015 // J. Res. & Dev., No. 1, Jan. 2002.
5017 //----------ATTRIBUTES---------------------------------------------------------
5018 attributes %{
5020 // Power4 instructions are of fixed length.
5021 fixed_size_instructions;
5023 // TODO: if `bundle' means number of instructions fetched
5024 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5025 // max instructions issued per cycle, this is 5.
5026 max_instructions_per_bundle = 8;
5028 // A Power4 instruction is 4 bytes long.
5029 instruction_unit_size = 4;
5031 // The Power4 processor fetches 64 bytes...
5032 instruction_fetch_unit_size = 64;
5034 // ...in one line
5035 instruction_fetch_units = 1
5037 // Unused, list one so that array generated by adlc is not empty.
5038 // Aix compiler chokes if _nop_count = 0.
5039 nops(fxNop);
5040 %}
5042 //----------RESOURCES----------------------------------------------------------
5043 // Resources are the functional units available to the machine
5044 resources(
5045 PPC_BR, // branch unit
5046 PPC_CR, // condition unit
5047 PPC_FX1, // integer arithmetic unit 1
5048 PPC_FX2, // integer arithmetic unit 2
5049 PPC_LDST1, // load/store unit 1
5050 PPC_LDST2, // load/store unit 2
5051 PPC_FP1, // float arithmetic unit 1
5052 PPC_FP2, // float arithmetic unit 2
5053 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5054 PPC_FX = PPC_FX1 | PPC_FX2,
5055 PPC_FP = PPC_FP1 | PPC_FP2
5056 );
5058 //----------PIPELINE DESCRIPTION-----------------------------------------------
5059 // Pipeline Description specifies the stages in the machine's pipeline
5060 pipe_desc(
5061 // Power4 longest pipeline path
5062 PPC_IF, // instruction fetch
5063 PPC_IC,
5064 //PPC_BP, // branch prediction
5065 PPC_D0, // decode
5066 PPC_D1, // decode
5067 PPC_D2, // decode
5068 PPC_D3, // decode
5069 PPC_Xfer1,
5070 PPC_GD, // group definition
5071 PPC_MP, // map
5072 PPC_ISS, // issue
5073 PPC_RF, // resource fetch
5074 PPC_EX1, // execute (all units)
5075 PPC_EX2, // execute (FP, LDST)
5076 PPC_EX3, // execute (FP, LDST)
5077 PPC_EX4, // execute (FP)
5078 PPC_EX5, // execute (FP)
5079 PPC_EX6, // execute (FP)
5080 PPC_WB, // write back
5081 PPC_Xfer2,
5082 PPC_CP
5083 );
5085 //----------PIPELINE CLASSES---------------------------------------------------
5086 // Pipeline Classes describe the stages in which input and output are
5087 // referenced by the hardware pipeline.
5089 // Simple pipeline classes.
5091 // Default pipeline class.
5092 pipe_class pipe_class_default() %{
5093 single_instruction;
5094 fixed_latency(2);
5095 %}
5097 // Pipeline class for empty instructions.
5098 pipe_class pipe_class_empty() %{
5099 single_instruction;
5100 fixed_latency(0);
5101 %}
5103 // Pipeline class for compares.
5104 pipe_class pipe_class_compare() %{
5105 single_instruction;
5106 fixed_latency(16);
5107 %}
5109 // Pipeline class for traps.
5110 pipe_class pipe_class_trap() %{
5111 single_instruction;
5112 fixed_latency(100);
5113 %}
5115 // Pipeline class for memory operations.
5116 pipe_class pipe_class_memory() %{
5117 single_instruction;
5118 fixed_latency(16);
5119 %}
5121 // Pipeline class for call.
5122 pipe_class pipe_class_call() %{
5123 single_instruction;
5124 fixed_latency(100);
5125 %}
5127 // Define the class for the Nop node.
5128 define %{
5129 MachNop = pipe_class_default;
5130 %}
5132 %}
5134 //----------INSTRUCTIONS-------------------------------------------------------
5136 // Naming of instructions:
5137 // opA_operB / opA_operB_operC:
5138 // Operation 'op' with one or two source operands 'oper'. Result
5139 // type is A, source operand types are B and C.
5140 // Iff A == B == C, B and C are left out.
5141 //
5142 // The instructions are ordered according to the following scheme:
5143 // - loads
5144 // - load constants
5145 // - prefetch
5146 // - store
5147 // - encode/decode
5148 // - membar
5149 // - conditional moves
5150 // - compare & swap
5151 // - arithmetic and logic operations
5152 // * int: Add, Sub, Mul, Div, Mod
5153 // * int: lShift, arShift, urShift, rot
5154 // * float: Add, Sub, Mul, Div
5155 // * and, or, xor ...
5156 // - register moves: float <-> int, reg <-> stack, repl
5157 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5158 // - conv (low level type cast requiring bit changes (sign extend etc)
5159 // - compares, range & zero checks.
5160 // - branches
5161 // - complex operations, intrinsics, min, max, replicate
5162 // - lock
5163 // - Calls
5164 //
5165 // If there are similar instructions with different types they are sorted:
5166 // int before float
5167 // small before big
5168 // signed before unsigned
5169 // e.g., loadS before loadUS before loadI before loadF.
5172 //----------Load/Store Instructions--------------------------------------------
5174 //----------Load Instructions--------------------------------------------------
5176 // Converts byte to int.
5177 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5178 // reuses the 'amount' operand, but adlc expects that operand specification
5179 // and operands in match rule are equivalent.
5180 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5181 effect(DEF dst, USE src);
5182 format %{ "EXTSB $dst, $src \t// byte->int" %}
5183 size(4);
5184 ins_encode %{
5185 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5186 __ extsb($dst$$Register, $src$$Register);
5187 %}
5188 ins_pipe(pipe_class_default);
5189 %}
5191 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5192 // match-rule, false predicate
5193 match(Set dst (LoadB mem));
5194 predicate(false);
5196 format %{ "LBZ $dst, $mem" %}
5197 size(4);
5198 ins_encode( enc_lbz(dst, mem) );
5199 ins_pipe(pipe_class_memory);
5200 %}
5202 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5203 // match-rule, false predicate
5204 match(Set dst (LoadB mem));
5205 predicate(false);
5207 format %{ "LBZ $dst, $mem\n\t"
5208 "TWI $dst\n\t"
5209 "ISYNC" %}
5210 size(12);
5211 ins_encode( enc_lbz_ac(dst, mem) );
5212 ins_pipe(pipe_class_memory);
5213 %}
5215 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5216 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5217 match(Set dst (LoadB mem));
5218 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5219 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5220 expand %{
5221 iRegIdst tmp;
5222 loadUB_indirect(tmp, mem);
5223 convB2I_reg_2(dst, tmp);
5224 %}
5225 %}
5227 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5228 match(Set dst (LoadB mem));
5229 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5230 expand %{
5231 iRegIdst tmp;
5232 loadUB_indirect_ac(tmp, mem);
5233 convB2I_reg_2(dst, tmp);
5234 %}
5235 %}
5237 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5238 // match-rule, false predicate
5239 match(Set dst (LoadB mem));
5240 predicate(false);
5242 format %{ "LBZ $dst, $mem" %}
5243 size(4);
5244 ins_encode( enc_lbz(dst, mem) );
5245 ins_pipe(pipe_class_memory);
5246 %}
5248 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5249 // match-rule, false predicate
5250 match(Set dst (LoadB mem));
5251 predicate(false);
5253 format %{ "LBZ $dst, $mem\n\t"
5254 "TWI $dst\n\t"
5255 "ISYNC" %}
5256 size(12);
5257 ins_encode( enc_lbz_ac(dst, mem) );
5258 ins_pipe(pipe_class_memory);
5259 %}
5261 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5262 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5263 match(Set dst (LoadB mem));
5264 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5265 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5267 expand %{
5268 iRegIdst tmp;
5269 loadUB_indOffset16(tmp, mem);
5270 convB2I_reg_2(dst, tmp);
5271 %}
5272 %}
5274 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5275 match(Set dst (LoadB mem));
5276 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5278 expand %{
5279 iRegIdst tmp;
5280 loadUB_indOffset16_ac(tmp, mem);
5281 convB2I_reg_2(dst, tmp);
5282 %}
5283 %}
5285 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5286 instruct loadUB(iRegIdst dst, memory mem) %{
5287 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5288 match(Set dst (LoadUB mem));
5289 ins_cost(MEMORY_REF_COST);
5291 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5292 size(4);
5293 ins_encode( enc_lbz(dst, mem) );
5294 ins_pipe(pipe_class_memory);
5295 %}
5297 // Load Unsigned Byte (8bit UNsigned) acquire.
5298 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5299 match(Set dst (LoadUB mem));
5300 ins_cost(3*MEMORY_REF_COST);
5302 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5303 "TWI $dst\n\t"
5304 "ISYNC" %}
5305 size(12);
5306 ins_encode( enc_lbz_ac(dst, mem) );
5307 ins_pipe(pipe_class_memory);
5308 %}
5310 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5311 instruct loadUB2L(iRegLdst dst, memory mem) %{
5312 match(Set dst (ConvI2L (LoadUB mem)));
5313 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5314 ins_cost(MEMORY_REF_COST);
5316 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5317 size(4);
5318 ins_encode( enc_lbz(dst, mem) );
5319 ins_pipe(pipe_class_memory);
5320 %}
5322 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5323 match(Set dst (ConvI2L (LoadUB mem)));
5324 ins_cost(3*MEMORY_REF_COST);
5326 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5327 "TWI $dst\n\t"
5328 "ISYNC" %}
5329 size(12);
5330 ins_encode( enc_lbz_ac(dst, mem) );
5331 ins_pipe(pipe_class_memory);
5332 %}
5334 // Load Short (16bit signed)
5335 instruct loadS(iRegIdst dst, memory mem) %{
5336 match(Set dst (LoadS mem));
5337 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5338 ins_cost(MEMORY_REF_COST);
5340 format %{ "LHA $dst, $mem" %}
5341 size(4);
5342 ins_encode %{
5343 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5344 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5345 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5346 %}
5347 ins_pipe(pipe_class_memory);
5348 %}
5350 // Load Short (16bit signed) acquire.
5351 instruct loadS_ac(iRegIdst dst, memory mem) %{
5352 match(Set dst (LoadS mem));
5353 ins_cost(3*MEMORY_REF_COST);
5355 format %{ "LHA $dst, $mem\t acquire\n\t"
5356 "TWI $dst\n\t"
5357 "ISYNC" %}
5358 size(12);
5359 ins_encode %{
5360 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5361 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5362 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5363 __ twi_0($dst$$Register);
5364 __ isync();
5365 %}
5366 ins_pipe(pipe_class_memory);
5367 %}
5369 // Load Char (16bit unsigned)
5370 instruct loadUS(iRegIdst dst, memory mem) %{
5371 match(Set dst (LoadUS mem));
5372 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5373 ins_cost(MEMORY_REF_COST);
5375 format %{ "LHZ $dst, $mem" %}
5376 size(4);
5377 ins_encode( enc_lhz(dst, mem) );
5378 ins_pipe(pipe_class_memory);
5379 %}
5381 // Load Char (16bit unsigned) acquire.
5382 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5383 match(Set dst (LoadUS mem));
5384 ins_cost(3*MEMORY_REF_COST);
5386 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5387 "TWI $dst\n\t"
5388 "ISYNC" %}
5389 size(12);
5390 ins_encode( enc_lhz_ac(dst, mem) );
5391 ins_pipe(pipe_class_memory);
5392 %}
5394 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5395 instruct loadUS2L(iRegLdst dst, memory mem) %{
5396 match(Set dst (ConvI2L (LoadUS mem)));
5397 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5398 ins_cost(MEMORY_REF_COST);
5400 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5401 size(4);
5402 ins_encode( enc_lhz(dst, mem) );
5403 ins_pipe(pipe_class_memory);
5404 %}
5406 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5407 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5408 match(Set dst (ConvI2L (LoadUS mem)));
5409 ins_cost(3*MEMORY_REF_COST);
5411 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5412 "TWI $dst\n\t"
5413 "ISYNC" %}
5414 size(12);
5415 ins_encode( enc_lhz_ac(dst, mem) );
5416 ins_pipe(pipe_class_memory);
5417 %}
5419 // Load Integer.
5420 instruct loadI(iRegIdst dst, memory mem) %{
5421 match(Set dst (LoadI mem));
5422 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5423 ins_cost(MEMORY_REF_COST);
5425 format %{ "LWZ $dst, $mem" %}
5426 size(4);
5427 ins_encode( enc_lwz(dst, mem) );
5428 ins_pipe(pipe_class_memory);
5429 %}
5431 // Load Integer acquire.
5432 instruct loadI_ac(iRegIdst dst, memory mem) %{
5433 match(Set dst (LoadI mem));
5434 ins_cost(3*MEMORY_REF_COST);
5436 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5437 "TWI $dst\n\t"
5438 "ISYNC" %}
5439 size(12);
5440 ins_encode( enc_lwz_ac(dst, mem) );
5441 ins_pipe(pipe_class_memory);
5442 %}
5444 // Match loading integer and casting it to unsigned int in
5445 // long register.
5446 // LoadI + ConvI2L + AndL 0xffffffff.
5447 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5448 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5449 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5450 ins_cost(MEMORY_REF_COST);
5452 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5453 size(4);
5454 ins_encode( enc_lwz(dst, mem) );
5455 ins_pipe(pipe_class_memory);
5456 %}
5458 // Match loading integer and casting it to long.
5459 instruct loadI2L(iRegLdst dst, memory mem) %{
5460 match(Set dst (ConvI2L (LoadI mem)));
5461 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5462 ins_cost(MEMORY_REF_COST);
5464 format %{ "LWA $dst, $mem \t// loadI2L" %}
5465 size(4);
5466 ins_encode %{
5467 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5468 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5469 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5470 %}
5471 ins_pipe(pipe_class_memory);
5472 %}
5474 // Match loading integer and casting it to long - acquire.
5475 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5476 match(Set dst (ConvI2L (LoadI mem)));
5477 ins_cost(3*MEMORY_REF_COST);
5479 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5480 "TWI $dst\n\t"
5481 "ISYNC" %}
5482 size(12);
5483 ins_encode %{
5484 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5485 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5486 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5487 __ twi_0($dst$$Register);
5488 __ isync();
5489 %}
5490 ins_pipe(pipe_class_memory);
5491 %}
5493 // Load Long - aligned
5494 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5495 match(Set dst (LoadL mem));
5496 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5497 ins_cost(MEMORY_REF_COST);
5499 format %{ "LD $dst, $mem \t// long" %}
5500 size(4);
5501 ins_encode( enc_ld(dst, mem) );
5502 ins_pipe(pipe_class_memory);
5503 %}
5505 // Load Long - aligned acquire.
5506 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5507 match(Set dst (LoadL mem));
5508 ins_cost(3*MEMORY_REF_COST);
5510 format %{ "LD $dst, $mem \t// long acquire\n\t"
5511 "TWI $dst\n\t"
5512 "ISYNC" %}
5513 size(12);
5514 ins_encode( enc_ld_ac(dst, mem) );
5515 ins_pipe(pipe_class_memory);
5516 %}
5518 // Load Long - UNaligned
5519 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5520 match(Set dst (LoadL_unaligned mem));
5521 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5522 ins_cost(MEMORY_REF_COST);
5524 format %{ "LD $dst, $mem \t// unaligned long" %}
5525 size(4);
5526 ins_encode( enc_ld(dst, mem) );
5527 ins_pipe(pipe_class_memory);
5528 %}
5530 // Load nodes for superwords
5532 // Load Aligned Packed Byte
5533 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5534 predicate(n->as_LoadVector()->memory_size() == 8);
5535 match(Set dst (LoadVector mem));
5536 ins_cost(MEMORY_REF_COST);
5538 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5539 size(4);
5540 ins_encode( enc_ld(dst, mem) );
5541 ins_pipe(pipe_class_memory);
5542 %}
5544 // Load Range, range = array length (=jint)
5545 instruct loadRange(iRegIdst dst, memory mem) %{
5546 match(Set dst (LoadRange mem));
5547 ins_cost(MEMORY_REF_COST);
5549 format %{ "LWZ $dst, $mem \t// range" %}
5550 size(4);
5551 ins_encode( enc_lwz(dst, mem) );
5552 ins_pipe(pipe_class_memory);
5553 %}
5555 // Load Compressed Pointer
5556 instruct loadN(iRegNdst dst, memory mem) %{
5557 match(Set dst (LoadN mem));
5558 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5559 ins_cost(MEMORY_REF_COST);
5561 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5562 size(4);
5563 ins_encode( enc_lwz(dst, mem) );
5564 ins_pipe(pipe_class_memory);
5565 %}
5567 // Load Compressed Pointer acquire.
5568 instruct loadN_ac(iRegNdst dst, memory mem) %{
5569 match(Set dst (LoadN mem));
5570 ins_cost(3*MEMORY_REF_COST);
5572 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5573 "TWI $dst\n\t"
5574 "ISYNC" %}
5575 size(12);
5576 ins_encode( enc_lwz_ac(dst, mem) );
5577 ins_pipe(pipe_class_memory);
5578 %}
5580 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5581 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5582 match(Set dst (DecodeN (LoadN mem)));
5583 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5584 ins_cost(MEMORY_REF_COST);
5586 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5587 size(4);
5588 ins_encode( enc_lwz(dst, mem) );
5589 ins_pipe(pipe_class_memory);
5590 %}
5592 // Load Pointer
5593 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5594 match(Set dst (LoadP mem));
5595 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5596 ins_cost(MEMORY_REF_COST);
5598 format %{ "LD $dst, $mem \t// ptr" %}
5599 size(4);
5600 ins_encode( enc_ld(dst, mem) );
5601 ins_pipe(pipe_class_memory);
5602 %}
5604 // Load Pointer acquire.
5605 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5606 match(Set dst (LoadP mem));
5607 ins_cost(3*MEMORY_REF_COST);
5609 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5610 "TWI $dst\n\t"
5611 "ISYNC" %}
5612 size(12);
5613 ins_encode( enc_ld_ac(dst, mem) );
5614 ins_pipe(pipe_class_memory);
5615 %}
5617 // LoadP + CastP2L
5618 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5619 match(Set dst (CastP2X (LoadP mem)));
5620 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5621 ins_cost(MEMORY_REF_COST);
5623 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5624 size(4);
5625 ins_encode( enc_ld(dst, mem) );
5626 ins_pipe(pipe_class_memory);
5627 %}
5629 // Load compressed klass pointer.
5630 instruct loadNKlass(iRegNdst dst, memory mem) %{
5631 match(Set dst (LoadNKlass mem));
5632 ins_cost(MEMORY_REF_COST);
5634 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5635 size(4);
5636 ins_encode( enc_lwz(dst, mem) );
5637 ins_pipe(pipe_class_memory);
5638 %}
5640 //// Load compressed klass and decode it if narrow_klass_shift == 0.
5641 //// TODO: will narrow_klass_shift ever be 0?
5642 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
5643 // match(Set dst (DecodeNKlass (LoadNKlass mem)));
5644 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
5645 // ins_cost(MEMORY_REF_COST);
5646 //
5647 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
5648 // size(4);
5649 // ins_encode( enc_lwz(dst, mem) );
5650 // ins_pipe(pipe_class_memory);
5651 //%}
5653 // Load Klass Pointer
5654 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5655 match(Set dst (LoadKlass mem));
5656 ins_cost(MEMORY_REF_COST);
5658 format %{ "LD $dst, $mem \t// klass ptr" %}
5659 size(4);
5660 ins_encode( enc_ld(dst, mem) );
5661 ins_pipe(pipe_class_memory);
5662 %}
5664 // Load Float
5665 instruct loadF(regF dst, memory mem) %{
5666 match(Set dst (LoadF mem));
5667 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5668 ins_cost(MEMORY_REF_COST);
5670 format %{ "LFS $dst, $mem" %}
5671 size(4);
5672 ins_encode %{
5673 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5674 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5675 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5676 %}
5677 ins_pipe(pipe_class_memory);
5678 %}
5680 // Load Float acquire.
5681 instruct loadF_ac(regF dst, memory mem) %{
5682 match(Set dst (LoadF mem));
5683 ins_cost(3*MEMORY_REF_COST);
5685 format %{ "LFS $dst, $mem \t// acquire\n\t"
5686 "FCMPU cr0, $dst, $dst\n\t"
5687 "BNE cr0, next\n"
5688 "next:\n\t"
5689 "ISYNC" %}
5690 size(16);
5691 ins_encode %{
5692 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5693 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5694 Label next;
5695 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5696 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5697 __ bne(CCR0, next);
5698 __ bind(next);
5699 __ isync();
5700 %}
5701 ins_pipe(pipe_class_memory);
5702 %}
5704 // Load Double - aligned
5705 instruct loadD(regD dst, memory mem) %{
5706 match(Set dst (LoadD mem));
5707 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5708 ins_cost(MEMORY_REF_COST);
5710 format %{ "LFD $dst, $mem" %}
5711 size(4);
5712 ins_encode( enc_lfd(dst, mem) );
5713 ins_pipe(pipe_class_memory);
5714 %}
5716 // Load Double - aligned acquire.
5717 instruct loadD_ac(regD dst, memory mem) %{
5718 match(Set dst (LoadD mem));
5719 ins_cost(3*MEMORY_REF_COST);
5721 format %{ "LFD $dst, $mem \t// acquire\n\t"
5722 "FCMPU cr0, $dst, $dst\n\t"
5723 "BNE cr0, next\n"
5724 "next:\n\t"
5725 "ISYNC" %}
5726 size(16);
5727 ins_encode %{
5728 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5729 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5730 Label next;
5731 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5732 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5733 __ bne(CCR0, next);
5734 __ bind(next);
5735 __ isync();
5736 %}
5737 ins_pipe(pipe_class_memory);
5738 %}
5740 // Load Double - UNaligned
5741 instruct loadD_unaligned(regD dst, memory mem) %{
5742 match(Set dst (LoadD_unaligned mem));
5743 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5744 ins_cost(MEMORY_REF_COST);
5746 format %{ "LFD $dst, $mem" %}
5747 size(4);
5748 ins_encode( enc_lfd(dst, mem) );
5749 ins_pipe(pipe_class_memory);
5750 %}
5752 //----------Constants--------------------------------------------------------
5754 // Load MachConstantTableBase: add hi offset to global toc.
5755 // TODO: Handle hidden register r29 in bundler!
5756 instruct loadToc_hi(iRegLdst dst) %{
5757 effect(DEF dst);
5758 ins_cost(DEFAULT_COST);
5760 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5761 size(4);
5762 ins_encode %{
5763 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5764 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5765 %}
5766 ins_pipe(pipe_class_default);
5767 %}
5769 // Load MachConstantTableBase: add lo offset to global toc.
5770 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5771 effect(DEF dst, USE src);
5772 ins_cost(DEFAULT_COST);
5774 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5775 size(4);
5776 ins_encode %{
5777 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5778 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5779 %}
5780 ins_pipe(pipe_class_default);
5781 %}
5783 // Load 16-bit integer constant 0xssss????
5784 instruct loadConI16(iRegIdst dst, immI16 src) %{
5785 match(Set dst src);
5787 format %{ "LI $dst, $src" %}
5788 size(4);
5789 ins_encode %{
5790 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5791 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5792 %}
5793 ins_pipe(pipe_class_default);
5794 %}
5796 // Load integer constant 0x????0000
5797 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5798 match(Set dst src);
5799 ins_cost(DEFAULT_COST);
5801 format %{ "LIS $dst, $src.hi" %}
5802 size(4);
5803 ins_encode %{
5804 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5805 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5806 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5807 %}
5808 ins_pipe(pipe_class_default);
5809 %}
5811 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5812 // and sign extended), this adds the low 16 bits.
5813 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5814 // no match-rule, false predicate
5815 effect(DEF dst, USE src1, USE src2);
5816 predicate(false);
5818 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5819 size(4);
5820 ins_encode %{
5821 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5822 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5823 %}
5824 ins_pipe(pipe_class_default);
5825 %}
5827 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5828 match(Set dst src);
5829 ins_cost(DEFAULT_COST*2);
5831 expand %{
5832 // Would like to use $src$$constant.
5833 immI16 srcLo %{ _opnds[1]->constant() %}
5834 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5835 immIhi16 srcHi %{ _opnds[1]->constant() %}
5836 iRegIdst tmpI;
5837 loadConIhi16(tmpI, srcHi);
5838 loadConI32_lo16(dst, tmpI, srcLo);
5839 %}
5840 %}
5842 // No constant pool entries required.
5843 instruct loadConL16(iRegLdst dst, immL16 src) %{
5844 match(Set dst src);
5846 format %{ "LI $dst, $src \t// long" %}
5847 size(4);
5848 ins_encode %{
5849 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5850 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5851 %}
5852 ins_pipe(pipe_class_default);
5853 %}
5855 // Load long constant 0xssssssss????0000
5856 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5857 match(Set dst src);
5858 ins_cost(DEFAULT_COST);
5860 format %{ "LIS $dst, $src.hi \t// long" %}
5861 size(4);
5862 ins_encode %{
5863 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5864 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5865 %}
5866 ins_pipe(pipe_class_default);
5867 %}
5869 // To load a 32 bit constant: merge lower 16 bits into already loaded
5870 // high 16 bits.
5871 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5872 // no match-rule, false predicate
5873 effect(DEF dst, USE src1, USE src2);
5874 predicate(false);
5876 format %{ "ORI $dst, $src1, $src2.lo" %}
5877 size(4);
5878 ins_encode %{
5879 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5880 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5881 %}
5882 ins_pipe(pipe_class_default);
5883 %}
5885 // Load 32-bit long constant
5886 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5887 match(Set dst src);
5888 ins_cost(DEFAULT_COST*2);
5890 expand %{
5891 // Would like to use $src$$constant.
5892 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5893 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5894 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5895 iRegLdst tmpL;
5896 loadConL32hi16(tmpL, srcHi);
5897 loadConL32_lo16(dst, tmpL, srcLo);
5898 %}
5899 %}
5901 // Load long constant 0x????000000000000.
5902 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5903 match(Set dst src);
5904 ins_cost(DEFAULT_COST);
5906 expand %{
5907 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5908 immI shift32 %{ 32 %}
5909 iRegLdst tmpL;
5910 loadConL32hi16(tmpL, srcHi);
5911 lshiftL_regL_immI(dst, tmpL, shift32);
5912 %}
5913 %}
5915 // Expand node for constant pool load: small offset.
5916 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5917 effect(DEF dst, USE src, USE toc);
5918 ins_cost(MEMORY_REF_COST);
5920 ins_num_consts(1);
5921 // Needed so that CallDynamicJavaDirect can compute the address of this
5922 // instruction for relocation.
5923 ins_field_cbuf_insts_offset(int);
5925 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5926 size(4);
5927 ins_encode( enc_load_long_constL(dst, src, toc) );
5928 ins_pipe(pipe_class_memory);
5929 %}
5931 // Expand node for constant pool load: large offset.
5932 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5933 effect(DEF dst, USE src, USE toc);
5934 predicate(false);
5936 ins_num_consts(1);
5937 ins_field_const_toc_offset(int);
5938 // Needed so that CallDynamicJavaDirect can compute the address of this
5939 // instruction for relocation.
5940 ins_field_cbuf_insts_offset(int);
5942 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5943 size(4);
5944 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5945 ins_pipe(pipe_class_default);
5946 %}
5948 // Expand node for constant pool load: large offset.
5949 // No constant pool entries required.
5950 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5951 effect(DEF dst, USE src, USE base);
5952 predicate(false);
5954 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5956 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5957 size(4);
5958 ins_encode %{
5959 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5960 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5961 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5962 %}
5963 ins_pipe(pipe_class_memory);
5964 %}
5966 // Load long constant from constant table. Expand in case of
5967 // offset > 16 bit is needed.
5968 // Adlc adds toc node MachConstantTableBase.
5969 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5970 match(Set dst src);
5971 ins_cost(MEMORY_REF_COST);
5973 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5974 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5975 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5976 %}
5978 // Load NULL as compressed oop.
5979 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5980 match(Set dst src);
5981 ins_cost(DEFAULT_COST);
5983 format %{ "LI $dst, $src \t// compressed ptr" %}
5984 size(4);
5985 ins_encode %{
5986 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5987 __ li($dst$$Register, 0);
5988 %}
5989 ins_pipe(pipe_class_default);
5990 %}
5992 // Load hi part of compressed oop constant.
5993 instruct loadConN_hi(iRegNdst dst, immN src) %{
5994 effect(DEF dst, USE src);
5995 ins_cost(DEFAULT_COST);
5997 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5998 size(4);
5999 ins_encode %{
6000 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6001 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
6002 %}
6003 ins_pipe(pipe_class_default);
6004 %}
6006 // Add lo part of compressed oop constant to already loaded hi part.
6007 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6008 effect(DEF dst, USE src1, USE src2);
6009 ins_cost(DEFAULT_COST);
6011 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6012 size(4);
6013 ins_encode %{
6014 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6015 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6016 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6017 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6018 __ relocate(rspec, 1);
6019 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6020 %}
6021 ins_pipe(pipe_class_default);
6022 %}
6024 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6025 // leaving the upper 32 bits with sign-extension bits.
6026 // This clears these bits: dst = src & 0xFFFFFFFF.
6027 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6028 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6029 effect(DEF dst, USE src);
6030 predicate(false);
6032 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6033 size(4);
6034 ins_encode %{
6035 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6036 __ clrldi($dst$$Register, $src$$Register, 0x20);
6037 %}
6038 ins_pipe(pipe_class_default);
6039 %}
6041 // Loading ConN must be postalloc expanded so that edges between
6042 // the nodes are safe. They may not interfere with a safepoint.
6043 // GL TODO: This needs three instructions: better put this into the constant pool.
6044 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6045 match(Set dst src);
6046 ins_cost(DEFAULT_COST*2);
6048 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6049 postalloc_expand %{
6050 MachNode *m1 = new (C) loadConN_hiNode();
6051 MachNode *m2 = new (C) loadConN_loNode();
6052 MachNode *m3 = new (C) clearMs32bNode();
6053 m1->add_req(NULL);
6054 m2->add_req(NULL, m1);
6055 m3->add_req(NULL, m2);
6056 m1->_opnds[0] = op_dst;
6057 m1->_opnds[1] = op_src;
6058 m2->_opnds[0] = op_dst;
6059 m2->_opnds[1] = op_dst;
6060 m2->_opnds[2] = op_src;
6061 m3->_opnds[0] = op_dst;
6062 m3->_opnds[1] = op_dst;
6063 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6064 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6065 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6066 nodes->push(m1);
6067 nodes->push(m2);
6068 nodes->push(m3);
6069 %}
6070 %}
6072 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
6073 effect(DEF dst, USE src);
6074 ins_cost(DEFAULT_COST);
6076 format %{ "LIS $dst, $src \t// narrow oop hi" %}
6077 size(4);
6078 ins_encode %{
6079 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6080 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6081 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6082 %}
6083 ins_pipe(pipe_class_default);
6084 %}
6086 // This needs a match rule so that build_oop_map knows this is
6087 // not a narrow oop.
6088 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6089 match(Set dst src1);
6090 effect(TEMP src2);
6091 ins_cost(DEFAULT_COST);
6093 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
6094 size(4);
6095 ins_encode %{
6096 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6097 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6098 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6099 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6100 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6102 __ relocate(rspec, 1);
6103 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6104 %}
6105 ins_pipe(pipe_class_default);
6106 %}
6108 // Loading ConNKlass must be postalloc expanded so that edges between
6109 // the nodes are safe. They may not interfere with a safepoint.
6110 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6111 match(Set dst src);
6112 ins_cost(DEFAULT_COST*2);
6114 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6115 postalloc_expand %{
6116 // Load high bits into register. Sign extended.
6117 MachNode *m1 = new (C) loadConNKlass_hiNode();
6118 m1->add_req(NULL);
6119 m1->_opnds[0] = op_dst;
6120 m1->_opnds[1] = op_src;
6121 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6122 nodes->push(m1);
6124 MachNode *m2 = m1;
6125 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6126 // Value might be 1-extended. Mask out these bits.
6127 m2 = new (C) clearMs32bNode();
6128 m2->add_req(NULL, m1);
6129 m2->_opnds[0] = op_dst;
6130 m2->_opnds[1] = op_dst;
6131 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6132 nodes->push(m2);
6133 }
6135 MachNode *m3 = new (C) loadConNKlass_loNode();
6136 m3->add_req(NULL, m2);
6137 m3->_opnds[0] = op_dst;
6138 m3->_opnds[1] = op_src;
6139 m3->_opnds[2] = op_dst;
6140 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6141 nodes->push(m3);
6142 %}
6143 %}
6145 // 0x1 is used in object initialization (initial object header).
6146 // No constant pool entries required.
6147 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6148 match(Set dst src);
6150 format %{ "LI $dst, $src \t// ptr" %}
6151 size(4);
6152 ins_encode %{
6153 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6154 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6155 %}
6156 ins_pipe(pipe_class_default);
6157 %}
6159 // Expand node for constant pool load: small offset.
6160 // The match rule is needed to generate the correct bottom_type(),
6161 // however this node should never match. The use of predicate is not
6162 // possible since ADLC forbids predicates for chain rules. The higher
6163 // costs do not prevent matching in this case. For that reason the
6164 // operand immP_NM with predicate(false) is used.
6165 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6166 match(Set dst src);
6167 effect(TEMP toc);
6169 ins_num_consts(1);
6171 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6172 size(4);
6173 ins_encode( enc_load_long_constP(dst, src, toc) );
6174 ins_pipe(pipe_class_memory);
6175 %}
6177 // Expand node for constant pool load: large offset.
6178 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6179 effect(DEF dst, USE src, USE toc);
6180 predicate(false);
6182 ins_num_consts(1);
6183 ins_field_const_toc_offset(int);
6185 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6186 size(4);
6187 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6188 ins_pipe(pipe_class_default);
6189 %}
6191 // Expand node for constant pool load: large offset.
6192 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6193 match(Set dst src);
6194 effect(TEMP base);
6196 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6198 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6199 size(4);
6200 ins_encode %{
6201 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6202 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6203 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6204 %}
6205 ins_pipe(pipe_class_memory);
6206 %}
6208 // Load pointer constant from constant table. Expand in case an
6209 // offset > 16 bit is needed.
6210 // Adlc adds toc node MachConstantTableBase.
6211 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6212 match(Set dst src);
6213 ins_cost(MEMORY_REF_COST);
6215 // This rule does not use "expand" because then
6216 // the result type is not known to be an Oop. An ADLC
6217 // enhancement will be needed to make that work - not worth it!
6219 // If this instruction rematerializes, it prolongs the live range
6220 // of the toc node, causing illegal graphs.
6221 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6222 ins_cannot_rematerialize(true);
6224 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6225 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6226 %}
6228 // Expand node for constant pool load: small offset.
6229 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6230 effect(DEF dst, USE src, USE toc);
6231 ins_cost(MEMORY_REF_COST);
6233 ins_num_consts(1);
6235 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6236 size(4);
6237 ins_encode %{
6238 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6239 address float_address = __ float_constant($src$$constant);
6240 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6241 %}
6242 ins_pipe(pipe_class_memory);
6243 %}
6245 // Expand node for constant pool load: large offset.
6246 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6247 effect(DEF dst, USE src, USE toc);
6248 ins_cost(MEMORY_REF_COST);
6250 ins_num_consts(1);
6252 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6253 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6254 "ADDIS $toc, $toc, -offset_hi"%}
6255 size(12);
6256 ins_encode %{
6257 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6258 FloatRegister Rdst = $dst$$FloatRegister;
6259 Register Rtoc = $toc$$Register;
6260 address float_address = __ float_constant($src$$constant);
6261 int offset = __ offset_to_method_toc(float_address);
6262 int hi = (offset + (1<<15))>>16;
6263 int lo = offset - hi * (1<<16);
6265 __ addis(Rtoc, Rtoc, hi);
6266 __ lfs(Rdst, lo, Rtoc);
6267 __ addis(Rtoc, Rtoc, -hi);
6268 %}
6269 ins_pipe(pipe_class_memory);
6270 %}
6272 // Adlc adds toc node MachConstantTableBase.
6273 instruct loadConF_Ex(regF dst, immF src) %{
6274 match(Set dst src);
6275 ins_cost(MEMORY_REF_COST);
6277 // See loadConP.
6278 ins_cannot_rematerialize(true);
6280 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6281 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6282 %}
6284 // Expand node for constant pool load: small offset.
6285 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6286 effect(DEF dst, USE src, USE toc);
6287 ins_cost(MEMORY_REF_COST);
6289 ins_num_consts(1);
6291 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6292 size(4);
6293 ins_encode %{
6294 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6295 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6296 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6297 %}
6298 ins_pipe(pipe_class_memory);
6299 %}
6301 // Expand node for constant pool load: large offset.
6302 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6303 effect(DEF dst, USE src, USE toc);
6304 ins_cost(MEMORY_REF_COST);
6306 ins_num_consts(1);
6308 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6309 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6310 "ADDIS $toc, $toc, -offset_hi" %}
6311 size(12);
6312 ins_encode %{
6313 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6314 FloatRegister Rdst = $dst$$FloatRegister;
6315 Register Rtoc = $toc$$Register;
6316 address float_address = __ double_constant($src$$constant);
6317 int offset = __ offset_to_method_toc(float_address);
6318 int hi = (offset + (1<<15))>>16;
6319 int lo = offset - hi * (1<<16);
6321 __ addis(Rtoc, Rtoc, hi);
6322 __ lfd(Rdst, lo, Rtoc);
6323 __ addis(Rtoc, Rtoc, -hi);
6324 %}
6325 ins_pipe(pipe_class_memory);
6326 %}
6328 // Adlc adds toc node MachConstantTableBase.
6329 instruct loadConD_Ex(regD dst, immD src) %{
6330 match(Set dst src);
6331 ins_cost(MEMORY_REF_COST);
6333 // See loadConP.
6334 ins_cannot_rematerialize(true);
6336 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6337 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6338 %}
6340 // Prefetch instructions.
6341 // Must be safe to execute with invalid address (cannot fault).
6343 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6344 match(PrefetchRead (AddP mem src));
6345 ins_cost(MEMORY_REF_COST);
6347 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6348 size(4);
6349 ins_encode %{
6350 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6351 __ dcbt($src$$Register, $mem$$base$$Register);
6352 %}
6353 ins_pipe(pipe_class_memory);
6354 %}
6356 instruct prefetchr_no_offset(indirectMemory mem) %{
6357 match(PrefetchRead mem);
6358 ins_cost(MEMORY_REF_COST);
6360 format %{ "PREFETCH $mem" %}
6361 size(4);
6362 ins_encode %{
6363 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6364 __ dcbt($mem$$base$$Register);
6365 %}
6366 ins_pipe(pipe_class_memory);
6367 %}
6369 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6370 match(PrefetchWrite (AddP mem src));
6371 ins_cost(MEMORY_REF_COST);
6373 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6374 size(4);
6375 ins_encode %{
6376 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6377 __ dcbtst($src$$Register, $mem$$base$$Register);
6378 %}
6379 ins_pipe(pipe_class_memory);
6380 %}
6382 instruct prefetchw_no_offset(indirectMemory mem) %{
6383 match(PrefetchWrite mem);
6384 ins_cost(MEMORY_REF_COST);
6386 format %{ "PREFETCH $mem" %}
6387 size(4);
6388 ins_encode %{
6389 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6390 __ dcbtst($mem$$base$$Register);
6391 %}
6392 ins_pipe(pipe_class_memory);
6393 %}
6395 // Special prefetch versions which use the dcbz instruction.
6396 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6397 match(PrefetchAllocation (AddP mem src));
6398 predicate(AllocatePrefetchStyle == 3);
6399 ins_cost(MEMORY_REF_COST);
6401 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6402 size(4);
6403 ins_encode %{
6404 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6405 __ dcbz($src$$Register, $mem$$base$$Register);
6406 %}
6407 ins_pipe(pipe_class_memory);
6408 %}
6410 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6411 match(PrefetchAllocation mem);
6412 predicate(AllocatePrefetchStyle == 3);
6413 ins_cost(MEMORY_REF_COST);
6415 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6416 size(4);
6417 ins_encode %{
6418 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6419 __ dcbz($mem$$base$$Register);
6420 %}
6421 ins_pipe(pipe_class_memory);
6422 %}
6424 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6425 match(PrefetchAllocation (AddP mem src));
6426 predicate(AllocatePrefetchStyle != 3);
6427 ins_cost(MEMORY_REF_COST);
6429 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6430 size(4);
6431 ins_encode %{
6432 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6433 __ dcbtst($src$$Register, $mem$$base$$Register);
6434 %}
6435 ins_pipe(pipe_class_memory);
6436 %}
6438 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6439 match(PrefetchAllocation mem);
6440 predicate(AllocatePrefetchStyle != 3);
6441 ins_cost(MEMORY_REF_COST);
6443 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6444 size(4);
6445 ins_encode %{
6446 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6447 __ dcbtst($mem$$base$$Register);
6448 %}
6449 ins_pipe(pipe_class_memory);
6450 %}
6452 //----------Store Instructions-------------------------------------------------
6454 // Store Byte
6455 instruct storeB(memory mem, iRegIsrc src) %{
6456 match(Set mem (StoreB mem src));
6457 ins_cost(MEMORY_REF_COST);
6459 format %{ "STB $src, $mem \t// byte" %}
6460 size(4);
6461 ins_encode %{
6462 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6463 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6464 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6465 %}
6466 ins_pipe(pipe_class_memory);
6467 %}
6469 // Store Char/Short
6470 instruct storeC(memory mem, iRegIsrc src) %{
6471 match(Set mem (StoreC mem src));
6472 ins_cost(MEMORY_REF_COST);
6474 format %{ "STH $src, $mem \t// short" %}
6475 size(4);
6476 ins_encode %{
6477 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6478 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6479 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6480 %}
6481 ins_pipe(pipe_class_memory);
6482 %}
6484 // Store Integer
6485 instruct storeI(memory mem, iRegIsrc src) %{
6486 match(Set mem (StoreI mem src));
6487 ins_cost(MEMORY_REF_COST);
6489 format %{ "STW $src, $mem" %}
6490 size(4);
6491 ins_encode( enc_stw(src, mem) );
6492 ins_pipe(pipe_class_memory);
6493 %}
6495 // ConvL2I + StoreI.
6496 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6497 match(Set mem (StoreI mem (ConvL2I src)));
6498 ins_cost(MEMORY_REF_COST);
6500 format %{ "STW l2i($src), $mem" %}
6501 size(4);
6502 ins_encode( enc_stw(src, mem) );
6503 ins_pipe(pipe_class_memory);
6504 %}
6506 // Store Long
6507 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6508 match(Set mem (StoreL mem src));
6509 ins_cost(MEMORY_REF_COST);
6511 format %{ "STD $src, $mem \t// long" %}
6512 size(4);
6513 ins_encode( enc_std(src, mem) );
6514 ins_pipe(pipe_class_memory);
6515 %}
6517 // Store super word nodes.
6519 // Store Aligned Packed Byte long register to memory
6520 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6521 predicate(n->as_StoreVector()->memory_size() == 8);
6522 match(Set mem (StoreVector mem src));
6523 ins_cost(MEMORY_REF_COST);
6525 format %{ "STD $mem, $src \t// packed8B" %}
6526 size(4);
6527 ins_encode( enc_std(src, mem) );
6528 ins_pipe(pipe_class_memory);
6529 %}
6531 // Store Compressed Oop
6532 instruct storeN(memory dst, iRegN_P2N src) %{
6533 match(Set dst (StoreN dst src));
6534 ins_cost(MEMORY_REF_COST);
6536 format %{ "STW $src, $dst \t// compressed oop" %}
6537 size(4);
6538 ins_encode( enc_stw(src, dst) );
6539 ins_pipe(pipe_class_memory);
6540 %}
6542 // Store Compressed KLass
6543 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6544 match(Set dst (StoreNKlass dst src));
6545 ins_cost(MEMORY_REF_COST);
6547 format %{ "STW $src, $dst \t// compressed klass" %}
6548 size(4);
6549 ins_encode( enc_stw(src, dst) );
6550 ins_pipe(pipe_class_memory);
6551 %}
6553 // Store Pointer
6554 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6555 match(Set dst (StoreP dst src));
6556 ins_cost(MEMORY_REF_COST);
6558 format %{ "STD $src, $dst \t// ptr" %}
6559 size(4);
6560 ins_encode( enc_std(src, dst) );
6561 ins_pipe(pipe_class_memory);
6562 %}
6564 // Store Float
6565 instruct storeF(memory mem, regF src) %{
6566 match(Set mem (StoreF mem src));
6567 ins_cost(MEMORY_REF_COST);
6569 format %{ "STFS $src, $mem" %}
6570 size(4);
6571 ins_encode( enc_stfs(src, mem) );
6572 ins_pipe(pipe_class_memory);
6573 %}
6575 // Store Double
6576 instruct storeD(memory mem, regD src) %{
6577 match(Set mem (StoreD mem src));
6578 ins_cost(MEMORY_REF_COST);
6580 format %{ "STFD $src, $mem" %}
6581 size(4);
6582 ins_encode( enc_stfd(src, mem) );
6583 ins_pipe(pipe_class_memory);
6584 %}
6586 //----------Store Instructions With Zeros--------------------------------------
6588 // Card-mark for CMS garbage collection.
6589 // This cardmark does an optimization so that it must not always
6590 // do a releasing store. For this, it gets the address of
6591 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6592 // (Using releaseFieldAddr in the match rule is a hack.)
6593 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6594 match(Set mem (StoreCM mem releaseFieldAddr));
6595 predicate(false);
6596 ins_cost(MEMORY_REF_COST);
6598 // See loadConP.
6599 ins_cannot_rematerialize(true);
6601 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6602 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6603 ins_pipe(pipe_class_memory);
6604 %}
6606 // Card-mark for CMS garbage collection.
6607 // This cardmark does an optimization so that it must not always
6608 // do a releasing store. For this, it needs the constant address of
6609 // CMSCollectorCardTableModRefBSExt::_requires_release.
6610 // This constant address is split off here by expand so we can use
6611 // adlc / matcher functionality to load it from the constant section.
6612 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6613 match(Set mem (StoreCM mem zero));
6614 predicate(UseConcMarkSweepGC);
6616 expand %{
6617 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6618 iRegLdst releaseFieldAddress;
6619 loadConL_Ex(releaseFieldAddress, baseImm);
6620 storeCM_CMS(mem, releaseFieldAddress);
6621 %}
6622 %}
6624 instruct storeCM_G1(memory mem, immI_0 zero) %{
6625 match(Set mem (StoreCM mem zero));
6626 predicate(UseG1GC);
6627 ins_cost(MEMORY_REF_COST);
6629 ins_cannot_rematerialize(true);
6631 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6632 size(8);
6633 ins_encode %{
6634 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6635 __ li(R0, 0);
6636 //__ release(); // G1: oops are allowed to get visible after dirty marking
6637 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6638 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6639 %}
6640 ins_pipe(pipe_class_memory);
6641 %}
6643 // Convert oop pointer into compressed form.
6645 // Nodes for postalloc expand.
6647 // Shift node for expand.
6648 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6649 // The match rule is needed to make it a 'MachTypeNode'!
6650 match(Set dst (EncodeP src));
6651 predicate(false);
6653 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6654 size(4);
6655 ins_encode %{
6656 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6657 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6658 %}
6659 ins_pipe(pipe_class_default);
6660 %}
6662 // Add node for expand.
6663 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6664 // The match rule is needed to make it a 'MachTypeNode'!
6665 match(Set dst (EncodeP src));
6666 predicate(false);
6668 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6669 size(4);
6670 ins_encode %{
6671 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6672 __ subf($dst$$Register, R30, $src$$Register);
6673 %}
6674 ins_pipe(pipe_class_default);
6675 %}
6677 // Conditional sub base.
6678 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6679 // The match rule is needed to make it a 'MachTypeNode'!
6680 match(Set dst (EncodeP (Binary crx src1)));
6681 predicate(false);
6683 ins_variable_size_depending_on_alignment(true);
6685 format %{ "BEQ $crx, done\n\t"
6686 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6687 "done:" %}
6688 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6689 ins_encode %{
6690 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6691 Label done;
6692 __ beq($crx$$CondRegister, done);
6693 __ subf($dst$$Register, R30, $src1$$Register);
6694 // TODO PPC port __ endgroup_if_needed(_size == 12);
6695 __ bind(done);
6696 %}
6697 ins_pipe(pipe_class_default);
6698 %}
6700 // Power 7 can use isel instruction
6701 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6702 // The match rule is needed to make it a 'MachTypeNode'!
6703 match(Set dst (EncodeP (Binary crx src1)));
6704 predicate(false);
6706 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6707 size(4);
6708 ins_encode %{
6709 // This is a Power7 instruction for which no machine description exists.
6710 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6711 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6712 %}
6713 ins_pipe(pipe_class_default);
6714 %}
6716 // base != 0
6717 // 32G aligned narrow oop base.
6718 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6719 match(Set dst (EncodeP src));
6720 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6722 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6723 size(4);
6724 ins_encode %{
6725 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6726 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6727 %}
6728 ins_pipe(pipe_class_default);
6729 %}
6731 // shift != 0, base != 0
6732 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6733 match(Set dst (EncodeP src));
6734 effect(TEMP crx);
6735 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6736 Universe::narrow_oop_shift() != 0 &&
6737 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6739 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6740 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6741 %}
6743 // shift != 0, base != 0
6744 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6745 match(Set dst (EncodeP src));
6746 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6747 Universe::narrow_oop_shift() != 0 &&
6748 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6750 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6751 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6752 %}
6754 // shift != 0, base == 0
6755 // TODO: This is the same as encodeP_shift. Merge!
6756 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6757 match(Set dst (EncodeP src));
6758 predicate(Universe::narrow_oop_shift() != 0 &&
6759 Universe::narrow_oop_base() ==0);
6761 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6762 size(4);
6763 ins_encode %{
6764 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6765 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6766 %}
6767 ins_pipe(pipe_class_default);
6768 %}
6770 // Compressed OOPs with narrow_oop_shift == 0.
6771 // shift == 0, base == 0
6772 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6773 match(Set dst (EncodeP src));
6774 predicate(Universe::narrow_oop_shift() == 0);
6776 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6777 // variable size, 0 or 4.
6778 ins_encode %{
6779 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6780 __ mr_if_needed($dst$$Register, $src$$Register);
6781 %}
6782 ins_pipe(pipe_class_default);
6783 %}
6785 // Decode nodes.
6787 // Shift node for expand.
6788 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6789 // The match rule is needed to make it a 'MachTypeNode'!
6790 match(Set dst (DecodeN src));
6791 predicate(false);
6793 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6794 size(4);
6795 ins_encode %{
6796 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6797 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6798 %}
6799 ins_pipe(pipe_class_default);
6800 %}
6802 // Add node for expand.
6803 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6804 // The match rule is needed to make it a 'MachTypeNode'!
6805 match(Set dst (DecodeN src));
6806 predicate(false);
6808 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6809 size(4);
6810 ins_encode %{
6811 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6812 __ add($dst$$Register, $src$$Register, R30);
6813 %}
6814 ins_pipe(pipe_class_default);
6815 %}
6817 // conditianal add base for expand
6818 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6819 // The match rule is needed to make it a 'MachTypeNode'!
6820 // NOTICE that the rule is nonsense - we just have to make sure that:
6821 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6822 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6823 match(Set dst (DecodeN (Binary crx src1)));
6824 predicate(false);
6826 ins_variable_size_depending_on_alignment(true);
6828 format %{ "BEQ $crx, done\n\t"
6829 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6830 "done:" %}
6831 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6832 ins_encode %{
6833 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6834 Label done;
6835 __ beq($crx$$CondRegister, done);
6836 __ add($dst$$Register, $src1$$Register, R30);
6837 // TODO PPC port __ endgroup_if_needed(_size == 12);
6838 __ bind(done);
6839 %}
6840 ins_pipe(pipe_class_default);
6841 %}
6843 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6844 // The match rule is needed to make it a 'MachTypeNode'!
6845 // NOTICE that the rule is nonsense - we just have to make sure that:
6846 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6847 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6848 match(Set dst (DecodeN (Binary crx src1)));
6849 predicate(false);
6851 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6852 size(4);
6853 ins_encode %{
6854 // This is a Power7 instruction for which no machine description exists.
6855 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6856 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6857 %}
6858 ins_pipe(pipe_class_default);
6859 %}
6861 // shift != 0, base != 0
6862 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6863 match(Set dst (DecodeN src));
6864 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6865 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6866 Universe::narrow_oop_shift() != 0 &&
6867 Universe::narrow_oop_base() != 0);
6868 effect(TEMP crx);
6870 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6871 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6872 %}
6874 // shift != 0, base == 0
6875 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6876 match(Set dst (DecodeN src));
6877 predicate(Universe::narrow_oop_shift() != 0 &&
6878 Universe::narrow_oop_base() == 0);
6880 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6881 size(4);
6882 ins_encode %{
6883 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6884 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6885 %}
6886 ins_pipe(pipe_class_default);
6887 %}
6889 // src != 0, shift != 0, base != 0
6890 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6891 match(Set dst (DecodeN src));
6892 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6893 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6894 Universe::narrow_oop_shift() != 0 &&
6895 Universe::narrow_oop_base() != 0);
6897 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6898 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6899 %}
6901 // Compressed OOPs with narrow_oop_shift == 0.
6902 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6903 match(Set dst (DecodeN src));
6904 predicate(Universe::narrow_oop_shift() == 0);
6905 ins_cost(DEFAULT_COST);
6907 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6908 // variable size, 0 or 4.
6909 ins_encode %{
6910 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6911 __ mr_if_needed($dst$$Register, $src$$Register);
6912 %}
6913 ins_pipe(pipe_class_default);
6914 %}
6916 // Convert compressed oop into int for vectors alignment masking.
6917 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6918 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6919 predicate(Universe::narrow_oop_shift() == 0);
6920 ins_cost(DEFAULT_COST);
6922 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6923 // variable size, 0 or 4.
6924 ins_encode %{
6925 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6926 __ mr_if_needed($dst$$Register, $src$$Register);
6927 %}
6928 ins_pipe(pipe_class_default);
6929 %}
6931 // Convert klass pointer into compressed form.
6933 // Nodes for postalloc expand.
6935 // Shift node for expand.
6936 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6937 // The match rule is needed to make it a 'MachTypeNode'!
6938 match(Set dst (EncodePKlass src));
6939 predicate(false);
6941 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6942 size(4);
6943 ins_encode %{
6944 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6945 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6946 %}
6947 ins_pipe(pipe_class_default);
6948 %}
6950 // Add node for expand.
6951 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6952 // The match rule is needed to make it a 'MachTypeNode'!
6953 match(Set dst (EncodePKlass (Binary base src)));
6954 predicate(false);
6956 format %{ "SUB $dst, $base, $src \t// encode" %}
6957 size(4);
6958 ins_encode %{
6959 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6960 __ subf($dst$$Register, $base$$Register, $src$$Register);
6961 %}
6962 ins_pipe(pipe_class_default);
6963 %}
6965 // base != 0
6966 // 32G aligned narrow oop base.
6967 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6968 match(Set dst (EncodePKlass src));
6969 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6971 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6972 size(4);
6973 ins_encode %{
6974 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6975 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6976 %}
6977 ins_pipe(pipe_class_default);
6978 %}
6980 // shift != 0, base != 0
6981 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6982 match(Set dst (EncodePKlass (Binary base src)));
6983 predicate(false);
6985 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6986 postalloc_expand %{
6987 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
6988 n1->add_req(n_region, n_base, n_src);
6989 n1->_opnds[0] = op_dst;
6990 n1->_opnds[1] = op_base;
6991 n1->_opnds[2] = op_src;
6992 n1->_bottom_type = _bottom_type;
6994 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
6995 n2->add_req(n_region, n1);
6996 n2->_opnds[0] = op_dst;
6997 n2->_opnds[1] = op_dst;
6998 n2->_bottom_type = _bottom_type;
6999 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7000 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7002 nodes->push(n1);
7003 nodes->push(n2);
7004 %}
7005 %}
7007 // shift != 0, base != 0
7008 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7009 match(Set dst (EncodePKlass src));
7010 //predicate(Universe::narrow_klass_shift() != 0 &&
7011 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7013 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7014 ins_cost(DEFAULT_COST*2); // Don't count constant.
7015 expand %{
7016 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7017 iRegLdst base;
7018 loadConL_Ex(base, baseImm);
7019 encodePKlass_not_null_Ex(dst, base, src);
7020 %}
7021 %}
7023 // Decode nodes.
7025 // Shift node for expand.
7026 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7027 // The match rule is needed to make it a 'MachTypeNode'!
7028 match(Set dst (DecodeNKlass src));
7029 predicate(false);
7031 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7032 size(4);
7033 ins_encode %{
7034 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7035 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7036 %}
7037 ins_pipe(pipe_class_default);
7038 %}
7040 // Add node for expand.
7042 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7043 // The match rule is needed to make it a 'MachTypeNode'!
7044 match(Set dst (DecodeNKlass (Binary base src)));
7045 predicate(false);
7047 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7048 size(4);
7049 ins_encode %{
7050 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7051 __ add($dst$$Register, $base$$Register, $src$$Register);
7052 %}
7053 ins_pipe(pipe_class_default);
7054 %}
7056 // src != 0, shift != 0, base != 0
7057 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7058 match(Set dst (DecodeNKlass (Binary base src)));
7059 //effect(kill src); // We need a register for the immediate result after shifting.
7060 predicate(false);
7062 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7063 postalloc_expand %{
7064 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7065 n1->add_req(n_region, n_base, n_src);
7066 n1->_opnds[0] = op_dst;
7067 n1->_opnds[1] = op_base;
7068 n1->_opnds[2] = op_src;
7069 n1->_bottom_type = _bottom_type;
7071 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7072 n2->add_req(n_region, n1);
7073 n2->_opnds[0] = op_dst;
7074 n2->_opnds[1] = op_dst;
7075 n2->_bottom_type = _bottom_type;
7077 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7078 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7080 nodes->push(n1);
7081 nodes->push(n2);
7082 %}
7083 %}
7085 // src != 0, shift != 0, base != 0
7086 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7087 match(Set dst (DecodeNKlass src));
7088 // predicate(Universe::narrow_klass_shift() != 0 &&
7089 // Universe::narrow_klass_base() != 0);
7091 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7093 ins_cost(DEFAULT_COST*2); // Don't count constant.
7094 expand %{
7095 // We add first, then we shift. Like this, we can get along with one register less.
7096 // But we have to load the base pre-shifted.
7097 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7098 iRegLdst base;
7099 loadConL_Ex(base, baseImm);
7100 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7101 %}
7102 %}
7104 //----------MemBar Instructions-----------------------------------------------
7105 // Memory barrier flavors
7107 instruct membar_acquire() %{
7108 match(LoadFence);
7109 ins_cost(4*MEMORY_REF_COST);
7111 format %{ "MEMBAR-acquire" %}
7112 size(4);
7113 ins_encode %{
7114 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7115 __ acquire();
7116 %}
7117 ins_pipe(pipe_class_default);
7118 %}
7120 instruct unnecessary_membar_acquire() %{
7121 match(MemBarAcquire);
7122 ins_cost(0);
7124 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7125 size(0);
7126 ins_encode( /*empty*/ );
7127 ins_pipe(pipe_class_default);
7128 %}
7130 instruct membar_acquire_lock() %{
7131 match(MemBarAcquireLock);
7132 ins_cost(0);
7134 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7135 size(0);
7136 ins_encode( /*empty*/ );
7137 ins_pipe(pipe_class_default);
7138 %}
7140 instruct membar_release() %{
7141 match(MemBarRelease);
7142 match(StoreFence);
7143 ins_cost(4*MEMORY_REF_COST);
7145 format %{ "MEMBAR-release" %}
7146 size(4);
7147 ins_encode %{
7148 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7149 __ release();
7150 %}
7151 ins_pipe(pipe_class_default);
7152 %}
7154 instruct membar_storestore() %{
7155 match(MemBarStoreStore);
7156 ins_cost(4*MEMORY_REF_COST);
7158 format %{ "MEMBAR-store-store" %}
7159 size(4);
7160 ins_encode %{
7161 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7162 __ membar(Assembler::StoreStore);
7163 %}
7164 ins_pipe(pipe_class_default);
7165 %}
7167 instruct membar_release_lock() %{
7168 match(MemBarReleaseLock);
7169 ins_cost(0);
7171 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7172 size(0);
7173 ins_encode( /*empty*/ );
7174 ins_pipe(pipe_class_default);
7175 %}
7177 instruct membar_volatile() %{
7178 match(MemBarVolatile);
7179 ins_cost(4*MEMORY_REF_COST);
7181 format %{ "MEMBAR-volatile" %}
7182 size(4);
7183 ins_encode %{
7184 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7185 __ fence();
7186 %}
7187 ins_pipe(pipe_class_default);
7188 %}
7190 // This optimization is wrong on PPC. The following pattern is not supported:
7191 // MemBarVolatile
7192 // ^ ^
7193 // | |
7194 // CtrlProj MemProj
7195 // ^ ^
7196 // | |
7197 // | Load
7198 // |
7199 // MemBarVolatile
7200 //
7201 // The first MemBarVolatile could get optimized out! According to
7202 // Vladimir, this pattern can not occur on Oracle platforms.
7203 // However, it does occur on PPC64 (because of membars in
7204 // inline_unsafe_load_store).
7205 //
7206 // Add this node again if we found a good solution for inline_unsafe_load_store().
7207 // Don't forget to look at the implementation of post_store_load_barrier again,
7208 // we did other fixes in that method.
7209 //instruct unnecessary_membar_volatile() %{
7210 // match(MemBarVolatile);
7211 // predicate(Matcher::post_store_load_barrier(n));
7212 // ins_cost(0);
7213 //
7214 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7215 // size(0);
7216 // ins_encode( /*empty*/ );
7217 // ins_pipe(pipe_class_default);
7218 //%}
7220 instruct membar_CPUOrder() %{
7221 match(MemBarCPUOrder);
7222 ins_cost(0);
7224 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7225 size(0);
7226 ins_encode( /*empty*/ );
7227 ins_pipe(pipe_class_default);
7228 %}
7230 //----------Conditional Move---------------------------------------------------
7232 // Cmove using isel.
7233 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7234 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7235 predicate(VM_Version::has_isel());
7236 ins_cost(DEFAULT_COST);
7238 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7239 size(4);
7240 ins_encode %{
7241 // This is a Power7 instruction for which no machine description
7242 // exists. Anyways, the scheduler should be off on Power7.
7243 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7244 int cc = $cmp$$cmpcode;
7245 __ isel($dst$$Register, $crx$$CondRegister,
7246 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7247 %}
7248 ins_pipe(pipe_class_default);
7249 %}
7251 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7252 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7253 predicate(!VM_Version::has_isel());
7254 ins_cost(DEFAULT_COST+BRANCH_COST);
7256 ins_variable_size_depending_on_alignment(true);
7258 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7259 // Worst case is branch + move + stop, no stop without scheduler
7260 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7261 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7262 ins_pipe(pipe_class_default);
7263 %}
7265 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7266 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7267 ins_cost(DEFAULT_COST+BRANCH_COST);
7269 ins_variable_size_depending_on_alignment(true);
7271 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7272 // Worst case is branch + move + stop, no stop without scheduler
7273 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7274 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7275 ins_pipe(pipe_class_default);
7276 %}
7278 // Cmove using isel.
7279 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7280 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7281 predicate(VM_Version::has_isel());
7282 ins_cost(DEFAULT_COST);
7284 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7285 size(4);
7286 ins_encode %{
7287 // This is a Power7 instruction for which no machine description
7288 // exists. Anyways, the scheduler should be off on Power7.
7289 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7290 int cc = $cmp$$cmpcode;
7291 __ isel($dst$$Register, $crx$$CondRegister,
7292 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7293 %}
7294 ins_pipe(pipe_class_default);
7295 %}
7297 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7298 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7299 predicate(!VM_Version::has_isel());
7300 ins_cost(DEFAULT_COST+BRANCH_COST);
7302 ins_variable_size_depending_on_alignment(true);
7304 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7305 // Worst case is branch + move + stop, no stop without scheduler.
7306 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7307 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7308 ins_pipe(pipe_class_default);
7309 %}
7311 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7312 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7313 ins_cost(DEFAULT_COST+BRANCH_COST);
7315 ins_variable_size_depending_on_alignment(true);
7317 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7318 // Worst case is branch + move + stop, no stop without scheduler.
7319 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7320 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7321 ins_pipe(pipe_class_default);
7322 %}
7324 // Cmove using isel.
7325 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7326 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7327 predicate(VM_Version::has_isel());
7328 ins_cost(DEFAULT_COST);
7330 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7331 size(4);
7332 ins_encode %{
7333 // This is a Power7 instruction for which no machine description
7334 // exists. Anyways, the scheduler should be off on Power7.
7335 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7336 int cc = $cmp$$cmpcode;
7337 __ isel($dst$$Register, $crx$$CondRegister,
7338 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7339 %}
7340 ins_pipe(pipe_class_default);
7341 %}
7343 // Conditional move for RegN. Only cmov(reg, reg).
7344 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7345 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7346 predicate(!VM_Version::has_isel());
7347 ins_cost(DEFAULT_COST+BRANCH_COST);
7349 ins_variable_size_depending_on_alignment(true);
7351 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7352 // Worst case is branch + move + stop, no stop without scheduler.
7353 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7354 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7355 ins_pipe(pipe_class_default);
7356 %}
7358 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7359 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7360 ins_cost(DEFAULT_COST+BRANCH_COST);
7362 ins_variable_size_depending_on_alignment(true);
7364 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7365 // Worst case is branch + move + stop, no stop without scheduler.
7366 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7367 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7368 ins_pipe(pipe_class_default);
7369 %}
7371 // Cmove using isel.
7372 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7373 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7374 predicate(VM_Version::has_isel());
7375 ins_cost(DEFAULT_COST);
7377 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7378 size(4);
7379 ins_encode %{
7380 // This is a Power7 instruction for which no machine description
7381 // exists. Anyways, the scheduler should be off on Power7.
7382 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7383 int cc = $cmp$$cmpcode;
7384 __ isel($dst$$Register, $crx$$CondRegister,
7385 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7386 %}
7387 ins_pipe(pipe_class_default);
7388 %}
7390 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7391 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7392 predicate(!VM_Version::has_isel());
7393 ins_cost(DEFAULT_COST+BRANCH_COST);
7395 ins_variable_size_depending_on_alignment(true);
7397 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7398 // Worst case is branch + move + stop, no stop without scheduler.
7399 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7400 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7401 ins_pipe(pipe_class_default);
7402 %}
7404 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7405 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7406 ins_cost(DEFAULT_COST+BRANCH_COST);
7408 ins_variable_size_depending_on_alignment(true);
7410 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7411 // Worst case is branch + move + stop, no stop without scheduler.
7412 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7413 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7414 ins_pipe(pipe_class_default);
7415 %}
7417 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7418 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7419 ins_cost(DEFAULT_COST+BRANCH_COST);
7421 ins_variable_size_depending_on_alignment(true);
7423 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7424 // Worst case is branch + move + stop, no stop without scheduler.
7425 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7426 ins_encode %{
7427 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7428 Label done;
7429 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7430 // Branch if not (cmp crx).
7431 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7432 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7433 // TODO PPC port __ endgroup_if_needed(_size == 12);
7434 __ bind(done);
7435 %}
7436 ins_pipe(pipe_class_default);
7437 %}
7439 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7440 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7441 ins_cost(DEFAULT_COST+BRANCH_COST);
7443 ins_variable_size_depending_on_alignment(true);
7445 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7446 // Worst case is branch + move + stop, no stop without scheduler.
7447 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7448 ins_encode %{
7449 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7450 Label done;
7451 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7452 // Branch if not (cmp crx).
7453 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7454 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7455 // TODO PPC port __ endgroup_if_needed(_size == 12);
7456 __ bind(done);
7457 %}
7458 ins_pipe(pipe_class_default);
7459 %}
7461 //----------Conditional_store--------------------------------------------------
7462 // Conditional-store of the updated heap-top.
7463 // Used during allocation of the shared heap.
7464 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7466 // As compareAndSwapL, but return flag register instead of boolean value in
7467 // int register.
7468 // Used by sun/misc/AtomicLongCSImpl.java.
7469 // Mem_ptr must be a memory operand, else this node does not get
7470 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7471 // can be rematerialized which leads to errors.
7472 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7473 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7474 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7475 ins_encode %{
7476 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7477 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7478 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7479 noreg, NULL, true);
7480 %}
7481 ins_pipe(pipe_class_default);
7482 %}
7484 // As compareAndSwapP, but return flag register instead of boolean value in
7485 // int register.
7486 // This instruction is matched if UseTLAB is off.
7487 // Mem_ptr must be a memory operand, else this node does not get
7488 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7489 // can be rematerialized which leads to errors.
7490 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7491 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7492 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7493 ins_encode %{
7494 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7495 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7496 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7497 noreg, NULL, true);
7498 %}
7499 ins_pipe(pipe_class_default);
7500 %}
7502 // Implement LoadPLocked. Must be ordered against changes of the memory location
7503 // by storePConditional.
7504 // Don't know whether this is ever used.
7505 instruct loadPLocked(iRegPdst dst, memory mem) %{
7506 match(Set dst (LoadPLocked mem));
7507 ins_cost(MEMORY_REF_COST);
7509 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7510 "TWI $dst\n\t"
7511 "ISYNC" %}
7512 size(12);
7513 ins_encode( enc_ld_ac(dst, mem) );
7514 ins_pipe(pipe_class_memory);
7515 %}
7517 //----------Compare-And-Swap---------------------------------------------------
7519 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7520 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7521 // matched.
7523 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7524 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7525 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7526 // Variable size: instruction count smaller if regs are disjoint.
7527 ins_encode %{
7528 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7529 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7530 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7531 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7532 $res$$Register, true);
7533 %}
7534 ins_pipe(pipe_class_default);
7535 %}
7537 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7538 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7539 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7540 // Variable size: instruction count smaller if regs are disjoint.
7541 ins_encode %{
7542 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7543 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7544 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7545 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7546 $res$$Register, true);
7547 %}
7548 ins_pipe(pipe_class_default);
7549 %}
7551 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7552 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7553 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7554 // Variable size: instruction count smaller if regs are disjoint.
7555 ins_encode %{
7556 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7557 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7558 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7559 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7560 $res$$Register, NULL, true);
7561 %}
7562 ins_pipe(pipe_class_default);
7563 %}
7565 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7566 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7567 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7568 // Variable size: instruction count smaller if regs are disjoint.
7569 ins_encode %{
7570 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7571 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7572 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7573 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7574 $res$$Register, NULL, true);
7575 %}
7576 ins_pipe(pipe_class_default);
7577 %}
7579 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7580 match(Set res (GetAndAddI mem_ptr src));
7581 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7582 // Variable size: instruction count smaller if regs are disjoint.
7583 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7584 ins_pipe(pipe_class_default);
7585 %}
7587 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7588 match(Set res (GetAndAddL mem_ptr src));
7589 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7590 // Variable size: instruction count smaller if regs are disjoint.
7591 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7592 ins_pipe(pipe_class_default);
7593 %}
7595 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7596 match(Set res (GetAndSetI mem_ptr src));
7597 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7598 // Variable size: instruction count smaller if regs are disjoint.
7599 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7600 ins_pipe(pipe_class_default);
7601 %}
7603 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7604 match(Set res (GetAndSetL mem_ptr src));
7605 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7606 // Variable size: instruction count smaller if regs are disjoint.
7607 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7608 ins_pipe(pipe_class_default);
7609 %}
7611 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7612 match(Set res (GetAndSetP mem_ptr src));
7613 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7614 // Variable size: instruction count smaller if regs are disjoint.
7615 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7616 ins_pipe(pipe_class_default);
7617 %}
7619 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7620 match(Set res (GetAndSetN mem_ptr src));
7621 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7622 // Variable size: instruction count smaller if regs are disjoint.
7623 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7624 ins_pipe(pipe_class_default);
7625 %}
7627 //----------Arithmetic Instructions--------------------------------------------
7628 // Addition Instructions
7630 // Register Addition
7631 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7632 match(Set dst (AddI src1 src2));
7633 format %{ "ADD $dst, $src1, $src2" %}
7634 size(4);
7635 ins_encode %{
7636 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7637 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7638 %}
7639 ins_pipe(pipe_class_default);
7640 %}
7642 // Expand does not work with above instruct. (??)
7643 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7644 // no match-rule
7645 effect(DEF dst, USE src1, USE src2);
7646 format %{ "ADD $dst, $src1, $src2" %}
7647 size(4);
7648 ins_encode %{
7649 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7650 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7651 %}
7652 ins_pipe(pipe_class_default);
7653 %}
7655 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7656 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7657 ins_cost(DEFAULT_COST*3);
7659 expand %{
7660 // FIXME: we should do this in the ideal world.
7661 iRegIdst tmp1;
7662 iRegIdst tmp2;
7663 addI_reg_reg(tmp1, src1, src2);
7664 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7665 addI_reg_reg(dst, tmp1, tmp2);
7666 %}
7667 %}
7669 // Immediate Addition
7670 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7671 match(Set dst (AddI src1 src2));
7672 format %{ "ADDI $dst, $src1, $src2" %}
7673 size(4);
7674 ins_encode %{
7675 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7676 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7677 %}
7678 ins_pipe(pipe_class_default);
7679 %}
7681 // Immediate Addition with 16-bit shifted operand
7682 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7683 match(Set dst (AddI src1 src2));
7684 format %{ "ADDIS $dst, $src1, $src2" %}
7685 size(4);
7686 ins_encode %{
7687 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7688 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7689 %}
7690 ins_pipe(pipe_class_default);
7691 %}
7693 // Long Addition
7694 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7695 match(Set dst (AddL src1 src2));
7696 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7697 size(4);
7698 ins_encode %{
7699 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7700 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7701 %}
7702 ins_pipe(pipe_class_default);
7703 %}
7705 // Expand does not work with above instruct. (??)
7706 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7707 // no match-rule
7708 effect(DEF dst, USE src1, USE src2);
7709 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7710 size(4);
7711 ins_encode %{
7712 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7713 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7714 %}
7715 ins_pipe(pipe_class_default);
7716 %}
7718 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7719 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7720 ins_cost(DEFAULT_COST*3);
7722 expand %{
7723 // FIXME: we should do this in the ideal world.
7724 iRegLdst tmp1;
7725 iRegLdst tmp2;
7726 addL_reg_reg(tmp1, src1, src2);
7727 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7728 addL_reg_reg(dst, tmp1, tmp2);
7729 %}
7730 %}
7732 // AddL + ConvL2I.
7733 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7734 match(Set dst (ConvL2I (AddL src1 src2)));
7736 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7737 size(4);
7738 ins_encode %{
7739 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7740 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7741 %}
7742 ins_pipe(pipe_class_default);
7743 %}
7745 // No constant pool entries required.
7746 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7747 match(Set dst (AddL src1 src2));
7749 format %{ "ADDI $dst, $src1, $src2" %}
7750 size(4);
7751 ins_encode %{
7752 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7753 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7754 %}
7755 ins_pipe(pipe_class_default);
7756 %}
7758 // Long Immediate Addition with 16-bit shifted operand.
7759 // No constant pool entries required.
7760 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7761 match(Set dst (AddL src1 src2));
7763 format %{ "ADDIS $dst, $src1, $src2" %}
7764 size(4);
7765 ins_encode %{
7766 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7767 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7768 %}
7769 ins_pipe(pipe_class_default);
7770 %}
7772 // Pointer Register Addition
7773 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7774 match(Set dst (AddP src1 src2));
7775 format %{ "ADD $dst, $src1, $src2" %}
7776 size(4);
7777 ins_encode %{
7778 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7779 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7780 %}
7781 ins_pipe(pipe_class_default);
7782 %}
7784 // Pointer Immediate Addition
7785 // No constant pool entries required.
7786 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7787 match(Set dst (AddP src1 src2));
7789 format %{ "ADDI $dst, $src1, $src2" %}
7790 size(4);
7791 ins_encode %{
7792 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7793 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7794 %}
7795 ins_pipe(pipe_class_default);
7796 %}
7798 // Pointer Immediate Addition with 16-bit shifted operand.
7799 // No constant pool entries required.
7800 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7801 match(Set dst (AddP src1 src2));
7803 format %{ "ADDIS $dst, $src1, $src2" %}
7804 size(4);
7805 ins_encode %{
7806 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7807 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7808 %}
7809 ins_pipe(pipe_class_default);
7810 %}
7812 //---------------------
7813 // Subtraction Instructions
7815 // Register Subtraction
7816 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7817 match(Set dst (SubI src1 src2));
7818 format %{ "SUBF $dst, $src2, $src1" %}
7819 size(4);
7820 ins_encode %{
7821 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7822 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7823 %}
7824 ins_pipe(pipe_class_default);
7825 %}
7827 // Immediate Subtraction
7828 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7829 // so this rule seems to be unused.
7830 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7831 match(Set dst (SubI src1 src2));
7832 format %{ "SUBI $dst, $src1, $src2" %}
7833 size(4);
7834 ins_encode %{
7835 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7836 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7837 %}
7838 ins_pipe(pipe_class_default);
7839 %}
7841 // SubI from constant (using subfic).
7842 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7843 match(Set dst (SubI src1 src2));
7844 format %{ "SUBI $dst, $src1, $src2" %}
7846 size(4);
7847 ins_encode %{
7848 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7849 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7850 %}
7851 ins_pipe(pipe_class_default);
7852 %}
7854 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7855 // positive integers and 0xF...F for negative ones.
7856 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7857 // no match-rule, false predicate
7858 effect(DEF dst, USE src);
7859 predicate(false);
7861 format %{ "SRAWI $dst, $src, #31" %}
7862 size(4);
7863 ins_encode %{
7864 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7865 __ srawi($dst$$Register, $src$$Register, 0x1f);
7866 %}
7867 ins_pipe(pipe_class_default);
7868 %}
7870 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7871 match(Set dst (AbsI src));
7872 ins_cost(DEFAULT_COST*3);
7874 expand %{
7875 iRegIdst tmp1;
7876 iRegIdst tmp2;
7877 signmask32I_regI(tmp1, src);
7878 xorI_reg_reg(tmp2, tmp1, src);
7879 subI_reg_reg(dst, tmp2, tmp1);
7880 %}
7881 %}
7883 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7884 match(Set dst (SubI zero src2));
7885 format %{ "NEG $dst, $src2" %}
7886 size(4);
7887 ins_encode %{
7888 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7889 __ neg($dst$$Register, $src2$$Register);
7890 %}
7891 ins_pipe(pipe_class_default);
7892 %}
7894 // Long subtraction
7895 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7896 match(Set dst (SubL src1 src2));
7897 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7898 size(4);
7899 ins_encode %{
7900 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7901 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7902 %}
7903 ins_pipe(pipe_class_default);
7904 %}
7906 // SubL + convL2I.
7907 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7908 match(Set dst (ConvL2I (SubL src1 src2)));
7910 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7911 size(4);
7912 ins_encode %{
7913 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7914 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7915 %}
7916 ins_pipe(pipe_class_default);
7917 %}
7919 // Immediate Subtraction
7920 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7921 // so this rule seems to be unused.
7922 // No constant pool entries required.
7923 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7924 match(Set dst (SubL src1 src2));
7926 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7927 size(4);
7928 ins_encode %{
7929 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7930 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7931 %}
7932 ins_pipe(pipe_class_default);
7933 %}
7935 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7936 // positive longs and 0xF...F for negative ones.
7937 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7938 // no match-rule, false predicate
7939 effect(DEF dst, USE src);
7940 predicate(false);
7942 format %{ "SRADI $dst, $src, #63" %}
7943 size(4);
7944 ins_encode %{
7945 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7946 __ sradi($dst$$Register, $src$$Register, 0x3f);
7947 %}
7948 ins_pipe(pipe_class_default);
7949 %}
7951 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7952 // positive longs and 0xF...F for negative ones.
7953 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7954 // no match-rule, false predicate
7955 effect(DEF dst, USE src);
7956 predicate(false);
7958 format %{ "SRADI $dst, $src, #63" %}
7959 size(4);
7960 ins_encode %{
7961 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7962 __ sradi($dst$$Register, $src$$Register, 0x3f);
7963 %}
7964 ins_pipe(pipe_class_default);
7965 %}
7967 // Long negation
7968 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7969 match(Set dst (SubL zero src2));
7970 format %{ "NEG $dst, $src2 \t// long" %}
7971 size(4);
7972 ins_encode %{
7973 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7974 __ neg($dst$$Register, $src2$$Register);
7975 %}
7976 ins_pipe(pipe_class_default);
7977 %}
7979 // NegL + ConvL2I.
7980 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7981 match(Set dst (ConvL2I (SubL zero src2)));
7983 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7984 size(4);
7985 ins_encode %{
7986 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7987 __ neg($dst$$Register, $src2$$Register);
7988 %}
7989 ins_pipe(pipe_class_default);
7990 %}
7992 // Multiplication Instructions
7993 // Integer Multiplication
7995 // Register Multiplication
7996 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7997 match(Set dst (MulI src1 src2));
7998 ins_cost(DEFAULT_COST);
8000 format %{ "MULLW $dst, $src1, $src2" %}
8001 size(4);
8002 ins_encode %{
8003 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8004 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8005 %}
8006 ins_pipe(pipe_class_default);
8007 %}
8009 // Immediate Multiplication
8010 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8011 match(Set dst (MulI src1 src2));
8012 ins_cost(DEFAULT_COST);
8014 format %{ "MULLI $dst, $src1, $src2" %}
8015 size(4);
8016 ins_encode %{
8017 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8018 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8019 %}
8020 ins_pipe(pipe_class_default);
8021 %}
8023 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8024 match(Set dst (MulL src1 src2));
8025 ins_cost(DEFAULT_COST);
8027 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8028 size(4);
8029 ins_encode %{
8030 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8031 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8032 %}
8033 ins_pipe(pipe_class_default);
8034 %}
8036 // Multiply high for optimized long division by constant.
8037 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8038 match(Set dst (MulHiL src1 src2));
8039 ins_cost(DEFAULT_COST);
8041 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8042 size(4);
8043 ins_encode %{
8044 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8045 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8046 %}
8047 ins_pipe(pipe_class_default);
8048 %}
8050 // Immediate Multiplication
8051 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8052 match(Set dst (MulL src1 src2));
8053 ins_cost(DEFAULT_COST);
8055 format %{ "MULLI $dst, $src1, $src2" %}
8056 size(4);
8057 ins_encode %{
8058 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8059 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8060 %}
8061 ins_pipe(pipe_class_default);
8062 %}
8064 // Integer Division with Immediate -1: Negate.
8065 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8066 match(Set dst (DivI src1 src2));
8067 ins_cost(DEFAULT_COST);
8069 format %{ "NEG $dst, $src1 \t// /-1" %}
8070 size(4);
8071 ins_encode %{
8072 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8073 __ neg($dst$$Register, $src1$$Register);
8074 %}
8075 ins_pipe(pipe_class_default);
8076 %}
8078 // Integer Division with constant, but not -1.
8079 // We should be able to improve this by checking the type of src2.
8080 // It might well be that src2 is known to be positive.
8081 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8082 match(Set dst (DivI src1 src2));
8083 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8084 ins_cost(2*DEFAULT_COST);
8086 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8087 size(4);
8088 ins_encode %{
8089 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8090 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8091 %}
8092 ins_pipe(pipe_class_default);
8093 %}
8095 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8096 effect(USE_DEF dst, USE src1, USE crx);
8097 predicate(false);
8099 ins_variable_size_depending_on_alignment(true);
8101 format %{ "CMOVE $dst, neg($src1), $crx" %}
8102 // Worst case is branch + move + stop, no stop without scheduler.
8103 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8104 ins_encode %{
8105 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8106 Label done;
8107 __ bne($crx$$CondRegister, done);
8108 __ neg($dst$$Register, $src1$$Register);
8109 // TODO PPC port __ endgroup_if_needed(_size == 12);
8110 __ bind(done);
8111 %}
8112 ins_pipe(pipe_class_default);
8113 %}
8115 // Integer Division with Registers not containing constants.
8116 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8117 match(Set dst (DivI src1 src2));
8118 ins_cost(10*DEFAULT_COST);
8120 expand %{
8121 immI16 imm %{ (int)-1 %}
8122 flagsReg tmp1;
8123 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8124 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8125 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8126 %}
8127 %}
8129 // Long Division with Immediate -1: Negate.
8130 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8131 match(Set dst (DivL src1 src2));
8132 ins_cost(DEFAULT_COST);
8134 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8135 size(4);
8136 ins_encode %{
8137 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8138 __ neg($dst$$Register, $src1$$Register);
8139 %}
8140 ins_pipe(pipe_class_default);
8141 %}
8143 // Long Division with constant, but not -1.
8144 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8145 match(Set dst (DivL src1 src2));
8146 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8147 ins_cost(2*DEFAULT_COST);
8149 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8150 size(4);
8151 ins_encode %{
8152 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8153 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8154 %}
8155 ins_pipe(pipe_class_default);
8156 %}
8158 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8159 effect(USE_DEF dst, USE src1, USE crx);
8160 predicate(false);
8162 ins_variable_size_depending_on_alignment(true);
8164 format %{ "CMOVE $dst, neg($src1), $crx" %}
8165 // Worst case is branch + move + stop, no stop without scheduler.
8166 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8167 ins_encode %{
8168 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8169 Label done;
8170 __ bne($crx$$CondRegister, done);
8171 __ neg($dst$$Register, $src1$$Register);
8172 // TODO PPC port __ endgroup_if_needed(_size == 12);
8173 __ bind(done);
8174 %}
8175 ins_pipe(pipe_class_default);
8176 %}
8178 // Long Division with Registers not containing constants.
8179 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8180 match(Set dst (DivL src1 src2));
8181 ins_cost(10*DEFAULT_COST);
8183 expand %{
8184 immL16 imm %{ (int)-1 %}
8185 flagsReg tmp1;
8186 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8187 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8188 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8189 %}
8190 %}
8192 // Integer Remainder with registers.
8193 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8194 match(Set dst (ModI src1 src2));
8195 ins_cost(10*DEFAULT_COST);
8197 expand %{
8198 immI16 imm %{ (int)-1 %}
8199 flagsReg tmp1;
8200 iRegIdst tmp2;
8201 iRegIdst tmp3;
8202 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8203 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8204 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8205 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8206 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8207 %}
8208 %}
8210 // Long Remainder with registers
8211 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8212 match(Set dst (ModL src1 src2));
8213 ins_cost(10*DEFAULT_COST);
8215 expand %{
8216 immL16 imm %{ (int)-1 %}
8217 flagsReg tmp1;
8218 iRegLdst tmp2;
8219 iRegLdst tmp3;
8220 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8221 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8222 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8223 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8224 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8225 %}
8226 %}
8228 // Integer Shift Instructions
8230 // Register Shift Left
8232 // Clear all but the lowest #mask bits.
8233 // Used to normalize shift amounts in registers.
8234 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8235 // no match-rule, false predicate
8236 effect(DEF dst, USE src, USE mask);
8237 predicate(false);
8239 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8240 size(4);
8241 ins_encode %{
8242 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8243 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8244 %}
8245 ins_pipe(pipe_class_default);
8246 %}
8248 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8249 // no match-rule, false predicate
8250 effect(DEF dst, USE src1, USE src2);
8251 predicate(false);
8253 format %{ "SLW $dst, $src1, $src2" %}
8254 size(4);
8255 ins_encode %{
8256 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8257 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8258 %}
8259 ins_pipe(pipe_class_default);
8260 %}
8262 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8263 match(Set dst (LShiftI src1 src2));
8264 ins_cost(DEFAULT_COST*2);
8265 expand %{
8266 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8267 iRegIdst tmpI;
8268 maskI_reg_imm(tmpI, src2, mask);
8269 lShiftI_reg_reg(dst, src1, tmpI);
8270 %}
8271 %}
8273 // Register Shift Left Immediate
8274 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8275 match(Set dst (LShiftI src1 src2));
8277 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8278 size(4);
8279 ins_encode %{
8280 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8281 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8282 %}
8283 ins_pipe(pipe_class_default);
8284 %}
8286 // AndI with negpow2-constant + LShiftI
8287 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8288 match(Set dst (LShiftI (AndI src1 src2) src3));
8289 predicate(UseRotateAndMaskInstructionsPPC64);
8291 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8292 size(4);
8293 ins_encode %{
8294 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8295 long src2 = $src2$$constant;
8296 long src3 = $src3$$constant;
8297 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8298 if (maskbits >= 32) {
8299 __ li($dst$$Register, 0); // addi
8300 } else {
8301 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8302 }
8303 %}
8304 ins_pipe(pipe_class_default);
8305 %}
8307 // RShiftI + AndI with negpow2-constant + LShiftI
8308 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8309 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8310 predicate(UseRotateAndMaskInstructionsPPC64);
8312 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8313 size(4);
8314 ins_encode %{
8315 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8316 long src2 = $src2$$constant;
8317 long src3 = $src3$$constant;
8318 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8319 if (maskbits >= 32) {
8320 __ li($dst$$Register, 0); // addi
8321 } else {
8322 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8323 }
8324 %}
8325 ins_pipe(pipe_class_default);
8326 %}
8328 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8329 // no match-rule, false predicate
8330 effect(DEF dst, USE src1, USE src2);
8331 predicate(false);
8333 format %{ "SLD $dst, $src1, $src2" %}
8334 size(4);
8335 ins_encode %{
8336 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8337 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8338 %}
8339 ins_pipe(pipe_class_default);
8340 %}
8342 // Register Shift Left
8343 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8344 match(Set dst (LShiftL src1 src2));
8345 ins_cost(DEFAULT_COST*2);
8346 expand %{
8347 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8348 iRegIdst tmpI;
8349 maskI_reg_imm(tmpI, src2, mask);
8350 lShiftL_regL_regI(dst, src1, tmpI);
8351 %}
8352 %}
8354 // Register Shift Left Immediate
8355 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8356 match(Set dst (LShiftL src1 src2));
8357 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8358 size(4);
8359 ins_encode %{
8360 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8361 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8362 %}
8363 ins_pipe(pipe_class_default);
8364 %}
8366 // If we shift more than 32 bits, we need not convert I2L.
8367 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8368 match(Set dst (LShiftL (ConvI2L src1) src2));
8369 ins_cost(DEFAULT_COST);
8371 size(4);
8372 format %{ "SLDI $dst, i2l($src1), $src2" %}
8373 ins_encode %{
8374 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8375 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8376 %}
8377 ins_pipe(pipe_class_default);
8378 %}
8380 // Shift a postivie int to the left.
8381 // Clrlsldi clears the upper 32 bits and shifts.
8382 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8383 match(Set dst (LShiftL (ConvI2L src1) src2));
8384 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8386 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8387 size(4);
8388 ins_encode %{
8389 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8390 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8391 %}
8392 ins_pipe(pipe_class_default);
8393 %}
8395 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8396 // no match-rule, false predicate
8397 effect(DEF dst, USE src1, USE src2);
8398 predicate(false);
8400 format %{ "SRAW $dst, $src1, $src2" %}
8401 size(4);
8402 ins_encode %{
8403 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8404 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8405 %}
8406 ins_pipe(pipe_class_default);
8407 %}
8409 // Register Arithmetic Shift Right
8410 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8411 match(Set dst (RShiftI src1 src2));
8412 ins_cost(DEFAULT_COST*2);
8413 expand %{
8414 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8415 iRegIdst tmpI;
8416 maskI_reg_imm(tmpI, src2, mask);
8417 arShiftI_reg_reg(dst, src1, tmpI);
8418 %}
8419 %}
8421 // Register Arithmetic Shift Right Immediate
8422 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8423 match(Set dst (RShiftI src1 src2));
8425 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8426 size(4);
8427 ins_encode %{
8428 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8429 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8430 %}
8431 ins_pipe(pipe_class_default);
8432 %}
8434 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8435 // no match-rule, false predicate
8436 effect(DEF dst, USE src1, USE src2);
8437 predicate(false);
8439 format %{ "SRAD $dst, $src1, $src2" %}
8440 size(4);
8441 ins_encode %{
8442 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8443 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8444 %}
8445 ins_pipe(pipe_class_default);
8446 %}
8448 // Register Shift Right Arithmetic Long
8449 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8450 match(Set dst (RShiftL src1 src2));
8451 ins_cost(DEFAULT_COST*2);
8453 expand %{
8454 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8455 iRegIdst tmpI;
8456 maskI_reg_imm(tmpI, src2, mask);
8457 arShiftL_regL_regI(dst, src1, tmpI);
8458 %}
8459 %}
8461 // Register Shift Right Immediate
8462 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8463 match(Set dst (RShiftL src1 src2));
8465 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8466 size(4);
8467 ins_encode %{
8468 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8469 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8470 %}
8471 ins_pipe(pipe_class_default);
8472 %}
8474 // RShiftL + ConvL2I
8475 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8476 match(Set dst (ConvL2I (RShiftL src1 src2)));
8478 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8479 size(4);
8480 ins_encode %{
8481 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8482 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8483 %}
8484 ins_pipe(pipe_class_default);
8485 %}
8487 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8488 // no match-rule, false predicate
8489 effect(DEF dst, USE src1, USE src2);
8490 predicate(false);
8492 format %{ "SRW $dst, $src1, $src2" %}
8493 size(4);
8494 ins_encode %{
8495 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8496 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8497 %}
8498 ins_pipe(pipe_class_default);
8499 %}
8501 // Register Shift Right
8502 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8503 match(Set dst (URShiftI src1 src2));
8504 ins_cost(DEFAULT_COST*2);
8506 expand %{
8507 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8508 iRegIdst tmpI;
8509 maskI_reg_imm(tmpI, src2, mask);
8510 urShiftI_reg_reg(dst, src1, tmpI);
8511 %}
8512 %}
8514 // Register Shift Right Immediate
8515 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8516 match(Set dst (URShiftI src1 src2));
8518 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8519 size(4);
8520 ins_encode %{
8521 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8522 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8523 %}
8524 ins_pipe(pipe_class_default);
8525 %}
8527 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8528 // no match-rule, false predicate
8529 effect(DEF dst, USE src1, USE src2);
8530 predicate(false);
8532 format %{ "SRD $dst, $src1, $src2" %}
8533 size(4);
8534 ins_encode %{
8535 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8536 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8537 %}
8538 ins_pipe(pipe_class_default);
8539 %}
8541 // Register Shift Right
8542 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8543 match(Set dst (URShiftL src1 src2));
8544 ins_cost(DEFAULT_COST*2);
8546 expand %{
8547 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8548 iRegIdst tmpI;
8549 maskI_reg_imm(tmpI, src2, mask);
8550 urShiftL_regL_regI(dst, src1, tmpI);
8551 %}
8552 %}
8554 // Register Shift Right Immediate
8555 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8556 match(Set dst (URShiftL src1 src2));
8558 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8559 size(4);
8560 ins_encode %{
8561 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8562 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8563 %}
8564 ins_pipe(pipe_class_default);
8565 %}
8567 // URShiftL + ConvL2I.
8568 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8569 match(Set dst (ConvL2I (URShiftL src1 src2)));
8571 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8572 size(4);
8573 ins_encode %{
8574 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8575 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8576 %}
8577 ins_pipe(pipe_class_default);
8578 %}
8580 // Register Shift Right Immediate with a CastP2X
8581 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8582 match(Set dst (URShiftL (CastP2X src1) src2));
8584 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8585 size(4);
8586 ins_encode %{
8587 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8588 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8589 %}
8590 ins_pipe(pipe_class_default);
8591 %}
8593 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8594 match(Set dst (ConvL2I (ConvI2L src)));
8596 format %{ "EXTSW $dst, $src \t// int->int" %}
8597 size(4);
8598 ins_encode %{
8599 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8600 __ extsw($dst$$Register, $src$$Register);
8601 %}
8602 ins_pipe(pipe_class_default);
8603 %}
8605 //----------Rotate Instructions------------------------------------------------
8607 // Rotate Left by 8-bit immediate
8608 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8609 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8610 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8612 format %{ "ROTLWI $dst, $src, $lshift" %}
8613 size(4);
8614 ins_encode %{
8615 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8616 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8617 %}
8618 ins_pipe(pipe_class_default);
8619 %}
8621 // Rotate Right by 8-bit immediate
8622 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8623 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8624 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8626 format %{ "ROTRWI $dst, $rshift" %}
8627 size(4);
8628 ins_encode %{
8629 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8630 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8631 %}
8632 ins_pipe(pipe_class_default);
8633 %}
8635 //----------Floating Point Arithmetic Instructions-----------------------------
8637 // Add float single precision
8638 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8639 match(Set dst (AddF src1 src2));
8641 format %{ "FADDS $dst, $src1, $src2" %}
8642 size(4);
8643 ins_encode %{
8644 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8645 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8646 %}
8647 ins_pipe(pipe_class_default);
8648 %}
8650 // Add float double precision
8651 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8652 match(Set dst (AddD src1 src2));
8654 format %{ "FADD $dst, $src1, $src2" %}
8655 size(4);
8656 ins_encode %{
8657 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8658 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8659 %}
8660 ins_pipe(pipe_class_default);
8661 %}
8663 // Sub float single precision
8664 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8665 match(Set dst (SubF src1 src2));
8667 format %{ "FSUBS $dst, $src1, $src2" %}
8668 size(4);
8669 ins_encode %{
8670 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8671 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8672 %}
8673 ins_pipe(pipe_class_default);
8674 %}
8676 // Sub float double precision
8677 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8678 match(Set dst (SubD src1 src2));
8679 format %{ "FSUB $dst, $src1, $src2" %}
8680 size(4);
8681 ins_encode %{
8682 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8683 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8684 %}
8685 ins_pipe(pipe_class_default);
8686 %}
8688 // Mul float single precision
8689 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8690 match(Set dst (MulF src1 src2));
8691 format %{ "FMULS $dst, $src1, $src2" %}
8692 size(4);
8693 ins_encode %{
8694 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8695 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8696 %}
8697 ins_pipe(pipe_class_default);
8698 %}
8700 // Mul float double precision
8701 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8702 match(Set dst (MulD src1 src2));
8703 format %{ "FMUL $dst, $src1, $src2" %}
8704 size(4);
8705 ins_encode %{
8706 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8707 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8708 %}
8709 ins_pipe(pipe_class_default);
8710 %}
8712 // Div float single precision
8713 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8714 match(Set dst (DivF src1 src2));
8715 format %{ "FDIVS $dst, $src1, $src2" %}
8716 size(4);
8717 ins_encode %{
8718 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8719 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8720 %}
8721 ins_pipe(pipe_class_default);
8722 %}
8724 // Div float double precision
8725 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8726 match(Set dst (DivD src1 src2));
8727 format %{ "FDIV $dst, $src1, $src2" %}
8728 size(4);
8729 ins_encode %{
8730 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8731 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8732 %}
8733 ins_pipe(pipe_class_default);
8734 %}
8736 // Absolute float single precision
8737 instruct absF_reg(regF dst, regF src) %{
8738 match(Set dst (AbsF src));
8739 format %{ "FABS $dst, $src \t// float" %}
8740 size(4);
8741 ins_encode %{
8742 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8743 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8744 %}
8745 ins_pipe(pipe_class_default);
8746 %}
8748 // Absolute float double precision
8749 instruct absD_reg(regD dst, regD src) %{
8750 match(Set dst (AbsD src));
8751 format %{ "FABS $dst, $src \t// double" %}
8752 size(4);
8753 ins_encode %{
8754 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8755 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8756 %}
8757 ins_pipe(pipe_class_default);
8758 %}
8760 instruct negF_reg(regF dst, regF src) %{
8761 match(Set dst (NegF src));
8762 format %{ "FNEG $dst, $src \t// float" %}
8763 size(4);
8764 ins_encode %{
8765 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8766 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8767 %}
8768 ins_pipe(pipe_class_default);
8769 %}
8771 instruct negD_reg(regD dst, regD src) %{
8772 match(Set dst (NegD src));
8773 format %{ "FNEG $dst, $src \t// double" %}
8774 size(4);
8775 ins_encode %{
8776 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8777 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8778 %}
8779 ins_pipe(pipe_class_default);
8780 %}
8782 // AbsF + NegF.
8783 instruct negF_absF_reg(regF dst, regF src) %{
8784 match(Set dst (NegF (AbsF src)));
8785 format %{ "FNABS $dst, $src \t// float" %}
8786 size(4);
8787 ins_encode %{
8788 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8789 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8790 %}
8791 ins_pipe(pipe_class_default);
8792 %}
8794 // AbsD + NegD.
8795 instruct negD_absD_reg(regD dst, regD src) %{
8796 match(Set dst (NegD (AbsD src)));
8797 format %{ "FNABS $dst, $src \t// double" %}
8798 size(4);
8799 ins_encode %{
8800 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8801 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8802 %}
8803 ins_pipe(pipe_class_default);
8804 %}
8806 // VM_Version::has_fsqrt() decides if this node will be used.
8807 // Sqrt float double precision
8808 instruct sqrtD_reg(regD dst, regD src) %{
8809 match(Set dst (SqrtD src));
8810 format %{ "FSQRT $dst, $src" %}
8811 size(4);
8812 ins_encode %{
8813 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8814 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8815 %}
8816 ins_pipe(pipe_class_default);
8817 %}
8819 // Single-precision sqrt.
8820 instruct sqrtF_reg(regF dst, regF src) %{
8821 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8822 predicate(VM_Version::has_fsqrts());
8823 ins_cost(DEFAULT_COST);
8825 format %{ "FSQRTS $dst, $src" %}
8826 size(4);
8827 ins_encode %{
8828 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8829 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8830 %}
8831 ins_pipe(pipe_class_default);
8832 %}
8834 instruct roundDouble_nop(regD dst) %{
8835 match(Set dst (RoundDouble dst));
8836 ins_cost(0);
8838 format %{ " -- \t// RoundDouble not needed - empty" %}
8839 size(0);
8840 // PPC results are already "rounded" (i.e., normal-format IEEE).
8841 ins_encode( /*empty*/ );
8842 ins_pipe(pipe_class_default);
8843 %}
8845 instruct roundFloat_nop(regF dst) %{
8846 match(Set dst (RoundFloat dst));
8847 ins_cost(0);
8849 format %{ " -- \t// RoundFloat not needed - empty" %}
8850 size(0);
8851 // PPC results are already "rounded" (i.e., normal-format IEEE).
8852 ins_encode( /*empty*/ );
8853 ins_pipe(pipe_class_default);
8854 %}
8856 //----------Logical Instructions-----------------------------------------------
8858 // And Instructions
8860 // Register And
8861 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8862 match(Set dst (AndI src1 src2));
8863 format %{ "AND $dst, $src1, $src2" %}
8864 size(4);
8865 ins_encode %{
8866 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8867 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8868 %}
8869 ins_pipe(pipe_class_default);
8870 %}
8872 // Immediate And
8873 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8874 match(Set dst (AndI src1 src2));
8875 effect(KILL cr0);
8877 format %{ "ANDI $dst, $src1, $src2" %}
8878 size(4);
8879 ins_encode %{
8880 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8881 // FIXME: avoid andi_ ?
8882 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8883 %}
8884 ins_pipe(pipe_class_default);
8885 %}
8887 // Immediate And where the immediate is a negative power of 2.
8888 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8889 match(Set dst (AndI src1 src2));
8890 format %{ "ANDWI $dst, $src1, $src2" %}
8891 size(4);
8892 ins_encode %{
8893 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8894 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8895 %}
8896 ins_pipe(pipe_class_default);
8897 %}
8899 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8900 match(Set dst (AndI src1 src2));
8901 format %{ "ANDWI $dst, $src1, $src2" %}
8902 size(4);
8903 ins_encode %{
8904 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8905 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8906 %}
8907 ins_pipe(pipe_class_default);
8908 %}
8910 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8911 match(Set dst (AndI src1 src2));
8912 predicate(UseRotateAndMaskInstructionsPPC64);
8913 format %{ "ANDWI $dst, $src1, $src2" %}
8914 size(4);
8915 ins_encode %{
8916 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8917 __ rlwinm($dst$$Register, $src1$$Register, 0,
8918 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8919 %}
8920 ins_pipe(pipe_class_default);
8921 %}
8923 // Register And Long
8924 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8925 match(Set dst (AndL src1 src2));
8926 ins_cost(DEFAULT_COST);
8928 format %{ "AND $dst, $src1, $src2 \t// long" %}
8929 size(4);
8930 ins_encode %{
8931 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8932 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8933 %}
8934 ins_pipe(pipe_class_default);
8935 %}
8937 // Immediate And long
8938 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8939 match(Set dst (AndL src1 src2));
8940 effect(KILL cr0);
8941 ins_cost(DEFAULT_COST);
8943 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8944 size(4);
8945 ins_encode %{
8946 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8947 // FIXME: avoid andi_ ?
8948 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8949 %}
8950 ins_pipe(pipe_class_default);
8951 %}
8953 // Immediate And Long where the immediate is a negative power of 2.
8954 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8955 match(Set dst (AndL src1 src2));
8956 format %{ "ANDDI $dst, $src1, $src2" %}
8957 size(4);
8958 ins_encode %{
8959 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8960 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8961 %}
8962 ins_pipe(pipe_class_default);
8963 %}
8965 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8966 match(Set dst (AndL src1 src2));
8967 format %{ "ANDDI $dst, $src1, $src2" %}
8968 size(4);
8969 ins_encode %{
8970 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8971 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8972 %}
8973 ins_pipe(pipe_class_default);
8974 %}
8976 // AndL + ConvL2I.
8977 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8978 match(Set dst (ConvL2I (AndL src1 src2)));
8979 ins_cost(DEFAULT_COST);
8981 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8982 size(4);
8983 ins_encode %{
8984 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8985 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8986 %}
8987 ins_pipe(pipe_class_default);
8988 %}
8990 // Or Instructions
8992 // Register Or
8993 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8994 match(Set dst (OrI src1 src2));
8995 format %{ "OR $dst, $src1, $src2" %}
8996 size(4);
8997 ins_encode %{
8998 // TODO: PPC port $archOpcode(ppc64Opcode_or);
8999 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9000 %}
9001 ins_pipe(pipe_class_default);
9002 %}
9004 // Expand does not work with above instruct. (??)
9005 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9006 // no match-rule
9007 effect(DEF dst, USE src1, USE src2);
9008 format %{ "OR $dst, $src1, $src2" %}
9009 size(4);
9010 ins_encode %{
9011 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9012 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9013 %}
9014 ins_pipe(pipe_class_default);
9015 %}
9017 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9018 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9019 ins_cost(DEFAULT_COST*3);
9021 expand %{
9022 // FIXME: we should do this in the ideal world.
9023 iRegIdst tmp1;
9024 iRegIdst tmp2;
9025 orI_reg_reg(tmp1, src1, src2);
9026 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9027 orI_reg_reg(dst, tmp1, tmp2);
9028 %}
9029 %}
9031 // Immediate Or
9032 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9033 match(Set dst (OrI src1 src2));
9034 format %{ "ORI $dst, $src1, $src2" %}
9035 size(4);
9036 ins_encode %{
9037 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9038 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9039 %}
9040 ins_pipe(pipe_class_default);
9041 %}
9043 // Register Or Long
9044 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9045 match(Set dst (OrL src1 src2));
9046 ins_cost(DEFAULT_COST);
9048 size(4);
9049 format %{ "OR $dst, $src1, $src2 \t// long" %}
9050 ins_encode %{
9051 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9052 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9053 %}
9054 ins_pipe(pipe_class_default);
9055 %}
9057 // OrL + ConvL2I.
9058 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9059 match(Set dst (ConvL2I (OrL src1 src2)));
9060 ins_cost(DEFAULT_COST);
9062 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9063 size(4);
9064 ins_encode %{
9065 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9066 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9067 %}
9068 ins_pipe(pipe_class_default);
9069 %}
9071 // Immediate Or long
9072 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9073 match(Set dst (OrL src1 con));
9074 ins_cost(DEFAULT_COST);
9076 format %{ "ORI $dst, $src1, $con \t// long" %}
9077 size(4);
9078 ins_encode %{
9079 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9080 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9081 %}
9082 ins_pipe(pipe_class_default);
9083 %}
9085 // Xor Instructions
9087 // Register Xor
9088 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9089 match(Set dst (XorI src1 src2));
9090 format %{ "XOR $dst, $src1, $src2" %}
9091 size(4);
9092 ins_encode %{
9093 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9094 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9095 %}
9096 ins_pipe(pipe_class_default);
9097 %}
9099 // Expand does not work with above instruct. (??)
9100 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9101 // no match-rule
9102 effect(DEF dst, USE src1, USE src2);
9103 format %{ "XOR $dst, $src1, $src2" %}
9104 size(4);
9105 ins_encode %{
9106 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9107 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9108 %}
9109 ins_pipe(pipe_class_default);
9110 %}
9112 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9113 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9114 ins_cost(DEFAULT_COST*3);
9116 expand %{
9117 // FIXME: we should do this in the ideal world.
9118 iRegIdst tmp1;
9119 iRegIdst tmp2;
9120 xorI_reg_reg(tmp1, src1, src2);
9121 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9122 xorI_reg_reg(dst, tmp1, tmp2);
9123 %}
9124 %}
9126 // Immediate Xor
9127 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9128 match(Set dst (XorI src1 src2));
9129 format %{ "XORI $dst, $src1, $src2" %}
9130 size(4);
9131 ins_encode %{
9132 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9133 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9134 %}
9135 ins_pipe(pipe_class_default);
9136 %}
9138 // Register Xor Long
9139 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9140 match(Set dst (XorL src1 src2));
9141 ins_cost(DEFAULT_COST);
9143 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9144 size(4);
9145 ins_encode %{
9146 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9147 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9148 %}
9149 ins_pipe(pipe_class_default);
9150 %}
9152 // XorL + ConvL2I.
9153 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9154 match(Set dst (ConvL2I (XorL src1 src2)));
9155 ins_cost(DEFAULT_COST);
9157 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9158 size(4);
9159 ins_encode %{
9160 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9161 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9162 %}
9163 ins_pipe(pipe_class_default);
9164 %}
9166 // Immediate Xor Long
9167 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9168 match(Set dst (XorL src1 src2));
9169 ins_cost(DEFAULT_COST);
9171 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9172 size(4);
9173 ins_encode %{
9174 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9175 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9176 %}
9177 ins_pipe(pipe_class_default);
9178 %}
9180 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9181 match(Set dst (XorI src1 src2));
9182 ins_cost(DEFAULT_COST);
9184 format %{ "NOT $dst, $src1 ($src2)" %}
9185 size(4);
9186 ins_encode %{
9187 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9188 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9189 %}
9190 ins_pipe(pipe_class_default);
9191 %}
9193 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9194 match(Set dst (XorL src1 src2));
9195 ins_cost(DEFAULT_COST);
9197 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9198 size(4);
9199 ins_encode %{
9200 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9201 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9202 %}
9203 ins_pipe(pipe_class_default);
9204 %}
9206 // And-complement
9207 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9208 match(Set dst (AndI (XorI src1 src2) src3));
9209 ins_cost(DEFAULT_COST);
9211 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9212 size(4);
9213 ins_encode( enc_andc(dst, src3, src1) );
9214 ins_pipe(pipe_class_default);
9215 %}
9217 // And-complement
9218 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9219 // no match-rule, false predicate
9220 effect(DEF dst, USE src1, USE src2);
9221 predicate(false);
9223 format %{ "ANDC $dst, $src1, $src2" %}
9224 size(4);
9225 ins_encode %{
9226 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9227 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9228 %}
9229 ins_pipe(pipe_class_default);
9230 %}
9232 //----------Moves between int/long and float/double----------------------------
9233 //
9234 // The following rules move values from int/long registers/stack-locations
9235 // to float/double registers/stack-locations and vice versa, without doing any
9236 // conversions. These rules are used to implement the bit-conversion methods
9237 // of java.lang.Float etc., e.g.
9238 // int floatToIntBits(float value)
9239 // float intBitsToFloat(int bits)
9240 //
9241 // Notes on the implementation on ppc64:
9242 // We only provide rules which move between a register and a stack-location,
9243 // because we always have to go through memory when moving between a float
9244 // register and an integer register.
9246 //---------- Chain stack slots between similar types --------
9248 // These are needed so that the rules below can match.
9250 // Load integer from stack slot
9251 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9252 match(Set dst src);
9253 ins_cost(MEMORY_REF_COST);
9255 format %{ "LWZ $dst, $src" %}
9256 size(4);
9257 ins_encode( enc_lwz(dst, src) );
9258 ins_pipe(pipe_class_memory);
9259 %}
9261 // Store integer to stack slot
9262 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9263 match(Set dst src);
9264 ins_cost(MEMORY_REF_COST);
9266 format %{ "STW $src, $dst \t// stk" %}
9267 size(4);
9268 ins_encode( enc_stw(src, dst) ); // rs=rt
9269 ins_pipe(pipe_class_memory);
9270 %}
9272 // Load long from stack slot
9273 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9274 match(Set dst src);
9275 ins_cost(MEMORY_REF_COST);
9277 format %{ "LD $dst, $src \t// long" %}
9278 size(4);
9279 ins_encode( enc_ld(dst, src) );
9280 ins_pipe(pipe_class_memory);
9281 %}
9283 // Store long to stack slot
9284 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9285 match(Set dst src);
9286 ins_cost(MEMORY_REF_COST);
9288 format %{ "STD $src, $dst \t// long" %}
9289 size(4);
9290 ins_encode( enc_std(src, dst) ); // rs=rt
9291 ins_pipe(pipe_class_memory);
9292 %}
9294 //----------Moves between int and float
9296 // Move float value from float stack-location to integer register.
9297 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9298 match(Set dst (MoveF2I src));
9299 ins_cost(MEMORY_REF_COST);
9301 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9302 size(4);
9303 ins_encode( enc_lwz(dst, src) );
9304 ins_pipe(pipe_class_memory);
9305 %}
9307 // Move float value from float register to integer stack-location.
9308 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9309 match(Set dst (MoveF2I src));
9310 ins_cost(MEMORY_REF_COST);
9312 format %{ "STFS $src, $dst \t// MoveF2I" %}
9313 size(4);
9314 ins_encode( enc_stfs(src, dst) );
9315 ins_pipe(pipe_class_memory);
9316 %}
9318 // Move integer value from integer stack-location to float register.
9319 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9320 match(Set dst (MoveI2F src));
9321 ins_cost(MEMORY_REF_COST);
9323 format %{ "LFS $dst, $src \t// MoveI2F" %}
9324 size(4);
9325 ins_encode %{
9326 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9327 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9328 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9329 %}
9330 ins_pipe(pipe_class_memory);
9331 %}
9333 // Move integer value from integer register to float stack-location.
9334 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9335 match(Set dst (MoveI2F src));
9336 ins_cost(MEMORY_REF_COST);
9338 format %{ "STW $src, $dst \t// MoveI2F" %}
9339 size(4);
9340 ins_encode( enc_stw(src, dst) );
9341 ins_pipe(pipe_class_memory);
9342 %}
9344 //----------Moves between long and float
9346 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9347 // no match-rule, false predicate
9348 effect(DEF dst, USE src);
9349 predicate(false);
9351 format %{ "storeD $src, $dst \t// STACK" %}
9352 size(4);
9353 ins_encode( enc_stfd(src, dst) );
9354 ins_pipe(pipe_class_default);
9355 %}
9357 //----------Moves between long and double
9359 // Move double value from double stack-location to long register.
9360 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9361 match(Set dst (MoveD2L src));
9362 ins_cost(MEMORY_REF_COST);
9363 size(4);
9364 format %{ "LD $dst, $src \t// MoveD2L" %}
9365 ins_encode( enc_ld(dst, src) );
9366 ins_pipe(pipe_class_memory);
9367 %}
9369 // Move double value from double register to long stack-location.
9370 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9371 match(Set dst (MoveD2L src));
9372 effect(DEF dst, USE src);
9373 ins_cost(MEMORY_REF_COST);
9375 format %{ "STFD $src, $dst \t// MoveD2L" %}
9376 size(4);
9377 ins_encode( enc_stfd(src, dst) );
9378 ins_pipe(pipe_class_memory);
9379 %}
9381 // Move long value from long stack-location to double register.
9382 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9383 match(Set dst (MoveL2D src));
9384 ins_cost(MEMORY_REF_COST);
9386 format %{ "LFD $dst, $src \t// MoveL2D" %}
9387 size(4);
9388 ins_encode( enc_lfd(dst, src) );
9389 ins_pipe(pipe_class_memory);
9390 %}
9392 // Move long value from long register to double stack-location.
9393 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9394 match(Set dst (MoveL2D src));
9395 ins_cost(MEMORY_REF_COST);
9397 format %{ "STD $src, $dst \t// MoveL2D" %}
9398 size(4);
9399 ins_encode( enc_std(src, dst) );
9400 ins_pipe(pipe_class_memory);
9401 %}
9403 //----------Register Move Instructions-----------------------------------------
9405 // Replicate for Superword
9407 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9408 predicate(false);
9409 effect(DEF dst, USE src);
9411 format %{ "MR $dst, $src \t// replicate " %}
9412 // variable size, 0 or 4.
9413 ins_encode %{
9414 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9415 __ mr_if_needed($dst$$Register, $src$$Register);
9416 %}
9417 ins_pipe(pipe_class_default);
9418 %}
9420 //----------Cast instructions (Java-level type cast)---------------------------
9422 // Cast Long to Pointer for unsafe natives.
9423 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9424 match(Set dst (CastX2P src));
9426 format %{ "MR $dst, $src \t// Long->Ptr" %}
9427 // variable size, 0 or 4.
9428 ins_encode %{
9429 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9430 __ mr_if_needed($dst$$Register, $src$$Register);
9431 %}
9432 ins_pipe(pipe_class_default);
9433 %}
9435 // Cast Pointer to Long for unsafe natives.
9436 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9437 match(Set dst (CastP2X src));
9439 format %{ "MR $dst, $src \t// Ptr->Long" %}
9440 // variable size, 0 or 4.
9441 ins_encode %{
9442 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9443 __ mr_if_needed($dst$$Register, $src$$Register);
9444 %}
9445 ins_pipe(pipe_class_default);
9446 %}
9448 instruct castPP(iRegPdst dst) %{
9449 match(Set dst (CastPP dst));
9450 format %{ " -- \t// castPP of $dst" %}
9451 size(0);
9452 ins_encode( /*empty*/ );
9453 ins_pipe(pipe_class_default);
9454 %}
9456 instruct castII(iRegIdst dst) %{
9457 match(Set dst (CastII dst));
9458 format %{ " -- \t// castII of $dst" %}
9459 size(0);
9460 ins_encode( /*empty*/ );
9461 ins_pipe(pipe_class_default);
9462 %}
9464 instruct checkCastPP(iRegPdst dst) %{
9465 match(Set dst (CheckCastPP dst));
9466 format %{ " -- \t// checkcastPP of $dst" %}
9467 size(0);
9468 ins_encode( /*empty*/ );
9469 ins_pipe(pipe_class_default);
9470 %}
9472 //----------Convert instructions-----------------------------------------------
9474 // Convert to boolean.
9476 // int_to_bool(src) : { 1 if src != 0
9477 // { 0 else
9478 //
9479 // strategy:
9480 // 1) Count leading zeros of 32 bit-value src,
9481 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9482 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9483 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9485 // convI2Bool
9486 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9487 match(Set dst (Conv2B src));
9488 predicate(UseCountLeadingZerosInstructionsPPC64);
9489 ins_cost(DEFAULT_COST);
9491 expand %{
9492 immI shiftAmount %{ 0x5 %}
9493 uimmI16 mask %{ 0x1 %}
9494 iRegIdst tmp1;
9495 iRegIdst tmp2;
9496 countLeadingZerosI(tmp1, src);
9497 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9498 xorI_reg_uimm16(dst, tmp2, mask);
9499 %}
9500 %}
9502 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9503 match(Set dst (Conv2B src));
9504 effect(TEMP crx);
9505 predicate(!UseCountLeadingZerosInstructionsPPC64);
9506 ins_cost(DEFAULT_COST);
9508 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9509 "LI $dst, #0\n\t"
9510 "BEQ $crx, done\n\t"
9511 "LI $dst, #1\n"
9512 "done:" %}
9513 size(16);
9514 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9515 ins_pipe(pipe_class_compare);
9516 %}
9518 // ConvI2B + XorI
9519 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9520 match(Set dst (XorI (Conv2B src) mask));
9521 predicate(UseCountLeadingZerosInstructionsPPC64);
9522 ins_cost(DEFAULT_COST);
9524 expand %{
9525 immI shiftAmount %{ 0x5 %}
9526 iRegIdst tmp1;
9527 countLeadingZerosI(tmp1, src);
9528 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9529 %}
9530 %}
9532 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9533 match(Set dst (XorI (Conv2B src) mask));
9534 effect(TEMP crx);
9535 predicate(!UseCountLeadingZerosInstructionsPPC64);
9536 ins_cost(DEFAULT_COST);
9538 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9539 "LI $dst, #1\n\t"
9540 "BEQ $crx, done\n\t"
9541 "LI $dst, #0\n"
9542 "done:" %}
9543 size(16);
9544 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9545 ins_pipe(pipe_class_compare);
9546 %}
9548 // AndI 0b0..010..0 + ConvI2B
9549 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9550 match(Set dst (Conv2B (AndI src mask)));
9551 predicate(UseRotateAndMaskInstructionsPPC64);
9552 ins_cost(DEFAULT_COST);
9554 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9555 size(4);
9556 ins_encode %{
9557 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9558 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9559 %}
9560 ins_pipe(pipe_class_default);
9561 %}
9563 // Convert pointer to boolean.
9564 //
9565 // ptr_to_bool(src) : { 1 if src != 0
9566 // { 0 else
9567 //
9568 // strategy:
9569 // 1) Count leading zeros of 64 bit-value src,
9570 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9571 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9572 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9574 // ConvP2B
9575 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9576 match(Set dst (Conv2B src));
9577 predicate(UseCountLeadingZerosInstructionsPPC64);
9578 ins_cost(DEFAULT_COST);
9580 expand %{
9581 immI shiftAmount %{ 0x6 %}
9582 uimmI16 mask %{ 0x1 %}
9583 iRegIdst tmp1;
9584 iRegIdst tmp2;
9585 countLeadingZerosP(tmp1, src);
9586 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9587 xorI_reg_uimm16(dst, tmp2, mask);
9588 %}
9589 %}
9591 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9592 match(Set dst (Conv2B src));
9593 effect(TEMP crx);
9594 predicate(!UseCountLeadingZerosInstructionsPPC64);
9595 ins_cost(DEFAULT_COST);
9597 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9598 "LI $dst, #0\n\t"
9599 "BEQ $crx, done\n\t"
9600 "LI $dst, #1\n"
9601 "done:" %}
9602 size(16);
9603 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9604 ins_pipe(pipe_class_compare);
9605 %}
9607 // ConvP2B + XorI
9608 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9609 match(Set dst (XorI (Conv2B src) mask));
9610 predicate(UseCountLeadingZerosInstructionsPPC64);
9611 ins_cost(DEFAULT_COST);
9613 expand %{
9614 immI shiftAmount %{ 0x6 %}
9615 iRegIdst tmp1;
9616 countLeadingZerosP(tmp1, src);
9617 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9618 %}
9619 %}
9621 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9622 match(Set dst (XorI (Conv2B src) mask));
9623 effect(TEMP crx);
9624 predicate(!UseCountLeadingZerosInstructionsPPC64);
9625 ins_cost(DEFAULT_COST);
9627 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9628 "LI $dst, #1\n\t"
9629 "BEQ $crx, done\n\t"
9630 "LI $dst, #0\n"
9631 "done:" %}
9632 size(16);
9633 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9634 ins_pipe(pipe_class_compare);
9635 %}
9637 // if src1 < src2, return -1 else return 0
9638 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9639 match(Set dst (CmpLTMask src1 src2));
9640 ins_cost(DEFAULT_COST*4);
9642 expand %{
9643 iRegLdst src1s;
9644 iRegLdst src2s;
9645 iRegLdst diff;
9646 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9647 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9648 subL_reg_reg(diff, src1s, src2s);
9649 // Need to consider >=33 bit result, therefore we need signmaskL.
9650 signmask64I_regL(dst, diff);
9651 %}
9652 %}
9654 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9655 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9656 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9657 size(4);
9658 ins_encode %{
9659 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9660 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9661 %}
9662 ins_pipe(pipe_class_default);
9663 %}
9665 //----------Arithmetic Conversion Instructions---------------------------------
9667 // Convert to Byte -- nop
9668 // Convert to Short -- nop
9670 // Convert to Int
9672 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9673 match(Set dst (RShiftI (LShiftI src amount) amount));
9674 format %{ "EXTSB $dst, $src \t// byte->int" %}
9675 size(4);
9676 ins_encode %{
9677 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9678 __ extsb($dst$$Register, $src$$Register);
9679 %}
9680 ins_pipe(pipe_class_default);
9681 %}
9683 // LShiftI 16 + RShiftI 16 converts short to int.
9684 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9685 match(Set dst (RShiftI (LShiftI src amount) amount));
9686 format %{ "EXTSH $dst, $src \t// short->int" %}
9687 size(4);
9688 ins_encode %{
9689 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9690 __ extsh($dst$$Register, $src$$Register);
9691 %}
9692 ins_pipe(pipe_class_default);
9693 %}
9695 // ConvL2I + ConvI2L: Sign extend int in long register.
9696 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9697 match(Set dst (ConvI2L (ConvL2I src)));
9699 format %{ "EXTSW $dst, $src \t// long->long" %}
9700 size(4);
9701 ins_encode %{
9702 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9703 __ extsw($dst$$Register, $src$$Register);
9704 %}
9705 ins_pipe(pipe_class_default);
9706 %}
9708 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9709 match(Set dst (ConvL2I src));
9710 format %{ "MR $dst, $src \t// long->int" %}
9711 // variable size, 0 or 4
9712 ins_encode %{
9713 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9714 __ mr_if_needed($dst$$Register, $src$$Register);
9715 %}
9716 ins_pipe(pipe_class_default);
9717 %}
9719 instruct convD2IRaw_regD(regD dst, regD src) %{
9720 // no match-rule, false predicate
9721 effect(DEF dst, USE src);
9722 predicate(false);
9724 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9725 size(4);
9726 ins_encode %{
9727 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9728 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9729 %}
9730 ins_pipe(pipe_class_default);
9731 %}
9733 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9734 // no match-rule, false predicate
9735 effect(DEF dst, USE crx, USE src);
9736 predicate(false);
9738 ins_variable_size_depending_on_alignment(true);
9740 format %{ "cmovI $crx, $dst, $src" %}
9741 // Worst case is branch + move + stop, no stop without scheduler.
9742 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9743 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9744 ins_pipe(pipe_class_default);
9745 %}
9747 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9748 // no match-rule, false predicate
9749 effect(DEF dst, USE crx, USE mem);
9750 predicate(false);
9752 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9753 postalloc_expand %{
9754 //
9755 // replaces
9756 //
9757 // region dst crx mem
9758 // \ | | /
9759 // dst=cmovI_bso_stackSlotL_conLvalue0
9760 //
9761 // with
9762 //
9763 // region dst
9764 // \ /
9765 // dst=loadConI16(0)
9766 // |
9767 // ^ region dst crx mem
9768 // | \ | | /
9769 // dst=cmovI_bso_stackSlotL
9770 //
9772 // Create new nodes.
9773 MachNode *m1 = new (C) loadConI16Node();
9774 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9776 // inputs for new nodes
9777 m1->add_req(n_region);
9778 m2->add_req(n_region, n_crx, n_mem);
9780 // precedences for new nodes
9781 m2->add_prec(m1);
9783 // operands for new nodes
9784 m1->_opnds[0] = op_dst;
9785 m1->_opnds[1] = new (C) immI16Oper(0);
9787 m2->_opnds[0] = op_dst;
9788 m2->_opnds[1] = op_crx;
9789 m2->_opnds[2] = op_mem;
9791 // registers for new nodes
9792 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9793 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9795 // Insert new nodes.
9796 nodes->push(m1);
9797 nodes->push(m2);
9798 %}
9799 %}
9801 // Double to Int conversion, NaN is mapped to 0.
9802 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9803 match(Set dst (ConvD2I src));
9804 ins_cost(DEFAULT_COST);
9806 expand %{
9807 regD tmpD;
9808 stackSlotL tmpS;
9809 flagsReg crx;
9810 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9811 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9812 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9813 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9814 %}
9815 %}
9817 instruct convF2IRaw_regF(regF dst, regF src) %{
9818 // no match-rule, false predicate
9819 effect(DEF dst, USE src);
9820 predicate(false);
9822 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9823 size(4);
9824 ins_encode %{
9825 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9826 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9827 %}
9828 ins_pipe(pipe_class_default);
9829 %}
9831 // Float to Int conversion, NaN is mapped to 0.
9832 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9833 match(Set dst (ConvF2I src));
9834 ins_cost(DEFAULT_COST);
9836 expand %{
9837 regF tmpF;
9838 stackSlotL tmpS;
9839 flagsReg crx;
9840 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9841 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9842 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9843 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9844 %}
9845 %}
9847 // Convert to Long
9849 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9850 match(Set dst (ConvI2L src));
9851 format %{ "EXTSW $dst, $src \t// int->long" %}
9852 size(4);
9853 ins_encode %{
9854 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9855 __ extsw($dst$$Register, $src$$Register);
9856 %}
9857 ins_pipe(pipe_class_default);
9858 %}
9860 // Zero-extend: convert unsigned int to long (convUI2L).
9861 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9862 match(Set dst (AndL (ConvI2L src) mask));
9863 ins_cost(DEFAULT_COST);
9865 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9866 size(4);
9867 ins_encode %{
9868 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9869 __ clrldi($dst$$Register, $src$$Register, 32);
9870 %}
9871 ins_pipe(pipe_class_default);
9872 %}
9874 // Zero-extend: convert unsigned int to long in long register.
9875 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9876 match(Set dst (AndL src mask));
9877 ins_cost(DEFAULT_COST);
9879 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9880 size(4);
9881 ins_encode %{
9882 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9883 __ clrldi($dst$$Register, $src$$Register, 32);
9884 %}
9885 ins_pipe(pipe_class_default);
9886 %}
9888 instruct convF2LRaw_regF(regF dst, regF src) %{
9889 // no match-rule, false predicate
9890 effect(DEF dst, USE src);
9891 predicate(false);
9893 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9894 size(4);
9895 ins_encode %{
9896 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9897 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9898 %}
9899 ins_pipe(pipe_class_default);
9900 %}
9902 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9903 // no match-rule, false predicate
9904 effect(DEF dst, USE crx, USE src);
9905 predicate(false);
9907 ins_variable_size_depending_on_alignment(true);
9909 format %{ "cmovL $crx, $dst, $src" %}
9910 // Worst case is branch + move + stop, no stop without scheduler.
9911 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9912 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9913 ins_pipe(pipe_class_default);
9914 %}
9916 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9917 // no match-rule, false predicate
9918 effect(DEF dst, USE crx, USE mem);
9919 predicate(false);
9921 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9922 postalloc_expand %{
9923 //
9924 // replaces
9925 //
9926 // region dst crx mem
9927 // \ | | /
9928 // dst=cmovL_bso_stackSlotL_conLvalue0
9929 //
9930 // with
9931 //
9932 // region dst
9933 // \ /
9934 // dst=loadConL16(0)
9935 // |
9936 // ^ region dst crx mem
9937 // | \ | | /
9938 // dst=cmovL_bso_stackSlotL
9939 //
9941 // Create new nodes.
9942 MachNode *m1 = new (C) loadConL16Node();
9943 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9945 // inputs for new nodes
9946 m1->add_req(n_region);
9947 m2->add_req(n_region, n_crx, n_mem);
9948 m2->add_prec(m1);
9950 // operands for new nodes
9951 m1->_opnds[0] = op_dst;
9952 m1->_opnds[1] = new (C) immL16Oper(0);
9953 m2->_opnds[0] = op_dst;
9954 m2->_opnds[1] = op_crx;
9955 m2->_opnds[2] = op_mem;
9957 // registers for new nodes
9958 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9959 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9961 // Insert new nodes.
9962 nodes->push(m1);
9963 nodes->push(m2);
9964 %}
9965 %}
9967 // Float to Long conversion, NaN is mapped to 0.
9968 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9969 match(Set dst (ConvF2L src));
9970 ins_cost(DEFAULT_COST);
9972 expand %{
9973 regF tmpF;
9974 stackSlotL tmpS;
9975 flagsReg crx;
9976 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9977 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9978 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9979 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9980 %}
9981 %}
9983 instruct convD2LRaw_regD(regD dst, regD src) %{
9984 // no match-rule, false predicate
9985 effect(DEF dst, USE src);
9986 predicate(false);
9988 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
9989 size(4);
9990 ins_encode %{
9991 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9992 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9993 %}
9994 ins_pipe(pipe_class_default);
9995 %}
9997 // Double to Long conversion, NaN is mapped to 0.
9998 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
9999 match(Set dst (ConvD2L src));
10000 ins_cost(DEFAULT_COST);
10002 expand %{
10003 regD tmpD;
10004 stackSlotL tmpS;
10005 flagsReg crx;
10006 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10007 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10008 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10009 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10010 %}
10011 %}
10013 // Convert to Float
10015 // Placed here as needed in expand.
10016 instruct convL2DRaw_regD(regD dst, regD src) %{
10017 // no match-rule, false predicate
10018 effect(DEF dst, USE src);
10019 predicate(false);
10021 format %{ "FCFID $dst, $src \t// convL2D" %}
10022 size(4);
10023 ins_encode %{
10024 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10025 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10026 %}
10027 ins_pipe(pipe_class_default);
10028 %}
10030 // Placed here as needed in expand.
10031 instruct convD2F_reg(regF dst, regD src) %{
10032 match(Set dst (ConvD2F src));
10033 format %{ "FRSP $dst, $src \t// convD2F" %}
10034 size(4);
10035 ins_encode %{
10036 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10037 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10038 %}
10039 ins_pipe(pipe_class_default);
10040 %}
10042 // Integer to Float conversion.
10043 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10044 match(Set dst (ConvI2F src));
10045 predicate(!VM_Version::has_fcfids());
10046 ins_cost(DEFAULT_COST);
10048 expand %{
10049 iRegLdst tmpL;
10050 stackSlotL tmpS;
10051 regD tmpD;
10052 regD tmpD2;
10053 convI2L_reg(tmpL, src); // Sign-extension int to long.
10054 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10055 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10056 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10057 convD2F_reg(dst, tmpD2); // Convert double to float.
10058 %}
10059 %}
10061 instruct convL2FRaw_regF(regF dst, regD src) %{
10062 // no match-rule, false predicate
10063 effect(DEF dst, USE src);
10064 predicate(false);
10066 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10067 size(4);
10068 ins_encode %{
10069 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10070 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10071 %}
10072 ins_pipe(pipe_class_default);
10073 %}
10075 // Integer to Float conversion. Special version for Power7.
10076 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10077 match(Set dst (ConvI2F src));
10078 predicate(VM_Version::has_fcfids());
10079 ins_cost(DEFAULT_COST);
10081 expand %{
10082 iRegLdst tmpL;
10083 stackSlotL tmpS;
10084 regD tmpD;
10085 convI2L_reg(tmpL, src); // Sign-extension int to long.
10086 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10087 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10088 convL2FRaw_regF(dst, tmpD); // Convert to float.
10089 %}
10090 %}
10092 // L2F to avoid runtime call.
10093 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10094 match(Set dst (ConvL2F src));
10095 predicate(VM_Version::has_fcfids());
10096 ins_cost(DEFAULT_COST);
10098 expand %{
10099 stackSlotL tmpS;
10100 regD tmpD;
10101 regL_to_stkL(tmpS, src); // Store long to stack.
10102 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10103 convL2FRaw_regF(dst, tmpD); // Convert to float.
10104 %}
10105 %}
10107 // Moved up as used in expand.
10108 //instruct convD2F_reg(regF dst, regD src) %{%}
10110 // Convert to Double
10112 // Integer to Double conversion.
10113 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10114 match(Set dst (ConvI2D src));
10115 ins_cost(DEFAULT_COST);
10117 expand %{
10118 iRegLdst tmpL;
10119 stackSlotL tmpS;
10120 regD tmpD;
10121 convI2L_reg(tmpL, src); // Sign-extension int to long.
10122 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10123 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10124 convL2DRaw_regD(dst, tmpD); // Convert to double.
10125 %}
10126 %}
10128 // Long to Double conversion
10129 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10130 match(Set dst (ConvL2D src));
10131 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10133 expand %{
10134 regD tmpD;
10135 moveL2D_stack_reg(tmpD, src);
10136 convL2DRaw_regD(dst, tmpD);
10137 %}
10138 %}
10140 instruct convF2D_reg(regD dst, regF src) %{
10141 match(Set dst (ConvF2D src));
10142 format %{ "FMR $dst, $src \t// float->double" %}
10143 // variable size, 0 or 4
10144 ins_encode %{
10145 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10146 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10147 %}
10148 ins_pipe(pipe_class_default);
10149 %}
10151 //----------Control Flow Instructions------------------------------------------
10152 // Compare Instructions
10154 // Compare Integers
10155 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10156 match(Set crx (CmpI src1 src2));
10157 size(4);
10158 format %{ "CMPW $crx, $src1, $src2" %}
10159 ins_encode %{
10160 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10161 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10162 %}
10163 ins_pipe(pipe_class_compare);
10164 %}
10166 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10167 match(Set crx (CmpI src1 src2));
10168 format %{ "CMPWI $crx, $src1, $src2" %}
10169 size(4);
10170 ins_encode %{
10171 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10172 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10173 %}
10174 ins_pipe(pipe_class_compare);
10175 %}
10177 // (src1 & src2) == 0?
10178 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10179 match(Set cr0 (CmpI (AndI src1 src2) zero));
10180 // r0 is killed
10181 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10182 size(4);
10183 ins_encode %{
10184 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10185 // FIXME: avoid andi_ ?
10186 __ andi_(R0, $src1$$Register, $src2$$constant);
10187 %}
10188 ins_pipe(pipe_class_compare);
10189 %}
10191 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10192 match(Set crx (CmpL src1 src2));
10193 format %{ "CMPD $crx, $src1, $src2" %}
10194 size(4);
10195 ins_encode %{
10196 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10197 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10198 %}
10199 ins_pipe(pipe_class_compare);
10200 %}
10202 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10203 match(Set crx (CmpL src1 src2));
10204 format %{ "CMPDI $crx, $src1, $src2" %}
10205 size(4);
10206 ins_encode %{
10207 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10208 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10209 %}
10210 ins_pipe(pipe_class_compare);
10211 %}
10213 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10214 match(Set cr0 (CmpL (AndL src1 src2) zero));
10215 // r0 is killed
10216 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10217 size(4);
10218 ins_encode %{
10219 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10220 __ and_(R0, $src1$$Register, $src2$$Register);
10221 %}
10222 ins_pipe(pipe_class_compare);
10223 %}
10225 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10226 match(Set cr0 (CmpL (AndL src1 src2) zero));
10227 // r0 is killed
10228 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10229 size(4);
10230 ins_encode %{
10231 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10232 // FIXME: avoid andi_ ?
10233 __ andi_(R0, $src1$$Register, $src2$$constant);
10234 %}
10235 ins_pipe(pipe_class_compare);
10236 %}
10238 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10239 // no match-rule, false predicate
10240 effect(DEF dst, USE crx);
10241 predicate(false);
10243 ins_variable_size_depending_on_alignment(true);
10245 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10246 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10247 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10248 ins_encode %{
10249 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10250 Label done;
10251 // li(Rdst, 0); // equal -> 0
10252 __ beq($crx$$CondRegister, done);
10253 __ li($dst$$Register, 1); // greater -> +1
10254 __ bgt($crx$$CondRegister, done);
10255 __ li($dst$$Register, -1); // unordered or less -> -1
10256 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10257 __ bind(done);
10258 %}
10259 ins_pipe(pipe_class_compare);
10260 %}
10262 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10263 // no match-rule, false predicate
10264 effect(DEF dst, USE crx);
10265 predicate(false);
10267 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10268 postalloc_expand %{
10269 //
10270 // replaces
10271 //
10272 // region crx
10273 // \ |
10274 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10275 //
10276 // with
10277 //
10278 // region
10279 // \
10280 // dst=loadConI16(0)
10281 // |
10282 // ^ region crx
10283 // | \ |
10284 // dst=cmovI_conIvalueMinus1_conIvalue1
10285 //
10287 // Create new nodes.
10288 MachNode *m1 = new (C) loadConI16Node();
10289 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10291 // inputs for new nodes
10292 m1->add_req(n_region);
10293 m2->add_req(n_region, n_crx);
10294 m2->add_prec(m1);
10296 // operands for new nodes
10297 m1->_opnds[0] = op_dst;
10298 m1->_opnds[1] = new (C) immI16Oper(0);
10299 m2->_opnds[0] = op_dst;
10300 m2->_opnds[1] = op_crx;
10302 // registers for new nodes
10303 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10304 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10306 // Insert new nodes.
10307 nodes->push(m1);
10308 nodes->push(m2);
10309 %}
10310 %}
10312 // Manifest a CmpL3 result in an integer register. Very painful.
10313 // This is the test to avoid.
10314 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10315 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10316 match(Set dst (CmpL3 src1 src2));
10317 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10319 expand %{
10320 flagsReg tmp1;
10321 cmpL_reg_reg(tmp1, src1, src2);
10322 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10323 %}
10324 %}
10326 // Implicit range checks.
10327 // A range check in the ideal world has one of the following shapes:
10328 // - (If le (CmpU length index)), (IfTrue throw exception)
10329 // - (If lt (CmpU index length)), (IfFalse throw exception)
10330 //
10331 // Match range check 'If le (CmpU length index)'.
10332 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10333 match(If cmp (CmpU src_length index));
10334 effect(USE labl);
10335 predicate(TrapBasedRangeChecks &&
10336 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10337 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10338 (Matcher::branches_to_uncommon_trap(_leaf)));
10340 ins_is_TrapBasedCheckNode(true);
10342 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10343 size(4);
10344 ins_encode %{
10345 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10346 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10347 __ trap_range_check_le($src_length$$Register, $index$$constant);
10348 } else {
10349 // Both successors are uncommon traps, probability is 0.
10350 // Node got flipped during fixup flow.
10351 assert($cmp$$cmpcode == 0x9, "must be greater");
10352 __ trap_range_check_g($src_length$$Register, $index$$constant);
10353 }
10354 %}
10355 ins_pipe(pipe_class_trap);
10356 %}
10358 // Match range check 'If lt (CmpU index length)'.
10359 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10360 match(If cmp (CmpU src_index src_length));
10361 effect(USE labl);
10362 predicate(TrapBasedRangeChecks &&
10363 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10364 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10365 (Matcher::branches_to_uncommon_trap(_leaf)));
10367 ins_is_TrapBasedCheckNode(true);
10369 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10370 size(4);
10371 ins_encode %{
10372 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10373 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10374 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10375 } else {
10376 // Both successors are uncommon traps, probability is 0.
10377 // Node got flipped during fixup flow.
10378 assert($cmp$$cmpcode == 0x8, "must be less");
10379 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10380 }
10381 %}
10382 ins_pipe(pipe_class_trap);
10383 %}
10385 // Match range check 'If lt (CmpU index length)'.
10386 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10387 match(If cmp (CmpU src_index length));
10388 effect(USE labl);
10389 predicate(TrapBasedRangeChecks &&
10390 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10391 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10392 (Matcher::branches_to_uncommon_trap(_leaf)));
10394 ins_is_TrapBasedCheckNode(true);
10396 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10397 size(4);
10398 ins_encode %{
10399 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10400 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10401 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10402 } else {
10403 // Both successors are uncommon traps, probability is 0.
10404 // Node got flipped during fixup flow.
10405 assert($cmp$$cmpcode == 0x8, "must be less");
10406 __ trap_range_check_l($src_index$$Register, $length$$constant);
10407 }
10408 %}
10409 ins_pipe(pipe_class_trap);
10410 %}
10412 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10413 match(Set crx (CmpU src1 src2));
10414 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10415 size(4);
10416 ins_encode %{
10417 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10418 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10419 %}
10420 ins_pipe(pipe_class_compare);
10421 %}
10423 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10424 match(Set crx (CmpU src1 src2));
10425 size(4);
10426 format %{ "CMPLWI $crx, $src1, $src2" %}
10427 ins_encode %{
10428 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10429 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10430 %}
10431 ins_pipe(pipe_class_compare);
10432 %}
10434 // Implicit zero checks (more implicit null checks).
10435 // No constant pool entries required.
10436 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10437 match(If cmp (CmpN value zero));
10438 effect(USE labl);
10439 predicate(TrapBasedNullChecks &&
10440 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10441 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10442 Matcher::branches_to_uncommon_trap(_leaf));
10443 ins_cost(1);
10445 ins_is_TrapBasedCheckNode(true);
10447 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10448 size(4);
10449 ins_encode %{
10450 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10451 if ($cmp$$cmpcode == 0xA) {
10452 __ trap_null_check($value$$Register);
10453 } else {
10454 // Both successors are uncommon traps, probability is 0.
10455 // Node got flipped during fixup flow.
10456 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10457 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10458 }
10459 %}
10460 ins_pipe(pipe_class_trap);
10461 %}
10463 // Compare narrow oops.
10464 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10465 match(Set crx (CmpN src1 src2));
10467 size(4);
10468 ins_cost(DEFAULT_COST);
10469 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10470 ins_encode %{
10471 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10472 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10473 %}
10474 ins_pipe(pipe_class_compare);
10475 %}
10477 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10478 match(Set crx (CmpN src1 src2));
10479 // Make this more expensive than zeroCheckN_iReg_imm0.
10480 ins_cost(DEFAULT_COST);
10482 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10483 size(4);
10484 ins_encode %{
10485 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10486 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10487 %}
10488 ins_pipe(pipe_class_compare);
10489 %}
10491 // Implicit zero checks (more implicit null checks).
10492 // No constant pool entries required.
10493 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10494 match(If cmp (CmpP value zero));
10495 effect(USE labl);
10496 predicate(TrapBasedNullChecks &&
10497 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10498 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10499 Matcher::branches_to_uncommon_trap(_leaf));
10501 ins_is_TrapBasedCheckNode(true);
10503 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10504 size(4);
10505 ins_encode %{
10506 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10507 if ($cmp$$cmpcode == 0xA) {
10508 __ trap_null_check($value$$Register);
10509 } else {
10510 // Both successors are uncommon traps, probability is 0.
10511 // Node got flipped during fixup flow.
10512 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10513 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10514 }
10515 %}
10516 ins_pipe(pipe_class_trap);
10517 %}
10519 // Compare Pointers
10520 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10521 match(Set crx (CmpP src1 src2));
10522 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10523 size(4);
10524 ins_encode %{
10525 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10526 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10527 %}
10528 ins_pipe(pipe_class_compare);
10529 %}
10531 // Used in postalloc expand.
10532 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10533 // This match rule prevents reordering of node before a safepoint.
10534 // This only makes sense if this instructions is used exclusively
10535 // for the expansion of EncodeP!
10536 match(Set crx (CmpP src1 src2));
10537 predicate(false);
10539 format %{ "CMPDI $crx, $src1, $src2" %}
10540 size(4);
10541 ins_encode %{
10542 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10543 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10544 %}
10545 ins_pipe(pipe_class_compare);
10546 %}
10548 //----------Float Compares----------------------------------------------------
10550 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10551 // no match-rule, false predicate
10552 effect(DEF crx, USE src1, USE src2);
10553 predicate(false);
10555 format %{ "cmpFUrd $crx, $src1, $src2" %}
10556 size(4);
10557 ins_encode %{
10558 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10559 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10560 %}
10561 ins_pipe(pipe_class_default);
10562 %}
10564 instruct cmov_bns_less(flagsReg crx) %{
10565 // no match-rule, false predicate
10566 effect(DEF crx);
10567 predicate(false);
10569 ins_variable_size_depending_on_alignment(true);
10571 format %{ "cmov $crx" %}
10572 // Worst case is branch + move + stop, no stop without scheduler.
10573 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10574 ins_encode %{
10575 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10576 Label done;
10577 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10578 __ li(R0, 0);
10579 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10580 // TODO PPC port __ endgroup_if_needed(_size == 16);
10581 __ bind(done);
10582 %}
10583 ins_pipe(pipe_class_default);
10584 %}
10586 // Compare floating, generate condition code.
10587 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10588 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10589 //
10590 // The following code sequence occurs a lot in mpegaudio:
10591 //
10592 // block BXX:
10593 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10594 // cmpFUrd CCR6, F11, F9
10595 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10596 // cmov CCR6
10597 // 8: instruct branchConSched:
10598 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10599 match(Set crx (CmpF src1 src2));
10600 ins_cost(DEFAULT_COST+BRANCH_COST);
10602 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10603 postalloc_expand %{
10604 //
10605 // replaces
10606 //
10607 // region src1 src2
10608 // \ | |
10609 // crx=cmpF_reg_reg
10610 //
10611 // with
10612 //
10613 // region src1 src2
10614 // \ | |
10615 // crx=cmpFUnordered_reg_reg
10616 // |
10617 // ^ region
10618 // | \
10619 // crx=cmov_bns_less
10620 //
10622 // Create new nodes.
10623 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10624 MachNode *m2 = new (C) cmov_bns_lessNode();
10626 // inputs for new nodes
10627 m1->add_req(n_region, n_src1, n_src2);
10628 m2->add_req(n_region);
10629 m2->add_prec(m1);
10631 // operands for new nodes
10632 m1->_opnds[0] = op_crx;
10633 m1->_opnds[1] = op_src1;
10634 m1->_opnds[2] = op_src2;
10635 m2->_opnds[0] = op_crx;
10637 // registers for new nodes
10638 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10639 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10641 // Insert new nodes.
10642 nodes->push(m1);
10643 nodes->push(m2);
10644 %}
10645 %}
10647 // Compare float, generate -1,0,1
10648 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10649 match(Set dst (CmpF3 src1 src2));
10650 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10652 expand %{
10653 flagsReg tmp1;
10654 cmpFUnordered_reg_reg(tmp1, src1, src2);
10655 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10656 %}
10657 %}
10659 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10660 // no match-rule, false predicate
10661 effect(DEF crx, USE src1, USE src2);
10662 predicate(false);
10664 format %{ "cmpFUrd $crx, $src1, $src2" %}
10665 size(4);
10666 ins_encode %{
10667 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10668 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10669 %}
10670 ins_pipe(pipe_class_default);
10671 %}
10673 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10674 match(Set crx (CmpD src1 src2));
10675 ins_cost(DEFAULT_COST+BRANCH_COST);
10677 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10678 postalloc_expand %{
10679 //
10680 // replaces
10681 //
10682 // region src1 src2
10683 // \ | |
10684 // crx=cmpD_reg_reg
10685 //
10686 // with
10687 //
10688 // region src1 src2
10689 // \ | |
10690 // crx=cmpDUnordered_reg_reg
10691 // |
10692 // ^ region
10693 // | \
10694 // crx=cmov_bns_less
10695 //
10697 // create new nodes
10698 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10699 MachNode *m2 = new (C) cmov_bns_lessNode();
10701 // inputs for new nodes
10702 m1->add_req(n_region, n_src1, n_src2);
10703 m2->add_req(n_region);
10704 m2->add_prec(m1);
10706 // operands for new nodes
10707 m1->_opnds[0] = op_crx;
10708 m1->_opnds[1] = op_src1;
10709 m1->_opnds[2] = op_src2;
10710 m2->_opnds[0] = op_crx;
10712 // registers for new nodes
10713 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10714 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10716 // Insert new nodes.
10717 nodes->push(m1);
10718 nodes->push(m2);
10719 %}
10720 %}
10722 // Compare double, generate -1,0,1
10723 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10724 match(Set dst (CmpD3 src1 src2));
10725 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10727 expand %{
10728 flagsReg tmp1;
10729 cmpDUnordered_reg_reg(tmp1, src1, src2);
10730 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10731 %}
10732 %}
10734 //----------Branches---------------------------------------------------------
10735 // Jump
10737 // Direct Branch.
10738 instruct branch(label labl) %{
10739 match(Goto);
10740 effect(USE labl);
10741 ins_cost(BRANCH_COST);
10743 format %{ "B $labl" %}
10744 size(4);
10745 ins_encode %{
10746 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10747 Label d; // dummy
10748 __ bind(d);
10749 Label* p = $labl$$label;
10750 // `p' is `NULL' when this encoding class is used only to
10751 // determine the size of the encoded instruction.
10752 Label& l = (NULL == p)? d : *(p);
10753 __ b(l);
10754 %}
10755 ins_pipe(pipe_class_default);
10756 %}
10758 // Conditional Near Branch
10759 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10760 // Same match rule as `branchConFar'.
10761 match(If cmp crx);
10762 effect(USE lbl);
10763 ins_cost(BRANCH_COST);
10765 // If set to 1 this indicates that the current instruction is a
10766 // short variant of a long branch. This avoids using this
10767 // instruction in first-pass matching. It will then only be used in
10768 // the `Shorten_branches' pass.
10769 ins_short_branch(1);
10771 format %{ "B$cmp $crx, $lbl" %}
10772 size(4);
10773 ins_encode( enc_bc(crx, cmp, lbl) );
10774 ins_pipe(pipe_class_default);
10775 %}
10777 // This is for cases when the ppc64 `bc' instruction does not
10778 // reach far enough. So we emit a far branch here, which is more
10779 // expensive.
10780 //
10781 // Conditional Far Branch
10782 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10783 // Same match rule as `branchCon'.
10784 match(If cmp crx);
10785 effect(USE crx, USE lbl);
10786 predicate(!false /* TODO: PPC port HB_Schedule*/);
10787 // Higher cost than `branchCon'.
10788 ins_cost(5*BRANCH_COST);
10790 // This is not a short variant of a branch, but the long variant.
10791 ins_short_branch(0);
10793 format %{ "B_FAR$cmp $crx, $lbl" %}
10794 size(8);
10795 ins_encode( enc_bc_far(crx, cmp, lbl) );
10796 ins_pipe(pipe_class_default);
10797 %}
10799 // Conditional Branch used with Power6 scheduler (can be far or short).
10800 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10801 // Same match rule as `branchCon'.
10802 match(If cmp crx);
10803 effect(USE crx, USE lbl);
10804 predicate(false /* TODO: PPC port HB_Schedule*/);
10805 // Higher cost than `branchCon'.
10806 ins_cost(5*BRANCH_COST);
10808 // Actually size doesn't depend on alignment but on shortening.
10809 ins_variable_size_depending_on_alignment(true);
10810 // long variant.
10811 ins_short_branch(0);
10813 format %{ "B_FAR$cmp $crx, $lbl" %}
10814 size(8); // worst case
10815 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10816 ins_pipe(pipe_class_default);
10817 %}
10819 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10820 match(CountedLoopEnd cmp crx);
10821 effect(USE labl);
10822 ins_cost(BRANCH_COST);
10824 // short variant.
10825 ins_short_branch(1);
10827 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10828 size(4);
10829 ins_encode( enc_bc(crx, cmp, labl) );
10830 ins_pipe(pipe_class_default);
10831 %}
10833 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10834 match(CountedLoopEnd cmp crx);
10835 effect(USE labl);
10836 predicate(!false /* TODO: PPC port HB_Schedule */);
10837 ins_cost(BRANCH_COST);
10839 // Long variant.
10840 ins_short_branch(0);
10842 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10843 size(8);
10844 ins_encode( enc_bc_far(crx, cmp, labl) );
10845 ins_pipe(pipe_class_default);
10846 %}
10848 // Conditional Branch used with Power6 scheduler (can be far or short).
10849 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10850 match(CountedLoopEnd cmp crx);
10851 effect(USE labl);
10852 predicate(false /* TODO: PPC port HB_Schedule */);
10853 // Higher cost than `branchCon'.
10854 ins_cost(5*BRANCH_COST);
10856 // Actually size doesn't depend on alignment but on shortening.
10857 ins_variable_size_depending_on_alignment(true);
10858 // Long variant.
10859 ins_short_branch(0);
10861 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10862 size(8); // worst case
10863 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10864 ins_pipe(pipe_class_default);
10865 %}
10867 // ============================================================================
10868 // Java runtime operations, intrinsics and other complex operations.
10870 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10871 // array for an instance of the superklass. Set a hidden internal cache on a
10872 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10873 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10874 //
10875 // GL TODO: Improve this.
10876 // - result should not be a TEMP
10877 // - Add match rule as on sparc avoiding additional Cmp.
10878 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10879 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10880 match(Set result (PartialSubtypeCheck subklass superklass));
10881 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10882 ins_cost(DEFAULT_COST*10);
10884 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10885 ins_encode %{
10886 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10887 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10888 $tmp_klass$$Register, NULL, $result$$Register);
10889 %}
10890 ins_pipe(pipe_class_default);
10891 %}
10893 // inlined locking and unlocking
10895 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10896 match(Set crx (FastLock oop box));
10897 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10898 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10900 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10901 ins_encode %{
10902 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10903 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10904 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10905 // If locking was successfull, crx should indicate 'EQ'.
10906 // The compiler generates a branch to the runtime call to
10907 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10908 %}
10909 ins_pipe(pipe_class_compare);
10910 %}
10912 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10913 match(Set crx (FastUnlock oop box));
10914 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10916 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10917 ins_encode %{
10918 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10919 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10920 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10921 // If unlocking was successfull, crx should indicate 'EQ'.
10922 // The compiler generates a branch to the runtime call to
10923 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10924 %}
10925 ins_pipe(pipe_class_compare);
10926 %}
10928 // Align address.
10929 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10930 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10932 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10933 size(4);
10934 ins_encode %{
10935 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10936 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10937 %}
10938 ins_pipe(pipe_class_default);
10939 %}
10941 // Array size computation.
10942 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10943 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10945 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10946 size(4);
10947 ins_encode %{
10948 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10949 __ subf($dst$$Register, $start$$Register, $end$$Register);
10950 %}
10951 ins_pipe(pipe_class_default);
10952 %}
10954 // Clear-array with dynamic array-size.
10955 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10956 match(Set dummy (ClearArray cnt base));
10957 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10958 ins_cost(MEMORY_REF_COST);
10960 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10962 format %{ "ClearArray $cnt, $base" %}
10963 ins_encode %{
10964 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10965 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10966 %}
10967 ins_pipe(pipe_class_default);
10968 %}
10970 // String_IndexOf for needle of length 1.
10971 //
10972 // Match needle into immediate operands: no loadConP node needed. Saves one
10973 // register and two instructions over string_indexOf_imm1Node.
10974 //
10975 // Assumes register result differs from all input registers.
10976 //
10977 // Preserves registers haystack, haycnt
10978 // Kills registers tmp1, tmp2
10979 // Defines registers result
10980 //
10981 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10982 //
10983 // Unfortunately this does not match too often. In many situations the AddP is used
10984 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10985 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10986 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10987 iRegIdst tmp1, iRegIdst tmp2,
10988 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
10989 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
10990 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
10992 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
10994 ins_cost(150);
10995 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
10996 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
10998 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
10999 ins_encode %{
11000 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11001 immPOper *needleOper = (immPOper *)$needleImm;
11002 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11003 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11005 __ string_indexof_1($result$$Register,
11006 $haystack$$Register, $haycnt$$Register,
11007 R0, needle_values->char_at(0),
11008 $tmp1$$Register, $tmp2$$Register);
11009 %}
11010 ins_pipe(pipe_class_compare);
11011 %}
11013 // String_IndexOf for needle of length 1.
11014 //
11015 // Special case requires less registers and emits less instructions.
11016 //
11017 // Assumes register result differs from all input registers.
11018 //
11019 // Preserves registers haystack, haycnt
11020 // Kills registers tmp1, tmp2, needle
11021 // Defines registers result
11022 //
11023 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11024 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11025 rscratch2RegP needle, immI_1 needlecntImm,
11026 iRegIdst tmp1, iRegIdst tmp2,
11027 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11028 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11029 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
11030 TEMP tmp1, TEMP tmp2);
11031 // Required for EA: check if it is still a type_array.
11032 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11033 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11034 ins_cost(180);
11036 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11038 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11039 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11040 ins_encode %{
11041 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11042 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11043 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11044 guarantee(needle_values, "sanity");
11045 if (needle_values != NULL) {
11046 __ string_indexof_1($result$$Register,
11047 $haystack$$Register, $haycnt$$Register,
11048 R0, needle_values->char_at(0),
11049 $tmp1$$Register, $tmp2$$Register);
11050 } else {
11051 __ string_indexof_1($result$$Register,
11052 $haystack$$Register, $haycnt$$Register,
11053 $needle$$Register, 0,
11054 $tmp1$$Register, $tmp2$$Register);
11055 }
11056 %}
11057 ins_pipe(pipe_class_compare);
11058 %}
11060 // String_IndexOf.
11061 //
11062 // Length of needle as immediate. This saves instruction loading constant needle
11063 // length.
11064 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11065 // completely or do it in vector instruction. This should save registers for
11066 // needlecnt and needle.
11067 //
11068 // Assumes register result differs from all input registers.
11069 // Overwrites haycnt, needlecnt.
11070 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11071 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11072 iRegPsrc needle, uimmI15 needlecntImm,
11073 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11074 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11075 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11076 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11077 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11078 // Required for EA: check if it is still a type_array.
11079 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11080 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11081 ins_cost(250);
11083 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11085 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11086 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11087 ins_encode %{
11088 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11089 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11090 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11092 __ string_indexof($result$$Register,
11093 $haystack$$Register, $haycnt$$Register,
11094 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11095 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11096 %}
11097 ins_pipe(pipe_class_compare);
11098 %}
11100 // StrIndexOf node.
11101 //
11102 // Assumes register result differs from all input registers.
11103 // Overwrites haycnt, needlecnt.
11104 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11105 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11106 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11107 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11108 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11109 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11110 TEMP result,
11111 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11112 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11113 ins_cost(300);
11115 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11117 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11118 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11119 ins_encode %{
11120 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11121 __ string_indexof($result$$Register,
11122 $haystack$$Register, $haycnt$$Register,
11123 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11124 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11125 %}
11126 ins_pipe(pipe_class_compare);
11127 %}
11129 // String equals with immediate.
11130 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11131 iRegPdst tmp1, iRegPdst tmp2,
11132 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11133 match(Set result (StrEquals (Binary str1 str2) cntImm));
11134 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11135 KILL cr0, KILL cr6, KILL ctr);
11136 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11137 ins_cost(250);
11139 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11141 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11142 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11143 ins_encode %{
11144 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11145 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11146 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11147 %}
11148 ins_pipe(pipe_class_compare);
11149 %}
11151 // String equals.
11152 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11153 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11154 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11155 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11156 match(Set result (StrEquals (Binary str1 str2) cnt));
11157 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11158 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11159 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11160 ins_cost(300);
11162 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11164 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11165 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11166 ins_encode %{
11167 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11168 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11169 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11170 %}
11171 ins_pipe(pipe_class_compare);
11172 %}
11174 // String compare.
11175 // Char[] pointers are passed in.
11176 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11177 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11178 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11179 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11180 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11181 ins_cost(300);
11183 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11185 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11186 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11187 ins_encode %{
11188 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11189 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11190 $result$$Register, $tmp$$Register);
11191 %}
11192 ins_pipe(pipe_class_compare);
11193 %}
11195 //---------- Min/Max Instructions ---------------------------------------------
11197 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11198 match(Set dst (MinI src1 src2));
11199 ins_cost(DEFAULT_COST*6);
11201 expand %{
11202 iRegLdst src1s;
11203 iRegLdst src2s;
11204 iRegLdst diff;
11205 iRegLdst sm;
11206 iRegLdst doz; // difference or zero
11207 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11208 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11209 subL_reg_reg(diff, src2s, src1s);
11210 // Need to consider >=33 bit result, therefore we need signmaskL.
11211 signmask64L_regL(sm, diff);
11212 andL_reg_reg(doz, diff, sm); // <=0
11213 addI_regL_regL(dst, doz, src1s);
11214 %}
11215 %}
11217 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11218 match(Set dst (MaxI src1 src2));
11219 ins_cost(DEFAULT_COST*6);
11221 expand %{
11222 iRegLdst src1s;
11223 iRegLdst src2s;
11224 iRegLdst diff;
11225 iRegLdst sm;
11226 iRegLdst doz; // difference or zero
11227 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11228 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11229 subL_reg_reg(diff, src2s, src1s);
11230 // Need to consider >=33 bit result, therefore we need signmaskL.
11231 signmask64L_regL(sm, diff);
11232 andcL_reg_reg(doz, diff, sm); // >=0
11233 addI_regL_regL(dst, doz, src1s);
11234 %}
11235 %}
11237 //---------- Population Count Instructions ------------------------------------
11239 // Popcnt for Power7.
11240 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11241 match(Set dst (PopCountI src));
11242 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11243 ins_cost(DEFAULT_COST);
11245 format %{ "POPCNTW $dst, $src" %}
11246 size(4);
11247 ins_encode %{
11248 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11249 __ popcntw($dst$$Register, $src$$Register);
11250 %}
11251 ins_pipe(pipe_class_default);
11252 %}
11254 // Popcnt for Power7.
11255 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11256 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11257 match(Set dst (PopCountL src));
11258 ins_cost(DEFAULT_COST);
11260 format %{ "POPCNTD $dst, $src" %}
11261 size(4);
11262 ins_encode %{
11263 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11264 __ popcntd($dst$$Register, $src$$Register);
11265 %}
11266 ins_pipe(pipe_class_default);
11267 %}
11269 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11270 match(Set dst (CountLeadingZerosI src));
11271 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11272 ins_cost(DEFAULT_COST);
11274 format %{ "CNTLZW $dst, $src" %}
11275 size(4);
11276 ins_encode %{
11277 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11278 __ cntlzw($dst$$Register, $src$$Register);
11279 %}
11280 ins_pipe(pipe_class_default);
11281 %}
11283 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11284 match(Set dst (CountLeadingZerosL src));
11285 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11286 ins_cost(DEFAULT_COST);
11288 format %{ "CNTLZD $dst, $src" %}
11289 size(4);
11290 ins_encode %{
11291 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11292 __ cntlzd($dst$$Register, $src$$Register);
11293 %}
11294 ins_pipe(pipe_class_default);
11295 %}
11297 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11298 // no match-rule, false predicate
11299 effect(DEF dst, USE src);
11300 predicate(false);
11302 format %{ "CNTLZD $dst, $src" %}
11303 size(4);
11304 ins_encode %{
11305 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11306 __ cntlzd($dst$$Register, $src$$Register);
11307 %}
11308 ins_pipe(pipe_class_default);
11309 %}
11311 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11312 match(Set dst (CountTrailingZerosI src));
11313 predicate(UseCountLeadingZerosInstructionsPPC64);
11314 ins_cost(DEFAULT_COST);
11316 expand %{
11317 immI16 imm1 %{ (int)-1 %}
11318 immI16 imm2 %{ (int)32 %}
11319 immI_minus1 m1 %{ -1 %}
11320 iRegIdst tmpI1;
11321 iRegIdst tmpI2;
11322 iRegIdst tmpI3;
11323 addI_reg_imm16(tmpI1, src, imm1);
11324 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11325 countLeadingZerosI(tmpI3, tmpI2);
11326 subI_imm16_reg(dst, imm2, tmpI3);
11327 %}
11328 %}
11330 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11331 match(Set dst (CountTrailingZerosL src));
11332 predicate(UseCountLeadingZerosInstructionsPPC64);
11333 ins_cost(DEFAULT_COST);
11335 expand %{
11336 immL16 imm1 %{ (long)-1 %}
11337 immI16 imm2 %{ (int)64 %}
11338 iRegLdst tmpL1;
11339 iRegLdst tmpL2;
11340 iRegIdst tmpL3;
11341 addL_reg_imm16(tmpL1, src, imm1);
11342 andcL_reg_reg(tmpL2, tmpL1, src);
11343 countLeadingZerosL(tmpL3, tmpL2);
11344 subI_imm16_reg(dst, imm2, tmpL3);
11345 %}
11346 %}
11348 // Expand nodes for byte_reverse_int.
11349 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11350 effect(DEF dst, USE src, USE pos, USE shift);
11351 predicate(false);
11353 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11354 size(4);
11355 ins_encode %{
11356 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11357 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11358 %}
11359 ins_pipe(pipe_class_default);
11360 %}
11362 // As insrwi_a, but with USE_DEF.
11363 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11364 effect(USE_DEF dst, USE src, USE pos, USE shift);
11365 predicate(false);
11367 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11368 size(4);
11369 ins_encode %{
11370 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11371 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11372 %}
11373 ins_pipe(pipe_class_default);
11374 %}
11376 // Just slightly faster than java implementation.
11377 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11378 match(Set dst (ReverseBytesI src));
11379 predicate(UseCountLeadingZerosInstructionsPPC64);
11380 ins_cost(DEFAULT_COST);
11382 expand %{
11383 immI16 imm24 %{ (int) 24 %}
11384 immI16 imm16 %{ (int) 16 %}
11385 immI16 imm8 %{ (int) 8 %}
11386 immI16 imm4 %{ (int) 4 %}
11387 immI16 imm0 %{ (int) 0 %}
11388 iRegLdst tmpI1;
11389 iRegLdst tmpI2;
11390 iRegLdst tmpI3;
11392 urShiftI_reg_imm(tmpI1, src, imm24);
11393 insrwi_a(dst, tmpI1, imm24, imm8);
11394 urShiftI_reg_imm(tmpI2, src, imm16);
11395 insrwi(dst, tmpI2, imm8, imm16);
11396 urShiftI_reg_imm(tmpI3, src, imm8);
11397 insrwi(dst, tmpI3, imm8, imm8);
11398 insrwi(dst, src, imm0, imm8);
11399 %}
11400 %}
11402 //---------- Replicate Vector Instructions ------------------------------------
11404 // Insrdi does replicate if src == dst.
11405 instruct repl32(iRegLdst dst) %{
11406 predicate(false);
11407 effect(USE_DEF dst);
11409 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11410 size(4);
11411 ins_encode %{
11412 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11413 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11414 %}
11415 ins_pipe(pipe_class_default);
11416 %}
11418 // Insrdi does replicate if src == dst.
11419 instruct repl48(iRegLdst dst) %{
11420 predicate(false);
11421 effect(USE_DEF dst);
11423 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11424 size(4);
11425 ins_encode %{
11426 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11427 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11428 %}
11429 ins_pipe(pipe_class_default);
11430 %}
11432 // Insrdi does replicate if src == dst.
11433 instruct repl56(iRegLdst dst) %{
11434 predicate(false);
11435 effect(USE_DEF dst);
11437 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11438 size(4);
11439 ins_encode %{
11440 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11441 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11442 %}
11443 ins_pipe(pipe_class_default);
11444 %}
11446 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11447 match(Set dst (ReplicateB src));
11448 predicate(n->as_Vector()->length() == 8);
11449 expand %{
11450 moveReg(dst, src);
11451 repl56(dst);
11452 repl48(dst);
11453 repl32(dst);
11454 %}
11455 %}
11457 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11458 match(Set dst (ReplicateB zero));
11459 predicate(n->as_Vector()->length() == 8);
11460 format %{ "LI $dst, #0 \t// replicate8B" %}
11461 size(4);
11462 ins_encode %{
11463 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11464 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11465 %}
11466 ins_pipe(pipe_class_default);
11467 %}
11469 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11470 match(Set dst (ReplicateB src));
11471 predicate(n->as_Vector()->length() == 8);
11472 format %{ "LI $dst, #-1 \t// replicate8B" %}
11473 size(4);
11474 ins_encode %{
11475 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11476 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11477 %}
11478 ins_pipe(pipe_class_default);
11479 %}
11481 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11482 match(Set dst (ReplicateS src));
11483 predicate(n->as_Vector()->length() == 4);
11484 expand %{
11485 moveReg(dst, src);
11486 repl48(dst);
11487 repl32(dst);
11488 %}
11489 %}
11491 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11492 match(Set dst (ReplicateS zero));
11493 predicate(n->as_Vector()->length() == 4);
11494 format %{ "LI $dst, #0 \t// replicate4C" %}
11495 size(4);
11496 ins_encode %{
11497 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11498 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11499 %}
11500 ins_pipe(pipe_class_default);
11501 %}
11503 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11504 match(Set dst (ReplicateS src));
11505 predicate(n->as_Vector()->length() == 4);
11506 format %{ "LI $dst, -1 \t// replicate4C" %}
11507 size(4);
11508 ins_encode %{
11509 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11510 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11511 %}
11512 ins_pipe(pipe_class_default);
11513 %}
11515 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11516 match(Set dst (ReplicateI src));
11517 predicate(n->as_Vector()->length() == 2);
11518 ins_cost(2 * DEFAULT_COST);
11519 expand %{
11520 moveReg(dst, src);
11521 repl32(dst);
11522 %}
11523 %}
11525 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11526 match(Set dst (ReplicateI zero));
11527 predicate(n->as_Vector()->length() == 2);
11528 format %{ "LI $dst, #0 \t// replicate4C" %}
11529 size(4);
11530 ins_encode %{
11531 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11532 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11533 %}
11534 ins_pipe(pipe_class_default);
11535 %}
11537 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11538 match(Set dst (ReplicateI src));
11539 predicate(n->as_Vector()->length() == 2);
11540 format %{ "LI $dst, -1 \t// replicate4C" %}
11541 size(4);
11542 ins_encode %{
11543 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11544 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11545 %}
11546 ins_pipe(pipe_class_default);
11547 %}
11549 // Move float to int register via stack, replicate.
11550 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11551 match(Set dst (ReplicateF src));
11552 predicate(n->as_Vector()->length() == 2);
11553 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11554 expand %{
11555 stackSlotL tmpS;
11556 iRegIdst tmpI;
11557 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11558 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11559 moveReg(dst, tmpI); // Move int to long reg.
11560 repl32(dst); // Replicate bitpattern.
11561 %}
11562 %}
11564 // Replicate scalar constant to packed float values in Double register
11565 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11566 match(Set dst (ReplicateF src));
11567 predicate(n->as_Vector()->length() == 2);
11568 ins_cost(5 * DEFAULT_COST);
11570 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11571 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11572 %}
11574 // Replicate scalar zero constant to packed float values in Double register
11575 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11576 match(Set dst (ReplicateF zero));
11577 predicate(n->as_Vector()->length() == 2);
11579 format %{ "LI $dst, #0 \t// replicate2F" %}
11580 ins_encode %{
11581 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11582 __ li($dst$$Register, 0x0);
11583 %}
11584 ins_pipe(pipe_class_default);
11585 %}
11587 // ============================================================================
11588 // Safepoint Instruction
11590 instruct safePoint_poll(iRegPdst poll) %{
11591 match(SafePoint poll);
11592 predicate(LoadPollAddressFromThread);
11594 // It caused problems to add the effect that r0 is killed, but this
11595 // effect no longer needs to be mentioned, since r0 is not contained
11596 // in a reg_class.
11598 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11599 size(4);
11600 ins_encode( enc_poll(0x0, poll) );
11601 ins_pipe(pipe_class_default);
11602 %}
11604 // Safepoint without per-thread support. Load address of page to poll
11605 // as constant.
11606 // Rscratch2RegP is R12.
11607 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11608 // a seperate node so that the oop map is at the right location.
11609 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11610 match(SafePoint poll);
11611 predicate(!LoadPollAddressFromThread);
11613 // It caused problems to add the effect that r0 is killed, but this
11614 // effect no longer needs to be mentioned, since r0 is not contained
11615 // in a reg_class.
11617 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11618 ins_encode( enc_poll(0x0, poll) );
11619 ins_pipe(pipe_class_default);
11620 %}
11622 // ============================================================================
11623 // Call Instructions
11625 // Call Java Static Instruction
11627 // Schedulable version of call static node.
11628 instruct CallStaticJavaDirect(method meth) %{
11629 match(CallStaticJava);
11630 effect(USE meth);
11631 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11632 ins_cost(CALL_COST);
11634 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11636 format %{ "CALL,static $meth \t// ==> " %}
11637 size(4);
11638 ins_encode( enc_java_static_call(meth) );
11639 ins_pipe(pipe_class_call);
11640 %}
11642 // Schedulable version of call static node.
11643 instruct CallStaticJavaDirectHandle(method meth) %{
11644 match(CallStaticJava);
11645 effect(USE meth);
11646 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11647 ins_cost(CALL_COST);
11649 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11651 format %{ "CALL,static $meth \t// ==> " %}
11652 ins_encode( enc_java_handle_call(meth) );
11653 ins_pipe(pipe_class_call);
11654 %}
11656 // Call Java Dynamic Instruction
11658 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11659 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11660 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11661 // The call destination must still be placed in the constant pool.
11662 instruct CallDynamicJavaDirectSched(method meth) %{
11663 match(CallDynamicJava); // To get all the data fields we need ...
11664 effect(USE meth);
11665 predicate(false); // ... but never match.
11667 ins_field_load_ic_hi_node(loadConL_hiNode*);
11668 ins_field_load_ic_node(loadConLNode*);
11669 ins_num_consts(1 /* 1 patchable constant: call destination */);
11671 format %{ "BL \t// dynamic $meth ==> " %}
11672 size(4);
11673 ins_encode( enc_java_dynamic_call_sched(meth) );
11674 ins_pipe(pipe_class_call);
11675 %}
11677 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11678 // We use postalloc expanded calls if we use inline caches
11679 // and do not update method data.
11680 //
11681 // This instruction has two constants: inline cache (IC) and call destination.
11682 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11683 // one constant.
11684 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11685 match(CallDynamicJava);
11686 effect(USE meth);
11687 predicate(UseInlineCaches);
11688 ins_cost(CALL_COST);
11690 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11692 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11693 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11694 %}
11696 // Compound version of call dynamic java
11697 // We use postalloc expanded calls if we use inline caches
11698 // and do not update method data.
11699 instruct CallDynamicJavaDirect(method meth) %{
11700 match(CallDynamicJava);
11701 effect(USE meth);
11702 predicate(!UseInlineCaches);
11703 ins_cost(CALL_COST);
11705 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11706 ins_num_consts(4);
11708 format %{ "CALL,dynamic $meth \t// ==> " %}
11709 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11710 ins_pipe(pipe_class_call);
11711 %}
11713 // Call Runtime Instruction
11715 instruct CallRuntimeDirect(method meth) %{
11716 match(CallRuntime);
11717 effect(USE meth);
11718 ins_cost(CALL_COST);
11720 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11721 // env for callee, C-toc.
11722 ins_num_consts(3);
11724 format %{ "CALL,runtime" %}
11725 ins_encode( enc_java_to_runtime_call(meth) );
11726 ins_pipe(pipe_class_call);
11727 %}
11729 // Call Leaf
11731 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11732 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11733 effect(DEF dst, USE src);
11735 ins_num_consts(1);
11737 format %{ "MTCTR $src" %}
11738 size(4);
11739 ins_encode( enc_leaf_call_mtctr(src) );
11740 ins_pipe(pipe_class_default);
11741 %}
11743 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11744 instruct CallLeafDirect(method meth) %{
11745 match(CallLeaf); // To get the data all the data fields we need ...
11746 effect(USE meth);
11747 predicate(false); // but never match.
11749 format %{ "BCTRL \t// leaf call $meth ==> " %}
11750 size(4);
11751 ins_encode %{
11752 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11753 __ bctrl();
11754 %}
11755 ins_pipe(pipe_class_call);
11756 %}
11758 // postalloc expand of CallLeafDirect.
11759 // Load adress to call from TOC, then bl to it.
11760 instruct CallLeafDirect_Ex(method meth) %{
11761 match(CallLeaf);
11762 effect(USE meth);
11763 ins_cost(CALL_COST);
11765 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11766 // env for callee, C-toc.
11767 ins_num_consts(3);
11769 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11770 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11771 %}
11773 // Call runtime without safepoint - same as CallLeaf.
11774 // postalloc expand of CallLeafNoFPDirect.
11775 // Load adress to call from TOC, then bl to it.
11776 instruct CallLeafNoFPDirect_Ex(method meth) %{
11777 match(CallLeafNoFP);
11778 effect(USE meth);
11779 ins_cost(CALL_COST);
11781 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11782 // env for callee, C-toc.
11783 ins_num_consts(3);
11785 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11786 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11787 %}
11789 // Tail Call; Jump from runtime stub to Java code.
11790 // Also known as an 'interprocedural jump'.
11791 // Target of jump will eventually return to caller.
11792 // TailJump below removes the return address.
11793 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11794 match(TailCall jump_target method_oop);
11795 ins_cost(CALL_COST);
11797 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11798 "BCTR \t// tail call" %}
11799 size(8);
11800 ins_encode %{
11801 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11802 __ mtctr($jump_target$$Register);
11803 __ bctr();
11804 %}
11805 ins_pipe(pipe_class_call);
11806 %}
11808 // Return Instruction
11809 instruct Ret() %{
11810 match(Return);
11811 format %{ "BLR \t// branch to link register" %}
11812 size(4);
11813 ins_encode %{
11814 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11815 // LR is restored in MachEpilogNode. Just do the RET here.
11816 __ blr();
11817 %}
11818 ins_pipe(pipe_class_default);
11819 %}
11821 // Tail Jump; remove the return address; jump to target.
11822 // TailCall above leaves the return address around.
11823 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11824 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11825 // "restore" before this instruction (in Epilogue), we need to materialize it
11826 // in %i0.
11827 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11828 match(TailJump jump_target ex_oop);
11829 ins_cost(CALL_COST);
11831 format %{ "LD R4_ARG2 = LR\n\t"
11832 "MTCTR $jump_target\n\t"
11833 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11834 size(12);
11835 ins_encode %{
11836 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11837 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11838 __ mtctr($jump_target$$Register);
11839 __ bctr();
11840 %}
11841 ins_pipe(pipe_class_call);
11842 %}
11844 // Create exception oop: created by stack-crawling runtime code.
11845 // Created exception is now available to this handler, and is setup
11846 // just prior to jumping to this handler. No code emitted.
11847 instruct CreateException(rarg1RegP ex_oop) %{
11848 match(Set ex_oop (CreateEx));
11849 ins_cost(0);
11851 format %{ " -- \t// exception oop; no code emitted" %}
11852 size(0);
11853 ins_encode( /*empty*/ );
11854 ins_pipe(pipe_class_default);
11855 %}
11857 // Rethrow exception: The exception oop will come in the first
11858 // argument position. Then JUMP (not call) to the rethrow stub code.
11859 instruct RethrowException() %{
11860 match(Rethrow);
11861 ins_cost(CALL_COST);
11863 format %{ "Jmp rethrow_stub" %}
11864 ins_encode %{
11865 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11866 cbuf.set_insts_mark();
11867 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11868 %}
11869 ins_pipe(pipe_class_call);
11870 %}
11872 // Die now.
11873 instruct ShouldNotReachHere() %{
11874 match(Halt);
11875 ins_cost(CALL_COST);
11877 format %{ "ShouldNotReachHere" %}
11878 size(4);
11879 ins_encode %{
11880 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11881 __ trap_should_not_reach_here();
11882 %}
11883 ins_pipe(pipe_class_default);
11884 %}
11886 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11887 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11888 // Get a DEF on threadRegP, no costs, no encoding, use
11889 // 'ins_should_rematerialize(true)' to avoid spilling.
11890 instruct tlsLoadP(threadRegP dst) %{
11891 match(Set dst (ThreadLocal));
11892 ins_cost(0);
11894 ins_should_rematerialize(true);
11896 format %{ " -- \t// $dst=Thread::current(), empty" %}
11897 size(0);
11898 ins_encode( /*empty*/ );
11899 ins_pipe(pipe_class_empty);
11900 %}
11902 //---Some PPC specific nodes---------------------------------------------------
11904 // Stop a group.
11905 instruct endGroup() %{
11906 ins_cost(0);
11908 ins_is_nop(true);
11910 format %{ "End Bundle (ori r1, r1, 0)" %}
11911 size(4);
11912 ins_encode %{
11913 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11914 __ endgroup();
11915 %}
11916 ins_pipe(pipe_class_default);
11917 %}
11919 // Nop instructions
11921 instruct fxNop() %{
11922 ins_cost(0);
11924 ins_is_nop(true);
11926 format %{ "fxNop" %}
11927 size(4);
11928 ins_encode %{
11929 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11930 __ nop();
11931 %}
11932 ins_pipe(pipe_class_default);
11933 %}
11935 instruct fpNop0() %{
11936 ins_cost(0);
11938 ins_is_nop(true);
11940 format %{ "fpNop0" %}
11941 size(4);
11942 ins_encode %{
11943 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11944 __ fpnop0();
11945 %}
11946 ins_pipe(pipe_class_default);
11947 %}
11949 instruct fpNop1() %{
11950 ins_cost(0);
11952 ins_is_nop(true);
11954 format %{ "fpNop1" %}
11955 size(4);
11956 ins_encode %{
11957 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11958 __ fpnop1();
11959 %}
11960 ins_pipe(pipe_class_default);
11961 %}
11963 instruct brNop0() %{
11964 ins_cost(0);
11965 size(4);
11966 format %{ "brNop0" %}
11967 ins_encode %{
11968 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11969 __ brnop0();
11970 %}
11971 ins_is_nop(true);
11972 ins_pipe(pipe_class_default);
11973 %}
11975 instruct brNop1() %{
11976 ins_cost(0);
11978 ins_is_nop(true);
11980 format %{ "brNop1" %}
11981 size(4);
11982 ins_encode %{
11983 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11984 __ brnop1();
11985 %}
11986 ins_pipe(pipe_class_default);
11987 %}
11989 instruct brNop2() %{
11990 ins_cost(0);
11992 ins_is_nop(true);
11994 format %{ "brNop2" %}
11995 size(4);
11996 ins_encode %{
11997 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11998 __ brnop2();
11999 %}
12000 ins_pipe(pipe_class_default);
12001 %}
12003 //----------PEEPHOLE RULES-----------------------------------------------------
12004 // These must follow all instruction definitions as they use the names
12005 // defined in the instructions definitions.
12006 //
12007 // peepmatch ( root_instr_name [preceeding_instruction]* );
12008 //
12009 // peepconstraint %{
12010 // (instruction_number.operand_name relational_op instruction_number.operand_name
12011 // [, ...] );
12012 // // instruction numbers are zero-based using left to right order in peepmatch
12013 //
12014 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12015 // // provide an instruction_number.operand_name for each operand that appears
12016 // // in the replacement instruction's match rule
12017 //
12018 // ---------VM FLAGS---------------------------------------------------------
12019 //
12020 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12021 //
12022 // Each peephole rule is given an identifying number starting with zero and
12023 // increasing by one in the order seen by the parser. An individual peephole
12024 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12025 // on the command-line.
12026 //
12027 // ---------CURRENT LIMITATIONS----------------------------------------------
12028 //
12029 // Only match adjacent instructions in same basic block
12030 // Only equality constraints
12031 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12032 // Only one replacement instruction
12033 //
12034 // ---------EXAMPLE----------------------------------------------------------
12035 //
12036 // // pertinent parts of existing instructions in architecture description
12037 // instruct movI(eRegI dst, eRegI src) %{
12038 // match(Set dst (CopyI src));
12039 // %}
12040 //
12041 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12042 // match(Set dst (AddI dst src));
12043 // effect(KILL cr);
12044 // %}
12045 //
12046 // // Change (inc mov) to lea
12047 // peephole %{
12048 // // increment preceeded by register-register move
12049 // peepmatch ( incI_eReg movI );
12050 // // require that the destination register of the increment
12051 // // match the destination register of the move
12052 // peepconstraint ( 0.dst == 1.dst );
12053 // // construct a replacement instruction that sets
12054 // // the destination to ( move's source register + one )
12055 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12056 // %}
12057 //
12058 // Implementation no longer uses movX instructions since
12059 // machine-independent system no longer uses CopyX nodes.
12060 //
12061 // peephole %{
12062 // peepmatch ( incI_eReg movI );
12063 // peepconstraint ( 0.dst == 1.dst );
12064 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12065 // %}
12066 //
12067 // peephole %{
12068 // peepmatch ( decI_eReg movI );
12069 // peepconstraint ( 0.dst == 1.dst );
12070 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12071 // %}
12072 //
12073 // peephole %{
12074 // peepmatch ( addI_eReg_imm movI );
12075 // peepconstraint ( 0.dst == 1.dst );
12076 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12077 // %}
12078 //
12079 // peephole %{
12080 // peepmatch ( addP_eReg_imm movP );
12081 // peepconstraint ( 0.dst == 1.dst );
12082 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12083 // %}
12085 // // Change load of spilled value to only a spill
12086 // instruct storeI(memory mem, eRegI src) %{
12087 // match(Set mem (StoreI mem src));
12088 // %}
12089 //
12090 // instruct loadI(eRegI dst, memory mem) %{
12091 // match(Set dst (LoadI mem));
12092 // %}
12093 //
12094 peephole %{
12095 peepmatch ( loadI storeI );
12096 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12097 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12098 %}
12100 peephole %{
12101 peepmatch ( loadL storeL );
12102 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12103 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12104 %}
12106 peephole %{
12107 peepmatch ( loadP storeP );
12108 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12109 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12110 %}
12112 //----------SMARTSPILL RULES---------------------------------------------------
12113 // These must follow all instruction definitions as they use the names
12114 // defined in the instructions definitions.