Thu, 18 Aug 2016 11:54:02 +0800
Fix a bug in the definitions of (gslwxc1/gsldxc1/gsswxc1/gssdxc1): Register --> FloatRegister.
src/cpu/mips/vm/assembler_mips.hpp | file | annotate | diff | comparison | revisions |
1.1 --- a/src/cpu/mips/vm/assembler_mips.hpp Thu Aug 18 11:50:18 2016 +0800 1.2 +++ b/src/cpu/mips/vm/assembler_mips.hpp Thu Aug 18 11:54:02 2016 +0800 1.3 @@ -1203,12 +1203,12 @@ 1.4 int branch_destination(int inst, int pos); 1.5 1.6 /* Godson3 extension */ 1.7 - void gsldxc1(Register rt, Register base, Register index, int off) { 1.8 + void gsldxc1(FloatRegister rt, Register base, Register index, int off) { 1.9 assert(is_simm(off, 8), "gsldxc1: off exceeds 8 bits"); 1.10 emit_long((gs_ldc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gsldxc1_op); 1.11 } 1.12 1.13 - void gslwxc1(Register rt, Register base, Register index, int off) { 1.14 + void gslwxc1(FloatRegister rt, Register base, Register index, int off) { 1.15 assert(is_simm(off, 8), "gslwxc1: off exceeds 8 bits"); 1.16 emit_long((gs_ldc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gslwxc1_op); 1.17 } 1.18 @@ -1233,12 +1233,12 @@ 1.19 emit_long((gs_ldc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gslbx_op); 1.20 } 1.21 1.22 - void gssdxc1(Register rt, Register base, Register index, int off) { 1.23 + void gssdxc1(FloatRegister rt, Register base, Register index, int off) { 1.24 assert(is_simm(off, 8), "gssdxc1: off exceeds 8 bits"); 1.25 emit_long((gs_sdc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gssdxc1_op); 1.26 } 1.27 1.28 - void gsswxc1(Register rt, Register base, Register index, int off) { 1.29 + void gsswxc1(FloatRegister rt, Register base, Register index, int off) { 1.30 assert(is_simm(off, 8), "gsswxc1: off exceeds 8 bits"); 1.31 emit_long((gs_sdc2_op << 26) | ((int)base->encoding() << 21) | ((int)rt->encoding() << 16) | ((int)index->encoding() << 11) | (off << 3) | gsswxc1_op); 1.32 }