Mercurial > jdk8-mips64-public > hotspot / changeset
changeset
#7428 [C1] Refactory (base + index << scale + disp) load and store support
Fri, 24 Aug 2018 14:14:41 +0800
- author
- zhaixiang
- date
- Fri, 24 Aug 2018 14:14:41 +0800
- changeset 9219
- 0fa7c31d7b02
- parent 9218
- 03cc6174e972
- child 9220
- ef1b05ef238a
#7428 [C1] Refactory (base + index << scale + disp) load and store support
Summary: Refactory reg2mem, mem2reg and const2mem, implement rebase_Address, store_for_type and load_for_type
Reviewed-by: aoqi, fujie
1.1 --- a/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Tue Aug 21 15:43:26 2018 +0800 1.2 +++ b/src/cpu/mips/vm/c1_LIRAssembler_mips.cpp Fri Aug 24 14:14:41 2018 +0800 1.3 @@ -195,25 +195,55 @@ 1.4 1.5 1.6 Address LIR_Assembler::as_Address(LIR_Address* addr) { 1.7 -#ifndef _LP64 1.8 - Register reg = addr->base()->as_register(); 1.9 -#else 1.10 -//FIXME aoqi 1.11 - Register reg = addr->base()->is_single_cpu()? addr->base()->as_register() : addr->base()->as_register_lo(); 1.12 -#endif 1.13 - // now we need this for parameter pass 1.14 - return Address(reg, addr->disp()); 1.15 + Unimplemented(); 1.16 } 1.17 1.18 +// Register base = old register base + register index << scale + register disp(31...16 bits) 1.19 +Address LIR_Assembler::rebase_Address(LIR_Address* addr, Register disp) { 1.20 + bool disp_rebased = false; 1.21 + 1.22 + if (addr->base()->is_illegal()) { 1.23 + assert(addr->index()->is_illegal(), "must be illegal too"); 1.24 + AddressLiteral laddr((address)addr->disp(), relocInfo::none); 1.25 + Unimplemented(); 1.26 + } 1.27 + 1.28 + Register base = addr->base()->as_pointer_register(); 1.29 + if (disp != NOREG) { 1.30 + assert(!Assembler::is_simm16(addr->disp()), "must be"); 1.31 + __ add(disp, base, disp); 1.32 + disp_rebased = true; 1.33 + } 1.34 + 1.35 + if (addr->index()->is_illegal()) { 1.36 + return Address(disp_rebased ? disp : base, disp_rebased ? 0 : addr->disp()); 1.37 + } else if (addr->index()->is_cpu_register()) { 1.38 + Register index = addr->index()->as_pointer_register(); 1.39 + return Address(disp_rebased ? disp : base, index, (Address::ScaleFactor) addr->scale(), disp_rebased ? 0 : addr->disp()); 1.40 + } else if (addr->index()->is_constant()) { 1.41 + intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()); 1.42 + if (!disp_rebased) { 1.43 + addr_offset += addr->disp(); 1.44 + } 1.45 + assert(Assembler::is_simm32(addr_offset), "must be"); 1.46 + return Address(disp_rebased ? disp : base, addr_offset); 1.47 + } else { 1.48 + Unimplemented(); 1.49 + } 1.50 + 1.51 + // fall through 1.52 + ShouldNotReachHere(); 1.53 + return Address(); 1.54 +} 1.55 + 1.56 1.57 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1.58 - return as_Address(addr); 1.59 + Unimplemented(); 1.60 } 1.61 1.62 1.63 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1.64 - Register reg = addr->base()->as_register(); 1.65 - return Address(reg, addr->disp()+longSize/2); 1.66 + Unimplemented(); 1.67 } 1.68 1.69 1.70 @@ -849,49 +879,45 @@ 1.71 case T_LONG: // fall through 1.72 case T_DOUBLE: 1.73 #ifndef _LP64 1.74 + Unimplemented(); 1.75 __ move(AT, c->as_jint_hi_bits()); 1.76 __ sw(AT, as_Address_hi(addr)); 1.77 __ move(AT, c->as_jint_lo_bits()); 1.78 __ sw(AT, as_Address_lo(addr)); 1.79 #else 1.80 - if(c->as_jlong_bits() != 0) { 1.81 + if (c->as_jlong_bits() != 0) { 1.82 /* DoublePrint: -0.0 1.83 * (gdb) print /x -9223372036854775808 1.84 * $1 = 0x8000000000000000 1.85 */ 1.86 __ li64(AT, c->as_jlong_bits()); 1.87 - __ sd(AT, as_Address_lo(addr)); 1.88 - } else 1.89 - __ sd(R0, as_Address(addr)); 1.90 + __ store_for_type(AT, rebase_Address(addr), T_LONG); 1.91 + } else { 1.92 + __ store_for_type(R0, rebase_Address(addr), T_LONG); 1.93 + } 1.94 #endif 1.95 break; 1.96 case T_OBJECT: // fall through 1.97 case T_ARRAY: 1.98 if (c->as_jobject() == NULL){ 1.99 - if (UseCompressedOops && !wide) { 1.100 - __ sw(R0, as_Address(addr)); 1.101 - } else { 1.102 - __ st_ptr(R0, as_Address(addr)); 1.103 - } 1.104 + __ store_for_type(R0, rebase_Address(addr), T_OBJECT, wide); 1.105 } else { 1.106 int oop_index = __ oop_recorder()->find_index(c->as_jobject()); 1.107 RelocationHolder rspec = oop_Relocation::spec(oop_index); 1.108 __ relocate(rspec); 1.109 #ifndef _LP64 1.110 + Unimplemented(); 1.111 __ lui(AT, Assembler::split_high((int)c->as_jobject())); 1.112 __ addiu(AT, AT, Assembler::split_low((int)c->as_jobject())); 1.113 __ st_ptr(AT, as_Address(addr)); 1.114 null_check_here = code_offset(); 1.115 #else 1.116 - //by_css 1.117 __ li64(AT, (long)c->as_jobject()); 1.118 if (UseCompressedOops && !wide) { 1.119 __ encode_heap_oop(AT); 1.120 null_check_here = code_offset(); 1.121 - __ sw(AT, as_Address(addr)); 1.122 - } else { 1.123 - __ st_ptr(AT, as_Address(addr)); 1.124 } 1.125 + __ store_for_type(AT, rebase_Address(addr), T_OBJECT, wide); 1.126 #endif 1.127 } 1.128 break; 1.129 @@ -899,31 +925,31 @@ 1.130 case T_FLOAT: 1.131 if(c->as_jint_bits() != 0) { 1.132 __ move(AT, c->as_jint_bits()); 1.133 - __ sw(AT, as_Address(addr)); 1.134 + __ store_for_type(AT, rebase_Address(addr)); 1.135 } else 1.136 - __ sw(R0, as_Address(addr)); 1.137 + __ store_for_type(R0, rebase_Address(addr)); 1.138 break; 1.139 case T_ADDRESS: 1.140 __ move(AT, c->as_jint_bits()); 1.141 - __ st_ptr(AT, as_Address(addr)); 1.142 + __ store_for_type(AT, rebase_Address(addr), T_ADDRESS); 1.143 break; 1.144 case T_BOOLEAN: // fall through 1.145 case T_BYTE: 1.146 if(c->as_jint() != 0) { 1.147 __ move(AT, c->as_jint()); 1.148 - __ sb(AT, as_Address(addr)); 1.149 + __ store_for_type(AT, rebase_Address(addr), T_BYTE); 1.150 + } else { 1.151 + __ store_for_type(R0, rebase_Address(addr), T_BYTE); 1.152 } 1.153 - else 1.154 - __ sb(R0, as_Address(addr)); 1.155 break; 1.156 case T_CHAR: // fall through 1.157 case T_SHORT: 1.158 if(c->as_jint() != 0) { 1.159 __ move(AT, c->as_jint()); 1.160 - __ sh(AT, as_Address(addr)); 1.161 + __ store_for_type(AT, rebase_Address(addr), T_SHORT); 1.162 + } else { 1.163 + __ store_for_type(R0, rebase_Address(addr), T_SHORT); 1.164 } 1.165 - else 1.166 - __ sh(R0, as_Address(addr)); 1.167 break; 1.168 default: ShouldNotReachHere(); 1.169 }; 1.170 @@ -1074,27 +1100,12 @@ 1.171 } 1.172 } 1.173 1.174 -//FIXME 1.175 + 1.176 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info,bool pop_fpu_stack, bool wide, bool/*unaliged*/) { 1.177 LIR_Address* to_addr = dest->as_address_ptr(); 1.178 1.179 Register base_reg = to_addr->base()->as_pointer_register(); 1.180 1.181 - // Use T9 as a tmp reg 1.182 - Register tmp_reg = T9; 1.183 - if (to_addr->index()->is_illegal()) { 1.184 - tmp_reg = NOREG; 1.185 - } else if (to_addr->index()->is_cpu_register()) { 1.186 - Register index_reg = to_addr->index()->as_pointer_register(); 1.187 - if (to_addr->scale() != 0) { 1.188 - __ dsll(tmp_reg, index_reg, to_addr->scale()); 1.189 - } 1.190 - } else if (to_addr->index()->is_constant()) { 1.191 - __ set64(tmp_reg, to_addr->index()->as_constant_ptr()->as_jint() << to_addr->scale()); 1.192 - } else { 1.193 - Unimplemented(); 1.194 - } 1.195 - 1.196 PatchingStub* patch = NULL; 1.197 bool needs_patching = (patch_code != lir_patch_none); 1.198 Register disp_reg = NOREG; 1.199 @@ -1122,7 +1133,7 @@ 1.200 patch_code == lir_patch_none || 1.201 patch_code == lir_patch_normal, 1.202 "patching doesn't match register"); 1.203 - Address toa = as_Address(to_addr); 1.204 + Address toa = rebase_Address(to_addr); 1.205 assert(toa.disp() != 0, "must have"); 1.206 } 1.207 1.208 @@ -1131,52 +1142,47 @@ 1.209 } 1.210 if (needs_patching) { 1.211 disp_reg = AT; 1.212 - __ lui(AT, Assembler::split_high(disp_value)); 1.213 - __ addiu(AT, AT, Assembler::split_low(disp_value)); 1.214 + __ lui(disp_reg, Assembler::split_high(disp_value)); 1.215 + __ addiu(disp_reg, disp_reg, Assembler::split_low(disp_value)); 1.216 } else if (!Assembler::is_simm16(disp_value)) { 1.217 disp_reg = AT; 1.218 - __ lui(AT, Assembler::split_high(disp_value)); 1.219 + __ lui(disp_reg, Assembler::split_high(disp_value)); 1.220 } 1.221 int offset = code_offset(); 1.222 1.223 switch(type) { 1.224 case T_DOUBLE: 1.225 assert(src->is_double_fpu(), "just check"); 1.226 +#ifndef _LP64 1.227 + Unimplemented(); 1.228 if (disp_reg == noreg) { 1.229 -#ifndef _LP64 1.230 __ swc1(src->as_double_reg(), base_reg, disp_value); 1.231 - __ swc1(src->as_double_reg()+1, base_reg, disp_value+4); 1.232 -#else 1.233 - __ sdc1(src->as_double_reg(), base_reg, disp_value); 1.234 -#endif 1.235 + __ swc1(src->as_double_reg() + 1, base_reg, disp_value + 4); 1.236 } else if (needs_patching) { 1.237 __ add(AT, base_reg, disp_reg); 1.238 + __ swc1(src->as_double_reg(), AT, 0); 1.239 + __ swc1(src->as_double_reg() + 1, AT, 4); 1.240 +#else 1.241 + if (needs_patching) { 1.242 + __ store_for_type(src->as_double_reg(), rebase_Address(to_addr, disp_reg), T_DOUBLE); 1.243 +#endif 1.244 + } else { 1.245 #ifndef _LP64 1.246 - __ swc1(src->as_double_reg(), AT, 0); 1.247 - __ swc1(src->as_double_reg()+1, AT, 4); 1.248 + Unimplemented(); 1.249 + __ add(AT, base_reg, disp_reg); 1.250 + __ swc1(src->as_double_reg(), AT, Assembler::split_low(disp_value)); 1.251 + __ swc1(src->as_double_reg() + 1, AT, Assembler::split_low(disp_value) + 4); 1.252 #else 1.253 - __ sdc1(src->as_double_reg(), AT, 0); 1.254 -#endif 1.255 - } else { 1.256 - __ add(AT, base_reg, disp_reg); 1.257 -#ifndef _LP64 1.258 - __ swc1(src->as_double_reg(), AT, Assembler::split_low(disp_value)); 1.259 - __ swc1(src->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4); 1.260 -#else 1.261 - __ sdc1(src->as_double_reg(), AT, Assembler::split_low(disp_value)); 1.262 + __ store_for_type(src->as_double_reg(), rebase_Address(to_addr), T_DOUBLE); 1.263 #endif 1.264 } 1.265 break; 1.266 1.267 case T_FLOAT: 1.268 - if (disp_reg == noreg) { 1.269 - __ swc1(src->as_float_reg(), base_reg, disp_value); 1.270 - } else if(needs_patching) { 1.271 - __ add(AT, base_reg, disp_reg); 1.272 - __ swc1(src->as_float_reg(), AT, 0); 1.273 + if (needs_patching) { 1.274 + __ store_for_type(src->as_float_reg(), rebase_Address(to_addr, disp_reg), T_FLOAT); 1.275 } else { 1.276 - __ add(AT, base_reg, disp_reg); 1.277 - __ swc1(src->as_float_reg(), AT, Assembler::split_low(disp_value)); 1.278 + __ store_for_type(src->as_float_reg(), rebase_Address(to_addr), T_FLOAT); 1.279 } 1.280 break; 1.281 1.282 @@ -1185,12 +1191,12 @@ 1.283 Register from_hi = src->as_register_hi(); 1.284 #ifdef _LP64 1.285 if (needs_patching) { 1.286 - __ add(AT, base_reg, disp_reg); 1.287 - __ st_ptr(from_lo, AT, 0); 1.288 + __ store_for_type(from_lo, rebase_Address(to_addr, disp_reg), T_LONG); 1.289 } else { 1.290 - __ st_ptr(from_lo, as_Address_lo(to_addr)); 1.291 + __ store_for_type(from_lo, rebase_Address(to_addr), T_LONG); 1.292 } 1.293 #else 1.294 + Unimplemented(); 1.295 Register base = to_addr->base()->as_register(); 1.296 Register index = noreg; 1.297 if (to_addr->index()->is_register()) { 1.298 @@ -1225,68 +1231,43 @@ 1.299 case T_OBJECT: 1.300 #ifdef _LP64 1.301 if (UseCompressedOops && !wide) { 1.302 - if (disp_reg == noreg) { 1.303 - __ sw(compressed_src, base_reg, disp_value); 1.304 - } else if (needs_patching) { 1.305 - __ add(AT, base_reg, disp_reg); 1.306 - __ sw(compressed_src, AT, 0); 1.307 + if (needs_patching) { 1.308 + __ store_for_type(compressed_src, rebase_Address(to_addr, disp_reg), T_OBJECT, wide); 1.309 } else { 1.310 - __ add(AT, base_reg, disp_reg); 1.311 - __ sw(compressed_src, AT, Assembler::split_low(disp_value)); 1.312 + __ store_for_type(compressed_src, rebase_Address(to_addr), T_OBJECT, wide); 1.313 } 1.314 } else { 1.315 - if (disp_reg == noreg) { 1.316 - __ st_ptr(src->as_register(), base_reg, disp_value); 1.317 - } else if (needs_patching) { 1.318 - __ add(AT, base_reg, disp_reg); 1.319 - __ st_ptr(src->as_register(), AT, 0); 1.320 + if (needs_patching) { 1.321 + __ store_for_type(src->as_register(), rebase_Address(to_addr, disp_reg), T_OBJECT, wide); 1.322 } else { 1.323 - __ add(AT, base_reg, disp_reg); 1.324 - __ st_ptr(src->as_register(), AT, Assembler::split_low(disp_value)); 1.325 + __ store_for_type(src->as_register(), rebase_Address(to_addr), T_OBJECT, wide); 1.326 } 1.327 } 1.328 break; 1.329 #endif 1.330 case T_ADDRESS: 1.331 #ifdef _LP64 1.332 - if (disp_reg == noreg) { 1.333 - __ st_ptr(src->as_register(), base_reg, disp_value); 1.334 - } else if (needs_patching) { 1.335 - __ add(AT, base_reg, disp_reg); 1.336 - __ st_ptr(src->as_register(), AT, 0); 1.337 + if (needs_patching) { 1.338 + __ store_for_type(src->as_register(), rebase_Address(to_addr, disp_reg), T_ADDRESS); 1.339 } else { 1.340 - __ add(AT, base_reg, disp_reg); 1.341 - __ st_ptr(src->as_register(), AT, Assembler::split_low(disp_value)); 1.342 + __ store_for_type(src->as_register(), rebase_Address(to_addr), T_ADDRESS); 1.343 } 1.344 break; 1.345 #endif 1.346 case T_INT: 1.347 - if (disp_reg == noreg) { 1.348 - if (tmp_reg != NOREG) { 1.349 - __ daddu(tmp_reg, base_reg, tmp_reg); 1.350 - __ sw(src->as_register(), tmp_reg, disp_value); 1.351 - } else { 1.352 - __ sw(src->as_register(), base_reg, disp_value); 1.353 - } 1.354 - } else if (needs_patching) { 1.355 - __ add(AT, base_reg, disp_reg); 1.356 - __ sw(src->as_register(), AT, 0); 1.357 + if (needs_patching) { 1.358 + __ store_for_type(src->as_register(), rebase_Address(to_addr, disp_reg)); 1.359 } else { 1.360 - __ add(AT, base_reg, disp_reg); 1.361 - __ sw(src->as_register(), AT, Assembler::split_low(disp_value)); 1.362 + __ store_for_type(src->as_register(), rebase_Address(to_addr)); 1.363 } 1.364 break; 1.365 1.366 case T_CHAR: 1.367 case T_SHORT: 1.368 - if (disp_reg == noreg) { 1.369 - __ sh(src->as_register(), base_reg, disp_value); 1.370 - } else if (needs_patching) { 1.371 - __ add(AT, base_reg, disp_reg); 1.372 - __ sh(src->as_register(), AT, 0); 1.373 + if (needs_patching) { 1.374 + __ store_for_type(src->as_register(), rebase_Address(to_addr, disp_reg), T_SHORT); 1.375 } else { 1.376 - __ add(AT, base_reg, disp_reg); 1.377 - __ sh(src->as_register(), AT, Assembler::split_low(disp_value)); 1.378 + __ store_for_type(src->as_register(), rebase_Address(to_addr), T_SHORT); 1.379 } 1.380 break; 1.381 1.382 @@ -1294,14 +1275,10 @@ 1.383 case T_BOOLEAN: 1.384 assert(src->is_single_cpu(), "just check"); 1.385 1.386 - if (disp_reg == noreg) { 1.387 - __ sb(src->as_register(), base_reg, disp_value); 1.388 - } else if (needs_patching) { 1.389 - __ add(AT, base_reg, disp_reg); 1.390 - __ sb(src->as_register(), AT, 0); 1.391 + if (needs_patching) { 1.392 + __ store_for_type(src->as_register(), rebase_Address(to_addr, disp_reg), T_BYTE); 1.393 } else { 1.394 - __ add(AT, base_reg, disp_reg); 1.395 - __ sb(src->as_register(), AT, Assembler::split_low(disp_value)); 1.396 + __ store_for_type(src->as_register(), rebase_Address(to_addr), T_BYTE); 1.397 } 1.398 break; 1.399 1.400 @@ -1421,11 +1398,8 @@ 1.401 assert(src->is_address(), "should not call otherwise"); 1.402 assert(dest->is_register(), "should not call otherwise"); 1.403 LIR_Address* addr = src->as_address_ptr(); 1.404 - //Address from_addr = as_Address(addr); 1.405 - 1.406 - //Register src_reg = addr->base()->as_register(); 1.407 - // FIXME aoqi 1.408 - Register src_reg = addr->base()->is_single_cpu()? addr->base()->as_register() : addr->base()->as_register_lo(); 1.409 + 1.410 + Register src_reg = addr->base()->as_pointer_register(); 1.411 Register disp_reg = noreg; 1.412 int disp_value = addr->disp(); 1.413 bool needs_patching = (patch_code != lir_patch_none); 1.414 @@ -1438,11 +1412,11 @@ 1.415 // we must use lui&addiu, 1.416 if (needs_patching) { 1.417 disp_reg = AT; 1.418 - __ lui(AT, Assembler::split_high(disp_value)); 1.419 - __ addiu(AT, AT, Assembler::split_low(disp_value)); 1.420 + __ lui(disp_reg, Assembler::split_high(disp_value)); 1.421 + __ addiu(disp_reg, AT, Assembler::split_low(disp_value)); 1.422 } else if (!Assembler::is_simm16(disp_value)) { 1.423 disp_reg = AT; 1.424 - __ lui(AT, Assembler::split_high(disp_value)); 1.425 + __ lui(disp_reg, Assembler::split_high(disp_value)); 1.426 } 1.427 1.428 // remember the offset of the load. The patching_epilog must be done 1.429 @@ -1453,226 +1427,163 @@ 1.430 switch(type) { 1.431 case T_BOOLEAN: 1.432 case T_BYTE: { 1.433 - //assert(to_reg.is_word(), "just check"); 1.434 - if (disp_reg == noreg) { 1.435 - __ lb(dest->as_register(), src_reg, disp_value); 1.436 - } else if (needs_patching) { 1.437 - __ add(AT, src_reg, disp_reg); 1.438 - offset = code_offset(); 1.439 - __ lb(dest->as_register(), AT, 0); 1.440 - } else { 1.441 - __ add(AT, src_reg, disp_reg); 1.442 - offset = code_offset(); 1.443 - __ lb(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.444 - } 1.445 - } 1.446 - break; 1.447 + if (needs_patching) { 1.448 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_BYTE); 1.449 + } else { 1.450 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_BYTE); 1.451 + } 1.452 + } 1.453 + break; 1.454 1.455 case T_CHAR: { 1.456 - //assert(to_reg.is_word(), "just check"); 1.457 - if (disp_reg == noreg) { 1.458 - __ lhu(dest->as_register(), src_reg, disp_value); 1.459 - } else if (needs_patching) { 1.460 - __ add(AT, src_reg, disp_reg); 1.461 - offset = code_offset(); 1.462 - __ lhu(dest->as_register(), AT, 0); 1.463 - } else { 1.464 - __ add(AT, src_reg, disp_reg); 1.465 - offset = code_offset(); 1.466 - __ lhu(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.467 - } 1.468 - } 1.469 - break; 1.470 + if (needs_patching) { 1.471 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_CHAR); 1.472 + } else { 1.473 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_CHAR); 1.474 + } 1.475 + } 1.476 + break; 1.477 1.478 case T_SHORT: { 1.479 - // assert(to_reg.is_word(), "just check"); 1.480 - if (disp_reg == noreg) { 1.481 - __ lh(dest->as_register(), src_reg, disp_value); 1.482 - } else if (needs_patching) { 1.483 - __ add(AT, src_reg, disp_reg); 1.484 - offset = code_offset(); 1.485 - __ lh(dest->as_register(), AT, 0); 1.486 - } else { 1.487 - __ add(AT, src_reg, disp_reg); 1.488 - offset = code_offset(); 1.489 - __ lh(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.490 - } 1.491 + if (needs_patching) { 1.492 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_SHORT); 1.493 + } else { 1.494 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_SHORT); 1.495 } 1.496 - break; 1.497 + } 1.498 + break; 1.499 1.500 case T_OBJECT: 1.501 case T_ARRAY: 1.502 if (UseCompressedOops && !wide) { 1.503 - if (disp_reg == noreg) { 1.504 - __ lwu(dest->as_register(), src_reg, disp_value); 1.505 - } else if (needs_patching) { 1.506 - __ dadd(AT, src_reg, disp_reg); 1.507 - offset = code_offset(); 1.508 - __ lwu(dest->as_register(), AT, 0); 1.509 - } else { 1.510 - __ dadd(AT, src_reg, disp_reg); 1.511 - offset = code_offset(); 1.512 - __ lwu(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.513 - } 1.514 + if (needs_patching) { 1.515 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_OBJECT, wide); 1.516 + } else { 1.517 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_OBJECT, wide); 1.518 + } 1.519 } else { 1.520 - if (disp_reg == noreg) { 1.521 - __ ld_ptr(dest->as_register(), src_reg, disp_value); 1.522 - } else if (needs_patching) { 1.523 - __ dadd(AT, src_reg, disp_reg); 1.524 - offset = code_offset(); 1.525 - __ ld_ptr(dest->as_register(), AT, 0); 1.526 - } else { 1.527 - __ dadd(AT, src_reg, disp_reg); 1.528 - offset = code_offset(); 1.529 - __ ld_ptr(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.530 - } 1.531 + if (needs_patching) { 1.532 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_OBJECT, wide); 1.533 + } else { 1.534 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_OBJECT, wide); 1.535 + } 1.536 } 1.537 break; 1.538 case T_ADDRESS: 1.539 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1.540 - if (disp_reg == noreg) { 1.541 - __ lwu(dest->as_register(), src_reg, disp_value); 1.542 - } else if (needs_patching) { 1.543 - __ dadd(AT, src_reg, disp_reg); 1.544 - offset = code_offset(); 1.545 - __ lwu(dest->as_register(), AT, 0); 1.546 + if (needs_patching) { 1.547 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_ADDRESS); 1.548 } else { 1.549 - __ dadd(AT, src_reg, disp_reg); 1.550 - offset = code_offset(); 1.551 - __ lwu(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.552 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_ADDRESS); 1.553 } 1.554 } else { 1.555 - if (disp_reg == noreg) { 1.556 - __ ld_ptr(dest->as_register(), src_reg, disp_value); 1.557 - } else if (needs_patching) { 1.558 - __ dadd(AT, src_reg, disp_reg); 1.559 - offset = code_offset(); 1.560 - __ ld_ptr(dest->as_register(), AT, 0); 1.561 + if (needs_patching) { 1.562 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_ADDRESS); 1.563 } else { 1.564 - __ dadd(AT, src_reg, disp_reg); 1.565 - offset = code_offset(); 1.566 - __ ld_ptr(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.567 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_ADDRESS); 1.568 } 1.569 } 1.570 break; 1.571 case T_INT: { 1.572 - //assert(to_reg.is_word(), "just check"); 1.573 - if (disp_reg == noreg) { 1.574 - __ lw(dest->as_register(), src_reg, disp_value); 1.575 - } else if (needs_patching) { 1.576 - __ add(AT, src_reg, disp_reg); 1.577 - offset = code_offset(); 1.578 - __ lw(dest->as_register(), AT, 0); 1.579 + if (needs_patching) { 1.580 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr, disp_reg), T_INT); 1.581 } else { 1.582 - __ add(AT, src_reg, disp_reg); 1.583 - offset = code_offset(); 1.584 - __ lw(dest->as_register(), AT, Assembler::split_low(disp_value)); 1.585 + offset = __ load_for_type(dest->as_register(), rebase_Address(addr), T_INT); 1.586 } 1.587 } 1.588 break; 1.589 1.590 case T_LONG: { 1.591 - Register to_lo = dest->as_register_lo(); 1.592 - Register to_hi = dest->as_register_hi(); 1.593 + Register to_lo = dest->as_register_lo(); 1.594 + Register to_hi = dest->as_register_hi(); 1.595 #ifdef _LP64 1.596 - if (needs_patching) { 1.597 - __ add(AT, src_reg, disp_reg); 1.598 - __ ld_ptr(to_lo, AT, 0); 1.599 - } else { 1.600 - __ ld_ptr(to_lo, as_Address_lo(addr)); 1.601 - } 1.602 + if (needs_patching) { 1.603 + __ load_for_type(to_lo, rebase_Address(addr, disp_reg), T_LONG); 1.604 + } else { 1.605 + __ load_for_type(to_lo, rebase_Address(addr), T_LONG); 1.606 + } 1.607 #else 1.608 - Register base = addr->base()->as_register(); 1.609 - Register index = noreg; 1.610 - if (addr->index()->is_register()) { 1.611 - index = addr->index()->as_register(); 1.612 - } 1.613 - if ((base == to_lo && index == to_hi) ||(base == to_hi && index == to_lo)) { 1.614 - // addresses with 2 registers are only formed as a result of 1.615 - // array access so this code will never have to deal with 1.616 - // patches or null checks. 1.617 - assert(info == NULL && patch == NULL, "must be"); 1.618 - __ lea(to_hi, as_Address(addr)); 1.619 - __ lw(to_lo, Address(to_hi)); 1.620 - __ lw(to_hi, Address(to_hi, BytesPerWord)); 1.621 - } else if (base == to_lo || index == to_lo) { 1.622 - assert(base != to_hi, "can't be"); 1.623 - assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1.624 - if (needs_patching) { 1.625 - __ add(AT, src_reg, disp_reg); 1.626 - offset = code_offset(); 1.627 - __ lw(to_hi, AT, longSize/2); 1.628 - __ lw(to_lo, AT, 0); 1.629 - } else { 1.630 - __ lw(to_hi, as_Address_hi(addr)); 1.631 - __ lw(to_lo, as_Address_lo(addr)); 1.632 - } 1.633 - } else { 1.634 - assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1.635 - if (needs_patching) { 1.636 - __ add(AT, src_reg, disp_reg); 1.637 - offset = code_offset(); 1.638 - __ lw(to_lo, AT, 0); 1.639 - __ lw(to_hi, AT, longSize/2); 1.640 - } else { 1.641 - __ lw(to_lo, as_Address_lo(addr)); 1.642 - __ lw(to_hi, as_Address_hi(addr)); 1.643 - } 1.644 - } 1.645 -#endif 1.646 - } 1.647 - break; 1.648 - 1.649 - case T_FLOAT: { 1.650 - //assert(to_reg.is_float(), "just check"); 1.651 - if (disp_reg == noreg) { 1.652 - __ lwc1(dest->as_float_reg(), src_reg, disp_value); 1.653 - } else if (needs_patching) { 1.654 + Unimplemented(); 1.655 + Register base = addr->base()->as_register(); 1.656 + Register index = noreg; 1.657 + if (addr->index()->is_register()) { 1.658 + index = addr->index()->as_register(); 1.659 + } 1.660 + if ((base == to_lo && index == to_hi) ||(base == to_hi && index == to_lo)) { 1.661 + // addresses with 2 registers are only formed as a result of 1.662 + // array access so this code will never have to deal with 1.663 + // patches or null checks. 1.664 + assert(info == NULL && patch == NULL, "must be"); 1.665 + __ lea(to_hi, as_Address(addr)); 1.666 + __ lw(to_lo, Address(to_hi)); 1.667 + __ lw(to_hi, Address(to_hi, BytesPerWord)); 1.668 + } else if (base == to_lo || index == to_lo) { 1.669 + assert(base != to_hi, "can't be"); 1.670 + assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1.671 + if (needs_patching) { 1.672 __ add(AT, src_reg, disp_reg); 1.673 offset = code_offset(); 1.674 - __ lwc1(dest->as_float_reg(), AT, 0); 1.675 + __ lw(to_hi, AT, longSize/2); 1.676 + __ lw(to_lo, AT, 0); 1.677 } else { 1.678 + __ lw(to_hi, as_Address_hi(addr)); 1.679 + __ lw(to_lo, as_Address_lo(addr)); 1.680 + } 1.681 + } else { 1.682 + assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1.683 + if (needs_patching) { 1.684 __ add(AT, src_reg, disp_reg); 1.685 offset = code_offset(); 1.686 - __ lwc1(dest->as_float_reg(), AT, Assembler::split_low(disp_value)); 1.687 + __ lw(to_lo, AT, 0); 1.688 + __ lw(to_hi, AT, longSize/2); 1.689 + } else { 1.690 + __ lw(to_lo, as_Address_lo(addr)); 1.691 + __ lw(to_hi, as_Address_hi(addr)); 1.692 } 1.693 } 1.694 - break; 1.695 +#endif 1.696 + } 1.697 + break; 1.698 + 1.699 + case T_FLOAT: { 1.700 + if (needs_patching) { 1.701 + offset = __ load_for_type(dest->as_float_reg(), rebase_Address(addr, disp_reg), T_FLOAT); 1.702 + } else { 1.703 + offset = __ load_for_type(dest->as_float_reg(), rebase_Address(addr), T_FLOAT); 1.704 + } 1.705 + } 1.706 + break; 1.707 1.708 case T_DOUBLE: { 1.709 - //assert(to_reg.is_double(), "just check"); 1.710 - 1.711 - if (disp_reg == noreg) { 1.712 #ifndef _LP64 1.713 - __ lwc1(dest->as_double_reg(), src_reg, disp_value); 1.714 - __ lwc1(dest->as_double_reg()+1, src_reg, disp_value+4); 1.715 + Unimplemented(); 1.716 + if (disp_reg == noreg) { 1.717 + __ lwc1(dest->as_double_reg(), src_reg, disp_value); 1.718 + __ lwc1(dest->as_double_reg() + 1, src_reg, disp_value + 4); 1.719 + } else if (needs_patching) { 1.720 + offset = code_offset(); 1.721 + __ add(AT, src_reg, disp_reg); 1.722 + __ lwc1(dest->as_double_reg(), AT, 0); 1.723 + __ lwc1(dest->as_double_reg() + 1, AT, 4); 1.724 #else 1.725 - __ ldc1(dest->as_double_reg(), src_reg, disp_value); 1.726 -#endif 1.727 - } else if (needs_patching) { 1.728 - __ add(AT, src_reg, disp_reg); 1.729 - offset = code_offset(); 1.730 + if (needs_patching) { 1.731 + offset = __ load_for_type(dest->as_double_reg(), rebase_Address(addr, disp_reg), T_DOUBLE); 1.732 +#endif 1.733 + } else { 1.734 #ifndef _LP64 1.735 - __ lwc1(dest->as_double_reg(), AT, 0); 1.736 - __ lwc1(dest->as_double_reg()+1, AT, 4); 1.737 + Unimplemented(); 1.738 + __ add(AT, src_reg, disp_reg); 1.739 + __ lwc1(dest->as_double_reg(), AT, Assembler::split_low(disp_value)); 1.740 + __ lwc1(dest->as_double_reg() + 1, AT, Assembler::split_low(disp_value) + 4); 1.741 #else 1.742 - __ ldc1(dest->as_double_reg(), AT, 0); 1.743 -#endif 1.744 - } else { 1.745 - __ add(AT, src_reg, disp_reg); 1.746 - offset = code_offset(); 1.747 -#ifndef _LP64 1.748 - __ lwc1(dest->as_double_reg(), AT, Assembler::split_low(disp_value)); 1.749 - __ lwc1(dest->as_double_reg()+1, AT, Assembler::split_low(disp_value) + 4); 1.750 -#else 1.751 - __ ldc1(dest->as_double_reg(), AT, Assembler::split_low(disp_value)); 1.752 -#endif 1.753 - } 1.754 - } 1.755 - break; 1.756 + offset = __ load_for_type(dest->as_double_reg(), rebase_Address(addr), T_DOUBLE); 1.757 +#endif 1.758 + } 1.759 + } 1.760 + break; 1.761 1.762 default: 1.763 - ShouldNotReachHere(); 1.764 + ShouldNotReachHere(); 1.765 } 1.766 1.767 if (needs_patching) { 1.768 @@ -1681,11 +1592,11 @@ 1.769 1.770 if (type == T_ARRAY || type == T_OBJECT) { 1.771 #ifdef _LP64 1.772 - if (UseCompressedOops && !wide) { 1.773 - __ decode_heap_oop(dest->as_register()); 1.774 - } 1.775 -#endif 1.776 - __ verify_oop(dest->as_register()); 1.777 + if (UseCompressedOops && !wide) { 1.778 + __ decode_heap_oop(dest->as_register()); 1.779 + } 1.780 +#endif 1.781 + __ verify_oop(dest->as_register()); 1.782 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { 1.783 if (UseCompressedClassPointers) { 1.784 __ decode_klass_not_null(dest->as_register()); 1.785 @@ -1697,7 +1608,7 @@ 1.786 1.787 void LIR_Assembler::prefetchr(LIR_Opr src) { 1.788 LIR_Address* addr = src->as_address_ptr(); 1.789 - Address from_addr = as_Address(addr); 1.790 + Address from_addr = rebase_Address(addr); 1.791 } 1.792 1.793 1.794 @@ -2579,9 +2490,9 @@ 1.795 if (opr2->is_address()) { 1.796 //FIXME. aoqi lw or ld_ptr? 1.797 if (op->type() == T_INT) 1.798 - __ lw(AT, as_Address(opr2->pointer()->as_address())); 1.799 + __ lw(AT, rebase_Address(opr2->pointer()->as_address())); 1.800 else 1.801 - __ ld_ptr(AT, as_Address(opr2->pointer()->as_address())); 1.802 + __ ld_ptr(AT, rebase_Address(opr2->pointer()->as_address())); 1.803 } else if (opr2->is_stack()) { 1.804 //FIXME. aoqi 1.805 __ ld_ptr(AT, frame_map()->address_for_slot(opr2->single_stack_ix())); 1.806 @@ -2679,7 +2590,7 @@ 1.807 1.808 if (Assembler::is_simm16(temp_value)) { 1.809 if (opr1->is_address()) { 1.810 - __ lw(AT, as_Address(opr1->pointer()->as_address())); 1.811 + __ lw(AT, rebase_Address(opr1->pointer()->as_address())); 1.812 } else { 1.813 __ lw(AT, frame_map()->address_for_slot(opr1->single_stack_ix())); 1.814 } 1.815 @@ -4448,7 +4359,7 @@ 1.816 if (left->is_single_stack()) { 1.817 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 1.818 } else if (left->is_address()) { 1.819 - laddr = as_Address(left->as_address_ptr()); 1.820 + laddr = rebase_Address(left->as_address_ptr()); 1.821 } else { 1.822 ShouldNotReachHere(); 1.823 } 1.824 @@ -5763,7 +5674,7 @@ 1.825 Register obj = op->obj()->as_register(); 1.826 Register tmp = op->tmp()->as_pointer_register(); 1.827 Register tmp1 = T9; 1.828 - Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 1.829 + Address mdo_addr = rebase_Address(op->mdp()->as_address_ptr()); 1.830 ciKlass* exact_klass = op->exact_klass(); 1.831 intptr_t current_klass = op->current_klass(); 1.832 bool not_null = op->not_null(); 1.833 @@ -6107,7 +6018,7 @@ 1.834 assert(addr->is_address() && dest->is_register(), "check"); 1.835 Register reg; 1.836 reg = dest->as_pointer_register(); 1.837 - __ lea(reg, as_Address(addr->as_address_ptr())); 1.838 + __ lea(reg, rebase_Address(addr->as_address_ptr())); 1.839 } 1.840 1.841 1.842 @@ -6157,7 +6068,7 @@ 1.843 if(src->is_register() && dest->is_address()) { 1.844 if(src->is_double_cpu()) { 1.845 #ifdef _LP64 1.846 - __ sd(src->as_register_lo(), as_Address(dest->as_address_ptr())); 1.847 + __ sd(src->as_register_lo(), rebase_Address(dest->as_address_ptr())); 1.848 #else 1.849 Unimplemented(); 1.850 //__ sw(src->as_register_lo(), as_Address(dest->as_address_ptr())); 1.851 @@ -6166,7 +6077,7 @@ 1.852 #endif 1.853 } else if (src->is_double_fpu()) { 1.854 #ifdef _LP64 1.855 - __ sdc1(src->as_double_reg(), as_Address(dest->as_address_ptr())); 1.856 + __ sdc1(src->as_double_reg(), rebase_Address(dest->as_address_ptr())); 1.857 #else 1.858 Unimplemented(); 1.859 //__ swc1(src->as_fpu_lo(), as_Address(dest->as_address_ptr())); 1.860 @@ -6179,7 +6090,7 @@ 1.861 } else if (src->is_address() && dest->is_register()){ 1.862 if(dest->is_double_cpu()) { 1.863 #ifdef _LP64 1.864 - __ ld(dest->as_register_lo(), as_Address(src->as_address_ptr())); 1.865 + __ ld(dest->as_register_lo(), rebase_Address(src->as_address_ptr())); 1.866 #else 1.867 Unimplemented(); 1.868 // __ lw(dest->as_register_lo(), as_Address(src->as_address_ptr())); 1.869 @@ -6188,7 +6099,7 @@ 1.870 #endif 1.871 } else if (dest->is_double_fpu()) { 1.872 #ifdef _LP64 1.873 - __ ldc1(dest->as_double_reg(), as_Address(src->as_address_ptr())); 1.874 + __ ldc1(dest->as_double_reg(), rebase_Address(src->as_address_ptr())); 1.875 #else 1.876 Unimplemented(); 1.877 // __ lwc1(dest->as_fpu_lo(), as_Address(src->as_address_ptr()));
2.1 --- a/src/cpu/mips/vm/c1_LIRAssembler_mips.hpp Tue Aug 21 15:43:26 2018 +0800 2.2 +++ b/src/cpu/mips/vm/c1_LIRAssembler_mips.hpp Fri Aug 24 14:14:41 2018 +0800 2.3 @@ -40,9 +40,8 @@ 2.4 2.5 bool is_literal_address(LIR_Address* addr); 2.6 2.7 - // When we need to use something other than rscratch1 use this 2.8 - // method. 2.9 - Address as_Address(LIR_Address* addr, Register tmp); 2.10 + // Reset base register 2.11 + Address rebase_Address(LIR_Address* addr, Register tmp = NOREG); 2.12 2.13 // Record the type of the receiver in ReceiverTypeData 2.14 void type_profile_helper(Register mdo,
3.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp Tue Aug 21 15:43:26 2018 +0800 3.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp Fri Aug 24 14:14:41 2018 +0800 3.3 @@ -4155,3 +4155,221 @@ 3.4 3.5 pop(tmp); 3.6 } 3.7 + 3.8 +void MacroAssembler::store_for_type_by_register(Register src_reg, Register tmp_reg, int disp, BasicType type, bool wide) { 3.9 + switch (type) { 3.10 + case T_LONG: 3.11 + st_ptr(src_reg, tmp_reg, disp); 3.12 + break; 3.13 + case T_ARRAY: 3.14 + case T_OBJECT: 3.15 + if (UseCompressedOops && !wide) { 3.16 + sw(src_reg, tmp_reg, disp); 3.17 + } else { 3.18 + st_ptr(src_reg, tmp_reg, disp); 3.19 + } 3.20 + break; 3.21 + case T_ADDRESS: 3.22 + st_ptr(src_reg, tmp_reg, disp); 3.23 + break; 3.24 + case T_INT: 3.25 + sw(src_reg, tmp_reg, disp); 3.26 + break; 3.27 + case T_CHAR: 3.28 + case T_SHORT: 3.29 + sh(src_reg, tmp_reg, disp); 3.30 + break; 3.31 + case T_BYTE: 3.32 + case T_BOOLEAN: 3.33 + sb(src_reg, tmp_reg, disp); 3.34 + break; 3.35 + default: 3.36 + ShouldNotReachHere(); 3.37 + } 3.38 +} 3.39 + 3.40 +void MacroAssembler::store_for_type(Register src_reg, Address addr, BasicType type, bool wide) { 3.41 + Register tmp_reg = T9; 3.42 + Register index_reg = addr.index(); 3.43 + if (index_reg == NOREG) { 3.44 + tmp_reg = NOREG; 3.45 + } 3.46 + 3.47 + int scale = addr.scale(); 3.48 + if (tmp_reg != NOREG && scale >= 0) { 3.49 + dsll(tmp_reg, index_reg, scale); 3.50 + } 3.51 + 3.52 + int disp = addr.disp(); 3.53 + guarantee(Assembler::is_simm16(disp), "must be"); 3.54 + 3.55 + Register base_reg = addr.base(); 3.56 + if (tmp_reg != NOREG) { 3.57 + assert_different_registers(tmp_reg, base_reg, index_reg); 3.58 + } 3.59 + 3.60 + if (tmp_reg != NOREG) { 3.61 + daddu(tmp_reg, base_reg, tmp_reg); 3.62 + store_for_type_by_register(src_reg, tmp_reg, disp, type, wide); 3.63 + } else { 3.64 + store_for_type_by_register(src_reg, base_reg, disp, type, wide); 3.65 + } 3.66 +} 3.67 + 3.68 +void MacroAssembler::store_for_type_by_register(FloatRegister src_reg, Register tmp_reg, int disp, BasicType type) { 3.69 + switch (type) { 3.70 + case T_DOUBLE: 3.71 + sdc1(src_reg, tmp_reg, disp); 3.72 + break; 3.73 + case T_FLOAT: 3.74 + swc1(src_reg, tmp_reg, disp); 3.75 + break; 3.76 + default: 3.77 + ShouldNotReachHere(); 3.78 + } 3.79 +} 3.80 + 3.81 +void MacroAssembler::store_for_type(FloatRegister src_reg, Address addr, BasicType type) { 3.82 + Register tmp_reg = T9; 3.83 + Register index_reg = addr.index(); 3.84 + if (index_reg == NOREG) { 3.85 + tmp_reg = NOREG; 3.86 + } 3.87 + 3.88 + int scale = addr.scale(); 3.89 + if (tmp_reg != NOREG && scale >= 0) { 3.90 + dsll(tmp_reg, index_reg, scale); 3.91 + } 3.92 + 3.93 + int disp = addr.disp(); 3.94 + guarantee(Assembler::is_simm16(disp), "must be"); 3.95 + 3.96 + Register base_reg = addr.base(); 3.97 + if (tmp_reg != NOREG) { 3.98 + assert_different_registers(tmp_reg, base_reg, index_reg); 3.99 + } 3.100 + 3.101 + if (tmp_reg != NOREG) { 3.102 + daddu(tmp_reg, base_reg, tmp_reg); 3.103 + store_for_type_by_register(src_reg, tmp_reg, disp, type); 3.104 + } else { 3.105 + store_for_type_by_register(src_reg, base_reg, disp, type); 3.106 + } 3.107 +} 3.108 + 3.109 +void MacroAssembler::load_for_type_by_register(Register dst_reg, Register tmp_reg, int disp, BasicType type, bool wide) { 3.110 + switch (type) { 3.111 + case T_LONG: 3.112 + ld_ptr(dst_reg, tmp_reg, disp); 3.113 + break; 3.114 + case T_ARRAY: 3.115 + case T_OBJECT: 3.116 + if (UseCompressedOops && !wide) { 3.117 + lwu(dst_reg, tmp_reg, disp); 3.118 + } else { 3.119 + ld_ptr(dst_reg, tmp_reg, disp); 3.120 + } 3.121 + break; 3.122 + case T_ADDRESS: 3.123 + if (UseCompressedClassPointers && disp == oopDesc::klass_offset_in_bytes()) { 3.124 + lwu(dst_reg, tmp_reg, disp); 3.125 + } else { 3.126 + ld_ptr(dst_reg, tmp_reg, disp); 3.127 + } 3.128 + break; 3.129 + case T_INT: 3.130 + lw(dst_reg, tmp_reg, disp); 3.131 + break; 3.132 + case T_CHAR: 3.133 + lhu(dst_reg, tmp_reg, disp); 3.134 + break; 3.135 + case T_SHORT: 3.136 + lh(dst_reg, tmp_reg, disp); 3.137 + break; 3.138 + case T_BYTE: 3.139 + case T_BOOLEAN: 3.140 + lb(dst_reg, tmp_reg, disp); 3.141 + break; 3.142 + default: 3.143 + ShouldNotReachHere(); 3.144 + } 3.145 +} 3.146 + 3.147 +int MacroAssembler::load_for_type(Register dst_reg, Address addr, BasicType type, bool wide) { 3.148 + int code_offset = 0; 3.149 + Register tmp_reg = T9; 3.150 + Register index_reg = addr.index(); 3.151 + if (index_reg == NOREG) { 3.152 + tmp_reg = NOREG; 3.153 + } 3.154 + 3.155 + int scale = addr.scale(); 3.156 + if (tmp_reg != NOREG && scale >= 0) { 3.157 + dsll(tmp_reg, index_reg, scale); 3.158 + } 3.159 + 3.160 + int disp = addr.disp(); 3.161 + guarantee(Assembler::is_simm16(disp), "must be"); 3.162 + 3.163 + Register base_reg = addr.base(); 3.164 + if (tmp_reg != NOREG) { 3.165 + assert_different_registers(tmp_reg, base_reg, index_reg); 3.166 + } 3.167 + 3.168 + if (tmp_reg != NOREG) { 3.169 + daddu(tmp_reg, base_reg, tmp_reg); 3.170 + code_offset = offset(); 3.171 + load_for_type_by_register(dst_reg, tmp_reg, disp, type, wide); 3.172 + } else { 3.173 + code_offset = offset(); 3.174 + load_for_type_by_register(dst_reg, base_reg, disp, type, wide); 3.175 + } 3.176 + 3.177 + return code_offset; 3.178 +} 3.179 + 3.180 +void MacroAssembler::load_for_type_by_register(FloatRegister dst_reg, Register tmp_reg, int disp, BasicType type) { 3.181 + switch (type) { 3.182 + case T_DOUBLE: 3.183 + ldc1(dst_reg, tmp_reg, disp); 3.184 + break; 3.185 + case T_FLOAT: 3.186 + lwc1(dst_reg, tmp_reg, disp); 3.187 + break; 3.188 + default: 3.189 + ShouldNotReachHere(); 3.190 + } 3.191 +} 3.192 + 3.193 +int MacroAssembler::load_for_type(FloatRegister dst_reg, Address addr, BasicType type) { 3.194 + int code_offset = 0; 3.195 + Register tmp_reg = T9; 3.196 + Register index_reg = addr.index(); 3.197 + if (index_reg == NOREG) { 3.198 + tmp_reg = NOREG; 3.199 + } 3.200 + 3.201 + int scale = addr.scale(); 3.202 + if (tmp_reg != NOREG && scale >= 0) { 3.203 + dsll(tmp_reg, index_reg, scale); 3.204 + } 3.205 + 3.206 + int disp = addr.disp(); 3.207 + guarantee(Assembler::is_simm16(disp), "must be"); 3.208 + 3.209 + Register base_reg = addr.base(); 3.210 + if (tmp_reg != NOREG) { 3.211 + assert_different_registers(tmp_reg, base_reg, index_reg); 3.212 + } 3.213 + 3.214 + if (tmp_reg != NOREG) { 3.215 + daddu(tmp_reg, base_reg, tmp_reg); 3.216 + code_offset = offset(); 3.217 + load_for_type_by_register(dst_reg, tmp_reg, disp, type); 3.218 + } else { 3.219 + code_offset = offset(); 3.220 + load_for_type_by_register(dst_reg, base_reg, disp, type); 3.221 + } 3.222 + 3.223 + return code_offset; 3.224 +}
4.1 --- a/src/cpu/mips/vm/macroAssembler_mips.hpp Tue Aug 21 15:43:26 2018 +0800 4.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.hpp Fri Aug 24 14:14:41 2018 +0800 4.3 @@ -722,6 +722,14 @@ 4.4 void mov_metadata(Register dst, Metadata* obj); 4.5 void mov_metadata(Address dst, Metadata* obj); 4.6 4.7 + void store_for_type_by_register(Register src_reg, Register tmp_reg, int disp, BasicType type, bool wide); 4.8 + void store_for_type_by_register(FloatRegister src_reg, Register tmp_reg, int disp, BasicType type); 4.9 + void store_for_type(Register src_reg, Address addr, BasicType type = T_INT, bool wide = false); 4.10 + void store_for_type(FloatRegister src_reg, Address addr, BasicType type = T_INT); 4.11 + void load_for_type_by_register(Register dst_reg, Register tmp_reg, int disp, BasicType type, bool wide); 4.12 + void load_for_type_by_register(FloatRegister dst_reg, Register tmp_reg, int disp, BasicType type); 4.13 + int load_for_type(Register dst_reg, Address addr, BasicType type = T_INT, bool wide = false); 4.14 + int load_for_type(FloatRegister dst_reg, Address addr, BasicType type = T_INT); 4.15 4.16 #ifndef PRODUCT 4.17 static void pd_print_patched_instruction(address branch) {
