1.1 --- a/src/cpu/mips/vm/macroAssembler_mips.cpp Tue Aug 21 15:43:26 2018 +0800
1.2 +++ b/src/cpu/mips/vm/macroAssembler_mips.cpp Fri Aug 24 14:14:41 2018 +0800
1.3 @@ -4155,3 +4155,221 @@
1.4
1.5 pop(tmp);
1.6 }
1.7 +
1.8 +void MacroAssembler::store_for_type_by_register(Register src_reg, Register tmp_reg, int disp, BasicType type, bool wide) {
1.9 + switch (type) {
1.10 + case T_LONG:
1.11 + st_ptr(src_reg, tmp_reg, disp);
1.12 + break;
1.13 + case T_ARRAY:
1.14 + case T_OBJECT:
1.15 + if (UseCompressedOops && !wide) {
1.16 + sw(src_reg, tmp_reg, disp);
1.17 + } else {
1.18 + st_ptr(src_reg, tmp_reg, disp);
1.19 + }
1.20 + break;
1.21 + case T_ADDRESS:
1.22 + st_ptr(src_reg, tmp_reg, disp);
1.23 + break;
1.24 + case T_INT:
1.25 + sw(src_reg, tmp_reg, disp);
1.26 + break;
1.27 + case T_CHAR:
1.28 + case T_SHORT:
1.29 + sh(src_reg, tmp_reg, disp);
1.30 + break;
1.31 + case T_BYTE:
1.32 + case T_BOOLEAN:
1.33 + sb(src_reg, tmp_reg, disp);
1.34 + break;
1.35 + default:
1.36 + ShouldNotReachHere();
1.37 + }
1.38 +}
1.39 +
1.40 +void MacroAssembler::store_for_type(Register src_reg, Address addr, BasicType type, bool wide) {
1.41 + Register tmp_reg = T9;
1.42 + Register index_reg = addr.index();
1.43 + if (index_reg == NOREG) {
1.44 + tmp_reg = NOREG;
1.45 + }
1.46 +
1.47 + int scale = addr.scale();
1.48 + if (tmp_reg != NOREG && scale >= 0) {
1.49 + dsll(tmp_reg, index_reg, scale);
1.50 + }
1.51 +
1.52 + int disp = addr.disp();
1.53 + guarantee(Assembler::is_simm16(disp), "must be");
1.54 +
1.55 + Register base_reg = addr.base();
1.56 + if (tmp_reg != NOREG) {
1.57 + assert_different_registers(tmp_reg, base_reg, index_reg);
1.58 + }
1.59 +
1.60 + if (tmp_reg != NOREG) {
1.61 + daddu(tmp_reg, base_reg, tmp_reg);
1.62 + store_for_type_by_register(src_reg, tmp_reg, disp, type, wide);
1.63 + } else {
1.64 + store_for_type_by_register(src_reg, base_reg, disp, type, wide);
1.65 + }
1.66 +}
1.67 +
1.68 +void MacroAssembler::store_for_type_by_register(FloatRegister src_reg, Register tmp_reg, int disp, BasicType type) {
1.69 + switch (type) {
1.70 + case T_DOUBLE:
1.71 + sdc1(src_reg, tmp_reg, disp);
1.72 + break;
1.73 + case T_FLOAT:
1.74 + swc1(src_reg, tmp_reg, disp);
1.75 + break;
1.76 + default:
1.77 + ShouldNotReachHere();
1.78 + }
1.79 +}
1.80 +
1.81 +void MacroAssembler::store_for_type(FloatRegister src_reg, Address addr, BasicType type) {
1.82 + Register tmp_reg = T9;
1.83 + Register index_reg = addr.index();
1.84 + if (index_reg == NOREG) {
1.85 + tmp_reg = NOREG;
1.86 + }
1.87 +
1.88 + int scale = addr.scale();
1.89 + if (tmp_reg != NOREG && scale >= 0) {
1.90 + dsll(tmp_reg, index_reg, scale);
1.91 + }
1.92 +
1.93 + int disp = addr.disp();
1.94 + guarantee(Assembler::is_simm16(disp), "must be");
1.95 +
1.96 + Register base_reg = addr.base();
1.97 + if (tmp_reg != NOREG) {
1.98 + assert_different_registers(tmp_reg, base_reg, index_reg);
1.99 + }
1.100 +
1.101 + if (tmp_reg != NOREG) {
1.102 + daddu(tmp_reg, base_reg, tmp_reg);
1.103 + store_for_type_by_register(src_reg, tmp_reg, disp, type);
1.104 + } else {
1.105 + store_for_type_by_register(src_reg, base_reg, disp, type);
1.106 + }
1.107 +}
1.108 +
1.109 +void MacroAssembler::load_for_type_by_register(Register dst_reg, Register tmp_reg, int disp, BasicType type, bool wide) {
1.110 + switch (type) {
1.111 + case T_LONG:
1.112 + ld_ptr(dst_reg, tmp_reg, disp);
1.113 + break;
1.114 + case T_ARRAY:
1.115 + case T_OBJECT:
1.116 + if (UseCompressedOops && !wide) {
1.117 + lwu(dst_reg, tmp_reg, disp);
1.118 + } else {
1.119 + ld_ptr(dst_reg, tmp_reg, disp);
1.120 + }
1.121 + break;
1.122 + case T_ADDRESS:
1.123 + if (UseCompressedClassPointers && disp == oopDesc::klass_offset_in_bytes()) {
1.124 + lwu(dst_reg, tmp_reg, disp);
1.125 + } else {
1.126 + ld_ptr(dst_reg, tmp_reg, disp);
1.127 + }
1.128 + break;
1.129 + case T_INT:
1.130 + lw(dst_reg, tmp_reg, disp);
1.131 + break;
1.132 + case T_CHAR:
1.133 + lhu(dst_reg, tmp_reg, disp);
1.134 + break;
1.135 + case T_SHORT:
1.136 + lh(dst_reg, tmp_reg, disp);
1.137 + break;
1.138 + case T_BYTE:
1.139 + case T_BOOLEAN:
1.140 + lb(dst_reg, tmp_reg, disp);
1.141 + break;
1.142 + default:
1.143 + ShouldNotReachHere();
1.144 + }
1.145 +}
1.146 +
1.147 +int MacroAssembler::load_for_type(Register dst_reg, Address addr, BasicType type, bool wide) {
1.148 + int code_offset = 0;
1.149 + Register tmp_reg = T9;
1.150 + Register index_reg = addr.index();
1.151 + if (index_reg == NOREG) {
1.152 + tmp_reg = NOREG;
1.153 + }
1.154 +
1.155 + int scale = addr.scale();
1.156 + if (tmp_reg != NOREG && scale >= 0) {
1.157 + dsll(tmp_reg, index_reg, scale);
1.158 + }
1.159 +
1.160 + int disp = addr.disp();
1.161 + guarantee(Assembler::is_simm16(disp), "must be");
1.162 +
1.163 + Register base_reg = addr.base();
1.164 + if (tmp_reg != NOREG) {
1.165 + assert_different_registers(tmp_reg, base_reg, index_reg);
1.166 + }
1.167 +
1.168 + if (tmp_reg != NOREG) {
1.169 + daddu(tmp_reg, base_reg, tmp_reg);
1.170 + code_offset = offset();
1.171 + load_for_type_by_register(dst_reg, tmp_reg, disp, type, wide);
1.172 + } else {
1.173 + code_offset = offset();
1.174 + load_for_type_by_register(dst_reg, base_reg, disp, type, wide);
1.175 + }
1.176 +
1.177 + return code_offset;
1.178 +}
1.179 +
1.180 +void MacroAssembler::load_for_type_by_register(FloatRegister dst_reg, Register tmp_reg, int disp, BasicType type) {
1.181 + switch (type) {
1.182 + case T_DOUBLE:
1.183 + ldc1(dst_reg, tmp_reg, disp);
1.184 + break;
1.185 + case T_FLOAT:
1.186 + lwc1(dst_reg, tmp_reg, disp);
1.187 + break;
1.188 + default:
1.189 + ShouldNotReachHere();
1.190 + }
1.191 +}
1.192 +
1.193 +int MacroAssembler::load_for_type(FloatRegister dst_reg, Address addr, BasicType type) {
1.194 + int code_offset = 0;
1.195 + Register tmp_reg = T9;
1.196 + Register index_reg = addr.index();
1.197 + if (index_reg == NOREG) {
1.198 + tmp_reg = NOREG;
1.199 + }
1.200 +
1.201 + int scale = addr.scale();
1.202 + if (tmp_reg != NOREG && scale >= 0) {
1.203 + dsll(tmp_reg, index_reg, scale);
1.204 + }
1.205 +
1.206 + int disp = addr.disp();
1.207 + guarantee(Assembler::is_simm16(disp), "must be");
1.208 +
1.209 + Register base_reg = addr.base();
1.210 + if (tmp_reg != NOREG) {
1.211 + assert_different_registers(tmp_reg, base_reg, index_reg);
1.212 + }
1.213 +
1.214 + if (tmp_reg != NOREG) {
1.215 + daddu(tmp_reg, base_reg, tmp_reg);
1.216 + code_offset = offset();
1.217 + load_for_type_by_register(dst_reg, tmp_reg, disp, type);
1.218 + } else {
1.219 + code_offset = offset();
1.220 + load_for_type_by_register(dst_reg, base_reg, disp, type);
1.221 + }
1.222 +
1.223 + return code_offset;
1.224 +}
