Mercurial > jdk8-mips64-public > hotspot / changeset

     1.1 --- a/src/cpu/mips/vm/assembler_mips.cpp	Thu Mar 16 21:58:58 2017 +0800
     1.2 +++ b/src/cpu/mips/vm/assembler_mips.cpp	Fri Mar 17 22:15:27 2017 +0800
     1.3 @@ -522,7 +522,7 @@
     1.4  }
     1.5  
     1.6  void MacroAssembler::general_j(address entry) {
     1.7 -#ifdef MIPS64
     1.8 +#ifdef _LP64
     1.9  	int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xfffffffff0000000))>>2;
    1.10  #else
    1.11  	int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xf0000000))>>2;
    1.12 @@ -532,30 +532,34 @@
    1.13            nop();
    1.14            nop();
    1.15            nop();
    1.16 +          nop();
    1.17 +          nop();
    1.18          } else {
    1.19            patchable_set48(T9, (long)entry);
    1.20 +          jr(T9);
    1.21 +          nop();
    1.22          }
    1.23  
    1.24 -        jr(T9);
    1.25 -        nop();
    1.26  }
    1.27  
    1.28  void MacroAssembler::general_jal(address entry) {
    1.29 -#ifdef MIPS64
    1.30 +#ifdef _LP64
    1.31  	int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xfffffffff0000000))>>2;
    1.32  #else
    1.33  	int dest = ((intptr_t)entry - (((intptr_t)pc() + 4) & 0xf0000000))>>2;
    1.34  #endif
    1.35          if ((dest >= 0) && (dest < (1<<26))) {
    1.36 +          nop();
    1.37 +          nop();
    1.38 +          nop();
    1.39 +          nop();
    1.40            emit_long((jal_op<<26) | dest); 
    1.41            nop();
    1.42 -          nop();
    1.43 -          nop();
    1.44          } else {
    1.45            patchable_set48(T9, (long)entry);
    1.46 +          jalr(T9);
    1.47 +          nop();
    1.48          }
    1.49 -        jalr(T9);
    1.50 -        nop();
    1.51  }
    1.52  
    1.53  void MacroAssembler::beq_far(Register rs, Register rt, address entry)
    1.54 @@ -1131,9 +1135,7 @@
    1.55  	assert(entry != NULL, "call most probably wrong");
    1.56  	InstructionMark im(this);
    1.57  	relocate(rh);
    1.58 -	patchable_set48(T9, (long)entry);
    1.59 -	jalr(T9);
    1.60 -	delayed()->nop();
    1.61 +        general_jal(entry);
    1.62  }
    1.63  
    1.64  void MacroAssembler::c2bool(Register r) {

     2.1 --- a/src/cpu/mips/vm/disassembler_mips.cpp	Thu Mar 16 21:58:58 2017 +0800
     2.2 +++ b/src/cpu/mips/vm/disassembler_mips.cpp	Fri Mar 17 22:15:27 2017 +0800
     2.3 @@ -123,7 +123,7 @@
     2.4    env->print_label( (intptr_t)start + 4 + ((short)Assembler::low16(insn)<<2) ) 
     2.5  
     2.6  #define PRINT_J(OP) \
     2.7 -  env->print((char*)OP); \
     2.8 +  env->print("%s ", (char*)OP); \
     2.9    env->print_label( ( ( (intptr_t)start + 4 ) & 0xc0000000 ) | ( Assembler::low26(insn) << 2 ) ); \
    2.10    env->print("");
    2.11  

     3.1 --- a/src/cpu/mips/vm/mips_64.ad	Thu Mar 16 21:58:58 2017 +0800
     3.2 +++ b/src/cpu/mips/vm/mips_64.ad	Fri Mar 17 22:15:27 2017 +0800
     3.3 @@ -3395,9 +3395,7 @@
     3.4        __ relocate(relocInfo::static_call_type);
     3.5      }
     3.6  
     3.7 -    __ patchable_set48(T9, $meth$$method);
     3.8 -    __ jalr(T9);
     3.9 -    __ nop();
    3.10 +    __ general_jal((address)($meth$$method));
    3.11      if( _method ) {  // Emit stub for static call
    3.12        emit_java_to_interp(cbuf);
    3.13      }

     4.1 --- a/src/cpu/mips/vm/nativeInst_mips.cpp	Thu Mar 16 21:58:58 2017 +0800
     4.2 +++ b/src/cpu/mips/vm/nativeInst_mips.cpp	Fri Mar 17 22:15:27 2017 +0800
     4.3 @@ -120,6 +120,21 @@
     4.4    }
     4.5  #else
     4.6  
     4.7 +  // nop
     4.8 +  // nop
     4.9 +  // nop
    4.10 +  // nop
    4.11 +  // jal targe 
    4.12 +  // nop
    4.13 +  if ( is_nop() &&
    4.14 +	nativeInstruction_at(addr_at(4))->is_nop()   &&
    4.15 +	nativeInstruction_at(addr_at(8))->is_nop()   &&
    4.16 +	nativeInstruction_at(addr_at(12))->is_nop()  &&
    4.17 +	is_op(int_at(16), Assembler::jal_op)  &&
    4.18 +	nativeInstruction_at(addr_at(20))->is_nop() ) {
    4.19 +      return;
    4.20 +  }
    4.21 +
    4.22    // li64
    4.23    if ( is_op(Assembler::lui_op) &&
    4.24  	is_op(int_at(4), Assembler::ori_op) &&
    4.25 @@ -236,6 +251,24 @@
    4.26    return (address)Assembler::merge(int_at(4)&0xffff, long_at(0)&0xffff);
    4.27  #else
    4.28  
    4.29 +  // nop
    4.30 +  // nop
    4.31 +  // nop
    4.32 +  // nop 
    4.33 +  // jal target
    4.34 +  // nop
    4.35 +  if ( nativeInstruction_at(addr_at(0))->is_nop() &&
    4.36 +	nativeInstruction_at(addr_at(4))->is_nop()   &&
    4.37 +	nativeInstruction_at(addr_at(8))->is_nop()   &&
    4.38 +	nativeInstruction_at(addr_at(12))->is_nop()  &&
    4.39 +	is_op(int_at(16), Assembler::jal_op)         &&
    4.40 +	nativeInstruction_at(addr_at(20))->is_nop()) {
    4.41 +      int instr_index = int_at(16) & 0x3ffffff;
    4.42 +      intptr_t target_high = ((intptr_t)addr_at(20)) & 0xfffffffff0000000; 
    4.43 +      intptr_t target = target_high | (instr_index << 2);
    4.44 +      return (address)target;
    4.45 +  }
    4.46 +
    4.47    // li64
    4.48    if ( is_op(Assembler::lui_op) &&
    4.49          is_op(int_at(4), Assembler::ori_op) &&
    4.50 @@ -358,6 +391,7 @@
    4.51        }
    4.52    }
    4.53  
    4.54 +  fatal("not a call");
    4.55  #endif
    4.56  }
    4.57  
    4.58 @@ -390,9 +424,42 @@
    4.59    return p;
    4.60  }
    4.61  
    4.62 +void  NativeCall::patch_on_jal_gs(address dst) {
    4.63 +#ifdef _LP64
    4.64 +        long dest = ((long)dst - (((long)addr_at(20)) & 0xfffffffff0000000))>>2;
    4.65 +#else
    4.66 +        long dest = ((long)dst - (((long)addr_at(20)) & 0xf0000000))>>2;
    4.67 +#endif
    4.68 +        if ((dest >= 0) && (dest < (1<<26))) {
    4.69 +          jint jal_inst = (Assembler::jal_op << 26) | dest;
    4.70 +          set_int_at(16, jal_inst);
    4.71 +          ICache::invalidate_range(addr_at(16), 4);
    4.72 +        } else {
    4.73 +          patch_set48_gs(dst);
    4.74 +          ICache::invalidate_range(addr_at(0), 16);
    4.75 +          guarantee(false, "Not implement yet !");
    4.76 +        }
    4.77 +}
    4.78 +
    4.79 +void  NativeCall::patch_on_jal(address dst) {
    4.80 +          guarantee(false, "Not implement yet !");
    4.81 +}
    4.82 +
    4.83 +void  NativeCall::patch_on_jalr_gs(address dst) {
    4.84 +          patch_set48_gs(dst);
    4.85 +          ICache::invalidate_range(addr_at(0), 16);
    4.86 +}
    4.87 +
    4.88 +void  NativeCall::patch_on_jalr(address dst) {
    4.89 +          guarantee(false, "Not implement yet !");
    4.90 +}
    4.91 +
    4.92  void  NativeCall::patch_set48_gs(address dest) {
    4.93    jlong value = (jlong) dest;
    4.94    int  rt_reg = (int_at(0) & (0x1f << 16));
    4.95 +
    4.96 +  if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9 
    4.97 +
    4.98    int  rs_reg = rt_reg << 5;
    4.99    int  rd_reg = rt_reg >> 5;
   4.100  
   4.101 @@ -471,6 +538,9 @@
   4.102  void  NativeCall::patch_set32_gs(address dest) {
   4.103    jlong value = (jlong) dest;
   4.104    int  rt_reg = (int_at(0) & (0x1f << 16));
   4.105 +
   4.106 +  if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9 
   4.107 +
   4.108    int  rs_reg = rt_reg << 5;
   4.109    int  rd_reg = rt_reg >> 5;
   4.110  
   4.111 @@ -520,6 +590,9 @@
   4.112  void  NativeCall::patch_set48(address dest) {
   4.113    jlong value = (jlong) dest;
   4.114    int  rt_reg = (int_at(0) & (0x1f << 16));
   4.115 +
   4.116 +  if (rt_reg == 0) rt_reg = 25 << 16; // r25 is T9 
   4.117 +
   4.118    int  rs_reg = rt_reg << 5;
   4.119    int  rd_reg = rt_reg >> 5;
   4.120  
   4.121 @@ -601,14 +674,20 @@
   4.122        set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
   4.123        set_int_at(0, (first_word & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 48) & 0xffff));
   4.124        ICache::invalidate_range(addr_at(0), 24);
   4.125 -  } else if (is_special_op(int_at(16), Assembler::jalr_op)) {
   4.126 +  } else if (is_op(int_at(16), Assembler::jal_op)) {
   4.127      if (UseLoongsonISA) {
   4.128        guarantee(!os::is_MP() || (((long)addr_at(0) % 16) == 0), "destination must be aligned for GSSD");
   4.129 -      patch_set48_gs(dest);
   4.130 +      patch_on_jal_gs(dest);
   4.131      } else {
   4.132 -      patch_set48(dest);
   4.133 +      patch_on_jal(dest);
   4.134      }
   4.135 -    ICache::invalidate_range(addr_at(0), 16);
   4.136 +  } else if (is_special_op(int_at(16), Assembler::jalr_op)) { 
   4.137 +    if (UseLoongsonISA) {
   4.138 +      guarantee(!os::is_MP() || (((long)addr_at(0) % 16) == 0), "destination must be aligned for GSSD");
   4.139 +      patch_on_jalr_gs(dest);
   4.140 +    } else {
   4.141 +      patch_on_jalr(dest);
   4.142 +    }
   4.143    } else if (is_special_op(int_at(8), Assembler::jalr_op)) {
   4.144      guarantee(!os::is_MP() || (((long)addr_at(0) % 8) == 0), "destination must be aligned by 8");
   4.145      if (UseLoongsonISA) {

     5.1 --- a/src/cpu/mips/vm/nativeInst_mips.hpp	Thu Mar 16 21:58:58 2017 +0800
     5.2 +++ b/src/cpu/mips/vm/nativeInst_mips.hpp	Fri Mar 17 22:15:27 2017 +0800
     5.3 @@ -189,6 +189,12 @@
     5.4      void  patch_set48_gs(address dest);
     5.5      void  patch_set48(address dest);
     5.6  
     5.7 +    void  patch_on_jalr_gs(address dest);
     5.8 +    void  patch_on_jalr(address dest);
     5.9 +
    5.10 +    void  patch_on_jal_gs(address dest);
    5.11 +    void  patch_on_jal(address dest);
    5.12 +
    5.13      void  patch_set32_gs(address dest);
    5.14      void  patch_set32(address dest);
    5.15  
    5.16 @@ -533,7 +539,23 @@
    5.17           is_op(long_at(4), Assembler::addiu_op) &&
    5.18  	 is_special_op(long_at(8), Assembler::jalr_op);
    5.19  #else
    5.20 -// li64
    5.21 +
    5.22 +  // nop
    5.23 +  // nop
    5.24 +  // nop
    5.25 +  // nop
    5.26 +  // jal target 
    5.27 +  // nop
    5.28 +  if ( is_nop() &&
    5.29 +         nativeInstruction_at(addr_at(4))->is_nop()  &&
    5.30 +         nativeInstruction_at(addr_at(8))->is_nop()  &&
    5.31 +         nativeInstruction_at(addr_at(12))->is_nop() &&
    5.32 +         nativeInstruction_at(addr_at(16))->is_op(Assembler::jal_op) &&
    5.33 +         nativeInstruction_at(addr_at(20))->is_nop() ) {
    5.34 +      return true;
    5.35 +  }
    5.36 +
    5.37 +  // li64
    5.38    if ( is_op(Assembler::lui_op) &&
    5.39  	is_op(int_at(4), Assembler::ori_op) &&
    5.40  	is_special_op(int_at(8), Assembler::dsll_op) &&