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src/os_cpu/aix_ppc/vm/orderAccess_aix_ppc.inline.hpp@f90c822e73f8
src/os_cpu/aix_ppc/vm/orderAccess_aix_ppc.inline.hpp
Wed, 27 Apr 2016 01:25:04 +0800
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- Wed, 27 Apr 2016 01:25:04 +0800
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changeset: 6782:28b50d07f6f8
tag: jdk8u25-b17
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2013 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
27 #define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
29 #include "runtime/orderAccess.hpp"
30 #include "vm_version_ppc.hpp"
32 // Implementation of class OrderAccess.
34 //
35 // Machine barrier instructions:
36 //
37 // - sync Two-way memory barrier, aka fence.
38 // - lwsync orders Store|Store,
39 // Load|Store,
40 // Load|Load,
41 // but not Store|Load
42 // - eieio orders Store|Store
43 // - isync Invalidates speculatively executed instructions,
44 // but isync may complete before storage accesses
45 // associated with instructions preceding isync have
46 // been performed.
47 //
48 // Semantic barrier instructions:
49 // (as defined in orderAccess.hpp)
50 //
51 // - release orders Store|Store, (maps to lwsync)
52 // Load|Store
53 // - acquire orders Load|Store, (maps to lwsync)
54 // Load|Load
55 // - fence orders Store|Store, (maps to sync)
56 // Load|Store,
57 // Load|Load,
58 // Store|Load
59 //
61 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory");
62 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
63 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
64 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
65 #define inlasm_release() inlasm_lwsync();
66 #define inlasm_acquire() inlasm_lwsync();
67 // Use twi-isync for load_acquire (faster than lwsync).
68 // ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"):
69 // #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
70 #define inlasm_acquire_reg(X) inlasm_lwsync();
71 #define inlasm_fence() inlasm_sync();
73 inline void OrderAccess::loadload() { inlasm_lwsync(); }
74 inline void OrderAccess::storestore() { inlasm_lwsync(); }
75 inline void OrderAccess::loadstore() { inlasm_lwsync(); }
76 inline void OrderAccess::storeload() { inlasm_fence(); }
78 inline void OrderAccess::acquire() { inlasm_acquire(); }
79 inline void OrderAccess::release() { inlasm_release(); }
80 inline void OrderAccess::fence() { inlasm_fence(); }
82 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { register jbyte t = *p; inlasm_acquire_reg(t); return t; }
83 inline jshort OrderAccess::load_acquire(volatile jshort* p) { register jshort t = *p; inlasm_acquire_reg(t); return t; }
84 inline jint OrderAccess::load_acquire(volatile jint* p) { register jint t = *p; inlasm_acquire_reg(t); return t; }
85 inline jlong OrderAccess::load_acquire(volatile jlong* p) { register jlong t = *p; inlasm_acquire_reg(t); return t; }
86 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { register jubyte t = *p; inlasm_acquire_reg(t); return t; }
87 inline jushort OrderAccess::load_acquire(volatile jushort* p) { register jushort t = *p; inlasm_acquire_reg(t); return t; }
88 inline juint OrderAccess::load_acquire(volatile juint* p) { register juint t = *p; inlasm_acquire_reg(t); return t; }
89 inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong)load_acquire((volatile jlong*)p); }
90 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { register jfloat t = *p; inlasm_acquire(); return t; }
91 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { register jdouble t = *p; inlasm_acquire(); return t; }
93 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)load_acquire((volatile jlong*)p); }
94 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
95 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
97 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; }
98 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { inlasm_release(); *p = v; }
99 inline void OrderAccess::release_store(volatile jint* p, jint v) { inlasm_release(); *p = v; }
100 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { inlasm_release(); *p = v; }
101 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; }
102 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { inlasm_release(); *p = v; }
103 inline void OrderAccess::release_store(volatile juint* p, juint v) { inlasm_release(); *p = v; }
104 inline void OrderAccess::release_store(volatile julong* p, julong v) { inlasm_release(); *p = v; }
105 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; }
106 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; }
108 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; }
109 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; }
111 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; inlasm_fence(); }
112 inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; inlasm_fence(); }
113 inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; inlasm_fence(); }
114 inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; inlasm_fence(); }
115 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; inlasm_fence(); }
116 inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; inlasm_fence(); }
117 inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; inlasm_fence(); }
118 inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; inlasm_fence(); }
119 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; inlasm_fence(); }
120 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; inlasm_fence(); }
122 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; inlasm_fence(); }
123 inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; inlasm_fence(); }
125 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; inlasm_fence(); }
126 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { inlasm_release(); *p = v; inlasm_fence(); }
127 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { inlasm_release(); *p = v; inlasm_fence(); }
128 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { inlasm_release(); *p = v; inlasm_fence(); }
129 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; inlasm_fence(); }
130 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { inlasm_release(); *p = v; inlasm_fence(); }
131 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { inlasm_release(); *p = v; inlasm_fence(); }
132 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { inlasm_release(); *p = v; inlasm_fence(); }
133 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; inlasm_fence(); }
134 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; inlasm_fence(); }
136 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; inlasm_fence(); }
137 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; inlasm_fence(); }
139 #undef inlasm_sync
140 #undef inlasm_lwsync
141 #undef inlasm_eieio
142 #undef inlasm_isync
143 #undef inlasm_release
144 #undef inlasm_acquire
145 #undef inlasm_fence
147 #endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
