1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/src/os_cpu/aix_ppc/vm/orderAccess_aix_ppc.inline.hpp Wed Apr 27 01:25:04 2016 +0800
1.3 @@ -0,0 +1,147 @@
1.4 +/*
1.5 + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 + * Copyright 2012, 2013 SAP AG. All rights reserved.
1.7 + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.8 + *
1.9 + * This code is free software; you can redistribute it and/or modify it
1.10 + * under the terms of the GNU General Public License version 2 only, as
1.11 + * published by the Free Software Foundation.
1.12 + *
1.13 + * This code is distributed in the hope that it will be useful, but WITHOUT
1.14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1.15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1.16 + * version 2 for more details (a copy is included in the LICENSE file that
1.17 + * accompanied this code).
1.18 + *
1.19 + * You should have received a copy of the GNU General Public License version
1.20 + * 2 along with this work; if not, write to the Free Software Foundation,
1.21 + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
1.22 + *
1.23 + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1.24 + * or visit www.oracle.com if you need additional information or have any
1.25 + * questions.
1.26 + *
1.27 + */
1.28 +
1.29 +#ifndef OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
1.30 +#define OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
1.31 +
1.32 +#include "runtime/orderAccess.hpp"
1.33 +#include "vm_version_ppc.hpp"
1.34 +
1.35 +// Implementation of class OrderAccess.
1.36 +
1.37 +//
1.38 +// Machine barrier instructions:
1.39 +//
1.40 +// - sync Two-way memory barrier, aka fence.
1.41 +// - lwsync orders Store|Store,
1.42 +// Load|Store,
1.43 +// Load|Load,
1.44 +// but not Store|Load
1.45 +// - eieio orders Store|Store
1.46 +// - isync Invalidates speculatively executed instructions,
1.47 +// but isync may complete before storage accesses
1.48 +// associated with instructions preceding isync have
1.49 +// been performed.
1.50 +//
1.51 +// Semantic barrier instructions:
1.52 +// (as defined in orderAccess.hpp)
1.53 +//
1.54 +// - release orders Store|Store, (maps to lwsync)
1.55 +// Load|Store
1.56 +// - acquire orders Load|Store, (maps to lwsync)
1.57 +// Load|Load
1.58 +// - fence orders Store|Store, (maps to sync)
1.59 +// Load|Store,
1.60 +// Load|Load,
1.61 +// Store|Load
1.62 +//
1.63 +
1.64 +#define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory");
1.65 +#define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
1.66 +#define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
1.67 +#define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
1.68 +#define inlasm_release() inlasm_lwsync();
1.69 +#define inlasm_acquire() inlasm_lwsync();
1.70 +// Use twi-isync for load_acquire (faster than lwsync).
1.71 +// ATTENTION: seems like xlC 10.1 has problems with this inline assembler macro (VerifyMethodHandles found "bad vminfo in AMH.conv"):
1.72 +// #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
1.73 +#define inlasm_acquire_reg(X) inlasm_lwsync();
1.74 +#define inlasm_fence() inlasm_sync();
1.75 +
1.76 +inline void OrderAccess::loadload() { inlasm_lwsync(); }
1.77 +inline void OrderAccess::storestore() { inlasm_lwsync(); }
1.78 +inline void OrderAccess::loadstore() { inlasm_lwsync(); }
1.79 +inline void OrderAccess::storeload() { inlasm_fence(); }
1.80 +
1.81 +inline void OrderAccess::acquire() { inlasm_acquire(); }
1.82 +inline void OrderAccess::release() { inlasm_release(); }
1.83 +inline void OrderAccess::fence() { inlasm_fence(); }
1.84 +
1.85 +inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { register jbyte t = *p; inlasm_acquire_reg(t); return t; }
1.86 +inline jshort OrderAccess::load_acquire(volatile jshort* p) { register jshort t = *p; inlasm_acquire_reg(t); return t; }
1.87 +inline jint OrderAccess::load_acquire(volatile jint* p) { register jint t = *p; inlasm_acquire_reg(t); return t; }
1.88 +inline jlong OrderAccess::load_acquire(volatile jlong* p) { register jlong t = *p; inlasm_acquire_reg(t); return t; }
1.89 +inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { register jubyte t = *p; inlasm_acquire_reg(t); return t; }
1.90 +inline jushort OrderAccess::load_acquire(volatile jushort* p) { register jushort t = *p; inlasm_acquire_reg(t); return t; }
1.91 +inline juint OrderAccess::load_acquire(volatile juint* p) { register juint t = *p; inlasm_acquire_reg(t); return t; }
1.92 +inline julong OrderAccess::load_acquire(volatile julong* p) { return (julong)load_acquire((volatile jlong*)p); }
1.93 +inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { register jfloat t = *p; inlasm_acquire(); return t; }
1.94 +inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { register jdouble t = *p; inlasm_acquire(); return t; }
1.95 +
1.96 +inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return (intptr_t)load_acquire((volatile jlong*)p); }
1.97 +inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
1.98 +inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return (void*) load_acquire((volatile jlong*)p); }
1.99 +
1.100 +inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; }
1.101 +inline void OrderAccess::release_store(volatile jshort* p, jshort v) { inlasm_release(); *p = v; }
1.102 +inline void OrderAccess::release_store(volatile jint* p, jint v) { inlasm_release(); *p = v; }
1.103 +inline void OrderAccess::release_store(volatile jlong* p, jlong v) { inlasm_release(); *p = v; }
1.104 +inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; }
1.105 +inline void OrderAccess::release_store(volatile jushort* p, jushort v) { inlasm_release(); *p = v; }
1.106 +inline void OrderAccess::release_store(volatile juint* p, juint v) { inlasm_release(); *p = v; }
1.107 +inline void OrderAccess::release_store(volatile julong* p, julong v) { inlasm_release(); *p = v; }
1.108 +inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; }
1.109 +inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; }
1.110 +
1.111 +inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; }
1.112 +inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; }
1.113 +
1.114 +inline void OrderAccess::store_fence(jbyte* p, jbyte v) { *p = v; inlasm_fence(); }
1.115 +inline void OrderAccess::store_fence(jshort* p, jshort v) { *p = v; inlasm_fence(); }
1.116 +inline void OrderAccess::store_fence(jint* p, jint v) { *p = v; inlasm_fence(); }
1.117 +inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; inlasm_fence(); }
1.118 +inline void OrderAccess::store_fence(jubyte* p, jubyte v) { *p = v; inlasm_fence(); }
1.119 +inline void OrderAccess::store_fence(jushort* p, jushort v) { *p = v; inlasm_fence(); }
1.120 +inline void OrderAccess::store_fence(juint* p, juint v) { *p = v; inlasm_fence(); }
1.121 +inline void OrderAccess::store_fence(julong* p, julong v) { *p = v; inlasm_fence(); }
1.122 +inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; inlasm_fence(); }
1.123 +inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; inlasm_fence(); }
1.124 +
1.125 +inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { *p = v; inlasm_fence(); }
1.126 +inline void OrderAccess::store_ptr_fence(void** p, void* v) { *p = v; inlasm_fence(); }
1.127 +
1.128 +inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { inlasm_release(); *p = v; inlasm_fence(); }
1.129 +inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { inlasm_release(); *p = v; inlasm_fence(); }
1.130 +inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { inlasm_release(); *p = v; inlasm_fence(); }
1.131 +inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { inlasm_release(); *p = v; inlasm_fence(); }
1.132 +inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { inlasm_release(); *p = v; inlasm_fence(); }
1.133 +inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { inlasm_release(); *p = v; inlasm_fence(); }
1.134 +inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { inlasm_release(); *p = v; inlasm_fence(); }
1.135 +inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { inlasm_release(); *p = v; inlasm_fence(); }
1.136 +inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { inlasm_release(); *p = v; inlasm_fence(); }
1.137 +inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { inlasm_release(); *p = v; inlasm_fence(); }
1.138 +
1.139 +inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { inlasm_release(); *p = v; inlasm_fence(); }
1.140 +inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { inlasm_release(); *(void* volatile *)p = v; inlasm_fence(); }
1.141 +
1.142 +#undef inlasm_sync
1.143 +#undef inlasm_lwsync
1.144 +#undef inlasm_eieio
1.145 +#undef inlasm_isync
1.146 +#undef inlasm_release
1.147 +#undef inlasm_acquire
1.148 +#undef inlasm_fence
1.149 +
1.150 +#endif // OS_CPU_AIX_OJDKPPC_VM_ORDERACCESS_AIX_PPC_INLINE_HPP
