Thu, 19 Aug 2010 14:51:47 -0700
6978249: spill between cpu and fpu registers when those moves are fast
Reviewed-by: kvn
1 //
2 // Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source_hpp %{
239 // Must be visible to the DFA in dfa_x86_32.cpp
240 extern bool is_operand_hi32_zero(Node* n);
241 %}
243 source %{
244 #define RELOC_IMM32 Assembler::imm_operand
245 #define RELOC_DISP32 Assembler::disp32_operand
247 #define __ _masm.
249 // How to find the high register of a Long pair, given the low register
250 #define HIGH_FROM_LOW(x) ((x)+2)
252 // These masks are used to provide 128-bit aligned bitmasks to the XMM
253 // instructions, to allow sign-masking or sign-bit flipping. They allow
254 // fast versions of NegF/NegD and AbsF/AbsD.
256 // Note: 'double' and 'long long' have 32-bits alignment on x86.
257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
259 // of 128-bits operands for SSE instructions.
260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
261 // Store the value to a 128-bits operand.
262 operand[0] = lo;
263 operand[1] = hi;
264 return operand;
265 }
267 // Buffer for 128-bits masks used by SSE instructions.
268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
270 // Static initialization during VM startup.
271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
276 // Offset hacking within calls.
277 static int pre_call_FPU_size() {
278 if (Compile::current()->in_24_bit_fp_mode())
279 return 6; // fldcw
280 return 0;
281 }
283 static int preserve_SP_size() {
284 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg)
285 }
287 // !!!!! Special hack to get all type of calls to specify the byte offset
288 // from the start of the call to the point where the return address
289 // will point.
290 int MachCallStaticJavaNode::ret_addr_offset() {
291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
292 if (_method_handle_invoke)
293 offset += preserve_SP_size();
294 return offset;
295 }
297 int MachCallDynamicJavaNode::ret_addr_offset() {
298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
299 }
301 static int sizeof_FFree_Float_Stack_All = -1;
303 int MachCallRuntimeNode::ret_addr_offset() {
304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
306 }
308 // Indicate if the safepoint node needs the polling page as an input.
309 // Since x86 does have absolute addressing, it doesn't.
310 bool SafePointNode::needs_polling_address_input() {
311 return false;
312 }
314 //
315 // Compute padding required for nodes which need alignment
316 //
318 // The address of the call instruction needs to be 4-byte aligned to
319 // ensure that it does not span a cache line so that it can be patched.
320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
321 current_offset += pre_call_FPU_size(); // skip fldcw, if any
322 current_offset += 1; // skip call opcode byte
323 return round_to(current_offset, alignment_required()) - current_offset;
324 }
326 // The address of the call instruction needs to be 4-byte aligned to
327 // ensure that it does not span a cache line so that it can be patched.
328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
329 current_offset += pre_call_FPU_size(); // skip fldcw, if any
330 current_offset += preserve_SP_size(); // skip mov rbp, rsp
331 current_offset += 1; // skip call opcode byte
332 return round_to(current_offset, alignment_required()) - current_offset;
333 }
335 // The address of the call instruction needs to be 4-byte aligned to
336 // ensure that it does not span a cache line so that it can be patched.
337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
338 current_offset += pre_call_FPU_size(); // skip fldcw, if any
339 current_offset += 5; // skip MOV instruction
340 current_offset += 1; // skip call opcode byte
341 return round_to(current_offset, alignment_required()) - current_offset;
342 }
344 #ifndef PRODUCT
345 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
346 st->print("INT3");
347 }
348 #endif
350 // EMIT_RM()
351 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
352 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
353 *(cbuf.code_end()) = c;
354 cbuf.set_code_end(cbuf.code_end() + 1);
355 }
357 // EMIT_CC()
358 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
359 unsigned char c = (unsigned char)( f1 | f2 );
360 *(cbuf.code_end()) = c;
361 cbuf.set_code_end(cbuf.code_end() + 1);
362 }
364 // EMIT_OPCODE()
365 void emit_opcode(CodeBuffer &cbuf, int code) {
366 *(cbuf.code_end()) = (unsigned char)code;
367 cbuf.set_code_end(cbuf.code_end() + 1);
368 }
370 // EMIT_OPCODE() w/ relocation information
371 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
372 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
373 emit_opcode(cbuf, code);
374 }
376 // EMIT_D8()
377 void emit_d8(CodeBuffer &cbuf, int d8) {
378 *(cbuf.code_end()) = (unsigned char)d8;
379 cbuf.set_code_end(cbuf.code_end() + 1);
380 }
382 // EMIT_D16()
383 void emit_d16(CodeBuffer &cbuf, int d16) {
384 *((short *)(cbuf.code_end())) = d16;
385 cbuf.set_code_end(cbuf.code_end() + 2);
386 }
388 // EMIT_D32()
389 void emit_d32(CodeBuffer &cbuf, int d32) {
390 *((int *)(cbuf.code_end())) = d32;
391 cbuf.set_code_end(cbuf.code_end() + 4);
392 }
394 // emit 32 bit value and construct relocation entry from relocInfo::relocType
395 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
396 int format) {
397 cbuf.relocate(cbuf.inst_mark(), reloc, format);
399 *((int *)(cbuf.code_end())) = d32;
400 cbuf.set_code_end(cbuf.code_end() + 4);
401 }
403 // emit 32 bit value and construct relocation entry from RelocationHolder
404 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
405 int format) {
406 #ifdef ASSERT
407 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
408 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
409 }
410 #endif
411 cbuf.relocate(cbuf.inst_mark(), rspec, format);
413 *((int *)(cbuf.code_end())) = d32;
414 cbuf.set_code_end(cbuf.code_end() + 4);
415 }
417 // Access stack slot for load or store
418 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
419 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
420 if( -128 <= disp && disp <= 127 ) {
421 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
422 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
423 emit_d8 (cbuf, disp); // Displacement // R/M byte
424 } else {
425 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
426 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
427 emit_d32(cbuf, disp); // Displacement // R/M byte
428 }
429 }
431 // eRegI ereg, memory mem) %{ // emit_reg_mem
432 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
433 // There is no index & no scale, use form without SIB byte
434 if ((index == 0x4) &&
435 (scale == 0) && (base != ESP_enc)) {
436 // If no displacement, mode is 0x0; unless base is [EBP]
437 if ( (displace == 0) && (base != EBP_enc) ) {
438 emit_rm(cbuf, 0x0, reg_encoding, base);
439 }
440 else { // If 8-bit displacement, mode 0x1
441 if ((displace >= -128) && (displace <= 127)
442 && !(displace_is_oop) ) {
443 emit_rm(cbuf, 0x1, reg_encoding, base);
444 emit_d8(cbuf, displace);
445 }
446 else { // If 32-bit displacement
447 if (base == -1) { // Special flag for absolute address
448 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
449 // (manual lies; no SIB needed here)
450 if ( displace_is_oop ) {
451 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
452 } else {
453 emit_d32 (cbuf, displace);
454 }
455 }
456 else { // Normal base + offset
457 emit_rm(cbuf, 0x2, reg_encoding, base);
458 if ( displace_is_oop ) {
459 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
460 } else {
461 emit_d32 (cbuf, displace);
462 }
463 }
464 }
465 }
466 }
467 else { // Else, encode with the SIB byte
468 // If no displacement, mode is 0x0; unless base is [EBP]
469 if (displace == 0 && (base != EBP_enc)) { // If no displacement
470 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
471 emit_rm(cbuf, scale, index, base);
472 }
473 else { // If 8-bit displacement, mode 0x1
474 if ((displace >= -128) && (displace <= 127)
475 && !(displace_is_oop) ) {
476 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
477 emit_rm(cbuf, scale, index, base);
478 emit_d8(cbuf, displace);
479 }
480 else { // If 32-bit displacement
481 if (base == 0x04 ) {
482 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
483 emit_rm(cbuf, scale, index, 0x04);
484 } else {
485 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
486 emit_rm(cbuf, scale, index, base);
487 }
488 if ( displace_is_oop ) {
489 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
490 } else {
491 emit_d32 (cbuf, displace);
492 }
493 }
494 }
495 }
496 }
499 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
500 if( dst_encoding == src_encoding ) {
501 // reg-reg copy, use an empty encoding
502 } else {
503 emit_opcode( cbuf, 0x8B );
504 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
505 }
506 }
508 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
509 if( dst_encoding == src_encoding ) {
510 // reg-reg copy, use an empty encoding
511 } else {
512 MacroAssembler _masm(&cbuf);
514 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
515 }
516 }
519 //=============================================================================
520 #ifndef PRODUCT
521 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
522 Compile* C = ra_->C;
523 if( C->in_24_bit_fp_mode() ) {
524 st->print("FLDCW 24 bit fpu control word");
525 st->print_cr(""); st->print("\t");
526 }
528 int framesize = C->frame_slots() << LogBytesPerInt;
529 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
530 // Remove two words for return addr and rbp,
531 framesize -= 2*wordSize;
533 // Calls to C2R adapters often do not accept exceptional returns.
534 // We require that their callers must bang for them. But be careful, because
535 // some VM calls (such as call site linkage) can use several kilobytes of
536 // stack. But the stack safety zone should account for that.
537 // See bugs 4446381, 4468289, 4497237.
538 if (C->need_stack_bang(framesize)) {
539 st->print_cr("# stack bang"); st->print("\t");
540 }
541 st->print_cr("PUSHL EBP"); st->print("\t");
543 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
544 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
545 st->print_cr(""); st->print("\t");
546 framesize -= wordSize;
547 }
549 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
550 if (framesize) {
551 st->print("SUB ESP,%d\t# Create frame",framesize);
552 }
553 } else {
554 st->print("SUB ESP,%d\t# Create frame",framesize);
555 }
556 }
557 #endif
560 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
561 Compile* C = ra_->C;
563 if (UseSSE >= 2 && VerifyFPU) {
564 MacroAssembler masm(&cbuf);
565 masm.verify_FPU(0, "FPU stack must be clean on entry");
566 }
568 // WARNING: Initial instruction MUST be 5 bytes or longer so that
569 // NativeJump::patch_verified_entry will be able to patch out the entry
570 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
571 // depth is ok at 5 bytes, the frame allocation can be either 3 or
572 // 6 bytes. So if we don't do the fldcw or the push then we must
573 // use the 6 byte frame allocation even if we have no frame. :-(
574 // If method sets FPU control word do it now
575 if( C->in_24_bit_fp_mode() ) {
576 MacroAssembler masm(&cbuf);
577 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
578 }
580 int framesize = C->frame_slots() << LogBytesPerInt;
581 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
582 // Remove two words for return addr and rbp,
583 framesize -= 2*wordSize;
585 // Calls to C2R adapters often do not accept exceptional returns.
586 // We require that their callers must bang for them. But be careful, because
587 // some VM calls (such as call site linkage) can use several kilobytes of
588 // stack. But the stack safety zone should account for that.
589 // See bugs 4446381, 4468289, 4497237.
590 if (C->need_stack_bang(framesize)) {
591 MacroAssembler masm(&cbuf);
592 masm.generate_stack_overflow_check(framesize);
593 }
595 // We always push rbp, so that on return to interpreter rbp, will be
596 // restored correctly and we can correct the stack.
597 emit_opcode(cbuf, 0x50 | EBP_enc);
599 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
600 emit_opcode(cbuf, 0x68); // push 0xbadb100d
601 emit_d32(cbuf, 0xbadb100d);
602 framesize -= wordSize;
603 }
605 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
606 if (framesize) {
607 emit_opcode(cbuf, 0x83); // sub SP,#framesize
608 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
609 emit_d8(cbuf, framesize);
610 }
611 } else {
612 emit_opcode(cbuf, 0x81); // sub SP,#framesize
613 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
614 emit_d32(cbuf, framesize);
615 }
616 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
618 #ifdef ASSERT
619 if (VerifyStackAtCalls) {
620 Label L;
621 MacroAssembler masm(&cbuf);
622 masm.push(rax);
623 masm.mov(rax, rsp);
624 masm.andptr(rax, StackAlignmentInBytes-1);
625 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
626 masm.pop(rax);
627 masm.jcc(Assembler::equal, L);
628 masm.stop("Stack is not properly aligned!");
629 masm.bind(L);
630 }
631 #endif
633 }
635 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
636 return MachNode::size(ra_); // too many variables; just compute it the hard way
637 }
639 int MachPrologNode::reloc() const {
640 return 0; // a large enough number
641 }
643 //=============================================================================
644 #ifndef PRODUCT
645 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
646 Compile *C = ra_->C;
647 int framesize = C->frame_slots() << LogBytesPerInt;
648 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
649 // Remove two words for return addr and rbp,
650 framesize -= 2*wordSize;
652 if( C->in_24_bit_fp_mode() ) {
653 st->print("FLDCW standard control word");
654 st->cr(); st->print("\t");
655 }
656 if( framesize ) {
657 st->print("ADD ESP,%d\t# Destroy frame",framesize);
658 st->cr(); st->print("\t");
659 }
660 st->print_cr("POPL EBP"); st->print("\t");
661 if( do_polling() && C->is_method_compilation() ) {
662 st->print("TEST PollPage,EAX\t! Poll Safepoint");
663 st->cr(); st->print("\t");
664 }
665 }
666 #endif
668 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
669 Compile *C = ra_->C;
671 // If method set FPU control word, restore to standard control word
672 if( C->in_24_bit_fp_mode() ) {
673 MacroAssembler masm(&cbuf);
674 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
675 }
677 int framesize = C->frame_slots() << LogBytesPerInt;
678 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
679 // Remove two words for return addr and rbp,
680 framesize -= 2*wordSize;
682 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
684 if( framesize >= 128 ) {
685 emit_opcode(cbuf, 0x81); // add SP, #framesize
686 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
687 emit_d32(cbuf, framesize);
688 }
689 else if( framesize ) {
690 emit_opcode(cbuf, 0x83); // add SP, #framesize
691 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
692 emit_d8(cbuf, framesize);
693 }
695 emit_opcode(cbuf, 0x58 | EBP_enc);
697 if( do_polling() && C->is_method_compilation() ) {
698 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
699 emit_opcode(cbuf,0x85);
700 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
701 emit_d32(cbuf, (intptr_t)os::get_polling_page());
702 }
703 }
705 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
706 Compile *C = ra_->C;
707 // If method set FPU control word, restore to standard control word
708 int size = C->in_24_bit_fp_mode() ? 6 : 0;
709 if( do_polling() && C->is_method_compilation() ) size += 6;
711 int framesize = C->frame_slots() << LogBytesPerInt;
712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
713 // Remove two words for return addr and rbp,
714 framesize -= 2*wordSize;
716 size++; // popl rbp,
718 if( framesize >= 128 ) {
719 size += 6;
720 } else {
721 size += framesize ? 3 : 0;
722 }
723 return size;
724 }
726 int MachEpilogNode::reloc() const {
727 return 0; // a large enough number
728 }
730 const Pipeline * MachEpilogNode::pipeline() const {
731 return MachNode::pipeline_class();
732 }
734 int MachEpilogNode::safepoint_offset() const { return 0; }
736 //=============================================================================
738 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
739 static enum RC rc_class( OptoReg::Name reg ) {
741 if( !OptoReg::is_valid(reg) ) return rc_bad;
742 if (OptoReg::is_stack(reg)) return rc_stack;
744 VMReg r = OptoReg::as_VMReg(reg);
745 if (r->is_Register()) return rc_int;
746 if (r->is_FloatRegister()) {
747 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
748 return rc_float;
749 }
750 assert(r->is_XMMRegister(), "must be");
751 return rc_xmm;
752 }
754 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
755 int opcode, const char *op_str, int size, outputStream* st ) {
756 if( cbuf ) {
757 emit_opcode (*cbuf, opcode );
758 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
759 #ifndef PRODUCT
760 } else if( !do_size ) {
761 if( size != 0 ) st->print("\n\t");
762 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
763 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
764 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
765 } else { // FLD, FST, PUSH, POP
766 st->print("%s [ESP + #%d]",op_str,offset);
767 }
768 #endif
769 }
770 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
771 return size+3+offset_size;
772 }
774 // Helper for XMM registers. Extra opcode bits, limited syntax.
775 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
776 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
777 if( cbuf ) {
778 if( reg_lo+1 == reg_hi ) { // double move?
779 if( is_load && !UseXmmLoadAndClearUpper )
780 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
781 else
782 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
783 } else {
784 emit_opcode(*cbuf, 0xF3 );
785 }
786 emit_opcode(*cbuf, 0x0F );
787 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
788 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
789 else
790 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
791 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
792 #ifndef PRODUCT
793 } else if( !do_size ) {
794 if( size != 0 ) st->print("\n\t");
795 if( reg_lo+1 == reg_hi ) { // double move?
796 if( is_load ) st->print("%s %s,[ESP + #%d]",
797 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
798 Matcher::regName[reg_lo], offset);
799 else st->print("MOVSD [ESP + #%d],%s",
800 offset, Matcher::regName[reg_lo]);
801 } else {
802 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
803 Matcher::regName[reg_lo], offset);
804 else st->print("MOVSS [ESP + #%d],%s",
805 offset, Matcher::regName[reg_lo]);
806 }
807 #endif
808 }
809 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
810 return size+5+offset_size;
811 }
814 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
815 int src_hi, int dst_hi, int size, outputStream* st ) {
816 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
817 if( cbuf ) {
818 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
819 emit_opcode(*cbuf, 0x66 );
820 }
821 emit_opcode(*cbuf, 0x0F );
822 emit_opcode(*cbuf, 0x28 );
823 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
824 #ifndef PRODUCT
825 } else if( !do_size ) {
826 if( size != 0 ) st->print("\n\t");
827 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
828 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
829 } else {
830 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
831 }
832 #endif
833 }
834 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
835 } else {
836 if( cbuf ) {
837 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
838 emit_opcode(*cbuf, 0x0F );
839 emit_opcode(*cbuf, 0x10 );
840 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
841 #ifndef PRODUCT
842 } else if( !do_size ) {
843 if( size != 0 ) st->print("\n\t");
844 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
845 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
846 } else {
847 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
848 }
849 #endif
850 }
851 return size+4;
852 }
853 }
855 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
856 int src_hi, int dst_hi, int size, outputStream* st ) {
857 // 32-bit
858 if (cbuf) {
859 emit_opcode(*cbuf, 0x66);
860 emit_opcode(*cbuf, 0x0F);
861 emit_opcode(*cbuf, 0x6E);
862 emit_rm(*cbuf, 0x3, Matcher::_regEncode[dst_lo] & 7, Matcher::_regEncode[src_lo] & 7);
863 #ifndef PRODUCT
864 } else if (!do_size) {
865 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
866 #endif
867 }
868 return 4;
869 }
872 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
873 int src_hi, int dst_hi, int size, outputStream* st ) {
874 // 32-bit
875 if (cbuf) {
876 emit_opcode(*cbuf, 0x66);
877 emit_opcode(*cbuf, 0x0F);
878 emit_opcode(*cbuf, 0x7E);
879 emit_rm(*cbuf, 0x3, Matcher::_regEncode[src_lo] & 7, Matcher::_regEncode[dst_lo] & 7);
880 #ifndef PRODUCT
881 } else if (!do_size) {
882 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
883 #endif
884 }
885 return 4;
886 }
888 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
889 if( cbuf ) {
890 emit_opcode(*cbuf, 0x8B );
891 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
892 #ifndef PRODUCT
893 } else if( !do_size ) {
894 if( size != 0 ) st->print("\n\t");
895 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
896 #endif
897 }
898 return size+2;
899 }
901 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
902 int offset, int size, outputStream* st ) {
903 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
904 if( cbuf ) {
905 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
906 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
907 #ifndef PRODUCT
908 } else if( !do_size ) {
909 if( size != 0 ) st->print("\n\t");
910 st->print("FLD %s",Matcher::regName[src_lo]);
911 #endif
912 }
913 size += 2;
914 }
916 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
917 const char *op_str;
918 int op;
919 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
920 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
921 op = 0xDD;
922 } else { // 32-bit store
923 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
924 op = 0xD9;
925 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
926 }
928 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
929 }
931 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
932 // Get registers to move
933 OptoReg::Name src_second = ra_->get_reg_second(in(1));
934 OptoReg::Name src_first = ra_->get_reg_first(in(1));
935 OptoReg::Name dst_second = ra_->get_reg_second(this );
936 OptoReg::Name dst_first = ra_->get_reg_first(this );
938 enum RC src_second_rc = rc_class(src_second);
939 enum RC src_first_rc = rc_class(src_first);
940 enum RC dst_second_rc = rc_class(dst_second);
941 enum RC dst_first_rc = rc_class(dst_first);
943 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
945 // Generate spill code!
946 int size = 0;
948 if( src_first == dst_first && src_second == dst_second )
949 return size; // Self copy, no move
951 // --------------------------------------
952 // Check for mem-mem move. push/pop to move.
953 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
954 if( src_second == dst_first ) { // overlapping stack copy ranges
955 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
956 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
957 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
958 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
959 }
960 // move low bits
961 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
962 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
963 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
964 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
965 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
966 }
967 return size;
968 }
970 // --------------------------------------
971 // Check for integer reg-reg copy
972 if( src_first_rc == rc_int && dst_first_rc == rc_int )
973 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
975 // Check for integer store
976 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
977 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
979 // Check for integer load
980 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
981 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
983 // Check for integer reg-xmm reg copy
984 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
985 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
986 "no 64 bit integer-float reg moves" );
987 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
988 }
989 // --------------------------------------
990 // Check for float reg-reg copy
991 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
992 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
993 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
994 if( cbuf ) {
996 // Note the mucking with the register encode to compensate for the 0/1
997 // indexing issue mentioned in a comment in the reg_def sections
998 // for FPR registers many lines above here.
1000 if( src_first != FPR1L_num ) {
1001 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1002 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1003 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1004 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1005 } else {
1006 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1007 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1008 }
1009 #ifndef PRODUCT
1010 } else if( !do_size ) {
1011 if( size != 0 ) st->print("\n\t");
1012 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1013 else st->print( "FST %s", Matcher::regName[dst_first]);
1014 #endif
1015 }
1016 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1017 }
1019 // Check for float store
1020 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1021 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1022 }
1024 // Check for float load
1025 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1026 int offset = ra_->reg2offset(src_first);
1027 const char *op_str;
1028 int op;
1029 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1030 op_str = "FLD_D";
1031 op = 0xDD;
1032 } else { // 32-bit load
1033 op_str = "FLD_S";
1034 op = 0xD9;
1035 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1036 }
1037 if( cbuf ) {
1038 emit_opcode (*cbuf, op );
1039 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1040 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1041 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1042 #ifndef PRODUCT
1043 } else if( !do_size ) {
1044 if( size != 0 ) st->print("\n\t");
1045 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1046 #endif
1047 }
1048 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1049 return size + 3+offset_size+2;
1050 }
1052 // Check for xmm reg-reg copy
1053 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1054 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1055 (src_first+1 == src_second && dst_first+1 == dst_second),
1056 "no non-adjacent float-moves" );
1057 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1058 }
1060 // Check for xmm reg-integer reg copy
1061 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1062 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1063 "no 64 bit float-integer reg moves" );
1064 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1065 }
1067 // Check for xmm store
1068 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1069 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1070 }
1072 // Check for float xmm load
1073 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1074 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1075 }
1077 // Copy from float reg to xmm reg
1078 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1079 // copy to the top of stack from floating point reg
1080 // and use LEA to preserve flags
1081 if( cbuf ) {
1082 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1083 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1084 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1085 emit_d8(*cbuf,0xF8);
1086 #ifndef PRODUCT
1087 } else if( !do_size ) {
1088 if( size != 0 ) st->print("\n\t");
1089 st->print("LEA ESP,[ESP-8]");
1090 #endif
1091 }
1092 size += 4;
1094 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1096 // Copy from the temp memory to the xmm reg.
1097 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1099 if( cbuf ) {
1100 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1101 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1102 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1103 emit_d8(*cbuf,0x08);
1104 #ifndef PRODUCT
1105 } else if( !do_size ) {
1106 if( size != 0 ) st->print("\n\t");
1107 st->print("LEA ESP,[ESP+8]");
1108 #endif
1109 }
1110 size += 4;
1111 return size;
1112 }
1114 assert( size > 0, "missed a case" );
1116 // --------------------------------------------------------------------
1117 // Check for second bits still needing moving.
1118 if( src_second == dst_second )
1119 return size; // Self copy; no move
1120 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1122 // Check for second word int-int move
1123 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1124 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1126 // Check for second word integer store
1127 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1128 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1130 // Check for second word integer load
1131 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1132 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1135 Unimplemented();
1136 }
1138 #ifndef PRODUCT
1139 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1140 implementation( NULL, ra_, false, st );
1141 }
1142 #endif
1144 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1145 implementation( &cbuf, ra_, false, NULL );
1146 }
1148 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1149 return implementation( NULL, ra_, true, NULL );
1150 }
1152 //=============================================================================
1153 #ifndef PRODUCT
1154 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1155 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1156 }
1157 #endif
1159 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1160 MacroAssembler _masm(&cbuf);
1161 __ nop(_count);
1162 }
1164 uint MachNopNode::size(PhaseRegAlloc *) const {
1165 return _count;
1166 }
1169 //=============================================================================
1170 #ifndef PRODUCT
1171 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1172 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1173 int reg = ra_->get_reg_first(this);
1174 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1175 }
1176 #endif
1178 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1179 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1180 int reg = ra_->get_encode(this);
1181 if( offset >= 128 ) {
1182 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1183 emit_rm(cbuf, 0x2, reg, 0x04);
1184 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1185 emit_d32(cbuf, offset);
1186 }
1187 else {
1188 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1189 emit_rm(cbuf, 0x1, reg, 0x04);
1190 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1191 emit_d8(cbuf, offset);
1192 }
1193 }
1195 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1196 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1197 if( offset >= 128 ) {
1198 return 7;
1199 }
1200 else {
1201 return 4;
1202 }
1203 }
1205 //=============================================================================
1207 // emit call stub, compiled java to interpreter
1208 void emit_java_to_interp(CodeBuffer &cbuf ) {
1209 // Stub is fixed up when the corresponding call is converted from calling
1210 // compiled code to calling interpreted code.
1211 // mov rbx,0
1212 // jmp -1
1214 address mark = cbuf.inst_mark(); // get mark within main instrs section
1216 // Note that the code buffer's inst_mark is always relative to insts.
1217 // That's why we must use the macroassembler to generate a stub.
1218 MacroAssembler _masm(&cbuf);
1220 address base =
1221 __ start_a_stub(Compile::MAX_stubs_size);
1222 if (base == NULL) return; // CodeBuffer::expand failed
1223 // static stub relocation stores the instruction address of the call
1224 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1225 // static stub relocation also tags the methodOop in the code-stream.
1226 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1227 // This is recognized as unresolved by relocs/nativeInst/ic code
1228 __ jump(RuntimeAddress(__ pc()));
1230 __ end_a_stub();
1231 // Update current stubs pointer and restore code_end.
1232 }
1233 // size of call stub, compiled java to interpretor
1234 uint size_java_to_interp() {
1235 return 10; // movl; jmp
1236 }
1237 // relocation entries for call stub, compiled java to interpretor
1238 uint reloc_java_to_interp() {
1239 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1240 }
1242 //=============================================================================
1243 #ifndef PRODUCT
1244 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1245 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1246 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1247 st->print_cr("\tNOP");
1248 st->print_cr("\tNOP");
1249 if( !OptoBreakpoint )
1250 st->print_cr("\tNOP");
1251 }
1252 #endif
1254 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1255 MacroAssembler masm(&cbuf);
1256 #ifdef ASSERT
1257 uint code_size = cbuf.code_size();
1258 #endif
1259 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1260 masm.jump_cc(Assembler::notEqual,
1261 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1262 /* WARNING these NOPs are critical so that verified entry point is properly
1263 aligned for patching by NativeJump::patch_verified_entry() */
1264 int nops_cnt = 2;
1265 if( !OptoBreakpoint ) // Leave space for int3
1266 nops_cnt += 1;
1267 masm.nop(nops_cnt);
1269 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1270 }
1272 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1273 return OptoBreakpoint ? 11 : 12;
1274 }
1277 //=============================================================================
1278 uint size_exception_handler() {
1279 // NativeCall instruction size is the same as NativeJump.
1280 // exception handler starts out as jump and can be patched to
1281 // a call be deoptimization. (4932387)
1282 // Note that this value is also credited (in output.cpp) to
1283 // the size of the code section.
1284 return NativeJump::instruction_size;
1285 }
1287 // Emit exception handler code. Stuff framesize into a register
1288 // and call a VM stub routine.
1289 int emit_exception_handler(CodeBuffer& cbuf) {
1291 // Note that the code buffer's inst_mark is always relative to insts.
1292 // That's why we must use the macroassembler to generate a handler.
1293 MacroAssembler _masm(&cbuf);
1294 address base =
1295 __ start_a_stub(size_exception_handler());
1296 if (base == NULL) return 0; // CodeBuffer::expand failed
1297 int offset = __ offset();
1298 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1299 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1300 __ end_a_stub();
1301 return offset;
1302 }
1304 uint size_deopt_handler() {
1305 // NativeCall instruction size is the same as NativeJump.
1306 // exception handler starts out as jump and can be patched to
1307 // a call be deoptimization. (4932387)
1308 // Note that this value is also credited (in output.cpp) to
1309 // the size of the code section.
1310 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1311 }
1313 // Emit deopt handler code.
1314 int emit_deopt_handler(CodeBuffer& cbuf) {
1316 // Note that the code buffer's inst_mark is always relative to insts.
1317 // That's why we must use the macroassembler to generate a handler.
1318 MacroAssembler _masm(&cbuf);
1319 address base =
1320 __ start_a_stub(size_exception_handler());
1321 if (base == NULL) return 0; // CodeBuffer::expand failed
1322 int offset = __ offset();
1323 InternalAddress here(__ pc());
1324 __ pushptr(here.addr());
1326 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1327 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1328 __ end_a_stub();
1329 return offset;
1330 }
1333 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1334 int mark = cbuf.insts()->mark_off();
1335 MacroAssembler _masm(&cbuf);
1336 address double_address = __ double_constant(x);
1337 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1338 emit_d32_reloc(cbuf,
1339 (int)double_address,
1340 internal_word_Relocation::spec(double_address),
1341 RELOC_DISP32);
1342 }
1344 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1345 int mark = cbuf.insts()->mark_off();
1346 MacroAssembler _masm(&cbuf);
1347 address float_address = __ float_constant(x);
1348 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1349 emit_d32_reloc(cbuf,
1350 (int)float_address,
1351 internal_word_Relocation::spec(float_address),
1352 RELOC_DISP32);
1353 }
1356 const bool Matcher::match_rule_supported(int opcode) {
1357 if (!has_match_rule(opcode))
1358 return false;
1360 return true; // Per default match rules are supported.
1361 }
1363 int Matcher::regnum_to_fpu_offset(int regnum) {
1364 return regnum - 32; // The FP registers are in the second chunk
1365 }
1367 bool is_positive_zero_float(jfloat f) {
1368 return jint_cast(f) == jint_cast(0.0F);
1369 }
1371 bool is_positive_one_float(jfloat f) {
1372 return jint_cast(f) == jint_cast(1.0F);
1373 }
1375 bool is_positive_zero_double(jdouble d) {
1376 return jlong_cast(d) == jlong_cast(0.0);
1377 }
1379 bool is_positive_one_double(jdouble d) {
1380 return jlong_cast(d) == jlong_cast(1.0);
1381 }
1383 // This is UltraSparc specific, true just means we have fast l2f conversion
1384 const bool Matcher::convL2FSupported(void) {
1385 return true;
1386 }
1388 // Vector width in bytes
1389 const uint Matcher::vector_width_in_bytes(void) {
1390 return UseSSE >= 2 ? 8 : 0;
1391 }
1393 // Vector ideal reg
1394 const uint Matcher::vector_ideal_reg(void) {
1395 return Op_RegD;
1396 }
1398 // Is this branch offset short enough that a short branch can be used?
1399 //
1400 // NOTE: If the platform does not provide any short branch variants, then
1401 // this method should return false for offset 0.
1402 bool Matcher::is_short_branch_offset(int rule, int offset) {
1403 // the short version of jmpConUCF2 contains multiple branches,
1404 // making the reach slightly less
1405 if (rule == jmpConUCF2_rule)
1406 return (-126 <= offset && offset <= 125);
1407 return (-128 <= offset && offset <= 127);
1408 }
1410 const bool Matcher::isSimpleConstant64(jlong value) {
1411 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1412 return false;
1413 }
1415 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1416 const bool Matcher::init_array_count_is_in_bytes = false;
1418 // Threshold size for cleararray.
1419 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1421 // Should the Matcher clone shifts on addressing modes, expecting them to
1422 // be subsumed into complex addressing expressions or compute them into
1423 // registers? True for Intel but false for most RISCs
1424 const bool Matcher::clone_shift_expressions = true;
1426 bool Matcher::narrow_oop_use_complex_address() {
1427 ShouldNotCallThis();
1428 return true;
1429 }
1432 // Is it better to copy float constants, or load them directly from memory?
1433 // Intel can load a float constant from a direct address, requiring no
1434 // extra registers. Most RISCs will have to materialize an address into a
1435 // register first, so they would do better to copy the constant from stack.
1436 const bool Matcher::rematerialize_float_constants = true;
1438 // If CPU can load and store mis-aligned doubles directly then no fixup is
1439 // needed. Else we split the double into 2 integer pieces and move it
1440 // piece-by-piece. Only happens when passing doubles into C code as the
1441 // Java calling convention forces doubles to be aligned.
1442 const bool Matcher::misaligned_doubles_ok = true;
1445 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1446 // Get the memory operand from the node
1447 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1448 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1449 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1450 uint opcnt = 1; // First operand
1451 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1452 while( idx >= skipped+num_edges ) {
1453 skipped += num_edges;
1454 opcnt++; // Bump operand count
1455 assert( opcnt < numopnds, "Accessing non-existent operand" );
1456 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1457 }
1459 MachOper *memory = node->_opnds[opcnt];
1460 MachOper *new_memory = NULL;
1461 switch (memory->opcode()) {
1462 case DIRECT:
1463 case INDOFFSET32X:
1464 // No transformation necessary.
1465 return;
1466 case INDIRECT:
1467 new_memory = new (C) indirect_win95_safeOper( );
1468 break;
1469 case INDOFFSET8:
1470 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1471 break;
1472 case INDOFFSET32:
1473 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1474 break;
1475 case INDINDEXOFFSET:
1476 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1477 break;
1478 case INDINDEXSCALE:
1479 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1480 break;
1481 case INDINDEXSCALEOFFSET:
1482 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1483 break;
1484 case LOAD_LONG_INDIRECT:
1485 case LOAD_LONG_INDOFFSET32:
1486 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1487 return;
1488 default:
1489 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1490 return;
1491 }
1492 node->_opnds[opcnt] = new_memory;
1493 }
1495 // Advertise here if the CPU requires explicit rounding operations
1496 // to implement the UseStrictFP mode.
1497 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1499 // Are floats conerted to double when stored to stack during deoptimization?
1500 // On x32 it is stored with convertion only when FPU is used for floats.
1501 bool Matcher::float_in_double() { return (UseSSE == 0); }
1503 // Do ints take an entire long register or just half?
1504 const bool Matcher::int_in_long = false;
1506 // Return whether or not this register is ever used as an argument. This
1507 // function is used on startup to build the trampoline stubs in generateOptoStub.
1508 // Registers not mentioned will be killed by the VM call in the trampoline, and
1509 // arguments in those registers not be available to the callee.
1510 bool Matcher::can_be_java_arg( int reg ) {
1511 if( reg == ECX_num || reg == EDX_num ) return true;
1512 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1513 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1514 return false;
1515 }
1517 bool Matcher::is_spillable_arg( int reg ) {
1518 return can_be_java_arg(reg);
1519 }
1521 // Register for DIVI projection of divmodI
1522 RegMask Matcher::divI_proj_mask() {
1523 return EAX_REG_mask;
1524 }
1526 // Register for MODI projection of divmodI
1527 RegMask Matcher::modI_proj_mask() {
1528 return EDX_REG_mask;
1529 }
1531 // Register for DIVL projection of divmodL
1532 RegMask Matcher::divL_proj_mask() {
1533 ShouldNotReachHere();
1534 return RegMask();
1535 }
1537 // Register for MODL projection of divmodL
1538 RegMask Matcher::modL_proj_mask() {
1539 ShouldNotReachHere();
1540 return RegMask();
1541 }
1543 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1544 return EBP_REG_mask;
1545 }
1547 // Returns true if the high 32 bits of the value is known to be zero.
1548 bool is_operand_hi32_zero(Node* n) {
1549 int opc = n->Opcode();
1550 if (opc == Op_LoadUI2L) {
1551 return true;
1552 }
1553 if (opc == Op_AndL) {
1554 Node* o2 = n->in(2);
1555 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1556 return true;
1557 }
1558 }
1559 return false;
1560 }
1562 %}
1564 //----------ENCODING BLOCK-----------------------------------------------------
1565 // This block specifies the encoding classes used by the compiler to output
1566 // byte streams. Encoding classes generate functions which are called by
1567 // Machine Instruction Nodes in order to generate the bit encoding of the
1568 // instruction. Operands specify their base encoding interface with the
1569 // interface keyword. There are currently supported four interfaces,
1570 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1571 // operand to generate a function which returns its register number when
1572 // queried. CONST_INTER causes an operand to generate a function which
1573 // returns the value of the constant when queried. MEMORY_INTER causes an
1574 // operand to generate four functions which return the Base Register, the
1575 // Index Register, the Scale Value, and the Offset Value of the operand when
1576 // queried. COND_INTER causes an operand to generate six functions which
1577 // return the encoding code (ie - encoding bits for the instruction)
1578 // associated with each basic boolean condition for a conditional instruction.
1579 // Instructions specify two basic values for encoding. They use the
1580 // ins_encode keyword to specify their encoding class (which must be one of
1581 // the class names specified in the encoding block), and they use the
1582 // opcode keyword to specify, in order, their primary, secondary, and
1583 // tertiary opcode. Only the opcode sections which a particular instruction
1584 // needs for encoding need to be specified.
1585 encode %{
1586 // Build emit functions for each basic byte or larger field in the intel
1587 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1588 // code in the enc_class source block. Emit functions will live in the
1589 // main source block for now. In future, we can generalize this by
1590 // adding a syntax that specifies the sizes of fields in an order,
1591 // so that the adlc can build the emit functions automagically
1593 // Emit primary opcode
1594 enc_class OpcP %{
1595 emit_opcode(cbuf, $primary);
1596 %}
1598 // Emit secondary opcode
1599 enc_class OpcS %{
1600 emit_opcode(cbuf, $secondary);
1601 %}
1603 // Emit opcode directly
1604 enc_class Opcode(immI d8) %{
1605 emit_opcode(cbuf, $d8$$constant);
1606 %}
1608 enc_class SizePrefix %{
1609 emit_opcode(cbuf,0x66);
1610 %}
1612 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1613 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1614 %}
1616 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1617 emit_opcode(cbuf,$opcode$$constant);
1618 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1619 %}
1621 enc_class mov_r32_imm0( eRegI dst ) %{
1622 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1623 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1624 %}
1626 enc_class cdq_enc %{
1627 // Full implementation of Java idiv and irem; checks for
1628 // special case as described in JVM spec., p.243 & p.271.
1629 //
1630 // normal case special case
1631 //
1632 // input : rax,: dividend min_int
1633 // reg: divisor -1
1634 //
1635 // output: rax,: quotient (= rax, idiv reg) min_int
1636 // rdx: remainder (= rax, irem reg) 0
1637 //
1638 // Code sequnce:
1639 //
1640 // 81 F8 00 00 00 80 cmp rax,80000000h
1641 // 0F 85 0B 00 00 00 jne normal_case
1642 // 33 D2 xor rdx,edx
1643 // 83 F9 FF cmp rcx,0FFh
1644 // 0F 84 03 00 00 00 je done
1645 // normal_case:
1646 // 99 cdq
1647 // F7 F9 idiv rax,ecx
1648 // done:
1649 //
1650 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1651 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1652 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1653 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1654 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1655 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1656 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1657 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1658 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1659 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1660 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1661 // normal_case:
1662 emit_opcode(cbuf,0x99); // cdq
1663 // idiv (note: must be emitted by the user of this rule)
1664 // normal:
1665 %}
1667 // Dense encoding for older common ops
1668 enc_class Opc_plus(immI opcode, eRegI reg) %{
1669 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1670 %}
1673 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1674 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1675 // Check for 8-bit immediate, and set sign extend bit in opcode
1676 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1677 emit_opcode(cbuf, $primary | 0x02);
1678 }
1679 else { // If 32-bit immediate
1680 emit_opcode(cbuf, $primary);
1681 }
1682 %}
1684 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1685 // Emit primary opcode and set sign-extend bit
1686 // Check for 8-bit immediate, and set sign extend bit in opcode
1687 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1688 emit_opcode(cbuf, $primary | 0x02); }
1689 else { // If 32-bit immediate
1690 emit_opcode(cbuf, $primary);
1691 }
1692 // Emit r/m byte with secondary opcode, after primary opcode.
1693 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1694 %}
1696 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1697 // Check for 8-bit immediate, and set sign extend bit in opcode
1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1699 $$$emit8$imm$$constant;
1700 }
1701 else { // If 32-bit immediate
1702 // Output immediate
1703 $$$emit32$imm$$constant;
1704 }
1705 %}
1707 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1708 // Emit primary opcode and set sign-extend bit
1709 // Check for 8-bit immediate, and set sign extend bit in opcode
1710 int con = (int)$imm$$constant; // Throw away top bits
1711 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1712 // Emit r/m byte with secondary opcode, after primary opcode.
1713 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1714 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1715 else emit_d32(cbuf,con);
1716 %}
1718 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1719 // Emit primary opcode and set sign-extend bit
1720 // Check for 8-bit immediate, and set sign extend bit in opcode
1721 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1722 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1723 // Emit r/m byte with tertiary opcode, after primary opcode.
1724 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1725 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1726 else emit_d32(cbuf,con);
1727 %}
1729 enc_class Lbl (label labl) %{ // JMP, CALL
1730 Label *l = $labl$$label;
1731 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1732 %}
1734 enc_class LblShort (label labl) %{ // JMP, CALL
1735 Label *l = $labl$$label;
1736 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1737 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1738 emit_d8(cbuf, disp);
1739 %}
1741 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1742 emit_cc(cbuf, $secondary, $dst$$reg );
1743 %}
1745 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1746 int destlo = $dst$$reg;
1747 int desthi = HIGH_FROM_LOW(destlo);
1748 // bswap lo
1749 emit_opcode(cbuf, 0x0F);
1750 emit_cc(cbuf, 0xC8, destlo);
1751 // bswap hi
1752 emit_opcode(cbuf, 0x0F);
1753 emit_cc(cbuf, 0xC8, desthi);
1754 // xchg lo and hi
1755 emit_opcode(cbuf, 0x87);
1756 emit_rm(cbuf, 0x3, destlo, desthi);
1757 %}
1759 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1760 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1761 %}
1763 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1764 Label *l = $labl$$label;
1765 $$$emit8$primary;
1766 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1767 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1768 %}
1770 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1771 Label *l = $labl$$label;
1772 emit_cc(cbuf, $primary, $cop$$cmpcode);
1773 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1774 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1775 emit_d8(cbuf, disp);
1776 %}
1778 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1779 $$$emit8$primary;
1780 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1781 %}
1783 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1784 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1785 emit_d8(cbuf, op >> 8 );
1786 emit_d8(cbuf, op & 255);
1787 %}
1789 // emulate a CMOV with a conditional branch around a MOV
1790 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1791 // Invert sense of branch from sense of CMOV
1792 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1793 emit_d8( cbuf, $brOffs$$constant );
1794 %}
1796 enc_class enc_PartialSubtypeCheck( ) %{
1797 Register Redi = as_Register(EDI_enc); // result register
1798 Register Reax = as_Register(EAX_enc); // super class
1799 Register Recx = as_Register(ECX_enc); // killed
1800 Register Resi = as_Register(ESI_enc); // sub class
1801 Label miss;
1803 MacroAssembler _masm(&cbuf);
1804 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1805 NULL, &miss,
1806 /*set_cond_codes:*/ true);
1807 if ($primary) {
1808 __ xorptr(Redi, Redi);
1809 }
1810 __ bind(miss);
1811 %}
1813 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1814 MacroAssembler masm(&cbuf);
1815 int start = masm.offset();
1816 if (UseSSE >= 2) {
1817 if (VerifyFPU) {
1818 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1819 }
1820 } else {
1821 // External c_calling_convention expects the FPU stack to be 'clean'.
1822 // Compiled code leaves it dirty. Do cleanup now.
1823 masm.empty_FPU_stack();
1824 }
1825 if (sizeof_FFree_Float_Stack_All == -1) {
1826 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1827 } else {
1828 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1829 }
1830 %}
1832 enc_class Verify_FPU_For_Leaf %{
1833 if( VerifyFPU ) {
1834 MacroAssembler masm(&cbuf);
1835 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1836 }
1837 %}
1839 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1840 // This is the instruction starting address for relocation info.
1841 cbuf.set_inst_mark();
1842 $$$emit8$primary;
1843 // CALL directly to the runtime
1844 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1845 runtime_call_Relocation::spec(), RELOC_IMM32 );
1847 if (UseSSE >= 2) {
1848 MacroAssembler _masm(&cbuf);
1849 BasicType rt = tf()->return_type();
1851 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1852 // A C runtime call where the return value is unused. In SSE2+
1853 // mode the result needs to be removed from the FPU stack. It's
1854 // likely that this function call could be removed by the
1855 // optimizer if the C function is a pure function.
1856 __ ffree(0);
1857 } else if (rt == T_FLOAT) {
1858 __ lea(rsp, Address(rsp, -4));
1859 __ fstp_s(Address(rsp, 0));
1860 __ movflt(xmm0, Address(rsp, 0));
1861 __ lea(rsp, Address(rsp, 4));
1862 } else if (rt == T_DOUBLE) {
1863 __ lea(rsp, Address(rsp, -8));
1864 __ fstp_d(Address(rsp, 0));
1865 __ movdbl(xmm0, Address(rsp, 0));
1866 __ lea(rsp, Address(rsp, 8));
1867 }
1868 }
1869 %}
1872 enc_class pre_call_FPU %{
1873 // If method sets FPU control word restore it here
1874 debug_only(int off0 = cbuf.code_size());
1875 if( Compile::current()->in_24_bit_fp_mode() ) {
1876 MacroAssembler masm(&cbuf);
1877 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1878 }
1879 debug_only(int off1 = cbuf.code_size());
1880 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1881 %}
1883 enc_class post_call_FPU %{
1884 // If method sets FPU control word do it here also
1885 if( Compile::current()->in_24_bit_fp_mode() ) {
1886 MacroAssembler masm(&cbuf);
1887 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1888 }
1889 %}
1891 enc_class preserve_SP %{
1892 debug_only(int off0 = cbuf.code_size());
1893 MacroAssembler _masm(&cbuf);
1894 // RBP is preserved across all calls, even compiled calls.
1895 // Use it to preserve RSP in places where the callee might change the SP.
1896 __ movptr(rbp_mh_SP_save, rsp);
1897 debug_only(int off1 = cbuf.code_size());
1898 assert(off1 - off0 == preserve_SP_size(), "correct size prediction");
1899 %}
1901 enc_class restore_SP %{
1902 MacroAssembler _masm(&cbuf);
1903 __ movptr(rsp, rbp_mh_SP_save);
1904 %}
1906 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1907 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1908 // who we intended to call.
1909 cbuf.set_inst_mark();
1910 $$$emit8$primary;
1911 if ( !_method ) {
1912 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1913 runtime_call_Relocation::spec(), RELOC_IMM32 );
1914 } else if(_optimized_virtual) {
1915 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1916 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1917 } else {
1918 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1919 static_call_Relocation::spec(), RELOC_IMM32 );
1920 }
1921 if( _method ) { // Emit stub for static call
1922 emit_java_to_interp(cbuf);
1923 }
1924 %}
1926 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1927 // !!!!!
1928 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1929 // emit_call_dynamic_prologue( cbuf );
1930 cbuf.set_inst_mark();
1931 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1932 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1933 address virtual_call_oop_addr = cbuf.inst_mark();
1934 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1935 // who we intended to call.
1936 cbuf.set_inst_mark();
1937 $$$emit8$primary;
1938 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1939 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1940 %}
1942 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1943 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1944 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1946 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1947 cbuf.set_inst_mark();
1948 $$$emit8$primary;
1949 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1950 emit_d8(cbuf, disp); // Displacement
1952 %}
1954 enc_class Xor_Reg (eRegI dst) %{
1955 emit_opcode(cbuf, 0x33);
1956 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1957 %}
1959 // Following encoding is no longer used, but may be restored if calling
1960 // convention changes significantly.
1961 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1962 //
1963 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1964 // // int ic_reg = Matcher::inline_cache_reg();
1965 // // int ic_encode = Matcher::_regEncode[ic_reg];
1966 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1967 // // int imo_encode = Matcher::_regEncode[imo_reg];
1968 //
1969 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1970 // // // so we load it immediately before the call
1971 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1972 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1973 //
1974 // // xor rbp,ebp
1975 // emit_opcode(cbuf, 0x33);
1976 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1977 //
1978 // // CALL to interpreter.
1979 // cbuf.set_inst_mark();
1980 // $$$emit8$primary;
1981 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1982 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1983 // %}
1985 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1986 $$$emit8$primary;
1987 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1988 $$$emit8$shift$$constant;
1989 %}
1991 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1992 // Load immediate does not have a zero or sign extended version
1993 // for 8-bit immediates
1994 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1995 $$$emit32$src$$constant;
1996 %}
1998 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1999 // Load immediate does not have a zero or sign extended version
2000 // for 8-bit immediates
2001 emit_opcode(cbuf, $primary + $dst$$reg);
2002 $$$emit32$src$$constant;
2003 %}
2005 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
2006 // Load immediate does not have a zero or sign extended version
2007 // for 8-bit immediates
2008 int dst_enc = $dst$$reg;
2009 int src_con = $src$$constant & 0x0FFFFFFFFL;
2010 if (src_con == 0) {
2011 // xor dst, dst
2012 emit_opcode(cbuf, 0x33);
2013 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2014 } else {
2015 emit_opcode(cbuf, $primary + dst_enc);
2016 emit_d32(cbuf, src_con);
2017 }
2018 %}
2020 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
2021 // Load immediate does not have a zero or sign extended version
2022 // for 8-bit immediates
2023 int dst_enc = $dst$$reg + 2;
2024 int src_con = ((julong)($src$$constant)) >> 32;
2025 if (src_con == 0) {
2026 // xor dst, dst
2027 emit_opcode(cbuf, 0x33);
2028 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2029 } else {
2030 emit_opcode(cbuf, $primary + dst_enc);
2031 emit_d32(cbuf, src_con);
2032 }
2033 %}
2036 enc_class LdImmD (immD src) %{ // Load Immediate
2037 if( is_positive_zero_double($src$$constant)) {
2038 // FLDZ
2039 emit_opcode(cbuf,0xD9);
2040 emit_opcode(cbuf,0xEE);
2041 } else if( is_positive_one_double($src$$constant)) {
2042 // FLD1
2043 emit_opcode(cbuf,0xD9);
2044 emit_opcode(cbuf,0xE8);
2045 } else {
2046 emit_opcode(cbuf,0xDD);
2047 emit_rm(cbuf, 0x0, 0x0, 0x5);
2048 emit_double_constant(cbuf, $src$$constant);
2049 }
2050 %}
2053 enc_class LdImmF (immF src) %{ // Load Immediate
2054 if( is_positive_zero_float($src$$constant)) {
2055 emit_opcode(cbuf,0xD9);
2056 emit_opcode(cbuf,0xEE);
2057 } else if( is_positive_one_float($src$$constant)) {
2058 emit_opcode(cbuf,0xD9);
2059 emit_opcode(cbuf,0xE8);
2060 } else {
2061 $$$emit8$primary;
2062 // Load immediate does not have a zero or sign extended version
2063 // for 8-bit immediates
2064 // First load to TOS, then move to dst
2065 emit_rm(cbuf, 0x0, 0x0, 0x5);
2066 emit_float_constant(cbuf, $src$$constant);
2067 }
2068 %}
2070 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
2071 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2072 emit_float_constant(cbuf, $con$$constant);
2073 %}
2075 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
2076 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2077 emit_double_constant(cbuf, $con$$constant);
2078 %}
2080 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
2081 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2082 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2083 emit_opcode(cbuf, 0x0F);
2084 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2085 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
2086 emit_double_constant(cbuf, $con$$constant);
2087 %}
2089 enc_class Opc_MemImm_F(immF src) %{
2090 cbuf.set_inst_mark();
2091 $$$emit8$primary;
2092 emit_rm(cbuf, 0x0, $secondary, 0x5);
2093 emit_float_constant(cbuf, $src$$constant);
2094 %}
2097 enc_class MovI2X_reg(regX dst, eRegI src) %{
2098 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2099 emit_opcode(cbuf, 0x0F );
2100 emit_opcode(cbuf, 0x6E );
2101 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2102 %}
2104 enc_class MovX2I_reg(eRegI dst, regX src) %{
2105 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
2106 emit_opcode(cbuf, 0x0F );
2107 emit_opcode(cbuf, 0x7E );
2108 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2109 %}
2111 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
2112 { // MOVD $dst,$src.lo
2113 emit_opcode(cbuf,0x66);
2114 emit_opcode(cbuf,0x0F);
2115 emit_opcode(cbuf,0x6E);
2116 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2117 }
2118 { // MOVD $tmp,$src.hi
2119 emit_opcode(cbuf,0x66);
2120 emit_opcode(cbuf,0x0F);
2121 emit_opcode(cbuf,0x6E);
2122 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2123 }
2124 { // PUNPCKLDQ $dst,$tmp
2125 emit_opcode(cbuf,0x66);
2126 emit_opcode(cbuf,0x0F);
2127 emit_opcode(cbuf,0x62);
2128 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2129 }
2130 %}
2132 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2133 { // MOVD $dst.lo,$src
2134 emit_opcode(cbuf,0x66);
2135 emit_opcode(cbuf,0x0F);
2136 emit_opcode(cbuf,0x7E);
2137 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2138 }
2139 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2140 emit_opcode(cbuf,0xF2);
2141 emit_opcode(cbuf,0x0F);
2142 emit_opcode(cbuf,0x70);
2143 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2144 emit_d8(cbuf, 0x4E);
2145 }
2146 { // MOVD $dst.hi,$tmp
2147 emit_opcode(cbuf,0x66);
2148 emit_opcode(cbuf,0x0F);
2149 emit_opcode(cbuf,0x7E);
2150 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2151 }
2152 %}
2155 // Encode a reg-reg copy. If it is useless, then empty encoding.
2156 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2157 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2158 %}
2160 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2161 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2162 %}
2164 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2165 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2166 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2167 %}
2169 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2170 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2171 %}
2173 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2174 $$$emit8$primary;
2175 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2176 %}
2178 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2179 $$$emit8$secondary;
2180 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2181 %}
2183 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2184 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2185 %}
2187 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2188 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2189 %}
2191 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2192 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2193 %}
2195 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2196 // Output immediate
2197 $$$emit32$src$$constant;
2198 %}
2200 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2201 // Output Float immediate bits
2202 jfloat jf = $src$$constant;
2203 int jf_as_bits = jint_cast( jf );
2204 emit_d32(cbuf, jf_as_bits);
2205 %}
2207 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2208 // Output Float immediate bits
2209 jfloat jf = $src$$constant;
2210 int jf_as_bits = jint_cast( jf );
2211 emit_d32(cbuf, jf_as_bits);
2212 %}
2214 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2215 // Output immediate
2216 $$$emit16$src$$constant;
2217 %}
2219 enc_class Con_d32(immI src) %{
2220 emit_d32(cbuf,$src$$constant);
2221 %}
2223 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2224 // Output immediate memory reference
2225 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2226 emit_d32(cbuf, 0x00);
2227 %}
2229 enc_class lock_prefix( ) %{
2230 if( os::is_MP() )
2231 emit_opcode(cbuf,0xF0); // [Lock]
2232 %}
2234 // Cmp-xchg long value.
2235 // Note: we need to swap rbx, and rcx before and after the
2236 // cmpxchg8 instruction because the instruction uses
2237 // rcx as the high order word of the new value to store but
2238 // our register encoding uses rbx,.
2239 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2241 // XCHG rbx,ecx
2242 emit_opcode(cbuf,0x87);
2243 emit_opcode(cbuf,0xD9);
2244 // [Lock]
2245 if( os::is_MP() )
2246 emit_opcode(cbuf,0xF0);
2247 // CMPXCHG8 [Eptr]
2248 emit_opcode(cbuf,0x0F);
2249 emit_opcode(cbuf,0xC7);
2250 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2251 // XCHG rbx,ecx
2252 emit_opcode(cbuf,0x87);
2253 emit_opcode(cbuf,0xD9);
2254 %}
2256 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2257 // [Lock]
2258 if( os::is_MP() )
2259 emit_opcode(cbuf,0xF0);
2261 // CMPXCHG [Eptr]
2262 emit_opcode(cbuf,0x0F);
2263 emit_opcode(cbuf,0xB1);
2264 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2265 %}
2267 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2268 int res_encoding = $res$$reg;
2270 // MOV res,0
2271 emit_opcode( cbuf, 0xB8 + res_encoding);
2272 emit_d32( cbuf, 0 );
2273 // JNE,s fail
2274 emit_opcode(cbuf,0x75);
2275 emit_d8(cbuf, 5 );
2276 // MOV res,1
2277 emit_opcode( cbuf, 0xB8 + res_encoding);
2278 emit_d32( cbuf, 1 );
2279 // fail:
2280 %}
2282 enc_class set_instruction_start( ) %{
2283 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2284 %}
2286 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2287 int reg_encoding = $ereg$$reg;
2288 int base = $mem$$base;
2289 int index = $mem$$index;
2290 int scale = $mem$$scale;
2291 int displace = $mem$$disp;
2292 bool disp_is_oop = $mem->disp_is_oop();
2293 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2294 %}
2296 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2297 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2298 int base = $mem$$base;
2299 int index = $mem$$index;
2300 int scale = $mem$$scale;
2301 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2302 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2303 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2304 %}
2306 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2307 int r1, r2;
2308 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2309 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2310 emit_opcode(cbuf,0x0F);
2311 emit_opcode(cbuf,$tertiary);
2312 emit_rm(cbuf, 0x3, r1, r2);
2313 emit_d8(cbuf,$cnt$$constant);
2314 emit_d8(cbuf,$primary);
2315 emit_rm(cbuf, 0x3, $secondary, r1);
2316 emit_d8(cbuf,$cnt$$constant);
2317 %}
2319 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2320 emit_opcode( cbuf, 0x8B ); // Move
2321 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2322 emit_d8(cbuf,$primary);
2323 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2324 emit_d8(cbuf,$cnt$$constant-32);
2325 emit_d8(cbuf,$primary);
2326 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2327 emit_d8(cbuf,31);
2328 %}
2330 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2331 int r1, r2;
2332 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2333 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2335 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2336 emit_rm(cbuf, 0x3, r1, r2);
2337 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2338 emit_opcode(cbuf,$primary);
2339 emit_rm(cbuf, 0x3, $secondary, r1);
2340 emit_d8(cbuf,$cnt$$constant-32);
2341 }
2342 emit_opcode(cbuf,0x33); // XOR r2,r2
2343 emit_rm(cbuf, 0x3, r2, r2);
2344 %}
2346 // Clone of RegMem but accepts an extra parameter to access each
2347 // half of a double in memory; it never needs relocation info.
2348 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2349 emit_opcode(cbuf,$opcode$$constant);
2350 int reg_encoding = $rm_reg$$reg;
2351 int base = $mem$$base;
2352 int index = $mem$$index;
2353 int scale = $mem$$scale;
2354 int displace = $mem$$disp + $disp_for_half$$constant;
2355 bool disp_is_oop = false;
2356 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2357 %}
2359 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2360 //
2361 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2362 // and it never needs relocation information.
2363 // Frequently used to move data between FPU's Stack Top and memory.
2364 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2365 int rm_byte_opcode = $rm_opcode$$constant;
2366 int base = $mem$$base;
2367 int index = $mem$$index;
2368 int scale = $mem$$scale;
2369 int displace = $mem$$disp;
2370 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2371 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2372 %}
2374 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2375 int rm_byte_opcode = $rm_opcode$$constant;
2376 int base = $mem$$base;
2377 int index = $mem$$index;
2378 int scale = $mem$$scale;
2379 int displace = $mem$$disp;
2380 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2381 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2382 %}
2384 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2385 int reg_encoding = $dst$$reg;
2386 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2387 int index = 0x04; // 0x04 indicates no index
2388 int scale = 0x00; // 0x00 indicates no scale
2389 int displace = $src1$$constant; // 0x00 indicates no displacement
2390 bool disp_is_oop = false;
2391 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2392 %}
2394 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2395 // Compare dst,src
2396 emit_opcode(cbuf,0x3B);
2397 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2398 // jmp dst < src around move
2399 emit_opcode(cbuf,0x7C);
2400 emit_d8(cbuf,2);
2401 // move dst,src
2402 emit_opcode(cbuf,0x8B);
2403 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2404 %}
2406 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2407 // Compare dst,src
2408 emit_opcode(cbuf,0x3B);
2409 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2410 // jmp dst > src around move
2411 emit_opcode(cbuf,0x7F);
2412 emit_d8(cbuf,2);
2413 // move dst,src
2414 emit_opcode(cbuf,0x8B);
2415 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2416 %}
2418 enc_class enc_FP_store(memory mem, regD src) %{
2419 // If src is FPR1, we can just FST to store it.
2420 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2421 int reg_encoding = 0x2; // Just store
2422 int base = $mem$$base;
2423 int index = $mem$$index;
2424 int scale = $mem$$scale;
2425 int displace = $mem$$disp;
2426 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2427 if( $src$$reg != FPR1L_enc ) {
2428 reg_encoding = 0x3; // Store & pop
2429 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2430 emit_d8( cbuf, 0xC0-1+$src$$reg );
2431 }
2432 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2433 emit_opcode(cbuf,$primary);
2434 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2435 %}
2437 enc_class neg_reg(eRegI dst) %{
2438 // NEG $dst
2439 emit_opcode(cbuf,0xF7);
2440 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2441 %}
2443 enc_class setLT_reg(eCXRegI dst) %{
2444 // SETLT $dst
2445 emit_opcode(cbuf,0x0F);
2446 emit_opcode(cbuf,0x9C);
2447 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2448 %}
2450 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2451 int tmpReg = $tmp$$reg;
2453 // SUB $p,$q
2454 emit_opcode(cbuf,0x2B);
2455 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2456 // SBB $tmp,$tmp
2457 emit_opcode(cbuf,0x1B);
2458 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2459 // AND $tmp,$y
2460 emit_opcode(cbuf,0x23);
2461 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2462 // ADD $p,$tmp
2463 emit_opcode(cbuf,0x03);
2464 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2465 %}
2467 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2468 int tmpReg = $tmp$$reg;
2470 // SUB $p,$q
2471 emit_opcode(cbuf,0x2B);
2472 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2473 // SBB $tmp,$tmp
2474 emit_opcode(cbuf,0x1B);
2475 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2476 // AND $tmp,$y
2477 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2478 emit_opcode(cbuf,0x23);
2479 int reg_encoding = tmpReg;
2480 int base = $mem$$base;
2481 int index = $mem$$index;
2482 int scale = $mem$$scale;
2483 int displace = $mem$$disp;
2484 bool disp_is_oop = $mem->disp_is_oop();
2485 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2486 // ADD $p,$tmp
2487 emit_opcode(cbuf,0x03);
2488 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2489 %}
2491 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2492 // TEST shift,32
2493 emit_opcode(cbuf,0xF7);
2494 emit_rm(cbuf, 0x3, 0, ECX_enc);
2495 emit_d32(cbuf,0x20);
2496 // JEQ,s small
2497 emit_opcode(cbuf, 0x74);
2498 emit_d8(cbuf, 0x04);
2499 // MOV $dst.hi,$dst.lo
2500 emit_opcode( cbuf, 0x8B );
2501 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2502 // CLR $dst.lo
2503 emit_opcode(cbuf, 0x33);
2504 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2505 // small:
2506 // SHLD $dst.hi,$dst.lo,$shift
2507 emit_opcode(cbuf,0x0F);
2508 emit_opcode(cbuf,0xA5);
2509 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2510 // SHL $dst.lo,$shift"
2511 emit_opcode(cbuf,0xD3);
2512 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2513 %}
2515 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2516 // TEST shift,32
2517 emit_opcode(cbuf,0xF7);
2518 emit_rm(cbuf, 0x3, 0, ECX_enc);
2519 emit_d32(cbuf,0x20);
2520 // JEQ,s small
2521 emit_opcode(cbuf, 0x74);
2522 emit_d8(cbuf, 0x04);
2523 // MOV $dst.lo,$dst.hi
2524 emit_opcode( cbuf, 0x8B );
2525 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2526 // CLR $dst.hi
2527 emit_opcode(cbuf, 0x33);
2528 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2529 // small:
2530 // SHRD $dst.lo,$dst.hi,$shift
2531 emit_opcode(cbuf,0x0F);
2532 emit_opcode(cbuf,0xAD);
2533 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2534 // SHR $dst.hi,$shift"
2535 emit_opcode(cbuf,0xD3);
2536 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2537 %}
2539 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2540 // TEST shift,32
2541 emit_opcode(cbuf,0xF7);
2542 emit_rm(cbuf, 0x3, 0, ECX_enc);
2543 emit_d32(cbuf,0x20);
2544 // JEQ,s small
2545 emit_opcode(cbuf, 0x74);
2546 emit_d8(cbuf, 0x05);
2547 // MOV $dst.lo,$dst.hi
2548 emit_opcode( cbuf, 0x8B );
2549 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2550 // SAR $dst.hi,31
2551 emit_opcode(cbuf, 0xC1);
2552 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2553 emit_d8(cbuf, 0x1F );
2554 // small:
2555 // SHRD $dst.lo,$dst.hi,$shift
2556 emit_opcode(cbuf,0x0F);
2557 emit_opcode(cbuf,0xAD);
2558 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2559 // SAR $dst.hi,$shift"
2560 emit_opcode(cbuf,0xD3);
2561 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2562 %}
2565 // ----------------- Encodings for floating point unit -----------------
2566 // May leave result in FPU-TOS or FPU reg depending on opcodes
2567 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2568 $$$emit8$primary;
2569 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2570 %}
2572 // Pop argument in FPR0 with FSTP ST(0)
2573 enc_class PopFPU() %{
2574 emit_opcode( cbuf, 0xDD );
2575 emit_d8( cbuf, 0xD8 );
2576 %}
2578 // !!!!! equivalent to Pop_Reg_F
2579 enc_class Pop_Reg_D( regD dst ) %{
2580 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2581 emit_d8( cbuf, 0xD8+$dst$$reg );
2582 %}
2584 enc_class Push_Reg_D( regD dst ) %{
2585 emit_opcode( cbuf, 0xD9 );
2586 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2587 %}
2589 enc_class strictfp_bias1( regD dst ) %{
2590 emit_opcode( cbuf, 0xDB ); // FLD m80real
2591 emit_opcode( cbuf, 0x2D );
2592 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2593 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2594 emit_opcode( cbuf, 0xC8+$dst$$reg );
2595 %}
2597 enc_class strictfp_bias2( regD dst ) %{
2598 emit_opcode( cbuf, 0xDB ); // FLD m80real
2599 emit_opcode( cbuf, 0x2D );
2600 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2601 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2602 emit_opcode( cbuf, 0xC8+$dst$$reg );
2603 %}
2605 // Special case for moving an integer register to a stack slot.
2606 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2607 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2608 %}
2610 // Special case for moving a register to a stack slot.
2611 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2612 // Opcode already emitted
2613 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2614 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2615 emit_d32(cbuf, $dst$$disp); // Displacement
2616 %}
2618 // Push the integer in stackSlot 'src' onto FP-stack
2619 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2620 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2621 %}
2623 // Push the float in stackSlot 'src' onto FP-stack
2624 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2625 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2626 %}
2628 // Push the double in stackSlot 'src' onto FP-stack
2629 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2630 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2631 %}
2633 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2634 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2635 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2636 %}
2638 // Same as Pop_Mem_F except for opcode
2639 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2640 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2641 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2642 %}
2644 enc_class Pop_Reg_F( regF dst ) %{
2645 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2646 emit_d8( cbuf, 0xD8+$dst$$reg );
2647 %}
2649 enc_class Push_Reg_F( regF dst ) %{
2650 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2651 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2652 %}
2654 // Push FPU's float to a stack-slot, and pop FPU-stack
2655 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2656 int pop = 0x02;
2657 if ($src$$reg != FPR1L_enc) {
2658 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2659 emit_d8( cbuf, 0xC0-1+$src$$reg );
2660 pop = 0x03;
2661 }
2662 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2663 %}
2665 // Push FPU's double to a stack-slot, and pop FPU-stack
2666 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2667 int pop = 0x02;
2668 if ($src$$reg != FPR1L_enc) {
2669 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2670 emit_d8( cbuf, 0xC0-1+$src$$reg );
2671 pop = 0x03;
2672 }
2673 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2674 %}
2676 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2677 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2678 int pop = 0xD0 - 1; // -1 since we skip FLD
2679 if ($src$$reg != FPR1L_enc) {
2680 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2681 emit_d8( cbuf, 0xC0-1+$src$$reg );
2682 pop = 0xD8;
2683 }
2684 emit_opcode( cbuf, 0xDD );
2685 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2686 %}
2689 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2690 MacroAssembler masm(&cbuf);
2691 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2692 masm.fmul( $src2$$reg+0); // value at TOS
2693 masm.fadd( $src$$reg+0); // value at TOS
2694 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2695 %}
2698 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2699 // load dst in FPR0
2700 emit_opcode( cbuf, 0xD9 );
2701 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2702 if ($src$$reg != FPR1L_enc) {
2703 // fincstp
2704 emit_opcode (cbuf, 0xD9);
2705 emit_opcode (cbuf, 0xF7);
2706 // swap src with FPR1:
2707 // FXCH FPR1 with src
2708 emit_opcode(cbuf, 0xD9);
2709 emit_d8(cbuf, 0xC8-1+$src$$reg );
2710 // fdecstp
2711 emit_opcode (cbuf, 0xD9);
2712 emit_opcode (cbuf, 0xF6);
2713 }
2714 %}
2716 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2717 // Allocate a word
2718 emit_opcode(cbuf,0x83); // SUB ESP,8
2719 emit_opcode(cbuf,0xEC);
2720 emit_d8(cbuf,0x08);
2722 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2723 emit_opcode (cbuf, 0x0F );
2724 emit_opcode (cbuf, 0x11 );
2725 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2727 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2728 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2730 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2731 emit_opcode (cbuf, 0x0F );
2732 emit_opcode (cbuf, 0x11 );
2733 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2735 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2736 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2738 %}
2740 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2741 // Allocate a word
2742 emit_opcode(cbuf,0x83); // SUB ESP,4
2743 emit_opcode(cbuf,0xEC);
2744 emit_d8(cbuf,0x04);
2746 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2747 emit_opcode (cbuf, 0x0F );
2748 emit_opcode (cbuf, 0x11 );
2749 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2751 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2752 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2754 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2755 emit_opcode (cbuf, 0x0F );
2756 emit_opcode (cbuf, 0x11 );
2757 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2759 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2760 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2762 %}
2764 enc_class Push_ResultXD(regXD dst) %{
2765 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2767 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2768 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2769 emit_opcode (cbuf, 0x0F );
2770 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2771 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2773 emit_opcode(cbuf,0x83); // ADD ESP,8
2774 emit_opcode(cbuf,0xC4);
2775 emit_d8(cbuf,0x08);
2776 %}
2778 enc_class Push_ResultX(regX dst, immI d8) %{
2779 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2781 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2782 emit_opcode (cbuf, 0x0F );
2783 emit_opcode (cbuf, 0x10 );
2784 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2786 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2787 emit_opcode(cbuf,0xC4);
2788 emit_d8(cbuf,$d8$$constant);
2789 %}
2791 enc_class Push_SrcXD(regXD src) %{
2792 // Allocate a word
2793 emit_opcode(cbuf,0x83); // SUB ESP,8
2794 emit_opcode(cbuf,0xEC);
2795 emit_d8(cbuf,0x08);
2797 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2798 emit_opcode (cbuf, 0x0F );
2799 emit_opcode (cbuf, 0x11 );
2800 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2802 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2803 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2804 %}
2806 enc_class push_stack_temp_qword() %{
2807 emit_opcode(cbuf,0x83); // SUB ESP,8
2808 emit_opcode(cbuf,0xEC);
2809 emit_d8 (cbuf,0x08);
2810 %}
2812 enc_class pop_stack_temp_qword() %{
2813 emit_opcode(cbuf,0x83); // ADD ESP,8
2814 emit_opcode(cbuf,0xC4);
2815 emit_d8 (cbuf,0x08);
2816 %}
2818 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2819 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2820 emit_opcode (cbuf, 0x0F );
2821 emit_opcode (cbuf, 0x11 );
2822 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2824 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2825 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2826 %}
2828 // Compute X^Y using Intel's fast hardware instructions, if possible.
2829 // Otherwise return a NaN.
2830 enc_class pow_exp_core_encoding %{
2831 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2832 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2833 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2834 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2835 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2836 emit_opcode(cbuf,0x1C);
2837 emit_d8(cbuf,0x24);
2838 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2839 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2840 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2841 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2842 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2843 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2844 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2845 emit_d32(cbuf,0xFFFFF800);
2846 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2847 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2848 emit_d32(cbuf,1023);
2849 emit_opcode(cbuf,0x8B); // mov rbx,eax
2850 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2851 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2852 emit_rm(cbuf,0x3,0x4,EAX_enc);
2853 emit_d8(cbuf,20);
2854 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2855 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2856 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2857 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2858 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2859 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2860 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2861 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2862 emit_d32(cbuf,0);
2863 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2864 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2865 %}
2867 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2868 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2870 enc_class Push_Result_Mod_D( regD src) %{
2871 if ($src$$reg != FPR1L_enc) {
2872 // fincstp
2873 emit_opcode (cbuf, 0xD9);
2874 emit_opcode (cbuf, 0xF7);
2875 // FXCH FPR1 with src
2876 emit_opcode(cbuf, 0xD9);
2877 emit_d8(cbuf, 0xC8-1+$src$$reg );
2878 // fdecstp
2879 emit_opcode (cbuf, 0xD9);
2880 emit_opcode (cbuf, 0xF6);
2881 }
2882 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2883 // // FSTP FPR$dst$$reg
2884 // emit_opcode( cbuf, 0xDD );
2885 // emit_d8( cbuf, 0xD8+$dst$$reg );
2886 %}
2888 enc_class fnstsw_sahf_skip_parity() %{
2889 // fnstsw ax
2890 emit_opcode( cbuf, 0xDF );
2891 emit_opcode( cbuf, 0xE0 );
2892 // sahf
2893 emit_opcode( cbuf, 0x9E );
2894 // jnp ::skip
2895 emit_opcode( cbuf, 0x7B );
2896 emit_opcode( cbuf, 0x05 );
2897 %}
2899 enc_class emitModD() %{
2900 // fprem must be iterative
2901 // :: loop
2902 // fprem
2903 emit_opcode( cbuf, 0xD9 );
2904 emit_opcode( cbuf, 0xF8 );
2905 // wait
2906 emit_opcode( cbuf, 0x9b );
2907 // fnstsw ax
2908 emit_opcode( cbuf, 0xDF );
2909 emit_opcode( cbuf, 0xE0 );
2910 // sahf
2911 emit_opcode( cbuf, 0x9E );
2912 // jp ::loop
2913 emit_opcode( cbuf, 0x0F );
2914 emit_opcode( cbuf, 0x8A );
2915 emit_opcode( cbuf, 0xF4 );
2916 emit_opcode( cbuf, 0xFF );
2917 emit_opcode( cbuf, 0xFF );
2918 emit_opcode( cbuf, 0xFF );
2919 %}
2921 enc_class fpu_flags() %{
2922 // fnstsw_ax
2923 emit_opcode( cbuf, 0xDF);
2924 emit_opcode( cbuf, 0xE0);
2925 // test ax,0x0400
2926 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2927 emit_opcode( cbuf, 0xA9 );
2928 emit_d16 ( cbuf, 0x0400 );
2929 // // // This sequence works, but stalls for 12-16 cycles on PPro
2930 // // test rax,0x0400
2931 // emit_opcode( cbuf, 0xA9 );
2932 // emit_d32 ( cbuf, 0x00000400 );
2933 //
2934 // jz exit (no unordered comparison)
2935 emit_opcode( cbuf, 0x74 );
2936 emit_d8 ( cbuf, 0x02 );
2937 // mov ah,1 - treat as LT case (set carry flag)
2938 emit_opcode( cbuf, 0xB4 );
2939 emit_d8 ( cbuf, 0x01 );
2940 // sahf
2941 emit_opcode( cbuf, 0x9E);
2942 %}
2944 enc_class cmpF_P6_fixup() %{
2945 // Fixup the integer flags in case comparison involved a NaN
2946 //
2947 // JNP exit (no unordered comparison, P-flag is set by NaN)
2948 emit_opcode( cbuf, 0x7B );
2949 emit_d8 ( cbuf, 0x03 );
2950 // MOV AH,1 - treat as LT case (set carry flag)
2951 emit_opcode( cbuf, 0xB4 );
2952 emit_d8 ( cbuf, 0x01 );
2953 // SAHF
2954 emit_opcode( cbuf, 0x9E);
2955 // NOP // target for branch to avoid branch to branch
2956 emit_opcode( cbuf, 0x90);
2957 %}
2959 // fnstsw_ax();
2960 // sahf();
2961 // movl(dst, nan_result);
2962 // jcc(Assembler::parity, exit);
2963 // movl(dst, less_result);
2964 // jcc(Assembler::below, exit);
2965 // movl(dst, equal_result);
2966 // jcc(Assembler::equal, exit);
2967 // movl(dst, greater_result);
2969 // less_result = 1;
2970 // greater_result = -1;
2971 // equal_result = 0;
2972 // nan_result = -1;
2974 enc_class CmpF_Result(eRegI dst) %{
2975 // fnstsw_ax();
2976 emit_opcode( cbuf, 0xDF);
2977 emit_opcode( cbuf, 0xE0);
2978 // sahf
2979 emit_opcode( cbuf, 0x9E);
2980 // movl(dst, nan_result);
2981 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2982 emit_d32( cbuf, -1 );
2983 // jcc(Assembler::parity, exit);
2984 emit_opcode( cbuf, 0x7A );
2985 emit_d8 ( cbuf, 0x13 );
2986 // movl(dst, less_result);
2987 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2988 emit_d32( cbuf, -1 );
2989 // jcc(Assembler::below, exit);
2990 emit_opcode( cbuf, 0x72 );
2991 emit_d8 ( cbuf, 0x0C );
2992 // movl(dst, equal_result);
2993 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2994 emit_d32( cbuf, 0 );
2995 // jcc(Assembler::equal, exit);
2996 emit_opcode( cbuf, 0x74 );
2997 emit_d8 ( cbuf, 0x05 );
2998 // movl(dst, greater_result);
2999 emit_opcode( cbuf, 0xB8 + $dst$$reg);
3000 emit_d32( cbuf, 1 );
3001 %}
3004 // XMM version of CmpF_Result. Because the XMM compare
3005 // instructions set the EFLAGS directly. It becomes simpler than
3006 // the float version above.
3007 enc_class CmpX_Result(eRegI dst) %{
3008 MacroAssembler _masm(&cbuf);
3009 Label nan, inc, done;
3011 __ jccb(Assembler::parity, nan);
3012 __ jccb(Assembler::equal, done);
3013 __ jccb(Assembler::above, inc);
3014 __ bind(nan);
3015 __ decrement(as_Register($dst$$reg)); // NO L qqq
3016 __ jmpb(done);
3017 __ bind(inc);
3018 __ increment(as_Register($dst$$reg)); // NO L qqq
3019 __ bind(done);
3020 %}
3022 // Compare the longs and set flags
3023 // BROKEN! Do Not use as-is
3024 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
3025 // CMP $src1.hi,$src2.hi
3026 emit_opcode( cbuf, 0x3B );
3027 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3028 // JNE,s done
3029 emit_opcode(cbuf,0x75);
3030 emit_d8(cbuf, 2 );
3031 // CMP $src1.lo,$src2.lo
3032 emit_opcode( cbuf, 0x3B );
3033 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3034 // done:
3035 %}
3037 enc_class convert_int_long( regL dst, eRegI src ) %{
3038 // mov $dst.lo,$src
3039 int dst_encoding = $dst$$reg;
3040 int src_encoding = $src$$reg;
3041 encode_Copy( cbuf, dst_encoding , src_encoding );
3042 // mov $dst.hi,$src
3043 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
3044 // sar $dst.hi,31
3045 emit_opcode( cbuf, 0xC1 );
3046 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
3047 emit_d8(cbuf, 0x1F );
3048 %}
3050 enc_class convert_long_double( eRegL src ) %{
3051 // push $src.hi
3052 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
3053 // push $src.lo
3054 emit_opcode(cbuf, 0x50+$src$$reg );
3055 // fild 64-bits at [SP]
3056 emit_opcode(cbuf,0xdf);
3057 emit_d8(cbuf, 0x6C);
3058 emit_d8(cbuf, 0x24);
3059 emit_d8(cbuf, 0x00);
3060 // pop stack
3061 emit_opcode(cbuf, 0x83); // add SP, #8
3062 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3063 emit_d8(cbuf, 0x8);
3064 %}
3066 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
3067 // IMUL EDX:EAX,$src1
3068 emit_opcode( cbuf, 0xF7 );
3069 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
3070 // SAR EDX,$cnt-32
3071 int shift_count = ((int)$cnt$$constant) - 32;
3072 if (shift_count > 0) {
3073 emit_opcode(cbuf, 0xC1);
3074 emit_rm(cbuf, 0x3, 7, $dst$$reg );
3075 emit_d8(cbuf, shift_count);
3076 }
3077 %}
3079 // this version doesn't have add sp, 8
3080 enc_class convert_long_double2( eRegL src ) %{
3081 // push $src.hi
3082 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
3083 // push $src.lo
3084 emit_opcode(cbuf, 0x50+$src$$reg );
3085 // fild 64-bits at [SP]
3086 emit_opcode(cbuf,0xdf);
3087 emit_d8(cbuf, 0x6C);
3088 emit_d8(cbuf, 0x24);
3089 emit_d8(cbuf, 0x00);
3090 %}
3092 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
3093 // Basic idea: long = (long)int * (long)int
3094 // IMUL EDX:EAX, src
3095 emit_opcode( cbuf, 0xF7 );
3096 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
3097 %}
3099 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
3100 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
3101 // MUL EDX:EAX, src
3102 emit_opcode( cbuf, 0xF7 );
3103 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
3104 %}
3106 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
3107 // Basic idea: lo(result) = lo(x_lo * y_lo)
3108 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3109 // MOV $tmp,$src.lo
3110 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
3111 // IMUL $tmp,EDX
3112 emit_opcode( cbuf, 0x0F );
3113 emit_opcode( cbuf, 0xAF );
3114 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3115 // MOV EDX,$src.hi
3116 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3117 // IMUL EDX,EAX
3118 emit_opcode( cbuf, 0x0F );
3119 emit_opcode( cbuf, 0xAF );
3120 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3121 // ADD $tmp,EDX
3122 emit_opcode( cbuf, 0x03 );
3123 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3124 // MUL EDX:EAX,$src.lo
3125 emit_opcode( cbuf, 0xF7 );
3126 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3127 // ADD EDX,ESI
3128 emit_opcode( cbuf, 0x03 );
3129 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3130 %}
3132 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3133 // Basic idea: lo(result) = lo(src * y_lo)
3134 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3135 // IMUL $tmp,EDX,$src
3136 emit_opcode( cbuf, 0x6B );
3137 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3138 emit_d8( cbuf, (int)$src$$constant );
3139 // MOV EDX,$src
3140 emit_opcode(cbuf, 0xB8 + EDX_enc);
3141 emit_d32( cbuf, (int)$src$$constant );
3142 // MUL EDX:EAX,EDX
3143 emit_opcode( cbuf, 0xF7 );
3144 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3145 // ADD EDX,ESI
3146 emit_opcode( cbuf, 0x03 );
3147 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3148 %}
3150 enc_class long_div( eRegL src1, eRegL src2 ) %{
3151 // PUSH src1.hi
3152 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3153 // PUSH src1.lo
3154 emit_opcode(cbuf, 0x50+$src1$$reg );
3155 // PUSH src2.hi
3156 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3157 // PUSH src2.lo
3158 emit_opcode(cbuf, 0x50+$src2$$reg );
3159 // CALL directly to the runtime
3160 cbuf.set_inst_mark();
3161 emit_opcode(cbuf,0xE8); // Call into runtime
3162 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3163 // Restore stack
3164 emit_opcode(cbuf, 0x83); // add SP, #framesize
3165 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3166 emit_d8(cbuf, 4*4);
3167 %}
3169 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3170 // PUSH src1.hi
3171 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3172 // PUSH src1.lo
3173 emit_opcode(cbuf, 0x50+$src1$$reg );
3174 // PUSH src2.hi
3175 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3176 // PUSH src2.lo
3177 emit_opcode(cbuf, 0x50+$src2$$reg );
3178 // CALL directly to the runtime
3179 cbuf.set_inst_mark();
3180 emit_opcode(cbuf,0xE8); // Call into runtime
3181 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3182 // Restore stack
3183 emit_opcode(cbuf, 0x83); // add SP, #framesize
3184 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3185 emit_d8(cbuf, 4*4);
3186 %}
3188 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3189 // MOV $tmp,$src.lo
3190 emit_opcode(cbuf, 0x8B);
3191 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3192 // OR $tmp,$src.hi
3193 emit_opcode(cbuf, 0x0B);
3194 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3195 %}
3197 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3198 // CMP $src1.lo,$src2.lo
3199 emit_opcode( cbuf, 0x3B );
3200 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3201 // JNE,s skip
3202 emit_cc(cbuf, 0x70, 0x5);
3203 emit_d8(cbuf,2);
3204 // CMP $src1.hi,$src2.hi
3205 emit_opcode( cbuf, 0x3B );
3206 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3207 %}
3209 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3210 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3211 emit_opcode( cbuf, 0x3B );
3212 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3213 // MOV $tmp,$src1.hi
3214 emit_opcode( cbuf, 0x8B );
3215 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3216 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3217 emit_opcode( cbuf, 0x1B );
3218 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3219 %}
3221 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3222 // XOR $tmp,$tmp
3223 emit_opcode(cbuf,0x33); // XOR
3224 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3225 // CMP $tmp,$src.lo
3226 emit_opcode( cbuf, 0x3B );
3227 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3228 // SBB $tmp,$src.hi
3229 emit_opcode( cbuf, 0x1B );
3230 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3231 %}
3233 // Sniff, sniff... smells like Gnu Superoptimizer
3234 enc_class neg_long( eRegL dst ) %{
3235 emit_opcode(cbuf,0xF7); // NEG hi
3236 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3237 emit_opcode(cbuf,0xF7); // NEG lo
3238 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3239 emit_opcode(cbuf,0x83); // SBB hi,0
3240 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3241 emit_d8 (cbuf,0 );
3242 %}
3244 enc_class movq_ld(regXD dst, memory mem) %{
3245 MacroAssembler _masm(&cbuf);
3246 __ movq($dst$$XMMRegister, $mem$$Address);
3247 %}
3249 enc_class movq_st(memory mem, regXD src) %{
3250 MacroAssembler _masm(&cbuf);
3251 __ movq($mem$$Address, $src$$XMMRegister);
3252 %}
3254 enc_class pshufd_8x8(regX dst, regX src) %{
3255 MacroAssembler _masm(&cbuf);
3257 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3258 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3259 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3260 %}
3262 enc_class pshufd_4x16(regX dst, regX src) %{
3263 MacroAssembler _masm(&cbuf);
3265 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3266 %}
3268 enc_class pshufd(regXD dst, regXD src, int mode) %{
3269 MacroAssembler _masm(&cbuf);
3271 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3272 %}
3274 enc_class pxor(regXD dst, regXD src) %{
3275 MacroAssembler _masm(&cbuf);
3277 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3278 %}
3280 enc_class mov_i2x(regXD dst, eRegI src) %{
3281 MacroAssembler _masm(&cbuf);
3283 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3284 %}
3287 // Because the transitions from emitted code to the runtime
3288 // monitorenter/exit helper stubs are so slow it's critical that
3289 // we inline both the stack-locking fast-path and the inflated fast path.
3290 //
3291 // See also: cmpFastLock and cmpFastUnlock.
3292 //
3293 // What follows is a specialized inline transliteration of the code
3294 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3295 // another option would be to emit TrySlowEnter and TrySlowExit methods
3296 // at startup-time. These methods would accept arguments as
3297 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3298 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3299 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3300 // In practice, however, the # of lock sites is bounded and is usually small.
3301 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3302 // if the processor uses simple bimodal branch predictors keyed by EIP
3303 // Since the helper routines would be called from multiple synchronization
3304 // sites.
3305 //
3306 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3307 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3308 // to those specialized methods. That'd give us a mostly platform-independent
3309 // implementation that the JITs could optimize and inline at their pleasure.
3310 // Done correctly, the only time we'd need to cross to native could would be
3311 // to park() or unpark() threads. We'd also need a few more unsafe operators
3312 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3313 // (b) explicit barriers or fence operations.
3314 //
3315 // TODO:
3316 //
3317 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3318 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3319 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3320 // the lock operators would typically be faster than reifying Self.
3321 //
3322 // * Ideally I'd define the primitives as:
3323 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3324 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3325 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3326 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3327 // Furthermore the register assignments are overconstrained, possibly resulting in
3328 // sub-optimal code near the synchronization site.
3329 //
3330 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3331 // Alternately, use a better sp-proximity test.
3332 //
3333 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3334 // Either one is sufficient to uniquely identify a thread.
3335 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3336 //
3337 // * Intrinsify notify() and notifyAll() for the common cases where the
3338 // object is locked by the calling thread but the waitlist is empty.
3339 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3340 //
3341 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3342 // But beware of excessive branch density on AMD Opterons.
3343 //
3344 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3345 // or failure of the fast-path. If the fast-path fails then we pass
3346 // control to the slow-path, typically in C. In Fast_Lock and
3347 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3348 // will emit a conditional branch immediately after the node.
3349 // So we have branches to branches and lots of ICC.ZF games.
3350 // Instead, it might be better to have C2 pass a "FailureLabel"
3351 // into Fast_Lock and Fast_Unlock. In the case of success, control
3352 // will drop through the node. ICC.ZF is undefined at exit.
3353 // In the case of failure, the node will branch directly to the
3354 // FailureLabel
3357 // obj: object to lock
3358 // box: on-stack box address (displaced header location) - KILLED
3359 // rax,: tmp -- KILLED
3360 // scr: tmp -- KILLED
3361 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3363 Register objReg = as_Register($obj$$reg);
3364 Register boxReg = as_Register($box$$reg);
3365 Register tmpReg = as_Register($tmp$$reg);
3366 Register scrReg = as_Register($scr$$reg);
3368 // Ensure the register assignents are disjoint
3369 guarantee (objReg != boxReg, "") ;
3370 guarantee (objReg != tmpReg, "") ;
3371 guarantee (objReg != scrReg, "") ;
3372 guarantee (boxReg != tmpReg, "") ;
3373 guarantee (boxReg != scrReg, "") ;
3374 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3376 MacroAssembler masm(&cbuf);
3378 if (_counters != NULL) {
3379 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3380 }
3381 if (EmitSync & 1) {
3382 // set box->dhw = unused_mark (3)
3383 // Force all sync thru slow-path: slow_enter() and slow_exit()
3384 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3385 masm.cmpptr (rsp, (int32_t)0) ;
3386 } else
3387 if (EmitSync & 2) {
3388 Label DONE_LABEL ;
3389 if (UseBiasedLocking) {
3390 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3391 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3392 }
3394 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3395 masm.orptr (tmpReg, 0x1);
3396 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3397 if (os::is_MP()) { masm.lock(); }
3398 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3399 masm.jcc(Assembler::equal, DONE_LABEL);
3400 // Recursive locking
3401 masm.subptr(tmpReg, rsp);
3402 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3403 masm.movptr(Address(boxReg, 0), tmpReg);
3404 masm.bind(DONE_LABEL) ;
3405 } else {
3406 // Possible cases that we'll encounter in fast_lock
3407 // ------------------------------------------------
3408 // * Inflated
3409 // -- unlocked
3410 // -- Locked
3411 // = by self
3412 // = by other
3413 // * biased
3414 // -- by Self
3415 // -- by other
3416 // * neutral
3417 // * stack-locked
3418 // -- by self
3419 // = sp-proximity test hits
3420 // = sp-proximity test generates false-negative
3421 // -- by other
3422 //
3424 Label IsInflated, DONE_LABEL, PopDone ;
3426 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3427 // order to reduce the number of conditional branches in the most common cases.
3428 // Beware -- there's a subtle invariant that fetch of the markword
3429 // at [FETCH], below, will never observe a biased encoding (*101b).
3430 // If this invariant is not held we risk exclusion (safety) failure.
3431 if (UseBiasedLocking && !UseOptoBiasInlining) {
3432 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3433 }
3435 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3436 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3437 masm.jccb (Assembler::notZero, IsInflated) ;
3439 // Attempt stack-locking ...
3440 masm.orptr (tmpReg, 0x1);
3441 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3442 if (os::is_MP()) { masm.lock(); }
3443 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3444 if (_counters != NULL) {
3445 masm.cond_inc32(Assembler::equal,
3446 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3447 }
3448 masm.jccb (Assembler::equal, DONE_LABEL);
3450 // Recursive locking
3451 masm.subptr(tmpReg, rsp);
3452 masm.andptr(tmpReg, 0xFFFFF003 );
3453 masm.movptr(Address(boxReg, 0), tmpReg);
3454 if (_counters != NULL) {
3455 masm.cond_inc32(Assembler::equal,
3456 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3457 }
3458 masm.jmp (DONE_LABEL) ;
3460 masm.bind (IsInflated) ;
3462 // The object is inflated.
3463 //
3464 // TODO-FIXME: eliminate the ugly use of manifest constants:
3465 // Use markOopDesc::monitor_value instead of "2".
3466 // use markOop::unused_mark() instead of "3".
3467 // The tmpReg value is an objectMonitor reference ORed with
3468 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3469 // objectmonitor pointer by masking off the "2" bit or we can just
3470 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3471 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3472 //
3473 // I use the latter as it avoids AGI stalls.
3474 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3475 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3476 //
3477 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3479 // boxReg refers to the on-stack BasicLock in the current frame.
3480 // We'd like to write:
3481 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3482 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3483 // additional latency as we have another ST in the store buffer that must drain.
3485 if (EmitSync & 8192) {
3486 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3487 masm.get_thread (scrReg) ;
3488 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3489 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3490 if (os::is_MP()) { masm.lock(); }
3491 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3492 } else
3493 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3494 masm.movptr(scrReg, boxReg) ;
3495 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3497 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3498 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3499 // prefetchw [eax + Offset(_owner)-2]
3500 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3501 }
3503 if ((EmitSync & 64) == 0) {
3504 // Optimistic form: consider XORL tmpReg,tmpReg
3505 masm.movptr(tmpReg, NULL_WORD) ;
3506 } else {
3507 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3508 // Test-And-CAS instead of CAS
3509 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3510 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3511 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3512 }
3514 // Appears unlocked - try to swing _owner from null to non-null.
3515 // Ideally, I'd manifest "Self" with get_thread and then attempt
3516 // to CAS the register containing Self into m->Owner.
3517 // But we don't have enough registers, so instead we can either try to CAS
3518 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3519 // we later store "Self" into m->Owner. Transiently storing a stack address
3520 // (rsp or the address of the box) into m->owner is harmless.
3521 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3522 if (os::is_MP()) { masm.lock(); }
3523 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3524 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3525 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3526 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3527 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3528 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3530 // If the CAS fails we can either retry or pass control to the slow-path.
3531 // We use the latter tactic.
3532 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3533 // If the CAS was successful ...
3534 // Self has acquired the lock
3535 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3536 // Intentional fall-through into DONE_LABEL ...
3537 } else {
3538 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3539 masm.movptr(boxReg, tmpReg) ;
3541 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3542 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3543 // prefetchw [eax + Offset(_owner)-2]
3544 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3545 }
3547 if ((EmitSync & 64) == 0) {
3548 // Optimistic form
3549 masm.xorptr (tmpReg, tmpReg) ;
3550 } else {
3551 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3552 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3553 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3554 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3555 }
3557 // Appears unlocked - try to swing _owner from null to non-null.
3558 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3559 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3560 masm.get_thread (scrReg) ;
3561 if (os::is_MP()) { masm.lock(); }
3562 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3564 // If the CAS fails we can either retry or pass control to the slow-path.
3565 // We use the latter tactic.
3566 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3567 // If the CAS was successful ...
3568 // Self has acquired the lock
3569 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3570 // Intentional fall-through into DONE_LABEL ...
3571 }
3573 // DONE_LABEL is a hot target - we'd really like to place it at the
3574 // start of cache line by padding with NOPs.
3575 // See the AMD and Intel software optimization manuals for the
3576 // most efficient "long" NOP encodings.
3577 // Unfortunately none of our alignment mechanisms suffice.
3578 masm.bind(DONE_LABEL);
3580 // Avoid branch-to-branch on AMD processors
3581 // This appears to be superstition.
3582 if (EmitSync & 32) masm.nop() ;
3585 // At DONE_LABEL the icc ZFlag is set as follows ...
3586 // Fast_Unlock uses the same protocol.
3587 // ZFlag == 1 -> Success
3588 // ZFlag == 0 -> Failure - force control through the slow-path
3589 }
3590 %}
3592 // obj: object to unlock
3593 // box: box address (displaced header location), killed. Must be EAX.
3594 // rbx,: killed tmp; cannot be obj nor box.
3595 //
3596 // Some commentary on balanced locking:
3597 //
3598 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3599 // Methods that don't have provably balanced locking are forced to run in the
3600 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3601 // The interpreter provides two properties:
3602 // I1: At return-time the interpreter automatically and quietly unlocks any
3603 // objects acquired the current activation (frame). Recall that the
3604 // interpreter maintains an on-stack list of locks currently held by
3605 // a frame.
3606 // I2: If a method attempts to unlock an object that is not held by the
3607 // the frame the interpreter throws IMSX.
3608 //
3609 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3610 // B() doesn't have provably balanced locking so it runs in the interpreter.
3611 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3612 // is still locked by A().
3613 //
3614 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3615 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3616 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3617 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3619 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3621 Register objReg = as_Register($obj$$reg);
3622 Register boxReg = as_Register($box$$reg);
3623 Register tmpReg = as_Register($tmp$$reg);
3625 guarantee (objReg != boxReg, "") ;
3626 guarantee (objReg != tmpReg, "") ;
3627 guarantee (boxReg != tmpReg, "") ;
3628 guarantee (boxReg == as_Register(EAX_enc), "") ;
3629 MacroAssembler masm(&cbuf);
3631 if (EmitSync & 4) {
3632 // Disable - inhibit all inlining. Force control through the slow-path
3633 masm.cmpptr (rsp, 0) ;
3634 } else
3635 if (EmitSync & 8) {
3636 Label DONE_LABEL ;
3637 if (UseBiasedLocking) {
3638 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3639 }
3640 // classic stack-locking code ...
3641 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3642 masm.testptr(tmpReg, tmpReg) ;
3643 masm.jcc (Assembler::zero, DONE_LABEL) ;
3644 if (os::is_MP()) { masm.lock(); }
3645 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3646 masm.bind(DONE_LABEL);
3647 } else {
3648 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3650 // Critically, the biased locking test must have precedence over
3651 // and appear before the (box->dhw == 0) recursive stack-lock test.
3652 if (UseBiasedLocking && !UseOptoBiasInlining) {
3653 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3654 }
3656 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3657 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3658 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3660 masm.testptr(tmpReg, 0x02) ; // Inflated?
3661 masm.jccb (Assembler::zero, Stacked) ;
3663 masm.bind (Inflated) ;
3664 // It's inflated.
3665 // Despite our balanced locking property we still check that m->_owner == Self
3666 // as java routines or native JNI code called by this thread might
3667 // have released the lock.
3668 // Refer to the comments in synchronizer.cpp for how we might encode extra
3669 // state in _succ so we can avoid fetching EntryList|cxq.
3670 //
3671 // I'd like to add more cases in fast_lock() and fast_unlock() --
3672 // such as recursive enter and exit -- but we have to be wary of
3673 // I$ bloat, T$ effects and BP$ effects.
3674 //
3675 // If there's no contention try a 1-0 exit. That is, exit without
3676 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3677 // we detect and recover from the race that the 1-0 exit admits.
3678 //
3679 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3680 // before it STs null into _owner, releasing the lock. Updates
3681 // to data protected by the critical section must be visible before
3682 // we drop the lock (and thus before any other thread could acquire
3683 // the lock and observe the fields protected by the lock).
3684 // IA32's memory-model is SPO, so STs are ordered with respect to
3685 // each other and there's no need for an explicit barrier (fence).
3686 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3688 masm.get_thread (boxReg) ;
3689 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3690 // prefetchw [ebx + Offset(_owner)-2]
3691 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3692 }
3694 // Note that we could employ various encoding schemes to reduce
3695 // the number of loads below (currently 4) to just 2 or 3.
3696 // Refer to the comments in synchronizer.cpp.
3697 // In practice the chain of fetches doesn't seem to impact performance, however.
3698 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3699 // Attempt to reduce branch density - AMD's branch predictor.
3700 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3701 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3702 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3703 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3704 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3705 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3706 masm.jmpb (DONE_LABEL) ;
3707 } else {
3708 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3709 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3710 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3711 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3712 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3713 masm.jccb (Assembler::notZero, CheckSucc) ;
3714 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3715 masm.jmpb (DONE_LABEL) ;
3716 }
3718 // The Following code fragment (EmitSync & 65536) improves the performance of
3719 // contended applications and contended synchronization microbenchmarks.
3720 // Unfortunately the emission of the code - even though not executed - causes regressions
3721 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3722 // with an equal number of never-executed NOPs results in the same regression.
3723 // We leave it off by default.
3725 if ((EmitSync & 65536) != 0) {
3726 Label LSuccess, LGoSlowPath ;
3728 masm.bind (CheckSucc) ;
3730 // Optional pre-test ... it's safe to elide this
3731 if ((EmitSync & 16) == 0) {
3732 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3733 masm.jccb (Assembler::zero, LGoSlowPath) ;
3734 }
3736 // We have a classic Dekker-style idiom:
3737 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3738 // There are a number of ways to implement the barrier:
3739 // (1) lock:andl &m->_owner, 0
3740 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3741 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3742 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3743 // (2) If supported, an explicit MFENCE is appealing.
3744 // In older IA32 processors MFENCE is slower than lock:add or xchg
3745 // particularly if the write-buffer is full as might be the case if
3746 // if stores closely precede the fence or fence-equivalent instruction.
3747 // In more modern implementations MFENCE appears faster, however.
3748 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3749 // The $lines underlying the top-of-stack should be in M-state.
3750 // The locked add instruction is serializing, of course.
3751 // (4) Use xchg, which is serializing
3752 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3753 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3754 // The integer condition codes will tell us if succ was 0.
3755 // Since _succ and _owner should reside in the same $line and
3756 // we just stored into _owner, it's likely that the $line
3757 // remains in M-state for the lock:orl.
3758 //
3759 // We currently use (3), although it's likely that switching to (2)
3760 // is correct for the future.
3762 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3763 if (os::is_MP()) {
3764 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3765 masm.mfence();
3766 } else {
3767 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3768 }
3769 }
3770 // Ratify _succ remains non-null
3771 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3772 masm.jccb (Assembler::notZero, LSuccess) ;
3774 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3775 if (os::is_MP()) { masm.lock(); }
3776 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3777 masm.jccb (Assembler::notEqual, LSuccess) ;
3778 // Since we're low on registers we installed rsp as a placeholding in _owner.
3779 // Now install Self over rsp. This is safe as we're transitioning from
3780 // non-null to non=null
3781 masm.get_thread (boxReg) ;
3782 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3783 // Intentional fall-through into LGoSlowPath ...
3785 masm.bind (LGoSlowPath) ;
3786 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3787 masm.jmpb (DONE_LABEL) ;
3789 masm.bind (LSuccess) ;
3790 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3791 masm.jmpb (DONE_LABEL) ;
3792 }
3794 masm.bind (Stacked) ;
3795 // It's not inflated and it's not recursively stack-locked and it's not biased.
3796 // It must be stack-locked.
3797 // Try to reset the header to displaced header.
3798 // The "box" value on the stack is stable, so we can reload
3799 // and be assured we observe the same value as above.
3800 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3801 if (os::is_MP()) { masm.lock(); }
3802 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3803 // Intention fall-thru into DONE_LABEL
3806 // DONE_LABEL is a hot target - we'd really like to place it at the
3807 // start of cache line by padding with NOPs.
3808 // See the AMD and Intel software optimization manuals for the
3809 // most efficient "long" NOP encodings.
3810 // Unfortunately none of our alignment mechanisms suffice.
3811 if ((EmitSync & 65536) == 0) {
3812 masm.bind (CheckSucc) ;
3813 }
3814 masm.bind(DONE_LABEL);
3816 // Avoid branch to branch on AMD processors
3817 if (EmitSync & 32768) { masm.nop() ; }
3818 }
3819 %}
3822 enc_class enc_pop_rdx() %{
3823 emit_opcode(cbuf,0x5A);
3824 %}
3826 enc_class enc_rethrow() %{
3827 cbuf.set_inst_mark();
3828 emit_opcode(cbuf, 0xE9); // jmp entry
3829 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3830 runtime_call_Relocation::spec(), RELOC_IMM32 );
3831 %}
3834 // Convert a double to an int. Java semantics require we do complex
3835 // manglelations in the corner cases. So we set the rounding mode to
3836 // 'zero', store the darned double down as an int, and reset the
3837 // rounding mode to 'nearest'. The hardware throws an exception which
3838 // patches up the correct value directly to the stack.
3839 enc_class D2I_encoding( regD src ) %{
3840 // Flip to round-to-zero mode. We attempted to allow invalid-op
3841 // exceptions here, so that a NAN or other corner-case value will
3842 // thrown an exception (but normal values get converted at full speed).
3843 // However, I2C adapters and other float-stack manglers leave pending
3844 // invalid-op exceptions hanging. We would have to clear them before
3845 // enabling them and that is more expensive than just testing for the
3846 // invalid value Intel stores down in the corner cases.
3847 emit_opcode(cbuf,0xD9); // FLDCW trunc
3848 emit_opcode(cbuf,0x2D);
3849 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3850 // Allocate a word
3851 emit_opcode(cbuf,0x83); // SUB ESP,4
3852 emit_opcode(cbuf,0xEC);
3853 emit_d8(cbuf,0x04);
3854 // Encoding assumes a double has been pushed into FPR0.
3855 // Store down the double as an int, popping the FPU stack
3856 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3857 emit_opcode(cbuf,0x1C);
3858 emit_d8(cbuf,0x24);
3859 // Restore the rounding mode; mask the exception
3860 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3861 emit_opcode(cbuf,0x2D);
3862 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3863 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3864 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3866 // Load the converted int; adjust CPU stack
3867 emit_opcode(cbuf,0x58); // POP EAX
3868 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3869 emit_d32 (cbuf,0x80000000); // 0x80000000
3870 emit_opcode(cbuf,0x75); // JNE around_slow_call
3871 emit_d8 (cbuf,0x07); // Size of slow_call
3872 // Push src onto stack slow-path
3873 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3874 emit_d8 (cbuf,0xC0-1+$src$$reg );
3875 // CALL directly to the runtime
3876 cbuf.set_inst_mark();
3877 emit_opcode(cbuf,0xE8); // Call into runtime
3878 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3879 // Carry on here...
3880 %}
3882 enc_class D2L_encoding( regD src ) %{
3883 emit_opcode(cbuf,0xD9); // FLDCW trunc
3884 emit_opcode(cbuf,0x2D);
3885 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3886 // Allocate a word
3887 emit_opcode(cbuf,0x83); // SUB ESP,8
3888 emit_opcode(cbuf,0xEC);
3889 emit_d8(cbuf,0x08);
3890 // Encoding assumes a double has been pushed into FPR0.
3891 // Store down the double as a long, popping the FPU stack
3892 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3893 emit_opcode(cbuf,0x3C);
3894 emit_d8(cbuf,0x24);
3895 // Restore the rounding mode; mask the exception
3896 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3897 emit_opcode(cbuf,0x2D);
3898 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3899 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3900 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3902 // Load the converted int; adjust CPU stack
3903 emit_opcode(cbuf,0x58); // POP EAX
3904 emit_opcode(cbuf,0x5A); // POP EDX
3905 emit_opcode(cbuf,0x81); // CMP EDX,imm
3906 emit_d8 (cbuf,0xFA); // rdx
3907 emit_d32 (cbuf,0x80000000); // 0x80000000
3908 emit_opcode(cbuf,0x75); // JNE around_slow_call
3909 emit_d8 (cbuf,0x07+4); // Size of slow_call
3910 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3911 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3912 emit_opcode(cbuf,0x75); // JNE around_slow_call
3913 emit_d8 (cbuf,0x07); // Size of slow_call
3914 // Push src onto stack slow-path
3915 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3916 emit_d8 (cbuf,0xC0-1+$src$$reg );
3917 // CALL directly to the runtime
3918 cbuf.set_inst_mark();
3919 emit_opcode(cbuf,0xE8); // Call into runtime
3920 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3921 // Carry on here...
3922 %}
3924 enc_class X2L_encoding( regX src ) %{
3925 // Allocate a word
3926 emit_opcode(cbuf,0x83); // SUB ESP,8
3927 emit_opcode(cbuf,0xEC);
3928 emit_d8(cbuf,0x08);
3930 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3931 emit_opcode (cbuf, 0x0F );
3932 emit_opcode (cbuf, 0x11 );
3933 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3935 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3936 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3938 emit_opcode(cbuf,0xD9); // FLDCW trunc
3939 emit_opcode(cbuf,0x2D);
3940 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3942 // Encoding assumes a double has been pushed into FPR0.
3943 // Store down the double as a long, popping the FPU stack
3944 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3945 emit_opcode(cbuf,0x3C);
3946 emit_d8(cbuf,0x24);
3948 // Restore the rounding mode; mask the exception
3949 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3950 emit_opcode(cbuf,0x2D);
3951 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3952 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3953 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3955 // Load the converted int; adjust CPU stack
3956 emit_opcode(cbuf,0x58); // POP EAX
3958 emit_opcode(cbuf,0x5A); // POP EDX
3960 emit_opcode(cbuf,0x81); // CMP EDX,imm
3961 emit_d8 (cbuf,0xFA); // rdx
3962 emit_d32 (cbuf,0x80000000);// 0x80000000
3964 emit_opcode(cbuf,0x75); // JNE around_slow_call
3965 emit_d8 (cbuf,0x13+4); // Size of slow_call
3967 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3968 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3970 emit_opcode(cbuf,0x75); // JNE around_slow_call
3971 emit_d8 (cbuf,0x13); // Size of slow_call
3973 // Allocate a word
3974 emit_opcode(cbuf,0x83); // SUB ESP,4
3975 emit_opcode(cbuf,0xEC);
3976 emit_d8(cbuf,0x04);
3978 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3979 emit_opcode (cbuf, 0x0F );
3980 emit_opcode (cbuf, 0x11 );
3981 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3983 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3984 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3986 emit_opcode(cbuf,0x83); // ADD ESP,4
3987 emit_opcode(cbuf,0xC4);
3988 emit_d8(cbuf,0x04);
3990 // CALL directly to the runtime
3991 cbuf.set_inst_mark();
3992 emit_opcode(cbuf,0xE8); // Call into runtime
3993 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3994 // Carry on here...
3995 %}
3997 enc_class XD2L_encoding( regXD src ) %{
3998 // Allocate a word
3999 emit_opcode(cbuf,0x83); // SUB ESP,8
4000 emit_opcode(cbuf,0xEC);
4001 emit_d8(cbuf,0x08);
4003 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4004 emit_opcode (cbuf, 0x0F );
4005 emit_opcode (cbuf, 0x11 );
4006 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4008 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4009 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4011 emit_opcode(cbuf,0xD9); // FLDCW trunc
4012 emit_opcode(cbuf,0x2D);
4013 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4015 // Encoding assumes a double has been pushed into FPR0.
4016 // Store down the double as a long, popping the FPU stack
4017 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4018 emit_opcode(cbuf,0x3C);
4019 emit_d8(cbuf,0x24);
4021 // Restore the rounding mode; mask the exception
4022 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4023 emit_opcode(cbuf,0x2D);
4024 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4025 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4026 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4028 // Load the converted int; adjust CPU stack
4029 emit_opcode(cbuf,0x58); // POP EAX
4031 emit_opcode(cbuf,0x5A); // POP EDX
4033 emit_opcode(cbuf,0x81); // CMP EDX,imm
4034 emit_d8 (cbuf,0xFA); // rdx
4035 emit_d32 (cbuf,0x80000000); // 0x80000000
4037 emit_opcode(cbuf,0x75); // JNE around_slow_call
4038 emit_d8 (cbuf,0x13+4); // Size of slow_call
4040 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4041 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4043 emit_opcode(cbuf,0x75); // JNE around_slow_call
4044 emit_d8 (cbuf,0x13); // Size of slow_call
4046 // Push src onto stack slow-path
4047 // Allocate a word
4048 emit_opcode(cbuf,0x83); // SUB ESP,8
4049 emit_opcode(cbuf,0xEC);
4050 emit_d8(cbuf,0x08);
4052 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4053 emit_opcode (cbuf, 0x0F );
4054 emit_opcode (cbuf, 0x11 );
4055 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4057 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4058 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4060 emit_opcode(cbuf,0x83); // ADD ESP,8
4061 emit_opcode(cbuf,0xC4);
4062 emit_d8(cbuf,0x08);
4064 // CALL directly to the runtime
4065 cbuf.set_inst_mark();
4066 emit_opcode(cbuf,0xE8); // Call into runtime
4067 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4068 // Carry on here...
4069 %}
4071 enc_class D2X_encoding( regX dst, regD src ) %{
4072 // Allocate a word
4073 emit_opcode(cbuf,0x83); // SUB ESP,4
4074 emit_opcode(cbuf,0xEC);
4075 emit_d8(cbuf,0x04);
4076 int pop = 0x02;
4077 if ($src$$reg != FPR1L_enc) {
4078 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4079 emit_d8( cbuf, 0xC0-1+$src$$reg );
4080 pop = 0x03;
4081 }
4082 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4084 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4085 emit_opcode (cbuf, 0x0F );
4086 emit_opcode (cbuf, 0x10 );
4087 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4089 emit_opcode(cbuf,0x83); // ADD ESP,4
4090 emit_opcode(cbuf,0xC4);
4091 emit_d8(cbuf,0x04);
4092 // Carry on here...
4093 %}
4095 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4096 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4098 // Compare the result to see if we need to go to the slow path
4099 emit_opcode(cbuf,0x81); // CMP dst,imm
4100 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4101 emit_d32 (cbuf,0x80000000); // 0x80000000
4103 emit_opcode(cbuf,0x75); // JNE around_slow_call
4104 emit_d8 (cbuf,0x13); // Size of slow_call
4105 // Store xmm to a temp memory
4106 // location and push it onto stack.
4108 emit_opcode(cbuf,0x83); // SUB ESP,4
4109 emit_opcode(cbuf,0xEC);
4110 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4112 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4113 emit_opcode (cbuf, 0x0F );
4114 emit_opcode (cbuf, 0x11 );
4115 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4117 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4118 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4120 emit_opcode(cbuf,0x83); // ADD ESP,4
4121 emit_opcode(cbuf,0xC4);
4122 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4124 // CALL directly to the runtime
4125 cbuf.set_inst_mark();
4126 emit_opcode(cbuf,0xE8); // Call into runtime
4127 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4129 // Carry on here...
4130 %}
4132 enc_class X2D_encoding( regD dst, regX src ) %{
4133 // Allocate a word
4134 emit_opcode(cbuf,0x83); // SUB ESP,4
4135 emit_opcode(cbuf,0xEC);
4136 emit_d8(cbuf,0x04);
4138 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4139 emit_opcode (cbuf, 0x0F );
4140 emit_opcode (cbuf, 0x11 );
4141 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4143 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4144 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4146 emit_opcode(cbuf,0x83); // ADD ESP,4
4147 emit_opcode(cbuf,0xC4);
4148 emit_d8(cbuf,0x04);
4150 // Carry on here...
4151 %}
4153 enc_class AbsXF_encoding(regX dst) %{
4154 address signmask_address=(address)float_signmask_pool;
4155 // andpd:\tANDPS $dst,[signconst]
4156 emit_opcode(cbuf, 0x0F);
4157 emit_opcode(cbuf, 0x54);
4158 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4159 emit_d32(cbuf, (int)signmask_address);
4160 %}
4162 enc_class AbsXD_encoding(regXD dst) %{
4163 address signmask_address=(address)double_signmask_pool;
4164 // andpd:\tANDPD $dst,[signconst]
4165 emit_opcode(cbuf, 0x66);
4166 emit_opcode(cbuf, 0x0F);
4167 emit_opcode(cbuf, 0x54);
4168 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4169 emit_d32(cbuf, (int)signmask_address);
4170 %}
4172 enc_class NegXF_encoding(regX dst) %{
4173 address signmask_address=(address)float_signflip_pool;
4174 // andpd:\tXORPS $dst,[signconst]
4175 emit_opcode(cbuf, 0x0F);
4176 emit_opcode(cbuf, 0x57);
4177 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4178 emit_d32(cbuf, (int)signmask_address);
4179 %}
4181 enc_class NegXD_encoding(regXD dst) %{
4182 address signmask_address=(address)double_signflip_pool;
4183 // andpd:\tXORPD $dst,[signconst]
4184 emit_opcode(cbuf, 0x66);
4185 emit_opcode(cbuf, 0x0F);
4186 emit_opcode(cbuf, 0x57);
4187 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4188 emit_d32(cbuf, (int)signmask_address);
4189 %}
4191 enc_class FMul_ST_reg( eRegF src1 ) %{
4192 // Operand was loaded from memory into fp ST (stack top)
4193 // FMUL ST,$src /* D8 C8+i */
4194 emit_opcode(cbuf, 0xD8);
4195 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4196 %}
4198 enc_class FAdd_ST_reg( eRegF src2 ) %{
4199 // FADDP ST,src2 /* D8 C0+i */
4200 emit_opcode(cbuf, 0xD8);
4201 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4202 //could use FADDP src2,fpST /* DE C0+i */
4203 %}
4205 enc_class FAddP_reg_ST( eRegF src2 ) %{
4206 // FADDP src2,ST /* DE C0+i */
4207 emit_opcode(cbuf, 0xDE);
4208 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4209 %}
4211 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4212 // Operand has been loaded into fp ST (stack top)
4213 // FSUB ST,$src1
4214 emit_opcode(cbuf, 0xD8);
4215 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4217 // FDIV
4218 emit_opcode(cbuf, 0xD8);
4219 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4220 %}
4222 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4223 // Operand was loaded from memory into fp ST (stack top)
4224 // FADD ST,$src /* D8 C0+i */
4225 emit_opcode(cbuf, 0xD8);
4226 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4228 // FMUL ST,src2 /* D8 C*+i */
4229 emit_opcode(cbuf, 0xD8);
4230 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4231 %}
4234 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4235 // Operand was loaded from memory into fp ST (stack top)
4236 // FADD ST,$src /* D8 C0+i */
4237 emit_opcode(cbuf, 0xD8);
4238 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4240 // FMULP src2,ST /* DE C8+i */
4241 emit_opcode(cbuf, 0xDE);
4242 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4243 %}
4245 // Atomically load the volatile long
4246 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4247 emit_opcode(cbuf,0xDF);
4248 int rm_byte_opcode = 0x05;
4249 int base = $mem$$base;
4250 int index = $mem$$index;
4251 int scale = $mem$$scale;
4252 int displace = $mem$$disp;
4253 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4255 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4256 %}
4258 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4259 { // Atomic long load
4260 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4261 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4262 emit_opcode(cbuf,0x0F);
4263 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4264 int base = $mem$$base;
4265 int index = $mem$$index;
4266 int scale = $mem$$scale;
4267 int displace = $mem$$disp;
4268 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4269 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4270 }
4271 { // MOVSD $dst,$tmp ! atomic long store
4272 emit_opcode(cbuf,0xF2);
4273 emit_opcode(cbuf,0x0F);
4274 emit_opcode(cbuf,0x11);
4275 int base = $dst$$base;
4276 int index = $dst$$index;
4277 int scale = $dst$$scale;
4278 int displace = $dst$$disp;
4279 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4280 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4281 }
4282 %}
4284 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4285 { // Atomic long load
4286 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4287 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4288 emit_opcode(cbuf,0x0F);
4289 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4290 int base = $mem$$base;
4291 int index = $mem$$index;
4292 int scale = $mem$$scale;
4293 int displace = $mem$$disp;
4294 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4295 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4296 }
4297 { // MOVD $dst.lo,$tmp
4298 emit_opcode(cbuf,0x66);
4299 emit_opcode(cbuf,0x0F);
4300 emit_opcode(cbuf,0x7E);
4301 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4302 }
4303 { // PSRLQ $tmp,32
4304 emit_opcode(cbuf,0x66);
4305 emit_opcode(cbuf,0x0F);
4306 emit_opcode(cbuf,0x73);
4307 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4308 emit_d8(cbuf, 0x20);
4309 }
4310 { // MOVD $dst.hi,$tmp
4311 emit_opcode(cbuf,0x66);
4312 emit_opcode(cbuf,0x0F);
4313 emit_opcode(cbuf,0x7E);
4314 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4315 }
4316 %}
4318 // Volatile Store Long. Must be atomic, so move it into
4319 // the FP TOS and then do a 64-bit FIST. Has to probe the
4320 // target address before the store (for null-ptr checks)
4321 // so the memory operand is used twice in the encoding.
4322 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4323 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4324 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4325 emit_opcode(cbuf,0xDF);
4326 int rm_byte_opcode = 0x07;
4327 int base = $mem$$base;
4328 int index = $mem$$index;
4329 int scale = $mem$$scale;
4330 int displace = $mem$$disp;
4331 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4332 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4333 %}
4335 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4336 { // Atomic long load
4337 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4338 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4339 emit_opcode(cbuf,0x0F);
4340 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4341 int base = $src$$base;
4342 int index = $src$$index;
4343 int scale = $src$$scale;
4344 int displace = $src$$disp;
4345 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4346 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4347 }
4348 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4349 { // MOVSD $mem,$tmp ! atomic long store
4350 emit_opcode(cbuf,0xF2);
4351 emit_opcode(cbuf,0x0F);
4352 emit_opcode(cbuf,0x11);
4353 int base = $mem$$base;
4354 int index = $mem$$index;
4355 int scale = $mem$$scale;
4356 int displace = $mem$$disp;
4357 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4358 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4359 }
4360 %}
4362 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4363 { // MOVD $tmp,$src.lo
4364 emit_opcode(cbuf,0x66);
4365 emit_opcode(cbuf,0x0F);
4366 emit_opcode(cbuf,0x6E);
4367 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4368 }
4369 { // MOVD $tmp2,$src.hi
4370 emit_opcode(cbuf,0x66);
4371 emit_opcode(cbuf,0x0F);
4372 emit_opcode(cbuf,0x6E);
4373 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4374 }
4375 { // PUNPCKLDQ $tmp,$tmp2
4376 emit_opcode(cbuf,0x66);
4377 emit_opcode(cbuf,0x0F);
4378 emit_opcode(cbuf,0x62);
4379 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4380 }
4381 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4382 { // MOVSD $mem,$tmp ! atomic long store
4383 emit_opcode(cbuf,0xF2);
4384 emit_opcode(cbuf,0x0F);
4385 emit_opcode(cbuf,0x11);
4386 int base = $mem$$base;
4387 int index = $mem$$index;
4388 int scale = $mem$$scale;
4389 int displace = $mem$$disp;
4390 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4391 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4392 }
4393 %}
4395 // Safepoint Poll. This polls the safepoint page, and causes an
4396 // exception if it is not readable. Unfortunately, it kills the condition code
4397 // in the process
4398 // We current use TESTL [spp],EDI
4399 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4401 enc_class Safepoint_Poll() %{
4402 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4403 emit_opcode(cbuf,0x85);
4404 emit_rm (cbuf, 0x0, 0x7, 0x5);
4405 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4406 %}
4407 %}
4410 //----------FRAME--------------------------------------------------------------
4411 // Definition of frame structure and management information.
4412 //
4413 // S T A C K L A Y O U T Allocators stack-slot number
4414 // | (to get allocators register number
4415 // G Owned by | | v add OptoReg::stack0())
4416 // r CALLER | |
4417 // o | +--------+ pad to even-align allocators stack-slot
4418 // w V | pad0 | numbers; owned by CALLER
4419 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4420 // h ^ | in | 5
4421 // | | args | 4 Holes in incoming args owned by SELF
4422 // | | | | 3
4423 // | | +--------+
4424 // V | | old out| Empty on Intel, window on Sparc
4425 // | old |preserve| Must be even aligned.
4426 // | SP-+--------+----> Matcher::_old_SP, even aligned
4427 // | | in | 3 area for Intel ret address
4428 // Owned by |preserve| Empty on Sparc.
4429 // SELF +--------+
4430 // | | pad2 | 2 pad to align old SP
4431 // | +--------+ 1
4432 // | | locks | 0
4433 // | +--------+----> OptoReg::stack0(), even aligned
4434 // | | pad1 | 11 pad to align new SP
4435 // | +--------+
4436 // | | | 10
4437 // | | spills | 9 spills
4438 // V | | 8 (pad0 slot for callee)
4439 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4440 // ^ | out | 7
4441 // | | args | 6 Holes in outgoing args owned by CALLEE
4442 // Owned by +--------+
4443 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4444 // | new |preserve| Must be even-aligned.
4445 // | SP-+--------+----> Matcher::_new_SP, even aligned
4446 // | | |
4447 //
4448 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4449 // known from SELF's arguments and the Java calling convention.
4450 // Region 6-7 is determined per call site.
4451 // Note 2: If the calling convention leaves holes in the incoming argument
4452 // area, those holes are owned by SELF. Holes in the outgoing area
4453 // are owned by the CALLEE. Holes should not be nessecary in the
4454 // incoming area, as the Java calling convention is completely under
4455 // the control of the AD file. Doubles can be sorted and packed to
4456 // avoid holes. Holes in the outgoing arguments may be nessecary for
4457 // varargs C calling conventions.
4458 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4459 // even aligned with pad0 as needed.
4460 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4461 // region 6-11 is even aligned; it may be padded out more so that
4462 // the region from SP to FP meets the minimum stack alignment.
4464 frame %{
4465 // What direction does stack grow in (assumed to be same for C & Java)
4466 stack_direction(TOWARDS_LOW);
4468 // These three registers define part of the calling convention
4469 // between compiled code and the interpreter.
4470 inline_cache_reg(EAX); // Inline Cache Register
4471 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4473 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4474 cisc_spilling_operand_name(indOffset32);
4476 // Number of stack slots consumed by locking an object
4477 sync_stack_slots(1);
4479 // Compiled code's Frame Pointer
4480 frame_pointer(ESP);
4481 // Interpreter stores its frame pointer in a register which is
4482 // stored to the stack by I2CAdaptors.
4483 // I2CAdaptors convert from interpreted java to compiled java.
4484 interpreter_frame_pointer(EBP);
4486 // Stack alignment requirement
4487 // Alignment size in bytes (128-bit -> 16 bytes)
4488 stack_alignment(StackAlignmentInBytes);
4490 // Number of stack slots between incoming argument block and the start of
4491 // a new frame. The PROLOG must add this many slots to the stack. The
4492 // EPILOG must remove this many slots. Intel needs one slot for
4493 // return address and one for rbp, (must save rbp)
4494 in_preserve_stack_slots(2+VerifyStackAtCalls);
4496 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4497 // for calls to C. Supports the var-args backing area for register parms.
4498 varargs_C_out_slots_killed(0);
4500 // The after-PROLOG location of the return address. Location of
4501 // return address specifies a type (REG or STACK) and a number
4502 // representing the register number (i.e. - use a register name) or
4503 // stack slot.
4504 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4505 // Otherwise, it is above the locks and verification slot and alignment word
4506 return_addr(STACK - 1 +
4507 round_to(1+VerifyStackAtCalls+
4508 Compile::current()->fixed_slots(),
4509 (StackAlignmentInBytes/wordSize)));
4511 // Body of function which returns an integer array locating
4512 // arguments either in registers or in stack slots. Passed an array
4513 // of ideal registers called "sig" and a "length" count. Stack-slot
4514 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4515 // arguments for a CALLEE. Incoming stack arguments are
4516 // automatically biased by the preserve_stack_slots field above.
4517 calling_convention %{
4518 // No difference between ingoing/outgoing just pass false
4519 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4520 %}
4523 // Body of function which returns an integer array locating
4524 // arguments either in registers or in stack slots. Passed an array
4525 // of ideal registers called "sig" and a "length" count. Stack-slot
4526 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4527 // arguments for a CALLEE. Incoming stack arguments are
4528 // automatically biased by the preserve_stack_slots field above.
4529 c_calling_convention %{
4530 // This is obviously always outgoing
4531 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4532 %}
4534 // Location of C & interpreter return values
4535 c_return_value %{
4536 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4537 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4538 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4540 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4541 // that C functions return float and double results in XMM0.
4542 if( ideal_reg == Op_RegD && UseSSE>=2 )
4543 return OptoRegPair(XMM0b_num,XMM0a_num);
4544 if( ideal_reg == Op_RegF && UseSSE>=2 )
4545 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4547 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4548 %}
4550 // Location of return values
4551 return_value %{
4552 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4553 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4554 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4555 if( ideal_reg == Op_RegD && UseSSE>=2 )
4556 return OptoRegPair(XMM0b_num,XMM0a_num);
4557 if( ideal_reg == Op_RegF && UseSSE>=1 )
4558 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4559 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4560 %}
4562 %}
4564 //----------ATTRIBUTES---------------------------------------------------------
4565 //----------Operand Attributes-------------------------------------------------
4566 op_attrib op_cost(0); // Required cost attribute
4568 //----------Instruction Attributes---------------------------------------------
4569 ins_attrib ins_cost(100); // Required cost attribute
4570 ins_attrib ins_size(8); // Required size attribute (in bits)
4571 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4572 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4573 // non-matching short branch variant of some
4574 // long branch?
4575 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4576 // specifies the alignment that some part of the instruction (not
4577 // necessarily the start) requires. If > 1, a compute_padding()
4578 // function must be provided for the instruction
4580 //----------OPERANDS-----------------------------------------------------------
4581 // Operand definitions must precede instruction definitions for correct parsing
4582 // in the ADLC because operands constitute user defined types which are used in
4583 // instruction definitions.
4585 //----------Simple Operands----------------------------------------------------
4586 // Immediate Operands
4587 // Integer Immediate
4588 operand immI() %{
4589 match(ConI);
4591 op_cost(10);
4592 format %{ %}
4593 interface(CONST_INTER);
4594 %}
4596 // Constant for test vs zero
4597 operand immI0() %{
4598 predicate(n->get_int() == 0);
4599 match(ConI);
4601 op_cost(0);
4602 format %{ %}
4603 interface(CONST_INTER);
4604 %}
4606 // Constant for increment
4607 operand immI1() %{
4608 predicate(n->get_int() == 1);
4609 match(ConI);
4611 op_cost(0);
4612 format %{ %}
4613 interface(CONST_INTER);
4614 %}
4616 // Constant for decrement
4617 operand immI_M1() %{
4618 predicate(n->get_int() == -1);
4619 match(ConI);
4621 op_cost(0);
4622 format %{ %}
4623 interface(CONST_INTER);
4624 %}
4626 // Valid scale values for addressing modes
4627 operand immI2() %{
4628 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4629 match(ConI);
4631 format %{ %}
4632 interface(CONST_INTER);
4633 %}
4635 operand immI8() %{
4636 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4637 match(ConI);
4639 op_cost(5);
4640 format %{ %}
4641 interface(CONST_INTER);
4642 %}
4644 operand immI16() %{
4645 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4646 match(ConI);
4648 op_cost(10);
4649 format %{ %}
4650 interface(CONST_INTER);
4651 %}
4653 // Constant for long shifts
4654 operand immI_32() %{
4655 predicate( n->get_int() == 32 );
4656 match(ConI);
4658 op_cost(0);
4659 format %{ %}
4660 interface(CONST_INTER);
4661 %}
4663 operand immI_1_31() %{
4664 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4665 match(ConI);
4667 op_cost(0);
4668 format %{ %}
4669 interface(CONST_INTER);
4670 %}
4672 operand immI_32_63() %{
4673 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4674 match(ConI);
4675 op_cost(0);
4677 format %{ %}
4678 interface(CONST_INTER);
4679 %}
4681 operand immI_1() %{
4682 predicate( n->get_int() == 1 );
4683 match(ConI);
4685 op_cost(0);
4686 format %{ %}
4687 interface(CONST_INTER);
4688 %}
4690 operand immI_2() %{
4691 predicate( n->get_int() == 2 );
4692 match(ConI);
4694 op_cost(0);
4695 format %{ %}
4696 interface(CONST_INTER);
4697 %}
4699 operand immI_3() %{
4700 predicate( n->get_int() == 3 );
4701 match(ConI);
4703 op_cost(0);
4704 format %{ %}
4705 interface(CONST_INTER);
4706 %}
4708 // Pointer Immediate
4709 operand immP() %{
4710 match(ConP);
4712 op_cost(10);
4713 format %{ %}
4714 interface(CONST_INTER);
4715 %}
4717 // NULL Pointer Immediate
4718 operand immP0() %{
4719 predicate( n->get_ptr() == 0 );
4720 match(ConP);
4721 op_cost(0);
4723 format %{ %}
4724 interface(CONST_INTER);
4725 %}
4727 // Long Immediate
4728 operand immL() %{
4729 match(ConL);
4731 op_cost(20);
4732 format %{ %}
4733 interface(CONST_INTER);
4734 %}
4736 // Long Immediate zero
4737 operand immL0() %{
4738 predicate( n->get_long() == 0L );
4739 match(ConL);
4740 op_cost(0);
4742 format %{ %}
4743 interface(CONST_INTER);
4744 %}
4746 // Long Immediate zero
4747 operand immL_M1() %{
4748 predicate( n->get_long() == -1L );
4749 match(ConL);
4750 op_cost(0);
4752 format %{ %}
4753 interface(CONST_INTER);
4754 %}
4756 // Long immediate from 0 to 127.
4757 // Used for a shorter form of long mul by 10.
4758 operand immL_127() %{
4759 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4760 match(ConL);
4761 op_cost(0);
4763 format %{ %}
4764 interface(CONST_INTER);
4765 %}
4767 // Long Immediate: low 32-bit mask
4768 operand immL_32bits() %{
4769 predicate(n->get_long() == 0xFFFFFFFFL);
4770 match(ConL);
4771 op_cost(0);
4773 format %{ %}
4774 interface(CONST_INTER);
4775 %}
4777 // Long Immediate: low 32-bit mask
4778 operand immL32() %{
4779 predicate(n->get_long() == (int)(n->get_long()));
4780 match(ConL);
4781 op_cost(20);
4783 format %{ %}
4784 interface(CONST_INTER);
4785 %}
4787 //Double Immediate zero
4788 operand immD0() %{
4789 // Do additional (and counter-intuitive) test against NaN to work around VC++
4790 // bug that generates code such that NaNs compare equal to 0.0
4791 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4792 match(ConD);
4794 op_cost(5);
4795 format %{ %}
4796 interface(CONST_INTER);
4797 %}
4799 // Double Immediate
4800 operand immD1() %{
4801 predicate( UseSSE<=1 && n->getd() == 1.0 );
4802 match(ConD);
4804 op_cost(5);
4805 format %{ %}
4806 interface(CONST_INTER);
4807 %}
4809 // Double Immediate
4810 operand immD() %{
4811 predicate(UseSSE<=1);
4812 match(ConD);
4814 op_cost(5);
4815 format %{ %}
4816 interface(CONST_INTER);
4817 %}
4819 operand immXD() %{
4820 predicate(UseSSE>=2);
4821 match(ConD);
4823 op_cost(5);
4824 format %{ %}
4825 interface(CONST_INTER);
4826 %}
4828 // Double Immediate zero
4829 operand immXD0() %{
4830 // Do additional (and counter-intuitive) test against NaN to work around VC++
4831 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4832 // compare equal to -0.0.
4833 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4834 match(ConD);
4836 format %{ %}
4837 interface(CONST_INTER);
4838 %}
4840 // Float Immediate zero
4841 operand immF0() %{
4842 predicate( UseSSE == 0 && n->getf() == 0.0 );
4843 match(ConF);
4845 op_cost(5);
4846 format %{ %}
4847 interface(CONST_INTER);
4848 %}
4850 // Float Immediate
4851 operand immF() %{
4852 predicate( UseSSE == 0 );
4853 match(ConF);
4855 op_cost(5);
4856 format %{ %}
4857 interface(CONST_INTER);
4858 %}
4860 // Float Immediate
4861 operand immXF() %{
4862 predicate(UseSSE >= 1);
4863 match(ConF);
4865 op_cost(5);
4866 format %{ %}
4867 interface(CONST_INTER);
4868 %}
4870 // Float Immediate zero. Zero and not -0.0
4871 operand immXF0() %{
4872 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4873 match(ConF);
4875 op_cost(5);
4876 format %{ %}
4877 interface(CONST_INTER);
4878 %}
4880 // Immediates for special shifts (sign extend)
4882 // Constants for increment
4883 operand immI_16() %{
4884 predicate( n->get_int() == 16 );
4885 match(ConI);
4887 format %{ %}
4888 interface(CONST_INTER);
4889 %}
4891 operand immI_24() %{
4892 predicate( n->get_int() == 24 );
4893 match(ConI);
4895 format %{ %}
4896 interface(CONST_INTER);
4897 %}
4899 // Constant for byte-wide masking
4900 operand immI_255() %{
4901 predicate( n->get_int() == 255 );
4902 match(ConI);
4904 format %{ %}
4905 interface(CONST_INTER);
4906 %}
4908 // Constant for short-wide masking
4909 operand immI_65535() %{
4910 predicate(n->get_int() == 65535);
4911 match(ConI);
4913 format %{ %}
4914 interface(CONST_INTER);
4915 %}
4917 // Register Operands
4918 // Integer Register
4919 operand eRegI() %{
4920 constraint(ALLOC_IN_RC(e_reg));
4921 match(RegI);
4922 match(xRegI);
4923 match(eAXRegI);
4924 match(eBXRegI);
4925 match(eCXRegI);
4926 match(eDXRegI);
4927 match(eDIRegI);
4928 match(eSIRegI);
4930 format %{ %}
4931 interface(REG_INTER);
4932 %}
4934 // Subset of Integer Register
4935 operand xRegI(eRegI reg) %{
4936 constraint(ALLOC_IN_RC(x_reg));
4937 match(reg);
4938 match(eAXRegI);
4939 match(eBXRegI);
4940 match(eCXRegI);
4941 match(eDXRegI);
4943 format %{ %}
4944 interface(REG_INTER);
4945 %}
4947 // Special Registers
4948 operand eAXRegI(xRegI reg) %{
4949 constraint(ALLOC_IN_RC(eax_reg));
4950 match(reg);
4951 match(eRegI);
4953 format %{ "EAX" %}
4954 interface(REG_INTER);
4955 %}
4957 // Special Registers
4958 operand eBXRegI(xRegI reg) %{
4959 constraint(ALLOC_IN_RC(ebx_reg));
4960 match(reg);
4961 match(eRegI);
4963 format %{ "EBX" %}
4964 interface(REG_INTER);
4965 %}
4967 operand eCXRegI(xRegI reg) %{
4968 constraint(ALLOC_IN_RC(ecx_reg));
4969 match(reg);
4970 match(eRegI);
4972 format %{ "ECX" %}
4973 interface(REG_INTER);
4974 %}
4976 operand eDXRegI(xRegI reg) %{
4977 constraint(ALLOC_IN_RC(edx_reg));
4978 match(reg);
4979 match(eRegI);
4981 format %{ "EDX" %}
4982 interface(REG_INTER);
4983 %}
4985 operand eDIRegI(xRegI reg) %{
4986 constraint(ALLOC_IN_RC(edi_reg));
4987 match(reg);
4988 match(eRegI);
4990 format %{ "EDI" %}
4991 interface(REG_INTER);
4992 %}
4994 operand naxRegI() %{
4995 constraint(ALLOC_IN_RC(nax_reg));
4996 match(RegI);
4997 match(eCXRegI);
4998 match(eDXRegI);
4999 match(eSIRegI);
5000 match(eDIRegI);
5002 format %{ %}
5003 interface(REG_INTER);
5004 %}
5006 operand nadxRegI() %{
5007 constraint(ALLOC_IN_RC(nadx_reg));
5008 match(RegI);
5009 match(eBXRegI);
5010 match(eCXRegI);
5011 match(eSIRegI);
5012 match(eDIRegI);
5014 format %{ %}
5015 interface(REG_INTER);
5016 %}
5018 operand ncxRegI() %{
5019 constraint(ALLOC_IN_RC(ncx_reg));
5020 match(RegI);
5021 match(eAXRegI);
5022 match(eDXRegI);
5023 match(eSIRegI);
5024 match(eDIRegI);
5026 format %{ %}
5027 interface(REG_INTER);
5028 %}
5030 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5031 // //
5032 operand eSIRegI(xRegI reg) %{
5033 constraint(ALLOC_IN_RC(esi_reg));
5034 match(reg);
5035 match(eRegI);
5037 format %{ "ESI" %}
5038 interface(REG_INTER);
5039 %}
5041 // Pointer Register
5042 operand anyRegP() %{
5043 constraint(ALLOC_IN_RC(any_reg));
5044 match(RegP);
5045 match(eAXRegP);
5046 match(eBXRegP);
5047 match(eCXRegP);
5048 match(eDIRegP);
5049 match(eRegP);
5051 format %{ %}
5052 interface(REG_INTER);
5053 %}
5055 operand eRegP() %{
5056 constraint(ALLOC_IN_RC(e_reg));
5057 match(RegP);
5058 match(eAXRegP);
5059 match(eBXRegP);
5060 match(eCXRegP);
5061 match(eDIRegP);
5063 format %{ %}
5064 interface(REG_INTER);
5065 %}
5067 // On windows95, EBP is not safe to use for implicit null tests.
5068 operand eRegP_no_EBP() %{
5069 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5070 match(RegP);
5071 match(eAXRegP);
5072 match(eBXRegP);
5073 match(eCXRegP);
5074 match(eDIRegP);
5076 op_cost(100);
5077 format %{ %}
5078 interface(REG_INTER);
5079 %}
5081 operand naxRegP() %{
5082 constraint(ALLOC_IN_RC(nax_reg));
5083 match(RegP);
5084 match(eBXRegP);
5085 match(eDXRegP);
5086 match(eCXRegP);
5087 match(eSIRegP);
5088 match(eDIRegP);
5090 format %{ %}
5091 interface(REG_INTER);
5092 %}
5094 operand nabxRegP() %{
5095 constraint(ALLOC_IN_RC(nabx_reg));
5096 match(RegP);
5097 match(eCXRegP);
5098 match(eDXRegP);
5099 match(eSIRegP);
5100 match(eDIRegP);
5102 format %{ %}
5103 interface(REG_INTER);
5104 %}
5106 operand pRegP() %{
5107 constraint(ALLOC_IN_RC(p_reg));
5108 match(RegP);
5109 match(eBXRegP);
5110 match(eDXRegP);
5111 match(eSIRegP);
5112 match(eDIRegP);
5114 format %{ %}
5115 interface(REG_INTER);
5116 %}
5118 // Special Registers
5119 // Return a pointer value
5120 operand eAXRegP(eRegP reg) %{
5121 constraint(ALLOC_IN_RC(eax_reg));
5122 match(reg);
5123 format %{ "EAX" %}
5124 interface(REG_INTER);
5125 %}
5127 // Used in AtomicAdd
5128 operand eBXRegP(eRegP reg) %{
5129 constraint(ALLOC_IN_RC(ebx_reg));
5130 match(reg);
5131 format %{ "EBX" %}
5132 interface(REG_INTER);
5133 %}
5135 // Tail-call (interprocedural jump) to interpreter
5136 operand eCXRegP(eRegP reg) %{
5137 constraint(ALLOC_IN_RC(ecx_reg));
5138 match(reg);
5139 format %{ "ECX" %}
5140 interface(REG_INTER);
5141 %}
5143 operand eSIRegP(eRegP reg) %{
5144 constraint(ALLOC_IN_RC(esi_reg));
5145 match(reg);
5146 format %{ "ESI" %}
5147 interface(REG_INTER);
5148 %}
5150 // Used in rep stosw
5151 operand eDIRegP(eRegP reg) %{
5152 constraint(ALLOC_IN_RC(edi_reg));
5153 match(reg);
5154 format %{ "EDI" %}
5155 interface(REG_INTER);
5156 %}
5158 operand eBPRegP() %{
5159 constraint(ALLOC_IN_RC(ebp_reg));
5160 match(RegP);
5161 format %{ "EBP" %}
5162 interface(REG_INTER);
5163 %}
5165 operand eRegL() %{
5166 constraint(ALLOC_IN_RC(long_reg));
5167 match(RegL);
5168 match(eADXRegL);
5170 format %{ %}
5171 interface(REG_INTER);
5172 %}
5174 operand eADXRegL( eRegL reg ) %{
5175 constraint(ALLOC_IN_RC(eadx_reg));
5176 match(reg);
5178 format %{ "EDX:EAX" %}
5179 interface(REG_INTER);
5180 %}
5182 operand eBCXRegL( eRegL reg ) %{
5183 constraint(ALLOC_IN_RC(ebcx_reg));
5184 match(reg);
5186 format %{ "EBX:ECX" %}
5187 interface(REG_INTER);
5188 %}
5190 // Special case for integer high multiply
5191 operand eADXRegL_low_only() %{
5192 constraint(ALLOC_IN_RC(eadx_reg));
5193 match(RegL);
5195 format %{ "EAX" %}
5196 interface(REG_INTER);
5197 %}
5199 // Flags register, used as output of compare instructions
5200 operand eFlagsReg() %{
5201 constraint(ALLOC_IN_RC(int_flags));
5202 match(RegFlags);
5204 format %{ "EFLAGS" %}
5205 interface(REG_INTER);
5206 %}
5208 // Flags register, used as output of FLOATING POINT compare instructions
5209 operand eFlagsRegU() %{
5210 constraint(ALLOC_IN_RC(int_flags));
5211 match(RegFlags);
5213 format %{ "EFLAGS_U" %}
5214 interface(REG_INTER);
5215 %}
5217 operand eFlagsRegUCF() %{
5218 constraint(ALLOC_IN_RC(int_flags));
5219 match(RegFlags);
5220 predicate(false);
5222 format %{ "EFLAGS_U_CF" %}
5223 interface(REG_INTER);
5224 %}
5226 // Condition Code Register used by long compare
5227 operand flagsReg_long_LTGE() %{
5228 constraint(ALLOC_IN_RC(int_flags));
5229 match(RegFlags);
5230 format %{ "FLAGS_LTGE" %}
5231 interface(REG_INTER);
5232 %}
5233 operand flagsReg_long_EQNE() %{
5234 constraint(ALLOC_IN_RC(int_flags));
5235 match(RegFlags);
5236 format %{ "FLAGS_EQNE" %}
5237 interface(REG_INTER);
5238 %}
5239 operand flagsReg_long_LEGT() %{
5240 constraint(ALLOC_IN_RC(int_flags));
5241 match(RegFlags);
5242 format %{ "FLAGS_LEGT" %}
5243 interface(REG_INTER);
5244 %}
5246 // Float register operands
5247 operand regD() %{
5248 predicate( UseSSE < 2 );
5249 constraint(ALLOC_IN_RC(dbl_reg));
5250 match(RegD);
5251 match(regDPR1);
5252 match(regDPR2);
5253 format %{ %}
5254 interface(REG_INTER);
5255 %}
5257 operand regDPR1(regD reg) %{
5258 predicate( UseSSE < 2 );
5259 constraint(ALLOC_IN_RC(dbl_reg0));
5260 match(reg);
5261 format %{ "FPR1" %}
5262 interface(REG_INTER);
5263 %}
5265 operand regDPR2(regD reg) %{
5266 predicate( UseSSE < 2 );
5267 constraint(ALLOC_IN_RC(dbl_reg1));
5268 match(reg);
5269 format %{ "FPR2" %}
5270 interface(REG_INTER);
5271 %}
5273 operand regnotDPR1(regD reg) %{
5274 predicate( UseSSE < 2 );
5275 constraint(ALLOC_IN_RC(dbl_notreg0));
5276 match(reg);
5277 format %{ %}
5278 interface(REG_INTER);
5279 %}
5281 // XMM Double register operands
5282 operand regXD() %{
5283 predicate( UseSSE>=2 );
5284 constraint(ALLOC_IN_RC(xdb_reg));
5285 match(RegD);
5286 match(regXD6);
5287 match(regXD7);
5288 format %{ %}
5289 interface(REG_INTER);
5290 %}
5292 // XMM6 double register operands
5293 operand regXD6(regXD reg) %{
5294 predicate( UseSSE>=2 );
5295 constraint(ALLOC_IN_RC(xdb_reg6));
5296 match(reg);
5297 format %{ "XMM6" %}
5298 interface(REG_INTER);
5299 %}
5301 // XMM7 double register operands
5302 operand regXD7(regXD reg) %{
5303 predicate( UseSSE>=2 );
5304 constraint(ALLOC_IN_RC(xdb_reg7));
5305 match(reg);
5306 format %{ "XMM7" %}
5307 interface(REG_INTER);
5308 %}
5310 // Float register operands
5311 operand regF() %{
5312 predicate( UseSSE < 2 );
5313 constraint(ALLOC_IN_RC(flt_reg));
5314 match(RegF);
5315 match(regFPR1);
5316 format %{ %}
5317 interface(REG_INTER);
5318 %}
5320 // Float register operands
5321 operand regFPR1(regF reg) %{
5322 predicate( UseSSE < 2 );
5323 constraint(ALLOC_IN_RC(flt_reg0));
5324 match(reg);
5325 format %{ "FPR1" %}
5326 interface(REG_INTER);
5327 %}
5329 // XMM register operands
5330 operand regX() %{
5331 predicate( UseSSE>=1 );
5332 constraint(ALLOC_IN_RC(xmm_reg));
5333 match(RegF);
5334 format %{ %}
5335 interface(REG_INTER);
5336 %}
5339 //----------Memory Operands----------------------------------------------------
5340 // Direct Memory Operand
5341 operand direct(immP addr) %{
5342 match(addr);
5344 format %{ "[$addr]" %}
5345 interface(MEMORY_INTER) %{
5346 base(0xFFFFFFFF);
5347 index(0x4);
5348 scale(0x0);
5349 disp($addr);
5350 %}
5351 %}
5353 // Indirect Memory Operand
5354 operand indirect(eRegP reg) %{
5355 constraint(ALLOC_IN_RC(e_reg));
5356 match(reg);
5358 format %{ "[$reg]" %}
5359 interface(MEMORY_INTER) %{
5360 base($reg);
5361 index(0x4);
5362 scale(0x0);
5363 disp(0x0);
5364 %}
5365 %}
5367 // Indirect Memory Plus Short Offset Operand
5368 operand indOffset8(eRegP reg, immI8 off) %{
5369 match(AddP reg off);
5371 format %{ "[$reg + $off]" %}
5372 interface(MEMORY_INTER) %{
5373 base($reg);
5374 index(0x4);
5375 scale(0x0);
5376 disp($off);
5377 %}
5378 %}
5380 // Indirect Memory Plus Long Offset Operand
5381 operand indOffset32(eRegP reg, immI off) %{
5382 match(AddP reg off);
5384 format %{ "[$reg + $off]" %}
5385 interface(MEMORY_INTER) %{
5386 base($reg);
5387 index(0x4);
5388 scale(0x0);
5389 disp($off);
5390 %}
5391 %}
5393 // Indirect Memory Plus Long Offset Operand
5394 operand indOffset32X(eRegI reg, immP off) %{
5395 match(AddP off reg);
5397 format %{ "[$reg + $off]" %}
5398 interface(MEMORY_INTER) %{
5399 base($reg);
5400 index(0x4);
5401 scale(0x0);
5402 disp($off);
5403 %}
5404 %}
5406 // Indirect Memory Plus Index Register Plus Offset Operand
5407 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5408 match(AddP (AddP reg ireg) off);
5410 op_cost(10);
5411 format %{"[$reg + $off + $ireg]" %}
5412 interface(MEMORY_INTER) %{
5413 base($reg);
5414 index($ireg);
5415 scale(0x0);
5416 disp($off);
5417 %}
5418 %}
5420 // Indirect Memory Plus Index Register Plus Offset Operand
5421 operand indIndex(eRegP reg, eRegI ireg) %{
5422 match(AddP reg ireg);
5424 op_cost(10);
5425 format %{"[$reg + $ireg]" %}
5426 interface(MEMORY_INTER) %{
5427 base($reg);
5428 index($ireg);
5429 scale(0x0);
5430 disp(0x0);
5431 %}
5432 %}
5434 // // -------------------------------------------------------------------------
5435 // // 486 architecture doesn't support "scale * index + offset" with out a base
5436 // // -------------------------------------------------------------------------
5437 // // Scaled Memory Operands
5438 // // Indirect Memory Times Scale Plus Offset Operand
5439 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5440 // match(AddP off (LShiftI ireg scale));
5441 //
5442 // op_cost(10);
5443 // format %{"[$off + $ireg << $scale]" %}
5444 // interface(MEMORY_INTER) %{
5445 // base(0x4);
5446 // index($ireg);
5447 // scale($scale);
5448 // disp($off);
5449 // %}
5450 // %}
5452 // Indirect Memory Times Scale Plus Index Register
5453 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5454 match(AddP reg (LShiftI ireg scale));
5456 op_cost(10);
5457 format %{"[$reg + $ireg << $scale]" %}
5458 interface(MEMORY_INTER) %{
5459 base($reg);
5460 index($ireg);
5461 scale($scale);
5462 disp(0x0);
5463 %}
5464 %}
5466 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5467 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5468 match(AddP (AddP reg (LShiftI ireg scale)) off);
5470 op_cost(10);
5471 format %{"[$reg + $off + $ireg << $scale]" %}
5472 interface(MEMORY_INTER) %{
5473 base($reg);
5474 index($ireg);
5475 scale($scale);
5476 disp($off);
5477 %}
5478 %}
5480 //----------Load Long Memory Operands------------------------------------------
5481 // The load-long idiom will use it's address expression again after loading
5482 // the first word of the long. If the load-long destination overlaps with
5483 // registers used in the addressing expression, the 2nd half will be loaded
5484 // from a clobbered address. Fix this by requiring that load-long use
5485 // address registers that do not overlap with the load-long target.
5487 // load-long support
5488 operand load_long_RegP() %{
5489 constraint(ALLOC_IN_RC(esi_reg));
5490 match(RegP);
5491 match(eSIRegP);
5492 op_cost(100);
5493 format %{ %}
5494 interface(REG_INTER);
5495 %}
5497 // Indirect Memory Operand Long
5498 operand load_long_indirect(load_long_RegP reg) %{
5499 constraint(ALLOC_IN_RC(esi_reg));
5500 match(reg);
5502 format %{ "[$reg]" %}
5503 interface(MEMORY_INTER) %{
5504 base($reg);
5505 index(0x4);
5506 scale(0x0);
5507 disp(0x0);
5508 %}
5509 %}
5511 // Indirect Memory Plus Long Offset Operand
5512 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5513 match(AddP reg off);
5515 format %{ "[$reg + $off]" %}
5516 interface(MEMORY_INTER) %{
5517 base($reg);
5518 index(0x4);
5519 scale(0x0);
5520 disp($off);
5521 %}
5522 %}
5524 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5527 //----------Special Memory Operands--------------------------------------------
5528 // Stack Slot Operand - This operand is used for loading and storing temporary
5529 // values on the stack where a match requires a value to
5530 // flow through memory.
5531 operand stackSlotP(sRegP reg) %{
5532 constraint(ALLOC_IN_RC(stack_slots));
5533 // No match rule because this operand is only generated in matching
5534 format %{ "[$reg]" %}
5535 interface(MEMORY_INTER) %{
5536 base(0x4); // ESP
5537 index(0x4); // No Index
5538 scale(0x0); // No Scale
5539 disp($reg); // Stack Offset
5540 %}
5541 %}
5543 operand stackSlotI(sRegI reg) %{
5544 constraint(ALLOC_IN_RC(stack_slots));
5545 // No match rule because this operand is only generated in matching
5546 format %{ "[$reg]" %}
5547 interface(MEMORY_INTER) %{
5548 base(0x4); // ESP
5549 index(0x4); // No Index
5550 scale(0x0); // No Scale
5551 disp($reg); // Stack Offset
5552 %}
5553 %}
5555 operand stackSlotF(sRegF reg) %{
5556 constraint(ALLOC_IN_RC(stack_slots));
5557 // No match rule because this operand is only generated in matching
5558 format %{ "[$reg]" %}
5559 interface(MEMORY_INTER) %{
5560 base(0x4); // ESP
5561 index(0x4); // No Index
5562 scale(0x0); // No Scale
5563 disp($reg); // Stack Offset
5564 %}
5565 %}
5567 operand stackSlotD(sRegD reg) %{
5568 constraint(ALLOC_IN_RC(stack_slots));
5569 // No match rule because this operand is only generated in matching
5570 format %{ "[$reg]" %}
5571 interface(MEMORY_INTER) %{
5572 base(0x4); // ESP
5573 index(0x4); // No Index
5574 scale(0x0); // No Scale
5575 disp($reg); // Stack Offset
5576 %}
5577 %}
5579 operand stackSlotL(sRegL reg) %{
5580 constraint(ALLOC_IN_RC(stack_slots));
5581 // No match rule because this operand is only generated in matching
5582 format %{ "[$reg]" %}
5583 interface(MEMORY_INTER) %{
5584 base(0x4); // ESP
5585 index(0x4); // No Index
5586 scale(0x0); // No Scale
5587 disp($reg); // Stack Offset
5588 %}
5589 %}
5591 //----------Memory Operands - Win95 Implicit Null Variants----------------
5592 // Indirect Memory Operand
5593 operand indirect_win95_safe(eRegP_no_EBP reg)
5594 %{
5595 constraint(ALLOC_IN_RC(e_reg));
5596 match(reg);
5598 op_cost(100);
5599 format %{ "[$reg]" %}
5600 interface(MEMORY_INTER) %{
5601 base($reg);
5602 index(0x4);
5603 scale(0x0);
5604 disp(0x0);
5605 %}
5606 %}
5608 // Indirect Memory Plus Short Offset Operand
5609 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5610 %{
5611 match(AddP reg off);
5613 op_cost(100);
5614 format %{ "[$reg + $off]" %}
5615 interface(MEMORY_INTER) %{
5616 base($reg);
5617 index(0x4);
5618 scale(0x0);
5619 disp($off);
5620 %}
5621 %}
5623 // Indirect Memory Plus Long Offset Operand
5624 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5625 %{
5626 match(AddP reg off);
5628 op_cost(100);
5629 format %{ "[$reg + $off]" %}
5630 interface(MEMORY_INTER) %{
5631 base($reg);
5632 index(0x4);
5633 scale(0x0);
5634 disp($off);
5635 %}
5636 %}
5638 // Indirect Memory Plus Index Register Plus Offset Operand
5639 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5640 %{
5641 match(AddP (AddP reg ireg) off);
5643 op_cost(100);
5644 format %{"[$reg + $off + $ireg]" %}
5645 interface(MEMORY_INTER) %{
5646 base($reg);
5647 index($ireg);
5648 scale(0x0);
5649 disp($off);
5650 %}
5651 %}
5653 // Indirect Memory Times Scale Plus Index Register
5654 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5655 %{
5656 match(AddP reg (LShiftI ireg scale));
5658 op_cost(100);
5659 format %{"[$reg + $ireg << $scale]" %}
5660 interface(MEMORY_INTER) %{
5661 base($reg);
5662 index($ireg);
5663 scale($scale);
5664 disp(0x0);
5665 %}
5666 %}
5668 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5669 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5670 %{
5671 match(AddP (AddP reg (LShiftI ireg scale)) off);
5673 op_cost(100);
5674 format %{"[$reg + $off + $ireg << $scale]" %}
5675 interface(MEMORY_INTER) %{
5676 base($reg);
5677 index($ireg);
5678 scale($scale);
5679 disp($off);
5680 %}
5681 %}
5683 //----------Conditional Branch Operands----------------------------------------
5684 // Comparison Op - This is the operation of the comparison, and is limited to
5685 // the following set of codes:
5686 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5687 //
5688 // Other attributes of the comparison, such as unsignedness, are specified
5689 // by the comparison instruction that sets a condition code flags register.
5690 // That result is represented by a flags operand whose subtype is appropriate
5691 // to the unsignedness (etc.) of the comparison.
5692 //
5693 // Later, the instruction which matches both the Comparison Op (a Bool) and
5694 // the flags (produced by the Cmp) specifies the coding of the comparison op
5695 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5697 // Comparision Code
5698 operand cmpOp() %{
5699 match(Bool);
5701 format %{ "" %}
5702 interface(COND_INTER) %{
5703 equal(0x4, "e");
5704 not_equal(0x5, "ne");
5705 less(0xC, "l");
5706 greater_equal(0xD, "ge");
5707 less_equal(0xE, "le");
5708 greater(0xF, "g");
5709 %}
5710 %}
5712 // Comparison Code, unsigned compare. Used by FP also, with
5713 // C2 (unordered) turned into GT or LT already. The other bits
5714 // C0 and C3 are turned into Carry & Zero flags.
5715 operand cmpOpU() %{
5716 match(Bool);
5718 format %{ "" %}
5719 interface(COND_INTER) %{
5720 equal(0x4, "e");
5721 not_equal(0x5, "ne");
5722 less(0x2, "b");
5723 greater_equal(0x3, "nb");
5724 less_equal(0x6, "be");
5725 greater(0x7, "nbe");
5726 %}
5727 %}
5729 // Floating comparisons that don't require any fixup for the unordered case
5730 operand cmpOpUCF() %{
5731 match(Bool);
5732 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5733 n->as_Bool()->_test._test == BoolTest::ge ||
5734 n->as_Bool()->_test._test == BoolTest::le ||
5735 n->as_Bool()->_test._test == BoolTest::gt);
5736 format %{ "" %}
5737 interface(COND_INTER) %{
5738 equal(0x4, "e");
5739 not_equal(0x5, "ne");
5740 less(0x2, "b");
5741 greater_equal(0x3, "nb");
5742 less_equal(0x6, "be");
5743 greater(0x7, "nbe");
5744 %}
5745 %}
5748 // Floating comparisons that can be fixed up with extra conditional jumps
5749 operand cmpOpUCF2() %{
5750 match(Bool);
5751 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5752 n->as_Bool()->_test._test == BoolTest::eq);
5753 format %{ "" %}
5754 interface(COND_INTER) %{
5755 equal(0x4, "e");
5756 not_equal(0x5, "ne");
5757 less(0x2, "b");
5758 greater_equal(0x3, "nb");
5759 less_equal(0x6, "be");
5760 greater(0x7, "nbe");
5761 %}
5762 %}
5764 // Comparison Code for FP conditional move
5765 operand cmpOp_fcmov() %{
5766 match(Bool);
5768 format %{ "" %}
5769 interface(COND_INTER) %{
5770 equal (0x0C8);
5771 not_equal (0x1C8);
5772 less (0x0C0);
5773 greater_equal(0x1C0);
5774 less_equal (0x0D0);
5775 greater (0x1D0);
5776 %}
5777 %}
5779 // Comparision Code used in long compares
5780 operand cmpOp_commute() %{
5781 match(Bool);
5783 format %{ "" %}
5784 interface(COND_INTER) %{
5785 equal(0x4, "e");
5786 not_equal(0x5, "ne");
5787 less(0xF, "g");
5788 greater_equal(0xE, "le");
5789 less_equal(0xD, "ge");
5790 greater(0xC, "l");
5791 %}
5792 %}
5794 //----------OPERAND CLASSES----------------------------------------------------
5795 // Operand Classes are groups of operands that are used as to simplify
5796 // instruction definitions by not requiring the AD writer to specify separate
5797 // instructions for every form of operand when the instruction accepts
5798 // multiple operand types with the same basic encoding and format. The classic
5799 // case of this is memory operands.
5801 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5802 indIndex, indIndexScale, indIndexScaleOffset);
5804 // Long memory operations are encoded in 2 instructions and a +4 offset.
5805 // This means some kind of offset is always required and you cannot use
5806 // an oop as the offset (done when working on static globals).
5807 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5808 indIndex, indIndexScale, indIndexScaleOffset);
5811 //----------PIPELINE-----------------------------------------------------------
5812 // Rules which define the behavior of the target architectures pipeline.
5813 pipeline %{
5815 //----------ATTRIBUTES---------------------------------------------------------
5816 attributes %{
5817 variable_size_instructions; // Fixed size instructions
5818 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5819 instruction_unit_size = 1; // An instruction is 1 bytes long
5820 instruction_fetch_unit_size = 16; // The processor fetches one line
5821 instruction_fetch_units = 1; // of 16 bytes
5823 // List of nop instructions
5824 nops( MachNop );
5825 %}
5827 //----------RESOURCES----------------------------------------------------------
5828 // Resources are the functional units available to the machine
5830 // Generic P2/P3 pipeline
5831 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5832 // 3 instructions decoded per cycle.
5833 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5834 // 2 ALU op, only ALU0 handles mul/div instructions.
5835 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5836 MS0, MS1, MEM = MS0 | MS1,
5837 BR, FPU,
5838 ALU0, ALU1, ALU = ALU0 | ALU1 );
5840 //----------PIPELINE DESCRIPTION-----------------------------------------------
5841 // Pipeline Description specifies the stages in the machine's pipeline
5843 // Generic P2/P3 pipeline
5844 pipe_desc(S0, S1, S2, S3, S4, S5);
5846 //----------PIPELINE CLASSES---------------------------------------------------
5847 // Pipeline Classes describe the stages in which input and output are
5848 // referenced by the hardware pipeline.
5850 // Naming convention: ialu or fpu
5851 // Then: _reg
5852 // Then: _reg if there is a 2nd register
5853 // Then: _long if it's a pair of instructions implementing a long
5854 // Then: _fat if it requires the big decoder
5855 // Or: _mem if it requires the big decoder and a memory unit.
5857 // Integer ALU reg operation
5858 pipe_class ialu_reg(eRegI dst) %{
5859 single_instruction;
5860 dst : S4(write);
5861 dst : S3(read);
5862 DECODE : S0; // any decoder
5863 ALU : S3; // any alu
5864 %}
5866 // Long ALU reg operation
5867 pipe_class ialu_reg_long(eRegL dst) %{
5868 instruction_count(2);
5869 dst : S4(write);
5870 dst : S3(read);
5871 DECODE : S0(2); // any 2 decoders
5872 ALU : S3(2); // both alus
5873 %}
5875 // Integer ALU reg operation using big decoder
5876 pipe_class ialu_reg_fat(eRegI dst) %{
5877 single_instruction;
5878 dst : S4(write);
5879 dst : S3(read);
5880 D0 : S0; // big decoder only
5881 ALU : S3; // any alu
5882 %}
5884 // Long ALU reg operation using big decoder
5885 pipe_class ialu_reg_long_fat(eRegL dst) %{
5886 instruction_count(2);
5887 dst : S4(write);
5888 dst : S3(read);
5889 D0 : S0(2); // big decoder only; twice
5890 ALU : S3(2); // any 2 alus
5891 %}
5893 // Integer ALU reg-reg operation
5894 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5895 single_instruction;
5896 dst : S4(write);
5897 src : S3(read);
5898 DECODE : S0; // any decoder
5899 ALU : S3; // any alu
5900 %}
5902 // Long ALU reg-reg operation
5903 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5904 instruction_count(2);
5905 dst : S4(write);
5906 src : S3(read);
5907 DECODE : S0(2); // any 2 decoders
5908 ALU : S3(2); // both alus
5909 %}
5911 // Integer ALU reg-reg operation
5912 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5913 single_instruction;
5914 dst : S4(write);
5915 src : S3(read);
5916 D0 : S0; // big decoder only
5917 ALU : S3; // any alu
5918 %}
5920 // Long ALU reg-reg operation
5921 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5922 instruction_count(2);
5923 dst : S4(write);
5924 src : S3(read);
5925 D0 : S0(2); // big decoder only; twice
5926 ALU : S3(2); // both alus
5927 %}
5929 // Integer ALU reg-mem operation
5930 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5931 single_instruction;
5932 dst : S5(write);
5933 mem : S3(read);
5934 D0 : S0; // big decoder only
5935 ALU : S4; // any alu
5936 MEM : S3; // any mem
5937 %}
5939 // Long ALU reg-mem operation
5940 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5941 instruction_count(2);
5942 dst : S5(write);
5943 mem : S3(read);
5944 D0 : S0(2); // big decoder only; twice
5945 ALU : S4(2); // any 2 alus
5946 MEM : S3(2); // both mems
5947 %}
5949 // Integer mem operation (prefetch)
5950 pipe_class ialu_mem(memory mem)
5951 %{
5952 single_instruction;
5953 mem : S3(read);
5954 D0 : S0; // big decoder only
5955 MEM : S3; // any mem
5956 %}
5958 // Integer Store to Memory
5959 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5960 single_instruction;
5961 mem : S3(read);
5962 src : S5(read);
5963 D0 : S0; // big decoder only
5964 ALU : S4; // any alu
5965 MEM : S3;
5966 %}
5968 // Long Store to Memory
5969 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5970 instruction_count(2);
5971 mem : S3(read);
5972 src : S5(read);
5973 D0 : S0(2); // big decoder only; twice
5974 ALU : S4(2); // any 2 alus
5975 MEM : S3(2); // Both mems
5976 %}
5978 // Integer Store to Memory
5979 pipe_class ialu_mem_imm(memory mem) %{
5980 single_instruction;
5981 mem : S3(read);
5982 D0 : S0; // big decoder only
5983 ALU : S4; // any alu
5984 MEM : S3;
5985 %}
5987 // Integer ALU0 reg-reg operation
5988 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5989 single_instruction;
5990 dst : S4(write);
5991 src : S3(read);
5992 D0 : S0; // Big decoder only
5993 ALU0 : S3; // only alu0
5994 %}
5996 // Integer ALU0 reg-mem operation
5997 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
5998 single_instruction;
5999 dst : S5(write);
6000 mem : S3(read);
6001 D0 : S0; // big decoder only
6002 ALU0 : S4; // ALU0 only
6003 MEM : S3; // any mem
6004 %}
6006 // Integer ALU reg-reg operation
6007 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6008 single_instruction;
6009 cr : S4(write);
6010 src1 : S3(read);
6011 src2 : S3(read);
6012 DECODE : S0; // any decoder
6013 ALU : S3; // any alu
6014 %}
6016 // Integer ALU reg-imm operation
6017 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6018 single_instruction;
6019 cr : S4(write);
6020 src1 : S3(read);
6021 DECODE : S0; // any decoder
6022 ALU : S3; // any alu
6023 %}
6025 // Integer ALU reg-mem operation
6026 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6027 single_instruction;
6028 cr : S4(write);
6029 src1 : S3(read);
6030 src2 : S3(read);
6031 D0 : S0; // big decoder only
6032 ALU : S4; // any alu
6033 MEM : S3;
6034 %}
6036 // Conditional move reg-reg
6037 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6038 instruction_count(4);
6039 y : S4(read);
6040 q : S3(read);
6041 p : S3(read);
6042 DECODE : S0(4); // any decoder
6043 %}
6045 // Conditional move reg-reg
6046 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6047 single_instruction;
6048 dst : S4(write);
6049 src : S3(read);
6050 cr : S3(read);
6051 DECODE : S0; // any decoder
6052 %}
6054 // Conditional move reg-mem
6055 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6056 single_instruction;
6057 dst : S4(write);
6058 src : S3(read);
6059 cr : S3(read);
6060 DECODE : S0; // any decoder
6061 MEM : S3;
6062 %}
6064 // Conditional move reg-reg long
6065 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6066 single_instruction;
6067 dst : S4(write);
6068 src : S3(read);
6069 cr : S3(read);
6070 DECODE : S0(2); // any 2 decoders
6071 %}
6073 // Conditional move double reg-reg
6074 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6075 single_instruction;
6076 dst : S4(write);
6077 src : S3(read);
6078 cr : S3(read);
6079 DECODE : S0; // any decoder
6080 %}
6082 // Float reg-reg operation
6083 pipe_class fpu_reg(regD dst) %{
6084 instruction_count(2);
6085 dst : S3(read);
6086 DECODE : S0(2); // any 2 decoders
6087 FPU : S3;
6088 %}
6090 // Float reg-reg operation
6091 pipe_class fpu_reg_reg(regD dst, regD src) %{
6092 instruction_count(2);
6093 dst : S4(write);
6094 src : S3(read);
6095 DECODE : S0(2); // any 2 decoders
6096 FPU : S3;
6097 %}
6099 // Float reg-reg operation
6100 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6101 instruction_count(3);
6102 dst : S4(write);
6103 src1 : S3(read);
6104 src2 : S3(read);
6105 DECODE : S0(3); // any 3 decoders
6106 FPU : S3(2);
6107 %}
6109 // Float reg-reg operation
6110 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6111 instruction_count(4);
6112 dst : S4(write);
6113 src1 : S3(read);
6114 src2 : S3(read);
6115 src3 : S3(read);
6116 DECODE : S0(4); // any 3 decoders
6117 FPU : S3(2);
6118 %}
6120 // Float reg-reg operation
6121 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6122 instruction_count(4);
6123 dst : S4(write);
6124 src1 : S3(read);
6125 src2 : S3(read);
6126 src3 : S3(read);
6127 DECODE : S1(3); // any 3 decoders
6128 D0 : S0; // Big decoder only
6129 FPU : S3(2);
6130 MEM : S3;
6131 %}
6133 // Float reg-mem operation
6134 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6135 instruction_count(2);
6136 dst : S5(write);
6137 mem : S3(read);
6138 D0 : S0; // big decoder only
6139 DECODE : S1; // any decoder for FPU POP
6140 FPU : S4;
6141 MEM : S3; // any mem
6142 %}
6144 // Float reg-mem operation
6145 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6146 instruction_count(3);
6147 dst : S5(write);
6148 src1 : S3(read);
6149 mem : S3(read);
6150 D0 : S0; // big decoder only
6151 DECODE : S1(2); // any decoder for FPU POP
6152 FPU : S4;
6153 MEM : S3; // any mem
6154 %}
6156 // Float mem-reg operation
6157 pipe_class fpu_mem_reg(memory mem, regD src) %{
6158 instruction_count(2);
6159 src : S5(read);
6160 mem : S3(read);
6161 DECODE : S0; // any decoder for FPU PUSH
6162 D0 : S1; // big decoder only
6163 FPU : S4;
6164 MEM : S3; // any mem
6165 %}
6167 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6168 instruction_count(3);
6169 src1 : S3(read);
6170 src2 : S3(read);
6171 mem : S3(read);
6172 DECODE : S0(2); // any decoder for FPU PUSH
6173 D0 : S1; // big decoder only
6174 FPU : S4;
6175 MEM : S3; // any mem
6176 %}
6178 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6179 instruction_count(3);
6180 src1 : S3(read);
6181 src2 : S3(read);
6182 mem : S4(read);
6183 DECODE : S0; // any decoder for FPU PUSH
6184 D0 : S0(2); // big decoder only
6185 FPU : S4;
6186 MEM : S3(2); // any mem
6187 %}
6189 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6190 instruction_count(2);
6191 src1 : S3(read);
6192 dst : S4(read);
6193 D0 : S0(2); // big decoder only
6194 MEM : S3(2); // any mem
6195 %}
6197 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6198 instruction_count(3);
6199 src1 : S3(read);
6200 src2 : S3(read);
6201 dst : S4(read);
6202 D0 : S0(3); // big decoder only
6203 FPU : S4;
6204 MEM : S3(3); // any mem
6205 %}
6207 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6208 instruction_count(3);
6209 src1 : S4(read);
6210 mem : S4(read);
6211 DECODE : S0; // any decoder for FPU PUSH
6212 D0 : S0(2); // big decoder only
6213 FPU : S4;
6214 MEM : S3(2); // any mem
6215 %}
6217 // Float load constant
6218 pipe_class fpu_reg_con(regD dst) %{
6219 instruction_count(2);
6220 dst : S5(write);
6221 D0 : S0; // big decoder only for the load
6222 DECODE : S1; // any decoder for FPU POP
6223 FPU : S4;
6224 MEM : S3; // any mem
6225 %}
6227 // Float load constant
6228 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6229 instruction_count(3);
6230 dst : S5(write);
6231 src : S3(read);
6232 D0 : S0; // big decoder only for the load
6233 DECODE : S1(2); // any decoder for FPU POP
6234 FPU : S4;
6235 MEM : S3; // any mem
6236 %}
6238 // UnConditional branch
6239 pipe_class pipe_jmp( label labl ) %{
6240 single_instruction;
6241 BR : S3;
6242 %}
6244 // Conditional branch
6245 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6246 single_instruction;
6247 cr : S1(read);
6248 BR : S3;
6249 %}
6251 // Allocation idiom
6252 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6253 instruction_count(1); force_serialization;
6254 fixed_latency(6);
6255 heap_ptr : S3(read);
6256 DECODE : S0(3);
6257 D0 : S2;
6258 MEM : S3;
6259 ALU : S3(2);
6260 dst : S5(write);
6261 BR : S5;
6262 %}
6264 // Generic big/slow expanded idiom
6265 pipe_class pipe_slow( ) %{
6266 instruction_count(10); multiple_bundles; force_serialization;
6267 fixed_latency(100);
6268 D0 : S0(2);
6269 MEM : S3(2);
6270 %}
6272 // The real do-nothing guy
6273 pipe_class empty( ) %{
6274 instruction_count(0);
6275 %}
6277 // Define the class for the Nop node
6278 define %{
6279 MachNop = empty;
6280 %}
6282 %}
6284 //----------INSTRUCTIONS-------------------------------------------------------
6285 //
6286 // match -- States which machine-independent subtree may be replaced
6287 // by this instruction.
6288 // ins_cost -- The estimated cost of this instruction is used by instruction
6289 // selection to identify a minimum cost tree of machine
6290 // instructions that matches a tree of machine-independent
6291 // instructions.
6292 // format -- A string providing the disassembly for this instruction.
6293 // The value of an instruction's operand may be inserted
6294 // by referring to it with a '$' prefix.
6295 // opcode -- Three instruction opcodes may be provided. These are referred
6296 // to within an encode class as $primary, $secondary, and $tertiary
6297 // respectively. The primary opcode is commonly used to
6298 // indicate the type of machine instruction, while secondary
6299 // and tertiary are often used for prefix options or addressing
6300 // modes.
6301 // ins_encode -- A list of encode classes with parameters. The encode class
6302 // name must have been defined in an 'enc_class' specification
6303 // in the encode section of the architecture description.
6305 //----------BSWAP-Instruction--------------------------------------------------
6306 instruct bytes_reverse_int(eRegI dst) %{
6307 match(Set dst (ReverseBytesI dst));
6309 format %{ "BSWAP $dst" %}
6310 opcode(0x0F, 0xC8);
6311 ins_encode( OpcP, OpcSReg(dst) );
6312 ins_pipe( ialu_reg );
6313 %}
6315 instruct bytes_reverse_long(eRegL dst) %{
6316 match(Set dst (ReverseBytesL dst));
6318 format %{ "BSWAP $dst.lo\n\t"
6319 "BSWAP $dst.hi\n\t"
6320 "XCHG $dst.lo $dst.hi" %}
6322 ins_cost(125);
6323 ins_encode( bswap_long_bytes(dst) );
6324 ins_pipe( ialu_reg_reg);
6325 %}
6327 instruct bytes_reverse_unsigned_short(eRegI dst) %{
6328 match(Set dst (ReverseBytesUS dst));
6330 format %{ "BSWAP $dst\n\t"
6331 "SHR $dst,16\n\t" %}
6332 ins_encode %{
6333 __ bswapl($dst$$Register);
6334 __ shrl($dst$$Register, 16);
6335 %}
6336 ins_pipe( ialu_reg );
6337 %}
6339 instruct bytes_reverse_short(eRegI dst) %{
6340 match(Set dst (ReverseBytesS dst));
6342 format %{ "BSWAP $dst\n\t"
6343 "SAR $dst,16\n\t" %}
6344 ins_encode %{
6345 __ bswapl($dst$$Register);
6346 __ sarl($dst$$Register, 16);
6347 %}
6348 ins_pipe( ialu_reg );
6349 %}
6352 //---------- Zeros Count Instructions ------------------------------------------
6354 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6355 predicate(UseCountLeadingZerosInstruction);
6356 match(Set dst (CountLeadingZerosI src));
6357 effect(KILL cr);
6359 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
6360 ins_encode %{
6361 __ lzcntl($dst$$Register, $src$$Register);
6362 %}
6363 ins_pipe(ialu_reg);
6364 %}
6366 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{
6367 predicate(!UseCountLeadingZerosInstruction);
6368 match(Set dst (CountLeadingZerosI src));
6369 effect(KILL cr);
6371 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
6372 "JNZ skip\n\t"
6373 "MOV $dst, -1\n"
6374 "skip:\n\t"
6375 "NEG $dst\n\t"
6376 "ADD $dst, 31" %}
6377 ins_encode %{
6378 Register Rdst = $dst$$Register;
6379 Register Rsrc = $src$$Register;
6380 Label skip;
6381 __ bsrl(Rdst, Rsrc);
6382 __ jccb(Assembler::notZero, skip);
6383 __ movl(Rdst, -1);
6384 __ bind(skip);
6385 __ negl(Rdst);
6386 __ addl(Rdst, BitsPerInt - 1);
6387 %}
6388 ins_pipe(ialu_reg);
6389 %}
6391 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6392 predicate(UseCountLeadingZerosInstruction);
6393 match(Set dst (CountLeadingZerosL src));
6394 effect(TEMP dst, KILL cr);
6396 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
6397 "JNC done\n\t"
6398 "LZCNT $dst, $src.lo\n\t"
6399 "ADD $dst, 32\n"
6400 "done:" %}
6401 ins_encode %{
6402 Register Rdst = $dst$$Register;
6403 Register Rsrc = $src$$Register;
6404 Label done;
6405 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
6406 __ jccb(Assembler::carryClear, done);
6407 __ lzcntl(Rdst, Rsrc);
6408 __ addl(Rdst, BitsPerInt);
6409 __ bind(done);
6410 %}
6411 ins_pipe(ialu_reg);
6412 %}
6414 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{
6415 predicate(!UseCountLeadingZerosInstruction);
6416 match(Set dst (CountLeadingZerosL src));
6417 effect(TEMP dst, KILL cr);
6419 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
6420 "JZ msw_is_zero\n\t"
6421 "ADD $dst, 32\n\t"
6422 "JMP not_zero\n"
6423 "msw_is_zero:\n\t"
6424 "BSR $dst, $src.lo\n\t"
6425 "JNZ not_zero\n\t"
6426 "MOV $dst, -1\n"
6427 "not_zero:\n\t"
6428 "NEG $dst\n\t"
6429 "ADD $dst, 63\n" %}
6430 ins_encode %{
6431 Register Rdst = $dst$$Register;
6432 Register Rsrc = $src$$Register;
6433 Label msw_is_zero;
6434 Label not_zero;
6435 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
6436 __ jccb(Assembler::zero, msw_is_zero);
6437 __ addl(Rdst, BitsPerInt);
6438 __ jmpb(not_zero);
6439 __ bind(msw_is_zero);
6440 __ bsrl(Rdst, Rsrc);
6441 __ jccb(Assembler::notZero, not_zero);
6442 __ movl(Rdst, -1);
6443 __ bind(not_zero);
6444 __ negl(Rdst);
6445 __ addl(Rdst, BitsPerLong - 1);
6446 %}
6447 ins_pipe(ialu_reg);
6448 %}
6450 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{
6451 match(Set dst (CountTrailingZerosI src));
6452 effect(KILL cr);
6454 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
6455 "JNZ done\n\t"
6456 "MOV $dst, 32\n"
6457 "done:" %}
6458 ins_encode %{
6459 Register Rdst = $dst$$Register;
6460 Label done;
6461 __ bsfl(Rdst, $src$$Register);
6462 __ jccb(Assembler::notZero, done);
6463 __ movl(Rdst, BitsPerInt);
6464 __ bind(done);
6465 %}
6466 ins_pipe(ialu_reg);
6467 %}
6469 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{
6470 match(Set dst (CountTrailingZerosL src));
6471 effect(TEMP dst, KILL cr);
6473 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
6474 "JNZ done\n\t"
6475 "BSF $dst, $src.hi\n\t"
6476 "JNZ msw_not_zero\n\t"
6477 "MOV $dst, 32\n"
6478 "msw_not_zero:\n\t"
6479 "ADD $dst, 32\n"
6480 "done:" %}
6481 ins_encode %{
6482 Register Rdst = $dst$$Register;
6483 Register Rsrc = $src$$Register;
6484 Label msw_not_zero;
6485 Label done;
6486 __ bsfl(Rdst, Rsrc);
6487 __ jccb(Assembler::notZero, done);
6488 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
6489 __ jccb(Assembler::notZero, msw_not_zero);
6490 __ movl(Rdst, BitsPerInt);
6491 __ bind(msw_not_zero);
6492 __ addl(Rdst, BitsPerInt);
6493 __ bind(done);
6494 %}
6495 ins_pipe(ialu_reg);
6496 %}
6499 //---------- Population Count Instructions -------------------------------------
6501 instruct popCountI(eRegI dst, eRegI src) %{
6502 predicate(UsePopCountInstruction);
6503 match(Set dst (PopCountI src));
6505 format %{ "POPCNT $dst, $src" %}
6506 ins_encode %{
6507 __ popcntl($dst$$Register, $src$$Register);
6508 %}
6509 ins_pipe(ialu_reg);
6510 %}
6512 instruct popCountI_mem(eRegI dst, memory mem) %{
6513 predicate(UsePopCountInstruction);
6514 match(Set dst (PopCountI (LoadI mem)));
6516 format %{ "POPCNT $dst, $mem" %}
6517 ins_encode %{
6518 __ popcntl($dst$$Register, $mem$$Address);
6519 %}
6520 ins_pipe(ialu_reg);
6521 %}
6523 // Note: Long.bitCount(long) returns an int.
6524 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6525 predicate(UsePopCountInstruction);
6526 match(Set dst (PopCountL src));
6527 effect(KILL cr, TEMP tmp, TEMP dst);
6529 format %{ "POPCNT $dst, $src.lo\n\t"
6530 "POPCNT $tmp, $src.hi\n\t"
6531 "ADD $dst, $tmp" %}
6532 ins_encode %{
6533 __ popcntl($dst$$Register, $src$$Register);
6534 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6535 __ addl($dst$$Register, $tmp$$Register);
6536 %}
6537 ins_pipe(ialu_reg);
6538 %}
6540 // Note: Long.bitCount(long) returns an int.
6541 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6542 predicate(UsePopCountInstruction);
6543 match(Set dst (PopCountL (LoadL mem)));
6544 effect(KILL cr, TEMP tmp, TEMP dst);
6546 format %{ "POPCNT $dst, $mem\n\t"
6547 "POPCNT $tmp, $mem+4\n\t"
6548 "ADD $dst, $tmp" %}
6549 ins_encode %{
6550 //__ popcntl($dst$$Register, $mem$$Address$$first);
6551 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6552 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6553 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6554 __ addl($dst$$Register, $tmp$$Register);
6555 %}
6556 ins_pipe(ialu_reg);
6557 %}
6560 //----------Load/Store/Move Instructions---------------------------------------
6561 //----------Load Instructions--------------------------------------------------
6562 // Load Byte (8bit signed)
6563 instruct loadB(xRegI dst, memory mem) %{
6564 match(Set dst (LoadB mem));
6566 ins_cost(125);
6567 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6569 ins_encode %{
6570 __ movsbl($dst$$Register, $mem$$Address);
6571 %}
6573 ins_pipe(ialu_reg_mem);
6574 %}
6576 // Load Byte (8bit signed) into Long Register
6577 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6578 match(Set dst (ConvI2L (LoadB mem)));
6579 effect(KILL cr);
6581 ins_cost(375);
6582 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6583 "MOV $dst.hi,$dst.lo\n\t"
6584 "SAR $dst.hi,7" %}
6586 ins_encode %{
6587 __ movsbl($dst$$Register, $mem$$Address);
6588 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6589 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6590 %}
6592 ins_pipe(ialu_reg_mem);
6593 %}
6595 // Load Unsigned Byte (8bit UNsigned)
6596 instruct loadUB(xRegI dst, memory mem) %{
6597 match(Set dst (LoadUB mem));
6599 ins_cost(125);
6600 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6602 ins_encode %{
6603 __ movzbl($dst$$Register, $mem$$Address);
6604 %}
6606 ins_pipe(ialu_reg_mem);
6607 %}
6609 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6610 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
6611 match(Set dst (ConvI2L (LoadUB mem)));
6612 effect(KILL cr);
6614 ins_cost(250);
6615 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6616 "XOR $dst.hi,$dst.hi" %}
6618 ins_encode %{
6619 Register Rdst = $dst$$Register;
6620 __ movzbl(Rdst, $mem$$Address);
6621 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6622 %}
6624 ins_pipe(ialu_reg_mem);
6625 %}
6627 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
6628 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
6629 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
6630 effect(KILL cr);
6632 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
6633 "XOR $dst.hi,$dst.hi\n\t"
6634 "AND $dst.lo,$mask" %}
6635 ins_encode %{
6636 Register Rdst = $dst$$Register;
6637 __ movzbl(Rdst, $mem$$Address);
6638 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6639 __ andl(Rdst, $mask$$constant);
6640 %}
6641 ins_pipe(ialu_reg_mem);
6642 %}
6644 // Load Short (16bit signed)
6645 instruct loadS(eRegI dst, memory mem) %{
6646 match(Set dst (LoadS mem));
6648 ins_cost(125);
6649 format %{ "MOVSX $dst,$mem\t# short" %}
6651 ins_encode %{
6652 __ movswl($dst$$Register, $mem$$Address);
6653 %}
6655 ins_pipe(ialu_reg_mem);
6656 %}
6658 // Load Short (16 bit signed) to Byte (8 bit signed)
6659 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6660 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6662 ins_cost(125);
6663 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
6664 ins_encode %{
6665 __ movsbl($dst$$Register, $mem$$Address);
6666 %}
6667 ins_pipe(ialu_reg_mem);
6668 %}
6670 // Load Short (16bit signed) into Long Register
6671 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6672 match(Set dst (ConvI2L (LoadS mem)));
6673 effect(KILL cr);
6675 ins_cost(375);
6676 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6677 "MOV $dst.hi,$dst.lo\n\t"
6678 "SAR $dst.hi,15" %}
6680 ins_encode %{
6681 __ movswl($dst$$Register, $mem$$Address);
6682 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6683 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6684 %}
6686 ins_pipe(ialu_reg_mem);
6687 %}
6689 // Load Unsigned Short/Char (16bit unsigned)
6690 instruct loadUS(eRegI dst, memory mem) %{
6691 match(Set dst (LoadUS mem));
6693 ins_cost(125);
6694 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6696 ins_encode %{
6697 __ movzwl($dst$$Register, $mem$$Address);
6698 %}
6700 ins_pipe(ialu_reg_mem);
6701 %}
6703 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6704 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6705 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6707 ins_cost(125);
6708 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6709 ins_encode %{
6710 __ movsbl($dst$$Register, $mem$$Address);
6711 %}
6712 ins_pipe(ialu_reg_mem);
6713 %}
6715 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6716 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6717 match(Set dst (ConvI2L (LoadUS mem)));
6718 effect(KILL cr);
6720 ins_cost(250);
6721 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6722 "XOR $dst.hi,$dst.hi" %}
6724 ins_encode %{
6725 __ movzwl($dst$$Register, $mem$$Address);
6726 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6727 %}
6729 ins_pipe(ialu_reg_mem);
6730 %}
6732 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6733 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6734 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6735 effect(KILL cr);
6737 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6738 "XOR $dst.hi,$dst.hi" %}
6739 ins_encode %{
6740 Register Rdst = $dst$$Register;
6741 __ movzbl(Rdst, $mem$$Address);
6742 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6743 %}
6744 ins_pipe(ialu_reg_mem);
6745 %}
6747 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6748 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6749 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6750 effect(KILL cr);
6752 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6753 "XOR $dst.hi,$dst.hi\n\t"
6754 "AND $dst.lo,$mask" %}
6755 ins_encode %{
6756 Register Rdst = $dst$$Register;
6757 __ movzwl(Rdst, $mem$$Address);
6758 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6759 __ andl(Rdst, $mask$$constant);
6760 %}
6761 ins_pipe(ialu_reg_mem);
6762 %}
6764 // Load Integer
6765 instruct loadI(eRegI dst, memory mem) %{
6766 match(Set dst (LoadI mem));
6768 ins_cost(125);
6769 format %{ "MOV $dst,$mem\t# int" %}
6771 ins_encode %{
6772 __ movl($dst$$Register, $mem$$Address);
6773 %}
6775 ins_pipe(ialu_reg_mem);
6776 %}
6778 // Load Integer (32 bit signed) to Byte (8 bit signed)
6779 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{
6780 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6782 ins_cost(125);
6783 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6784 ins_encode %{
6785 __ movsbl($dst$$Register, $mem$$Address);
6786 %}
6787 ins_pipe(ialu_reg_mem);
6788 %}
6790 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6791 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{
6792 match(Set dst (AndI (LoadI mem) mask));
6794 ins_cost(125);
6795 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6796 ins_encode %{
6797 __ movzbl($dst$$Register, $mem$$Address);
6798 %}
6799 ins_pipe(ialu_reg_mem);
6800 %}
6802 // Load Integer (32 bit signed) to Short (16 bit signed)
6803 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{
6804 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6806 ins_cost(125);
6807 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6808 ins_encode %{
6809 __ movswl($dst$$Register, $mem$$Address);
6810 %}
6811 ins_pipe(ialu_reg_mem);
6812 %}
6814 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6815 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{
6816 match(Set dst (AndI (LoadI mem) mask));
6818 ins_cost(125);
6819 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6820 ins_encode %{
6821 __ movzwl($dst$$Register, $mem$$Address);
6822 %}
6823 ins_pipe(ialu_reg_mem);
6824 %}
6826 // Load Integer into Long Register
6827 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6828 match(Set dst (ConvI2L (LoadI mem)));
6829 effect(KILL cr);
6831 ins_cost(375);
6832 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6833 "MOV $dst.hi,$dst.lo\n\t"
6834 "SAR $dst.hi,31" %}
6836 ins_encode %{
6837 __ movl($dst$$Register, $mem$$Address);
6838 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6839 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6840 %}
6842 ins_pipe(ialu_reg_mem);
6843 %}
6845 // Load Integer with mask 0xFF into Long Register
6846 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6847 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6848 effect(KILL cr);
6850 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6851 "XOR $dst.hi,$dst.hi" %}
6852 ins_encode %{
6853 Register Rdst = $dst$$Register;
6854 __ movzbl(Rdst, $mem$$Address);
6855 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6856 %}
6857 ins_pipe(ialu_reg_mem);
6858 %}
6860 // Load Integer with mask 0xFFFF into Long Register
6861 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6862 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6863 effect(KILL cr);
6865 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6866 "XOR $dst.hi,$dst.hi" %}
6867 ins_encode %{
6868 Register Rdst = $dst$$Register;
6869 __ movzwl(Rdst, $mem$$Address);
6870 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6871 %}
6872 ins_pipe(ialu_reg_mem);
6873 %}
6875 // Load Integer with 32-bit mask into Long Register
6876 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6877 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6878 effect(KILL cr);
6880 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6881 "XOR $dst.hi,$dst.hi\n\t"
6882 "AND $dst.lo,$mask" %}
6883 ins_encode %{
6884 Register Rdst = $dst$$Register;
6885 __ movl(Rdst, $mem$$Address);
6886 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6887 __ andl(Rdst, $mask$$constant);
6888 %}
6889 ins_pipe(ialu_reg_mem);
6890 %}
6892 // Load Unsigned Integer into Long Register
6893 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6894 match(Set dst (LoadUI2L mem));
6895 effect(KILL cr);
6897 ins_cost(250);
6898 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6899 "XOR $dst.hi,$dst.hi" %}
6901 ins_encode %{
6902 __ movl($dst$$Register, $mem$$Address);
6903 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6904 %}
6906 ins_pipe(ialu_reg_mem);
6907 %}
6909 // Load Long. Cannot clobber address while loading, so restrict address
6910 // register to ESI
6911 instruct loadL(eRegL dst, load_long_memory mem) %{
6912 predicate(!((LoadLNode*)n)->require_atomic_access());
6913 match(Set dst (LoadL mem));
6915 ins_cost(250);
6916 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6917 "MOV $dst.hi,$mem+4" %}
6919 ins_encode %{
6920 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6921 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6922 __ movl($dst$$Register, Amemlo);
6923 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6924 %}
6926 ins_pipe(ialu_reg_long_mem);
6927 %}
6929 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6930 // then store it down to the stack and reload on the int
6931 // side.
6932 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6933 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6934 match(Set dst (LoadL mem));
6936 ins_cost(200);
6937 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6938 "FISTp $dst" %}
6939 ins_encode(enc_loadL_volatile(mem,dst));
6940 ins_pipe( fpu_reg_mem );
6941 %}
6943 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6944 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6945 match(Set dst (LoadL mem));
6946 effect(TEMP tmp);
6947 ins_cost(180);
6948 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6949 "MOVSD $dst,$tmp" %}
6950 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6951 ins_pipe( pipe_slow );
6952 %}
6954 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6955 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6956 match(Set dst (LoadL mem));
6957 effect(TEMP tmp);
6958 ins_cost(160);
6959 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6960 "MOVD $dst.lo,$tmp\n\t"
6961 "PSRLQ $tmp,32\n\t"
6962 "MOVD $dst.hi,$tmp" %}
6963 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6964 ins_pipe( pipe_slow );
6965 %}
6967 // Load Range
6968 instruct loadRange(eRegI dst, memory mem) %{
6969 match(Set dst (LoadRange mem));
6971 ins_cost(125);
6972 format %{ "MOV $dst,$mem" %}
6973 opcode(0x8B);
6974 ins_encode( OpcP, RegMem(dst,mem));
6975 ins_pipe( ialu_reg_mem );
6976 %}
6979 // Load Pointer
6980 instruct loadP(eRegP dst, memory mem) %{
6981 match(Set dst (LoadP mem));
6983 ins_cost(125);
6984 format %{ "MOV $dst,$mem" %}
6985 opcode(0x8B);
6986 ins_encode( OpcP, RegMem(dst,mem));
6987 ins_pipe( ialu_reg_mem );
6988 %}
6990 // Load Klass Pointer
6991 instruct loadKlass(eRegP dst, memory mem) %{
6992 match(Set dst (LoadKlass mem));
6994 ins_cost(125);
6995 format %{ "MOV $dst,$mem" %}
6996 opcode(0x8B);
6997 ins_encode( OpcP, RegMem(dst,mem));
6998 ins_pipe( ialu_reg_mem );
6999 %}
7001 // Load Double
7002 instruct loadD(regD dst, memory mem) %{
7003 predicate(UseSSE<=1);
7004 match(Set dst (LoadD mem));
7006 ins_cost(150);
7007 format %{ "FLD_D ST,$mem\n\t"
7008 "FSTP $dst" %}
7009 opcode(0xDD); /* DD /0 */
7010 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7011 Pop_Reg_D(dst) );
7012 ins_pipe( fpu_reg_mem );
7013 %}
7015 // Load Double to XMM
7016 instruct loadXD(regXD dst, memory mem) %{
7017 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
7018 match(Set dst (LoadD mem));
7019 ins_cost(145);
7020 format %{ "MOVSD $dst,$mem" %}
7021 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7022 ins_pipe( pipe_slow );
7023 %}
7025 instruct loadXD_partial(regXD dst, memory mem) %{
7026 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
7027 match(Set dst (LoadD mem));
7028 ins_cost(145);
7029 format %{ "MOVLPD $dst,$mem" %}
7030 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
7031 ins_pipe( pipe_slow );
7032 %}
7034 // Load to XMM register (single-precision floating point)
7035 // MOVSS instruction
7036 instruct loadX(regX dst, memory mem) %{
7037 predicate(UseSSE>=1);
7038 match(Set dst (LoadF mem));
7039 ins_cost(145);
7040 format %{ "MOVSS $dst,$mem" %}
7041 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
7042 ins_pipe( pipe_slow );
7043 %}
7045 // Load Float
7046 instruct loadF(regF dst, memory mem) %{
7047 predicate(UseSSE==0);
7048 match(Set dst (LoadF mem));
7050 ins_cost(150);
7051 format %{ "FLD_S ST,$mem\n\t"
7052 "FSTP $dst" %}
7053 opcode(0xD9); /* D9 /0 */
7054 ins_encode( OpcP, RMopc_Mem(0x00,mem),
7055 Pop_Reg_F(dst) );
7056 ins_pipe( fpu_reg_mem );
7057 %}
7059 // Load Aligned Packed Byte to XMM register
7060 instruct loadA8B(regXD dst, memory mem) %{
7061 predicate(UseSSE>=1);
7062 match(Set dst (Load8B mem));
7063 ins_cost(125);
7064 format %{ "MOVQ $dst,$mem\t! packed8B" %}
7065 ins_encode( movq_ld(dst, mem));
7066 ins_pipe( pipe_slow );
7067 %}
7069 // Load Aligned Packed Short to XMM register
7070 instruct loadA4S(regXD dst, memory mem) %{
7071 predicate(UseSSE>=1);
7072 match(Set dst (Load4S mem));
7073 ins_cost(125);
7074 format %{ "MOVQ $dst,$mem\t! packed4S" %}
7075 ins_encode( movq_ld(dst, mem));
7076 ins_pipe( pipe_slow );
7077 %}
7079 // Load Aligned Packed Char to XMM register
7080 instruct loadA4C(regXD dst, memory mem) %{
7081 predicate(UseSSE>=1);
7082 match(Set dst (Load4C mem));
7083 ins_cost(125);
7084 format %{ "MOVQ $dst,$mem\t! packed4C" %}
7085 ins_encode( movq_ld(dst, mem));
7086 ins_pipe( pipe_slow );
7087 %}
7089 // Load Aligned Packed Integer to XMM register
7090 instruct load2IU(regXD dst, memory mem) %{
7091 predicate(UseSSE>=1);
7092 match(Set dst (Load2I mem));
7093 ins_cost(125);
7094 format %{ "MOVQ $dst,$mem\t! packed2I" %}
7095 ins_encode( movq_ld(dst, mem));
7096 ins_pipe( pipe_slow );
7097 %}
7099 // Load Aligned Packed Single to XMM
7100 instruct loadA2F(regXD dst, memory mem) %{
7101 predicate(UseSSE>=1);
7102 match(Set dst (Load2F mem));
7103 ins_cost(145);
7104 format %{ "MOVQ $dst,$mem\t! packed2F" %}
7105 ins_encode( movq_ld(dst, mem));
7106 ins_pipe( pipe_slow );
7107 %}
7109 // Load Effective Address
7110 instruct leaP8(eRegP dst, indOffset8 mem) %{
7111 match(Set dst mem);
7113 ins_cost(110);
7114 format %{ "LEA $dst,$mem" %}
7115 opcode(0x8D);
7116 ins_encode( OpcP, RegMem(dst,mem));
7117 ins_pipe( ialu_reg_reg_fat );
7118 %}
7120 instruct leaP32(eRegP dst, indOffset32 mem) %{
7121 match(Set dst mem);
7123 ins_cost(110);
7124 format %{ "LEA $dst,$mem" %}
7125 opcode(0x8D);
7126 ins_encode( OpcP, RegMem(dst,mem));
7127 ins_pipe( ialu_reg_reg_fat );
7128 %}
7130 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
7131 match(Set dst mem);
7133 ins_cost(110);
7134 format %{ "LEA $dst,$mem" %}
7135 opcode(0x8D);
7136 ins_encode( OpcP, RegMem(dst,mem));
7137 ins_pipe( ialu_reg_reg_fat );
7138 %}
7140 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
7141 match(Set dst mem);
7143 ins_cost(110);
7144 format %{ "LEA $dst,$mem" %}
7145 opcode(0x8D);
7146 ins_encode( OpcP, RegMem(dst,mem));
7147 ins_pipe( ialu_reg_reg_fat );
7148 %}
7150 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
7151 match(Set dst mem);
7153 ins_cost(110);
7154 format %{ "LEA $dst,$mem" %}
7155 opcode(0x8D);
7156 ins_encode( OpcP, RegMem(dst,mem));
7157 ins_pipe( ialu_reg_reg_fat );
7158 %}
7160 // Load Constant
7161 instruct loadConI(eRegI dst, immI src) %{
7162 match(Set dst src);
7164 format %{ "MOV $dst,$src" %}
7165 ins_encode( LdImmI(dst, src) );
7166 ins_pipe( ialu_reg_fat );
7167 %}
7169 // Load Constant zero
7170 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
7171 match(Set dst src);
7172 effect(KILL cr);
7174 ins_cost(50);
7175 format %{ "XOR $dst,$dst" %}
7176 opcode(0x33); /* + rd */
7177 ins_encode( OpcP, RegReg( dst, dst ) );
7178 ins_pipe( ialu_reg );
7179 %}
7181 instruct loadConP(eRegP dst, immP src) %{
7182 match(Set dst src);
7184 format %{ "MOV $dst,$src" %}
7185 opcode(0xB8); /* + rd */
7186 ins_encode( LdImmP(dst, src) );
7187 ins_pipe( ialu_reg_fat );
7188 %}
7190 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
7191 match(Set dst src);
7192 effect(KILL cr);
7193 ins_cost(200);
7194 format %{ "MOV $dst.lo,$src.lo\n\t"
7195 "MOV $dst.hi,$src.hi" %}
7196 opcode(0xB8);
7197 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7198 ins_pipe( ialu_reg_long_fat );
7199 %}
7201 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7202 match(Set dst src);
7203 effect(KILL cr);
7204 ins_cost(150);
7205 format %{ "XOR $dst.lo,$dst.lo\n\t"
7206 "XOR $dst.hi,$dst.hi" %}
7207 opcode(0x33,0x33);
7208 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7209 ins_pipe( ialu_reg_long );
7210 %}
7212 // The instruction usage is guarded by predicate in operand immF().
7213 instruct loadConF(regF dst, immF src) %{
7214 match(Set dst src);
7215 ins_cost(125);
7217 format %{ "FLD_S ST,$src\n\t"
7218 "FSTP $dst" %}
7219 opcode(0xD9, 0x00); /* D9 /0 */
7220 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7221 ins_pipe( fpu_reg_con );
7222 %}
7224 // The instruction usage is guarded by predicate in operand immXF().
7225 instruct loadConX(regX dst, immXF con) %{
7226 match(Set dst con);
7227 ins_cost(125);
7228 format %{ "MOVSS $dst,[$con]" %}
7229 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7230 ins_pipe( pipe_slow );
7231 %}
7233 // The instruction usage is guarded by predicate in operand immXF0().
7234 instruct loadConX0(regX dst, immXF0 src) %{
7235 match(Set dst src);
7236 ins_cost(100);
7237 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7238 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7239 ins_pipe( pipe_slow );
7240 %}
7242 // The instruction usage is guarded by predicate in operand immD().
7243 instruct loadConD(regD dst, immD src) %{
7244 match(Set dst src);
7245 ins_cost(125);
7247 format %{ "FLD_D ST,$src\n\t"
7248 "FSTP $dst" %}
7249 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7250 ins_pipe( fpu_reg_con );
7251 %}
7253 // The instruction usage is guarded by predicate in operand immXD().
7254 instruct loadConXD(regXD dst, immXD con) %{
7255 match(Set dst con);
7256 ins_cost(125);
7257 format %{ "MOVSD $dst,[$con]" %}
7258 ins_encode(load_conXD(dst, con));
7259 ins_pipe( pipe_slow );
7260 %}
7262 // The instruction usage is guarded by predicate in operand immXD0().
7263 instruct loadConXD0(regXD dst, immXD0 src) %{
7264 match(Set dst src);
7265 ins_cost(100);
7266 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7267 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7268 ins_pipe( pipe_slow );
7269 %}
7271 // Load Stack Slot
7272 instruct loadSSI(eRegI dst, stackSlotI src) %{
7273 match(Set dst src);
7274 ins_cost(125);
7276 format %{ "MOV $dst,$src" %}
7277 opcode(0x8B);
7278 ins_encode( OpcP, RegMem(dst,src));
7279 ins_pipe( ialu_reg_mem );
7280 %}
7282 instruct loadSSL(eRegL dst, stackSlotL src) %{
7283 match(Set dst src);
7285 ins_cost(200);
7286 format %{ "MOV $dst,$src.lo\n\t"
7287 "MOV $dst+4,$src.hi" %}
7288 opcode(0x8B, 0x8B);
7289 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7290 ins_pipe( ialu_mem_long_reg );
7291 %}
7293 // Load Stack Slot
7294 instruct loadSSP(eRegP dst, stackSlotP src) %{
7295 match(Set dst src);
7296 ins_cost(125);
7298 format %{ "MOV $dst,$src" %}
7299 opcode(0x8B);
7300 ins_encode( OpcP, RegMem(dst,src));
7301 ins_pipe( ialu_reg_mem );
7302 %}
7304 // Load Stack Slot
7305 instruct loadSSF(regF dst, stackSlotF src) %{
7306 match(Set dst src);
7307 ins_cost(125);
7309 format %{ "FLD_S $src\n\t"
7310 "FSTP $dst" %}
7311 opcode(0xD9); /* D9 /0, FLD m32real */
7312 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7313 Pop_Reg_F(dst) );
7314 ins_pipe( fpu_reg_mem );
7315 %}
7317 // Load Stack Slot
7318 instruct loadSSD(regD dst, stackSlotD src) %{
7319 match(Set dst src);
7320 ins_cost(125);
7322 format %{ "FLD_D $src\n\t"
7323 "FSTP $dst" %}
7324 opcode(0xDD); /* DD /0, FLD m64real */
7325 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7326 Pop_Reg_D(dst) );
7327 ins_pipe( fpu_reg_mem );
7328 %}
7330 // Prefetch instructions.
7331 // Must be safe to execute with invalid address (cannot fault).
7333 instruct prefetchr0( memory mem ) %{
7334 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7335 match(PrefetchRead mem);
7336 ins_cost(0);
7337 size(0);
7338 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7339 ins_encode();
7340 ins_pipe(empty);
7341 %}
7343 instruct prefetchr( memory mem ) %{
7344 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7345 match(PrefetchRead mem);
7346 ins_cost(100);
7348 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7349 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7350 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7351 ins_pipe(ialu_mem);
7352 %}
7354 instruct prefetchrNTA( memory mem ) %{
7355 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7356 match(PrefetchRead mem);
7357 ins_cost(100);
7359 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7360 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7361 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7362 ins_pipe(ialu_mem);
7363 %}
7365 instruct prefetchrT0( memory mem ) %{
7366 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7367 match(PrefetchRead mem);
7368 ins_cost(100);
7370 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7371 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7372 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7373 ins_pipe(ialu_mem);
7374 %}
7376 instruct prefetchrT2( memory mem ) %{
7377 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7378 match(PrefetchRead mem);
7379 ins_cost(100);
7381 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7382 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7383 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7384 ins_pipe(ialu_mem);
7385 %}
7387 instruct prefetchw0( memory mem ) %{
7388 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7389 match(PrefetchWrite mem);
7390 ins_cost(0);
7391 size(0);
7392 format %{ "Prefetch (non-SSE is empty encoding)" %}
7393 ins_encode();
7394 ins_pipe(empty);
7395 %}
7397 instruct prefetchw( memory mem ) %{
7398 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7399 match( PrefetchWrite mem );
7400 ins_cost(100);
7402 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7403 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7404 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7405 ins_pipe(ialu_mem);
7406 %}
7408 instruct prefetchwNTA( memory mem ) %{
7409 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7410 match(PrefetchWrite mem);
7411 ins_cost(100);
7413 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7414 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7415 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7416 ins_pipe(ialu_mem);
7417 %}
7419 instruct prefetchwT0( memory mem ) %{
7420 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7421 match(PrefetchWrite mem);
7422 ins_cost(100);
7424 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7425 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7426 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7427 ins_pipe(ialu_mem);
7428 %}
7430 instruct prefetchwT2( memory mem ) %{
7431 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7432 match(PrefetchWrite mem);
7433 ins_cost(100);
7435 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7436 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7437 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7438 ins_pipe(ialu_mem);
7439 %}
7441 //----------Store Instructions-------------------------------------------------
7443 // Store Byte
7444 instruct storeB(memory mem, xRegI src) %{
7445 match(Set mem (StoreB mem src));
7447 ins_cost(125);
7448 format %{ "MOV8 $mem,$src" %}
7449 opcode(0x88);
7450 ins_encode( OpcP, RegMem( src, mem ) );
7451 ins_pipe( ialu_mem_reg );
7452 %}
7454 // Store Char/Short
7455 instruct storeC(memory mem, eRegI src) %{
7456 match(Set mem (StoreC mem src));
7458 ins_cost(125);
7459 format %{ "MOV16 $mem,$src" %}
7460 opcode(0x89, 0x66);
7461 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7462 ins_pipe( ialu_mem_reg );
7463 %}
7465 // Store Integer
7466 instruct storeI(memory mem, eRegI src) %{
7467 match(Set mem (StoreI mem src));
7469 ins_cost(125);
7470 format %{ "MOV $mem,$src" %}
7471 opcode(0x89);
7472 ins_encode( OpcP, RegMem( src, mem ) );
7473 ins_pipe( ialu_mem_reg );
7474 %}
7476 // Store Long
7477 instruct storeL(long_memory mem, eRegL src) %{
7478 predicate(!((StoreLNode*)n)->require_atomic_access());
7479 match(Set mem (StoreL mem src));
7481 ins_cost(200);
7482 format %{ "MOV $mem,$src.lo\n\t"
7483 "MOV $mem+4,$src.hi" %}
7484 opcode(0x89, 0x89);
7485 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7486 ins_pipe( ialu_mem_long_reg );
7487 %}
7489 // Store Long to Integer
7490 instruct storeL2I(memory mem, eRegL src) %{
7491 match(Set mem (StoreI mem (ConvL2I src)));
7493 format %{ "MOV $mem,$src.lo\t# long -> int" %}
7494 ins_encode %{
7495 __ movl($mem$$Address, $src$$Register);
7496 %}
7497 ins_pipe(ialu_mem_reg);
7498 %}
7500 // Volatile Store Long. Must be atomic, so move it into
7501 // the FP TOS and then do a 64-bit FIST. Has to probe the
7502 // target address before the store (for null-ptr checks)
7503 // so the memory operand is used twice in the encoding.
7504 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7505 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7506 match(Set mem (StoreL mem src));
7507 effect( KILL cr );
7508 ins_cost(400);
7509 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7510 "FILD $src\n\t"
7511 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7512 opcode(0x3B);
7513 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7514 ins_pipe( fpu_reg_mem );
7515 %}
7517 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7518 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7519 match(Set mem (StoreL mem src));
7520 effect( TEMP tmp, KILL cr );
7521 ins_cost(380);
7522 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7523 "MOVSD $tmp,$src\n\t"
7524 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7525 opcode(0x3B);
7526 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7527 ins_pipe( pipe_slow );
7528 %}
7530 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7531 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7532 match(Set mem (StoreL mem src));
7533 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7534 ins_cost(360);
7535 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7536 "MOVD $tmp,$src.lo\n\t"
7537 "MOVD $tmp2,$src.hi\n\t"
7538 "PUNPCKLDQ $tmp,$tmp2\n\t"
7539 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7540 opcode(0x3B);
7541 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7542 ins_pipe( pipe_slow );
7543 %}
7545 // Store Pointer; for storing unknown oops and raw pointers
7546 instruct storeP(memory mem, anyRegP src) %{
7547 match(Set mem (StoreP mem src));
7549 ins_cost(125);
7550 format %{ "MOV $mem,$src" %}
7551 opcode(0x89);
7552 ins_encode( OpcP, RegMem( src, mem ) );
7553 ins_pipe( ialu_mem_reg );
7554 %}
7556 // Store Integer Immediate
7557 instruct storeImmI(memory mem, immI src) %{
7558 match(Set mem (StoreI mem src));
7560 ins_cost(150);
7561 format %{ "MOV $mem,$src" %}
7562 opcode(0xC7); /* C7 /0 */
7563 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7564 ins_pipe( ialu_mem_imm );
7565 %}
7567 // Store Short/Char Immediate
7568 instruct storeImmI16(memory mem, immI16 src) %{
7569 predicate(UseStoreImmI16);
7570 match(Set mem (StoreC mem src));
7572 ins_cost(150);
7573 format %{ "MOV16 $mem,$src" %}
7574 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7575 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7576 ins_pipe( ialu_mem_imm );
7577 %}
7579 // Store Pointer Immediate; null pointers or constant oops that do not
7580 // need card-mark barriers.
7581 instruct storeImmP(memory mem, immP src) %{
7582 match(Set mem (StoreP mem src));
7584 ins_cost(150);
7585 format %{ "MOV $mem,$src" %}
7586 opcode(0xC7); /* C7 /0 */
7587 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7588 ins_pipe( ialu_mem_imm );
7589 %}
7591 // Store Byte Immediate
7592 instruct storeImmB(memory mem, immI8 src) %{
7593 match(Set mem (StoreB mem src));
7595 ins_cost(150);
7596 format %{ "MOV8 $mem,$src" %}
7597 opcode(0xC6); /* C6 /0 */
7598 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7599 ins_pipe( ialu_mem_imm );
7600 %}
7602 // Store Aligned Packed Byte XMM register to memory
7603 instruct storeA8B(memory mem, regXD src) %{
7604 predicate(UseSSE>=1);
7605 match(Set mem (Store8B mem src));
7606 ins_cost(145);
7607 format %{ "MOVQ $mem,$src\t! packed8B" %}
7608 ins_encode( movq_st(mem, src));
7609 ins_pipe( pipe_slow );
7610 %}
7612 // Store Aligned Packed Char/Short XMM register to memory
7613 instruct storeA4C(memory mem, regXD src) %{
7614 predicate(UseSSE>=1);
7615 match(Set mem (Store4C mem src));
7616 ins_cost(145);
7617 format %{ "MOVQ $mem,$src\t! packed4C" %}
7618 ins_encode( movq_st(mem, src));
7619 ins_pipe( pipe_slow );
7620 %}
7622 // Store Aligned Packed Integer XMM register to memory
7623 instruct storeA2I(memory mem, regXD src) %{
7624 predicate(UseSSE>=1);
7625 match(Set mem (Store2I mem src));
7626 ins_cost(145);
7627 format %{ "MOVQ $mem,$src\t! packed2I" %}
7628 ins_encode( movq_st(mem, src));
7629 ins_pipe( pipe_slow );
7630 %}
7632 // Store CMS card-mark Immediate
7633 instruct storeImmCM(memory mem, immI8 src) %{
7634 match(Set mem (StoreCM mem src));
7636 ins_cost(150);
7637 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7638 opcode(0xC6); /* C6 /0 */
7639 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7640 ins_pipe( ialu_mem_imm );
7641 %}
7643 // Store Double
7644 instruct storeD( memory mem, regDPR1 src) %{
7645 predicate(UseSSE<=1);
7646 match(Set mem (StoreD mem src));
7648 ins_cost(100);
7649 format %{ "FST_D $mem,$src" %}
7650 opcode(0xDD); /* DD /2 */
7651 ins_encode( enc_FP_store(mem,src) );
7652 ins_pipe( fpu_mem_reg );
7653 %}
7655 // Store double does rounding on x86
7656 instruct storeD_rounded( memory mem, regDPR1 src) %{
7657 predicate(UseSSE<=1);
7658 match(Set mem (StoreD mem (RoundDouble src)));
7660 ins_cost(100);
7661 format %{ "FST_D $mem,$src\t# round" %}
7662 opcode(0xDD); /* DD /2 */
7663 ins_encode( enc_FP_store(mem,src) );
7664 ins_pipe( fpu_mem_reg );
7665 %}
7667 // Store XMM register to memory (double-precision floating points)
7668 // MOVSD instruction
7669 instruct storeXD(memory mem, regXD src) %{
7670 predicate(UseSSE>=2);
7671 match(Set mem (StoreD mem src));
7672 ins_cost(95);
7673 format %{ "MOVSD $mem,$src" %}
7674 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7675 ins_pipe( pipe_slow );
7676 %}
7678 // Store XMM register to memory (single-precision floating point)
7679 // MOVSS instruction
7680 instruct storeX(memory mem, regX src) %{
7681 predicate(UseSSE>=1);
7682 match(Set mem (StoreF mem src));
7683 ins_cost(95);
7684 format %{ "MOVSS $mem,$src" %}
7685 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7686 ins_pipe( pipe_slow );
7687 %}
7689 // Store Aligned Packed Single Float XMM register to memory
7690 instruct storeA2F(memory mem, regXD src) %{
7691 predicate(UseSSE>=1);
7692 match(Set mem (Store2F mem src));
7693 ins_cost(145);
7694 format %{ "MOVQ $mem,$src\t! packed2F" %}
7695 ins_encode( movq_st(mem, src));
7696 ins_pipe( pipe_slow );
7697 %}
7699 // Store Float
7700 instruct storeF( memory mem, regFPR1 src) %{
7701 predicate(UseSSE==0);
7702 match(Set mem (StoreF mem src));
7704 ins_cost(100);
7705 format %{ "FST_S $mem,$src" %}
7706 opcode(0xD9); /* D9 /2 */
7707 ins_encode( enc_FP_store(mem,src) );
7708 ins_pipe( fpu_mem_reg );
7709 %}
7711 // Store Float does rounding on x86
7712 instruct storeF_rounded( memory mem, regFPR1 src) %{
7713 predicate(UseSSE==0);
7714 match(Set mem (StoreF mem (RoundFloat src)));
7716 ins_cost(100);
7717 format %{ "FST_S $mem,$src\t# round" %}
7718 opcode(0xD9); /* D9 /2 */
7719 ins_encode( enc_FP_store(mem,src) );
7720 ins_pipe( fpu_mem_reg );
7721 %}
7723 // Store Float does rounding on x86
7724 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7725 predicate(UseSSE<=1);
7726 match(Set mem (StoreF mem (ConvD2F src)));
7728 ins_cost(100);
7729 format %{ "FST_S $mem,$src\t# D-round" %}
7730 opcode(0xD9); /* D9 /2 */
7731 ins_encode( enc_FP_store(mem,src) );
7732 ins_pipe( fpu_mem_reg );
7733 %}
7735 // Store immediate Float value (it is faster than store from FPU register)
7736 // The instruction usage is guarded by predicate in operand immF().
7737 instruct storeF_imm( memory mem, immF src) %{
7738 match(Set mem (StoreF mem src));
7740 ins_cost(50);
7741 format %{ "MOV $mem,$src\t# store float" %}
7742 opcode(0xC7); /* C7 /0 */
7743 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7744 ins_pipe( ialu_mem_imm );
7745 %}
7747 // Store immediate Float value (it is faster than store from XMM register)
7748 // The instruction usage is guarded by predicate in operand immXF().
7749 instruct storeX_imm( memory mem, immXF src) %{
7750 match(Set mem (StoreF mem src));
7752 ins_cost(50);
7753 format %{ "MOV $mem,$src\t# store float" %}
7754 opcode(0xC7); /* C7 /0 */
7755 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7756 ins_pipe( ialu_mem_imm );
7757 %}
7759 // Store Integer to stack slot
7760 instruct storeSSI(stackSlotI dst, eRegI src) %{
7761 match(Set dst src);
7763 ins_cost(100);
7764 format %{ "MOV $dst,$src" %}
7765 opcode(0x89);
7766 ins_encode( OpcPRegSS( dst, src ) );
7767 ins_pipe( ialu_mem_reg );
7768 %}
7770 // Store Integer to stack slot
7771 instruct storeSSP(stackSlotP dst, eRegP src) %{
7772 match(Set dst src);
7774 ins_cost(100);
7775 format %{ "MOV $dst,$src" %}
7776 opcode(0x89);
7777 ins_encode( OpcPRegSS( dst, src ) );
7778 ins_pipe( ialu_mem_reg );
7779 %}
7781 // Store Long to stack slot
7782 instruct storeSSL(stackSlotL dst, eRegL src) %{
7783 match(Set dst src);
7785 ins_cost(200);
7786 format %{ "MOV $dst,$src.lo\n\t"
7787 "MOV $dst+4,$src.hi" %}
7788 opcode(0x89, 0x89);
7789 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7790 ins_pipe( ialu_mem_long_reg );
7791 %}
7793 //----------MemBar Instructions-----------------------------------------------
7794 // Memory barrier flavors
7796 instruct membar_acquire() %{
7797 match(MemBarAcquire);
7798 ins_cost(400);
7800 size(0);
7801 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7802 ins_encode();
7803 ins_pipe(empty);
7804 %}
7806 instruct membar_acquire_lock() %{
7807 match(MemBarAcquire);
7808 predicate(Matcher::prior_fast_lock(n));
7809 ins_cost(0);
7811 size(0);
7812 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7813 ins_encode( );
7814 ins_pipe(empty);
7815 %}
7817 instruct membar_release() %{
7818 match(MemBarRelease);
7819 ins_cost(400);
7821 size(0);
7822 format %{ "MEMBAR-release ! (empty encoding)" %}
7823 ins_encode( );
7824 ins_pipe(empty);
7825 %}
7827 instruct membar_release_lock() %{
7828 match(MemBarRelease);
7829 predicate(Matcher::post_fast_unlock(n));
7830 ins_cost(0);
7832 size(0);
7833 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7834 ins_encode( );
7835 ins_pipe(empty);
7836 %}
7838 instruct membar_volatile(eFlagsReg cr) %{
7839 match(MemBarVolatile);
7840 effect(KILL cr);
7841 ins_cost(400);
7843 format %{
7844 $$template
7845 if (os::is_MP()) {
7846 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7847 } else {
7848 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7849 }
7850 %}
7851 ins_encode %{
7852 __ membar(Assembler::StoreLoad);
7853 %}
7854 ins_pipe(pipe_slow);
7855 %}
7857 instruct unnecessary_membar_volatile() %{
7858 match(MemBarVolatile);
7859 predicate(Matcher::post_store_load_barrier(n));
7860 ins_cost(0);
7862 size(0);
7863 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7864 ins_encode( );
7865 ins_pipe(empty);
7866 %}
7868 //----------Move Instructions--------------------------------------------------
7869 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7870 match(Set dst (CastX2P src));
7871 format %{ "# X2P $dst, $src" %}
7872 ins_encode( /*empty encoding*/ );
7873 ins_cost(0);
7874 ins_pipe(empty);
7875 %}
7877 instruct castP2X(eRegI dst, eRegP src ) %{
7878 match(Set dst (CastP2X src));
7879 ins_cost(50);
7880 format %{ "MOV $dst, $src\t# CastP2X" %}
7881 ins_encode( enc_Copy( dst, src) );
7882 ins_pipe( ialu_reg_reg );
7883 %}
7885 //----------Conditional Move---------------------------------------------------
7886 // Conditional move
7887 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7888 predicate(VM_Version::supports_cmov() );
7889 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7890 ins_cost(200);
7891 format %{ "CMOV$cop $dst,$src" %}
7892 opcode(0x0F,0x40);
7893 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7894 ins_pipe( pipe_cmov_reg );
7895 %}
7897 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7898 predicate(VM_Version::supports_cmov() );
7899 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7900 ins_cost(200);
7901 format %{ "CMOV$cop $dst,$src" %}
7902 opcode(0x0F,0x40);
7903 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7904 ins_pipe( pipe_cmov_reg );
7905 %}
7907 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7908 predicate(VM_Version::supports_cmov() );
7909 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7910 ins_cost(200);
7911 expand %{
7912 cmovI_regU(cop, cr, dst, src);
7913 %}
7914 %}
7916 // Conditional move
7917 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7918 predicate(VM_Version::supports_cmov() );
7919 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7920 ins_cost(250);
7921 format %{ "CMOV$cop $dst,$src" %}
7922 opcode(0x0F,0x40);
7923 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7924 ins_pipe( pipe_cmov_mem );
7925 %}
7927 // Conditional move
7928 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7929 predicate(VM_Version::supports_cmov() );
7930 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7931 ins_cost(250);
7932 format %{ "CMOV$cop $dst,$src" %}
7933 opcode(0x0F,0x40);
7934 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7935 ins_pipe( pipe_cmov_mem );
7936 %}
7938 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7939 predicate(VM_Version::supports_cmov() );
7940 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7941 ins_cost(250);
7942 expand %{
7943 cmovI_memU(cop, cr, dst, src);
7944 %}
7945 %}
7947 // Conditional move
7948 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7949 predicate(VM_Version::supports_cmov() );
7950 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7951 ins_cost(200);
7952 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7953 opcode(0x0F,0x40);
7954 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7955 ins_pipe( pipe_cmov_reg );
7956 %}
7958 // Conditional move (non-P6 version)
7959 // Note: a CMoveP is generated for stubs and native wrappers
7960 // regardless of whether we are on a P6, so we
7961 // emulate a cmov here
7962 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7963 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7964 ins_cost(300);
7965 format %{ "Jn$cop skip\n\t"
7966 "MOV $dst,$src\t# pointer\n"
7967 "skip:" %}
7968 opcode(0x8b);
7969 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7970 ins_pipe( pipe_cmov_reg );
7971 %}
7973 // Conditional move
7974 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7975 predicate(VM_Version::supports_cmov() );
7976 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7977 ins_cost(200);
7978 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7979 opcode(0x0F,0x40);
7980 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7981 ins_pipe( pipe_cmov_reg );
7982 %}
7984 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7985 predicate(VM_Version::supports_cmov() );
7986 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7987 ins_cost(200);
7988 expand %{
7989 cmovP_regU(cop, cr, dst, src);
7990 %}
7991 %}
7993 // DISABLED: Requires the ADLC to emit a bottom_type call that
7994 // correctly meets the two pointer arguments; one is an incoming
7995 // register but the other is a memory operand. ALSO appears to
7996 // be buggy with implicit null checks.
7997 //
7998 //// Conditional move
7999 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
8000 // predicate(VM_Version::supports_cmov() );
8001 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8002 // ins_cost(250);
8003 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8004 // opcode(0x0F,0x40);
8005 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8006 // ins_pipe( pipe_cmov_mem );
8007 //%}
8008 //
8009 //// Conditional move
8010 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
8011 // predicate(VM_Version::supports_cmov() );
8012 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
8013 // ins_cost(250);
8014 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
8015 // opcode(0x0F,0x40);
8016 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
8017 // ins_pipe( pipe_cmov_mem );
8018 //%}
8020 // Conditional move
8021 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
8022 predicate(UseSSE<=1);
8023 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8024 ins_cost(200);
8025 format %{ "FCMOV$cop $dst,$src\t# double" %}
8026 opcode(0xDA);
8027 ins_encode( enc_cmov_d(cop,src) );
8028 ins_pipe( pipe_cmovD_reg );
8029 %}
8031 // Conditional move
8032 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
8033 predicate(UseSSE==0);
8034 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8035 ins_cost(200);
8036 format %{ "FCMOV$cop $dst,$src\t# float" %}
8037 opcode(0xDA);
8038 ins_encode( enc_cmov_d(cop,src) );
8039 ins_pipe( pipe_cmovD_reg );
8040 %}
8042 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8043 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
8044 predicate(UseSSE<=1);
8045 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8046 ins_cost(200);
8047 format %{ "Jn$cop skip\n\t"
8048 "MOV $dst,$src\t# double\n"
8049 "skip:" %}
8050 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8051 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
8052 ins_pipe( pipe_cmovD_reg );
8053 %}
8055 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
8056 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
8057 predicate(UseSSE==0);
8058 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8059 ins_cost(200);
8060 format %{ "Jn$cop skip\n\t"
8061 "MOV $dst,$src\t# float\n"
8062 "skip:" %}
8063 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
8064 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
8065 ins_pipe( pipe_cmovD_reg );
8066 %}
8068 // No CMOVE with SSE/SSE2
8069 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
8070 predicate (UseSSE>=1);
8071 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8072 ins_cost(200);
8073 format %{ "Jn$cop skip\n\t"
8074 "MOVSS $dst,$src\t# float\n"
8075 "skip:" %}
8076 ins_encode %{
8077 Label skip;
8078 // Invert sense of branch from sense of CMOV
8079 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8080 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8081 __ bind(skip);
8082 %}
8083 ins_pipe( pipe_slow );
8084 %}
8086 // No CMOVE with SSE/SSE2
8087 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
8088 predicate (UseSSE>=2);
8089 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8090 ins_cost(200);
8091 format %{ "Jn$cop skip\n\t"
8092 "MOVSD $dst,$src\t# float\n"
8093 "skip:" %}
8094 ins_encode %{
8095 Label skip;
8096 // Invert sense of branch from sense of CMOV
8097 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8098 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8099 __ bind(skip);
8100 %}
8101 ins_pipe( pipe_slow );
8102 %}
8104 // unsigned version
8105 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
8106 predicate (UseSSE>=1);
8107 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8108 ins_cost(200);
8109 format %{ "Jn$cop skip\n\t"
8110 "MOVSS $dst,$src\t# float\n"
8111 "skip:" %}
8112 ins_encode %{
8113 Label skip;
8114 // Invert sense of branch from sense of CMOV
8115 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8116 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
8117 __ bind(skip);
8118 %}
8119 ins_pipe( pipe_slow );
8120 %}
8122 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
8123 predicate (UseSSE>=1);
8124 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
8125 ins_cost(200);
8126 expand %{
8127 fcmovX_regU(cop, cr, dst, src);
8128 %}
8129 %}
8131 // unsigned version
8132 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
8133 predicate (UseSSE>=2);
8134 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8135 ins_cost(200);
8136 format %{ "Jn$cop skip\n\t"
8137 "MOVSD $dst,$src\t# float\n"
8138 "skip:" %}
8139 ins_encode %{
8140 Label skip;
8141 // Invert sense of branch from sense of CMOV
8142 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
8143 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
8144 __ bind(skip);
8145 %}
8146 ins_pipe( pipe_slow );
8147 %}
8149 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
8150 predicate (UseSSE>=2);
8151 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
8152 ins_cost(200);
8153 expand %{
8154 fcmovXD_regU(cop, cr, dst, src);
8155 %}
8156 %}
8158 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
8159 predicate(VM_Version::supports_cmov() );
8160 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8161 ins_cost(200);
8162 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8163 "CMOV$cop $dst.hi,$src.hi" %}
8164 opcode(0x0F,0x40);
8165 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8166 ins_pipe( pipe_cmov_reg_long );
8167 %}
8169 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
8170 predicate(VM_Version::supports_cmov() );
8171 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8172 ins_cost(200);
8173 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
8174 "CMOV$cop $dst.hi,$src.hi" %}
8175 opcode(0x0F,0x40);
8176 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
8177 ins_pipe( pipe_cmov_reg_long );
8178 %}
8180 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
8181 predicate(VM_Version::supports_cmov() );
8182 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
8183 ins_cost(200);
8184 expand %{
8185 cmovL_regU(cop, cr, dst, src);
8186 %}
8187 %}
8189 //----------Arithmetic Instructions--------------------------------------------
8190 //----------Addition Instructions----------------------------------------------
8191 // Integer Addition Instructions
8192 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8193 match(Set dst (AddI dst src));
8194 effect(KILL cr);
8196 size(2);
8197 format %{ "ADD $dst,$src" %}
8198 opcode(0x03);
8199 ins_encode( OpcP, RegReg( dst, src) );
8200 ins_pipe( ialu_reg_reg );
8201 %}
8203 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8204 match(Set dst (AddI dst src));
8205 effect(KILL cr);
8207 format %{ "ADD $dst,$src" %}
8208 opcode(0x81, 0x00); /* /0 id */
8209 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8210 ins_pipe( ialu_reg );
8211 %}
8213 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
8214 predicate(UseIncDec);
8215 match(Set dst (AddI dst src));
8216 effect(KILL cr);
8218 size(1);
8219 format %{ "INC $dst" %}
8220 opcode(0x40); /* */
8221 ins_encode( Opc_plus( primary, dst ) );
8222 ins_pipe( ialu_reg );
8223 %}
8225 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8226 match(Set dst (AddI src0 src1));
8227 ins_cost(110);
8229 format %{ "LEA $dst,[$src0 + $src1]" %}
8230 opcode(0x8D); /* 0x8D /r */
8231 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8232 ins_pipe( ialu_reg_reg );
8233 %}
8235 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8236 match(Set dst (AddP src0 src1));
8237 ins_cost(110);
8239 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8240 opcode(0x8D); /* 0x8D /r */
8241 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8242 ins_pipe( ialu_reg_reg );
8243 %}
8245 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8246 predicate(UseIncDec);
8247 match(Set dst (AddI dst src));
8248 effect(KILL cr);
8250 size(1);
8251 format %{ "DEC $dst" %}
8252 opcode(0x48); /* */
8253 ins_encode( Opc_plus( primary, dst ) );
8254 ins_pipe( ialu_reg );
8255 %}
8257 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8258 match(Set dst (AddP dst src));
8259 effect(KILL cr);
8261 size(2);
8262 format %{ "ADD $dst,$src" %}
8263 opcode(0x03);
8264 ins_encode( OpcP, RegReg( dst, src) );
8265 ins_pipe( ialu_reg_reg );
8266 %}
8268 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8269 match(Set dst (AddP dst src));
8270 effect(KILL cr);
8272 format %{ "ADD $dst,$src" %}
8273 opcode(0x81,0x00); /* Opcode 81 /0 id */
8274 // ins_encode( RegImm( dst, src) );
8275 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8276 ins_pipe( ialu_reg );
8277 %}
8279 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8280 match(Set dst (AddI dst (LoadI src)));
8281 effect(KILL cr);
8283 ins_cost(125);
8284 format %{ "ADD $dst,$src" %}
8285 opcode(0x03);
8286 ins_encode( OpcP, RegMem( dst, src) );
8287 ins_pipe( ialu_reg_mem );
8288 %}
8290 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8291 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8292 effect(KILL cr);
8294 ins_cost(150);
8295 format %{ "ADD $dst,$src" %}
8296 opcode(0x01); /* Opcode 01 /r */
8297 ins_encode( OpcP, RegMem( src, dst ) );
8298 ins_pipe( ialu_mem_reg );
8299 %}
8301 // Add Memory with Immediate
8302 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8303 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8304 effect(KILL cr);
8306 ins_cost(125);
8307 format %{ "ADD $dst,$src" %}
8308 opcode(0x81); /* Opcode 81 /0 id */
8309 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8310 ins_pipe( ialu_mem_imm );
8311 %}
8313 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8314 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8315 effect(KILL cr);
8317 ins_cost(125);
8318 format %{ "INC $dst" %}
8319 opcode(0xFF); /* Opcode FF /0 */
8320 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8321 ins_pipe( ialu_mem_imm );
8322 %}
8324 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8325 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8326 effect(KILL cr);
8328 ins_cost(125);
8329 format %{ "DEC $dst" %}
8330 opcode(0xFF); /* Opcode FF /1 */
8331 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8332 ins_pipe( ialu_mem_imm );
8333 %}
8336 instruct checkCastPP( eRegP dst ) %{
8337 match(Set dst (CheckCastPP dst));
8339 size(0);
8340 format %{ "#checkcastPP of $dst" %}
8341 ins_encode( /*empty encoding*/ );
8342 ins_pipe( empty );
8343 %}
8345 instruct castPP( eRegP dst ) %{
8346 match(Set dst (CastPP dst));
8347 format %{ "#castPP of $dst" %}
8348 ins_encode( /*empty encoding*/ );
8349 ins_pipe( empty );
8350 %}
8352 instruct castII( eRegI dst ) %{
8353 match(Set dst (CastII dst));
8354 format %{ "#castII of $dst" %}
8355 ins_encode( /*empty encoding*/ );
8356 ins_cost(0);
8357 ins_pipe( empty );
8358 %}
8361 // Load-locked - same as a regular pointer load when used with compare-swap
8362 instruct loadPLocked(eRegP dst, memory mem) %{
8363 match(Set dst (LoadPLocked mem));
8365 ins_cost(125);
8366 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8367 opcode(0x8B);
8368 ins_encode( OpcP, RegMem(dst,mem));
8369 ins_pipe( ialu_reg_mem );
8370 %}
8372 // LoadLong-locked - same as a volatile long load when used with compare-swap
8373 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8374 predicate(UseSSE<=1);
8375 match(Set dst (LoadLLocked mem));
8377 ins_cost(200);
8378 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8379 "FISTp $dst" %}
8380 ins_encode(enc_loadL_volatile(mem,dst));
8381 ins_pipe( fpu_reg_mem );
8382 %}
8384 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8385 predicate(UseSSE>=2);
8386 match(Set dst (LoadLLocked mem));
8387 effect(TEMP tmp);
8388 ins_cost(180);
8389 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8390 "MOVSD $dst,$tmp" %}
8391 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8392 ins_pipe( pipe_slow );
8393 %}
8395 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8396 predicate(UseSSE>=2);
8397 match(Set dst (LoadLLocked mem));
8398 effect(TEMP tmp);
8399 ins_cost(160);
8400 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8401 "MOVD $dst.lo,$tmp\n\t"
8402 "PSRLQ $tmp,32\n\t"
8403 "MOVD $dst.hi,$tmp" %}
8404 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8405 ins_pipe( pipe_slow );
8406 %}
8408 // Conditional-store of the updated heap-top.
8409 // Used during allocation of the shared heap.
8410 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8411 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8412 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8413 // EAX is killed if there is contention, but then it's also unused.
8414 // In the common case of no contention, EAX holds the new oop address.
8415 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8416 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8417 ins_pipe( pipe_cmpxchg );
8418 %}
8420 // Conditional-store of an int value.
8421 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8422 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8423 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8424 effect(KILL oldval);
8425 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8426 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8427 ins_pipe( pipe_cmpxchg );
8428 %}
8430 // Conditional-store of a long value.
8431 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8432 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8433 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8434 effect(KILL oldval);
8435 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8436 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8437 "XCHG EBX,ECX"
8438 %}
8439 ins_encode %{
8440 // Note: we need to swap rbx, and rcx before and after the
8441 // cmpxchg8 instruction because the instruction uses
8442 // rcx as the high order word of the new value to store but
8443 // our register encoding uses rbx.
8444 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8445 if( os::is_MP() )
8446 __ lock();
8447 __ cmpxchg8($mem$$Address);
8448 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8449 %}
8450 ins_pipe( pipe_cmpxchg );
8451 %}
8453 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8455 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8456 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8457 effect(KILL cr, KILL oldval);
8458 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8459 "MOV $res,0\n\t"
8460 "JNE,s fail\n\t"
8461 "MOV $res,1\n"
8462 "fail:" %}
8463 ins_encode( enc_cmpxchg8(mem_ptr),
8464 enc_flags_ne_to_boolean(res) );
8465 ins_pipe( pipe_cmpxchg );
8466 %}
8468 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8469 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8470 effect(KILL cr, KILL oldval);
8471 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8472 "MOV $res,0\n\t"
8473 "JNE,s fail\n\t"
8474 "MOV $res,1\n"
8475 "fail:" %}
8476 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8477 ins_pipe( pipe_cmpxchg );
8478 %}
8480 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8481 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8482 effect(KILL cr, KILL oldval);
8483 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8484 "MOV $res,0\n\t"
8485 "JNE,s fail\n\t"
8486 "MOV $res,1\n"
8487 "fail:" %}
8488 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8489 ins_pipe( pipe_cmpxchg );
8490 %}
8492 //----------Subtraction Instructions-------------------------------------------
8493 // Integer Subtraction Instructions
8494 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8495 match(Set dst (SubI dst src));
8496 effect(KILL cr);
8498 size(2);
8499 format %{ "SUB $dst,$src" %}
8500 opcode(0x2B);
8501 ins_encode( OpcP, RegReg( dst, src) );
8502 ins_pipe( ialu_reg_reg );
8503 %}
8505 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8506 match(Set dst (SubI dst src));
8507 effect(KILL cr);
8509 format %{ "SUB $dst,$src" %}
8510 opcode(0x81,0x05); /* Opcode 81 /5 */
8511 // ins_encode( RegImm( dst, src) );
8512 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8513 ins_pipe( ialu_reg );
8514 %}
8516 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8517 match(Set dst (SubI dst (LoadI src)));
8518 effect(KILL cr);
8520 ins_cost(125);
8521 format %{ "SUB $dst,$src" %}
8522 opcode(0x2B);
8523 ins_encode( OpcP, RegMem( dst, src) );
8524 ins_pipe( ialu_reg_mem );
8525 %}
8527 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8528 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8529 effect(KILL cr);
8531 ins_cost(150);
8532 format %{ "SUB $dst,$src" %}
8533 opcode(0x29); /* Opcode 29 /r */
8534 ins_encode( OpcP, RegMem( src, dst ) );
8535 ins_pipe( ialu_mem_reg );
8536 %}
8538 // Subtract from a pointer
8539 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8540 match(Set dst (AddP dst (SubI zero src)));
8541 effect(KILL cr);
8543 size(2);
8544 format %{ "SUB $dst,$src" %}
8545 opcode(0x2B);
8546 ins_encode( OpcP, RegReg( dst, src) );
8547 ins_pipe( ialu_reg_reg );
8548 %}
8550 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8551 match(Set dst (SubI zero dst));
8552 effect(KILL cr);
8554 size(2);
8555 format %{ "NEG $dst" %}
8556 opcode(0xF7,0x03); // Opcode F7 /3
8557 ins_encode( OpcP, RegOpc( dst ) );
8558 ins_pipe( ialu_reg );
8559 %}
8562 //----------Multiplication/Division Instructions-------------------------------
8563 // Integer Multiplication Instructions
8564 // Multiply Register
8565 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8566 match(Set dst (MulI dst src));
8567 effect(KILL cr);
8569 size(3);
8570 ins_cost(300);
8571 format %{ "IMUL $dst,$src" %}
8572 opcode(0xAF, 0x0F);
8573 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8574 ins_pipe( ialu_reg_reg_alu0 );
8575 %}
8577 // Multiply 32-bit Immediate
8578 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8579 match(Set dst (MulI src imm));
8580 effect(KILL cr);
8582 ins_cost(300);
8583 format %{ "IMUL $dst,$src,$imm" %}
8584 opcode(0x69); /* 69 /r id */
8585 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8586 ins_pipe( ialu_reg_reg_alu0 );
8587 %}
8589 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8590 match(Set dst src);
8591 effect(KILL cr);
8593 // Note that this is artificially increased to make it more expensive than loadConL
8594 ins_cost(250);
8595 format %{ "MOV EAX,$src\t// low word only" %}
8596 opcode(0xB8);
8597 ins_encode( LdImmL_Lo(dst, src) );
8598 ins_pipe( ialu_reg_fat );
8599 %}
8601 // Multiply by 32-bit Immediate, taking the shifted high order results
8602 // (special case for shift by 32)
8603 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8604 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8605 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8606 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8607 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8608 effect(USE src1, KILL cr);
8610 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8611 ins_cost(0*100 + 1*400 - 150);
8612 format %{ "IMUL EDX:EAX,$src1" %}
8613 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8614 ins_pipe( pipe_slow );
8615 %}
8617 // Multiply by 32-bit Immediate, taking the shifted high order results
8618 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8619 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8620 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8621 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8622 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8623 effect(USE src1, KILL cr);
8625 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8626 ins_cost(1*100 + 1*400 - 150);
8627 format %{ "IMUL EDX:EAX,$src1\n\t"
8628 "SAR EDX,$cnt-32" %}
8629 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8630 ins_pipe( pipe_slow );
8631 %}
8633 // Multiply Memory 32-bit Immediate
8634 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8635 match(Set dst (MulI (LoadI src) imm));
8636 effect(KILL cr);
8638 ins_cost(300);
8639 format %{ "IMUL $dst,$src,$imm" %}
8640 opcode(0x69); /* 69 /r id */
8641 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8642 ins_pipe( ialu_reg_mem_alu0 );
8643 %}
8645 // Multiply Memory
8646 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8647 match(Set dst (MulI dst (LoadI src)));
8648 effect(KILL cr);
8650 ins_cost(350);
8651 format %{ "IMUL $dst,$src" %}
8652 opcode(0xAF, 0x0F);
8653 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8654 ins_pipe( ialu_reg_mem_alu0 );
8655 %}
8657 // Multiply Register Int to Long
8658 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8659 // Basic Idea: long = (long)int * (long)int
8660 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8661 effect(DEF dst, USE src, USE src1, KILL flags);
8663 ins_cost(300);
8664 format %{ "IMUL $dst,$src1" %}
8666 ins_encode( long_int_multiply( dst, src1 ) );
8667 ins_pipe( ialu_reg_reg_alu0 );
8668 %}
8670 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8671 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8672 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8673 effect(KILL flags);
8675 ins_cost(300);
8676 format %{ "MUL $dst,$src1" %}
8678 ins_encode( long_uint_multiply(dst, src1) );
8679 ins_pipe( ialu_reg_reg_alu0 );
8680 %}
8682 // Multiply Register Long
8683 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8684 match(Set dst (MulL dst src));
8685 effect(KILL cr, TEMP tmp);
8686 ins_cost(4*100+3*400);
8687 // Basic idea: lo(result) = lo(x_lo * y_lo)
8688 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8689 format %{ "MOV $tmp,$src.lo\n\t"
8690 "IMUL $tmp,EDX\n\t"
8691 "MOV EDX,$src.hi\n\t"
8692 "IMUL EDX,EAX\n\t"
8693 "ADD $tmp,EDX\n\t"
8694 "MUL EDX:EAX,$src.lo\n\t"
8695 "ADD EDX,$tmp" %}
8696 ins_encode( long_multiply( dst, src, tmp ) );
8697 ins_pipe( pipe_slow );
8698 %}
8700 // Multiply Register Long where the left operand's high 32 bits are zero
8701 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8702 predicate(is_operand_hi32_zero(n->in(1)));
8703 match(Set dst (MulL dst src));
8704 effect(KILL cr, TEMP tmp);
8705 ins_cost(2*100+2*400);
8706 // Basic idea: lo(result) = lo(x_lo * y_lo)
8707 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8708 format %{ "MOV $tmp,$src.hi\n\t"
8709 "IMUL $tmp,EAX\n\t"
8710 "MUL EDX:EAX,$src.lo\n\t"
8711 "ADD EDX,$tmp" %}
8712 ins_encode %{
8713 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8714 __ imull($tmp$$Register, rax);
8715 __ mull($src$$Register);
8716 __ addl(rdx, $tmp$$Register);
8717 %}
8718 ins_pipe( pipe_slow );
8719 %}
8721 // Multiply Register Long where the right operand's high 32 bits are zero
8722 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8723 predicate(is_operand_hi32_zero(n->in(2)));
8724 match(Set dst (MulL dst src));
8725 effect(KILL cr, TEMP tmp);
8726 ins_cost(2*100+2*400);
8727 // Basic idea: lo(result) = lo(x_lo * y_lo)
8728 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8729 format %{ "MOV $tmp,$src.lo\n\t"
8730 "IMUL $tmp,EDX\n\t"
8731 "MUL EDX:EAX,$src.lo\n\t"
8732 "ADD EDX,$tmp" %}
8733 ins_encode %{
8734 __ movl($tmp$$Register, $src$$Register);
8735 __ imull($tmp$$Register, rdx);
8736 __ mull($src$$Register);
8737 __ addl(rdx, $tmp$$Register);
8738 %}
8739 ins_pipe( pipe_slow );
8740 %}
8742 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8743 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8744 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8745 match(Set dst (MulL dst src));
8746 effect(KILL cr);
8747 ins_cost(1*400);
8748 // Basic idea: lo(result) = lo(x_lo * y_lo)
8749 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8750 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8751 ins_encode %{
8752 __ mull($src$$Register);
8753 %}
8754 ins_pipe( pipe_slow );
8755 %}
8757 // Multiply Register Long by small constant
8758 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8759 match(Set dst (MulL dst src));
8760 effect(KILL cr, TEMP tmp);
8761 ins_cost(2*100+2*400);
8762 size(12);
8763 // Basic idea: lo(result) = lo(src * EAX)
8764 // hi(result) = hi(src * EAX) + lo(src * EDX)
8765 format %{ "IMUL $tmp,EDX,$src\n\t"
8766 "MOV EDX,$src\n\t"
8767 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8768 "ADD EDX,$tmp" %}
8769 ins_encode( long_multiply_con( dst, src, tmp ) );
8770 ins_pipe( pipe_slow );
8771 %}
8773 // Integer DIV with Register
8774 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8775 match(Set rax (DivI rax div));
8776 effect(KILL rdx, KILL cr);
8777 size(26);
8778 ins_cost(30*100+10*100);
8779 format %{ "CMP EAX,0x80000000\n\t"
8780 "JNE,s normal\n\t"
8781 "XOR EDX,EDX\n\t"
8782 "CMP ECX,-1\n\t"
8783 "JE,s done\n"
8784 "normal: CDQ\n\t"
8785 "IDIV $div\n\t"
8786 "done:" %}
8787 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8788 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8789 ins_pipe( ialu_reg_reg_alu0 );
8790 %}
8792 // Divide Register Long
8793 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8794 match(Set dst (DivL src1 src2));
8795 effect( KILL cr, KILL cx, KILL bx );
8796 ins_cost(10000);
8797 format %{ "PUSH $src1.hi\n\t"
8798 "PUSH $src1.lo\n\t"
8799 "PUSH $src2.hi\n\t"
8800 "PUSH $src2.lo\n\t"
8801 "CALL SharedRuntime::ldiv\n\t"
8802 "ADD ESP,16" %}
8803 ins_encode( long_div(src1,src2) );
8804 ins_pipe( pipe_slow );
8805 %}
8807 // Integer DIVMOD with Register, both quotient and mod results
8808 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8809 match(DivModI rax div);
8810 effect(KILL cr);
8811 size(26);
8812 ins_cost(30*100+10*100);
8813 format %{ "CMP EAX,0x80000000\n\t"
8814 "JNE,s normal\n\t"
8815 "XOR EDX,EDX\n\t"
8816 "CMP ECX,-1\n\t"
8817 "JE,s done\n"
8818 "normal: CDQ\n\t"
8819 "IDIV $div\n\t"
8820 "done:" %}
8821 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8822 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8823 ins_pipe( pipe_slow );
8824 %}
8826 // Integer MOD with Register
8827 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8828 match(Set rdx (ModI rax div));
8829 effect(KILL rax, KILL cr);
8831 size(26);
8832 ins_cost(300);
8833 format %{ "CDQ\n\t"
8834 "IDIV $div" %}
8835 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8836 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8837 ins_pipe( ialu_reg_reg_alu0 );
8838 %}
8840 // Remainder Register Long
8841 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8842 match(Set dst (ModL src1 src2));
8843 effect( KILL cr, KILL cx, KILL bx );
8844 ins_cost(10000);
8845 format %{ "PUSH $src1.hi\n\t"
8846 "PUSH $src1.lo\n\t"
8847 "PUSH $src2.hi\n\t"
8848 "PUSH $src2.lo\n\t"
8849 "CALL SharedRuntime::lrem\n\t"
8850 "ADD ESP,16" %}
8851 ins_encode( long_mod(src1,src2) );
8852 ins_pipe( pipe_slow );
8853 %}
8855 // Integer Shift Instructions
8856 // Shift Left by one
8857 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8858 match(Set dst (LShiftI dst shift));
8859 effect(KILL cr);
8861 size(2);
8862 format %{ "SHL $dst,$shift" %}
8863 opcode(0xD1, 0x4); /* D1 /4 */
8864 ins_encode( OpcP, RegOpc( dst ) );
8865 ins_pipe( ialu_reg );
8866 %}
8868 // Shift Left by 8-bit immediate
8869 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8870 match(Set dst (LShiftI dst shift));
8871 effect(KILL cr);
8873 size(3);
8874 format %{ "SHL $dst,$shift" %}
8875 opcode(0xC1, 0x4); /* C1 /4 ib */
8876 ins_encode( RegOpcImm( dst, shift) );
8877 ins_pipe( ialu_reg );
8878 %}
8880 // Shift Left by variable
8881 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8882 match(Set dst (LShiftI dst shift));
8883 effect(KILL cr);
8885 size(2);
8886 format %{ "SHL $dst,$shift" %}
8887 opcode(0xD3, 0x4); /* D3 /4 */
8888 ins_encode( OpcP, RegOpc( dst ) );
8889 ins_pipe( ialu_reg_reg );
8890 %}
8892 // Arithmetic shift right by one
8893 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8894 match(Set dst (RShiftI dst shift));
8895 effect(KILL cr);
8897 size(2);
8898 format %{ "SAR $dst,$shift" %}
8899 opcode(0xD1, 0x7); /* D1 /7 */
8900 ins_encode( OpcP, RegOpc( dst ) );
8901 ins_pipe( ialu_reg );
8902 %}
8904 // Arithmetic shift right by one
8905 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8906 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8907 effect(KILL cr);
8908 format %{ "SAR $dst,$shift" %}
8909 opcode(0xD1, 0x7); /* D1 /7 */
8910 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8911 ins_pipe( ialu_mem_imm );
8912 %}
8914 // Arithmetic Shift Right by 8-bit immediate
8915 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8916 match(Set dst (RShiftI dst shift));
8917 effect(KILL cr);
8919 size(3);
8920 format %{ "SAR $dst,$shift" %}
8921 opcode(0xC1, 0x7); /* C1 /7 ib */
8922 ins_encode( RegOpcImm( dst, shift ) );
8923 ins_pipe( ialu_mem_imm );
8924 %}
8926 // Arithmetic Shift Right by 8-bit immediate
8927 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8928 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8929 effect(KILL cr);
8931 format %{ "SAR $dst,$shift" %}
8932 opcode(0xC1, 0x7); /* C1 /7 ib */
8933 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8934 ins_pipe( ialu_mem_imm );
8935 %}
8937 // Arithmetic Shift Right by variable
8938 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8939 match(Set dst (RShiftI dst shift));
8940 effect(KILL cr);
8942 size(2);
8943 format %{ "SAR $dst,$shift" %}
8944 opcode(0xD3, 0x7); /* D3 /7 */
8945 ins_encode( OpcP, RegOpc( dst ) );
8946 ins_pipe( ialu_reg_reg );
8947 %}
8949 // Logical shift right by one
8950 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8951 match(Set dst (URShiftI dst shift));
8952 effect(KILL cr);
8954 size(2);
8955 format %{ "SHR $dst,$shift" %}
8956 opcode(0xD1, 0x5); /* D1 /5 */
8957 ins_encode( OpcP, RegOpc( dst ) );
8958 ins_pipe( ialu_reg );
8959 %}
8961 // Logical Shift Right by 8-bit immediate
8962 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8963 match(Set dst (URShiftI dst shift));
8964 effect(KILL cr);
8966 size(3);
8967 format %{ "SHR $dst,$shift" %}
8968 opcode(0xC1, 0x5); /* C1 /5 ib */
8969 ins_encode( RegOpcImm( dst, shift) );
8970 ins_pipe( ialu_reg );
8971 %}
8974 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8975 // This idiom is used by the compiler for the i2b bytecode.
8976 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{
8977 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8979 size(3);
8980 format %{ "MOVSX $dst,$src :8" %}
8981 ins_encode %{
8982 __ movsbl($dst$$Register, $src$$Register);
8983 %}
8984 ins_pipe(ialu_reg_reg);
8985 %}
8987 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8988 // This idiom is used by the compiler the i2s bytecode.
8989 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{
8990 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8992 size(3);
8993 format %{ "MOVSX $dst,$src :16" %}
8994 ins_encode %{
8995 __ movswl($dst$$Register, $src$$Register);
8996 %}
8997 ins_pipe(ialu_reg_reg);
8998 %}
9001 // Logical Shift Right by variable
9002 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
9003 match(Set dst (URShiftI dst shift));
9004 effect(KILL cr);
9006 size(2);
9007 format %{ "SHR $dst,$shift" %}
9008 opcode(0xD3, 0x5); /* D3 /5 */
9009 ins_encode( OpcP, RegOpc( dst ) );
9010 ins_pipe( ialu_reg_reg );
9011 %}
9014 //----------Logical Instructions-----------------------------------------------
9015 //----------Integer Logical Instructions---------------------------------------
9016 // And Instructions
9017 // And Register with Register
9018 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9019 match(Set dst (AndI dst src));
9020 effect(KILL cr);
9022 size(2);
9023 format %{ "AND $dst,$src" %}
9024 opcode(0x23);
9025 ins_encode( OpcP, RegReg( dst, src) );
9026 ins_pipe( ialu_reg_reg );
9027 %}
9029 // And Register with Immediate
9030 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9031 match(Set dst (AndI dst src));
9032 effect(KILL cr);
9034 format %{ "AND $dst,$src" %}
9035 opcode(0x81,0x04); /* Opcode 81 /4 */
9036 // ins_encode( RegImm( dst, src) );
9037 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9038 ins_pipe( ialu_reg );
9039 %}
9041 // And Register with Memory
9042 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9043 match(Set dst (AndI dst (LoadI src)));
9044 effect(KILL cr);
9046 ins_cost(125);
9047 format %{ "AND $dst,$src" %}
9048 opcode(0x23);
9049 ins_encode( OpcP, RegMem( dst, src) );
9050 ins_pipe( ialu_reg_mem );
9051 %}
9053 // And Memory with Register
9054 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9055 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9056 effect(KILL cr);
9058 ins_cost(150);
9059 format %{ "AND $dst,$src" %}
9060 opcode(0x21); /* Opcode 21 /r */
9061 ins_encode( OpcP, RegMem( src, dst ) );
9062 ins_pipe( ialu_mem_reg );
9063 %}
9065 // And Memory with Immediate
9066 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9067 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9068 effect(KILL cr);
9070 ins_cost(125);
9071 format %{ "AND $dst,$src" %}
9072 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9073 // ins_encode( MemImm( dst, src) );
9074 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9075 ins_pipe( ialu_mem_imm );
9076 %}
9078 // Or Instructions
9079 // Or Register with Register
9080 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9081 match(Set dst (OrI dst src));
9082 effect(KILL cr);
9084 size(2);
9085 format %{ "OR $dst,$src" %}
9086 opcode(0x0B);
9087 ins_encode( OpcP, RegReg( dst, src) );
9088 ins_pipe( ialu_reg_reg );
9089 %}
9091 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
9092 match(Set dst (OrI dst (CastP2X src)));
9093 effect(KILL cr);
9095 size(2);
9096 format %{ "OR $dst,$src" %}
9097 opcode(0x0B);
9098 ins_encode( OpcP, RegReg( dst, src) );
9099 ins_pipe( ialu_reg_reg );
9100 %}
9103 // Or Register with Immediate
9104 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9105 match(Set dst (OrI dst src));
9106 effect(KILL cr);
9108 format %{ "OR $dst,$src" %}
9109 opcode(0x81,0x01); /* Opcode 81 /1 id */
9110 // ins_encode( RegImm( dst, src) );
9111 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9112 ins_pipe( ialu_reg );
9113 %}
9115 // Or Register with Memory
9116 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9117 match(Set dst (OrI dst (LoadI src)));
9118 effect(KILL cr);
9120 ins_cost(125);
9121 format %{ "OR $dst,$src" %}
9122 opcode(0x0B);
9123 ins_encode( OpcP, RegMem( dst, src) );
9124 ins_pipe( ialu_reg_mem );
9125 %}
9127 // Or Memory with Register
9128 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9129 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9130 effect(KILL cr);
9132 ins_cost(150);
9133 format %{ "OR $dst,$src" %}
9134 opcode(0x09); /* Opcode 09 /r */
9135 ins_encode( OpcP, RegMem( src, dst ) );
9136 ins_pipe( ialu_mem_reg );
9137 %}
9139 // Or Memory with Immediate
9140 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9141 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9142 effect(KILL cr);
9144 ins_cost(125);
9145 format %{ "OR $dst,$src" %}
9146 opcode(0x81,0x1); /* Opcode 81 /1 id */
9147 // ins_encode( MemImm( dst, src) );
9148 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9149 ins_pipe( ialu_mem_imm );
9150 %}
9152 // ROL/ROR
9153 // ROL expand
9154 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9155 effect(USE_DEF dst, USE shift, KILL cr);
9157 format %{ "ROL $dst, $shift" %}
9158 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9159 ins_encode( OpcP, RegOpc( dst ));
9160 ins_pipe( ialu_reg );
9161 %}
9163 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9164 effect(USE_DEF dst, USE shift, KILL cr);
9166 format %{ "ROL $dst, $shift" %}
9167 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
9168 ins_encode( RegOpcImm(dst, shift) );
9169 ins_pipe(ialu_reg);
9170 %}
9172 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
9173 effect(USE_DEF dst, USE shift, KILL cr);
9175 format %{ "ROL $dst, $shift" %}
9176 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9177 ins_encode(OpcP, RegOpc(dst));
9178 ins_pipe( ialu_reg_reg );
9179 %}
9180 // end of ROL expand
9182 // ROL 32bit by one once
9183 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
9184 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9186 expand %{
9187 rolI_eReg_imm1(dst, lshift, cr);
9188 %}
9189 %}
9191 // ROL 32bit var by imm8 once
9192 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
9193 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9194 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9196 expand %{
9197 rolI_eReg_imm8(dst, lshift, cr);
9198 %}
9199 %}
9201 // ROL 32bit var by var once
9202 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9203 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9205 expand %{
9206 rolI_eReg_CL(dst, shift, cr);
9207 %}
9208 %}
9210 // ROL 32bit var by var once
9211 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9212 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9214 expand %{
9215 rolI_eReg_CL(dst, shift, cr);
9216 %}
9217 %}
9219 // ROR expand
9220 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
9221 effect(USE_DEF dst, USE shift, KILL cr);
9223 format %{ "ROR $dst, $shift" %}
9224 opcode(0xD1,0x1); /* Opcode D1 /1 */
9225 ins_encode( OpcP, RegOpc( dst ) );
9226 ins_pipe( ialu_reg );
9227 %}
9229 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
9230 effect (USE_DEF dst, USE shift, KILL cr);
9232 format %{ "ROR $dst, $shift" %}
9233 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
9234 ins_encode( RegOpcImm(dst, shift) );
9235 ins_pipe( ialu_reg );
9236 %}
9238 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
9239 effect(USE_DEF dst, USE shift, KILL cr);
9241 format %{ "ROR $dst, $shift" %}
9242 opcode(0xD3, 0x1); /* Opcode D3 /1 */
9243 ins_encode(OpcP, RegOpc(dst));
9244 ins_pipe( ialu_reg_reg );
9245 %}
9246 // end of ROR expand
9248 // ROR right once
9249 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
9250 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9252 expand %{
9253 rorI_eReg_imm1(dst, rshift, cr);
9254 %}
9255 %}
9257 // ROR 32bit by immI8 once
9258 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
9259 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9260 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9262 expand %{
9263 rorI_eReg_imm8(dst, rshift, cr);
9264 %}
9265 %}
9267 // ROR 32bit var by var once
9268 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
9269 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9271 expand %{
9272 rorI_eReg_CL(dst, shift, cr);
9273 %}
9274 %}
9276 // ROR 32bit var by var once
9277 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9278 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9280 expand %{
9281 rorI_eReg_CL(dst, shift, cr);
9282 %}
9283 %}
9285 // Xor Instructions
9286 // Xor Register with Register
9287 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9288 match(Set dst (XorI dst src));
9289 effect(KILL cr);
9291 size(2);
9292 format %{ "XOR $dst,$src" %}
9293 opcode(0x33);
9294 ins_encode( OpcP, RegReg( dst, src) );
9295 ins_pipe( ialu_reg_reg );
9296 %}
9298 // Xor Register with Immediate -1
9299 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9300 match(Set dst (XorI dst imm));
9302 size(2);
9303 format %{ "NOT $dst" %}
9304 ins_encode %{
9305 __ notl($dst$$Register);
9306 %}
9307 ins_pipe( ialu_reg );
9308 %}
9310 // Xor Register with Immediate
9311 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9312 match(Set dst (XorI dst src));
9313 effect(KILL cr);
9315 format %{ "XOR $dst,$src" %}
9316 opcode(0x81,0x06); /* Opcode 81 /6 id */
9317 // ins_encode( RegImm( dst, src) );
9318 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9319 ins_pipe( ialu_reg );
9320 %}
9322 // Xor Register with Memory
9323 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9324 match(Set dst (XorI dst (LoadI src)));
9325 effect(KILL cr);
9327 ins_cost(125);
9328 format %{ "XOR $dst,$src" %}
9329 opcode(0x33);
9330 ins_encode( OpcP, RegMem(dst, src) );
9331 ins_pipe( ialu_reg_mem );
9332 %}
9334 // Xor Memory with Register
9335 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9336 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9337 effect(KILL cr);
9339 ins_cost(150);
9340 format %{ "XOR $dst,$src" %}
9341 opcode(0x31); /* Opcode 31 /r */
9342 ins_encode( OpcP, RegMem( src, dst ) );
9343 ins_pipe( ialu_mem_reg );
9344 %}
9346 // Xor Memory with Immediate
9347 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9348 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9349 effect(KILL cr);
9351 ins_cost(125);
9352 format %{ "XOR $dst,$src" %}
9353 opcode(0x81,0x6); /* Opcode 81 /6 id */
9354 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9355 ins_pipe( ialu_mem_imm );
9356 %}
9358 //----------Convert Int to Boolean---------------------------------------------
9360 instruct movI_nocopy(eRegI dst, eRegI src) %{
9361 effect( DEF dst, USE src );
9362 format %{ "MOV $dst,$src" %}
9363 ins_encode( enc_Copy( dst, src) );
9364 ins_pipe( ialu_reg_reg );
9365 %}
9367 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9368 effect( USE_DEF dst, USE src, KILL cr );
9370 size(4);
9371 format %{ "NEG $dst\n\t"
9372 "ADC $dst,$src" %}
9373 ins_encode( neg_reg(dst),
9374 OpcRegReg(0x13,dst,src) );
9375 ins_pipe( ialu_reg_reg_long );
9376 %}
9378 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9379 match(Set dst (Conv2B src));
9381 expand %{
9382 movI_nocopy(dst,src);
9383 ci2b(dst,src,cr);
9384 %}
9385 %}
9387 instruct movP_nocopy(eRegI dst, eRegP src) %{
9388 effect( DEF dst, USE src );
9389 format %{ "MOV $dst,$src" %}
9390 ins_encode( enc_Copy( dst, src) );
9391 ins_pipe( ialu_reg_reg );
9392 %}
9394 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9395 effect( USE_DEF dst, USE src, KILL cr );
9396 format %{ "NEG $dst\n\t"
9397 "ADC $dst,$src" %}
9398 ins_encode( neg_reg(dst),
9399 OpcRegReg(0x13,dst,src) );
9400 ins_pipe( ialu_reg_reg_long );
9401 %}
9403 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9404 match(Set dst (Conv2B src));
9406 expand %{
9407 movP_nocopy(dst,src);
9408 cp2b(dst,src,cr);
9409 %}
9410 %}
9412 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9413 match(Set dst (CmpLTMask p q));
9414 effect( KILL cr );
9415 ins_cost(400);
9417 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9418 format %{ "XOR $dst,$dst\n\t"
9419 "CMP $p,$q\n\t"
9420 "SETlt $dst\n\t"
9421 "NEG $dst" %}
9422 ins_encode( OpcRegReg(0x33,dst,dst),
9423 OpcRegReg(0x3B,p,q),
9424 setLT_reg(dst), neg_reg(dst) );
9425 ins_pipe( pipe_slow );
9426 %}
9428 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9429 match(Set dst (CmpLTMask dst zero));
9430 effect( DEF dst, KILL cr );
9431 ins_cost(100);
9433 format %{ "SAR $dst,31" %}
9434 opcode(0xC1, 0x7); /* C1 /7 ib */
9435 ins_encode( RegOpcImm( dst, 0x1F ) );
9436 ins_pipe( ialu_reg );
9437 %}
9440 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9441 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9442 effect( KILL tmp, KILL cr );
9443 ins_cost(400);
9444 // annoyingly, $tmp has no edges so you cant ask for it in
9445 // any format or encoding
9446 format %{ "SUB $p,$q\n\t"
9447 "SBB ECX,ECX\n\t"
9448 "AND ECX,$y\n\t"
9449 "ADD $p,ECX" %}
9450 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9451 ins_pipe( pipe_cmplt );
9452 %}
9454 /* If I enable this, I encourage spilling in the inner loop of compress.
9455 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9456 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9457 effect( USE_KILL tmp, KILL cr );
9458 ins_cost(400);
9460 format %{ "SUB $p,$q\n\t"
9461 "SBB ECX,ECX\n\t"
9462 "AND ECX,$y\n\t"
9463 "ADD $p,ECX" %}
9464 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9465 %}
9466 */
9468 //----------Long Instructions------------------------------------------------
9469 // Add Long Register with Register
9470 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9471 match(Set dst (AddL dst src));
9472 effect(KILL cr);
9473 ins_cost(200);
9474 format %{ "ADD $dst.lo,$src.lo\n\t"
9475 "ADC $dst.hi,$src.hi" %}
9476 opcode(0x03, 0x13);
9477 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9478 ins_pipe( ialu_reg_reg_long );
9479 %}
9481 // Add Long Register with Immediate
9482 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9483 match(Set dst (AddL dst src));
9484 effect(KILL cr);
9485 format %{ "ADD $dst.lo,$src.lo\n\t"
9486 "ADC $dst.hi,$src.hi" %}
9487 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9488 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9489 ins_pipe( ialu_reg_long );
9490 %}
9492 // Add Long Register with Memory
9493 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9494 match(Set dst (AddL dst (LoadL mem)));
9495 effect(KILL cr);
9496 ins_cost(125);
9497 format %{ "ADD $dst.lo,$mem\n\t"
9498 "ADC $dst.hi,$mem+4" %}
9499 opcode(0x03, 0x13);
9500 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9501 ins_pipe( ialu_reg_long_mem );
9502 %}
9504 // Subtract Long Register with Register.
9505 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9506 match(Set dst (SubL dst src));
9507 effect(KILL cr);
9508 ins_cost(200);
9509 format %{ "SUB $dst.lo,$src.lo\n\t"
9510 "SBB $dst.hi,$src.hi" %}
9511 opcode(0x2B, 0x1B);
9512 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9513 ins_pipe( ialu_reg_reg_long );
9514 %}
9516 // Subtract Long Register with Immediate
9517 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9518 match(Set dst (SubL dst src));
9519 effect(KILL cr);
9520 format %{ "SUB $dst.lo,$src.lo\n\t"
9521 "SBB $dst.hi,$src.hi" %}
9522 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9523 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9524 ins_pipe( ialu_reg_long );
9525 %}
9527 // Subtract Long Register with Memory
9528 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9529 match(Set dst (SubL dst (LoadL mem)));
9530 effect(KILL cr);
9531 ins_cost(125);
9532 format %{ "SUB $dst.lo,$mem\n\t"
9533 "SBB $dst.hi,$mem+4" %}
9534 opcode(0x2B, 0x1B);
9535 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9536 ins_pipe( ialu_reg_long_mem );
9537 %}
9539 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9540 match(Set dst (SubL zero dst));
9541 effect(KILL cr);
9542 ins_cost(300);
9543 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9544 ins_encode( neg_long(dst) );
9545 ins_pipe( ialu_reg_reg_long );
9546 %}
9548 // And Long Register with Register
9549 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9550 match(Set dst (AndL dst src));
9551 effect(KILL cr);
9552 format %{ "AND $dst.lo,$src.lo\n\t"
9553 "AND $dst.hi,$src.hi" %}
9554 opcode(0x23,0x23);
9555 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9556 ins_pipe( ialu_reg_reg_long );
9557 %}
9559 // And Long Register with Immediate
9560 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9561 match(Set dst (AndL dst src));
9562 effect(KILL cr);
9563 format %{ "AND $dst.lo,$src.lo\n\t"
9564 "AND $dst.hi,$src.hi" %}
9565 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9566 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9567 ins_pipe( ialu_reg_long );
9568 %}
9570 // And Long Register with Memory
9571 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9572 match(Set dst (AndL dst (LoadL mem)));
9573 effect(KILL cr);
9574 ins_cost(125);
9575 format %{ "AND $dst.lo,$mem\n\t"
9576 "AND $dst.hi,$mem+4" %}
9577 opcode(0x23, 0x23);
9578 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9579 ins_pipe( ialu_reg_long_mem );
9580 %}
9582 // Or Long Register with Register
9583 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9584 match(Set dst (OrL dst src));
9585 effect(KILL cr);
9586 format %{ "OR $dst.lo,$src.lo\n\t"
9587 "OR $dst.hi,$src.hi" %}
9588 opcode(0x0B,0x0B);
9589 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9590 ins_pipe( ialu_reg_reg_long );
9591 %}
9593 // Or Long Register with Immediate
9594 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9595 match(Set dst (OrL dst src));
9596 effect(KILL cr);
9597 format %{ "OR $dst.lo,$src.lo\n\t"
9598 "OR $dst.hi,$src.hi" %}
9599 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9600 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9601 ins_pipe( ialu_reg_long );
9602 %}
9604 // Or Long Register with Memory
9605 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9606 match(Set dst (OrL dst (LoadL mem)));
9607 effect(KILL cr);
9608 ins_cost(125);
9609 format %{ "OR $dst.lo,$mem\n\t"
9610 "OR $dst.hi,$mem+4" %}
9611 opcode(0x0B,0x0B);
9612 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9613 ins_pipe( ialu_reg_long_mem );
9614 %}
9616 // Xor Long Register with Register
9617 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9618 match(Set dst (XorL dst src));
9619 effect(KILL cr);
9620 format %{ "XOR $dst.lo,$src.lo\n\t"
9621 "XOR $dst.hi,$src.hi" %}
9622 opcode(0x33,0x33);
9623 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9624 ins_pipe( ialu_reg_reg_long );
9625 %}
9627 // Xor Long Register with Immediate -1
9628 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9629 match(Set dst (XorL dst imm));
9630 format %{ "NOT $dst.lo\n\t"
9631 "NOT $dst.hi" %}
9632 ins_encode %{
9633 __ notl($dst$$Register);
9634 __ notl(HIGH_FROM_LOW($dst$$Register));
9635 %}
9636 ins_pipe( ialu_reg_long );
9637 %}
9639 // Xor Long Register with Immediate
9640 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9641 match(Set dst (XorL dst src));
9642 effect(KILL cr);
9643 format %{ "XOR $dst.lo,$src.lo\n\t"
9644 "XOR $dst.hi,$src.hi" %}
9645 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9646 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9647 ins_pipe( ialu_reg_long );
9648 %}
9650 // Xor Long Register with Memory
9651 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9652 match(Set dst (XorL dst (LoadL mem)));
9653 effect(KILL cr);
9654 ins_cost(125);
9655 format %{ "XOR $dst.lo,$mem\n\t"
9656 "XOR $dst.hi,$mem+4" %}
9657 opcode(0x33,0x33);
9658 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9659 ins_pipe( ialu_reg_long_mem );
9660 %}
9662 // Shift Left Long by 1
9663 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9664 predicate(UseNewLongLShift);
9665 match(Set dst (LShiftL dst cnt));
9666 effect(KILL cr);
9667 ins_cost(100);
9668 format %{ "ADD $dst.lo,$dst.lo\n\t"
9669 "ADC $dst.hi,$dst.hi" %}
9670 ins_encode %{
9671 __ addl($dst$$Register,$dst$$Register);
9672 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9673 %}
9674 ins_pipe( ialu_reg_long );
9675 %}
9677 // Shift Left Long by 2
9678 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9679 predicate(UseNewLongLShift);
9680 match(Set dst (LShiftL dst cnt));
9681 effect(KILL cr);
9682 ins_cost(100);
9683 format %{ "ADD $dst.lo,$dst.lo\n\t"
9684 "ADC $dst.hi,$dst.hi\n\t"
9685 "ADD $dst.lo,$dst.lo\n\t"
9686 "ADC $dst.hi,$dst.hi" %}
9687 ins_encode %{
9688 __ addl($dst$$Register,$dst$$Register);
9689 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9690 __ addl($dst$$Register,$dst$$Register);
9691 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9692 %}
9693 ins_pipe( ialu_reg_long );
9694 %}
9696 // Shift Left Long by 3
9697 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9698 predicate(UseNewLongLShift);
9699 match(Set dst (LShiftL dst cnt));
9700 effect(KILL cr);
9701 ins_cost(100);
9702 format %{ "ADD $dst.lo,$dst.lo\n\t"
9703 "ADC $dst.hi,$dst.hi\n\t"
9704 "ADD $dst.lo,$dst.lo\n\t"
9705 "ADC $dst.hi,$dst.hi\n\t"
9706 "ADD $dst.lo,$dst.lo\n\t"
9707 "ADC $dst.hi,$dst.hi" %}
9708 ins_encode %{
9709 __ addl($dst$$Register,$dst$$Register);
9710 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9711 __ addl($dst$$Register,$dst$$Register);
9712 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9713 __ addl($dst$$Register,$dst$$Register);
9714 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9715 %}
9716 ins_pipe( ialu_reg_long );
9717 %}
9719 // Shift Left Long by 1-31
9720 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9721 match(Set dst (LShiftL dst cnt));
9722 effect(KILL cr);
9723 ins_cost(200);
9724 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9725 "SHL $dst.lo,$cnt" %}
9726 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9727 ins_encode( move_long_small_shift(dst,cnt) );
9728 ins_pipe( ialu_reg_long );
9729 %}
9731 // Shift Left Long by 32-63
9732 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9733 match(Set dst (LShiftL dst cnt));
9734 effect(KILL cr);
9735 ins_cost(300);
9736 format %{ "MOV $dst.hi,$dst.lo\n"
9737 "\tSHL $dst.hi,$cnt-32\n"
9738 "\tXOR $dst.lo,$dst.lo" %}
9739 opcode(0xC1, 0x4); /* C1 /4 ib */
9740 ins_encode( move_long_big_shift_clr(dst,cnt) );
9741 ins_pipe( ialu_reg_long );
9742 %}
9744 // Shift Left Long by variable
9745 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9746 match(Set dst (LShiftL dst shift));
9747 effect(KILL cr);
9748 ins_cost(500+200);
9749 size(17);
9750 format %{ "TEST $shift,32\n\t"
9751 "JEQ,s small\n\t"
9752 "MOV $dst.hi,$dst.lo\n\t"
9753 "XOR $dst.lo,$dst.lo\n"
9754 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9755 "SHL $dst.lo,$shift" %}
9756 ins_encode( shift_left_long( dst, shift ) );
9757 ins_pipe( pipe_slow );
9758 %}
9760 // Shift Right Long by 1-31
9761 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9762 match(Set dst (URShiftL dst cnt));
9763 effect(KILL cr);
9764 ins_cost(200);
9765 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9766 "SHR $dst.hi,$cnt" %}
9767 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9768 ins_encode( move_long_small_shift(dst,cnt) );
9769 ins_pipe( ialu_reg_long );
9770 %}
9772 // Shift Right Long by 32-63
9773 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9774 match(Set dst (URShiftL dst cnt));
9775 effect(KILL cr);
9776 ins_cost(300);
9777 format %{ "MOV $dst.lo,$dst.hi\n"
9778 "\tSHR $dst.lo,$cnt-32\n"
9779 "\tXOR $dst.hi,$dst.hi" %}
9780 opcode(0xC1, 0x5); /* C1 /5 ib */
9781 ins_encode( move_long_big_shift_clr(dst,cnt) );
9782 ins_pipe( ialu_reg_long );
9783 %}
9785 // Shift Right Long by variable
9786 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9787 match(Set dst (URShiftL dst shift));
9788 effect(KILL cr);
9789 ins_cost(600);
9790 size(17);
9791 format %{ "TEST $shift,32\n\t"
9792 "JEQ,s small\n\t"
9793 "MOV $dst.lo,$dst.hi\n\t"
9794 "XOR $dst.hi,$dst.hi\n"
9795 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9796 "SHR $dst.hi,$shift" %}
9797 ins_encode( shift_right_long( dst, shift ) );
9798 ins_pipe( pipe_slow );
9799 %}
9801 // Shift Right Long by 1-31
9802 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9803 match(Set dst (RShiftL dst cnt));
9804 effect(KILL cr);
9805 ins_cost(200);
9806 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9807 "SAR $dst.hi,$cnt" %}
9808 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9809 ins_encode( move_long_small_shift(dst,cnt) );
9810 ins_pipe( ialu_reg_long );
9811 %}
9813 // Shift Right Long by 32-63
9814 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9815 match(Set dst (RShiftL dst cnt));
9816 effect(KILL cr);
9817 ins_cost(300);
9818 format %{ "MOV $dst.lo,$dst.hi\n"
9819 "\tSAR $dst.lo,$cnt-32\n"
9820 "\tSAR $dst.hi,31" %}
9821 opcode(0xC1, 0x7); /* C1 /7 ib */
9822 ins_encode( move_long_big_shift_sign(dst,cnt) );
9823 ins_pipe( ialu_reg_long );
9824 %}
9826 // Shift Right arithmetic Long by variable
9827 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9828 match(Set dst (RShiftL dst shift));
9829 effect(KILL cr);
9830 ins_cost(600);
9831 size(18);
9832 format %{ "TEST $shift,32\n\t"
9833 "JEQ,s small\n\t"
9834 "MOV $dst.lo,$dst.hi\n\t"
9835 "SAR $dst.hi,31\n"
9836 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9837 "SAR $dst.hi,$shift" %}
9838 ins_encode( shift_right_arith_long( dst, shift ) );
9839 ins_pipe( pipe_slow );
9840 %}
9843 //----------Double Instructions------------------------------------------------
9844 // Double Math
9846 // Compare & branch
9848 // P6 version of float compare, sets condition codes in EFLAGS
9849 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9850 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9851 match(Set cr (CmpD src1 src2));
9852 effect(KILL rax);
9853 ins_cost(150);
9854 format %{ "FLD $src1\n\t"
9855 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9856 "JNP exit\n\t"
9857 "MOV ah,1 // saw a NaN, set CF\n\t"
9858 "SAHF\n"
9859 "exit:\tNOP // avoid branch to branch" %}
9860 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9861 ins_encode( Push_Reg_D(src1),
9862 OpcP, RegOpc(src2),
9863 cmpF_P6_fixup );
9864 ins_pipe( pipe_slow );
9865 %}
9867 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9868 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9869 match(Set cr (CmpD src1 src2));
9870 ins_cost(150);
9871 format %{ "FLD $src1\n\t"
9872 "FUCOMIP ST,$src2 // P6 instruction" %}
9873 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9874 ins_encode( Push_Reg_D(src1),
9875 OpcP, RegOpc(src2));
9876 ins_pipe( pipe_slow );
9877 %}
9879 // Compare & branch
9880 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9881 predicate(UseSSE<=1);
9882 match(Set cr (CmpD src1 src2));
9883 effect(KILL rax);
9884 ins_cost(200);
9885 format %{ "FLD $src1\n\t"
9886 "FCOMp $src2\n\t"
9887 "FNSTSW AX\n\t"
9888 "TEST AX,0x400\n\t"
9889 "JZ,s flags\n\t"
9890 "MOV AH,1\t# unordered treat as LT\n"
9891 "flags:\tSAHF" %}
9892 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9893 ins_encode( Push_Reg_D(src1),
9894 OpcP, RegOpc(src2),
9895 fpu_flags);
9896 ins_pipe( pipe_slow );
9897 %}
9899 // Compare vs zero into -1,0,1
9900 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9901 predicate(UseSSE<=1);
9902 match(Set dst (CmpD3 src1 zero));
9903 effect(KILL cr, KILL rax);
9904 ins_cost(280);
9905 format %{ "FTSTD $dst,$src1" %}
9906 opcode(0xE4, 0xD9);
9907 ins_encode( Push_Reg_D(src1),
9908 OpcS, OpcP, PopFPU,
9909 CmpF_Result(dst));
9910 ins_pipe( pipe_slow );
9911 %}
9913 // Compare into -1,0,1
9914 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9915 predicate(UseSSE<=1);
9916 match(Set dst (CmpD3 src1 src2));
9917 effect(KILL cr, KILL rax);
9918 ins_cost(300);
9919 format %{ "FCMPD $dst,$src1,$src2" %}
9920 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9921 ins_encode( Push_Reg_D(src1),
9922 OpcP, RegOpc(src2),
9923 CmpF_Result(dst));
9924 ins_pipe( pipe_slow );
9925 %}
9927 // float compare and set condition codes in EFLAGS by XMM regs
9928 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9929 predicate(UseSSE>=2);
9930 match(Set cr (CmpD dst src));
9931 effect(KILL rax);
9932 ins_cost(125);
9933 format %{ "COMISD $dst,$src\n"
9934 "\tJNP exit\n"
9935 "\tMOV ah,1 // saw a NaN, set CF\n"
9936 "\tSAHF\n"
9937 "exit:\tNOP // avoid branch to branch" %}
9938 opcode(0x66, 0x0F, 0x2F);
9939 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9940 ins_pipe( pipe_slow );
9941 %}
9943 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9944 predicate(UseSSE>=2);
9945 match(Set cr (CmpD dst src));
9946 ins_cost(100);
9947 format %{ "COMISD $dst,$src" %}
9948 opcode(0x66, 0x0F, 0x2F);
9949 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9950 ins_pipe( pipe_slow );
9951 %}
9953 // float compare and set condition codes in EFLAGS by XMM regs
9954 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9955 predicate(UseSSE>=2);
9956 match(Set cr (CmpD dst (LoadD src)));
9957 effect(KILL rax);
9958 ins_cost(145);
9959 format %{ "COMISD $dst,$src\n"
9960 "\tJNP exit\n"
9961 "\tMOV ah,1 // saw a NaN, set CF\n"
9962 "\tSAHF\n"
9963 "exit:\tNOP // avoid branch to branch" %}
9964 opcode(0x66, 0x0F, 0x2F);
9965 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9966 ins_pipe( pipe_slow );
9967 %}
9969 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9970 predicate(UseSSE>=2);
9971 match(Set cr (CmpD dst (LoadD src)));
9972 ins_cost(100);
9973 format %{ "COMISD $dst,$src" %}
9974 opcode(0x66, 0x0F, 0x2F);
9975 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9976 ins_pipe( pipe_slow );
9977 %}
9979 // Compare into -1,0,1 in XMM
9980 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9981 predicate(UseSSE>=2);
9982 match(Set dst (CmpD3 src1 src2));
9983 effect(KILL cr);
9984 ins_cost(255);
9985 format %{ "XOR $dst,$dst\n"
9986 "\tCOMISD $src1,$src2\n"
9987 "\tJP,s nan\n"
9988 "\tJEQ,s exit\n"
9989 "\tJA,s inc\n"
9990 "nan:\tDEC $dst\n"
9991 "\tJMP,s exit\n"
9992 "inc:\tINC $dst\n"
9993 "exit:"
9994 %}
9995 opcode(0x66, 0x0F, 0x2F);
9996 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9997 CmpX_Result(dst));
9998 ins_pipe( pipe_slow );
9999 %}
10001 // Compare into -1,0,1 in XMM and memory
10002 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
10003 predicate(UseSSE>=2);
10004 match(Set dst (CmpD3 src1 (LoadD mem)));
10005 effect(KILL cr);
10006 ins_cost(275);
10007 format %{ "COMISD $src1,$mem\n"
10008 "\tMOV $dst,0\t\t# do not blow flags\n"
10009 "\tJP,s nan\n"
10010 "\tJEQ,s exit\n"
10011 "\tJA,s inc\n"
10012 "nan:\tDEC $dst\n"
10013 "\tJMP,s exit\n"
10014 "inc:\tINC $dst\n"
10015 "exit:"
10016 %}
10017 opcode(0x66, 0x0F, 0x2F);
10018 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
10019 LdImmI(dst,0x0), CmpX_Result(dst));
10020 ins_pipe( pipe_slow );
10021 %}
10024 instruct subD_reg(regD dst, regD src) %{
10025 predicate (UseSSE <=1);
10026 match(Set dst (SubD dst src));
10028 format %{ "FLD $src\n\t"
10029 "DSUBp $dst,ST" %}
10030 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10031 ins_cost(150);
10032 ins_encode( Push_Reg_D(src),
10033 OpcP, RegOpc(dst) );
10034 ins_pipe( fpu_reg_reg );
10035 %}
10037 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10038 predicate (UseSSE <=1);
10039 match(Set dst (RoundDouble (SubD src1 src2)));
10040 ins_cost(250);
10042 format %{ "FLD $src2\n\t"
10043 "DSUB ST,$src1\n\t"
10044 "FSTP_D $dst\t# D-round" %}
10045 opcode(0xD8, 0x5);
10046 ins_encode( Push_Reg_D(src2),
10047 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10048 ins_pipe( fpu_mem_reg_reg );
10049 %}
10052 instruct subD_reg_mem(regD dst, memory src) %{
10053 predicate (UseSSE <=1);
10054 match(Set dst (SubD dst (LoadD src)));
10055 ins_cost(150);
10057 format %{ "FLD $src\n\t"
10058 "DSUBp $dst,ST" %}
10059 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10060 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10061 OpcP, RegOpc(dst) );
10062 ins_pipe( fpu_reg_mem );
10063 %}
10065 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
10066 predicate (UseSSE<=1);
10067 match(Set dst (AbsD src));
10068 ins_cost(100);
10069 format %{ "FABS" %}
10070 opcode(0xE1, 0xD9);
10071 ins_encode( OpcS, OpcP );
10072 ins_pipe( fpu_reg_reg );
10073 %}
10075 instruct absXD_reg( regXD dst ) %{
10076 predicate(UseSSE>=2);
10077 match(Set dst (AbsD dst));
10078 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
10079 ins_encode( AbsXD_encoding(dst));
10080 ins_pipe( pipe_slow );
10081 %}
10083 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
10084 predicate(UseSSE<=1);
10085 match(Set dst (NegD src));
10086 ins_cost(100);
10087 format %{ "FCHS" %}
10088 opcode(0xE0, 0xD9);
10089 ins_encode( OpcS, OpcP );
10090 ins_pipe( fpu_reg_reg );
10091 %}
10093 instruct negXD_reg( regXD dst ) %{
10094 predicate(UseSSE>=2);
10095 match(Set dst (NegD dst));
10096 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
10097 ins_encode %{
10098 __ xorpd($dst$$XMMRegister,
10099 ExternalAddress((address)double_signflip_pool));
10100 %}
10101 ins_pipe( pipe_slow );
10102 %}
10104 instruct addD_reg(regD dst, regD src) %{
10105 predicate(UseSSE<=1);
10106 match(Set dst (AddD dst src));
10107 format %{ "FLD $src\n\t"
10108 "DADD $dst,ST" %}
10109 size(4);
10110 ins_cost(150);
10111 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10112 ins_encode( Push_Reg_D(src),
10113 OpcP, RegOpc(dst) );
10114 ins_pipe( fpu_reg_reg );
10115 %}
10118 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10119 predicate(UseSSE<=1);
10120 match(Set dst (RoundDouble (AddD src1 src2)));
10121 ins_cost(250);
10123 format %{ "FLD $src2\n\t"
10124 "DADD ST,$src1\n\t"
10125 "FSTP_D $dst\t# D-round" %}
10126 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
10127 ins_encode( Push_Reg_D(src2),
10128 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
10129 ins_pipe( fpu_mem_reg_reg );
10130 %}
10133 instruct addD_reg_mem(regD dst, memory src) %{
10134 predicate(UseSSE<=1);
10135 match(Set dst (AddD dst (LoadD src)));
10136 ins_cost(150);
10138 format %{ "FLD $src\n\t"
10139 "DADDp $dst,ST" %}
10140 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
10141 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10142 OpcP, RegOpc(dst) );
10143 ins_pipe( fpu_reg_mem );
10144 %}
10146 // add-to-memory
10147 instruct addD_mem_reg(memory dst, regD src) %{
10148 predicate(UseSSE<=1);
10149 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
10150 ins_cost(150);
10152 format %{ "FLD_D $dst\n\t"
10153 "DADD ST,$src\n\t"
10154 "FST_D $dst" %}
10155 opcode(0xDD, 0x0);
10156 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
10157 Opcode(0xD8), RegOpc(src),
10158 set_instruction_start,
10159 Opcode(0xDD), RMopc_Mem(0x03,dst) );
10160 ins_pipe( fpu_reg_mem );
10161 %}
10163 instruct addD_reg_imm1(regD dst, immD1 src) %{
10164 predicate(UseSSE<=1);
10165 match(Set dst (AddD dst src));
10166 ins_cost(125);
10167 format %{ "FLD1\n\t"
10168 "DADDp $dst,ST" %}
10169 opcode(0xDE, 0x00);
10170 ins_encode( LdImmD(src),
10171 OpcP, RegOpc(dst) );
10172 ins_pipe( fpu_reg );
10173 %}
10175 instruct addD_reg_imm(regD dst, immD src) %{
10176 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10177 match(Set dst (AddD dst src));
10178 ins_cost(200);
10179 format %{ "FLD_D [$src]\n\t"
10180 "DADDp $dst,ST" %}
10181 opcode(0xDE, 0x00); /* DE /0 */
10182 ins_encode( LdImmD(src),
10183 OpcP, RegOpc(dst));
10184 ins_pipe( fpu_reg_mem );
10185 %}
10187 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
10188 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
10189 match(Set dst (RoundDouble (AddD src con)));
10190 ins_cost(200);
10191 format %{ "FLD_D [$con]\n\t"
10192 "DADD ST,$src\n\t"
10193 "FSTP_D $dst\t# D-round" %}
10194 opcode(0xD8, 0x00); /* D8 /0 */
10195 ins_encode( LdImmD(con),
10196 OpcP, RegOpc(src), Pop_Mem_D(dst));
10197 ins_pipe( fpu_mem_reg_con );
10198 %}
10200 // Add two double precision floating point values in xmm
10201 instruct addXD_reg(regXD dst, regXD src) %{
10202 predicate(UseSSE>=2);
10203 match(Set dst (AddD dst src));
10204 format %{ "ADDSD $dst,$src" %}
10205 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10206 ins_pipe( pipe_slow );
10207 %}
10209 instruct addXD_imm(regXD dst, immXD con) %{
10210 predicate(UseSSE>=2);
10211 match(Set dst (AddD dst con));
10212 format %{ "ADDSD $dst,[$con]" %}
10213 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
10214 ins_pipe( pipe_slow );
10215 %}
10217 instruct addXD_mem(regXD dst, memory mem) %{
10218 predicate(UseSSE>=2);
10219 match(Set dst (AddD dst (LoadD mem)));
10220 format %{ "ADDSD $dst,$mem" %}
10221 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
10222 ins_pipe( pipe_slow );
10223 %}
10225 // Sub two double precision floating point values in xmm
10226 instruct subXD_reg(regXD dst, regXD src) %{
10227 predicate(UseSSE>=2);
10228 match(Set dst (SubD dst src));
10229 format %{ "SUBSD $dst,$src" %}
10230 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10231 ins_pipe( pipe_slow );
10232 %}
10234 instruct subXD_imm(regXD dst, immXD con) %{
10235 predicate(UseSSE>=2);
10236 match(Set dst (SubD dst con));
10237 format %{ "SUBSD $dst,[$con]" %}
10238 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
10239 ins_pipe( pipe_slow );
10240 %}
10242 instruct subXD_mem(regXD dst, memory mem) %{
10243 predicate(UseSSE>=2);
10244 match(Set dst (SubD dst (LoadD mem)));
10245 format %{ "SUBSD $dst,$mem" %}
10246 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10247 ins_pipe( pipe_slow );
10248 %}
10250 // Mul two double precision floating point values in xmm
10251 instruct mulXD_reg(regXD dst, regXD src) %{
10252 predicate(UseSSE>=2);
10253 match(Set dst (MulD dst src));
10254 format %{ "MULSD $dst,$src" %}
10255 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10256 ins_pipe( pipe_slow );
10257 %}
10259 instruct mulXD_imm(regXD dst, immXD con) %{
10260 predicate(UseSSE>=2);
10261 match(Set dst (MulD dst con));
10262 format %{ "MULSD $dst,[$con]" %}
10263 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
10264 ins_pipe( pipe_slow );
10265 %}
10267 instruct mulXD_mem(regXD dst, memory mem) %{
10268 predicate(UseSSE>=2);
10269 match(Set dst (MulD dst (LoadD mem)));
10270 format %{ "MULSD $dst,$mem" %}
10271 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10272 ins_pipe( pipe_slow );
10273 %}
10275 // Div two double precision floating point values in xmm
10276 instruct divXD_reg(regXD dst, regXD src) %{
10277 predicate(UseSSE>=2);
10278 match(Set dst (DivD dst src));
10279 format %{ "DIVSD $dst,$src" %}
10280 opcode(0xF2, 0x0F, 0x5E);
10281 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10282 ins_pipe( pipe_slow );
10283 %}
10285 instruct divXD_imm(regXD dst, immXD con) %{
10286 predicate(UseSSE>=2);
10287 match(Set dst (DivD dst con));
10288 format %{ "DIVSD $dst,[$con]" %}
10289 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10290 ins_pipe( pipe_slow );
10291 %}
10293 instruct divXD_mem(regXD dst, memory mem) %{
10294 predicate(UseSSE>=2);
10295 match(Set dst (DivD dst (LoadD mem)));
10296 format %{ "DIVSD $dst,$mem" %}
10297 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10298 ins_pipe( pipe_slow );
10299 %}
10302 instruct mulD_reg(regD dst, regD src) %{
10303 predicate(UseSSE<=1);
10304 match(Set dst (MulD dst src));
10305 format %{ "FLD $src\n\t"
10306 "DMULp $dst,ST" %}
10307 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10308 ins_cost(150);
10309 ins_encode( Push_Reg_D(src),
10310 OpcP, RegOpc(dst) );
10311 ins_pipe( fpu_reg_reg );
10312 %}
10314 // Strict FP instruction biases argument before multiply then
10315 // biases result to avoid double rounding of subnormals.
10316 //
10317 // scale arg1 by multiplying arg1 by 2^(-15360)
10318 // load arg2
10319 // multiply scaled arg1 by arg2
10320 // rescale product by 2^(15360)
10321 //
10322 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10323 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10324 match(Set dst (MulD dst src));
10325 ins_cost(1); // Select this instruction for all strict FP double multiplies
10327 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10328 "DMULp $dst,ST\n\t"
10329 "FLD $src\n\t"
10330 "DMULp $dst,ST\n\t"
10331 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10332 "DMULp $dst,ST\n\t" %}
10333 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10334 ins_encode( strictfp_bias1(dst),
10335 Push_Reg_D(src),
10336 OpcP, RegOpc(dst),
10337 strictfp_bias2(dst) );
10338 ins_pipe( fpu_reg_reg );
10339 %}
10341 instruct mulD_reg_imm(regD dst, immD src) %{
10342 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10343 match(Set dst (MulD dst src));
10344 ins_cost(200);
10345 format %{ "FLD_D [$src]\n\t"
10346 "DMULp $dst,ST" %}
10347 opcode(0xDE, 0x1); /* DE /1 */
10348 ins_encode( LdImmD(src),
10349 OpcP, RegOpc(dst) );
10350 ins_pipe( fpu_reg_mem );
10351 %}
10354 instruct mulD_reg_mem(regD dst, memory src) %{
10355 predicate( UseSSE<=1 );
10356 match(Set dst (MulD dst (LoadD src)));
10357 ins_cost(200);
10358 format %{ "FLD_D $src\n\t"
10359 "DMULp $dst,ST" %}
10360 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10361 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10362 OpcP, RegOpc(dst) );
10363 ins_pipe( fpu_reg_mem );
10364 %}
10366 //
10367 // Cisc-alternate to reg-reg multiply
10368 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10369 predicate( UseSSE<=1 );
10370 match(Set dst (MulD src (LoadD mem)));
10371 ins_cost(250);
10372 format %{ "FLD_D $mem\n\t"
10373 "DMUL ST,$src\n\t"
10374 "FSTP_D $dst" %}
10375 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10376 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10377 OpcReg_F(src),
10378 Pop_Reg_D(dst) );
10379 ins_pipe( fpu_reg_reg_mem );
10380 %}
10383 // MACRO3 -- addD a mulD
10384 // This instruction is a '2-address' instruction in that the result goes
10385 // back to src2. This eliminates a move from the macro; possibly the
10386 // register allocator will have to add it back (and maybe not).
10387 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10388 predicate( UseSSE<=1 );
10389 match(Set src2 (AddD (MulD src0 src1) src2));
10390 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10391 "DMUL ST,$src1\n\t"
10392 "DADDp $src2,ST" %}
10393 ins_cost(250);
10394 opcode(0xDD); /* LoadD DD /0 */
10395 ins_encode( Push_Reg_F(src0),
10396 FMul_ST_reg(src1),
10397 FAddP_reg_ST(src2) );
10398 ins_pipe( fpu_reg_reg_reg );
10399 %}
10402 // MACRO3 -- subD a mulD
10403 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10404 predicate( UseSSE<=1 );
10405 match(Set src2 (SubD (MulD src0 src1) src2));
10406 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10407 "DMUL ST,$src1\n\t"
10408 "DSUBRp $src2,ST" %}
10409 ins_cost(250);
10410 ins_encode( Push_Reg_F(src0),
10411 FMul_ST_reg(src1),
10412 Opcode(0xDE), Opc_plus(0xE0,src2));
10413 ins_pipe( fpu_reg_reg_reg );
10414 %}
10417 instruct divD_reg(regD dst, regD src) %{
10418 predicate( UseSSE<=1 );
10419 match(Set dst (DivD dst src));
10421 format %{ "FLD $src\n\t"
10422 "FDIVp $dst,ST" %}
10423 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10424 ins_cost(150);
10425 ins_encode( Push_Reg_D(src),
10426 OpcP, RegOpc(dst) );
10427 ins_pipe( fpu_reg_reg );
10428 %}
10430 // Strict FP instruction biases argument before division then
10431 // biases result, to avoid double rounding of subnormals.
10432 //
10433 // scale dividend by multiplying dividend by 2^(-15360)
10434 // load divisor
10435 // divide scaled dividend by divisor
10436 // rescale quotient by 2^(15360)
10437 //
10438 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10439 predicate (UseSSE<=1);
10440 match(Set dst (DivD dst src));
10441 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10442 ins_cost(01);
10444 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10445 "DMULp $dst,ST\n\t"
10446 "FLD $src\n\t"
10447 "FDIVp $dst,ST\n\t"
10448 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10449 "DMULp $dst,ST\n\t" %}
10450 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10451 ins_encode( strictfp_bias1(dst),
10452 Push_Reg_D(src),
10453 OpcP, RegOpc(dst),
10454 strictfp_bias2(dst) );
10455 ins_pipe( fpu_reg_reg );
10456 %}
10458 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10459 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10460 match(Set dst (RoundDouble (DivD src1 src2)));
10462 format %{ "FLD $src1\n\t"
10463 "FDIV ST,$src2\n\t"
10464 "FSTP_D $dst\t# D-round" %}
10465 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10466 ins_encode( Push_Reg_D(src1),
10467 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10468 ins_pipe( fpu_mem_reg_reg );
10469 %}
10472 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10473 predicate(UseSSE<=1);
10474 match(Set dst (ModD dst src));
10475 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10477 format %{ "DMOD $dst,$src" %}
10478 ins_cost(250);
10479 ins_encode(Push_Reg_Mod_D(dst, src),
10480 emitModD(),
10481 Push_Result_Mod_D(src),
10482 Pop_Reg_D(dst));
10483 ins_pipe( pipe_slow );
10484 %}
10486 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10487 predicate(UseSSE>=2);
10488 match(Set dst (ModD src0 src1));
10489 effect(KILL rax, KILL cr);
10491 format %{ "SUB ESP,8\t # DMOD\n"
10492 "\tMOVSD [ESP+0],$src1\n"
10493 "\tFLD_D [ESP+0]\n"
10494 "\tMOVSD [ESP+0],$src0\n"
10495 "\tFLD_D [ESP+0]\n"
10496 "loop:\tFPREM\n"
10497 "\tFWAIT\n"
10498 "\tFNSTSW AX\n"
10499 "\tSAHF\n"
10500 "\tJP loop\n"
10501 "\tFSTP_D [ESP+0]\n"
10502 "\tMOVSD $dst,[ESP+0]\n"
10503 "\tADD ESP,8\n"
10504 "\tFSTP ST0\t # Restore FPU Stack"
10505 %}
10506 ins_cost(250);
10507 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10508 ins_pipe( pipe_slow );
10509 %}
10511 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10512 predicate (UseSSE<=1);
10513 match(Set dst (SinD src));
10514 ins_cost(1800);
10515 format %{ "DSIN $dst" %}
10516 opcode(0xD9, 0xFE);
10517 ins_encode( OpcP, OpcS );
10518 ins_pipe( pipe_slow );
10519 %}
10521 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10522 predicate (UseSSE>=2);
10523 match(Set dst (SinD dst));
10524 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10525 ins_cost(1800);
10526 format %{ "DSIN $dst" %}
10527 opcode(0xD9, 0xFE);
10528 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10529 ins_pipe( pipe_slow );
10530 %}
10532 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10533 predicate (UseSSE<=1);
10534 match(Set dst (CosD src));
10535 ins_cost(1800);
10536 format %{ "DCOS $dst" %}
10537 opcode(0xD9, 0xFF);
10538 ins_encode( OpcP, OpcS );
10539 ins_pipe( pipe_slow );
10540 %}
10542 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10543 predicate (UseSSE>=2);
10544 match(Set dst (CosD dst));
10545 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10546 ins_cost(1800);
10547 format %{ "DCOS $dst" %}
10548 opcode(0xD9, 0xFF);
10549 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10550 ins_pipe( pipe_slow );
10551 %}
10553 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10554 predicate (UseSSE<=1);
10555 match(Set dst(TanD src));
10556 format %{ "DTAN $dst" %}
10557 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10558 Opcode(0xDD), Opcode(0xD8)); // fstp st
10559 ins_pipe( pipe_slow );
10560 %}
10562 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10563 predicate (UseSSE>=2);
10564 match(Set dst(TanD dst));
10565 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10566 format %{ "DTAN $dst" %}
10567 ins_encode( Push_SrcXD(dst),
10568 Opcode(0xD9), Opcode(0xF2), // fptan
10569 Opcode(0xDD), Opcode(0xD8), // fstp st
10570 Push_ResultXD(dst) );
10571 ins_pipe( pipe_slow );
10572 %}
10574 instruct atanD_reg(regD dst, regD src) %{
10575 predicate (UseSSE<=1);
10576 match(Set dst(AtanD dst src));
10577 format %{ "DATA $dst,$src" %}
10578 opcode(0xD9, 0xF3);
10579 ins_encode( Push_Reg_D(src),
10580 OpcP, OpcS, RegOpc(dst) );
10581 ins_pipe( pipe_slow );
10582 %}
10584 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10585 predicate (UseSSE>=2);
10586 match(Set dst(AtanD dst src));
10587 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10588 format %{ "DATA $dst,$src" %}
10589 opcode(0xD9, 0xF3);
10590 ins_encode( Push_SrcXD(src),
10591 OpcP, OpcS, Push_ResultXD(dst) );
10592 ins_pipe( pipe_slow );
10593 %}
10595 instruct sqrtD_reg(regD dst, regD src) %{
10596 predicate (UseSSE<=1);
10597 match(Set dst (SqrtD src));
10598 format %{ "DSQRT $dst,$src" %}
10599 opcode(0xFA, 0xD9);
10600 ins_encode( Push_Reg_D(src),
10601 OpcS, OpcP, Pop_Reg_D(dst) );
10602 ins_pipe( pipe_slow );
10603 %}
10605 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10606 predicate (UseSSE<=1);
10607 match(Set Y (PowD X Y)); // Raise X to the Yth power
10608 effect(KILL rax, KILL rbx, KILL rcx);
10609 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10610 "FLD_D $X\n\t"
10611 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10613 "FDUP \t\t\t# Q Q\n\t"
10614 "FRNDINT\t\t\t# int(Q) Q\n\t"
10615 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10616 "FISTP dword [ESP]\n\t"
10617 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10618 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10619 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10620 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10621 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10622 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10623 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10624 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10625 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10626 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10627 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10628 "MOV [ESP+0],0\n\t"
10629 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10631 "ADD ESP,8"
10632 %}
10633 ins_encode( push_stack_temp_qword,
10634 Push_Reg_D(X),
10635 Opcode(0xD9), Opcode(0xF1), // fyl2x
10636 pow_exp_core_encoding,
10637 pop_stack_temp_qword);
10638 ins_pipe( pipe_slow );
10639 %}
10641 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10642 predicate (UseSSE>=2);
10643 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10644 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10645 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10646 "MOVSD [ESP],$src1\n\t"
10647 "FLD FPR1,$src1\n\t"
10648 "MOVSD [ESP],$src0\n\t"
10649 "FLD FPR1,$src0\n\t"
10650 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10652 "FDUP \t\t\t# Q Q\n\t"
10653 "FRNDINT\t\t\t# int(Q) Q\n\t"
10654 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10655 "FISTP dword [ESP]\n\t"
10656 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10657 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10658 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10659 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10660 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10661 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10662 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10663 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10664 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10665 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10666 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10667 "MOV [ESP+0],0\n\t"
10668 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10670 "FST_D [ESP]\n\t"
10671 "MOVSD $dst,[ESP]\n\t"
10672 "ADD ESP,8"
10673 %}
10674 ins_encode( push_stack_temp_qword,
10675 push_xmm_to_fpr1(src1),
10676 push_xmm_to_fpr1(src0),
10677 Opcode(0xD9), Opcode(0xF1), // fyl2x
10678 pow_exp_core_encoding,
10679 Push_ResultXD(dst) );
10680 ins_pipe( pipe_slow );
10681 %}
10684 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10685 predicate (UseSSE<=1);
10686 match(Set dpr1 (ExpD dpr1));
10687 effect(KILL rax, KILL rbx, KILL rcx);
10688 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10689 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10690 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10692 "FDUP \t\t\t# Q Q\n\t"
10693 "FRNDINT\t\t\t# int(Q) Q\n\t"
10694 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10695 "FISTP dword [ESP]\n\t"
10696 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10697 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10698 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10699 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10700 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10701 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10702 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10703 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10704 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10705 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10706 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10707 "MOV [ESP+0],0\n\t"
10708 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10710 "ADD ESP,8"
10711 %}
10712 ins_encode( push_stack_temp_qword,
10713 Opcode(0xD9), Opcode(0xEA), // fldl2e
10714 Opcode(0xDE), Opcode(0xC9), // fmulp
10715 pow_exp_core_encoding,
10716 pop_stack_temp_qword);
10717 ins_pipe( pipe_slow );
10718 %}
10720 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10721 predicate (UseSSE>=2);
10722 match(Set dst (ExpD src));
10723 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10724 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10725 "MOVSD [ESP],$src\n\t"
10726 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10727 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10729 "FDUP \t\t\t# Q Q\n\t"
10730 "FRNDINT\t\t\t# int(Q) Q\n\t"
10731 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10732 "FISTP dword [ESP]\n\t"
10733 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10734 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10735 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10736 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10737 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10738 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10739 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10740 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10741 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10742 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10743 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10744 "MOV [ESP+0],0\n\t"
10745 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10747 "FST_D [ESP]\n\t"
10748 "MOVSD $dst,[ESP]\n\t"
10749 "ADD ESP,8"
10750 %}
10751 ins_encode( Push_SrcXD(src),
10752 Opcode(0xD9), Opcode(0xEA), // fldl2e
10753 Opcode(0xDE), Opcode(0xC9), // fmulp
10754 pow_exp_core_encoding,
10755 Push_ResultXD(dst) );
10756 ins_pipe( pipe_slow );
10757 %}
10761 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10762 predicate (UseSSE<=1);
10763 // The source Double operand on FPU stack
10764 match(Set dst (Log10D src));
10765 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10766 // fxch ; swap ST(0) with ST(1)
10767 // fyl2x ; compute log_10(2) * log_2(x)
10768 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10769 "FXCH \n\t"
10770 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10771 %}
10772 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10773 Opcode(0xD9), Opcode(0xC9), // fxch
10774 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10776 ins_pipe( pipe_slow );
10777 %}
10779 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10780 predicate (UseSSE>=2);
10781 effect(KILL cr);
10782 match(Set dst (Log10D src));
10783 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10784 // fyl2x ; compute log_10(2) * log_2(x)
10785 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10786 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10787 %}
10788 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10789 Push_SrcXD(src),
10790 Opcode(0xD9), Opcode(0xF1), // fyl2x
10791 Push_ResultXD(dst));
10793 ins_pipe( pipe_slow );
10794 %}
10796 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10797 predicate (UseSSE<=1);
10798 // The source Double operand on FPU stack
10799 match(Set dst (LogD src));
10800 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10801 // fxch ; swap ST(0) with ST(1)
10802 // fyl2x ; compute log_e(2) * log_2(x)
10803 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10804 "FXCH \n\t"
10805 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10806 %}
10807 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10808 Opcode(0xD9), Opcode(0xC9), // fxch
10809 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10811 ins_pipe( pipe_slow );
10812 %}
10814 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10815 predicate (UseSSE>=2);
10816 effect(KILL cr);
10817 // The source and result Double operands in XMM registers
10818 match(Set dst (LogD src));
10819 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10820 // fyl2x ; compute log_e(2) * log_2(x)
10821 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10822 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10823 %}
10824 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10825 Push_SrcXD(src),
10826 Opcode(0xD9), Opcode(0xF1), // fyl2x
10827 Push_ResultXD(dst));
10828 ins_pipe( pipe_slow );
10829 %}
10831 //-------------Float Instructions-------------------------------
10832 // Float Math
10834 // Code for float compare:
10835 // fcompp();
10836 // fwait(); fnstsw_ax();
10837 // sahf();
10838 // movl(dst, unordered_result);
10839 // jcc(Assembler::parity, exit);
10840 // movl(dst, less_result);
10841 // jcc(Assembler::below, exit);
10842 // movl(dst, equal_result);
10843 // jcc(Assembler::equal, exit);
10844 // movl(dst, greater_result);
10845 // exit:
10847 // P6 version of float compare, sets condition codes in EFLAGS
10848 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10849 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10850 match(Set cr (CmpF src1 src2));
10851 effect(KILL rax);
10852 ins_cost(150);
10853 format %{ "FLD $src1\n\t"
10854 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10855 "JNP exit\n\t"
10856 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10857 "SAHF\n"
10858 "exit:\tNOP // avoid branch to branch" %}
10859 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10860 ins_encode( Push_Reg_D(src1),
10861 OpcP, RegOpc(src2),
10862 cmpF_P6_fixup );
10863 ins_pipe( pipe_slow );
10864 %}
10866 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10867 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10868 match(Set cr (CmpF src1 src2));
10869 ins_cost(100);
10870 format %{ "FLD $src1\n\t"
10871 "FUCOMIP ST,$src2 // P6 instruction" %}
10872 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10873 ins_encode( Push_Reg_D(src1),
10874 OpcP, RegOpc(src2));
10875 ins_pipe( pipe_slow );
10876 %}
10879 // Compare & branch
10880 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10881 predicate(UseSSE == 0);
10882 match(Set cr (CmpF src1 src2));
10883 effect(KILL rax);
10884 ins_cost(200);
10885 format %{ "FLD $src1\n\t"
10886 "FCOMp $src2\n\t"
10887 "FNSTSW AX\n\t"
10888 "TEST AX,0x400\n\t"
10889 "JZ,s flags\n\t"
10890 "MOV AH,1\t# unordered treat as LT\n"
10891 "flags:\tSAHF" %}
10892 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10893 ins_encode( Push_Reg_D(src1),
10894 OpcP, RegOpc(src2),
10895 fpu_flags);
10896 ins_pipe( pipe_slow );
10897 %}
10899 // Compare vs zero into -1,0,1
10900 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10901 predicate(UseSSE == 0);
10902 match(Set dst (CmpF3 src1 zero));
10903 effect(KILL cr, KILL rax);
10904 ins_cost(280);
10905 format %{ "FTSTF $dst,$src1" %}
10906 opcode(0xE4, 0xD9);
10907 ins_encode( Push_Reg_D(src1),
10908 OpcS, OpcP, PopFPU,
10909 CmpF_Result(dst));
10910 ins_pipe( pipe_slow );
10911 %}
10913 // Compare into -1,0,1
10914 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10915 predicate(UseSSE == 0);
10916 match(Set dst (CmpF3 src1 src2));
10917 effect(KILL cr, KILL rax);
10918 ins_cost(300);
10919 format %{ "FCMPF $dst,$src1,$src2" %}
10920 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10921 ins_encode( Push_Reg_D(src1),
10922 OpcP, RegOpc(src2),
10923 CmpF_Result(dst));
10924 ins_pipe( pipe_slow );
10925 %}
10927 // float compare and set condition codes in EFLAGS by XMM regs
10928 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10929 predicate(UseSSE>=1);
10930 match(Set cr (CmpF dst src));
10931 effect(KILL rax);
10932 ins_cost(145);
10933 format %{ "COMISS $dst,$src\n"
10934 "\tJNP exit\n"
10935 "\tMOV ah,1 // saw a NaN, set CF\n"
10936 "\tSAHF\n"
10937 "exit:\tNOP // avoid branch to branch" %}
10938 opcode(0x0F, 0x2F);
10939 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10940 ins_pipe( pipe_slow );
10941 %}
10943 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10944 predicate(UseSSE>=1);
10945 match(Set cr (CmpF dst src));
10946 ins_cost(100);
10947 format %{ "COMISS $dst,$src" %}
10948 opcode(0x0F, 0x2F);
10949 ins_encode(OpcP, OpcS, RegReg(dst, src));
10950 ins_pipe( pipe_slow );
10951 %}
10953 // float compare and set condition codes in EFLAGS by XMM regs
10954 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10955 predicate(UseSSE>=1);
10956 match(Set cr (CmpF dst (LoadF src)));
10957 effect(KILL rax);
10958 ins_cost(165);
10959 format %{ "COMISS $dst,$src\n"
10960 "\tJNP exit\n"
10961 "\tMOV ah,1 // saw a NaN, set CF\n"
10962 "\tSAHF\n"
10963 "exit:\tNOP // avoid branch to branch" %}
10964 opcode(0x0F, 0x2F);
10965 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10966 ins_pipe( pipe_slow );
10967 %}
10969 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10970 predicate(UseSSE>=1);
10971 match(Set cr (CmpF dst (LoadF src)));
10972 ins_cost(100);
10973 format %{ "COMISS $dst,$src" %}
10974 opcode(0x0F, 0x2F);
10975 ins_encode(OpcP, OpcS, RegMem(dst, src));
10976 ins_pipe( pipe_slow );
10977 %}
10979 // Compare into -1,0,1 in XMM
10980 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10981 predicate(UseSSE>=1);
10982 match(Set dst (CmpF3 src1 src2));
10983 effect(KILL cr);
10984 ins_cost(255);
10985 format %{ "XOR $dst,$dst\n"
10986 "\tCOMISS $src1,$src2\n"
10987 "\tJP,s nan\n"
10988 "\tJEQ,s exit\n"
10989 "\tJA,s inc\n"
10990 "nan:\tDEC $dst\n"
10991 "\tJMP,s exit\n"
10992 "inc:\tINC $dst\n"
10993 "exit:"
10994 %}
10995 opcode(0x0F, 0x2F);
10996 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10997 ins_pipe( pipe_slow );
10998 %}
11000 // Compare into -1,0,1 in XMM and memory
11001 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
11002 predicate(UseSSE>=1);
11003 match(Set dst (CmpF3 src1 (LoadF mem)));
11004 effect(KILL cr);
11005 ins_cost(275);
11006 format %{ "COMISS $src1,$mem\n"
11007 "\tMOV $dst,0\t\t# do not blow flags\n"
11008 "\tJP,s nan\n"
11009 "\tJEQ,s exit\n"
11010 "\tJA,s inc\n"
11011 "nan:\tDEC $dst\n"
11012 "\tJMP,s exit\n"
11013 "inc:\tINC $dst\n"
11014 "exit:"
11015 %}
11016 opcode(0x0F, 0x2F);
11017 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
11018 ins_pipe( pipe_slow );
11019 %}
11021 // Spill to obtain 24-bit precision
11022 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
11023 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11024 match(Set dst (SubF src1 src2));
11026 format %{ "FSUB $dst,$src1 - $src2" %}
11027 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
11028 ins_encode( Push_Reg_F(src1),
11029 OpcReg_F(src2),
11030 Pop_Mem_F(dst) );
11031 ins_pipe( fpu_mem_reg_reg );
11032 %}
11033 //
11034 // This instruction does not round to 24-bits
11035 instruct subF_reg(regF dst, regF src) %{
11036 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11037 match(Set dst (SubF dst src));
11039 format %{ "FSUB $dst,$src" %}
11040 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
11041 ins_encode( Push_Reg_F(src),
11042 OpcP, RegOpc(dst) );
11043 ins_pipe( fpu_reg_reg );
11044 %}
11046 // Spill to obtain 24-bit precision
11047 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
11048 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11049 match(Set dst (AddF src1 src2));
11051 format %{ "FADD $dst,$src1,$src2" %}
11052 opcode(0xD8, 0x0); /* D8 C0+i */
11053 ins_encode( Push_Reg_F(src2),
11054 OpcReg_F(src1),
11055 Pop_Mem_F(dst) );
11056 ins_pipe( fpu_mem_reg_reg );
11057 %}
11058 //
11059 // This instruction does not round to 24-bits
11060 instruct addF_reg(regF dst, regF src) %{
11061 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11062 match(Set dst (AddF dst src));
11064 format %{ "FLD $src\n\t"
11065 "FADDp $dst,ST" %}
11066 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
11067 ins_encode( Push_Reg_F(src),
11068 OpcP, RegOpc(dst) );
11069 ins_pipe( fpu_reg_reg );
11070 %}
11072 // Add two single precision floating point values in xmm
11073 instruct addX_reg(regX dst, regX src) %{
11074 predicate(UseSSE>=1);
11075 match(Set dst (AddF dst src));
11076 format %{ "ADDSS $dst,$src" %}
11077 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
11078 ins_pipe( pipe_slow );
11079 %}
11081 instruct addX_imm(regX dst, immXF con) %{
11082 predicate(UseSSE>=1);
11083 match(Set dst (AddF dst con));
11084 format %{ "ADDSS $dst,[$con]" %}
11085 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
11086 ins_pipe( pipe_slow );
11087 %}
11089 instruct addX_mem(regX dst, memory mem) %{
11090 predicate(UseSSE>=1);
11091 match(Set dst (AddF dst (LoadF mem)));
11092 format %{ "ADDSS $dst,$mem" %}
11093 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
11094 ins_pipe( pipe_slow );
11095 %}
11097 // Subtract two single precision floating point values in xmm
11098 instruct subX_reg(regX dst, regX src) %{
11099 predicate(UseSSE>=1);
11100 match(Set dst (SubF dst src));
11101 format %{ "SUBSS $dst,$src" %}
11102 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
11103 ins_pipe( pipe_slow );
11104 %}
11106 instruct subX_imm(regX dst, immXF con) %{
11107 predicate(UseSSE>=1);
11108 match(Set dst (SubF dst con));
11109 format %{ "SUBSS $dst,[$con]" %}
11110 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
11111 ins_pipe( pipe_slow );
11112 %}
11114 instruct subX_mem(regX dst, memory mem) %{
11115 predicate(UseSSE>=1);
11116 match(Set dst (SubF dst (LoadF mem)));
11117 format %{ "SUBSS $dst,$mem" %}
11118 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
11119 ins_pipe( pipe_slow );
11120 %}
11122 // Multiply two single precision floating point values in xmm
11123 instruct mulX_reg(regX dst, regX src) %{
11124 predicate(UseSSE>=1);
11125 match(Set dst (MulF dst src));
11126 format %{ "MULSS $dst,$src" %}
11127 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
11128 ins_pipe( pipe_slow );
11129 %}
11131 instruct mulX_imm(regX dst, immXF con) %{
11132 predicate(UseSSE>=1);
11133 match(Set dst (MulF dst con));
11134 format %{ "MULSS $dst,[$con]" %}
11135 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
11136 ins_pipe( pipe_slow );
11137 %}
11139 instruct mulX_mem(regX dst, memory mem) %{
11140 predicate(UseSSE>=1);
11141 match(Set dst (MulF dst (LoadF mem)));
11142 format %{ "MULSS $dst,$mem" %}
11143 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
11144 ins_pipe( pipe_slow );
11145 %}
11147 // Divide two single precision floating point values in xmm
11148 instruct divX_reg(regX dst, regX src) %{
11149 predicate(UseSSE>=1);
11150 match(Set dst (DivF dst src));
11151 format %{ "DIVSS $dst,$src" %}
11152 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
11153 ins_pipe( pipe_slow );
11154 %}
11156 instruct divX_imm(regX dst, immXF con) %{
11157 predicate(UseSSE>=1);
11158 match(Set dst (DivF dst con));
11159 format %{ "DIVSS $dst,[$con]" %}
11160 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
11161 ins_pipe( pipe_slow );
11162 %}
11164 instruct divX_mem(regX dst, memory mem) %{
11165 predicate(UseSSE>=1);
11166 match(Set dst (DivF dst (LoadF mem)));
11167 format %{ "DIVSS $dst,$mem" %}
11168 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
11169 ins_pipe( pipe_slow );
11170 %}
11172 // Get the square root of a single precision floating point values in xmm
11173 instruct sqrtX_reg(regX dst, regX src) %{
11174 predicate(UseSSE>=1);
11175 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
11176 format %{ "SQRTSS $dst,$src" %}
11177 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11178 ins_pipe( pipe_slow );
11179 %}
11181 instruct sqrtX_mem(regX dst, memory mem) %{
11182 predicate(UseSSE>=1);
11183 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
11184 format %{ "SQRTSS $dst,$mem" %}
11185 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11186 ins_pipe( pipe_slow );
11187 %}
11189 // Get the square root of a double precision floating point values in xmm
11190 instruct sqrtXD_reg(regXD dst, regXD src) %{
11191 predicate(UseSSE>=2);
11192 match(Set dst (SqrtD src));
11193 format %{ "SQRTSD $dst,$src" %}
11194 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
11195 ins_pipe( pipe_slow );
11196 %}
11198 instruct sqrtXD_mem(regXD dst, memory mem) %{
11199 predicate(UseSSE>=2);
11200 match(Set dst (SqrtD (LoadD mem)));
11201 format %{ "SQRTSD $dst,$mem" %}
11202 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
11203 ins_pipe( pipe_slow );
11204 %}
11206 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
11207 predicate(UseSSE==0);
11208 match(Set dst (AbsF src));
11209 ins_cost(100);
11210 format %{ "FABS" %}
11211 opcode(0xE1, 0xD9);
11212 ins_encode( OpcS, OpcP );
11213 ins_pipe( fpu_reg_reg );
11214 %}
11216 instruct absX_reg(regX dst ) %{
11217 predicate(UseSSE>=1);
11218 match(Set dst (AbsF dst));
11219 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
11220 ins_encode( AbsXF_encoding(dst));
11221 ins_pipe( pipe_slow );
11222 %}
11224 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
11225 predicate(UseSSE==0);
11226 match(Set dst (NegF src));
11227 ins_cost(100);
11228 format %{ "FCHS" %}
11229 opcode(0xE0, 0xD9);
11230 ins_encode( OpcS, OpcP );
11231 ins_pipe( fpu_reg_reg );
11232 %}
11234 instruct negX_reg( regX dst ) %{
11235 predicate(UseSSE>=1);
11236 match(Set dst (NegF dst));
11237 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
11238 ins_encode( NegXF_encoding(dst));
11239 ins_pipe( pipe_slow );
11240 %}
11242 // Cisc-alternate to addF_reg
11243 // Spill to obtain 24-bit precision
11244 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11245 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11246 match(Set dst (AddF src1 (LoadF src2)));
11248 format %{ "FLD $src2\n\t"
11249 "FADD ST,$src1\n\t"
11250 "FSTP_S $dst" %}
11251 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11252 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11253 OpcReg_F(src1),
11254 Pop_Mem_F(dst) );
11255 ins_pipe( fpu_mem_reg_mem );
11256 %}
11257 //
11258 // Cisc-alternate to addF_reg
11259 // This instruction does not round to 24-bits
11260 instruct addF_reg_mem(regF dst, memory src) %{
11261 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11262 match(Set dst (AddF dst (LoadF src)));
11264 format %{ "FADD $dst,$src" %}
11265 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
11266 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
11267 OpcP, RegOpc(dst) );
11268 ins_pipe( fpu_reg_mem );
11269 %}
11271 // // Following two instructions for _222_mpegaudio
11272 // Spill to obtain 24-bit precision
11273 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11274 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11275 match(Set dst (AddF src1 src2));
11277 format %{ "FADD $dst,$src1,$src2" %}
11278 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11279 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11280 OpcReg_F(src2),
11281 Pop_Mem_F(dst) );
11282 ins_pipe( fpu_mem_reg_mem );
11283 %}
11285 // Cisc-spill variant
11286 // Spill to obtain 24-bit precision
11287 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11288 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11289 match(Set dst (AddF src1 (LoadF src2)));
11291 format %{ "FADD $dst,$src1,$src2 cisc" %}
11292 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11293 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11294 set_instruction_start,
11295 OpcP, RMopc_Mem(secondary,src1),
11296 Pop_Mem_F(dst) );
11297 ins_pipe( fpu_mem_mem_mem );
11298 %}
11300 // Spill to obtain 24-bit precision
11301 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11302 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11303 match(Set dst (AddF src1 src2));
11305 format %{ "FADD $dst,$src1,$src2" %}
11306 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11307 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11308 set_instruction_start,
11309 OpcP, RMopc_Mem(secondary,src1),
11310 Pop_Mem_F(dst) );
11311 ins_pipe( fpu_mem_mem_mem );
11312 %}
11315 // Spill to obtain 24-bit precision
11316 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11317 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11318 match(Set dst (AddF src1 src2));
11319 format %{ "FLD $src1\n\t"
11320 "FADD $src2\n\t"
11321 "FSTP_S $dst" %}
11322 opcode(0xD8, 0x00); /* D8 /0 */
11323 ins_encode( Push_Reg_F(src1),
11324 Opc_MemImm_F(src2),
11325 Pop_Mem_F(dst));
11326 ins_pipe( fpu_mem_reg_con );
11327 %}
11328 //
11329 // This instruction does not round to 24-bits
11330 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11331 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11332 match(Set dst (AddF src1 src2));
11333 format %{ "FLD $src1\n\t"
11334 "FADD $src2\n\t"
11335 "FSTP_S $dst" %}
11336 opcode(0xD8, 0x00); /* D8 /0 */
11337 ins_encode( Push_Reg_F(src1),
11338 Opc_MemImm_F(src2),
11339 Pop_Reg_F(dst));
11340 ins_pipe( fpu_reg_reg_con );
11341 %}
11343 // Spill to obtain 24-bit precision
11344 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11345 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11346 match(Set dst (MulF src1 src2));
11348 format %{ "FLD $src1\n\t"
11349 "FMUL $src2\n\t"
11350 "FSTP_S $dst" %}
11351 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11352 ins_encode( Push_Reg_F(src1),
11353 OpcReg_F(src2),
11354 Pop_Mem_F(dst) );
11355 ins_pipe( fpu_mem_reg_reg );
11356 %}
11357 //
11358 // This instruction does not round to 24-bits
11359 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11360 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11361 match(Set dst (MulF src1 src2));
11363 format %{ "FLD $src1\n\t"
11364 "FMUL $src2\n\t"
11365 "FSTP_S $dst" %}
11366 opcode(0xD8, 0x1); /* D8 C8+i */
11367 ins_encode( Push_Reg_F(src2),
11368 OpcReg_F(src1),
11369 Pop_Reg_F(dst) );
11370 ins_pipe( fpu_reg_reg_reg );
11371 %}
11374 // Spill to obtain 24-bit precision
11375 // Cisc-alternate to reg-reg multiply
11376 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11377 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11378 match(Set dst (MulF src1 (LoadF src2)));
11380 format %{ "FLD_S $src2\n\t"
11381 "FMUL $src1\n\t"
11382 "FSTP_S $dst" %}
11383 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11384 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11385 OpcReg_F(src1),
11386 Pop_Mem_F(dst) );
11387 ins_pipe( fpu_mem_reg_mem );
11388 %}
11389 //
11390 // This instruction does not round to 24-bits
11391 // Cisc-alternate to reg-reg multiply
11392 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11393 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11394 match(Set dst (MulF src1 (LoadF src2)));
11396 format %{ "FMUL $dst,$src1,$src2" %}
11397 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11398 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11399 OpcReg_F(src1),
11400 Pop_Reg_F(dst) );
11401 ins_pipe( fpu_reg_reg_mem );
11402 %}
11404 // Spill to obtain 24-bit precision
11405 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11406 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11407 match(Set dst (MulF src1 src2));
11409 format %{ "FMUL $dst,$src1,$src2" %}
11410 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11411 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11412 set_instruction_start,
11413 OpcP, RMopc_Mem(secondary,src1),
11414 Pop_Mem_F(dst) );
11415 ins_pipe( fpu_mem_mem_mem );
11416 %}
11418 // Spill to obtain 24-bit precision
11419 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11420 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11421 match(Set dst (MulF src1 src2));
11423 format %{ "FMULc $dst,$src1,$src2" %}
11424 opcode(0xD8, 0x1); /* D8 /1*/
11425 ins_encode( Push_Reg_F(src1),
11426 Opc_MemImm_F(src2),
11427 Pop_Mem_F(dst));
11428 ins_pipe( fpu_mem_reg_con );
11429 %}
11430 //
11431 // This instruction does not round to 24-bits
11432 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11433 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11434 match(Set dst (MulF src1 src2));
11436 format %{ "FMULc $dst. $src1, $src2" %}
11437 opcode(0xD8, 0x1); /* D8 /1*/
11438 ins_encode( Push_Reg_F(src1),
11439 Opc_MemImm_F(src2),
11440 Pop_Reg_F(dst));
11441 ins_pipe( fpu_reg_reg_con );
11442 %}
11445 //
11446 // MACRO1 -- subsume unshared load into mulF
11447 // This instruction does not round to 24-bits
11448 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11449 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11450 match(Set dst (MulF (LoadF mem1) src));
11452 format %{ "FLD $mem1 ===MACRO1===\n\t"
11453 "FMUL ST,$src\n\t"
11454 "FSTP $dst" %}
11455 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11456 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11457 OpcReg_F(src),
11458 Pop_Reg_F(dst) );
11459 ins_pipe( fpu_reg_reg_mem );
11460 %}
11461 //
11462 // MACRO2 -- addF a mulF which subsumed an unshared load
11463 // This instruction does not round to 24-bits
11464 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11465 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11466 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11467 ins_cost(95);
11469 format %{ "FLD $mem1 ===MACRO2===\n\t"
11470 "FMUL ST,$src1 subsume mulF left load\n\t"
11471 "FADD ST,$src2\n\t"
11472 "FSTP $dst" %}
11473 opcode(0xD9); /* LoadF D9 /0 */
11474 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11475 FMul_ST_reg(src1),
11476 FAdd_ST_reg(src2),
11477 Pop_Reg_F(dst) );
11478 ins_pipe( fpu_reg_mem_reg_reg );
11479 %}
11481 // MACRO3 -- addF a mulF
11482 // This instruction does not round to 24-bits. It is a '2-address'
11483 // instruction in that the result goes back to src2. This eliminates
11484 // a move from the macro; possibly the register allocator will have
11485 // to add it back (and maybe not).
11486 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11487 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11488 match(Set src2 (AddF (MulF src0 src1) src2));
11490 format %{ "FLD $src0 ===MACRO3===\n\t"
11491 "FMUL ST,$src1\n\t"
11492 "FADDP $src2,ST" %}
11493 opcode(0xD9); /* LoadF D9 /0 */
11494 ins_encode( Push_Reg_F(src0),
11495 FMul_ST_reg(src1),
11496 FAddP_reg_ST(src2) );
11497 ins_pipe( fpu_reg_reg_reg );
11498 %}
11500 // MACRO4 -- divF subF
11501 // This instruction does not round to 24-bits
11502 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11503 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11504 match(Set dst (DivF (SubF src2 src1) src3));
11506 format %{ "FLD $src2 ===MACRO4===\n\t"
11507 "FSUB ST,$src1\n\t"
11508 "FDIV ST,$src3\n\t"
11509 "FSTP $dst" %}
11510 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11511 ins_encode( Push_Reg_F(src2),
11512 subF_divF_encode(src1,src3),
11513 Pop_Reg_F(dst) );
11514 ins_pipe( fpu_reg_reg_reg_reg );
11515 %}
11517 // Spill to obtain 24-bit precision
11518 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11519 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11520 match(Set dst (DivF src1 src2));
11522 format %{ "FDIV $dst,$src1,$src2" %}
11523 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11524 ins_encode( Push_Reg_F(src1),
11525 OpcReg_F(src2),
11526 Pop_Mem_F(dst) );
11527 ins_pipe( fpu_mem_reg_reg );
11528 %}
11529 //
11530 // This instruction does not round to 24-bits
11531 instruct divF_reg(regF dst, regF src) %{
11532 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11533 match(Set dst (DivF dst src));
11535 format %{ "FDIV $dst,$src" %}
11536 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11537 ins_encode( Push_Reg_F(src),
11538 OpcP, RegOpc(dst) );
11539 ins_pipe( fpu_reg_reg );
11540 %}
11543 // Spill to obtain 24-bit precision
11544 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11545 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11546 match(Set dst (ModF src1 src2));
11547 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11549 format %{ "FMOD $dst,$src1,$src2" %}
11550 ins_encode( Push_Reg_Mod_D(src1, src2),
11551 emitModD(),
11552 Push_Result_Mod_D(src2),
11553 Pop_Mem_F(dst));
11554 ins_pipe( pipe_slow );
11555 %}
11556 //
11557 // This instruction does not round to 24-bits
11558 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11559 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11560 match(Set dst (ModF dst src));
11561 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11563 format %{ "FMOD $dst,$src" %}
11564 ins_encode(Push_Reg_Mod_D(dst, src),
11565 emitModD(),
11566 Push_Result_Mod_D(src),
11567 Pop_Reg_F(dst));
11568 ins_pipe( pipe_slow );
11569 %}
11571 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11572 predicate(UseSSE>=1);
11573 match(Set dst (ModF src0 src1));
11574 effect(KILL rax, KILL cr);
11575 format %{ "SUB ESP,4\t # FMOD\n"
11576 "\tMOVSS [ESP+0],$src1\n"
11577 "\tFLD_S [ESP+0]\n"
11578 "\tMOVSS [ESP+0],$src0\n"
11579 "\tFLD_S [ESP+0]\n"
11580 "loop:\tFPREM\n"
11581 "\tFWAIT\n"
11582 "\tFNSTSW AX\n"
11583 "\tSAHF\n"
11584 "\tJP loop\n"
11585 "\tFSTP_S [ESP+0]\n"
11586 "\tMOVSS $dst,[ESP+0]\n"
11587 "\tADD ESP,4\n"
11588 "\tFSTP ST0\t # Restore FPU Stack"
11589 %}
11590 ins_cost(250);
11591 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11592 ins_pipe( pipe_slow );
11593 %}
11596 //----------Arithmetic Conversion Instructions---------------------------------
11597 // The conversions operations are all Alpha sorted. Please keep it that way!
11599 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11600 predicate(UseSSE==0);
11601 match(Set dst (RoundFloat src));
11602 ins_cost(125);
11603 format %{ "FST_S $dst,$src\t# F-round" %}
11604 ins_encode( Pop_Mem_Reg_F(dst, src) );
11605 ins_pipe( fpu_mem_reg );
11606 %}
11608 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11609 predicate(UseSSE<=1);
11610 match(Set dst (RoundDouble src));
11611 ins_cost(125);
11612 format %{ "FST_D $dst,$src\t# D-round" %}
11613 ins_encode( Pop_Mem_Reg_D(dst, src) );
11614 ins_pipe( fpu_mem_reg );
11615 %}
11617 // Force rounding to 24-bit precision and 6-bit exponent
11618 instruct convD2F_reg(stackSlotF dst, regD src) %{
11619 predicate(UseSSE==0);
11620 match(Set dst (ConvD2F src));
11621 format %{ "FST_S $dst,$src\t# F-round" %}
11622 expand %{
11623 roundFloat_mem_reg(dst,src);
11624 %}
11625 %}
11627 // Force rounding to 24-bit precision and 6-bit exponent
11628 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11629 predicate(UseSSE==1);
11630 match(Set dst (ConvD2F src));
11631 effect( KILL cr );
11632 format %{ "SUB ESP,4\n\t"
11633 "FST_S [ESP],$src\t# F-round\n\t"
11634 "MOVSS $dst,[ESP]\n\t"
11635 "ADD ESP,4" %}
11636 ins_encode( D2X_encoding(dst, src) );
11637 ins_pipe( pipe_slow );
11638 %}
11640 // Force rounding double precision to single precision
11641 instruct convXD2X_reg(regX dst, regXD src) %{
11642 predicate(UseSSE>=2);
11643 match(Set dst (ConvD2F src));
11644 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11645 opcode(0xF2, 0x0F, 0x5A);
11646 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11647 ins_pipe( pipe_slow );
11648 %}
11650 instruct convF2D_reg_reg(regD dst, regF src) %{
11651 predicate(UseSSE==0);
11652 match(Set dst (ConvF2D src));
11653 format %{ "FST_S $dst,$src\t# D-round" %}
11654 ins_encode( Pop_Reg_Reg_D(dst, src));
11655 ins_pipe( fpu_reg_reg );
11656 %}
11658 instruct convF2D_reg(stackSlotD dst, regF src) %{
11659 predicate(UseSSE==1);
11660 match(Set dst (ConvF2D src));
11661 format %{ "FST_D $dst,$src\t# D-round" %}
11662 expand %{
11663 roundDouble_mem_reg(dst,src);
11664 %}
11665 %}
11667 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11668 predicate(UseSSE==1);
11669 match(Set dst (ConvF2D src));
11670 effect( KILL cr );
11671 format %{ "SUB ESP,4\n\t"
11672 "MOVSS [ESP] $src\n\t"
11673 "FLD_S [ESP]\n\t"
11674 "ADD ESP,4\n\t"
11675 "FSTP $dst\t# D-round" %}
11676 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11677 ins_pipe( pipe_slow );
11678 %}
11680 instruct convX2XD_reg(regXD dst, regX src) %{
11681 predicate(UseSSE>=2);
11682 match(Set dst (ConvF2D src));
11683 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11684 opcode(0xF3, 0x0F, 0x5A);
11685 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11686 ins_pipe( pipe_slow );
11687 %}
11689 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11690 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11691 predicate(UseSSE<=1);
11692 match(Set dst (ConvD2I src));
11693 effect( KILL tmp, KILL cr );
11694 format %{ "FLD $src\t# Convert double to int \n\t"
11695 "FLDCW trunc mode\n\t"
11696 "SUB ESP,4\n\t"
11697 "FISTp [ESP + #0]\n\t"
11698 "FLDCW std/24-bit mode\n\t"
11699 "POP EAX\n\t"
11700 "CMP EAX,0x80000000\n\t"
11701 "JNE,s fast\n\t"
11702 "FLD_D $src\n\t"
11703 "CALL d2i_wrapper\n"
11704 "fast:" %}
11705 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11706 ins_pipe( pipe_slow );
11707 %}
11709 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11710 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11711 predicate(UseSSE>=2);
11712 match(Set dst (ConvD2I src));
11713 effect( KILL tmp, KILL cr );
11714 format %{ "CVTTSD2SI $dst, $src\n\t"
11715 "CMP $dst,0x80000000\n\t"
11716 "JNE,s fast\n\t"
11717 "SUB ESP, 8\n\t"
11718 "MOVSD [ESP], $src\n\t"
11719 "FLD_D [ESP]\n\t"
11720 "ADD ESP, 8\n\t"
11721 "CALL d2i_wrapper\n"
11722 "fast:" %}
11723 opcode(0x1); // double-precision conversion
11724 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11725 ins_pipe( pipe_slow );
11726 %}
11728 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11729 predicate(UseSSE<=1);
11730 match(Set dst (ConvD2L src));
11731 effect( KILL cr );
11732 format %{ "FLD $src\t# Convert double to long\n\t"
11733 "FLDCW trunc mode\n\t"
11734 "SUB ESP,8\n\t"
11735 "FISTp [ESP + #0]\n\t"
11736 "FLDCW std/24-bit mode\n\t"
11737 "POP EAX\n\t"
11738 "POP EDX\n\t"
11739 "CMP EDX,0x80000000\n\t"
11740 "JNE,s fast\n\t"
11741 "TEST EAX,EAX\n\t"
11742 "JNE,s fast\n\t"
11743 "FLD $src\n\t"
11744 "CALL d2l_wrapper\n"
11745 "fast:" %}
11746 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11747 ins_pipe( pipe_slow );
11748 %}
11750 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11751 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11752 predicate (UseSSE>=2);
11753 match(Set dst (ConvD2L src));
11754 effect( KILL cr );
11755 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11756 "MOVSD [ESP],$src\n\t"
11757 "FLD_D [ESP]\n\t"
11758 "FLDCW trunc mode\n\t"
11759 "FISTp [ESP + #0]\n\t"
11760 "FLDCW std/24-bit mode\n\t"
11761 "POP EAX\n\t"
11762 "POP EDX\n\t"
11763 "CMP EDX,0x80000000\n\t"
11764 "JNE,s fast\n\t"
11765 "TEST EAX,EAX\n\t"
11766 "JNE,s fast\n\t"
11767 "SUB ESP,8\n\t"
11768 "MOVSD [ESP],$src\n\t"
11769 "FLD_D [ESP]\n\t"
11770 "CALL d2l_wrapper\n"
11771 "fast:" %}
11772 ins_encode( XD2L_encoding(src) );
11773 ins_pipe( pipe_slow );
11774 %}
11776 // Convert a double to an int. Java semantics require we do complex
11777 // manglations in the corner cases. So we set the rounding mode to
11778 // 'zero', store the darned double down as an int, and reset the
11779 // rounding mode to 'nearest'. The hardware stores a flag value down
11780 // if we would overflow or converted a NAN; we check for this and
11781 // and go the slow path if needed.
11782 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11783 predicate(UseSSE==0);
11784 match(Set dst (ConvF2I src));
11785 effect( KILL tmp, KILL cr );
11786 format %{ "FLD $src\t# Convert float to int \n\t"
11787 "FLDCW trunc mode\n\t"
11788 "SUB ESP,4\n\t"
11789 "FISTp [ESP + #0]\n\t"
11790 "FLDCW std/24-bit mode\n\t"
11791 "POP EAX\n\t"
11792 "CMP EAX,0x80000000\n\t"
11793 "JNE,s fast\n\t"
11794 "FLD $src\n\t"
11795 "CALL d2i_wrapper\n"
11796 "fast:" %}
11797 // D2I_encoding works for F2I
11798 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11799 ins_pipe( pipe_slow );
11800 %}
11802 // Convert a float in xmm to an int reg.
11803 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11804 predicate(UseSSE>=1);
11805 match(Set dst (ConvF2I src));
11806 effect( KILL tmp, KILL cr );
11807 format %{ "CVTTSS2SI $dst, $src\n\t"
11808 "CMP $dst,0x80000000\n\t"
11809 "JNE,s fast\n\t"
11810 "SUB ESP, 4\n\t"
11811 "MOVSS [ESP], $src\n\t"
11812 "FLD [ESP]\n\t"
11813 "ADD ESP, 4\n\t"
11814 "CALL d2i_wrapper\n"
11815 "fast:" %}
11816 opcode(0x0); // single-precision conversion
11817 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11818 ins_pipe( pipe_slow );
11819 %}
11821 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11822 predicate(UseSSE==0);
11823 match(Set dst (ConvF2L src));
11824 effect( KILL cr );
11825 format %{ "FLD $src\t# Convert float to long\n\t"
11826 "FLDCW trunc mode\n\t"
11827 "SUB ESP,8\n\t"
11828 "FISTp [ESP + #0]\n\t"
11829 "FLDCW std/24-bit mode\n\t"
11830 "POP EAX\n\t"
11831 "POP EDX\n\t"
11832 "CMP EDX,0x80000000\n\t"
11833 "JNE,s fast\n\t"
11834 "TEST EAX,EAX\n\t"
11835 "JNE,s fast\n\t"
11836 "FLD $src\n\t"
11837 "CALL d2l_wrapper\n"
11838 "fast:" %}
11839 // D2L_encoding works for F2L
11840 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11841 ins_pipe( pipe_slow );
11842 %}
11844 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11845 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11846 predicate (UseSSE>=1);
11847 match(Set dst (ConvF2L src));
11848 effect( KILL cr );
11849 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11850 "MOVSS [ESP],$src\n\t"
11851 "FLD_S [ESP]\n\t"
11852 "FLDCW trunc mode\n\t"
11853 "FISTp [ESP + #0]\n\t"
11854 "FLDCW std/24-bit mode\n\t"
11855 "POP EAX\n\t"
11856 "POP EDX\n\t"
11857 "CMP EDX,0x80000000\n\t"
11858 "JNE,s fast\n\t"
11859 "TEST EAX,EAX\n\t"
11860 "JNE,s fast\n\t"
11861 "SUB ESP,4\t# Convert float to long\n\t"
11862 "MOVSS [ESP],$src\n\t"
11863 "FLD_S [ESP]\n\t"
11864 "ADD ESP,4\n\t"
11865 "CALL d2l_wrapper\n"
11866 "fast:" %}
11867 ins_encode( X2L_encoding(src) );
11868 ins_pipe( pipe_slow );
11869 %}
11871 instruct convI2D_reg(regD dst, stackSlotI src) %{
11872 predicate( UseSSE<=1 );
11873 match(Set dst (ConvI2D src));
11874 format %{ "FILD $src\n\t"
11875 "FSTP $dst" %}
11876 opcode(0xDB, 0x0); /* DB /0 */
11877 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11878 ins_pipe( fpu_reg_mem );
11879 %}
11881 instruct convI2XD_reg(regXD dst, eRegI src) %{
11882 predicate( UseSSE>=2 && !UseXmmI2D );
11883 match(Set dst (ConvI2D src));
11884 format %{ "CVTSI2SD $dst,$src" %}
11885 opcode(0xF2, 0x0F, 0x2A);
11886 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11887 ins_pipe( pipe_slow );
11888 %}
11890 instruct convI2XD_mem(regXD dst, memory mem) %{
11891 predicate( UseSSE>=2 );
11892 match(Set dst (ConvI2D (LoadI mem)));
11893 format %{ "CVTSI2SD $dst,$mem" %}
11894 opcode(0xF2, 0x0F, 0x2A);
11895 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11896 ins_pipe( pipe_slow );
11897 %}
11899 instruct convXI2XD_reg(regXD dst, eRegI src)
11900 %{
11901 predicate( UseSSE>=2 && UseXmmI2D );
11902 match(Set dst (ConvI2D src));
11904 format %{ "MOVD $dst,$src\n\t"
11905 "CVTDQ2PD $dst,$dst\t# i2d" %}
11906 ins_encode %{
11907 __ movdl($dst$$XMMRegister, $src$$Register);
11908 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11909 %}
11910 ins_pipe(pipe_slow); // XXX
11911 %}
11913 instruct convI2D_mem(regD dst, memory mem) %{
11914 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11915 match(Set dst (ConvI2D (LoadI mem)));
11916 format %{ "FILD $mem\n\t"
11917 "FSTP $dst" %}
11918 opcode(0xDB); /* DB /0 */
11919 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11920 Pop_Reg_D(dst));
11921 ins_pipe( fpu_reg_mem );
11922 %}
11924 // Convert a byte to a float; no rounding step needed.
11925 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11926 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11927 match(Set dst (ConvI2F src));
11928 format %{ "FILD $src\n\t"
11929 "FSTP $dst" %}
11931 opcode(0xDB, 0x0); /* DB /0 */
11932 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11933 ins_pipe( fpu_reg_mem );
11934 %}
11936 // In 24-bit mode, force exponent rounding by storing back out
11937 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11938 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11939 match(Set dst (ConvI2F src));
11940 ins_cost(200);
11941 format %{ "FILD $src\n\t"
11942 "FSTP_S $dst" %}
11943 opcode(0xDB, 0x0); /* DB /0 */
11944 ins_encode( Push_Mem_I(src),
11945 Pop_Mem_F(dst));
11946 ins_pipe( fpu_mem_mem );
11947 %}
11949 // In 24-bit mode, force exponent rounding by storing back out
11950 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11951 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11952 match(Set dst (ConvI2F (LoadI mem)));
11953 ins_cost(200);
11954 format %{ "FILD $mem\n\t"
11955 "FSTP_S $dst" %}
11956 opcode(0xDB); /* DB /0 */
11957 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11958 Pop_Mem_F(dst));
11959 ins_pipe( fpu_mem_mem );
11960 %}
11962 // This instruction does not round to 24-bits
11963 instruct convI2F_reg(regF dst, stackSlotI src) %{
11964 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11965 match(Set dst (ConvI2F src));
11966 format %{ "FILD $src\n\t"
11967 "FSTP $dst" %}
11968 opcode(0xDB, 0x0); /* DB /0 */
11969 ins_encode( Push_Mem_I(src),
11970 Pop_Reg_F(dst));
11971 ins_pipe( fpu_reg_mem );
11972 %}
11974 // This instruction does not round to 24-bits
11975 instruct convI2F_mem(regF dst, memory mem) %{
11976 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11977 match(Set dst (ConvI2F (LoadI mem)));
11978 format %{ "FILD $mem\n\t"
11979 "FSTP $dst" %}
11980 opcode(0xDB); /* DB /0 */
11981 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11982 Pop_Reg_F(dst));
11983 ins_pipe( fpu_reg_mem );
11984 %}
11986 // Convert an int to a float in xmm; no rounding step needed.
11987 instruct convI2X_reg(regX dst, eRegI src) %{
11988 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11989 match(Set dst (ConvI2F src));
11990 format %{ "CVTSI2SS $dst, $src" %}
11992 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11993 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11994 ins_pipe( pipe_slow );
11995 %}
11997 instruct convXI2X_reg(regX dst, eRegI src)
11998 %{
11999 predicate( UseSSE>=2 && UseXmmI2F );
12000 match(Set dst (ConvI2F src));
12002 format %{ "MOVD $dst,$src\n\t"
12003 "CVTDQ2PS $dst,$dst\t# i2f" %}
12004 ins_encode %{
12005 __ movdl($dst$$XMMRegister, $src$$Register);
12006 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
12007 %}
12008 ins_pipe(pipe_slow); // XXX
12009 %}
12011 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
12012 match(Set dst (ConvI2L src));
12013 effect(KILL cr);
12014 ins_cost(375);
12015 format %{ "MOV $dst.lo,$src\n\t"
12016 "MOV $dst.hi,$src\n\t"
12017 "SAR $dst.hi,31" %}
12018 ins_encode(convert_int_long(dst,src));
12019 ins_pipe( ialu_reg_reg_long );
12020 %}
12022 // Zero-extend convert int to long
12023 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
12024 match(Set dst (AndL (ConvI2L src) mask) );
12025 effect( KILL flags );
12026 ins_cost(250);
12027 format %{ "MOV $dst.lo,$src\n\t"
12028 "XOR $dst.hi,$dst.hi" %}
12029 opcode(0x33); // XOR
12030 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12031 ins_pipe( ialu_reg_reg_long );
12032 %}
12034 // Zero-extend long
12035 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
12036 match(Set dst (AndL src mask) );
12037 effect( KILL flags );
12038 ins_cost(250);
12039 format %{ "MOV $dst.lo,$src.lo\n\t"
12040 "XOR $dst.hi,$dst.hi\n\t" %}
12041 opcode(0x33); // XOR
12042 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
12043 ins_pipe( ialu_reg_reg_long );
12044 %}
12046 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
12047 predicate (UseSSE<=1);
12048 match(Set dst (ConvL2D src));
12049 effect( KILL cr );
12050 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12051 "PUSH $src.lo\n\t"
12052 "FILD ST,[ESP + #0]\n\t"
12053 "ADD ESP,8\n\t"
12054 "FSTP_D $dst\t# D-round" %}
12055 opcode(0xDF, 0x5); /* DF /5 */
12056 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
12057 ins_pipe( pipe_slow );
12058 %}
12060 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
12061 predicate (UseSSE>=2);
12062 match(Set dst (ConvL2D src));
12063 effect( KILL cr );
12064 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
12065 "PUSH $src.lo\n\t"
12066 "FILD_D [ESP]\n\t"
12067 "FSTP_D [ESP]\n\t"
12068 "MOVSD $dst,[ESP]\n\t"
12069 "ADD ESP,8" %}
12070 opcode(0xDF, 0x5); /* DF /5 */
12071 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
12072 ins_pipe( pipe_slow );
12073 %}
12075 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
12076 predicate (UseSSE>=1);
12077 match(Set dst (ConvL2F src));
12078 effect( KILL cr );
12079 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12080 "PUSH $src.lo\n\t"
12081 "FILD_D [ESP]\n\t"
12082 "FSTP_S [ESP]\n\t"
12083 "MOVSS $dst,[ESP]\n\t"
12084 "ADD ESP,8" %}
12085 opcode(0xDF, 0x5); /* DF /5 */
12086 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
12087 ins_pipe( pipe_slow );
12088 %}
12090 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
12091 match(Set dst (ConvL2F src));
12092 effect( KILL cr );
12093 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
12094 "PUSH $src.lo\n\t"
12095 "FILD ST,[ESP + #0]\n\t"
12096 "ADD ESP,8\n\t"
12097 "FSTP_S $dst\t# F-round" %}
12098 opcode(0xDF, 0x5); /* DF /5 */
12099 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
12100 ins_pipe( pipe_slow );
12101 %}
12103 instruct convL2I_reg( eRegI dst, eRegL src ) %{
12104 match(Set dst (ConvL2I src));
12105 effect( DEF dst, USE src );
12106 format %{ "MOV $dst,$src.lo" %}
12107 ins_encode(enc_CopyL_Lo(dst,src));
12108 ins_pipe( ialu_reg_reg );
12109 %}
12112 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
12113 match(Set dst (MoveF2I src));
12114 effect( DEF dst, USE src );
12115 ins_cost(100);
12116 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
12117 opcode(0x8B);
12118 ins_encode( OpcP, RegMem(dst,src));
12119 ins_pipe( ialu_reg_mem );
12120 %}
12122 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12123 predicate(UseSSE==0);
12124 match(Set dst (MoveF2I src));
12125 effect( DEF dst, USE src );
12127 ins_cost(125);
12128 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
12129 ins_encode( Pop_Mem_Reg_F(dst, src) );
12130 ins_pipe( fpu_mem_reg );
12131 %}
12133 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
12134 predicate(UseSSE>=1);
12135 match(Set dst (MoveF2I src));
12136 effect( DEF dst, USE src );
12138 ins_cost(95);
12139 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
12140 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
12141 ins_pipe( pipe_slow );
12142 %}
12144 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
12145 predicate(UseSSE>=2);
12146 match(Set dst (MoveF2I src));
12147 effect( DEF dst, USE src );
12148 ins_cost(85);
12149 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
12150 ins_encode( MovX2I_reg(dst, src));
12151 ins_pipe( pipe_slow );
12152 %}
12154 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
12155 match(Set dst (MoveI2F src));
12156 effect( DEF dst, USE src );
12158 ins_cost(100);
12159 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
12160 opcode(0x89);
12161 ins_encode( OpcPRegSS( dst, src ) );
12162 ins_pipe( ialu_mem_reg );
12163 %}
12166 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12167 predicate(UseSSE==0);
12168 match(Set dst (MoveI2F src));
12169 effect(DEF dst, USE src);
12171 ins_cost(125);
12172 format %{ "FLD_S $src\n\t"
12173 "FSTP $dst\t# MoveI2F_stack_reg" %}
12174 opcode(0xD9); /* D9 /0, FLD m32real */
12175 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12176 Pop_Reg_F(dst) );
12177 ins_pipe( fpu_reg_mem );
12178 %}
12180 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
12181 predicate(UseSSE>=1);
12182 match(Set dst (MoveI2F src));
12183 effect( DEF dst, USE src );
12185 ins_cost(95);
12186 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
12187 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12188 ins_pipe( pipe_slow );
12189 %}
12191 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
12192 predicate(UseSSE>=2);
12193 match(Set dst (MoveI2F src));
12194 effect( DEF dst, USE src );
12196 ins_cost(85);
12197 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
12198 ins_encode( MovI2X_reg(dst, src) );
12199 ins_pipe( pipe_slow );
12200 %}
12202 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
12203 match(Set dst (MoveD2L src));
12204 effect(DEF dst, USE src);
12206 ins_cost(250);
12207 format %{ "MOV $dst.lo,$src\n\t"
12208 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
12209 opcode(0x8B, 0x8B);
12210 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
12211 ins_pipe( ialu_mem_long_reg );
12212 %}
12214 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12215 predicate(UseSSE<=1);
12216 match(Set dst (MoveD2L src));
12217 effect(DEF dst, USE src);
12219 ins_cost(125);
12220 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
12221 ins_encode( Pop_Mem_Reg_D(dst, src) );
12222 ins_pipe( fpu_mem_reg );
12223 %}
12225 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
12226 predicate(UseSSE>=2);
12227 match(Set dst (MoveD2L src));
12228 effect(DEF dst, USE src);
12229 ins_cost(95);
12231 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
12232 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
12233 ins_pipe( pipe_slow );
12234 %}
12236 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
12237 predicate(UseSSE>=2);
12238 match(Set dst (MoveD2L src));
12239 effect(DEF dst, USE src, TEMP tmp);
12240 ins_cost(85);
12241 format %{ "MOVD $dst.lo,$src\n\t"
12242 "PSHUFLW $tmp,$src,0x4E\n\t"
12243 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
12244 ins_encode( MovXD2L_reg(dst, src, tmp) );
12245 ins_pipe( pipe_slow );
12246 %}
12248 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
12249 match(Set dst (MoveL2D src));
12250 effect(DEF dst, USE src);
12252 ins_cost(200);
12253 format %{ "MOV $dst,$src.lo\n\t"
12254 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
12255 opcode(0x89, 0x89);
12256 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
12257 ins_pipe( ialu_mem_long_reg );
12258 %}
12261 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12262 predicate(UseSSE<=1);
12263 match(Set dst (MoveL2D src));
12264 effect(DEF dst, USE src);
12265 ins_cost(125);
12267 format %{ "FLD_D $src\n\t"
12268 "FSTP $dst\t# MoveL2D_stack_reg" %}
12269 opcode(0xDD); /* DD /0, FLD m64real */
12270 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
12271 Pop_Reg_D(dst) );
12272 ins_pipe( fpu_reg_mem );
12273 %}
12276 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12277 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12278 match(Set dst (MoveL2D src));
12279 effect(DEF dst, USE src);
12281 ins_cost(95);
12282 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12283 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12284 ins_pipe( pipe_slow );
12285 %}
12287 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12288 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12289 match(Set dst (MoveL2D src));
12290 effect(DEF dst, USE src);
12292 ins_cost(95);
12293 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12294 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12295 ins_pipe( pipe_slow );
12296 %}
12298 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12299 predicate(UseSSE>=2);
12300 match(Set dst (MoveL2D src));
12301 effect(TEMP dst, USE src, TEMP tmp);
12302 ins_cost(85);
12303 format %{ "MOVD $dst,$src.lo\n\t"
12304 "MOVD $tmp,$src.hi\n\t"
12305 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12306 ins_encode( MovL2XD_reg(dst, src, tmp) );
12307 ins_pipe( pipe_slow );
12308 %}
12310 // Replicate scalar to packed byte (1 byte) values in xmm
12311 instruct Repl8B_reg(regXD dst, regXD src) %{
12312 predicate(UseSSE>=2);
12313 match(Set dst (Replicate8B src));
12314 format %{ "MOVDQA $dst,$src\n\t"
12315 "PUNPCKLBW $dst,$dst\n\t"
12316 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12317 ins_encode( pshufd_8x8(dst, src));
12318 ins_pipe( pipe_slow );
12319 %}
12321 // Replicate scalar to packed byte (1 byte) values in xmm
12322 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12323 predicate(UseSSE>=2);
12324 match(Set dst (Replicate8B src));
12325 format %{ "MOVD $dst,$src\n\t"
12326 "PUNPCKLBW $dst,$dst\n\t"
12327 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12328 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12329 ins_pipe( pipe_slow );
12330 %}
12332 // Replicate scalar zero to packed byte (1 byte) values in xmm
12333 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12334 predicate(UseSSE>=2);
12335 match(Set dst (Replicate8B zero));
12336 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12337 ins_encode( pxor(dst, dst));
12338 ins_pipe( fpu_reg_reg );
12339 %}
12341 // Replicate scalar to packed shore (2 byte) values in xmm
12342 instruct Repl4S_reg(regXD dst, regXD src) %{
12343 predicate(UseSSE>=2);
12344 match(Set dst (Replicate4S src));
12345 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12346 ins_encode( pshufd_4x16(dst, src));
12347 ins_pipe( fpu_reg_reg );
12348 %}
12350 // Replicate scalar to packed shore (2 byte) values in xmm
12351 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12352 predicate(UseSSE>=2);
12353 match(Set dst (Replicate4S src));
12354 format %{ "MOVD $dst,$src\n\t"
12355 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12356 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12357 ins_pipe( fpu_reg_reg );
12358 %}
12360 // Replicate scalar zero to packed short (2 byte) values in xmm
12361 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12362 predicate(UseSSE>=2);
12363 match(Set dst (Replicate4S zero));
12364 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12365 ins_encode( pxor(dst, dst));
12366 ins_pipe( fpu_reg_reg );
12367 %}
12369 // Replicate scalar to packed char (2 byte) values in xmm
12370 instruct Repl4C_reg(regXD dst, regXD src) %{
12371 predicate(UseSSE>=2);
12372 match(Set dst (Replicate4C src));
12373 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12374 ins_encode( pshufd_4x16(dst, src));
12375 ins_pipe( fpu_reg_reg );
12376 %}
12378 // Replicate scalar to packed char (2 byte) values in xmm
12379 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12380 predicate(UseSSE>=2);
12381 match(Set dst (Replicate4C src));
12382 format %{ "MOVD $dst,$src\n\t"
12383 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12384 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12385 ins_pipe( fpu_reg_reg );
12386 %}
12388 // Replicate scalar zero to packed char (2 byte) values in xmm
12389 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12390 predicate(UseSSE>=2);
12391 match(Set dst (Replicate4C zero));
12392 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12393 ins_encode( pxor(dst, dst));
12394 ins_pipe( fpu_reg_reg );
12395 %}
12397 // Replicate scalar to packed integer (4 byte) values in xmm
12398 instruct Repl2I_reg(regXD dst, regXD src) %{
12399 predicate(UseSSE>=2);
12400 match(Set dst (Replicate2I src));
12401 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12402 ins_encode( pshufd(dst, src, 0x00));
12403 ins_pipe( fpu_reg_reg );
12404 %}
12406 // Replicate scalar to packed integer (4 byte) values in xmm
12407 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12408 predicate(UseSSE>=2);
12409 match(Set dst (Replicate2I src));
12410 format %{ "MOVD $dst,$src\n\t"
12411 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12412 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12413 ins_pipe( fpu_reg_reg );
12414 %}
12416 // Replicate scalar zero to packed integer (2 byte) values in xmm
12417 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12418 predicate(UseSSE>=2);
12419 match(Set dst (Replicate2I zero));
12420 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12421 ins_encode( pxor(dst, dst));
12422 ins_pipe( fpu_reg_reg );
12423 %}
12425 // Replicate scalar to packed single precision floating point values in xmm
12426 instruct Repl2F_reg(regXD dst, regXD src) %{
12427 predicate(UseSSE>=2);
12428 match(Set dst (Replicate2F src));
12429 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12430 ins_encode( pshufd(dst, src, 0xe0));
12431 ins_pipe( fpu_reg_reg );
12432 %}
12434 // Replicate scalar to packed single precision floating point values in xmm
12435 instruct Repl2F_regX(regXD dst, regX src) %{
12436 predicate(UseSSE>=2);
12437 match(Set dst (Replicate2F src));
12438 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12439 ins_encode( pshufd(dst, src, 0xe0));
12440 ins_pipe( fpu_reg_reg );
12441 %}
12443 // Replicate scalar to packed single precision floating point values in xmm
12444 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12445 predicate(UseSSE>=2);
12446 match(Set dst (Replicate2F zero));
12447 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12448 ins_encode( pxor(dst, dst));
12449 ins_pipe( fpu_reg_reg );
12450 %}
12452 // =======================================================================
12453 // fast clearing of an array
12454 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12455 match(Set dummy (ClearArray cnt base));
12456 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12457 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12458 "XOR EAX,EAX\n\t"
12459 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12460 opcode(0,0x4);
12461 ins_encode( Opcode(0xD1), RegOpc(ECX),
12462 OpcRegReg(0x33,EAX,EAX),
12463 Opcode(0xF3), Opcode(0xAB) );
12464 ins_pipe( pipe_slow );
12465 %}
12467 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eBXRegI cnt2,
12468 eAXRegI result, regXD tmp1, regXD tmp2, eFlagsReg cr) %{
12469 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12470 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12472 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %}
12473 ins_encode %{
12474 __ string_compare($str1$$Register, $str2$$Register,
12475 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12476 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12477 %}
12478 ins_pipe( pipe_slow );
12479 %}
12481 // fast string equals
12482 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
12483 regXD tmp1, regXD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
12484 match(Set result (StrEquals (Binary str1 str2) cnt));
12485 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12487 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12488 ins_encode %{
12489 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
12490 $cnt$$Register, $result$$Register, $tmp3$$Register,
12491 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12492 %}
12493 ins_pipe( pipe_slow );
12494 %}
12496 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
12497 eBXRegI result, regXD tmp1, eCXRegI tmp2, eFlagsReg cr) %{
12498 predicate(UseSSE42Intrinsics);
12499 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12500 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr);
12502 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp2, $tmp1" %}
12503 ins_encode %{
12504 __ string_indexof($str1$$Register, $str2$$Register,
12505 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12506 $tmp1$$XMMRegister, $tmp2$$Register);
12507 %}
12508 ins_pipe( pipe_slow );
12509 %}
12511 // fast array equals
12512 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
12513 regXD tmp1, regXD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
12514 %{
12515 match(Set result (AryEq ary1 ary2));
12516 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12517 //ins_cost(300);
12519 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12520 ins_encode %{
12521 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
12522 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12523 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
12524 %}
12525 ins_pipe( pipe_slow );
12526 %}
12528 //----------Control Flow Instructions------------------------------------------
12529 // Signed compare Instructions
12530 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12531 match(Set cr (CmpI op1 op2));
12532 effect( DEF cr, USE op1, USE op2 );
12533 format %{ "CMP $op1,$op2" %}
12534 opcode(0x3B); /* Opcode 3B /r */
12535 ins_encode( OpcP, RegReg( op1, op2) );
12536 ins_pipe( ialu_cr_reg_reg );
12537 %}
12539 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12540 match(Set cr (CmpI op1 op2));
12541 effect( DEF cr, USE op1 );
12542 format %{ "CMP $op1,$op2" %}
12543 opcode(0x81,0x07); /* Opcode 81 /7 */
12544 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12545 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12546 ins_pipe( ialu_cr_reg_imm );
12547 %}
12549 // Cisc-spilled version of cmpI_eReg
12550 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12551 match(Set cr (CmpI op1 (LoadI op2)));
12553 format %{ "CMP $op1,$op2" %}
12554 ins_cost(500);
12555 opcode(0x3B); /* Opcode 3B /r */
12556 ins_encode( OpcP, RegMem( op1, op2) );
12557 ins_pipe( ialu_cr_reg_mem );
12558 %}
12560 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12561 match(Set cr (CmpI src zero));
12562 effect( DEF cr, USE src );
12564 format %{ "TEST $src,$src" %}
12565 opcode(0x85);
12566 ins_encode( OpcP, RegReg( src, src ) );
12567 ins_pipe( ialu_cr_reg_imm );
12568 %}
12570 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12571 match(Set cr (CmpI (AndI src con) zero));
12573 format %{ "TEST $src,$con" %}
12574 opcode(0xF7,0x00);
12575 ins_encode( OpcP, RegOpc(src), Con32(con) );
12576 ins_pipe( ialu_cr_reg_imm );
12577 %}
12579 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12580 match(Set cr (CmpI (AndI src mem) zero));
12582 format %{ "TEST $src,$mem" %}
12583 opcode(0x85);
12584 ins_encode( OpcP, RegMem( src, mem ) );
12585 ins_pipe( ialu_cr_reg_mem );
12586 %}
12588 // Unsigned compare Instructions; really, same as signed except they
12589 // produce an eFlagsRegU instead of eFlagsReg.
12590 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12591 match(Set cr (CmpU op1 op2));
12593 format %{ "CMPu $op1,$op2" %}
12594 opcode(0x3B); /* Opcode 3B /r */
12595 ins_encode( OpcP, RegReg( op1, op2) );
12596 ins_pipe( ialu_cr_reg_reg );
12597 %}
12599 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12600 match(Set cr (CmpU op1 op2));
12602 format %{ "CMPu $op1,$op2" %}
12603 opcode(0x81,0x07); /* Opcode 81 /7 */
12604 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12605 ins_pipe( ialu_cr_reg_imm );
12606 %}
12608 // // Cisc-spilled version of cmpU_eReg
12609 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12610 match(Set cr (CmpU op1 (LoadI op2)));
12612 format %{ "CMPu $op1,$op2" %}
12613 ins_cost(500);
12614 opcode(0x3B); /* Opcode 3B /r */
12615 ins_encode( OpcP, RegMem( op1, op2) );
12616 ins_pipe( ialu_cr_reg_mem );
12617 %}
12619 // // Cisc-spilled version of cmpU_eReg
12620 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12621 // match(Set cr (CmpU (LoadI op1) op2));
12622 //
12623 // format %{ "CMPu $op1,$op2" %}
12624 // ins_cost(500);
12625 // opcode(0x39); /* Opcode 39 /r */
12626 // ins_encode( OpcP, RegMem( op1, op2) );
12627 //%}
12629 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12630 match(Set cr (CmpU src zero));
12632 format %{ "TESTu $src,$src" %}
12633 opcode(0x85);
12634 ins_encode( OpcP, RegReg( src, src ) );
12635 ins_pipe( ialu_cr_reg_imm );
12636 %}
12638 // Unsigned pointer compare Instructions
12639 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12640 match(Set cr (CmpP op1 op2));
12642 format %{ "CMPu $op1,$op2" %}
12643 opcode(0x3B); /* Opcode 3B /r */
12644 ins_encode( OpcP, RegReg( op1, op2) );
12645 ins_pipe( ialu_cr_reg_reg );
12646 %}
12648 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12649 match(Set cr (CmpP op1 op2));
12651 format %{ "CMPu $op1,$op2" %}
12652 opcode(0x81,0x07); /* Opcode 81 /7 */
12653 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12654 ins_pipe( ialu_cr_reg_imm );
12655 %}
12657 // // Cisc-spilled version of cmpP_eReg
12658 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12659 match(Set cr (CmpP op1 (LoadP op2)));
12661 format %{ "CMPu $op1,$op2" %}
12662 ins_cost(500);
12663 opcode(0x3B); /* Opcode 3B /r */
12664 ins_encode( OpcP, RegMem( op1, op2) );
12665 ins_pipe( ialu_cr_reg_mem );
12666 %}
12668 // // Cisc-spilled version of cmpP_eReg
12669 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12670 // match(Set cr (CmpP (LoadP op1) op2));
12671 //
12672 // format %{ "CMPu $op1,$op2" %}
12673 // ins_cost(500);
12674 // opcode(0x39); /* Opcode 39 /r */
12675 // ins_encode( OpcP, RegMem( op1, op2) );
12676 //%}
12678 // Compare raw pointer (used in out-of-heap check).
12679 // Only works because non-oop pointers must be raw pointers
12680 // and raw pointers have no anti-dependencies.
12681 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12682 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12683 match(Set cr (CmpP op1 (LoadP op2)));
12685 format %{ "CMPu $op1,$op2" %}
12686 opcode(0x3B); /* Opcode 3B /r */
12687 ins_encode( OpcP, RegMem( op1, op2) );
12688 ins_pipe( ialu_cr_reg_mem );
12689 %}
12691 //
12692 // This will generate a signed flags result. This should be ok
12693 // since any compare to a zero should be eq/neq.
12694 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12695 match(Set cr (CmpP src zero));
12697 format %{ "TEST $src,$src" %}
12698 opcode(0x85);
12699 ins_encode( OpcP, RegReg( src, src ) );
12700 ins_pipe( ialu_cr_reg_imm );
12701 %}
12703 // Cisc-spilled version of testP_reg
12704 // This will generate a signed flags result. This should be ok
12705 // since any compare to a zero should be eq/neq.
12706 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12707 match(Set cr (CmpP (LoadP op) zero));
12709 format %{ "TEST $op,0xFFFFFFFF" %}
12710 ins_cost(500);
12711 opcode(0xF7); /* Opcode F7 /0 */
12712 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12713 ins_pipe( ialu_cr_reg_imm );
12714 %}
12716 // Yanked all unsigned pointer compare operations.
12717 // Pointer compares are done with CmpP which is already unsigned.
12719 //----------Max and Min--------------------------------------------------------
12720 // Min Instructions
12721 ////
12722 // *** Min and Max using the conditional move are slower than the
12723 // *** branch version on a Pentium III.
12724 // // Conditional move for min
12725 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12726 // effect( USE_DEF op2, USE op1, USE cr );
12727 // format %{ "CMOVlt $op2,$op1\t! min" %}
12728 // opcode(0x4C,0x0F);
12729 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12730 // ins_pipe( pipe_cmov_reg );
12731 //%}
12732 //
12733 //// Min Register with Register (P6 version)
12734 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12735 // predicate(VM_Version::supports_cmov() );
12736 // match(Set op2 (MinI op1 op2));
12737 // ins_cost(200);
12738 // expand %{
12739 // eFlagsReg cr;
12740 // compI_eReg(cr,op1,op2);
12741 // cmovI_reg_lt(op2,op1,cr);
12742 // %}
12743 //%}
12745 // Min Register with Register (generic version)
12746 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12747 match(Set dst (MinI dst src));
12748 effect(KILL flags);
12749 ins_cost(300);
12751 format %{ "MIN $dst,$src" %}
12752 opcode(0xCC);
12753 ins_encode( min_enc(dst,src) );
12754 ins_pipe( pipe_slow );
12755 %}
12757 // Max Register with Register
12758 // *** Min and Max using the conditional move are slower than the
12759 // *** branch version on a Pentium III.
12760 // // Conditional move for max
12761 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12762 // effect( USE_DEF op2, USE op1, USE cr );
12763 // format %{ "CMOVgt $op2,$op1\t! max" %}
12764 // opcode(0x4F,0x0F);
12765 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12766 // ins_pipe( pipe_cmov_reg );
12767 //%}
12768 //
12769 // // Max Register with Register (P6 version)
12770 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12771 // predicate(VM_Version::supports_cmov() );
12772 // match(Set op2 (MaxI op1 op2));
12773 // ins_cost(200);
12774 // expand %{
12775 // eFlagsReg cr;
12776 // compI_eReg(cr,op1,op2);
12777 // cmovI_reg_gt(op2,op1,cr);
12778 // %}
12779 //%}
12781 // Max Register with Register (generic version)
12782 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12783 match(Set dst (MaxI dst src));
12784 effect(KILL flags);
12785 ins_cost(300);
12787 format %{ "MAX $dst,$src" %}
12788 opcode(0xCC);
12789 ins_encode( max_enc(dst,src) );
12790 ins_pipe( pipe_slow );
12791 %}
12793 // ============================================================================
12794 // Branch Instructions
12795 // Jump Table
12796 instruct jumpXtnd(eRegI switch_val) %{
12797 match(Jump switch_val);
12798 ins_cost(350);
12800 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12802 ins_encode %{
12803 address table_base = __ address_table_constant(_index2label);
12805 // Jump to Address(table_base + switch_reg)
12806 InternalAddress table(table_base);
12807 Address index(noreg, $switch_val$$Register, Address::times_1);
12808 __ jump(ArrayAddress(table, index));
12809 %}
12810 ins_pc_relative(1);
12811 ins_pipe(pipe_jmp);
12812 %}
12814 // Jump Direct - Label defines a relative address from JMP+1
12815 instruct jmpDir(label labl) %{
12816 match(Goto);
12817 effect(USE labl);
12819 ins_cost(300);
12820 format %{ "JMP $labl" %}
12821 size(5);
12822 opcode(0xE9);
12823 ins_encode( OpcP, Lbl( labl ) );
12824 ins_pipe( pipe_jmp );
12825 ins_pc_relative(1);
12826 %}
12828 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12829 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12830 match(If cop cr);
12831 effect(USE labl);
12833 ins_cost(300);
12834 format %{ "J$cop $labl" %}
12835 size(6);
12836 opcode(0x0F, 0x80);
12837 ins_encode( Jcc( cop, labl) );
12838 ins_pipe( pipe_jcc );
12839 ins_pc_relative(1);
12840 %}
12842 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12843 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12844 match(CountedLoopEnd cop cr);
12845 effect(USE labl);
12847 ins_cost(300);
12848 format %{ "J$cop $labl\t# Loop end" %}
12849 size(6);
12850 opcode(0x0F, 0x80);
12851 ins_encode( Jcc( cop, labl) );
12852 ins_pipe( pipe_jcc );
12853 ins_pc_relative(1);
12854 %}
12856 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12857 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12858 match(CountedLoopEnd cop cmp);
12859 effect(USE labl);
12861 ins_cost(300);
12862 format %{ "J$cop,u $labl\t# Loop end" %}
12863 size(6);
12864 opcode(0x0F, 0x80);
12865 ins_encode( Jcc( cop, labl) );
12866 ins_pipe( pipe_jcc );
12867 ins_pc_relative(1);
12868 %}
12870 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12871 match(CountedLoopEnd cop cmp);
12872 effect(USE labl);
12874 ins_cost(200);
12875 format %{ "J$cop,u $labl\t# Loop end" %}
12876 size(6);
12877 opcode(0x0F, 0x80);
12878 ins_encode( Jcc( cop, labl) );
12879 ins_pipe( pipe_jcc );
12880 ins_pc_relative(1);
12881 %}
12883 // Jump Direct Conditional - using unsigned comparison
12884 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12885 match(If cop cmp);
12886 effect(USE labl);
12888 ins_cost(300);
12889 format %{ "J$cop,u $labl" %}
12890 size(6);
12891 opcode(0x0F, 0x80);
12892 ins_encode(Jcc(cop, labl));
12893 ins_pipe(pipe_jcc);
12894 ins_pc_relative(1);
12895 %}
12897 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12898 match(If cop cmp);
12899 effect(USE labl);
12901 ins_cost(200);
12902 format %{ "J$cop,u $labl" %}
12903 size(6);
12904 opcode(0x0F, 0x80);
12905 ins_encode(Jcc(cop, labl));
12906 ins_pipe(pipe_jcc);
12907 ins_pc_relative(1);
12908 %}
12910 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12911 match(If cop cmp);
12912 effect(USE labl);
12914 ins_cost(200);
12915 format %{ $$template
12916 if ($cop$$cmpcode == Assembler::notEqual) {
12917 $$emit$$"JP,u $labl\n\t"
12918 $$emit$$"J$cop,u $labl"
12919 } else {
12920 $$emit$$"JP,u done\n\t"
12921 $$emit$$"J$cop,u $labl\n\t"
12922 $$emit$$"done:"
12923 }
12924 %}
12925 size(12);
12926 opcode(0x0F, 0x80);
12927 ins_encode %{
12928 Label* l = $labl$$label;
12929 $$$emit8$primary;
12930 emit_cc(cbuf, $secondary, Assembler::parity);
12931 int parity_disp = -1;
12932 bool ok = false;
12933 if ($cop$$cmpcode == Assembler::notEqual) {
12934 // the two jumps 6 bytes apart so the jump distances are too
12935 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12936 } else if ($cop$$cmpcode == Assembler::equal) {
12937 parity_disp = 6;
12938 ok = true;
12939 } else {
12940 ShouldNotReachHere();
12941 }
12942 emit_d32(cbuf, parity_disp);
12943 $$$emit8$primary;
12944 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12945 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12946 emit_d32(cbuf, disp);
12947 %}
12948 ins_pipe(pipe_jcc);
12949 ins_pc_relative(1);
12950 %}
12952 // ============================================================================
12953 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12954 // array for an instance of the superklass. Set a hidden internal cache on a
12955 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12956 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12957 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12958 match(Set result (PartialSubtypeCheck sub super));
12959 effect( KILL rcx, KILL cr );
12961 ins_cost(1100); // slightly larger than the next version
12962 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12963 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12964 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12965 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12966 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12967 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12968 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12969 "miss:\t" %}
12971 opcode(0x1); // Force a XOR of EDI
12972 ins_encode( enc_PartialSubtypeCheck() );
12973 ins_pipe( pipe_slow );
12974 %}
12976 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12977 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12978 effect( KILL rcx, KILL result );
12980 ins_cost(1000);
12981 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12982 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12983 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12984 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12985 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12986 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12987 "miss:\t" %}
12989 opcode(0x0); // No need to XOR EDI
12990 ins_encode( enc_PartialSubtypeCheck() );
12991 ins_pipe( pipe_slow );
12992 %}
12994 // ============================================================================
12995 // Branch Instructions -- short offset versions
12996 //
12997 // These instructions are used to replace jumps of a long offset (the default
12998 // match) with jumps of a shorter offset. These instructions are all tagged
12999 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13000 // match rules in general matching. Instead, the ADLC generates a conversion
13001 // method in the MachNode which can be used to do in-place replacement of the
13002 // long variant with the shorter variant. The compiler will determine if a
13003 // branch can be taken by the is_short_branch_offset() predicate in the machine
13004 // specific code section of the file.
13006 // Jump Direct - Label defines a relative address from JMP+1
13007 instruct jmpDir_short(label labl) %{
13008 match(Goto);
13009 effect(USE labl);
13011 ins_cost(300);
13012 format %{ "JMP,s $labl" %}
13013 size(2);
13014 opcode(0xEB);
13015 ins_encode( OpcP, LblShort( labl ) );
13016 ins_pipe( pipe_jmp );
13017 ins_pc_relative(1);
13018 ins_short_branch(1);
13019 %}
13021 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13022 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
13023 match(If cop cr);
13024 effect(USE labl);
13026 ins_cost(300);
13027 format %{ "J$cop,s $labl" %}
13028 size(2);
13029 opcode(0x70);
13030 ins_encode( JccShort( cop, labl) );
13031 ins_pipe( pipe_jcc );
13032 ins_pc_relative(1);
13033 ins_short_branch(1);
13034 %}
13036 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13037 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
13038 match(CountedLoopEnd cop cr);
13039 effect(USE labl);
13041 ins_cost(300);
13042 format %{ "J$cop,s $labl\t# Loop end" %}
13043 size(2);
13044 opcode(0x70);
13045 ins_encode( JccShort( cop, labl) );
13046 ins_pipe( pipe_jcc );
13047 ins_pc_relative(1);
13048 ins_short_branch(1);
13049 %}
13051 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13052 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13053 match(CountedLoopEnd cop cmp);
13054 effect(USE labl);
13056 ins_cost(300);
13057 format %{ "J$cop,us $labl\t# Loop end" %}
13058 size(2);
13059 opcode(0x70);
13060 ins_encode( JccShort( cop, labl) );
13061 ins_pipe( pipe_jcc );
13062 ins_pc_relative(1);
13063 ins_short_branch(1);
13064 %}
13066 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13067 match(CountedLoopEnd cop cmp);
13068 effect(USE labl);
13070 ins_cost(300);
13071 format %{ "J$cop,us $labl\t# Loop end" %}
13072 size(2);
13073 opcode(0x70);
13074 ins_encode( JccShort( cop, labl) );
13075 ins_pipe( pipe_jcc );
13076 ins_pc_relative(1);
13077 ins_short_branch(1);
13078 %}
13080 // Jump Direct Conditional - using unsigned comparison
13081 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
13082 match(If cop cmp);
13083 effect(USE labl);
13085 ins_cost(300);
13086 format %{ "J$cop,us $labl" %}
13087 size(2);
13088 opcode(0x70);
13089 ins_encode( JccShort( cop, labl) );
13090 ins_pipe( pipe_jcc );
13091 ins_pc_relative(1);
13092 ins_short_branch(1);
13093 %}
13095 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
13096 match(If cop cmp);
13097 effect(USE labl);
13099 ins_cost(300);
13100 format %{ "J$cop,us $labl" %}
13101 size(2);
13102 opcode(0x70);
13103 ins_encode( JccShort( cop, labl) );
13104 ins_pipe( pipe_jcc );
13105 ins_pc_relative(1);
13106 ins_short_branch(1);
13107 %}
13109 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
13110 match(If cop cmp);
13111 effect(USE labl);
13113 ins_cost(300);
13114 format %{ $$template
13115 if ($cop$$cmpcode == Assembler::notEqual) {
13116 $$emit$$"JP,u,s $labl\n\t"
13117 $$emit$$"J$cop,u,s $labl"
13118 } else {
13119 $$emit$$"JP,u,s done\n\t"
13120 $$emit$$"J$cop,u,s $labl\n\t"
13121 $$emit$$"done:"
13122 }
13123 %}
13124 size(4);
13125 opcode(0x70);
13126 ins_encode %{
13127 Label* l = $labl$$label;
13128 emit_cc(cbuf, $primary, Assembler::parity);
13129 int parity_disp = -1;
13130 if ($cop$$cmpcode == Assembler::notEqual) {
13131 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13132 } else if ($cop$$cmpcode == Assembler::equal) {
13133 parity_disp = 2;
13134 } else {
13135 ShouldNotReachHere();
13136 }
13137 emit_d8(cbuf, parity_disp);
13138 emit_cc(cbuf, $primary, $cop$$cmpcode);
13139 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
13140 emit_d8(cbuf, disp);
13141 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
13142 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
13143 %}
13144 ins_pipe(pipe_jcc);
13145 ins_pc_relative(1);
13146 ins_short_branch(1);
13147 %}
13149 // ============================================================================
13150 // Long Compare
13151 //
13152 // Currently we hold longs in 2 registers. Comparing such values efficiently
13153 // is tricky. The flavor of compare used depends on whether we are testing
13154 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
13155 // The GE test is the negated LT test. The LE test can be had by commuting
13156 // the operands (yielding a GE test) and then negating; negate again for the
13157 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
13158 // NE test is negated from that.
13160 // Due to a shortcoming in the ADLC, it mixes up expressions like:
13161 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
13162 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
13163 // are collapsed internally in the ADLC's dfa-gen code. The match for
13164 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
13165 // foo match ends up with the wrong leaf. One fix is to not match both
13166 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
13167 // both forms beat the trinary form of long-compare and both are very useful
13168 // on Intel which has so few registers.
13170 // Manifest a CmpL result in an integer register. Very painful.
13171 // This is the test to avoid.
13172 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
13173 match(Set dst (CmpL3 src1 src2));
13174 effect( KILL flags );
13175 ins_cost(1000);
13176 format %{ "XOR $dst,$dst\n\t"
13177 "CMP $src1.hi,$src2.hi\n\t"
13178 "JLT,s m_one\n\t"
13179 "JGT,s p_one\n\t"
13180 "CMP $src1.lo,$src2.lo\n\t"
13181 "JB,s m_one\n\t"
13182 "JEQ,s done\n"
13183 "p_one:\tINC $dst\n\t"
13184 "JMP,s done\n"
13185 "m_one:\tDEC $dst\n"
13186 "done:" %}
13187 ins_encode %{
13188 Label p_one, m_one, done;
13189 __ xorptr($dst$$Register, $dst$$Register);
13190 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
13191 __ jccb(Assembler::less, m_one);
13192 __ jccb(Assembler::greater, p_one);
13193 __ cmpl($src1$$Register, $src2$$Register);
13194 __ jccb(Assembler::below, m_one);
13195 __ jccb(Assembler::equal, done);
13196 __ bind(p_one);
13197 __ incrementl($dst$$Register);
13198 __ jmpb(done);
13199 __ bind(m_one);
13200 __ decrementl($dst$$Register);
13201 __ bind(done);
13202 %}
13203 ins_pipe( pipe_slow );
13204 %}
13206 //======
13207 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13208 // compares. Can be used for LE or GT compares by reversing arguments.
13209 // NOT GOOD FOR EQ/NE tests.
13210 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
13211 match( Set flags (CmpL src zero ));
13212 ins_cost(100);
13213 format %{ "TEST $src.hi,$src.hi" %}
13214 opcode(0x85);
13215 ins_encode( OpcP, RegReg_Hi2( src, src ) );
13216 ins_pipe( ialu_cr_reg_reg );
13217 %}
13219 // Manifest a CmpL result in the normal flags. Only good for LT or GE
13220 // compares. Can be used for LE or GT compares by reversing arguments.
13221 // NOT GOOD FOR EQ/NE tests.
13222 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13223 match( Set flags (CmpL src1 src2 ));
13224 effect( TEMP tmp );
13225 ins_cost(300);
13226 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13227 "MOV $tmp,$src1.hi\n\t"
13228 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
13229 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
13230 ins_pipe( ialu_cr_reg_reg );
13231 %}
13233 // Long compares reg < zero/req OR reg >= zero/req.
13234 // Just a wrapper for a normal branch, plus the predicate test.
13235 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
13236 match(If cmp flags);
13237 effect(USE labl);
13238 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13239 expand %{
13240 jmpCon(cmp,flags,labl); // JLT or JGE...
13241 %}
13242 %}
13244 // Compare 2 longs and CMOVE longs.
13245 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
13246 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13247 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13248 ins_cost(400);
13249 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13250 "CMOV$cmp $dst.hi,$src.hi" %}
13251 opcode(0x0F,0x40);
13252 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13253 ins_pipe( pipe_cmov_reg_long );
13254 %}
13256 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
13257 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13258 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13259 ins_cost(500);
13260 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13261 "CMOV$cmp $dst.hi,$src.hi" %}
13262 opcode(0x0F,0x40);
13263 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13264 ins_pipe( pipe_cmov_reg_long );
13265 %}
13267 // Compare 2 longs and CMOVE ints.
13268 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
13269 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13270 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13271 ins_cost(200);
13272 format %{ "CMOV$cmp $dst,$src" %}
13273 opcode(0x0F,0x40);
13274 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13275 ins_pipe( pipe_cmov_reg );
13276 %}
13278 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
13279 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13280 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13281 ins_cost(250);
13282 format %{ "CMOV$cmp $dst,$src" %}
13283 opcode(0x0F,0x40);
13284 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13285 ins_pipe( pipe_cmov_mem );
13286 %}
13288 // Compare 2 longs and CMOVE ints.
13289 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13290 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13291 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13292 ins_cost(200);
13293 format %{ "CMOV$cmp $dst,$src" %}
13294 opcode(0x0F,0x40);
13295 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13296 ins_pipe( pipe_cmov_reg );
13297 %}
13299 // Compare 2 longs and CMOVE doubles
13300 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13301 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13302 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13303 ins_cost(200);
13304 expand %{
13305 fcmovD_regS(cmp,flags,dst,src);
13306 %}
13307 %}
13309 // Compare 2 longs and CMOVE doubles
13310 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13311 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13312 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13313 ins_cost(200);
13314 expand %{
13315 fcmovXD_regS(cmp,flags,dst,src);
13316 %}
13317 %}
13319 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13320 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13321 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13322 ins_cost(200);
13323 expand %{
13324 fcmovF_regS(cmp,flags,dst,src);
13325 %}
13326 %}
13328 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13329 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13330 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13331 ins_cost(200);
13332 expand %{
13333 fcmovX_regS(cmp,flags,dst,src);
13334 %}
13335 %}
13337 //======
13338 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13339 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13340 match( Set flags (CmpL src zero ));
13341 effect(TEMP tmp);
13342 ins_cost(200);
13343 format %{ "MOV $tmp,$src.lo\n\t"
13344 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13345 ins_encode( long_cmp_flags0( src, tmp ) );
13346 ins_pipe( ialu_reg_reg_long );
13347 %}
13349 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13350 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13351 match( Set flags (CmpL src1 src2 ));
13352 ins_cost(200+300);
13353 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13354 "JNE,s skip\n\t"
13355 "CMP $src1.hi,$src2.hi\n\t"
13356 "skip:\t" %}
13357 ins_encode( long_cmp_flags1( src1, src2 ) );
13358 ins_pipe( ialu_cr_reg_reg );
13359 %}
13361 // Long compare reg == zero/reg OR reg != zero/reg
13362 // Just a wrapper for a normal branch, plus the predicate test.
13363 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13364 match(If cmp flags);
13365 effect(USE labl);
13366 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13367 expand %{
13368 jmpCon(cmp,flags,labl); // JEQ or JNE...
13369 %}
13370 %}
13372 // Compare 2 longs and CMOVE longs.
13373 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13374 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13375 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13376 ins_cost(400);
13377 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13378 "CMOV$cmp $dst.hi,$src.hi" %}
13379 opcode(0x0F,0x40);
13380 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13381 ins_pipe( pipe_cmov_reg_long );
13382 %}
13384 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13385 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13386 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13387 ins_cost(500);
13388 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13389 "CMOV$cmp $dst.hi,$src.hi" %}
13390 opcode(0x0F,0x40);
13391 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13392 ins_pipe( pipe_cmov_reg_long );
13393 %}
13395 // Compare 2 longs and CMOVE ints.
13396 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13397 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13398 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13399 ins_cost(200);
13400 format %{ "CMOV$cmp $dst,$src" %}
13401 opcode(0x0F,0x40);
13402 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13403 ins_pipe( pipe_cmov_reg );
13404 %}
13406 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13407 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13408 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13409 ins_cost(250);
13410 format %{ "CMOV$cmp $dst,$src" %}
13411 opcode(0x0F,0x40);
13412 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13413 ins_pipe( pipe_cmov_mem );
13414 %}
13416 // Compare 2 longs and CMOVE ints.
13417 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13418 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13419 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13420 ins_cost(200);
13421 format %{ "CMOV$cmp $dst,$src" %}
13422 opcode(0x0F,0x40);
13423 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13424 ins_pipe( pipe_cmov_reg );
13425 %}
13427 // Compare 2 longs and CMOVE doubles
13428 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13429 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13430 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13431 ins_cost(200);
13432 expand %{
13433 fcmovD_regS(cmp,flags,dst,src);
13434 %}
13435 %}
13437 // Compare 2 longs and CMOVE doubles
13438 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13439 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13440 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13441 ins_cost(200);
13442 expand %{
13443 fcmovXD_regS(cmp,flags,dst,src);
13444 %}
13445 %}
13447 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13448 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13449 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13450 ins_cost(200);
13451 expand %{
13452 fcmovF_regS(cmp,flags,dst,src);
13453 %}
13454 %}
13456 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13457 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13458 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13459 ins_cost(200);
13460 expand %{
13461 fcmovX_regS(cmp,flags,dst,src);
13462 %}
13463 %}
13465 //======
13466 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13467 // Same as cmpL_reg_flags_LEGT except must negate src
13468 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13469 match( Set flags (CmpL src zero ));
13470 effect( TEMP tmp );
13471 ins_cost(300);
13472 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13473 "CMP $tmp,$src.lo\n\t"
13474 "SBB $tmp,$src.hi\n\t" %}
13475 ins_encode( long_cmp_flags3(src, tmp) );
13476 ins_pipe( ialu_reg_reg_long );
13477 %}
13479 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13480 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13481 // requires a commuted test to get the same result.
13482 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13483 match( Set flags (CmpL src1 src2 ));
13484 effect( TEMP tmp );
13485 ins_cost(300);
13486 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13487 "MOV $tmp,$src2.hi\n\t"
13488 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13489 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13490 ins_pipe( ialu_cr_reg_reg );
13491 %}
13493 // Long compares reg < zero/req OR reg >= zero/req.
13494 // Just a wrapper for a normal branch, plus the predicate test
13495 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13496 match(If cmp flags);
13497 effect(USE labl);
13498 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13499 ins_cost(300);
13500 expand %{
13501 jmpCon(cmp,flags,labl); // JGT or JLE...
13502 %}
13503 %}
13505 // Compare 2 longs and CMOVE longs.
13506 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13507 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13508 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13509 ins_cost(400);
13510 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13511 "CMOV$cmp $dst.hi,$src.hi" %}
13512 opcode(0x0F,0x40);
13513 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13514 ins_pipe( pipe_cmov_reg_long );
13515 %}
13517 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13518 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13519 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13520 ins_cost(500);
13521 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13522 "CMOV$cmp $dst.hi,$src.hi+4" %}
13523 opcode(0x0F,0x40);
13524 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13525 ins_pipe( pipe_cmov_reg_long );
13526 %}
13528 // Compare 2 longs and CMOVE ints.
13529 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13530 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13531 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13532 ins_cost(200);
13533 format %{ "CMOV$cmp $dst,$src" %}
13534 opcode(0x0F,0x40);
13535 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13536 ins_pipe( pipe_cmov_reg );
13537 %}
13539 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13540 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13541 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13542 ins_cost(250);
13543 format %{ "CMOV$cmp $dst,$src" %}
13544 opcode(0x0F,0x40);
13545 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13546 ins_pipe( pipe_cmov_mem );
13547 %}
13549 // Compare 2 longs and CMOVE ptrs.
13550 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13551 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13552 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13553 ins_cost(200);
13554 format %{ "CMOV$cmp $dst,$src" %}
13555 opcode(0x0F,0x40);
13556 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13557 ins_pipe( pipe_cmov_reg );
13558 %}
13560 // Compare 2 longs and CMOVE doubles
13561 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13562 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13563 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13564 ins_cost(200);
13565 expand %{
13566 fcmovD_regS(cmp,flags,dst,src);
13567 %}
13568 %}
13570 // Compare 2 longs and CMOVE doubles
13571 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13572 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13573 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13574 ins_cost(200);
13575 expand %{
13576 fcmovXD_regS(cmp,flags,dst,src);
13577 %}
13578 %}
13580 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13581 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13582 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13583 ins_cost(200);
13584 expand %{
13585 fcmovF_regS(cmp,flags,dst,src);
13586 %}
13587 %}
13590 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13591 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13592 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13593 ins_cost(200);
13594 expand %{
13595 fcmovX_regS(cmp,flags,dst,src);
13596 %}
13597 %}
13600 // ============================================================================
13601 // Procedure Call/Return Instructions
13602 // Call Java Static Instruction
13603 // Note: If this code changes, the corresponding ret_addr_offset() and
13604 // compute_padding() functions will have to be adjusted.
13605 instruct CallStaticJavaDirect(method meth) %{
13606 match(CallStaticJava);
13607 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13608 effect(USE meth);
13610 ins_cost(300);
13611 format %{ "CALL,static " %}
13612 opcode(0xE8); /* E8 cd */
13613 ins_encode( pre_call_FPU,
13614 Java_Static_Call( meth ),
13615 call_epilog,
13616 post_call_FPU );
13617 ins_pipe( pipe_slow );
13618 ins_pc_relative(1);
13619 ins_alignment(4);
13620 %}
13622 // Call Java Static Instruction (method handle version)
13623 // Note: If this code changes, the corresponding ret_addr_offset() and
13624 // compute_padding() functions will have to be adjusted.
13625 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13626 match(CallStaticJava);
13627 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13628 effect(USE meth);
13629 // EBP is saved by all callees (for interpreter stack correction).
13630 // We use it here for a similar purpose, in {preserve,restore}_SP.
13632 ins_cost(300);
13633 format %{ "CALL,static/MethodHandle " %}
13634 opcode(0xE8); /* E8 cd */
13635 ins_encode( pre_call_FPU,
13636 preserve_SP,
13637 Java_Static_Call( meth ),
13638 restore_SP,
13639 call_epilog,
13640 post_call_FPU );
13641 ins_pipe( pipe_slow );
13642 ins_pc_relative(1);
13643 ins_alignment(4);
13644 %}
13646 // Call Java Dynamic Instruction
13647 // Note: If this code changes, the corresponding ret_addr_offset() and
13648 // compute_padding() functions will have to be adjusted.
13649 instruct CallDynamicJavaDirect(method meth) %{
13650 match(CallDynamicJava);
13651 effect(USE meth);
13653 ins_cost(300);
13654 format %{ "MOV EAX,(oop)-1\n\t"
13655 "CALL,dynamic" %}
13656 opcode(0xE8); /* E8 cd */
13657 ins_encode( pre_call_FPU,
13658 Java_Dynamic_Call( meth ),
13659 call_epilog,
13660 post_call_FPU );
13661 ins_pipe( pipe_slow );
13662 ins_pc_relative(1);
13663 ins_alignment(4);
13664 %}
13666 // Call Runtime Instruction
13667 instruct CallRuntimeDirect(method meth) %{
13668 match(CallRuntime );
13669 effect(USE meth);
13671 ins_cost(300);
13672 format %{ "CALL,runtime " %}
13673 opcode(0xE8); /* E8 cd */
13674 // Use FFREEs to clear entries in float stack
13675 ins_encode( pre_call_FPU,
13676 FFree_Float_Stack_All,
13677 Java_To_Runtime( meth ),
13678 post_call_FPU );
13679 ins_pipe( pipe_slow );
13680 ins_pc_relative(1);
13681 %}
13683 // Call runtime without safepoint
13684 instruct CallLeafDirect(method meth) %{
13685 match(CallLeaf);
13686 effect(USE meth);
13688 ins_cost(300);
13689 format %{ "CALL_LEAF,runtime " %}
13690 opcode(0xE8); /* E8 cd */
13691 ins_encode( pre_call_FPU,
13692 FFree_Float_Stack_All,
13693 Java_To_Runtime( meth ),
13694 Verify_FPU_For_Leaf, post_call_FPU );
13695 ins_pipe( pipe_slow );
13696 ins_pc_relative(1);
13697 %}
13699 instruct CallLeafNoFPDirect(method meth) %{
13700 match(CallLeafNoFP);
13701 effect(USE meth);
13703 ins_cost(300);
13704 format %{ "CALL_LEAF_NOFP,runtime " %}
13705 opcode(0xE8); /* E8 cd */
13706 ins_encode(Java_To_Runtime(meth));
13707 ins_pipe( pipe_slow );
13708 ins_pc_relative(1);
13709 %}
13712 // Return Instruction
13713 // Remove the return address & jump to it.
13714 instruct Ret() %{
13715 match(Return);
13716 format %{ "RET" %}
13717 opcode(0xC3);
13718 ins_encode(OpcP);
13719 ins_pipe( pipe_jmp );
13720 %}
13722 // Tail Call; Jump from runtime stub to Java code.
13723 // Also known as an 'interprocedural jump'.
13724 // Target of jump will eventually return to caller.
13725 // TailJump below removes the return address.
13726 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13727 match(TailCall jump_target method_oop );
13728 ins_cost(300);
13729 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13730 opcode(0xFF, 0x4); /* Opcode FF /4 */
13731 ins_encode( OpcP, RegOpc(jump_target) );
13732 ins_pipe( pipe_jmp );
13733 %}
13736 // Tail Jump; remove the return address; jump to target.
13737 // TailCall above leaves the return address around.
13738 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13739 match( TailJump jump_target ex_oop );
13740 ins_cost(300);
13741 format %{ "POP EDX\t# pop return address into dummy\n\t"
13742 "JMP $jump_target " %}
13743 opcode(0xFF, 0x4); /* Opcode FF /4 */
13744 ins_encode( enc_pop_rdx,
13745 OpcP, RegOpc(jump_target) );
13746 ins_pipe( pipe_jmp );
13747 %}
13749 // Create exception oop: created by stack-crawling runtime code.
13750 // Created exception is now available to this handler, and is setup
13751 // just prior to jumping to this handler. No code emitted.
13752 instruct CreateException( eAXRegP ex_oop )
13753 %{
13754 match(Set ex_oop (CreateEx));
13756 size(0);
13757 // use the following format syntax
13758 format %{ "# exception oop is in EAX; no code emitted" %}
13759 ins_encode();
13760 ins_pipe( empty );
13761 %}
13764 // Rethrow exception:
13765 // The exception oop will come in the first argument position.
13766 // Then JUMP (not call) to the rethrow stub code.
13767 instruct RethrowException()
13768 %{
13769 match(Rethrow);
13771 // use the following format syntax
13772 format %{ "JMP rethrow_stub" %}
13773 ins_encode(enc_rethrow);
13774 ins_pipe( pipe_jmp );
13775 %}
13777 // inlined locking and unlocking
13780 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13781 match( Set cr (FastLock object box) );
13782 effect( TEMP tmp, TEMP scr );
13783 ins_cost(300);
13784 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13785 ins_encode( Fast_Lock(object,box,tmp,scr) );
13786 ins_pipe( pipe_slow );
13787 ins_pc_relative(1);
13788 %}
13790 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13791 match( Set cr (FastUnlock object box) );
13792 effect( TEMP tmp );
13793 ins_cost(300);
13794 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13795 ins_encode( Fast_Unlock(object,box,tmp) );
13796 ins_pipe( pipe_slow );
13797 ins_pc_relative(1);
13798 %}
13802 // ============================================================================
13803 // Safepoint Instruction
13804 instruct safePoint_poll(eFlagsReg cr) %{
13805 match(SafePoint);
13806 effect(KILL cr);
13808 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13809 // On SPARC that might be acceptable as we can generate the address with
13810 // just a sethi, saving an or. By polling at offset 0 we can end up
13811 // putting additional pressure on the index-0 in the D$. Because of
13812 // alignment (just like the situation at hand) the lower indices tend
13813 // to see more traffic. It'd be better to change the polling address
13814 // to offset 0 of the last $line in the polling page.
13816 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13817 ins_cost(125);
13818 size(6) ;
13819 ins_encode( Safepoint_Poll() );
13820 ins_pipe( ialu_reg_mem );
13821 %}
13823 //----------PEEPHOLE RULES-----------------------------------------------------
13824 // These must follow all instruction definitions as they use the names
13825 // defined in the instructions definitions.
13826 //
13827 // peepmatch ( root_instr_name [preceding_instruction]* );
13828 //
13829 // peepconstraint %{
13830 // (instruction_number.operand_name relational_op instruction_number.operand_name
13831 // [, ...] );
13832 // // instruction numbers are zero-based using left to right order in peepmatch
13833 //
13834 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13835 // // provide an instruction_number.operand_name for each operand that appears
13836 // // in the replacement instruction's match rule
13837 //
13838 // ---------VM FLAGS---------------------------------------------------------
13839 //
13840 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13841 //
13842 // Each peephole rule is given an identifying number starting with zero and
13843 // increasing by one in the order seen by the parser. An individual peephole
13844 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13845 // on the command-line.
13846 //
13847 // ---------CURRENT LIMITATIONS----------------------------------------------
13848 //
13849 // Only match adjacent instructions in same basic block
13850 // Only equality constraints
13851 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13852 // Only one replacement instruction
13853 //
13854 // ---------EXAMPLE----------------------------------------------------------
13855 //
13856 // // pertinent parts of existing instructions in architecture description
13857 // instruct movI(eRegI dst, eRegI src) %{
13858 // match(Set dst (CopyI src));
13859 // %}
13860 //
13861 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13862 // match(Set dst (AddI dst src));
13863 // effect(KILL cr);
13864 // %}
13865 //
13866 // // Change (inc mov) to lea
13867 // peephole %{
13868 // // increment preceeded by register-register move
13869 // peepmatch ( incI_eReg movI );
13870 // // require that the destination register of the increment
13871 // // match the destination register of the move
13872 // peepconstraint ( 0.dst == 1.dst );
13873 // // construct a replacement instruction that sets
13874 // // the destination to ( move's source register + one )
13875 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13876 // %}
13877 //
13878 // Implementation no longer uses movX instructions since
13879 // machine-independent system no longer uses CopyX nodes.
13880 //
13881 // peephole %{
13882 // peepmatch ( incI_eReg movI );
13883 // peepconstraint ( 0.dst == 1.dst );
13884 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13885 // %}
13886 //
13887 // peephole %{
13888 // peepmatch ( decI_eReg movI );
13889 // peepconstraint ( 0.dst == 1.dst );
13890 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13891 // %}
13892 //
13893 // peephole %{
13894 // peepmatch ( addI_eReg_imm movI );
13895 // peepconstraint ( 0.dst == 1.dst );
13896 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13897 // %}
13898 //
13899 // peephole %{
13900 // peepmatch ( addP_eReg_imm movP );
13901 // peepconstraint ( 0.dst == 1.dst );
13902 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13903 // %}
13905 // // Change load of spilled value to only a spill
13906 // instruct storeI(memory mem, eRegI src) %{
13907 // match(Set mem (StoreI mem src));
13908 // %}
13909 //
13910 // instruct loadI(eRegI dst, memory mem) %{
13911 // match(Set dst (LoadI mem));
13912 // %}
13913 //
13914 peephole %{
13915 peepmatch ( loadI storeI );
13916 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13917 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13918 %}
13920 //----------SMARTSPILL RULES---------------------------------------------------
13921 // These must follow all instruction definitions as they use the names
13922 // defined in the instructions definitions.