Tue, 21 Jun 2011 09:04:55 -0700
7056380: VM crashes with SIGSEGV in compiled code
Summary: code was using andq reg, imm instead of addq addr, imm
Reviewed-by: kvn, jrose, twisti
1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "assembler_x86.inline.hpp"
27 #include "gc_interface/collectedHeap.inline.hpp"
28 #include "interpreter/interpreter.hpp"
29 #include "memory/cardTableModRefBS.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/methodHandles.hpp"
32 #include "runtime/biasedLocking.hpp"
33 #include "runtime/interfaceSupport.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #ifndef SERIALGC
39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
41 #include "gc_implementation/g1/heapRegion.hpp"
42 #endif
44 // Implementation of AddressLiteral
46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
47 _is_lval = false;
48 _target = target;
49 switch (rtype) {
50 case relocInfo::oop_type:
51 // Oops are a special case. Normally they would be their own section
52 // but in cases like icBuffer they are literals in the code stream that
53 // we don't have a section for. We use none so that we get a literal address
54 // which is always patchable.
55 break;
56 case relocInfo::external_word_type:
57 _rspec = external_word_Relocation::spec(target);
58 break;
59 case relocInfo::internal_word_type:
60 _rspec = internal_word_Relocation::spec(target);
61 break;
62 case relocInfo::opt_virtual_call_type:
63 _rspec = opt_virtual_call_Relocation::spec();
64 break;
65 case relocInfo::static_call_type:
66 _rspec = static_call_Relocation::spec();
67 break;
68 case relocInfo::runtime_call_type:
69 _rspec = runtime_call_Relocation::spec();
70 break;
71 case relocInfo::poll_type:
72 case relocInfo::poll_return_type:
73 _rspec = Relocation::spec_simple(rtype);
74 break;
75 case relocInfo::none:
76 break;
77 default:
78 ShouldNotReachHere();
79 break;
80 }
81 }
83 // Implementation of Address
85 #ifdef _LP64
87 Address Address::make_array(ArrayAddress adr) {
88 // Not implementable on 64bit machines
89 // Should have been handled higher up the call chain.
90 ShouldNotReachHere();
91 return Address();
92 }
94 // exceedingly dangerous constructor
95 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
96 _base = noreg;
97 _index = noreg;
98 _scale = no_scale;
99 _disp = disp;
100 switch (rtype) {
101 case relocInfo::external_word_type:
102 _rspec = external_word_Relocation::spec(loc);
103 break;
104 case relocInfo::internal_word_type:
105 _rspec = internal_word_Relocation::spec(loc);
106 break;
107 case relocInfo::runtime_call_type:
108 // HMM
109 _rspec = runtime_call_Relocation::spec();
110 break;
111 case relocInfo::poll_type:
112 case relocInfo::poll_return_type:
113 _rspec = Relocation::spec_simple(rtype);
114 break;
115 case relocInfo::none:
116 break;
117 default:
118 ShouldNotReachHere();
119 }
120 }
121 #else // LP64
123 Address Address::make_array(ArrayAddress adr) {
124 AddressLiteral base = adr.base();
125 Address index = adr.index();
126 assert(index._disp == 0, "must not have disp"); // maybe it can?
127 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
128 array._rspec = base._rspec;
129 return array;
130 }
132 // exceedingly dangerous constructor
133 Address::Address(address loc, RelocationHolder spec) {
134 _base = noreg;
135 _index = noreg;
136 _scale = no_scale;
137 _disp = (intptr_t) loc;
138 _rspec = spec;
139 }
141 #endif // _LP64
145 // Convert the raw encoding form into the form expected by the constructor for
146 // Address. An index of 4 (rsp) corresponds to having no index, so convert
147 // that to noreg for the Address constructor.
148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
149 RelocationHolder rspec;
150 if (disp_is_oop) {
151 rspec = Relocation::spec_simple(relocInfo::oop_type);
152 }
153 bool valid_index = index != rsp->encoding();
154 if (valid_index) {
155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
156 madr._rspec = rspec;
157 return madr;
158 } else {
159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
160 madr._rspec = rspec;
161 return madr;
162 }
163 }
165 // Implementation of Assembler
167 int AbstractAssembler::code_fill_byte() {
168 return (u_char)'\xF4'; // hlt
169 }
171 // make this go away someday
172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
173 if (rtype == relocInfo::none)
174 emit_long(data);
175 else emit_data(data, Relocation::spec_simple(rtype), format);
176 }
178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
179 assert(imm_operand == 0, "default format must be immediate in this file");
180 assert(inst_mark() != NULL, "must be inside InstructionMark");
181 if (rspec.type() != relocInfo::none) {
182 #ifdef ASSERT
183 check_relocation(rspec, format);
184 #endif
185 // Do not use AbstractAssembler::relocate, which is not intended for
186 // embedded words. Instead, relocate to the enclosing instruction.
188 // hack. call32 is too wide for mask so use disp32
189 if (format == call32_operand)
190 code_section()->relocate(inst_mark(), rspec, disp32_operand);
191 else
192 code_section()->relocate(inst_mark(), rspec, format);
193 }
194 emit_long(data);
195 }
197 static int encode(Register r) {
198 int enc = r->encoding();
199 if (enc >= 8) {
200 enc -= 8;
201 }
202 return enc;
203 }
205 static int encode(XMMRegister r) {
206 int enc = r->encoding();
207 if (enc >= 8) {
208 enc -= 8;
209 }
210 return enc;
211 }
213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
214 assert(dst->has_byte_register(), "must have byte register");
215 assert(isByte(op1) && isByte(op2), "wrong opcode");
216 assert(isByte(imm8), "not a byte");
217 assert((op1 & 0x01) == 0, "should be 8bit operation");
218 emit_byte(op1);
219 emit_byte(op2 | encode(dst));
220 emit_byte(imm8);
221 }
224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
225 assert(isByte(op1) && isByte(op2), "wrong opcode");
226 assert((op1 & 0x01) == 1, "should be 32bit operation");
227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
228 if (is8bit(imm32)) {
229 emit_byte(op1 | 0x02); // set sign bit
230 emit_byte(op2 | encode(dst));
231 emit_byte(imm32 & 0xFF);
232 } else {
233 emit_byte(op1);
234 emit_byte(op2 | encode(dst));
235 emit_long(imm32);
236 }
237 }
239 // immediate-to-memory forms
240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
241 assert((op1 & 0x01) == 1, "should be 32bit operation");
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
243 if (is8bit(imm32)) {
244 emit_byte(op1 | 0x02); // set sign bit
245 emit_operand(rm, adr, 1);
246 emit_byte(imm32 & 0xFF);
247 } else {
248 emit_byte(op1);
249 emit_operand(rm, adr, 4);
250 emit_long(imm32);
251 }
252 }
254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
255 LP64_ONLY(ShouldNotReachHere());
256 assert(isByte(op1) && isByte(op2), "wrong opcode");
257 assert((op1 & 0x01) == 1, "should be 32bit operation");
258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
259 InstructionMark im(this);
260 emit_byte(op1);
261 emit_byte(op2 | encode(dst));
262 emit_data((intptr_t)obj, relocInfo::oop_type, 0);
263 }
266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
267 assert(isByte(op1) && isByte(op2), "wrong opcode");
268 emit_byte(op1);
269 emit_byte(op2 | encode(dst) << 3 | encode(src));
270 }
273 void Assembler::emit_operand(Register reg, Register base, Register index,
274 Address::ScaleFactor scale, int disp,
275 RelocationHolder const& rspec,
276 int rip_relative_correction) {
277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
279 // Encode the registers as needed in the fields they are used in
281 int regenc = encode(reg) << 3;
282 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
283 int baseenc = base->is_valid() ? encode(base) : 0;
285 if (base->is_valid()) {
286 if (index->is_valid()) {
287 assert(scale != Address::no_scale, "inconsistent address");
288 // [base + index*scale + disp]
289 if (disp == 0 && rtype == relocInfo::none &&
290 base != rbp LP64_ONLY(&& base != r13)) {
291 // [base + index*scale]
292 // [00 reg 100][ss index base]
293 assert(index != rsp, "illegal addressing mode");
294 emit_byte(0x04 | regenc);
295 emit_byte(scale << 6 | indexenc | baseenc);
296 } else if (is8bit(disp) && rtype == relocInfo::none) {
297 // [base + index*scale + imm8]
298 // [01 reg 100][ss index base] imm8
299 assert(index != rsp, "illegal addressing mode");
300 emit_byte(0x44 | regenc);
301 emit_byte(scale << 6 | indexenc | baseenc);
302 emit_byte(disp & 0xFF);
303 } else {
304 // [base + index*scale + disp32]
305 // [10 reg 100][ss index base] disp32
306 assert(index != rsp, "illegal addressing mode");
307 emit_byte(0x84 | regenc);
308 emit_byte(scale << 6 | indexenc | baseenc);
309 emit_data(disp, rspec, disp32_operand);
310 }
311 } else if (base == rsp LP64_ONLY(|| base == r12)) {
312 // [rsp + disp]
313 if (disp == 0 && rtype == relocInfo::none) {
314 // [rsp]
315 // [00 reg 100][00 100 100]
316 emit_byte(0x04 | regenc);
317 emit_byte(0x24);
318 } else if (is8bit(disp) && rtype == relocInfo::none) {
319 // [rsp + imm8]
320 // [01 reg 100][00 100 100] disp8
321 emit_byte(0x44 | regenc);
322 emit_byte(0x24);
323 emit_byte(disp & 0xFF);
324 } else {
325 // [rsp + imm32]
326 // [10 reg 100][00 100 100] disp32
327 emit_byte(0x84 | regenc);
328 emit_byte(0x24);
329 emit_data(disp, rspec, disp32_operand);
330 }
331 } else {
332 // [base + disp]
333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
334 if (disp == 0 && rtype == relocInfo::none &&
335 base != rbp LP64_ONLY(&& base != r13)) {
336 // [base]
337 // [00 reg base]
338 emit_byte(0x00 | regenc | baseenc);
339 } else if (is8bit(disp) && rtype == relocInfo::none) {
340 // [base + disp8]
341 // [01 reg base] disp8
342 emit_byte(0x40 | regenc | baseenc);
343 emit_byte(disp & 0xFF);
344 } else {
345 // [base + disp32]
346 // [10 reg base] disp32
347 emit_byte(0x80 | regenc | baseenc);
348 emit_data(disp, rspec, disp32_operand);
349 }
350 }
351 } else {
352 if (index->is_valid()) {
353 assert(scale != Address::no_scale, "inconsistent address");
354 // [index*scale + disp]
355 // [00 reg 100][ss index 101] disp32
356 assert(index != rsp, "illegal addressing mode");
357 emit_byte(0x04 | regenc);
358 emit_byte(scale << 6 | indexenc | 0x05);
359 emit_data(disp, rspec, disp32_operand);
360 } else if (rtype != relocInfo::none ) {
361 // [disp] (64bit) RIP-RELATIVE (32bit) abs
362 // [00 000 101] disp32
364 emit_byte(0x05 | regenc);
365 // Note that the RIP-rel. correction applies to the generated
366 // disp field, but _not_ to the target address in the rspec.
368 // disp was created by converting the target address minus the pc
369 // at the start of the instruction. That needs more correction here.
370 // intptr_t disp = target - next_ip;
371 assert(inst_mark() != NULL, "must be inside InstructionMark");
372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
373 int64_t adjusted = disp;
374 // Do rip-rel adjustment for 64bit
375 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
376 assert(is_simm32(adjusted),
377 "must be 32bit offset (RIP relative address)");
378 emit_data((int32_t) adjusted, rspec, disp32_operand);
380 } else {
381 // 32bit never did this, did everything as the rip-rel/disp code above
382 // [disp] ABSOLUTE
383 // [00 reg 100][00 100 101] disp32
384 emit_byte(0x04 | regenc);
385 emit_byte(0x25);
386 emit_data(disp, rspec, disp32_operand);
387 }
388 }
389 }
391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
392 Address::ScaleFactor scale, int disp,
393 RelocationHolder const& rspec) {
394 emit_operand((Register)reg, base, index, scale, disp, rspec);
395 }
397 // Secret local extension to Assembler::WhichOperand:
398 #define end_pc_operand (_WhichOperand_limit)
400 address Assembler::locate_operand(address inst, WhichOperand which) {
401 // Decode the given instruction, and return the address of
402 // an embedded 32-bit operand word.
404 // If "which" is disp32_operand, selects the displacement portion
405 // of an effective address specifier.
406 // If "which" is imm64_operand, selects the trailing immediate constant.
407 // If "which" is call32_operand, selects the displacement of a call or jump.
408 // Caller is responsible for ensuring that there is such an operand,
409 // and that it is 32/64 bits wide.
411 // If "which" is end_pc_operand, find the end of the instruction.
413 address ip = inst;
414 bool is_64bit = false;
416 debug_only(bool has_disp32 = false);
417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
419 again_after_prefix:
420 switch (0xFF & *ip++) {
422 // These convenience macros generate groups of "case" labels for the switch.
423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
425 case (x)+4: case (x)+5: case (x)+6: case (x)+7
426 #define REP16(x) REP8((x)+0): \
427 case REP8((x)+8)
429 case CS_segment:
430 case SS_segment:
431 case DS_segment:
432 case ES_segment:
433 case FS_segment:
434 case GS_segment:
435 // Seems dubious
436 LP64_ONLY(assert(false, "shouldn't have that prefix"));
437 assert(ip == inst+1, "only one prefix allowed");
438 goto again_after_prefix;
440 case 0x67:
441 case REX:
442 case REX_B:
443 case REX_X:
444 case REX_XB:
445 case REX_R:
446 case REX_RB:
447 case REX_RX:
448 case REX_RXB:
449 NOT_LP64(assert(false, "64bit prefixes"));
450 goto again_after_prefix;
452 case REX_W:
453 case REX_WB:
454 case REX_WX:
455 case REX_WXB:
456 case REX_WR:
457 case REX_WRB:
458 case REX_WRX:
459 case REX_WRXB:
460 NOT_LP64(assert(false, "64bit prefixes"));
461 is_64bit = true;
462 goto again_after_prefix;
464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
465 case 0x88: // movb a, r
466 case 0x89: // movl a, r
467 case 0x8A: // movb r, a
468 case 0x8B: // movl r, a
469 case 0x8F: // popl a
470 debug_only(has_disp32 = true);
471 break;
473 case 0x68: // pushq #32
474 if (which == end_pc_operand) {
475 return ip + 4;
476 }
477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
478 return ip; // not produced by emit_operand
480 case 0x66: // movw ... (size prefix)
481 again_after_size_prefix2:
482 switch (0xFF & *ip++) {
483 case REX:
484 case REX_B:
485 case REX_X:
486 case REX_XB:
487 case REX_R:
488 case REX_RB:
489 case REX_RX:
490 case REX_RXB:
491 case REX_W:
492 case REX_WB:
493 case REX_WX:
494 case REX_WXB:
495 case REX_WR:
496 case REX_WRB:
497 case REX_WRX:
498 case REX_WRXB:
499 NOT_LP64(assert(false, "64bit prefix found"));
500 goto again_after_size_prefix2;
501 case 0x8B: // movw r, a
502 case 0x89: // movw a, r
503 debug_only(has_disp32 = true);
504 break;
505 case 0xC7: // movw a, #16
506 debug_only(has_disp32 = true);
507 tail_size = 2; // the imm16
508 break;
509 case 0x0F: // several SSE/SSE2 variants
510 ip--; // reparse the 0x0F
511 goto again_after_prefix;
512 default:
513 ShouldNotReachHere();
514 }
515 break;
517 case REP8(0xB8): // movl/q r, #32/#64(oop?)
518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
519 // these asserts are somewhat nonsensical
520 #ifndef _LP64
521 assert(which == imm_operand || which == disp32_operand, "");
522 #else
523 assert((which == call32_operand || which == imm_operand) && is_64bit ||
524 which == narrow_oop_operand && !is_64bit, "");
525 #endif // _LP64
526 return ip;
528 case 0x69: // imul r, a, #32
529 case 0xC7: // movl a, #32(oop?)
530 tail_size = 4;
531 debug_only(has_disp32 = true); // has both kinds of operands!
532 break;
534 case 0x0F: // movx..., etc.
535 switch (0xFF & *ip++) {
536 case 0x12: // movlps
537 case 0x28: // movaps
538 case 0x2E: // ucomiss
539 case 0x2F: // comiss
540 case 0x54: // andps
541 case 0x55: // andnps
542 case 0x56: // orps
543 case 0x57: // xorps
544 case 0x6E: // movd
545 case 0x7E: // movd
546 case 0xAE: // ldmxcsr a
547 // 64bit side says it these have both operands but that doesn't
548 // appear to be true
549 debug_only(has_disp32 = true);
550 break;
552 case 0xAD: // shrd r, a, %cl
553 case 0xAF: // imul r, a
554 case 0xBE: // movsbl r, a (movsxb)
555 case 0xBF: // movswl r, a (movsxw)
556 case 0xB6: // movzbl r, a (movzxb)
557 case 0xB7: // movzwl r, a (movzxw)
558 case REP16(0x40): // cmovl cc, r, a
559 case 0xB0: // cmpxchgb
560 case 0xB1: // cmpxchg
561 case 0xC1: // xaddl
562 case 0xC7: // cmpxchg8
563 case REP16(0x90): // setcc a
564 debug_only(has_disp32 = true);
565 // fall out of the switch to decode the address
566 break;
568 case 0xAC: // shrd r, a, #8
569 debug_only(has_disp32 = true);
570 tail_size = 1; // the imm8
571 break;
573 case REP16(0x80): // jcc rdisp32
574 if (which == end_pc_operand) return ip + 4;
575 assert(which == call32_operand, "jcc has no disp32 or imm");
576 return ip;
577 default:
578 ShouldNotReachHere();
579 }
580 break;
582 case 0x81: // addl a, #32; addl r, #32
583 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
584 // on 32bit in the case of cmpl, the imm might be an oop
585 tail_size = 4;
586 debug_only(has_disp32 = true); // has both kinds of operands!
587 break;
589 case 0x83: // addl a, #8; addl r, #8
590 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
591 debug_only(has_disp32 = true); // has both kinds of operands!
592 tail_size = 1;
593 break;
595 case 0x9B:
596 switch (0xFF & *ip++) {
597 case 0xD9: // fnstcw a
598 debug_only(has_disp32 = true);
599 break;
600 default:
601 ShouldNotReachHere();
602 }
603 break;
605 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
606 case REP4(0x10): // adc...
607 case REP4(0x20): // and...
608 case REP4(0x30): // xor...
609 case REP4(0x08): // or...
610 case REP4(0x18): // sbb...
611 case REP4(0x28): // sub...
612 case 0xF7: // mull a
613 case 0x8D: // lea r, a
614 case 0x87: // xchg r, a
615 case REP4(0x38): // cmp...
616 case 0x85: // test r, a
617 debug_only(has_disp32 = true); // has both kinds of operands!
618 break;
620 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
621 case 0xC6: // movb a, #8
622 case 0x80: // cmpb a, #8
623 case 0x6B: // imul r, a, #8
624 debug_only(has_disp32 = true); // has both kinds of operands!
625 tail_size = 1; // the imm8
626 break;
628 case 0xE8: // call rdisp32
629 case 0xE9: // jmp rdisp32
630 if (which == end_pc_operand) return ip + 4;
631 assert(which == call32_operand, "call has no disp32 or imm");
632 return ip;
634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
637 case 0xDD: // fld_d a; fst_d a; fstp_d a
638 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
639 case 0xDF: // fild_d a; fistp_d a
640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
643 debug_only(has_disp32 = true);
644 break;
646 case 0xF0: // Lock
647 assert(os::is_MP(), "only on MP");
648 goto again_after_prefix;
650 case 0xF3: // For SSE
651 case 0xF2: // For SSE2
652 switch (0xFF & *ip++) {
653 case REX:
654 case REX_B:
655 case REX_X:
656 case REX_XB:
657 case REX_R:
658 case REX_RB:
659 case REX_RX:
660 case REX_RXB:
661 case REX_W:
662 case REX_WB:
663 case REX_WX:
664 case REX_WXB:
665 case REX_WR:
666 case REX_WRB:
667 case REX_WRX:
668 case REX_WRXB:
669 NOT_LP64(assert(false, "found 64bit prefix"));
670 ip++;
671 default:
672 ip++;
673 }
674 debug_only(has_disp32 = true); // has both kinds of operands!
675 break;
677 default:
678 ShouldNotReachHere();
680 #undef REP8
681 #undef REP16
682 }
684 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
685 #ifdef _LP64
686 assert(which != imm_operand, "instruction is not a movq reg, imm64");
687 #else
688 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
689 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
690 #endif // LP64
691 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
693 // parse the output of emit_operand
694 int op2 = 0xFF & *ip++;
695 int base = op2 & 0x07;
696 int op3 = -1;
697 const int b100 = 4;
698 const int b101 = 5;
699 if (base == b100 && (op2 >> 6) != 3) {
700 op3 = 0xFF & *ip++;
701 base = op3 & 0x07; // refetch the base
702 }
703 // now ip points at the disp (if any)
705 switch (op2 >> 6) {
706 case 0:
707 // [00 reg 100][ss index base]
708 // [00 reg 100][00 100 esp]
709 // [00 reg base]
710 // [00 reg 100][ss index 101][disp32]
711 // [00 reg 101] [disp32]
713 if (base == b101) {
714 if (which == disp32_operand)
715 return ip; // caller wants the disp32
716 ip += 4; // skip the disp32
717 }
718 break;
720 case 1:
721 // [01 reg 100][ss index base][disp8]
722 // [01 reg 100][00 100 esp][disp8]
723 // [01 reg base] [disp8]
724 ip += 1; // skip the disp8
725 break;
727 case 2:
728 // [10 reg 100][ss index base][disp32]
729 // [10 reg 100][00 100 esp][disp32]
730 // [10 reg base] [disp32]
731 if (which == disp32_operand)
732 return ip; // caller wants the disp32
733 ip += 4; // skip the disp32
734 break;
736 case 3:
737 // [11 reg base] (not a memory addressing mode)
738 break;
739 }
741 if (which == end_pc_operand) {
742 return ip + tail_size;
743 }
745 #ifdef _LP64
746 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
747 #else
748 assert(which == imm_operand, "instruction has only an imm field");
749 #endif // LP64
750 return ip;
751 }
753 address Assembler::locate_next_instruction(address inst) {
754 // Secretly share code with locate_operand:
755 return locate_operand(inst, end_pc_operand);
756 }
759 #ifdef ASSERT
760 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
761 address inst = inst_mark();
762 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
763 address opnd;
765 Relocation* r = rspec.reloc();
766 if (r->type() == relocInfo::none) {
767 return;
768 } else if (r->is_call() || format == call32_operand) {
769 // assert(format == imm32_operand, "cannot specify a nonzero format");
770 opnd = locate_operand(inst, call32_operand);
771 } else if (r->is_data()) {
772 assert(format == imm_operand || format == disp32_operand
773 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
774 opnd = locate_operand(inst, (WhichOperand)format);
775 } else {
776 assert(format == imm_operand, "cannot specify a format");
777 return;
778 }
779 assert(opnd == pc(), "must put operand where relocs can find it");
780 }
781 #endif // ASSERT
783 void Assembler::emit_operand32(Register reg, Address adr) {
784 assert(reg->encoding() < 8, "no extended registers");
785 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
786 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
787 adr._rspec);
788 }
790 void Assembler::emit_operand(Register reg, Address adr,
791 int rip_relative_correction) {
792 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
793 adr._rspec,
794 rip_relative_correction);
795 }
797 void Assembler::emit_operand(XMMRegister reg, Address adr) {
798 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
799 adr._rspec);
800 }
802 // MMX operations
803 void Assembler::emit_operand(MMXRegister reg, Address adr) {
804 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
805 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
806 }
808 // work around gcc (3.2.1-7a) bug
809 void Assembler::emit_operand(Address adr, MMXRegister reg) {
810 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
811 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
812 }
815 void Assembler::emit_farith(int b1, int b2, int i) {
816 assert(isByte(b1) && isByte(b2), "wrong opcode");
817 assert(0 <= i && i < 8, "illegal stack offset");
818 emit_byte(b1);
819 emit_byte(b2 + i);
820 }
823 // Now the Assembler instructions (identical for 32/64 bits)
825 void Assembler::adcl(Address dst, int32_t imm32) {
826 InstructionMark im(this);
827 prefix(dst);
828 emit_arith_operand(0x81, rdx, dst, imm32);
829 }
831 void Assembler::adcl(Address dst, Register src) {
832 InstructionMark im(this);
833 prefix(dst, src);
834 emit_byte(0x11);
835 emit_operand(src, dst);
836 }
838 void Assembler::adcl(Register dst, int32_t imm32) {
839 prefix(dst);
840 emit_arith(0x81, 0xD0, dst, imm32);
841 }
843 void Assembler::adcl(Register dst, Address src) {
844 InstructionMark im(this);
845 prefix(src, dst);
846 emit_byte(0x13);
847 emit_operand(dst, src);
848 }
850 void Assembler::adcl(Register dst, Register src) {
851 (void) prefix_and_encode(dst->encoding(), src->encoding());
852 emit_arith(0x13, 0xC0, dst, src);
853 }
855 void Assembler::addl(Address dst, int32_t imm32) {
856 InstructionMark im(this);
857 prefix(dst);
858 emit_arith_operand(0x81, rax, dst, imm32);
859 }
861 void Assembler::addl(Address dst, Register src) {
862 InstructionMark im(this);
863 prefix(dst, src);
864 emit_byte(0x01);
865 emit_operand(src, dst);
866 }
868 void Assembler::addl(Register dst, int32_t imm32) {
869 prefix(dst);
870 emit_arith(0x81, 0xC0, dst, imm32);
871 }
873 void Assembler::addl(Register dst, Address src) {
874 InstructionMark im(this);
875 prefix(src, dst);
876 emit_byte(0x03);
877 emit_operand(dst, src);
878 }
880 void Assembler::addl(Register dst, Register src) {
881 (void) prefix_and_encode(dst->encoding(), src->encoding());
882 emit_arith(0x03, 0xC0, dst, src);
883 }
885 void Assembler::addr_nop_4() {
886 // 4 bytes: NOP DWORD PTR [EAX+0]
887 emit_byte(0x0F);
888 emit_byte(0x1F);
889 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
890 emit_byte(0); // 8-bits offset (1 byte)
891 }
893 void Assembler::addr_nop_5() {
894 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
895 emit_byte(0x0F);
896 emit_byte(0x1F);
897 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
898 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
899 emit_byte(0); // 8-bits offset (1 byte)
900 }
902 void Assembler::addr_nop_7() {
903 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
904 emit_byte(0x0F);
905 emit_byte(0x1F);
906 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
907 emit_long(0); // 32-bits offset (4 bytes)
908 }
910 void Assembler::addr_nop_8() {
911 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
912 emit_byte(0x0F);
913 emit_byte(0x1F);
914 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
915 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
916 emit_long(0); // 32-bits offset (4 bytes)
917 }
919 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
920 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
921 emit_byte(0xF2);
922 int encode = prefix_and_encode(dst->encoding(), src->encoding());
923 emit_byte(0x0F);
924 emit_byte(0x58);
925 emit_byte(0xC0 | encode);
926 }
928 void Assembler::addsd(XMMRegister dst, Address src) {
929 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
930 InstructionMark im(this);
931 emit_byte(0xF2);
932 prefix(src, dst);
933 emit_byte(0x0F);
934 emit_byte(0x58);
935 emit_operand(dst, src);
936 }
938 void Assembler::addss(XMMRegister dst, XMMRegister src) {
939 NOT_LP64(assert(VM_Version::supports_sse(), ""));
940 emit_byte(0xF3);
941 int encode = prefix_and_encode(dst->encoding(), src->encoding());
942 emit_byte(0x0F);
943 emit_byte(0x58);
944 emit_byte(0xC0 | encode);
945 }
947 void Assembler::addss(XMMRegister dst, Address src) {
948 NOT_LP64(assert(VM_Version::supports_sse(), ""));
949 InstructionMark im(this);
950 emit_byte(0xF3);
951 prefix(src, dst);
952 emit_byte(0x0F);
953 emit_byte(0x58);
954 emit_operand(dst, src);
955 }
957 void Assembler::andl(Register dst, int32_t imm32) {
958 prefix(dst);
959 emit_arith(0x81, 0xE0, dst, imm32);
960 }
962 void Assembler::andl(Register dst, Address src) {
963 InstructionMark im(this);
964 prefix(src, dst);
965 emit_byte(0x23);
966 emit_operand(dst, src);
967 }
969 void Assembler::andl(Register dst, Register src) {
970 (void) prefix_and_encode(dst->encoding(), src->encoding());
971 emit_arith(0x23, 0xC0, dst, src);
972 }
974 void Assembler::andpd(XMMRegister dst, Address src) {
975 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
976 InstructionMark im(this);
977 emit_byte(0x66);
978 prefix(src, dst);
979 emit_byte(0x0F);
980 emit_byte(0x54);
981 emit_operand(dst, src);
982 }
984 void Assembler::bsfl(Register dst, Register src) {
985 int encode = prefix_and_encode(dst->encoding(), src->encoding());
986 emit_byte(0x0F);
987 emit_byte(0xBC);
988 emit_byte(0xC0 | encode);
989 }
991 void Assembler::bsrl(Register dst, Register src) {
992 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
993 int encode = prefix_and_encode(dst->encoding(), src->encoding());
994 emit_byte(0x0F);
995 emit_byte(0xBD);
996 emit_byte(0xC0 | encode);
997 }
999 void Assembler::bswapl(Register reg) { // bswap
1000 int encode = prefix_and_encode(reg->encoding());
1001 emit_byte(0x0F);
1002 emit_byte(0xC8 | encode);
1003 }
1005 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1006 // suspect disp32 is always good
1007 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1009 if (L.is_bound()) {
1010 const int long_size = 5;
1011 int offs = (int)( target(L) - pc() );
1012 assert(offs <= 0, "assembler error");
1013 InstructionMark im(this);
1014 // 1110 1000 #32-bit disp
1015 emit_byte(0xE8);
1016 emit_data(offs - long_size, rtype, operand);
1017 } else {
1018 InstructionMark im(this);
1019 // 1110 1000 #32-bit disp
1020 L.add_patch_at(code(), locator());
1022 emit_byte(0xE8);
1023 emit_data(int(0), rtype, operand);
1024 }
1025 }
1027 void Assembler::call(Register dst) {
1028 // This was originally using a 32bit register encoding
1029 // and surely we want 64bit!
1030 // this is a 32bit encoding but in 64bit mode the default
1031 // operand size is 64bit so there is no need for the
1032 // wide prefix. So prefix only happens if we use the
1033 // new registers. Much like push/pop.
1034 int x = offset();
1035 // this may be true but dbx disassembles it as if it
1036 // were 32bits...
1037 // int encode = prefix_and_encode(dst->encoding());
1038 // if (offset() != x) assert(dst->encoding() >= 8, "what?");
1039 int encode = prefixq_and_encode(dst->encoding());
1041 emit_byte(0xFF);
1042 emit_byte(0xD0 | encode);
1043 }
1046 void Assembler::call(Address adr) {
1047 InstructionMark im(this);
1048 prefix(adr);
1049 emit_byte(0xFF);
1050 emit_operand(rdx, adr);
1051 }
1053 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1054 assert(entry != NULL, "call most probably wrong");
1055 InstructionMark im(this);
1056 emit_byte(0xE8);
1057 intptr_t disp = entry - (_code_pos + sizeof(int32_t));
1058 assert(is_simm32(disp), "must be 32bit offset (call2)");
1059 // Technically, should use call32_operand, but this format is
1060 // implied by the fact that we're emitting a call instruction.
1062 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1063 emit_data((int) disp, rspec, operand);
1064 }
1066 void Assembler::cdql() {
1067 emit_byte(0x99);
1068 }
1070 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1071 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1072 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1073 emit_byte(0x0F);
1074 emit_byte(0x40 | cc);
1075 emit_byte(0xC0 | encode);
1076 }
1079 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1080 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1081 prefix(src, dst);
1082 emit_byte(0x0F);
1083 emit_byte(0x40 | cc);
1084 emit_operand(dst, src);
1085 }
1087 void Assembler::cmpb(Address dst, int imm8) {
1088 InstructionMark im(this);
1089 prefix(dst);
1090 emit_byte(0x80);
1091 emit_operand(rdi, dst, 1);
1092 emit_byte(imm8);
1093 }
1095 void Assembler::cmpl(Address dst, int32_t imm32) {
1096 InstructionMark im(this);
1097 prefix(dst);
1098 emit_byte(0x81);
1099 emit_operand(rdi, dst, 4);
1100 emit_long(imm32);
1101 }
1103 void Assembler::cmpl(Register dst, int32_t imm32) {
1104 prefix(dst);
1105 emit_arith(0x81, 0xF8, dst, imm32);
1106 }
1108 void Assembler::cmpl(Register dst, Register src) {
1109 (void) prefix_and_encode(dst->encoding(), src->encoding());
1110 emit_arith(0x3B, 0xC0, dst, src);
1111 }
1114 void Assembler::cmpl(Register dst, Address src) {
1115 InstructionMark im(this);
1116 prefix(src, dst);
1117 emit_byte(0x3B);
1118 emit_operand(dst, src);
1119 }
1121 void Assembler::cmpw(Address dst, int imm16) {
1122 InstructionMark im(this);
1123 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1124 emit_byte(0x66);
1125 emit_byte(0x81);
1126 emit_operand(rdi, dst, 2);
1127 emit_word(imm16);
1128 }
1130 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1131 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1132 // The ZF is set if the compared values were equal, and cleared otherwise.
1133 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1134 if (Atomics & 2) {
1135 // caveat: no instructionmark, so this isn't relocatable.
1136 // Emit a synthetic, non-atomic, CAS equivalent.
1137 // Beware. The synthetic form sets all ICCs, not just ZF.
1138 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1139 cmpl(rax, adr);
1140 movl(rax, adr);
1141 if (reg != rax) {
1142 Label L ;
1143 jcc(Assembler::notEqual, L);
1144 movl(adr, reg);
1145 bind(L);
1146 }
1147 } else {
1148 InstructionMark im(this);
1149 prefix(adr, reg);
1150 emit_byte(0x0F);
1151 emit_byte(0xB1);
1152 emit_operand(reg, adr);
1153 }
1154 }
1156 void Assembler::comisd(XMMRegister dst, Address src) {
1157 // NOTE: dbx seems to decode this as comiss even though the
1158 // 0x66 is there. Strangly ucomisd comes out correct
1159 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1160 emit_byte(0x66);
1161 comiss(dst, src);
1162 }
1164 void Assembler::comiss(XMMRegister dst, Address src) {
1165 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1167 InstructionMark im(this);
1168 prefix(src, dst);
1169 emit_byte(0x0F);
1170 emit_byte(0x2F);
1171 emit_operand(dst, src);
1172 }
1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1175 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1176 emit_byte(0xF3);
1177 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1178 emit_byte(0x0F);
1179 emit_byte(0xE6);
1180 emit_byte(0xC0 | encode);
1181 }
1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1184 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1185 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1186 emit_byte(0x0F);
1187 emit_byte(0x5B);
1188 emit_byte(0xC0 | encode);
1189 }
1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1192 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1193 emit_byte(0xF2);
1194 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1195 emit_byte(0x0F);
1196 emit_byte(0x5A);
1197 emit_byte(0xC0 | encode);
1198 }
1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1202 emit_byte(0xF2);
1203 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1204 emit_byte(0x0F);
1205 emit_byte(0x2A);
1206 emit_byte(0xC0 | encode);
1207 }
1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1210 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1211 emit_byte(0xF3);
1212 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1213 emit_byte(0x0F);
1214 emit_byte(0x2A);
1215 emit_byte(0xC0 | encode);
1216 }
1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1219 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1220 emit_byte(0xF3);
1221 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1222 emit_byte(0x0F);
1223 emit_byte(0x5A);
1224 emit_byte(0xC0 | encode);
1225 }
1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1228 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1229 emit_byte(0xF2);
1230 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1231 emit_byte(0x0F);
1232 emit_byte(0x2C);
1233 emit_byte(0xC0 | encode);
1234 }
1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1237 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1238 emit_byte(0xF3);
1239 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1240 emit_byte(0x0F);
1241 emit_byte(0x2C);
1242 emit_byte(0xC0 | encode);
1243 }
1245 void Assembler::decl(Address dst) {
1246 // Don't use it directly. Use MacroAssembler::decrement() instead.
1247 InstructionMark im(this);
1248 prefix(dst);
1249 emit_byte(0xFF);
1250 emit_operand(rcx, dst);
1251 }
1253 void Assembler::divsd(XMMRegister dst, Address src) {
1254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1255 InstructionMark im(this);
1256 emit_byte(0xF2);
1257 prefix(src, dst);
1258 emit_byte(0x0F);
1259 emit_byte(0x5E);
1260 emit_operand(dst, src);
1261 }
1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1265 emit_byte(0xF2);
1266 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1267 emit_byte(0x0F);
1268 emit_byte(0x5E);
1269 emit_byte(0xC0 | encode);
1270 }
1272 void Assembler::divss(XMMRegister dst, Address src) {
1273 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1274 InstructionMark im(this);
1275 emit_byte(0xF3);
1276 prefix(src, dst);
1277 emit_byte(0x0F);
1278 emit_byte(0x5E);
1279 emit_operand(dst, src);
1280 }
1282 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1283 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1284 emit_byte(0xF3);
1285 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1286 emit_byte(0x0F);
1287 emit_byte(0x5E);
1288 emit_byte(0xC0 | encode);
1289 }
1291 void Assembler::emms() {
1292 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1293 emit_byte(0x0F);
1294 emit_byte(0x77);
1295 }
1297 void Assembler::hlt() {
1298 emit_byte(0xF4);
1299 }
1301 void Assembler::idivl(Register src) {
1302 int encode = prefix_and_encode(src->encoding());
1303 emit_byte(0xF7);
1304 emit_byte(0xF8 | encode);
1305 }
1307 void Assembler::divl(Register src) { // Unsigned
1308 int encode = prefix_and_encode(src->encoding());
1309 emit_byte(0xF7);
1310 emit_byte(0xF0 | encode);
1311 }
1313 void Assembler::imull(Register dst, Register src) {
1314 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1315 emit_byte(0x0F);
1316 emit_byte(0xAF);
1317 emit_byte(0xC0 | encode);
1318 }
1321 void Assembler::imull(Register dst, Register src, int value) {
1322 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1323 if (is8bit(value)) {
1324 emit_byte(0x6B);
1325 emit_byte(0xC0 | encode);
1326 emit_byte(value & 0xFF);
1327 } else {
1328 emit_byte(0x69);
1329 emit_byte(0xC0 | encode);
1330 emit_long(value);
1331 }
1332 }
1334 void Assembler::incl(Address dst) {
1335 // Don't use it directly. Use MacroAssembler::increment() instead.
1336 InstructionMark im(this);
1337 prefix(dst);
1338 emit_byte(0xFF);
1339 emit_operand(rax, dst);
1340 }
1342 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
1343 InstructionMark im(this);
1344 relocate(rtype);
1345 assert((0 <= cc) && (cc < 16), "illegal cc");
1346 if (L.is_bound()) {
1347 address dst = target(L);
1348 assert(dst != NULL, "jcc most probably wrong");
1350 const int short_size = 2;
1351 const int long_size = 6;
1352 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos;
1353 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1354 // 0111 tttn #8-bit disp
1355 emit_byte(0x70 | cc);
1356 emit_byte((offs - short_size) & 0xFF);
1357 } else {
1358 // 0000 1111 1000 tttn #32-bit disp
1359 assert(is_simm32(offs - long_size),
1360 "must be 32bit offset (call4)");
1361 emit_byte(0x0F);
1362 emit_byte(0x80 | cc);
1363 emit_long(offs - long_size);
1364 }
1365 } else {
1366 // Note: could eliminate cond. jumps to this jump if condition
1367 // is the same however, seems to be rather unlikely case.
1368 // Note: use jccb() if label to be bound is very close to get
1369 // an 8-bit displacement
1370 L.add_patch_at(code(), locator());
1371 emit_byte(0x0F);
1372 emit_byte(0x80 | cc);
1373 emit_long(0);
1374 }
1375 }
1377 void Assembler::jccb(Condition cc, Label& L) {
1378 if (L.is_bound()) {
1379 const int short_size = 2;
1380 address entry = target(L);
1381 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
1382 "Dispacement too large for a short jmp");
1383 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1384 // 0111 tttn #8-bit disp
1385 emit_byte(0x70 | cc);
1386 emit_byte((offs - short_size) & 0xFF);
1387 } else {
1388 InstructionMark im(this);
1389 L.add_patch_at(code(), locator());
1390 emit_byte(0x70 | cc);
1391 emit_byte(0);
1392 }
1393 }
1395 void Assembler::jmp(Address adr) {
1396 InstructionMark im(this);
1397 prefix(adr);
1398 emit_byte(0xFF);
1399 emit_operand(rsp, adr);
1400 }
1402 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
1403 if (L.is_bound()) {
1404 address entry = target(L);
1405 assert(entry != NULL, "jmp most probably wrong");
1406 InstructionMark im(this);
1407 const int short_size = 2;
1408 const int long_size = 5;
1409 intptr_t offs = entry - _code_pos;
1410 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1411 emit_byte(0xEB);
1412 emit_byte((offs - short_size) & 0xFF);
1413 } else {
1414 emit_byte(0xE9);
1415 emit_long(offs - long_size);
1416 }
1417 } else {
1418 // By default, forward jumps are always 32-bit displacements, since
1419 // we can't yet know where the label will be bound. If you're sure that
1420 // the forward jump will not run beyond 256 bytes, use jmpb to
1421 // force an 8-bit displacement.
1422 InstructionMark im(this);
1423 relocate(rtype);
1424 L.add_patch_at(code(), locator());
1425 emit_byte(0xE9);
1426 emit_long(0);
1427 }
1428 }
1430 void Assembler::jmp(Register entry) {
1431 int encode = prefix_and_encode(entry->encoding());
1432 emit_byte(0xFF);
1433 emit_byte(0xE0 | encode);
1434 }
1436 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1437 InstructionMark im(this);
1438 emit_byte(0xE9);
1439 assert(dest != NULL, "must have a target");
1440 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1441 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1442 emit_data(disp, rspec.reloc(), call32_operand);
1443 }
1445 void Assembler::jmpb(Label& L) {
1446 if (L.is_bound()) {
1447 const int short_size = 2;
1448 address entry = target(L);
1449 assert(is8bit((entry - _code_pos) + short_size),
1450 "Dispacement too large for a short jmp");
1451 assert(entry != NULL, "jmp most probably wrong");
1452 intptr_t offs = entry - _code_pos;
1453 emit_byte(0xEB);
1454 emit_byte((offs - short_size) & 0xFF);
1455 } else {
1456 InstructionMark im(this);
1457 L.add_patch_at(code(), locator());
1458 emit_byte(0xEB);
1459 emit_byte(0);
1460 }
1461 }
1463 void Assembler::ldmxcsr( Address src) {
1464 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1465 InstructionMark im(this);
1466 prefix(src);
1467 emit_byte(0x0F);
1468 emit_byte(0xAE);
1469 emit_operand(as_Register(2), src);
1470 }
1472 void Assembler::leal(Register dst, Address src) {
1473 InstructionMark im(this);
1474 #ifdef _LP64
1475 emit_byte(0x67); // addr32
1476 prefix(src, dst);
1477 #endif // LP64
1478 emit_byte(0x8D);
1479 emit_operand(dst, src);
1480 }
1482 void Assembler::lock() {
1483 if (Atomics & 1) {
1484 // Emit either nothing, a NOP, or a NOP: prefix
1485 emit_byte(0x90) ;
1486 } else {
1487 emit_byte(0xF0);
1488 }
1489 }
1491 void Assembler::lzcntl(Register dst, Register src) {
1492 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1493 emit_byte(0xF3);
1494 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1495 emit_byte(0x0F);
1496 emit_byte(0xBD);
1497 emit_byte(0xC0 | encode);
1498 }
1500 // Emit mfence instruction
1501 void Assembler::mfence() {
1502 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1503 emit_byte( 0x0F );
1504 emit_byte( 0xAE );
1505 emit_byte( 0xF0 );
1506 }
1508 void Assembler::mov(Register dst, Register src) {
1509 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1510 }
1512 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1513 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1514 int dstenc = dst->encoding();
1515 int srcenc = src->encoding();
1516 emit_byte(0x66);
1517 if (dstenc < 8) {
1518 if (srcenc >= 8) {
1519 prefix(REX_B);
1520 srcenc -= 8;
1521 }
1522 } else {
1523 if (srcenc < 8) {
1524 prefix(REX_R);
1525 } else {
1526 prefix(REX_RB);
1527 srcenc -= 8;
1528 }
1529 dstenc -= 8;
1530 }
1531 emit_byte(0x0F);
1532 emit_byte(0x28);
1533 emit_byte(0xC0 | dstenc << 3 | srcenc);
1534 }
1536 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1537 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1538 int dstenc = dst->encoding();
1539 int srcenc = src->encoding();
1540 if (dstenc < 8) {
1541 if (srcenc >= 8) {
1542 prefix(REX_B);
1543 srcenc -= 8;
1544 }
1545 } else {
1546 if (srcenc < 8) {
1547 prefix(REX_R);
1548 } else {
1549 prefix(REX_RB);
1550 srcenc -= 8;
1551 }
1552 dstenc -= 8;
1553 }
1554 emit_byte(0x0F);
1555 emit_byte(0x28);
1556 emit_byte(0xC0 | dstenc << 3 | srcenc);
1557 }
1559 void Assembler::movb(Register dst, Address src) {
1560 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1561 InstructionMark im(this);
1562 prefix(src, dst, true);
1563 emit_byte(0x8A);
1564 emit_operand(dst, src);
1565 }
1568 void Assembler::movb(Address dst, int imm8) {
1569 InstructionMark im(this);
1570 prefix(dst);
1571 emit_byte(0xC6);
1572 emit_operand(rax, dst, 1);
1573 emit_byte(imm8);
1574 }
1577 void Assembler::movb(Address dst, Register src) {
1578 assert(src->has_byte_register(), "must have byte register");
1579 InstructionMark im(this);
1580 prefix(dst, src, true);
1581 emit_byte(0x88);
1582 emit_operand(src, dst);
1583 }
1585 void Assembler::movdl(XMMRegister dst, Register src) {
1586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1587 emit_byte(0x66);
1588 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1589 emit_byte(0x0F);
1590 emit_byte(0x6E);
1591 emit_byte(0xC0 | encode);
1592 }
1594 void Assembler::movdl(Register dst, XMMRegister src) {
1595 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1596 emit_byte(0x66);
1597 // swap src/dst to get correct prefix
1598 int encode = prefix_and_encode(src->encoding(), dst->encoding());
1599 emit_byte(0x0F);
1600 emit_byte(0x7E);
1601 emit_byte(0xC0 | encode);
1602 }
1604 void Assembler::movdl(XMMRegister dst, Address src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 InstructionMark im(this);
1607 emit_byte(0x66);
1608 prefix(src, dst);
1609 emit_byte(0x0F);
1610 emit_byte(0x6E);
1611 emit_operand(dst, src);
1612 }
1615 void Assembler::movdqa(XMMRegister dst, Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1617 InstructionMark im(this);
1618 emit_byte(0x66);
1619 prefix(src, dst);
1620 emit_byte(0x0F);
1621 emit_byte(0x6F);
1622 emit_operand(dst, src);
1623 }
1625 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1627 emit_byte(0x66);
1628 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1629 emit_byte(0x0F);
1630 emit_byte(0x6F);
1631 emit_byte(0xC0 | encode);
1632 }
1634 void Assembler::movdqa(Address dst, XMMRegister src) {
1635 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1636 InstructionMark im(this);
1637 emit_byte(0x66);
1638 prefix(dst, src);
1639 emit_byte(0x0F);
1640 emit_byte(0x7F);
1641 emit_operand(src, dst);
1642 }
1644 void Assembler::movdqu(XMMRegister dst, Address src) {
1645 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1646 InstructionMark im(this);
1647 emit_byte(0xF3);
1648 prefix(src, dst);
1649 emit_byte(0x0F);
1650 emit_byte(0x6F);
1651 emit_operand(dst, src);
1652 }
1654 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1655 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1656 emit_byte(0xF3);
1657 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
1658 emit_byte(0x0F);
1659 emit_byte(0x6F);
1660 emit_byte(0xC0 | encode);
1661 }
1663 void Assembler::movdqu(Address dst, XMMRegister src) {
1664 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1665 InstructionMark im(this);
1666 emit_byte(0xF3);
1667 prefix(dst, src);
1668 emit_byte(0x0F);
1669 emit_byte(0x7F);
1670 emit_operand(src, dst);
1671 }
1673 // Uses zero extension on 64bit
1675 void Assembler::movl(Register dst, int32_t imm32) {
1676 int encode = prefix_and_encode(dst->encoding());
1677 emit_byte(0xB8 | encode);
1678 emit_long(imm32);
1679 }
1681 void Assembler::movl(Register dst, Register src) {
1682 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1683 emit_byte(0x8B);
1684 emit_byte(0xC0 | encode);
1685 }
1687 void Assembler::movl(Register dst, Address src) {
1688 InstructionMark im(this);
1689 prefix(src, dst);
1690 emit_byte(0x8B);
1691 emit_operand(dst, src);
1692 }
1694 void Assembler::movl(Address dst, int32_t imm32) {
1695 InstructionMark im(this);
1696 prefix(dst);
1697 emit_byte(0xC7);
1698 emit_operand(rax, dst, 4);
1699 emit_long(imm32);
1700 }
1702 void Assembler::movl(Address dst, Register src) {
1703 InstructionMark im(this);
1704 prefix(dst, src);
1705 emit_byte(0x89);
1706 emit_operand(src, dst);
1707 }
1709 // New cpus require to use movsd and movss to avoid partial register stall
1710 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1711 // The selection is done in MacroAssembler::movdbl() and movflt().
1712 void Assembler::movlpd(XMMRegister dst, Address src) {
1713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1714 InstructionMark im(this);
1715 emit_byte(0x66);
1716 prefix(src, dst);
1717 emit_byte(0x0F);
1718 emit_byte(0x12);
1719 emit_operand(dst, src);
1720 }
1722 void Assembler::movq( MMXRegister dst, Address src ) {
1723 assert( VM_Version::supports_mmx(), "" );
1724 emit_byte(0x0F);
1725 emit_byte(0x6F);
1726 emit_operand(dst, src);
1727 }
1729 void Assembler::movq( Address dst, MMXRegister src ) {
1730 assert( VM_Version::supports_mmx(), "" );
1731 emit_byte(0x0F);
1732 emit_byte(0x7F);
1733 // workaround gcc (3.2.1-7a) bug
1734 // In that version of gcc with only an emit_operand(MMX, Address)
1735 // gcc will tail jump and try and reverse the parameters completely
1736 // obliterating dst in the process. By having a version available
1737 // that doesn't need to swap the args at the tail jump the bug is
1738 // avoided.
1739 emit_operand(dst, src);
1740 }
1742 void Assembler::movq(XMMRegister dst, Address src) {
1743 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1744 InstructionMark im(this);
1745 emit_byte(0xF3);
1746 prefix(src, dst);
1747 emit_byte(0x0F);
1748 emit_byte(0x7E);
1749 emit_operand(dst, src);
1750 }
1752 void Assembler::movq(Address dst, XMMRegister src) {
1753 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1754 InstructionMark im(this);
1755 emit_byte(0x66);
1756 prefix(dst, src);
1757 emit_byte(0x0F);
1758 emit_byte(0xD6);
1759 emit_operand(src, dst);
1760 }
1762 void Assembler::movsbl(Register dst, Address src) { // movsxb
1763 InstructionMark im(this);
1764 prefix(src, dst);
1765 emit_byte(0x0F);
1766 emit_byte(0xBE);
1767 emit_operand(dst, src);
1768 }
1770 void Assembler::movsbl(Register dst, Register src) { // movsxb
1771 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1772 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1773 emit_byte(0x0F);
1774 emit_byte(0xBE);
1775 emit_byte(0xC0 | encode);
1776 }
1778 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1780 emit_byte(0xF2);
1781 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1782 emit_byte(0x0F);
1783 emit_byte(0x10);
1784 emit_byte(0xC0 | encode);
1785 }
1787 void Assembler::movsd(XMMRegister dst, Address src) {
1788 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1789 InstructionMark im(this);
1790 emit_byte(0xF2);
1791 prefix(src, dst);
1792 emit_byte(0x0F);
1793 emit_byte(0x10);
1794 emit_operand(dst, src);
1795 }
1797 void Assembler::movsd(Address dst, XMMRegister src) {
1798 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1799 InstructionMark im(this);
1800 emit_byte(0xF2);
1801 prefix(dst, src);
1802 emit_byte(0x0F);
1803 emit_byte(0x11);
1804 emit_operand(src, dst);
1805 }
1807 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1808 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1809 emit_byte(0xF3);
1810 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1811 emit_byte(0x0F);
1812 emit_byte(0x10);
1813 emit_byte(0xC0 | encode);
1814 }
1816 void Assembler::movss(XMMRegister dst, Address src) {
1817 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1818 InstructionMark im(this);
1819 emit_byte(0xF3);
1820 prefix(src, dst);
1821 emit_byte(0x0F);
1822 emit_byte(0x10);
1823 emit_operand(dst, src);
1824 }
1826 void Assembler::movss(Address dst, XMMRegister src) {
1827 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1828 InstructionMark im(this);
1829 emit_byte(0xF3);
1830 prefix(dst, src);
1831 emit_byte(0x0F);
1832 emit_byte(0x11);
1833 emit_operand(src, dst);
1834 }
1836 void Assembler::movswl(Register dst, Address src) { // movsxw
1837 InstructionMark im(this);
1838 prefix(src, dst);
1839 emit_byte(0x0F);
1840 emit_byte(0xBF);
1841 emit_operand(dst, src);
1842 }
1844 void Assembler::movswl(Register dst, Register src) { // movsxw
1845 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1846 emit_byte(0x0F);
1847 emit_byte(0xBF);
1848 emit_byte(0xC0 | encode);
1849 }
1851 void Assembler::movw(Address dst, int imm16) {
1852 InstructionMark im(this);
1854 emit_byte(0x66); // switch to 16-bit mode
1855 prefix(dst);
1856 emit_byte(0xC7);
1857 emit_operand(rax, dst, 2);
1858 emit_word(imm16);
1859 }
1861 void Assembler::movw(Register dst, Address src) {
1862 InstructionMark im(this);
1863 emit_byte(0x66);
1864 prefix(src, dst);
1865 emit_byte(0x8B);
1866 emit_operand(dst, src);
1867 }
1869 void Assembler::movw(Address dst, Register src) {
1870 InstructionMark im(this);
1871 emit_byte(0x66);
1872 prefix(dst, src);
1873 emit_byte(0x89);
1874 emit_operand(src, dst);
1875 }
1877 void Assembler::movzbl(Register dst, Address src) { // movzxb
1878 InstructionMark im(this);
1879 prefix(src, dst);
1880 emit_byte(0x0F);
1881 emit_byte(0xB6);
1882 emit_operand(dst, src);
1883 }
1885 void Assembler::movzbl(Register dst, Register src) { // movzxb
1886 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1887 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1888 emit_byte(0x0F);
1889 emit_byte(0xB6);
1890 emit_byte(0xC0 | encode);
1891 }
1893 void Assembler::movzwl(Register dst, Address src) { // movzxw
1894 InstructionMark im(this);
1895 prefix(src, dst);
1896 emit_byte(0x0F);
1897 emit_byte(0xB7);
1898 emit_operand(dst, src);
1899 }
1901 void Assembler::movzwl(Register dst, Register src) { // movzxw
1902 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1903 emit_byte(0x0F);
1904 emit_byte(0xB7);
1905 emit_byte(0xC0 | encode);
1906 }
1908 void Assembler::mull(Address src) {
1909 InstructionMark im(this);
1910 prefix(src);
1911 emit_byte(0xF7);
1912 emit_operand(rsp, src);
1913 }
1915 void Assembler::mull(Register src) {
1916 int encode = prefix_and_encode(src->encoding());
1917 emit_byte(0xF7);
1918 emit_byte(0xE0 | encode);
1919 }
1921 void Assembler::mulsd(XMMRegister dst, Address src) {
1922 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1923 InstructionMark im(this);
1924 emit_byte(0xF2);
1925 prefix(src, dst);
1926 emit_byte(0x0F);
1927 emit_byte(0x59);
1928 emit_operand(dst, src);
1929 }
1931 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1932 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1933 emit_byte(0xF2);
1934 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1935 emit_byte(0x0F);
1936 emit_byte(0x59);
1937 emit_byte(0xC0 | encode);
1938 }
1940 void Assembler::mulss(XMMRegister dst, Address src) {
1941 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1942 InstructionMark im(this);
1943 emit_byte(0xF3);
1944 prefix(src, dst);
1945 emit_byte(0x0F);
1946 emit_byte(0x59);
1947 emit_operand(dst, src);
1948 }
1950 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1951 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1952 emit_byte(0xF3);
1953 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1954 emit_byte(0x0F);
1955 emit_byte(0x59);
1956 emit_byte(0xC0 | encode);
1957 }
1959 void Assembler::negl(Register dst) {
1960 int encode = prefix_and_encode(dst->encoding());
1961 emit_byte(0xF7);
1962 emit_byte(0xD8 | encode);
1963 }
1965 void Assembler::nop(int i) {
1966 #ifdef ASSERT
1967 assert(i > 0, " ");
1968 // The fancy nops aren't currently recognized by debuggers making it a
1969 // pain to disassemble code while debugging. If asserts are on clearly
1970 // speed is not an issue so simply use the single byte traditional nop
1971 // to do alignment.
1973 for (; i > 0 ; i--) emit_byte(0x90);
1974 return;
1976 #endif // ASSERT
1978 if (UseAddressNop && VM_Version::is_intel()) {
1979 //
1980 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1981 // 1: 0x90
1982 // 2: 0x66 0x90
1983 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1984 // 4: 0x0F 0x1F 0x40 0x00
1985 // 5: 0x0F 0x1F 0x44 0x00 0x00
1986 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1987 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1988 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1989 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1990 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1991 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1993 // The rest coding is Intel specific - don't use consecutive address nops
1995 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1996 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1997 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1998 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2000 while(i >= 15) {
2001 // For Intel don't generate consecutive addess nops (mix with regular nops)
2002 i -= 15;
2003 emit_byte(0x66); // size prefix
2004 emit_byte(0x66); // size prefix
2005 emit_byte(0x66); // size prefix
2006 addr_nop_8();
2007 emit_byte(0x66); // size prefix
2008 emit_byte(0x66); // size prefix
2009 emit_byte(0x66); // size prefix
2010 emit_byte(0x90); // nop
2011 }
2012 switch (i) {
2013 case 14:
2014 emit_byte(0x66); // size prefix
2015 case 13:
2016 emit_byte(0x66); // size prefix
2017 case 12:
2018 addr_nop_8();
2019 emit_byte(0x66); // size prefix
2020 emit_byte(0x66); // size prefix
2021 emit_byte(0x66); // size prefix
2022 emit_byte(0x90); // nop
2023 break;
2024 case 11:
2025 emit_byte(0x66); // size prefix
2026 case 10:
2027 emit_byte(0x66); // size prefix
2028 case 9:
2029 emit_byte(0x66); // size prefix
2030 case 8:
2031 addr_nop_8();
2032 break;
2033 case 7:
2034 addr_nop_7();
2035 break;
2036 case 6:
2037 emit_byte(0x66); // size prefix
2038 case 5:
2039 addr_nop_5();
2040 break;
2041 case 4:
2042 addr_nop_4();
2043 break;
2044 case 3:
2045 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2046 emit_byte(0x66); // size prefix
2047 case 2:
2048 emit_byte(0x66); // size prefix
2049 case 1:
2050 emit_byte(0x90); // nop
2051 break;
2052 default:
2053 assert(i == 0, " ");
2054 }
2055 return;
2056 }
2057 if (UseAddressNop && VM_Version::is_amd()) {
2058 //
2059 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2060 // 1: 0x90
2061 // 2: 0x66 0x90
2062 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2063 // 4: 0x0F 0x1F 0x40 0x00
2064 // 5: 0x0F 0x1F 0x44 0x00 0x00
2065 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2066 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2067 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2068 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2069 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2070 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2072 // The rest coding is AMD specific - use consecutive address nops
2074 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2075 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2076 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2077 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2078 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2079 // Size prefixes (0x66) are added for larger sizes
2081 while(i >= 22) {
2082 i -= 11;
2083 emit_byte(0x66); // size prefix
2084 emit_byte(0x66); // size prefix
2085 emit_byte(0x66); // size prefix
2086 addr_nop_8();
2087 }
2088 // Generate first nop for size between 21-12
2089 switch (i) {
2090 case 21:
2091 i -= 1;
2092 emit_byte(0x66); // size prefix
2093 case 20:
2094 case 19:
2095 i -= 1;
2096 emit_byte(0x66); // size prefix
2097 case 18:
2098 case 17:
2099 i -= 1;
2100 emit_byte(0x66); // size prefix
2101 case 16:
2102 case 15:
2103 i -= 8;
2104 addr_nop_8();
2105 break;
2106 case 14:
2107 case 13:
2108 i -= 7;
2109 addr_nop_7();
2110 break;
2111 case 12:
2112 i -= 6;
2113 emit_byte(0x66); // size prefix
2114 addr_nop_5();
2115 break;
2116 default:
2117 assert(i < 12, " ");
2118 }
2120 // Generate second nop for size between 11-1
2121 switch (i) {
2122 case 11:
2123 emit_byte(0x66); // size prefix
2124 case 10:
2125 emit_byte(0x66); // size prefix
2126 case 9:
2127 emit_byte(0x66); // size prefix
2128 case 8:
2129 addr_nop_8();
2130 break;
2131 case 7:
2132 addr_nop_7();
2133 break;
2134 case 6:
2135 emit_byte(0x66); // size prefix
2136 case 5:
2137 addr_nop_5();
2138 break;
2139 case 4:
2140 addr_nop_4();
2141 break;
2142 case 3:
2143 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2144 emit_byte(0x66); // size prefix
2145 case 2:
2146 emit_byte(0x66); // size prefix
2147 case 1:
2148 emit_byte(0x90); // nop
2149 break;
2150 default:
2151 assert(i == 0, " ");
2152 }
2153 return;
2154 }
2156 // Using nops with size prefixes "0x66 0x90".
2157 // From AMD Optimization Guide:
2158 // 1: 0x90
2159 // 2: 0x66 0x90
2160 // 3: 0x66 0x66 0x90
2161 // 4: 0x66 0x66 0x66 0x90
2162 // 5: 0x66 0x66 0x90 0x66 0x90
2163 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2164 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2165 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2166 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2167 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2168 //
2169 while(i > 12) {
2170 i -= 4;
2171 emit_byte(0x66); // size prefix
2172 emit_byte(0x66);
2173 emit_byte(0x66);
2174 emit_byte(0x90); // nop
2175 }
2176 // 1 - 12 nops
2177 if(i > 8) {
2178 if(i > 9) {
2179 i -= 1;
2180 emit_byte(0x66);
2181 }
2182 i -= 3;
2183 emit_byte(0x66);
2184 emit_byte(0x66);
2185 emit_byte(0x90);
2186 }
2187 // 1 - 8 nops
2188 if(i > 4) {
2189 if(i > 6) {
2190 i -= 1;
2191 emit_byte(0x66);
2192 }
2193 i -= 3;
2194 emit_byte(0x66);
2195 emit_byte(0x66);
2196 emit_byte(0x90);
2197 }
2198 switch (i) {
2199 case 4:
2200 emit_byte(0x66);
2201 case 3:
2202 emit_byte(0x66);
2203 case 2:
2204 emit_byte(0x66);
2205 case 1:
2206 emit_byte(0x90);
2207 break;
2208 default:
2209 assert(i == 0, " ");
2210 }
2211 }
2213 void Assembler::notl(Register dst) {
2214 int encode = prefix_and_encode(dst->encoding());
2215 emit_byte(0xF7);
2216 emit_byte(0xD0 | encode );
2217 }
2219 void Assembler::orl(Address dst, int32_t imm32) {
2220 InstructionMark im(this);
2221 prefix(dst);
2222 emit_arith_operand(0x81, rcx, dst, imm32);
2223 }
2225 void Assembler::orl(Register dst, int32_t imm32) {
2226 prefix(dst);
2227 emit_arith(0x81, 0xC8, dst, imm32);
2228 }
2230 void Assembler::orl(Register dst, Address src) {
2231 InstructionMark im(this);
2232 prefix(src, dst);
2233 emit_byte(0x0B);
2234 emit_operand(dst, src);
2235 }
2237 void Assembler::orl(Register dst, Register src) {
2238 (void) prefix_and_encode(dst->encoding(), src->encoding());
2239 emit_arith(0x0B, 0xC0, dst, src);
2240 }
2242 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2243 assert(VM_Version::supports_sse4_2(), "");
2245 InstructionMark im(this);
2246 emit_byte(0x66);
2247 prefix(src, dst);
2248 emit_byte(0x0F);
2249 emit_byte(0x3A);
2250 emit_byte(0x61);
2251 emit_operand(dst, src);
2252 emit_byte(imm8);
2253 }
2255 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2256 assert(VM_Version::supports_sse4_2(), "");
2258 emit_byte(0x66);
2259 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2260 emit_byte(0x0F);
2261 emit_byte(0x3A);
2262 emit_byte(0x61);
2263 emit_byte(0xC0 | encode);
2264 emit_byte(imm8);
2265 }
2267 // generic
2268 void Assembler::pop(Register dst) {
2269 int encode = prefix_and_encode(dst->encoding());
2270 emit_byte(0x58 | encode);
2271 }
2273 void Assembler::popcntl(Register dst, Address src) {
2274 assert(VM_Version::supports_popcnt(), "must support");
2275 InstructionMark im(this);
2276 emit_byte(0xF3);
2277 prefix(src, dst);
2278 emit_byte(0x0F);
2279 emit_byte(0xB8);
2280 emit_operand(dst, src);
2281 }
2283 void Assembler::popcntl(Register dst, Register src) {
2284 assert(VM_Version::supports_popcnt(), "must support");
2285 emit_byte(0xF3);
2286 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2287 emit_byte(0x0F);
2288 emit_byte(0xB8);
2289 emit_byte(0xC0 | encode);
2290 }
2292 void Assembler::popf() {
2293 emit_byte(0x9D);
2294 }
2296 #ifndef _LP64 // no 32bit push/pop on amd64
2297 void Assembler::popl(Address dst) {
2298 // NOTE: this will adjust stack by 8byte on 64bits
2299 InstructionMark im(this);
2300 prefix(dst);
2301 emit_byte(0x8F);
2302 emit_operand(rax, dst);
2303 }
2304 #endif
2306 void Assembler::prefetch_prefix(Address src) {
2307 prefix(src);
2308 emit_byte(0x0F);
2309 }
2311 void Assembler::prefetchnta(Address src) {
2312 NOT_LP64(assert(VM_Version::supports_sse2(), "must support"));
2313 InstructionMark im(this);
2314 prefetch_prefix(src);
2315 emit_byte(0x18);
2316 emit_operand(rax, src); // 0, src
2317 }
2319 void Assembler::prefetchr(Address src) {
2320 NOT_LP64(assert(VM_Version::supports_3dnow_prefetch(), "must support"));
2321 InstructionMark im(this);
2322 prefetch_prefix(src);
2323 emit_byte(0x0D);
2324 emit_operand(rax, src); // 0, src
2325 }
2327 void Assembler::prefetcht0(Address src) {
2328 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2329 InstructionMark im(this);
2330 prefetch_prefix(src);
2331 emit_byte(0x18);
2332 emit_operand(rcx, src); // 1, src
2333 }
2335 void Assembler::prefetcht1(Address src) {
2336 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2337 InstructionMark im(this);
2338 prefetch_prefix(src);
2339 emit_byte(0x18);
2340 emit_operand(rdx, src); // 2, src
2341 }
2343 void Assembler::prefetcht2(Address src) {
2344 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2345 InstructionMark im(this);
2346 prefetch_prefix(src);
2347 emit_byte(0x18);
2348 emit_operand(rbx, src); // 3, src
2349 }
2351 void Assembler::prefetchw(Address src) {
2352 NOT_LP64(assert(VM_Version::supports_3dnow_prefetch(), "must support"));
2353 InstructionMark im(this);
2354 prefetch_prefix(src);
2355 emit_byte(0x0D);
2356 emit_operand(rcx, src); // 1, src
2357 }
2359 void Assembler::prefix(Prefix p) {
2360 a_byte(p);
2361 }
2363 void Assembler::por(XMMRegister dst, XMMRegister src) {
2364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2366 emit_byte(0x66);
2367 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2368 emit_byte(0x0F);
2370 emit_byte(0xEB);
2371 emit_byte(0xC0 | encode);
2372 }
2374 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2375 assert(isByte(mode), "invalid value");
2376 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2378 emit_byte(0x66);
2379 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2380 emit_byte(0x0F);
2381 emit_byte(0x70);
2382 emit_byte(0xC0 | encode);
2383 emit_byte(mode & 0xFF);
2385 }
2387 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2388 assert(isByte(mode), "invalid value");
2389 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2391 InstructionMark im(this);
2392 emit_byte(0x66);
2393 prefix(src, dst);
2394 emit_byte(0x0F);
2395 emit_byte(0x70);
2396 emit_operand(dst, src);
2397 emit_byte(mode & 0xFF);
2398 }
2400 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2401 assert(isByte(mode), "invalid value");
2402 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2404 emit_byte(0xF2);
2405 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2406 emit_byte(0x0F);
2407 emit_byte(0x70);
2408 emit_byte(0xC0 | encode);
2409 emit_byte(mode & 0xFF);
2410 }
2412 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2413 assert(isByte(mode), "invalid value");
2414 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2416 InstructionMark im(this);
2417 emit_byte(0xF2);
2418 prefix(src, dst); // QQ new
2419 emit_byte(0x0F);
2420 emit_byte(0x70);
2421 emit_operand(dst, src);
2422 emit_byte(mode & 0xFF);
2423 }
2425 void Assembler::psrlq(XMMRegister dst, int shift) {
2426 // Shift 64 bit value logically right by specified number of bits.
2427 // HMM Table D-1 says sse2 or mmx.
2428 // Do not confuse it with psrldq SSE2 instruction which
2429 // shifts 128 bit value in xmm register by number of bytes.
2430 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2432 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding());
2433 emit_byte(0x66);
2434 emit_byte(0x0F);
2435 emit_byte(0x73);
2436 emit_byte(0xC0 | encode);
2437 emit_byte(shift);
2438 }
2440 void Assembler::psrldq(XMMRegister dst, int shift) {
2441 // Shift 128 bit value in xmm register by number of bytes.
2442 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2444 int encode = prefixq_and_encode(xmm3->encoding(), dst->encoding());
2445 emit_byte(0x66);
2446 emit_byte(0x0F);
2447 emit_byte(0x73);
2448 emit_byte(0xC0 | encode);
2449 emit_byte(shift);
2450 }
2452 void Assembler::ptest(XMMRegister dst, Address src) {
2453 assert(VM_Version::supports_sse4_1(), "");
2455 InstructionMark im(this);
2456 emit_byte(0x66);
2457 prefix(src, dst);
2458 emit_byte(0x0F);
2459 emit_byte(0x38);
2460 emit_byte(0x17);
2461 emit_operand(dst, src);
2462 }
2464 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2465 assert(VM_Version::supports_sse4_1(), "");
2467 emit_byte(0x66);
2468 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2469 emit_byte(0x0F);
2470 emit_byte(0x38);
2471 emit_byte(0x17);
2472 emit_byte(0xC0 | encode);
2473 }
2475 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2476 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2477 emit_byte(0x66);
2478 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2479 emit_byte(0x0F);
2480 emit_byte(0x60);
2481 emit_byte(0xC0 | encode);
2482 }
2484 void Assembler::push(int32_t imm32) {
2485 // in 64bits we push 64bits onto the stack but only
2486 // take a 32bit immediate
2487 emit_byte(0x68);
2488 emit_long(imm32);
2489 }
2491 void Assembler::push(Register src) {
2492 int encode = prefix_and_encode(src->encoding());
2494 emit_byte(0x50 | encode);
2495 }
2497 void Assembler::pushf() {
2498 emit_byte(0x9C);
2499 }
2501 #ifndef _LP64 // no 32bit push/pop on amd64
2502 void Assembler::pushl(Address src) {
2503 // Note this will push 64bit on 64bit
2504 InstructionMark im(this);
2505 prefix(src);
2506 emit_byte(0xFF);
2507 emit_operand(rsi, src);
2508 }
2509 #endif
2511 void Assembler::pxor(XMMRegister dst, Address src) {
2512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2513 InstructionMark im(this);
2514 emit_byte(0x66);
2515 prefix(src, dst);
2516 emit_byte(0x0F);
2517 emit_byte(0xEF);
2518 emit_operand(dst, src);
2519 }
2521 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2522 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2523 InstructionMark im(this);
2524 emit_byte(0x66);
2525 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2526 emit_byte(0x0F);
2527 emit_byte(0xEF);
2528 emit_byte(0xC0 | encode);
2529 }
2531 void Assembler::rcll(Register dst, int imm8) {
2532 assert(isShiftCount(imm8), "illegal shift count");
2533 int encode = prefix_and_encode(dst->encoding());
2534 if (imm8 == 1) {
2535 emit_byte(0xD1);
2536 emit_byte(0xD0 | encode);
2537 } else {
2538 emit_byte(0xC1);
2539 emit_byte(0xD0 | encode);
2540 emit_byte(imm8);
2541 }
2542 }
2544 // copies data from [esi] to [edi] using rcx pointer sized words
2545 // generic
2546 void Assembler::rep_mov() {
2547 emit_byte(0xF3);
2548 // MOVSQ
2549 LP64_ONLY(prefix(REX_W));
2550 emit_byte(0xA5);
2551 }
2553 // sets rcx pointer sized words with rax, value at [edi]
2554 // generic
2555 void Assembler::rep_set() { // rep_set
2556 emit_byte(0xF3);
2557 // STOSQ
2558 LP64_ONLY(prefix(REX_W));
2559 emit_byte(0xAB);
2560 }
2562 // scans rcx pointer sized words at [edi] for occurance of rax,
2563 // generic
2564 void Assembler::repne_scan() { // repne_scan
2565 emit_byte(0xF2);
2566 // SCASQ
2567 LP64_ONLY(prefix(REX_W));
2568 emit_byte(0xAF);
2569 }
2571 #ifdef _LP64
2572 // scans rcx 4 byte words at [edi] for occurance of rax,
2573 // generic
2574 void Assembler::repne_scanl() { // repne_scan
2575 emit_byte(0xF2);
2576 // SCASL
2577 emit_byte(0xAF);
2578 }
2579 #endif
2581 void Assembler::ret(int imm16) {
2582 if (imm16 == 0) {
2583 emit_byte(0xC3);
2584 } else {
2585 emit_byte(0xC2);
2586 emit_word(imm16);
2587 }
2588 }
2590 void Assembler::sahf() {
2591 #ifdef _LP64
2592 // Not supported in 64bit mode
2593 ShouldNotReachHere();
2594 #endif
2595 emit_byte(0x9E);
2596 }
2598 void Assembler::sarl(Register dst, int imm8) {
2599 int encode = prefix_and_encode(dst->encoding());
2600 assert(isShiftCount(imm8), "illegal shift count");
2601 if (imm8 == 1) {
2602 emit_byte(0xD1);
2603 emit_byte(0xF8 | encode);
2604 } else {
2605 emit_byte(0xC1);
2606 emit_byte(0xF8 | encode);
2607 emit_byte(imm8);
2608 }
2609 }
2611 void Assembler::sarl(Register dst) {
2612 int encode = prefix_and_encode(dst->encoding());
2613 emit_byte(0xD3);
2614 emit_byte(0xF8 | encode);
2615 }
2617 void Assembler::sbbl(Address dst, int32_t imm32) {
2618 InstructionMark im(this);
2619 prefix(dst);
2620 emit_arith_operand(0x81, rbx, dst, imm32);
2621 }
2623 void Assembler::sbbl(Register dst, int32_t imm32) {
2624 prefix(dst);
2625 emit_arith(0x81, 0xD8, dst, imm32);
2626 }
2629 void Assembler::sbbl(Register dst, Address src) {
2630 InstructionMark im(this);
2631 prefix(src, dst);
2632 emit_byte(0x1B);
2633 emit_operand(dst, src);
2634 }
2636 void Assembler::sbbl(Register dst, Register src) {
2637 (void) prefix_and_encode(dst->encoding(), src->encoding());
2638 emit_arith(0x1B, 0xC0, dst, src);
2639 }
2641 void Assembler::setb(Condition cc, Register dst) {
2642 assert(0 <= cc && cc < 16, "illegal cc");
2643 int encode = prefix_and_encode(dst->encoding(), true);
2644 emit_byte(0x0F);
2645 emit_byte(0x90 | cc);
2646 emit_byte(0xC0 | encode);
2647 }
2649 void Assembler::shll(Register dst, int imm8) {
2650 assert(isShiftCount(imm8), "illegal shift count");
2651 int encode = prefix_and_encode(dst->encoding());
2652 if (imm8 == 1 ) {
2653 emit_byte(0xD1);
2654 emit_byte(0xE0 | encode);
2655 } else {
2656 emit_byte(0xC1);
2657 emit_byte(0xE0 | encode);
2658 emit_byte(imm8);
2659 }
2660 }
2662 void Assembler::shll(Register dst) {
2663 int encode = prefix_and_encode(dst->encoding());
2664 emit_byte(0xD3);
2665 emit_byte(0xE0 | encode);
2666 }
2668 void Assembler::shrl(Register dst, int imm8) {
2669 assert(isShiftCount(imm8), "illegal shift count");
2670 int encode = prefix_and_encode(dst->encoding());
2671 emit_byte(0xC1);
2672 emit_byte(0xE8 | encode);
2673 emit_byte(imm8);
2674 }
2676 void Assembler::shrl(Register dst) {
2677 int encode = prefix_and_encode(dst->encoding());
2678 emit_byte(0xD3);
2679 emit_byte(0xE8 | encode);
2680 }
2682 // copies a single word from [esi] to [edi]
2683 void Assembler::smovl() {
2684 emit_byte(0xA5);
2685 }
2687 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2688 // HMM Table D-1 says sse2
2689 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2690 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2691 emit_byte(0xF2);
2692 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2693 emit_byte(0x0F);
2694 emit_byte(0x51);
2695 emit_byte(0xC0 | encode);
2696 }
2698 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2699 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2700 InstructionMark im(this);
2701 emit_byte(0xF2);
2702 prefix(src, dst);
2703 emit_byte(0x0F);
2704 emit_byte(0x51);
2705 emit_operand(dst, src);
2706 }
2708 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2709 // HMM Table D-1 says sse2
2710 // NOT_LP64(assert(VM_Version::supports_sse(), ""));
2711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2712 emit_byte(0xF3);
2713 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2714 emit_byte(0x0F);
2715 emit_byte(0x51);
2716 emit_byte(0xC0 | encode);
2717 }
2719 void Assembler::sqrtss(XMMRegister dst, Address src) {
2720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2721 InstructionMark im(this);
2722 emit_byte(0xF3);
2723 prefix(src, dst);
2724 emit_byte(0x0F);
2725 emit_byte(0x51);
2726 emit_operand(dst, src);
2727 }
2729 void Assembler::stmxcsr( Address dst) {
2730 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2731 InstructionMark im(this);
2732 prefix(dst);
2733 emit_byte(0x0F);
2734 emit_byte(0xAE);
2735 emit_operand(as_Register(3), dst);
2736 }
2738 void Assembler::subl(Address dst, int32_t imm32) {
2739 InstructionMark im(this);
2740 prefix(dst);
2741 emit_arith_operand(0x81, rbp, dst, imm32);
2742 }
2744 void Assembler::subl(Address dst, Register src) {
2745 InstructionMark im(this);
2746 prefix(dst, src);
2747 emit_byte(0x29);
2748 emit_operand(src, dst);
2749 }
2751 void Assembler::subl(Register dst, int32_t imm32) {
2752 prefix(dst);
2753 emit_arith(0x81, 0xE8, dst, imm32);
2754 }
2756 void Assembler::subl(Register dst, Address src) {
2757 InstructionMark im(this);
2758 prefix(src, dst);
2759 emit_byte(0x2B);
2760 emit_operand(dst, src);
2761 }
2763 void Assembler::subl(Register dst, Register src) {
2764 (void) prefix_and_encode(dst->encoding(), src->encoding());
2765 emit_arith(0x2B, 0xC0, dst, src);
2766 }
2768 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2769 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2770 emit_byte(0xF2);
2771 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2772 emit_byte(0x0F);
2773 emit_byte(0x5C);
2774 emit_byte(0xC0 | encode);
2775 }
2777 void Assembler::subsd(XMMRegister dst, Address src) {
2778 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2779 InstructionMark im(this);
2780 emit_byte(0xF2);
2781 prefix(src, dst);
2782 emit_byte(0x0F);
2783 emit_byte(0x5C);
2784 emit_operand(dst, src);
2785 }
2787 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2788 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2789 emit_byte(0xF3);
2790 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2791 emit_byte(0x0F);
2792 emit_byte(0x5C);
2793 emit_byte(0xC0 | encode);
2794 }
2796 void Assembler::subss(XMMRegister dst, Address src) {
2797 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2798 InstructionMark im(this);
2799 emit_byte(0xF3);
2800 prefix(src, dst);
2801 emit_byte(0x0F);
2802 emit_byte(0x5C);
2803 emit_operand(dst, src);
2804 }
2806 void Assembler::testb(Register dst, int imm8) {
2807 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2808 (void) prefix_and_encode(dst->encoding(), true);
2809 emit_arith_b(0xF6, 0xC0, dst, imm8);
2810 }
2812 void Assembler::testl(Register dst, int32_t imm32) {
2813 // not using emit_arith because test
2814 // doesn't support sign-extension of
2815 // 8bit operands
2816 int encode = dst->encoding();
2817 if (encode == 0) {
2818 emit_byte(0xA9);
2819 } else {
2820 encode = prefix_and_encode(encode);
2821 emit_byte(0xF7);
2822 emit_byte(0xC0 | encode);
2823 }
2824 emit_long(imm32);
2825 }
2827 void Assembler::testl(Register dst, Register src) {
2828 (void) prefix_and_encode(dst->encoding(), src->encoding());
2829 emit_arith(0x85, 0xC0, dst, src);
2830 }
2832 void Assembler::testl(Register dst, Address src) {
2833 InstructionMark im(this);
2834 prefix(src, dst);
2835 emit_byte(0x85);
2836 emit_operand(dst, src);
2837 }
2839 void Assembler::ucomisd(XMMRegister dst, Address src) {
2840 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2841 emit_byte(0x66);
2842 ucomiss(dst, src);
2843 }
2845 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2846 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2847 emit_byte(0x66);
2848 ucomiss(dst, src);
2849 }
2851 void Assembler::ucomiss(XMMRegister dst, Address src) {
2852 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2854 InstructionMark im(this);
2855 prefix(src, dst);
2856 emit_byte(0x0F);
2857 emit_byte(0x2E);
2858 emit_operand(dst, src);
2859 }
2861 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2862 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2863 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2864 emit_byte(0x0F);
2865 emit_byte(0x2E);
2866 emit_byte(0xC0 | encode);
2867 }
2870 void Assembler::xaddl(Address dst, Register src) {
2871 InstructionMark im(this);
2872 prefix(dst, src);
2873 emit_byte(0x0F);
2874 emit_byte(0xC1);
2875 emit_operand(src, dst);
2876 }
2878 void Assembler::xchgl(Register dst, Address src) { // xchg
2879 InstructionMark im(this);
2880 prefix(src, dst);
2881 emit_byte(0x87);
2882 emit_operand(dst, src);
2883 }
2885 void Assembler::xchgl(Register dst, Register src) {
2886 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2887 emit_byte(0x87);
2888 emit_byte(0xc0 | encode);
2889 }
2891 void Assembler::xorl(Register dst, int32_t imm32) {
2892 prefix(dst);
2893 emit_arith(0x81, 0xF0, dst, imm32);
2894 }
2896 void Assembler::xorl(Register dst, Address src) {
2897 InstructionMark im(this);
2898 prefix(src, dst);
2899 emit_byte(0x33);
2900 emit_operand(dst, src);
2901 }
2903 void Assembler::xorl(Register dst, Register src) {
2904 (void) prefix_and_encode(dst->encoding(), src->encoding());
2905 emit_arith(0x33, 0xC0, dst, src);
2906 }
2908 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2910 emit_byte(0x66);
2911 xorps(dst, src);
2912 }
2914 void Assembler::xorpd(XMMRegister dst, Address src) {
2915 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2916 InstructionMark im(this);
2917 emit_byte(0x66);
2918 prefix(src, dst);
2919 emit_byte(0x0F);
2920 emit_byte(0x57);
2921 emit_operand(dst, src);
2922 }
2925 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2926 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2927 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2928 emit_byte(0x0F);
2929 emit_byte(0x57);
2930 emit_byte(0xC0 | encode);
2931 }
2933 void Assembler::xorps(XMMRegister dst, Address src) {
2934 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2935 InstructionMark im(this);
2936 prefix(src, dst);
2937 emit_byte(0x0F);
2938 emit_byte(0x57);
2939 emit_operand(dst, src);
2940 }
2942 #ifndef _LP64
2943 // 32bit only pieces of the assembler
2945 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
2946 // NO PREFIX AS NEVER 64BIT
2947 InstructionMark im(this);
2948 emit_byte(0x81);
2949 emit_byte(0xF8 | src1->encoding());
2950 emit_data(imm32, rspec, 0);
2951 }
2953 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
2954 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
2955 InstructionMark im(this);
2956 emit_byte(0x81);
2957 emit_operand(rdi, src1);
2958 emit_data(imm32, rspec, 0);
2959 }
2961 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
2962 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
2963 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
2964 void Assembler::cmpxchg8(Address adr) {
2965 InstructionMark im(this);
2966 emit_byte(0x0F);
2967 emit_byte(0xc7);
2968 emit_operand(rcx, adr);
2969 }
2971 void Assembler::decl(Register dst) {
2972 // Don't use it directly. Use MacroAssembler::decrementl() instead.
2973 emit_byte(0x48 | dst->encoding());
2974 }
2976 #endif // _LP64
2978 // 64bit typically doesn't use the x87 but needs to for the trig funcs
2980 void Assembler::fabs() {
2981 emit_byte(0xD9);
2982 emit_byte(0xE1);
2983 }
2985 void Assembler::fadd(int i) {
2986 emit_farith(0xD8, 0xC0, i);
2987 }
2989 void Assembler::fadd_d(Address src) {
2990 InstructionMark im(this);
2991 emit_byte(0xDC);
2992 emit_operand32(rax, src);
2993 }
2995 void Assembler::fadd_s(Address src) {
2996 InstructionMark im(this);
2997 emit_byte(0xD8);
2998 emit_operand32(rax, src);
2999 }
3001 void Assembler::fadda(int i) {
3002 emit_farith(0xDC, 0xC0, i);
3003 }
3005 void Assembler::faddp(int i) {
3006 emit_farith(0xDE, 0xC0, i);
3007 }
3009 void Assembler::fchs() {
3010 emit_byte(0xD9);
3011 emit_byte(0xE0);
3012 }
3014 void Assembler::fcom(int i) {
3015 emit_farith(0xD8, 0xD0, i);
3016 }
3018 void Assembler::fcomp(int i) {
3019 emit_farith(0xD8, 0xD8, i);
3020 }
3022 void Assembler::fcomp_d(Address src) {
3023 InstructionMark im(this);
3024 emit_byte(0xDC);
3025 emit_operand32(rbx, src);
3026 }
3028 void Assembler::fcomp_s(Address src) {
3029 InstructionMark im(this);
3030 emit_byte(0xD8);
3031 emit_operand32(rbx, src);
3032 }
3034 void Assembler::fcompp() {
3035 emit_byte(0xDE);
3036 emit_byte(0xD9);
3037 }
3039 void Assembler::fcos() {
3040 emit_byte(0xD9);
3041 emit_byte(0xFF);
3042 }
3044 void Assembler::fdecstp() {
3045 emit_byte(0xD9);
3046 emit_byte(0xF6);
3047 }
3049 void Assembler::fdiv(int i) {
3050 emit_farith(0xD8, 0xF0, i);
3051 }
3053 void Assembler::fdiv_d(Address src) {
3054 InstructionMark im(this);
3055 emit_byte(0xDC);
3056 emit_operand32(rsi, src);
3057 }
3059 void Assembler::fdiv_s(Address src) {
3060 InstructionMark im(this);
3061 emit_byte(0xD8);
3062 emit_operand32(rsi, src);
3063 }
3065 void Assembler::fdiva(int i) {
3066 emit_farith(0xDC, 0xF8, i);
3067 }
3069 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3070 // is erroneous for some of the floating-point instructions below.
3072 void Assembler::fdivp(int i) {
3073 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3074 }
3076 void Assembler::fdivr(int i) {
3077 emit_farith(0xD8, 0xF8, i);
3078 }
3080 void Assembler::fdivr_d(Address src) {
3081 InstructionMark im(this);
3082 emit_byte(0xDC);
3083 emit_operand32(rdi, src);
3084 }
3086 void Assembler::fdivr_s(Address src) {
3087 InstructionMark im(this);
3088 emit_byte(0xD8);
3089 emit_operand32(rdi, src);
3090 }
3092 void Assembler::fdivra(int i) {
3093 emit_farith(0xDC, 0xF0, i);
3094 }
3096 void Assembler::fdivrp(int i) {
3097 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3098 }
3100 void Assembler::ffree(int i) {
3101 emit_farith(0xDD, 0xC0, i);
3102 }
3104 void Assembler::fild_d(Address adr) {
3105 InstructionMark im(this);
3106 emit_byte(0xDF);
3107 emit_operand32(rbp, adr);
3108 }
3110 void Assembler::fild_s(Address adr) {
3111 InstructionMark im(this);
3112 emit_byte(0xDB);
3113 emit_operand32(rax, adr);
3114 }
3116 void Assembler::fincstp() {
3117 emit_byte(0xD9);
3118 emit_byte(0xF7);
3119 }
3121 void Assembler::finit() {
3122 emit_byte(0x9B);
3123 emit_byte(0xDB);
3124 emit_byte(0xE3);
3125 }
3127 void Assembler::fist_s(Address adr) {
3128 InstructionMark im(this);
3129 emit_byte(0xDB);
3130 emit_operand32(rdx, adr);
3131 }
3133 void Assembler::fistp_d(Address adr) {
3134 InstructionMark im(this);
3135 emit_byte(0xDF);
3136 emit_operand32(rdi, adr);
3137 }
3139 void Assembler::fistp_s(Address adr) {
3140 InstructionMark im(this);
3141 emit_byte(0xDB);
3142 emit_operand32(rbx, adr);
3143 }
3145 void Assembler::fld1() {
3146 emit_byte(0xD9);
3147 emit_byte(0xE8);
3148 }
3150 void Assembler::fld_d(Address adr) {
3151 InstructionMark im(this);
3152 emit_byte(0xDD);
3153 emit_operand32(rax, adr);
3154 }
3156 void Assembler::fld_s(Address adr) {
3157 InstructionMark im(this);
3158 emit_byte(0xD9);
3159 emit_operand32(rax, adr);
3160 }
3163 void Assembler::fld_s(int index) {
3164 emit_farith(0xD9, 0xC0, index);
3165 }
3167 void Assembler::fld_x(Address adr) {
3168 InstructionMark im(this);
3169 emit_byte(0xDB);
3170 emit_operand32(rbp, adr);
3171 }
3173 void Assembler::fldcw(Address src) {
3174 InstructionMark im(this);
3175 emit_byte(0xd9);
3176 emit_operand32(rbp, src);
3177 }
3179 void Assembler::fldenv(Address src) {
3180 InstructionMark im(this);
3181 emit_byte(0xD9);
3182 emit_operand32(rsp, src);
3183 }
3185 void Assembler::fldlg2() {
3186 emit_byte(0xD9);
3187 emit_byte(0xEC);
3188 }
3190 void Assembler::fldln2() {
3191 emit_byte(0xD9);
3192 emit_byte(0xED);
3193 }
3195 void Assembler::fldz() {
3196 emit_byte(0xD9);
3197 emit_byte(0xEE);
3198 }
3200 void Assembler::flog() {
3201 fldln2();
3202 fxch();
3203 fyl2x();
3204 }
3206 void Assembler::flog10() {
3207 fldlg2();
3208 fxch();
3209 fyl2x();
3210 }
3212 void Assembler::fmul(int i) {
3213 emit_farith(0xD8, 0xC8, i);
3214 }
3216 void Assembler::fmul_d(Address src) {
3217 InstructionMark im(this);
3218 emit_byte(0xDC);
3219 emit_operand32(rcx, src);
3220 }
3222 void Assembler::fmul_s(Address src) {
3223 InstructionMark im(this);
3224 emit_byte(0xD8);
3225 emit_operand32(rcx, src);
3226 }
3228 void Assembler::fmula(int i) {
3229 emit_farith(0xDC, 0xC8, i);
3230 }
3232 void Assembler::fmulp(int i) {
3233 emit_farith(0xDE, 0xC8, i);
3234 }
3236 void Assembler::fnsave(Address dst) {
3237 InstructionMark im(this);
3238 emit_byte(0xDD);
3239 emit_operand32(rsi, dst);
3240 }
3242 void Assembler::fnstcw(Address src) {
3243 InstructionMark im(this);
3244 emit_byte(0x9B);
3245 emit_byte(0xD9);
3246 emit_operand32(rdi, src);
3247 }
3249 void Assembler::fnstsw_ax() {
3250 emit_byte(0xdF);
3251 emit_byte(0xE0);
3252 }
3254 void Assembler::fprem() {
3255 emit_byte(0xD9);
3256 emit_byte(0xF8);
3257 }
3259 void Assembler::fprem1() {
3260 emit_byte(0xD9);
3261 emit_byte(0xF5);
3262 }
3264 void Assembler::frstor(Address src) {
3265 InstructionMark im(this);
3266 emit_byte(0xDD);
3267 emit_operand32(rsp, src);
3268 }
3270 void Assembler::fsin() {
3271 emit_byte(0xD9);
3272 emit_byte(0xFE);
3273 }
3275 void Assembler::fsqrt() {
3276 emit_byte(0xD9);
3277 emit_byte(0xFA);
3278 }
3280 void Assembler::fst_d(Address adr) {
3281 InstructionMark im(this);
3282 emit_byte(0xDD);
3283 emit_operand32(rdx, adr);
3284 }
3286 void Assembler::fst_s(Address adr) {
3287 InstructionMark im(this);
3288 emit_byte(0xD9);
3289 emit_operand32(rdx, adr);
3290 }
3292 void Assembler::fstp_d(Address adr) {
3293 InstructionMark im(this);
3294 emit_byte(0xDD);
3295 emit_operand32(rbx, adr);
3296 }
3298 void Assembler::fstp_d(int index) {
3299 emit_farith(0xDD, 0xD8, index);
3300 }
3302 void Assembler::fstp_s(Address adr) {
3303 InstructionMark im(this);
3304 emit_byte(0xD9);
3305 emit_operand32(rbx, adr);
3306 }
3308 void Assembler::fstp_x(Address adr) {
3309 InstructionMark im(this);
3310 emit_byte(0xDB);
3311 emit_operand32(rdi, adr);
3312 }
3314 void Assembler::fsub(int i) {
3315 emit_farith(0xD8, 0xE0, i);
3316 }
3318 void Assembler::fsub_d(Address src) {
3319 InstructionMark im(this);
3320 emit_byte(0xDC);
3321 emit_operand32(rsp, src);
3322 }
3324 void Assembler::fsub_s(Address src) {
3325 InstructionMark im(this);
3326 emit_byte(0xD8);
3327 emit_operand32(rsp, src);
3328 }
3330 void Assembler::fsuba(int i) {
3331 emit_farith(0xDC, 0xE8, i);
3332 }
3334 void Assembler::fsubp(int i) {
3335 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
3336 }
3338 void Assembler::fsubr(int i) {
3339 emit_farith(0xD8, 0xE8, i);
3340 }
3342 void Assembler::fsubr_d(Address src) {
3343 InstructionMark im(this);
3344 emit_byte(0xDC);
3345 emit_operand32(rbp, src);
3346 }
3348 void Assembler::fsubr_s(Address src) {
3349 InstructionMark im(this);
3350 emit_byte(0xD8);
3351 emit_operand32(rbp, src);
3352 }
3354 void Assembler::fsubra(int i) {
3355 emit_farith(0xDC, 0xE0, i);
3356 }
3358 void Assembler::fsubrp(int i) {
3359 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
3360 }
3362 void Assembler::ftan() {
3363 emit_byte(0xD9);
3364 emit_byte(0xF2);
3365 emit_byte(0xDD);
3366 emit_byte(0xD8);
3367 }
3369 void Assembler::ftst() {
3370 emit_byte(0xD9);
3371 emit_byte(0xE4);
3372 }
3374 void Assembler::fucomi(int i) {
3375 // make sure the instruction is supported (introduced for P6, together with cmov)
3376 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3377 emit_farith(0xDB, 0xE8, i);
3378 }
3380 void Assembler::fucomip(int i) {
3381 // make sure the instruction is supported (introduced for P6, together with cmov)
3382 guarantee(VM_Version::supports_cmov(), "illegal instruction");
3383 emit_farith(0xDF, 0xE8, i);
3384 }
3386 void Assembler::fwait() {
3387 emit_byte(0x9B);
3388 }
3390 void Assembler::fxch(int i) {
3391 emit_farith(0xD9, 0xC8, i);
3392 }
3394 void Assembler::fyl2x() {
3395 emit_byte(0xD9);
3396 emit_byte(0xF1);
3397 }
3400 #ifndef _LP64
3402 void Assembler::incl(Register dst) {
3403 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3404 emit_byte(0x40 | dst->encoding());
3405 }
3407 void Assembler::lea(Register dst, Address src) {
3408 leal(dst, src);
3409 }
3411 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3412 InstructionMark im(this);
3413 emit_byte(0xC7);
3414 emit_operand(rax, dst);
3415 emit_data((int)imm32, rspec, 0);
3416 }
3418 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3419 InstructionMark im(this);
3420 int encode = prefix_and_encode(dst->encoding());
3421 emit_byte(0xB8 | encode);
3422 emit_data((int)imm32, rspec, 0);
3423 }
3425 void Assembler::popa() { // 32bit
3426 emit_byte(0x61);
3427 }
3429 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
3430 InstructionMark im(this);
3431 emit_byte(0x68);
3432 emit_data(imm32, rspec, 0);
3433 }
3435 void Assembler::pusha() { // 32bit
3436 emit_byte(0x60);
3437 }
3439 void Assembler::set_byte_if_not_zero(Register dst) {
3440 emit_byte(0x0F);
3441 emit_byte(0x95);
3442 emit_byte(0xE0 | dst->encoding());
3443 }
3445 void Assembler::shldl(Register dst, Register src) {
3446 emit_byte(0x0F);
3447 emit_byte(0xA5);
3448 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3449 }
3451 void Assembler::shrdl(Register dst, Register src) {
3452 emit_byte(0x0F);
3453 emit_byte(0xAD);
3454 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
3455 }
3457 #else // LP64
3459 void Assembler::set_byte_if_not_zero(Register dst) {
3460 int enc = prefix_and_encode(dst->encoding(), true);
3461 emit_byte(0x0F);
3462 emit_byte(0x95);
3463 emit_byte(0xE0 | enc);
3464 }
3466 // 64bit only pieces of the assembler
3467 // This should only be used by 64bit instructions that can use rip-relative
3468 // it cannot be used by instructions that want an immediate value.
3470 bool Assembler::reachable(AddressLiteral adr) {
3471 int64_t disp;
3472 // None will force a 64bit literal to the code stream. Likely a placeholder
3473 // for something that will be patched later and we need to certain it will
3474 // always be reachable.
3475 if (adr.reloc() == relocInfo::none) {
3476 return false;
3477 }
3478 if (adr.reloc() == relocInfo::internal_word_type) {
3479 // This should be rip relative and easily reachable.
3480 return true;
3481 }
3482 if (adr.reloc() == relocInfo::virtual_call_type ||
3483 adr.reloc() == relocInfo::opt_virtual_call_type ||
3484 adr.reloc() == relocInfo::static_call_type ||
3485 adr.reloc() == relocInfo::static_stub_type ) {
3486 // This should be rip relative within the code cache and easily
3487 // reachable until we get huge code caches. (At which point
3488 // ic code is going to have issues).
3489 return true;
3490 }
3491 if (adr.reloc() != relocInfo::external_word_type &&
3492 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
3493 adr.reloc() != relocInfo::poll_type && // relocs to identify them
3494 adr.reloc() != relocInfo::runtime_call_type ) {
3495 return false;
3496 }
3498 // Stress the correction code
3499 if (ForceUnreachable) {
3500 // Must be runtimecall reloc, see if it is in the codecache
3501 // Flipping stuff in the codecache to be unreachable causes issues
3502 // with things like inline caches where the additional instructions
3503 // are not handled.
3504 if (CodeCache::find_blob(adr._target) == NULL) {
3505 return false;
3506 }
3507 }
3508 // For external_word_type/runtime_call_type if it is reachable from where we
3509 // are now (possibly a temp buffer) and where we might end up
3510 // anywhere in the codeCache then we are always reachable.
3511 // This would have to change if we ever save/restore shared code
3512 // to be more pessimistic.
3513 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
3514 if (!is_simm32(disp)) return false;
3515 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
3516 if (!is_simm32(disp)) return false;
3518 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int));
3520 // Because rip relative is a disp + address_of_next_instruction and we
3521 // don't know the value of address_of_next_instruction we apply a fudge factor
3522 // to make sure we will be ok no matter the size of the instruction we get placed into.
3523 // We don't have to fudge the checks above here because they are already worst case.
3525 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
3526 // + 4 because better safe than sorry.
3527 const int fudge = 12 + 4;
3528 if (disp < 0) {
3529 disp -= fudge;
3530 } else {
3531 disp += fudge;
3532 }
3533 return is_simm32(disp);
3534 }
3536 // Check if the polling page is not reachable from the code cache using rip-relative
3537 // addressing.
3538 bool Assembler::is_polling_page_far() {
3539 intptr_t addr = (intptr_t)os::get_polling_page();
3540 return !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
3541 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
3542 }
3544 void Assembler::emit_data64(jlong data,
3545 relocInfo::relocType rtype,
3546 int format) {
3547 if (rtype == relocInfo::none) {
3548 emit_long64(data);
3549 } else {
3550 emit_data64(data, Relocation::spec_simple(rtype), format);
3551 }
3552 }
3554 void Assembler::emit_data64(jlong data,
3555 RelocationHolder const& rspec,
3556 int format) {
3557 assert(imm_operand == 0, "default format must be immediate in this file");
3558 assert(imm_operand == format, "must be immediate");
3559 assert(inst_mark() != NULL, "must be inside InstructionMark");
3560 // Do not use AbstractAssembler::relocate, which is not intended for
3561 // embedded words. Instead, relocate to the enclosing instruction.
3562 code_section()->relocate(inst_mark(), rspec, format);
3563 #ifdef ASSERT
3564 check_relocation(rspec, format);
3565 #endif
3566 emit_long64(data);
3567 }
3569 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
3570 if (reg_enc >= 8) {
3571 prefix(REX_B);
3572 reg_enc -= 8;
3573 } else if (byteinst && reg_enc >= 4) {
3574 prefix(REX);
3575 }
3576 return reg_enc;
3577 }
3579 int Assembler::prefixq_and_encode(int reg_enc) {
3580 if (reg_enc < 8) {
3581 prefix(REX_W);
3582 } else {
3583 prefix(REX_WB);
3584 reg_enc -= 8;
3585 }
3586 return reg_enc;
3587 }
3589 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
3590 if (dst_enc < 8) {
3591 if (src_enc >= 8) {
3592 prefix(REX_B);
3593 src_enc -= 8;
3594 } else if (byteinst && src_enc >= 4) {
3595 prefix(REX);
3596 }
3597 } else {
3598 if (src_enc < 8) {
3599 prefix(REX_R);
3600 } else {
3601 prefix(REX_RB);
3602 src_enc -= 8;
3603 }
3604 dst_enc -= 8;
3605 }
3606 return dst_enc << 3 | src_enc;
3607 }
3609 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
3610 if (dst_enc < 8) {
3611 if (src_enc < 8) {
3612 prefix(REX_W);
3613 } else {
3614 prefix(REX_WB);
3615 src_enc -= 8;
3616 }
3617 } else {
3618 if (src_enc < 8) {
3619 prefix(REX_WR);
3620 } else {
3621 prefix(REX_WRB);
3622 src_enc -= 8;
3623 }
3624 dst_enc -= 8;
3625 }
3626 return dst_enc << 3 | src_enc;
3627 }
3629 void Assembler::prefix(Register reg) {
3630 if (reg->encoding() >= 8) {
3631 prefix(REX_B);
3632 }
3633 }
3635 void Assembler::prefix(Address adr) {
3636 if (adr.base_needs_rex()) {
3637 if (adr.index_needs_rex()) {
3638 prefix(REX_XB);
3639 } else {
3640 prefix(REX_B);
3641 }
3642 } else {
3643 if (adr.index_needs_rex()) {
3644 prefix(REX_X);
3645 }
3646 }
3647 }
3649 void Assembler::prefixq(Address adr) {
3650 if (adr.base_needs_rex()) {
3651 if (adr.index_needs_rex()) {
3652 prefix(REX_WXB);
3653 } else {
3654 prefix(REX_WB);
3655 }
3656 } else {
3657 if (adr.index_needs_rex()) {
3658 prefix(REX_WX);
3659 } else {
3660 prefix(REX_W);
3661 }
3662 }
3663 }
3666 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
3667 if (reg->encoding() < 8) {
3668 if (adr.base_needs_rex()) {
3669 if (adr.index_needs_rex()) {
3670 prefix(REX_XB);
3671 } else {
3672 prefix(REX_B);
3673 }
3674 } else {
3675 if (adr.index_needs_rex()) {
3676 prefix(REX_X);
3677 } else if (reg->encoding() >= 4 ) {
3678 prefix(REX);
3679 }
3680 }
3681 } else {
3682 if (adr.base_needs_rex()) {
3683 if (adr.index_needs_rex()) {
3684 prefix(REX_RXB);
3685 } else {
3686 prefix(REX_RB);
3687 }
3688 } else {
3689 if (adr.index_needs_rex()) {
3690 prefix(REX_RX);
3691 } else {
3692 prefix(REX_R);
3693 }
3694 }
3695 }
3696 }
3698 void Assembler::prefixq(Address adr, Register src) {
3699 if (src->encoding() < 8) {
3700 if (adr.base_needs_rex()) {
3701 if (adr.index_needs_rex()) {
3702 prefix(REX_WXB);
3703 } else {
3704 prefix(REX_WB);
3705 }
3706 } else {
3707 if (adr.index_needs_rex()) {
3708 prefix(REX_WX);
3709 } else {
3710 prefix(REX_W);
3711 }
3712 }
3713 } else {
3714 if (adr.base_needs_rex()) {
3715 if (adr.index_needs_rex()) {
3716 prefix(REX_WRXB);
3717 } else {
3718 prefix(REX_WRB);
3719 }
3720 } else {
3721 if (adr.index_needs_rex()) {
3722 prefix(REX_WRX);
3723 } else {
3724 prefix(REX_WR);
3725 }
3726 }
3727 }
3728 }
3730 void Assembler::prefix(Address adr, XMMRegister reg) {
3731 if (reg->encoding() < 8) {
3732 if (adr.base_needs_rex()) {
3733 if (adr.index_needs_rex()) {
3734 prefix(REX_XB);
3735 } else {
3736 prefix(REX_B);
3737 }
3738 } else {
3739 if (adr.index_needs_rex()) {
3740 prefix(REX_X);
3741 }
3742 }
3743 } else {
3744 if (adr.base_needs_rex()) {
3745 if (adr.index_needs_rex()) {
3746 prefix(REX_RXB);
3747 } else {
3748 prefix(REX_RB);
3749 }
3750 } else {
3751 if (adr.index_needs_rex()) {
3752 prefix(REX_RX);
3753 } else {
3754 prefix(REX_R);
3755 }
3756 }
3757 }
3758 }
3760 void Assembler::adcq(Register dst, int32_t imm32) {
3761 (void) prefixq_and_encode(dst->encoding());
3762 emit_arith(0x81, 0xD0, dst, imm32);
3763 }
3765 void Assembler::adcq(Register dst, Address src) {
3766 InstructionMark im(this);
3767 prefixq(src, dst);
3768 emit_byte(0x13);
3769 emit_operand(dst, src);
3770 }
3772 void Assembler::adcq(Register dst, Register src) {
3773 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3774 emit_arith(0x13, 0xC0, dst, src);
3775 }
3777 void Assembler::addq(Address dst, int32_t imm32) {
3778 InstructionMark im(this);
3779 prefixq(dst);
3780 emit_arith_operand(0x81, rax, dst,imm32);
3781 }
3783 void Assembler::addq(Address dst, Register src) {
3784 InstructionMark im(this);
3785 prefixq(dst, src);
3786 emit_byte(0x01);
3787 emit_operand(src, dst);
3788 }
3790 void Assembler::addq(Register dst, int32_t imm32) {
3791 (void) prefixq_and_encode(dst->encoding());
3792 emit_arith(0x81, 0xC0, dst, imm32);
3793 }
3795 void Assembler::addq(Register dst, Address src) {
3796 InstructionMark im(this);
3797 prefixq(src, dst);
3798 emit_byte(0x03);
3799 emit_operand(dst, src);
3800 }
3802 void Assembler::addq(Register dst, Register src) {
3803 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3804 emit_arith(0x03, 0xC0, dst, src);
3805 }
3807 void Assembler::andq(Address dst, int32_t imm32) {
3808 InstructionMark im(this);
3809 prefixq(dst);
3810 emit_byte(0x81);
3811 emit_operand(rsp, dst, 4);
3812 emit_long(imm32);
3813 }
3815 void Assembler::andq(Register dst, int32_t imm32) {
3816 (void) prefixq_and_encode(dst->encoding());
3817 emit_arith(0x81, 0xE0, dst, imm32);
3818 }
3820 void Assembler::andq(Register dst, Address src) {
3821 InstructionMark im(this);
3822 prefixq(src, dst);
3823 emit_byte(0x23);
3824 emit_operand(dst, src);
3825 }
3827 void Assembler::andq(Register dst, Register src) {
3828 (int) prefixq_and_encode(dst->encoding(), src->encoding());
3829 emit_arith(0x23, 0xC0, dst, src);
3830 }
3832 void Assembler::bsfq(Register dst, Register src) {
3833 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3834 emit_byte(0x0F);
3835 emit_byte(0xBC);
3836 emit_byte(0xC0 | encode);
3837 }
3839 void Assembler::bsrq(Register dst, Register src) {
3840 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
3841 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3842 emit_byte(0x0F);
3843 emit_byte(0xBD);
3844 emit_byte(0xC0 | encode);
3845 }
3847 void Assembler::bswapq(Register reg) {
3848 int encode = prefixq_and_encode(reg->encoding());
3849 emit_byte(0x0F);
3850 emit_byte(0xC8 | encode);
3851 }
3853 void Assembler::cdqq() {
3854 prefix(REX_W);
3855 emit_byte(0x99);
3856 }
3858 void Assembler::clflush(Address adr) {
3859 prefix(adr);
3860 emit_byte(0x0F);
3861 emit_byte(0xAE);
3862 emit_operand(rdi, adr);
3863 }
3865 void Assembler::cmovq(Condition cc, Register dst, Register src) {
3866 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3867 emit_byte(0x0F);
3868 emit_byte(0x40 | cc);
3869 emit_byte(0xC0 | encode);
3870 }
3872 void Assembler::cmovq(Condition cc, Register dst, Address src) {
3873 InstructionMark im(this);
3874 prefixq(src, dst);
3875 emit_byte(0x0F);
3876 emit_byte(0x40 | cc);
3877 emit_operand(dst, src);
3878 }
3880 void Assembler::cmpq(Address dst, int32_t imm32) {
3881 InstructionMark im(this);
3882 prefixq(dst);
3883 emit_byte(0x81);
3884 emit_operand(rdi, dst, 4);
3885 emit_long(imm32);
3886 }
3888 void Assembler::cmpq(Register dst, int32_t imm32) {
3889 (void) prefixq_and_encode(dst->encoding());
3890 emit_arith(0x81, 0xF8, dst, imm32);
3891 }
3893 void Assembler::cmpq(Address dst, Register src) {
3894 InstructionMark im(this);
3895 prefixq(dst, src);
3896 emit_byte(0x3B);
3897 emit_operand(src, dst);
3898 }
3900 void Assembler::cmpq(Register dst, Register src) {
3901 (void) prefixq_and_encode(dst->encoding(), src->encoding());
3902 emit_arith(0x3B, 0xC0, dst, src);
3903 }
3905 void Assembler::cmpq(Register dst, Address src) {
3906 InstructionMark im(this);
3907 prefixq(src, dst);
3908 emit_byte(0x3B);
3909 emit_operand(dst, src);
3910 }
3912 void Assembler::cmpxchgq(Register reg, Address adr) {
3913 InstructionMark im(this);
3914 prefixq(adr, reg);
3915 emit_byte(0x0F);
3916 emit_byte(0xB1);
3917 emit_operand(reg, adr);
3918 }
3920 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
3921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3922 emit_byte(0xF2);
3923 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3924 emit_byte(0x0F);
3925 emit_byte(0x2A);
3926 emit_byte(0xC0 | encode);
3927 }
3929 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
3930 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3931 emit_byte(0xF3);
3932 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3933 emit_byte(0x0F);
3934 emit_byte(0x2A);
3935 emit_byte(0xC0 | encode);
3936 }
3938 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
3939 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3940 emit_byte(0xF2);
3941 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3942 emit_byte(0x0F);
3943 emit_byte(0x2C);
3944 emit_byte(0xC0 | encode);
3945 }
3947 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
3948 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3949 emit_byte(0xF3);
3950 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3951 emit_byte(0x0F);
3952 emit_byte(0x2C);
3953 emit_byte(0xC0 | encode);
3954 }
3956 void Assembler::decl(Register dst) {
3957 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3958 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
3959 int encode = prefix_and_encode(dst->encoding());
3960 emit_byte(0xFF);
3961 emit_byte(0xC8 | encode);
3962 }
3964 void Assembler::decq(Register dst) {
3965 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3966 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
3967 int encode = prefixq_and_encode(dst->encoding());
3968 emit_byte(0xFF);
3969 emit_byte(0xC8 | encode);
3970 }
3972 void Assembler::decq(Address dst) {
3973 // Don't use it directly. Use MacroAssembler::decrementq() instead.
3974 InstructionMark im(this);
3975 prefixq(dst);
3976 emit_byte(0xFF);
3977 emit_operand(rcx, dst);
3978 }
3980 void Assembler::fxrstor(Address src) {
3981 prefixq(src);
3982 emit_byte(0x0F);
3983 emit_byte(0xAE);
3984 emit_operand(as_Register(1), src);
3985 }
3987 void Assembler::fxsave(Address dst) {
3988 prefixq(dst);
3989 emit_byte(0x0F);
3990 emit_byte(0xAE);
3991 emit_operand(as_Register(0), dst);
3992 }
3994 void Assembler::idivq(Register src) {
3995 int encode = prefixq_and_encode(src->encoding());
3996 emit_byte(0xF7);
3997 emit_byte(0xF8 | encode);
3998 }
4000 void Assembler::imulq(Register dst, Register src) {
4001 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4002 emit_byte(0x0F);
4003 emit_byte(0xAF);
4004 emit_byte(0xC0 | encode);
4005 }
4007 void Assembler::imulq(Register dst, Register src, int value) {
4008 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4009 if (is8bit(value)) {
4010 emit_byte(0x6B);
4011 emit_byte(0xC0 | encode);
4012 emit_byte(value & 0xFF);
4013 } else {
4014 emit_byte(0x69);
4015 emit_byte(0xC0 | encode);
4016 emit_long(value);
4017 }
4018 }
4020 void Assembler::incl(Register dst) {
4021 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4022 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4023 int encode = prefix_and_encode(dst->encoding());
4024 emit_byte(0xFF);
4025 emit_byte(0xC0 | encode);
4026 }
4028 void Assembler::incq(Register dst) {
4029 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4030 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4031 int encode = prefixq_and_encode(dst->encoding());
4032 emit_byte(0xFF);
4033 emit_byte(0xC0 | encode);
4034 }
4036 void Assembler::incq(Address dst) {
4037 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4038 InstructionMark im(this);
4039 prefixq(dst);
4040 emit_byte(0xFF);
4041 emit_operand(rax, dst);
4042 }
4044 void Assembler::lea(Register dst, Address src) {
4045 leaq(dst, src);
4046 }
4048 void Assembler::leaq(Register dst, Address src) {
4049 InstructionMark im(this);
4050 prefixq(src, dst);
4051 emit_byte(0x8D);
4052 emit_operand(dst, src);
4053 }
4055 void Assembler::mov64(Register dst, int64_t imm64) {
4056 InstructionMark im(this);
4057 int encode = prefixq_and_encode(dst->encoding());
4058 emit_byte(0xB8 | encode);
4059 emit_long64(imm64);
4060 }
4062 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
4063 InstructionMark im(this);
4064 int encode = prefixq_and_encode(dst->encoding());
4065 emit_byte(0xB8 | encode);
4066 emit_data64(imm64, rspec);
4067 }
4069 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4070 InstructionMark im(this);
4071 int encode = prefix_and_encode(dst->encoding());
4072 emit_byte(0xB8 | encode);
4073 emit_data((int)imm32, rspec, narrow_oop_operand);
4074 }
4076 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4077 InstructionMark im(this);
4078 prefix(dst);
4079 emit_byte(0xC7);
4080 emit_operand(rax, dst, 4);
4081 emit_data((int)imm32, rspec, narrow_oop_operand);
4082 }
4084 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
4085 InstructionMark im(this);
4086 int encode = prefix_and_encode(src1->encoding());
4087 emit_byte(0x81);
4088 emit_byte(0xF8 | encode);
4089 emit_data((int)imm32, rspec, narrow_oop_operand);
4090 }
4092 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
4093 InstructionMark im(this);
4094 prefix(src1);
4095 emit_byte(0x81);
4096 emit_operand(rax, src1, 4);
4097 emit_data((int)imm32, rspec, narrow_oop_operand);
4098 }
4100 void Assembler::lzcntq(Register dst, Register src) {
4101 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
4102 emit_byte(0xF3);
4103 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4104 emit_byte(0x0F);
4105 emit_byte(0xBD);
4106 emit_byte(0xC0 | encode);
4107 }
4109 void Assembler::movdq(XMMRegister dst, Register src) {
4110 // table D-1 says MMX/SSE2
4111 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4112 emit_byte(0x66);
4113 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4114 emit_byte(0x0F);
4115 emit_byte(0x6E);
4116 emit_byte(0xC0 | encode);
4117 }
4119 void Assembler::movdq(Register dst, XMMRegister src) {
4120 // table D-1 says MMX/SSE2
4121 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), ""));
4122 emit_byte(0x66);
4123 // swap src/dst to get correct prefix
4124 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
4125 emit_byte(0x0F);
4126 emit_byte(0x7E);
4127 emit_byte(0xC0 | encode);
4128 }
4130 void Assembler::movq(Register dst, Register src) {
4131 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4132 emit_byte(0x8B);
4133 emit_byte(0xC0 | encode);
4134 }
4136 void Assembler::movq(Register dst, Address src) {
4137 InstructionMark im(this);
4138 prefixq(src, dst);
4139 emit_byte(0x8B);
4140 emit_operand(dst, src);
4141 }
4143 void Assembler::movq(Address dst, Register src) {
4144 InstructionMark im(this);
4145 prefixq(dst, src);
4146 emit_byte(0x89);
4147 emit_operand(src, dst);
4148 }
4150 void Assembler::movsbq(Register dst, Address src) {
4151 InstructionMark im(this);
4152 prefixq(src, dst);
4153 emit_byte(0x0F);
4154 emit_byte(0xBE);
4155 emit_operand(dst, src);
4156 }
4158 void Assembler::movsbq(Register dst, Register src) {
4159 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4160 emit_byte(0x0F);
4161 emit_byte(0xBE);
4162 emit_byte(0xC0 | encode);
4163 }
4165 void Assembler::movslq(Register dst, int32_t imm32) {
4166 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
4167 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
4168 // as a result we shouldn't use until tested at runtime...
4169 ShouldNotReachHere();
4170 InstructionMark im(this);
4171 int encode = prefixq_and_encode(dst->encoding());
4172 emit_byte(0xC7 | encode);
4173 emit_long(imm32);
4174 }
4176 void Assembler::movslq(Address dst, int32_t imm32) {
4177 assert(is_simm32(imm32), "lost bits");
4178 InstructionMark im(this);
4179 prefixq(dst);
4180 emit_byte(0xC7);
4181 emit_operand(rax, dst, 4);
4182 emit_long(imm32);
4183 }
4185 void Assembler::movslq(Register dst, Address src) {
4186 InstructionMark im(this);
4187 prefixq(src, dst);
4188 emit_byte(0x63);
4189 emit_operand(dst, src);
4190 }
4192 void Assembler::movslq(Register dst, Register src) {
4193 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4194 emit_byte(0x63);
4195 emit_byte(0xC0 | encode);
4196 }
4198 void Assembler::movswq(Register dst, Address src) {
4199 InstructionMark im(this);
4200 prefixq(src, dst);
4201 emit_byte(0x0F);
4202 emit_byte(0xBF);
4203 emit_operand(dst, src);
4204 }
4206 void Assembler::movswq(Register dst, Register src) {
4207 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4208 emit_byte(0x0F);
4209 emit_byte(0xBF);
4210 emit_byte(0xC0 | encode);
4211 }
4213 void Assembler::movzbq(Register dst, Address src) {
4214 InstructionMark im(this);
4215 prefixq(src, dst);
4216 emit_byte(0x0F);
4217 emit_byte(0xB6);
4218 emit_operand(dst, src);
4219 }
4221 void Assembler::movzbq(Register dst, Register src) {
4222 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4223 emit_byte(0x0F);
4224 emit_byte(0xB6);
4225 emit_byte(0xC0 | encode);
4226 }
4228 void Assembler::movzwq(Register dst, Address src) {
4229 InstructionMark im(this);
4230 prefixq(src, dst);
4231 emit_byte(0x0F);
4232 emit_byte(0xB7);
4233 emit_operand(dst, src);
4234 }
4236 void Assembler::movzwq(Register dst, Register src) {
4237 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4238 emit_byte(0x0F);
4239 emit_byte(0xB7);
4240 emit_byte(0xC0 | encode);
4241 }
4243 void Assembler::negq(Register dst) {
4244 int encode = prefixq_and_encode(dst->encoding());
4245 emit_byte(0xF7);
4246 emit_byte(0xD8 | encode);
4247 }
4249 void Assembler::notq(Register dst) {
4250 int encode = prefixq_and_encode(dst->encoding());
4251 emit_byte(0xF7);
4252 emit_byte(0xD0 | encode);
4253 }
4255 void Assembler::orq(Address dst, int32_t imm32) {
4256 InstructionMark im(this);
4257 prefixq(dst);
4258 emit_byte(0x81);
4259 emit_operand(rcx, dst, 4);
4260 emit_long(imm32);
4261 }
4263 void Assembler::orq(Register dst, int32_t imm32) {
4264 (void) prefixq_and_encode(dst->encoding());
4265 emit_arith(0x81, 0xC8, dst, imm32);
4266 }
4268 void Assembler::orq(Register dst, Address src) {
4269 InstructionMark im(this);
4270 prefixq(src, dst);
4271 emit_byte(0x0B);
4272 emit_operand(dst, src);
4273 }
4275 void Assembler::orq(Register dst, Register src) {
4276 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4277 emit_arith(0x0B, 0xC0, dst, src);
4278 }
4280 void Assembler::popa() { // 64bit
4281 movq(r15, Address(rsp, 0));
4282 movq(r14, Address(rsp, wordSize));
4283 movq(r13, Address(rsp, 2 * wordSize));
4284 movq(r12, Address(rsp, 3 * wordSize));
4285 movq(r11, Address(rsp, 4 * wordSize));
4286 movq(r10, Address(rsp, 5 * wordSize));
4287 movq(r9, Address(rsp, 6 * wordSize));
4288 movq(r8, Address(rsp, 7 * wordSize));
4289 movq(rdi, Address(rsp, 8 * wordSize));
4290 movq(rsi, Address(rsp, 9 * wordSize));
4291 movq(rbp, Address(rsp, 10 * wordSize));
4292 // skip rsp
4293 movq(rbx, Address(rsp, 12 * wordSize));
4294 movq(rdx, Address(rsp, 13 * wordSize));
4295 movq(rcx, Address(rsp, 14 * wordSize));
4296 movq(rax, Address(rsp, 15 * wordSize));
4298 addq(rsp, 16 * wordSize);
4299 }
4301 void Assembler::popcntq(Register dst, Address src) {
4302 assert(VM_Version::supports_popcnt(), "must support");
4303 InstructionMark im(this);
4304 emit_byte(0xF3);
4305 prefixq(src, dst);
4306 emit_byte(0x0F);
4307 emit_byte(0xB8);
4308 emit_operand(dst, src);
4309 }
4311 void Assembler::popcntq(Register dst, Register src) {
4312 assert(VM_Version::supports_popcnt(), "must support");
4313 emit_byte(0xF3);
4314 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4315 emit_byte(0x0F);
4316 emit_byte(0xB8);
4317 emit_byte(0xC0 | encode);
4318 }
4320 void Assembler::popq(Address dst) {
4321 InstructionMark im(this);
4322 prefixq(dst);
4323 emit_byte(0x8F);
4324 emit_operand(rax, dst);
4325 }
4327 void Assembler::pusha() { // 64bit
4328 // we have to store original rsp. ABI says that 128 bytes
4329 // below rsp are local scratch.
4330 movq(Address(rsp, -5 * wordSize), rsp);
4332 subq(rsp, 16 * wordSize);
4334 movq(Address(rsp, 15 * wordSize), rax);
4335 movq(Address(rsp, 14 * wordSize), rcx);
4336 movq(Address(rsp, 13 * wordSize), rdx);
4337 movq(Address(rsp, 12 * wordSize), rbx);
4338 // skip rsp
4339 movq(Address(rsp, 10 * wordSize), rbp);
4340 movq(Address(rsp, 9 * wordSize), rsi);
4341 movq(Address(rsp, 8 * wordSize), rdi);
4342 movq(Address(rsp, 7 * wordSize), r8);
4343 movq(Address(rsp, 6 * wordSize), r9);
4344 movq(Address(rsp, 5 * wordSize), r10);
4345 movq(Address(rsp, 4 * wordSize), r11);
4346 movq(Address(rsp, 3 * wordSize), r12);
4347 movq(Address(rsp, 2 * wordSize), r13);
4348 movq(Address(rsp, wordSize), r14);
4349 movq(Address(rsp, 0), r15);
4350 }
4352 void Assembler::pushq(Address src) {
4353 InstructionMark im(this);
4354 prefixq(src);
4355 emit_byte(0xFF);
4356 emit_operand(rsi, src);
4357 }
4359 void Assembler::rclq(Register dst, int imm8) {
4360 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4361 int encode = prefixq_and_encode(dst->encoding());
4362 if (imm8 == 1) {
4363 emit_byte(0xD1);
4364 emit_byte(0xD0 | encode);
4365 } else {
4366 emit_byte(0xC1);
4367 emit_byte(0xD0 | encode);
4368 emit_byte(imm8);
4369 }
4370 }
4371 void Assembler::sarq(Register dst, int imm8) {
4372 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4373 int encode = prefixq_and_encode(dst->encoding());
4374 if (imm8 == 1) {
4375 emit_byte(0xD1);
4376 emit_byte(0xF8 | encode);
4377 } else {
4378 emit_byte(0xC1);
4379 emit_byte(0xF8 | encode);
4380 emit_byte(imm8);
4381 }
4382 }
4384 void Assembler::sarq(Register dst) {
4385 int encode = prefixq_and_encode(dst->encoding());
4386 emit_byte(0xD3);
4387 emit_byte(0xF8 | encode);
4388 }
4390 void Assembler::sbbq(Address dst, int32_t imm32) {
4391 InstructionMark im(this);
4392 prefixq(dst);
4393 emit_arith_operand(0x81, rbx, dst, imm32);
4394 }
4396 void Assembler::sbbq(Register dst, int32_t imm32) {
4397 (void) prefixq_and_encode(dst->encoding());
4398 emit_arith(0x81, 0xD8, dst, imm32);
4399 }
4401 void Assembler::sbbq(Register dst, Address src) {
4402 InstructionMark im(this);
4403 prefixq(src, dst);
4404 emit_byte(0x1B);
4405 emit_operand(dst, src);
4406 }
4408 void Assembler::sbbq(Register dst, Register src) {
4409 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4410 emit_arith(0x1B, 0xC0, dst, src);
4411 }
4413 void Assembler::shlq(Register dst, int imm8) {
4414 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4415 int encode = prefixq_and_encode(dst->encoding());
4416 if (imm8 == 1) {
4417 emit_byte(0xD1);
4418 emit_byte(0xE0 | encode);
4419 } else {
4420 emit_byte(0xC1);
4421 emit_byte(0xE0 | encode);
4422 emit_byte(imm8);
4423 }
4424 }
4426 void Assembler::shlq(Register dst) {
4427 int encode = prefixq_and_encode(dst->encoding());
4428 emit_byte(0xD3);
4429 emit_byte(0xE0 | encode);
4430 }
4432 void Assembler::shrq(Register dst, int imm8) {
4433 assert(isShiftCount(imm8 >> 1), "illegal shift count");
4434 int encode = prefixq_and_encode(dst->encoding());
4435 emit_byte(0xC1);
4436 emit_byte(0xE8 | encode);
4437 emit_byte(imm8);
4438 }
4440 void Assembler::shrq(Register dst) {
4441 int encode = prefixq_and_encode(dst->encoding());
4442 emit_byte(0xD3);
4443 emit_byte(0xE8 | encode);
4444 }
4446 void Assembler::subq(Address dst, int32_t imm32) {
4447 InstructionMark im(this);
4448 prefixq(dst);
4449 emit_arith_operand(0x81, rbp, dst, imm32);
4450 }
4452 void Assembler::subq(Address dst, Register src) {
4453 InstructionMark im(this);
4454 prefixq(dst, src);
4455 emit_byte(0x29);
4456 emit_operand(src, dst);
4457 }
4459 void Assembler::subq(Register dst, int32_t imm32) {
4460 (void) prefixq_and_encode(dst->encoding());
4461 emit_arith(0x81, 0xE8, dst, imm32);
4462 }
4464 void Assembler::subq(Register dst, Address src) {
4465 InstructionMark im(this);
4466 prefixq(src, dst);
4467 emit_byte(0x2B);
4468 emit_operand(dst, src);
4469 }
4471 void Assembler::subq(Register dst, Register src) {
4472 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4473 emit_arith(0x2B, 0xC0, dst, src);
4474 }
4476 void Assembler::testq(Register dst, int32_t imm32) {
4477 // not using emit_arith because test
4478 // doesn't support sign-extension of
4479 // 8bit operands
4480 int encode = dst->encoding();
4481 if (encode == 0) {
4482 prefix(REX_W);
4483 emit_byte(0xA9);
4484 } else {
4485 encode = prefixq_and_encode(encode);
4486 emit_byte(0xF7);
4487 emit_byte(0xC0 | encode);
4488 }
4489 emit_long(imm32);
4490 }
4492 void Assembler::testq(Register dst, Register src) {
4493 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4494 emit_arith(0x85, 0xC0, dst, src);
4495 }
4497 void Assembler::xaddq(Address dst, Register src) {
4498 InstructionMark im(this);
4499 prefixq(dst, src);
4500 emit_byte(0x0F);
4501 emit_byte(0xC1);
4502 emit_operand(src, dst);
4503 }
4505 void Assembler::xchgq(Register dst, Address src) {
4506 InstructionMark im(this);
4507 prefixq(src, dst);
4508 emit_byte(0x87);
4509 emit_operand(dst, src);
4510 }
4512 void Assembler::xchgq(Register dst, Register src) {
4513 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4514 emit_byte(0x87);
4515 emit_byte(0xc0 | encode);
4516 }
4518 void Assembler::xorq(Register dst, Register src) {
4519 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4520 emit_arith(0x33, 0xC0, dst, src);
4521 }
4523 void Assembler::xorq(Register dst, Address src) {
4524 InstructionMark im(this);
4525 prefixq(src, dst);
4526 emit_byte(0x33);
4527 emit_operand(dst, src);
4528 }
4530 #endif // !LP64
4532 static Assembler::Condition reverse[] = {
4533 Assembler::noOverflow /* overflow = 0x0 */ ,
4534 Assembler::overflow /* noOverflow = 0x1 */ ,
4535 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
4536 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
4537 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
4538 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
4539 Assembler::above /* belowEqual = 0x6 */ ,
4540 Assembler::belowEqual /* above = 0x7 */ ,
4541 Assembler::positive /* negative = 0x8 */ ,
4542 Assembler::negative /* positive = 0x9 */ ,
4543 Assembler::noParity /* parity = 0xa */ ,
4544 Assembler::parity /* noParity = 0xb */ ,
4545 Assembler::greaterEqual /* less = 0xc */ ,
4546 Assembler::less /* greaterEqual = 0xd */ ,
4547 Assembler::greater /* lessEqual = 0xe */ ,
4548 Assembler::lessEqual /* greater = 0xf, */
4550 };
4553 // Implementation of MacroAssembler
4555 // First all the versions that have distinct versions depending on 32/64 bit
4556 // Unless the difference is trivial (1 line or so).
4558 #ifndef _LP64
4560 // 32bit versions
4562 Address MacroAssembler::as_Address(AddressLiteral adr) {
4563 return Address(adr.target(), adr.rspec());
4564 }
4566 Address MacroAssembler::as_Address(ArrayAddress adr) {
4567 return Address::make_array(adr);
4568 }
4570 int MacroAssembler::biased_locking_enter(Register lock_reg,
4571 Register obj_reg,
4572 Register swap_reg,
4573 Register tmp_reg,
4574 bool swap_reg_contains_mark,
4575 Label& done,
4576 Label* slow_case,
4577 BiasedLockingCounters* counters) {
4578 assert(UseBiasedLocking, "why call this otherwise?");
4579 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4580 assert_different_registers(lock_reg, obj_reg, swap_reg);
4582 if (PrintBiasedLockingStatistics && counters == NULL)
4583 counters = BiasedLocking::counters();
4585 bool need_tmp_reg = false;
4586 if (tmp_reg == noreg) {
4587 need_tmp_reg = true;
4588 tmp_reg = lock_reg;
4589 } else {
4590 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4591 }
4592 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4593 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4594 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4595 Address saved_mark_addr(lock_reg, 0);
4597 // Biased locking
4598 // See whether the lock is currently biased toward our thread and
4599 // whether the epoch is still valid
4600 // Note that the runtime guarantees sufficient alignment of JavaThread
4601 // pointers to allow age to be placed into low bits
4602 // First check to see whether biasing is even enabled for this object
4603 Label cas_label;
4604 int null_check_offset = -1;
4605 if (!swap_reg_contains_mark) {
4606 null_check_offset = offset();
4607 movl(swap_reg, mark_addr);
4608 }
4609 if (need_tmp_reg) {
4610 push(tmp_reg);
4611 }
4612 movl(tmp_reg, swap_reg);
4613 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4614 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4615 if (need_tmp_reg) {
4616 pop(tmp_reg);
4617 }
4618 jcc(Assembler::notEqual, cas_label);
4619 // The bias pattern is present in the object's header. Need to check
4620 // whether the bias owner and the epoch are both still current.
4621 // Note that because there is no current thread register on x86 we
4622 // need to store off the mark word we read out of the object to
4623 // avoid reloading it and needing to recheck invariants below. This
4624 // store is unfortunate but it makes the overall code shorter and
4625 // simpler.
4626 movl(saved_mark_addr, swap_reg);
4627 if (need_tmp_reg) {
4628 push(tmp_reg);
4629 }
4630 get_thread(tmp_reg);
4631 xorl(swap_reg, tmp_reg);
4632 if (swap_reg_contains_mark) {
4633 null_check_offset = offset();
4634 }
4635 movl(tmp_reg, klass_addr);
4636 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4637 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4638 if (need_tmp_reg) {
4639 pop(tmp_reg);
4640 }
4641 if (counters != NULL) {
4642 cond_inc32(Assembler::zero,
4643 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4644 }
4645 jcc(Assembler::equal, done);
4647 Label try_revoke_bias;
4648 Label try_rebias;
4650 // At this point we know that the header has the bias pattern and
4651 // that we are not the bias owner in the current epoch. We need to
4652 // figure out more details about the state of the header in order to
4653 // know what operations can be legally performed on the object's
4654 // header.
4656 // If the low three bits in the xor result aren't clear, that means
4657 // the prototype header is no longer biased and we have to revoke
4658 // the bias on this object.
4659 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4660 jcc(Assembler::notZero, try_revoke_bias);
4662 // Biasing is still enabled for this data type. See whether the
4663 // epoch of the current bias is still valid, meaning that the epoch
4664 // bits of the mark word are equal to the epoch bits of the
4665 // prototype header. (Note that the prototype header's epoch bits
4666 // only change at a safepoint.) If not, attempt to rebias the object
4667 // toward the current thread. Note that we must be absolutely sure
4668 // that the current epoch is invalid in order to do this because
4669 // otherwise the manipulations it performs on the mark word are
4670 // illegal.
4671 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4672 jcc(Assembler::notZero, try_rebias);
4674 // The epoch of the current bias is still valid but we know nothing
4675 // about the owner; it might be set or it might be clear. Try to
4676 // acquire the bias of the object using an atomic operation. If this
4677 // fails we will go in to the runtime to revoke the object's bias.
4678 // Note that we first construct the presumed unbiased header so we
4679 // don't accidentally blow away another thread's valid bias.
4680 movl(swap_reg, saved_mark_addr);
4681 andl(swap_reg,
4682 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
4683 if (need_tmp_reg) {
4684 push(tmp_reg);
4685 }
4686 get_thread(tmp_reg);
4687 orl(tmp_reg, swap_reg);
4688 if (os::is_MP()) {
4689 lock();
4690 }
4691 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4692 if (need_tmp_reg) {
4693 pop(tmp_reg);
4694 }
4695 // If the biasing toward our thread failed, this means that
4696 // another thread succeeded in biasing it toward itself and we
4697 // need to revoke that bias. The revocation will occur in the
4698 // interpreter runtime in the slow case.
4699 if (counters != NULL) {
4700 cond_inc32(Assembler::zero,
4701 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
4702 }
4703 if (slow_case != NULL) {
4704 jcc(Assembler::notZero, *slow_case);
4705 }
4706 jmp(done);
4708 bind(try_rebias);
4709 // At this point we know the epoch has expired, meaning that the
4710 // current "bias owner", if any, is actually invalid. Under these
4711 // circumstances _only_, we are allowed to use the current header's
4712 // value as the comparison value when doing the cas to acquire the
4713 // bias in the current epoch. In other words, we allow transfer of
4714 // the bias from one thread to another directly in this situation.
4715 //
4716 // FIXME: due to a lack of registers we currently blow away the age
4717 // bits in this situation. Should attempt to preserve them.
4718 if (need_tmp_reg) {
4719 push(tmp_reg);
4720 }
4721 get_thread(tmp_reg);
4722 movl(swap_reg, klass_addr);
4723 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4724 movl(swap_reg, saved_mark_addr);
4725 if (os::is_MP()) {
4726 lock();
4727 }
4728 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4729 if (need_tmp_reg) {
4730 pop(tmp_reg);
4731 }
4732 // If the biasing toward our thread failed, then another thread
4733 // succeeded in biasing it toward itself and we need to revoke that
4734 // bias. The revocation will occur in the runtime in the slow case.
4735 if (counters != NULL) {
4736 cond_inc32(Assembler::zero,
4737 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
4738 }
4739 if (slow_case != NULL) {
4740 jcc(Assembler::notZero, *slow_case);
4741 }
4742 jmp(done);
4744 bind(try_revoke_bias);
4745 // The prototype mark in the klass doesn't have the bias bit set any
4746 // more, indicating that objects of this data type are not supposed
4747 // to be biased any more. We are going to try to reset the mark of
4748 // this object to the prototype value and fall through to the
4749 // CAS-based locking scheme. Note that if our CAS fails, it means
4750 // that another thread raced us for the privilege of revoking the
4751 // bias of this particular object, so it's okay to continue in the
4752 // normal locking code.
4753 //
4754 // FIXME: due to a lack of registers we currently blow away the age
4755 // bits in this situation. Should attempt to preserve them.
4756 movl(swap_reg, saved_mark_addr);
4757 if (need_tmp_reg) {
4758 push(tmp_reg);
4759 }
4760 movl(tmp_reg, klass_addr);
4761 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4762 if (os::is_MP()) {
4763 lock();
4764 }
4765 cmpxchgptr(tmp_reg, Address(obj_reg, 0));
4766 if (need_tmp_reg) {
4767 pop(tmp_reg);
4768 }
4769 // Fall through to the normal CAS-based lock, because no matter what
4770 // the result of the above CAS, some thread must have succeeded in
4771 // removing the bias bit from the object's header.
4772 if (counters != NULL) {
4773 cond_inc32(Assembler::zero,
4774 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
4775 }
4777 bind(cas_label);
4779 return null_check_offset;
4780 }
4781 void MacroAssembler::call_VM_leaf_base(address entry_point,
4782 int number_of_arguments) {
4783 call(RuntimeAddress(entry_point));
4784 increment(rsp, number_of_arguments * wordSize);
4785 }
4787 void MacroAssembler::cmpoop(Address src1, jobject obj) {
4788 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4789 }
4791 void MacroAssembler::cmpoop(Register src1, jobject obj) {
4792 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
4793 }
4795 void MacroAssembler::extend_sign(Register hi, Register lo) {
4796 // According to Intel Doc. AP-526, "Integer Divide", p.18.
4797 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
4798 cdql();
4799 } else {
4800 movl(hi, lo);
4801 sarl(hi, 31);
4802 }
4803 }
4805 void MacroAssembler::fat_nop() {
4806 // A 5 byte nop that is safe for patching (see patch_verified_entry)
4807 emit_byte(0x26); // es:
4808 emit_byte(0x2e); // cs:
4809 emit_byte(0x64); // fs:
4810 emit_byte(0x65); // gs:
4811 emit_byte(0x90);
4812 }
4814 void MacroAssembler::jC2(Register tmp, Label& L) {
4815 // set parity bit if FPU flag C2 is set (via rax)
4816 save_rax(tmp);
4817 fwait(); fnstsw_ax();
4818 sahf();
4819 restore_rax(tmp);
4820 // branch
4821 jcc(Assembler::parity, L);
4822 }
4824 void MacroAssembler::jnC2(Register tmp, Label& L) {
4825 // set parity bit if FPU flag C2 is set (via rax)
4826 save_rax(tmp);
4827 fwait(); fnstsw_ax();
4828 sahf();
4829 restore_rax(tmp);
4830 // branch
4831 jcc(Assembler::noParity, L);
4832 }
4834 // 32bit can do a case table jump in one instruction but we no longer allow the base
4835 // to be installed in the Address class
4836 void MacroAssembler::jump(ArrayAddress entry) {
4837 jmp(as_Address(entry));
4838 }
4840 // Note: y_lo will be destroyed
4841 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
4842 // Long compare for Java (semantics as described in JVM spec.)
4843 Label high, low, done;
4845 cmpl(x_hi, y_hi);
4846 jcc(Assembler::less, low);
4847 jcc(Assembler::greater, high);
4848 // x_hi is the return register
4849 xorl(x_hi, x_hi);
4850 cmpl(x_lo, y_lo);
4851 jcc(Assembler::below, low);
4852 jcc(Assembler::equal, done);
4854 bind(high);
4855 xorl(x_hi, x_hi);
4856 increment(x_hi);
4857 jmp(done);
4859 bind(low);
4860 xorl(x_hi, x_hi);
4861 decrementl(x_hi);
4863 bind(done);
4864 }
4866 void MacroAssembler::lea(Register dst, AddressLiteral src) {
4867 mov_literal32(dst, (int32_t)src.target(), src.rspec());
4868 }
4870 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
4871 // leal(dst, as_Address(adr));
4872 // see note in movl as to why we must use a move
4873 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
4874 }
4876 void MacroAssembler::leave() {
4877 mov(rsp, rbp);
4878 pop(rbp);
4879 }
4881 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
4882 // Multiplication of two Java long values stored on the stack
4883 // as illustrated below. Result is in rdx:rax.
4884 //
4885 // rsp ---> [ ?? ] \ \
4886 // .... | y_rsp_offset |
4887 // [ y_lo ] / (in bytes) | x_rsp_offset
4888 // [ y_hi ] | (in bytes)
4889 // .... |
4890 // [ x_lo ] /
4891 // [ x_hi ]
4892 // ....
4893 //
4894 // Basic idea: lo(result) = lo(x_lo * y_lo)
4895 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
4896 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
4897 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
4898 Label quick;
4899 // load x_hi, y_hi and check if quick
4900 // multiplication is possible
4901 movl(rbx, x_hi);
4902 movl(rcx, y_hi);
4903 movl(rax, rbx);
4904 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
4905 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
4906 // do full multiplication
4907 // 1st step
4908 mull(y_lo); // x_hi * y_lo
4909 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
4910 // 2nd step
4911 movl(rax, x_lo);
4912 mull(rcx); // x_lo * y_hi
4913 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
4914 // 3rd step
4915 bind(quick); // note: rbx, = 0 if quick multiply!
4916 movl(rax, x_lo);
4917 mull(y_lo); // x_lo * y_lo
4918 addl(rdx, rbx); // correct hi(x_lo * y_lo)
4919 }
4921 void MacroAssembler::lneg(Register hi, Register lo) {
4922 negl(lo);
4923 adcl(hi, 0);
4924 negl(hi);
4925 }
4927 void MacroAssembler::lshl(Register hi, Register lo) {
4928 // Java shift left long support (semantics as described in JVM spec., p.305)
4929 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
4930 // shift value is in rcx !
4931 assert(hi != rcx, "must not use rcx");
4932 assert(lo != rcx, "must not use rcx");
4933 const Register s = rcx; // shift count
4934 const int n = BitsPerWord;
4935 Label L;
4936 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4937 cmpl(s, n); // if (s < n)
4938 jcc(Assembler::less, L); // else (s >= n)
4939 movl(hi, lo); // x := x << n
4940 xorl(lo, lo);
4941 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4942 bind(L); // s (mod n) < n
4943 shldl(hi, lo); // x := x << s
4944 shll(lo);
4945 }
4948 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
4949 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
4950 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
4951 assert(hi != rcx, "must not use rcx");
4952 assert(lo != rcx, "must not use rcx");
4953 const Register s = rcx; // shift count
4954 const int n = BitsPerWord;
4955 Label L;
4956 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
4957 cmpl(s, n); // if (s < n)
4958 jcc(Assembler::less, L); // else (s >= n)
4959 movl(lo, hi); // x := x >> n
4960 if (sign_extension) sarl(hi, 31);
4961 else xorl(hi, hi);
4962 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
4963 bind(L); // s (mod n) < n
4964 shrdl(lo, hi); // x := x >> s
4965 if (sign_extension) sarl(hi);
4966 else shrl(hi);
4967 }
4969 void MacroAssembler::movoop(Register dst, jobject obj) {
4970 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4971 }
4973 void MacroAssembler::movoop(Address dst, jobject obj) {
4974 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
4975 }
4977 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
4978 if (src.is_lval()) {
4979 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
4980 } else {
4981 movl(dst, as_Address(src));
4982 }
4983 }
4985 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
4986 movl(as_Address(dst), src);
4987 }
4989 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
4990 movl(dst, as_Address(src));
4991 }
4993 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
4994 void MacroAssembler::movptr(Address dst, intptr_t src) {
4995 movl(dst, src);
4996 }
4999 void MacroAssembler::pop_callee_saved_registers() {
5000 pop(rcx);
5001 pop(rdx);
5002 pop(rdi);
5003 pop(rsi);
5004 }
5006 void MacroAssembler::pop_fTOS() {
5007 fld_d(Address(rsp, 0));
5008 addl(rsp, 2 * wordSize);
5009 }
5011 void MacroAssembler::push_callee_saved_registers() {
5012 push(rsi);
5013 push(rdi);
5014 push(rdx);
5015 push(rcx);
5016 }
5018 void MacroAssembler::push_fTOS() {
5019 subl(rsp, 2 * wordSize);
5020 fstp_d(Address(rsp, 0));
5021 }
5024 void MacroAssembler::pushoop(jobject obj) {
5025 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
5026 }
5029 void MacroAssembler::pushptr(AddressLiteral src) {
5030 if (src.is_lval()) {
5031 push_literal32((int32_t)src.target(), src.rspec());
5032 } else {
5033 pushl(as_Address(src));
5034 }
5035 }
5037 void MacroAssembler::set_word_if_not_zero(Register dst) {
5038 xorl(dst, dst);
5039 set_byte_if_not_zero(dst);
5040 }
5042 static void pass_arg0(MacroAssembler* masm, Register arg) {
5043 masm->push(arg);
5044 }
5046 static void pass_arg1(MacroAssembler* masm, Register arg) {
5047 masm->push(arg);
5048 }
5050 static void pass_arg2(MacroAssembler* masm, Register arg) {
5051 masm->push(arg);
5052 }
5054 static void pass_arg3(MacroAssembler* masm, Register arg) {
5055 masm->push(arg);
5056 }
5058 #ifndef PRODUCT
5059 extern "C" void findpc(intptr_t x);
5060 #endif
5062 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
5063 // In order to get locks to work, we need to fake a in_VM state
5064 JavaThread* thread = JavaThread::current();
5065 JavaThreadState saved_state = thread->thread_state();
5066 thread->set_thread_state(_thread_in_vm);
5067 if (ShowMessageBoxOnError) {
5068 JavaThread* thread = JavaThread::current();
5069 JavaThreadState saved_state = thread->thread_state();
5070 thread->set_thread_state(_thread_in_vm);
5071 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5072 ttyLocker ttyl;
5073 BytecodeCounter::print();
5074 }
5075 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5076 // This is the value of eip which points to where verify_oop will return.
5077 if (os::message_box(msg, "Execution stopped, print registers?")) {
5078 ttyLocker ttyl;
5079 tty->print_cr("eip = 0x%08x", eip);
5080 #ifndef PRODUCT
5081 if ((WizardMode || Verbose) && PrintMiscellaneous) {
5082 tty->cr();
5083 findpc(eip);
5084 tty->cr();
5085 }
5086 #endif
5087 tty->print_cr("rax = 0x%08x", rax);
5088 tty->print_cr("rbx = 0x%08x", rbx);
5089 tty->print_cr("rcx = 0x%08x", rcx);
5090 tty->print_cr("rdx = 0x%08x", rdx);
5091 tty->print_cr("rdi = 0x%08x", rdi);
5092 tty->print_cr("rsi = 0x%08x", rsi);
5093 tty->print_cr("rbp = 0x%08x", rbp);
5094 tty->print_cr("rsp = 0x%08x", rsp);
5095 BREAKPOINT;
5096 assert(false, "start up GDB");
5097 }
5098 } else {
5099 ttyLocker ttyl;
5100 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
5101 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
5102 }
5103 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5104 }
5106 void MacroAssembler::stop(const char* msg) {
5107 ExternalAddress message((address)msg);
5108 // push address of message
5109 pushptr(message.addr());
5110 { Label L; call(L, relocInfo::none); bind(L); } // push eip
5111 pusha(); // push registers
5112 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
5113 hlt();
5114 }
5116 void MacroAssembler::warn(const char* msg) {
5117 push_CPU_state();
5119 ExternalAddress message((address) msg);
5120 // push address of message
5121 pushptr(message.addr());
5123 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
5124 addl(rsp, wordSize); // discard argument
5125 pop_CPU_state();
5126 }
5128 #else // _LP64
5130 // 64 bit versions
5132 Address MacroAssembler::as_Address(AddressLiteral adr) {
5133 // amd64 always does this as a pc-rel
5134 // we can be absolute or disp based on the instruction type
5135 // jmp/call are displacements others are absolute
5136 assert(!adr.is_lval(), "must be rval");
5137 assert(reachable(adr), "must be");
5138 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
5140 }
5142 Address MacroAssembler::as_Address(ArrayAddress adr) {
5143 AddressLiteral base = adr.base();
5144 lea(rscratch1, base);
5145 Address index = adr.index();
5146 assert(index._disp == 0, "must not have disp"); // maybe it can?
5147 Address array(rscratch1, index._index, index._scale, index._disp);
5148 return array;
5149 }
5151 int MacroAssembler::biased_locking_enter(Register lock_reg,
5152 Register obj_reg,
5153 Register swap_reg,
5154 Register tmp_reg,
5155 bool swap_reg_contains_mark,
5156 Label& done,
5157 Label* slow_case,
5158 BiasedLockingCounters* counters) {
5159 assert(UseBiasedLocking, "why call this otherwise?");
5160 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
5161 assert(tmp_reg != noreg, "tmp_reg must be supplied");
5162 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
5163 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
5164 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
5165 Address saved_mark_addr(lock_reg, 0);
5167 if (PrintBiasedLockingStatistics && counters == NULL)
5168 counters = BiasedLocking::counters();
5170 // Biased locking
5171 // See whether the lock is currently biased toward our thread and
5172 // whether the epoch is still valid
5173 // Note that the runtime guarantees sufficient alignment of JavaThread
5174 // pointers to allow age to be placed into low bits
5175 // First check to see whether biasing is even enabled for this object
5176 Label cas_label;
5177 int null_check_offset = -1;
5178 if (!swap_reg_contains_mark) {
5179 null_check_offset = offset();
5180 movq(swap_reg, mark_addr);
5181 }
5182 movq(tmp_reg, swap_reg);
5183 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5184 cmpq(tmp_reg, markOopDesc::biased_lock_pattern);
5185 jcc(Assembler::notEqual, cas_label);
5186 // The bias pattern is present in the object's header. Need to check
5187 // whether the bias owner and the epoch are both still current.
5188 load_prototype_header(tmp_reg, obj_reg);
5189 orq(tmp_reg, r15_thread);
5190 xorq(tmp_reg, swap_reg);
5191 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place));
5192 if (counters != NULL) {
5193 cond_inc32(Assembler::zero,
5194 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5195 }
5196 jcc(Assembler::equal, done);
5198 Label try_revoke_bias;
5199 Label try_rebias;
5201 // At this point we know that the header has the bias pattern and
5202 // that we are not the bias owner in the current epoch. We need to
5203 // figure out more details about the state of the header in order to
5204 // know what operations can be legally performed on the object's
5205 // header.
5207 // If the low three bits in the xor result aren't clear, that means
5208 // the prototype header is no longer biased and we have to revoke
5209 // the bias on this object.
5210 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place);
5211 jcc(Assembler::notZero, try_revoke_bias);
5213 // Biasing is still enabled for this data type. See whether the
5214 // epoch of the current bias is still valid, meaning that the epoch
5215 // bits of the mark word are equal to the epoch bits of the
5216 // prototype header. (Note that the prototype header's epoch bits
5217 // only change at a safepoint.) If not, attempt to rebias the object
5218 // toward the current thread. Note that we must be absolutely sure
5219 // that the current epoch is invalid in order to do this because
5220 // otherwise the manipulations it performs on the mark word are
5221 // illegal.
5222 testq(tmp_reg, markOopDesc::epoch_mask_in_place);
5223 jcc(Assembler::notZero, try_rebias);
5225 // The epoch of the current bias is still valid but we know nothing
5226 // about the owner; it might be set or it might be clear. Try to
5227 // acquire the bias of the object using an atomic operation. If this
5228 // fails we will go in to the runtime to revoke the object's bias.
5229 // Note that we first construct the presumed unbiased header so we
5230 // don't accidentally blow away another thread's valid bias.
5231 andq(swap_reg,
5232 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
5233 movq(tmp_reg, swap_reg);
5234 orq(tmp_reg, r15_thread);
5235 if (os::is_MP()) {
5236 lock();
5237 }
5238 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5239 // If the biasing toward our thread failed, this means that
5240 // another thread succeeded in biasing it toward itself and we
5241 // need to revoke that bias. The revocation will occur in the
5242 // interpreter runtime in the slow case.
5243 if (counters != NULL) {
5244 cond_inc32(Assembler::zero,
5245 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
5246 }
5247 if (slow_case != NULL) {
5248 jcc(Assembler::notZero, *slow_case);
5249 }
5250 jmp(done);
5252 bind(try_rebias);
5253 // At this point we know the epoch has expired, meaning that the
5254 // current "bias owner", if any, is actually invalid. Under these
5255 // circumstances _only_, we are allowed to use the current header's
5256 // value as the comparison value when doing the cas to acquire the
5257 // bias in the current epoch. In other words, we allow transfer of
5258 // the bias from one thread to another directly in this situation.
5259 //
5260 // FIXME: due to a lack of registers we currently blow away the age
5261 // bits in this situation. Should attempt to preserve them.
5262 load_prototype_header(tmp_reg, obj_reg);
5263 orq(tmp_reg, r15_thread);
5264 if (os::is_MP()) {
5265 lock();
5266 }
5267 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5268 // If the biasing toward our thread failed, then another thread
5269 // succeeded in biasing it toward itself and we need to revoke that
5270 // bias. The revocation will occur in the runtime in the slow case.
5271 if (counters != NULL) {
5272 cond_inc32(Assembler::zero,
5273 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
5274 }
5275 if (slow_case != NULL) {
5276 jcc(Assembler::notZero, *slow_case);
5277 }
5278 jmp(done);
5280 bind(try_revoke_bias);
5281 // The prototype mark in the klass doesn't have the bias bit set any
5282 // more, indicating that objects of this data type are not supposed
5283 // to be biased any more. We are going to try to reset the mark of
5284 // this object to the prototype value and fall through to the
5285 // CAS-based locking scheme. Note that if our CAS fails, it means
5286 // that another thread raced us for the privilege of revoking the
5287 // bias of this particular object, so it's okay to continue in the
5288 // normal locking code.
5289 //
5290 // FIXME: due to a lack of registers we currently blow away the age
5291 // bits in this situation. Should attempt to preserve them.
5292 load_prototype_header(tmp_reg, obj_reg);
5293 if (os::is_MP()) {
5294 lock();
5295 }
5296 cmpxchgq(tmp_reg, Address(obj_reg, 0));
5297 // Fall through to the normal CAS-based lock, because no matter what
5298 // the result of the above CAS, some thread must have succeeded in
5299 // removing the bias bit from the object's header.
5300 if (counters != NULL) {
5301 cond_inc32(Assembler::zero,
5302 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
5303 }
5305 bind(cas_label);
5307 return null_check_offset;
5308 }
5310 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
5311 Label L, E;
5313 #ifdef _WIN64
5314 // Windows always allocates space for it's register args
5315 assert(num_args <= 4, "only register arguments supported");
5316 subq(rsp, frame::arg_reg_save_area_bytes);
5317 #endif
5319 // Align stack if necessary
5320 testl(rsp, 15);
5321 jcc(Assembler::zero, L);
5323 subq(rsp, 8);
5324 {
5325 call(RuntimeAddress(entry_point));
5326 }
5327 addq(rsp, 8);
5328 jmp(E);
5330 bind(L);
5331 {
5332 call(RuntimeAddress(entry_point));
5333 }
5335 bind(E);
5337 #ifdef _WIN64
5338 // restore stack pointer
5339 addq(rsp, frame::arg_reg_save_area_bytes);
5340 #endif
5342 }
5344 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
5345 assert(!src2.is_lval(), "should use cmpptr");
5347 if (reachable(src2)) {
5348 cmpq(src1, as_Address(src2));
5349 } else {
5350 lea(rscratch1, src2);
5351 Assembler::cmpq(src1, Address(rscratch1, 0));
5352 }
5353 }
5355 int MacroAssembler::corrected_idivq(Register reg) {
5356 // Full implementation of Java ldiv and lrem; checks for special
5357 // case as described in JVM spec., p.243 & p.271. The function
5358 // returns the (pc) offset of the idivl instruction - may be needed
5359 // for implicit exceptions.
5360 //
5361 // normal case special case
5362 //
5363 // input : rax: dividend min_long
5364 // reg: divisor (may not be eax/edx) -1
5365 //
5366 // output: rax: quotient (= rax idiv reg) min_long
5367 // rdx: remainder (= rax irem reg) 0
5368 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
5369 static const int64_t min_long = 0x8000000000000000;
5370 Label normal_case, special_case;
5372 // check for special case
5373 cmp64(rax, ExternalAddress((address) &min_long));
5374 jcc(Assembler::notEqual, normal_case);
5375 xorl(rdx, rdx); // prepare rdx for possible special case (where
5376 // remainder = 0)
5377 cmpq(reg, -1);
5378 jcc(Assembler::equal, special_case);
5380 // handle normal case
5381 bind(normal_case);
5382 cdqq();
5383 int idivq_offset = offset();
5384 idivq(reg);
5386 // normal and special case exit
5387 bind(special_case);
5389 return idivq_offset;
5390 }
5392 void MacroAssembler::decrementq(Register reg, int value) {
5393 if (value == min_jint) { subq(reg, value); return; }
5394 if (value < 0) { incrementq(reg, -value); return; }
5395 if (value == 0) { ; return; }
5396 if (value == 1 && UseIncDec) { decq(reg) ; return; }
5397 /* else */ { subq(reg, value) ; return; }
5398 }
5400 void MacroAssembler::decrementq(Address dst, int value) {
5401 if (value == min_jint) { subq(dst, value); return; }
5402 if (value < 0) { incrementq(dst, -value); return; }
5403 if (value == 0) { ; return; }
5404 if (value == 1 && UseIncDec) { decq(dst) ; return; }
5405 /* else */ { subq(dst, value) ; return; }
5406 }
5408 void MacroAssembler::fat_nop() {
5409 // A 5 byte nop that is safe for patching (see patch_verified_entry)
5410 // Recommened sequence from 'Software Optimization Guide for the AMD
5411 // Hammer Processor'
5412 emit_byte(0x66);
5413 emit_byte(0x66);
5414 emit_byte(0x90);
5415 emit_byte(0x66);
5416 emit_byte(0x90);
5417 }
5419 void MacroAssembler::incrementq(Register reg, int value) {
5420 if (value == min_jint) { addq(reg, value); return; }
5421 if (value < 0) { decrementq(reg, -value); return; }
5422 if (value == 0) { ; return; }
5423 if (value == 1 && UseIncDec) { incq(reg) ; return; }
5424 /* else */ { addq(reg, value) ; return; }
5425 }
5427 void MacroAssembler::incrementq(Address dst, int value) {
5428 if (value == min_jint) { addq(dst, value); return; }
5429 if (value < 0) { decrementq(dst, -value); return; }
5430 if (value == 0) { ; return; }
5431 if (value == 1 && UseIncDec) { incq(dst) ; return; }
5432 /* else */ { addq(dst, value) ; return; }
5433 }
5435 // 32bit can do a case table jump in one instruction but we no longer allow the base
5436 // to be installed in the Address class
5437 void MacroAssembler::jump(ArrayAddress entry) {
5438 lea(rscratch1, entry.base());
5439 Address dispatch = entry.index();
5440 assert(dispatch._base == noreg, "must be");
5441 dispatch._base = rscratch1;
5442 jmp(dispatch);
5443 }
5445 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
5446 ShouldNotReachHere(); // 64bit doesn't use two regs
5447 cmpq(x_lo, y_lo);
5448 }
5450 void MacroAssembler::lea(Register dst, AddressLiteral src) {
5451 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5452 }
5454 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
5455 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
5456 movptr(dst, rscratch1);
5457 }
5459 void MacroAssembler::leave() {
5460 // %%% is this really better? Why not on 32bit too?
5461 emit_byte(0xC9); // LEAVE
5462 }
5464 void MacroAssembler::lneg(Register hi, Register lo) {
5465 ShouldNotReachHere(); // 64bit doesn't use two regs
5466 negq(lo);
5467 }
5469 void MacroAssembler::movoop(Register dst, jobject obj) {
5470 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5471 }
5473 void MacroAssembler::movoop(Address dst, jobject obj) {
5474 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
5475 movq(dst, rscratch1);
5476 }
5478 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
5479 if (src.is_lval()) {
5480 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
5481 } else {
5482 if (reachable(src)) {
5483 movq(dst, as_Address(src));
5484 } else {
5485 lea(rscratch1, src);
5486 movq(dst, Address(rscratch1,0));
5487 }
5488 }
5489 }
5491 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
5492 movq(as_Address(dst), src);
5493 }
5495 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
5496 movq(dst, as_Address(src));
5497 }
5499 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
5500 void MacroAssembler::movptr(Address dst, intptr_t src) {
5501 mov64(rscratch1, src);
5502 movq(dst, rscratch1);
5503 }
5505 // These are mostly for initializing NULL
5506 void MacroAssembler::movptr(Address dst, int32_t src) {
5507 movslq(dst, src);
5508 }
5510 void MacroAssembler::movptr(Register dst, int32_t src) {
5511 mov64(dst, (intptr_t)src);
5512 }
5514 void MacroAssembler::pushoop(jobject obj) {
5515 movoop(rscratch1, obj);
5516 push(rscratch1);
5517 }
5519 void MacroAssembler::pushptr(AddressLiteral src) {
5520 lea(rscratch1, src);
5521 if (src.is_lval()) {
5522 push(rscratch1);
5523 } else {
5524 pushq(Address(rscratch1, 0));
5525 }
5526 }
5528 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
5529 bool clear_pc) {
5530 // we must set sp to zero to clear frame
5531 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
5532 // must clear fp, so that compiled frames are not confused; it is
5533 // possible that we need it only for debugging
5534 if (clear_fp) {
5535 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
5536 }
5538 if (clear_pc) {
5539 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
5540 }
5541 }
5543 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
5544 Register last_java_fp,
5545 address last_java_pc) {
5546 // determine last_java_sp register
5547 if (!last_java_sp->is_valid()) {
5548 last_java_sp = rsp;
5549 }
5551 // last_java_fp is optional
5552 if (last_java_fp->is_valid()) {
5553 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
5554 last_java_fp);
5555 }
5557 // last_java_pc is optional
5558 if (last_java_pc != NULL) {
5559 Address java_pc(r15_thread,
5560 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
5561 lea(rscratch1, InternalAddress(last_java_pc));
5562 movptr(java_pc, rscratch1);
5563 }
5565 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
5566 }
5568 static void pass_arg0(MacroAssembler* masm, Register arg) {
5569 if (c_rarg0 != arg ) {
5570 masm->mov(c_rarg0, arg);
5571 }
5572 }
5574 static void pass_arg1(MacroAssembler* masm, Register arg) {
5575 if (c_rarg1 != arg ) {
5576 masm->mov(c_rarg1, arg);
5577 }
5578 }
5580 static void pass_arg2(MacroAssembler* masm, Register arg) {
5581 if (c_rarg2 != arg ) {
5582 masm->mov(c_rarg2, arg);
5583 }
5584 }
5586 static void pass_arg3(MacroAssembler* masm, Register arg) {
5587 if (c_rarg3 != arg ) {
5588 masm->mov(c_rarg3, arg);
5589 }
5590 }
5592 void MacroAssembler::stop(const char* msg) {
5593 address rip = pc();
5594 pusha(); // get regs on stack
5595 lea(c_rarg0, ExternalAddress((address) msg));
5596 lea(c_rarg1, InternalAddress(rip));
5597 movq(c_rarg2, rsp); // pass pointer to regs array
5598 andq(rsp, -16); // align stack as required by ABI
5599 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
5600 hlt();
5601 }
5603 void MacroAssembler::warn(const char* msg) {
5604 push(rsp);
5605 andq(rsp, -16); // align stack as required by push_CPU_state and call
5607 push_CPU_state(); // keeps alignment at 16 bytes
5608 lea(c_rarg0, ExternalAddress((address) msg));
5609 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
5610 pop_CPU_state();
5611 pop(rsp);
5612 }
5614 #ifndef PRODUCT
5615 extern "C" void findpc(intptr_t x);
5616 #endif
5618 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
5619 // In order to get locks to work, we need to fake a in_VM state
5620 if (ShowMessageBoxOnError ) {
5621 JavaThread* thread = JavaThread::current();
5622 JavaThreadState saved_state = thread->thread_state();
5623 thread->set_thread_state(_thread_in_vm);
5624 #ifndef PRODUCT
5625 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
5626 ttyLocker ttyl;
5627 BytecodeCounter::print();
5628 }
5629 #endif
5630 // To see where a verify_oop failed, get $ebx+40/X for this frame.
5631 // XXX correct this offset for amd64
5632 // This is the value of eip which points to where verify_oop will return.
5633 if (os::message_box(msg, "Execution stopped, print registers?")) {
5634 ttyLocker ttyl;
5635 tty->print_cr("rip = 0x%016lx", pc);
5636 #ifndef PRODUCT
5637 tty->cr();
5638 findpc(pc);
5639 tty->cr();
5640 #endif
5641 tty->print_cr("rax = 0x%016lx", regs[15]);
5642 tty->print_cr("rbx = 0x%016lx", regs[12]);
5643 tty->print_cr("rcx = 0x%016lx", regs[14]);
5644 tty->print_cr("rdx = 0x%016lx", regs[13]);
5645 tty->print_cr("rdi = 0x%016lx", regs[8]);
5646 tty->print_cr("rsi = 0x%016lx", regs[9]);
5647 tty->print_cr("rbp = 0x%016lx", regs[10]);
5648 tty->print_cr("rsp = 0x%016lx", regs[11]);
5649 tty->print_cr("r8 = 0x%016lx", regs[7]);
5650 tty->print_cr("r9 = 0x%016lx", regs[6]);
5651 tty->print_cr("r10 = 0x%016lx", regs[5]);
5652 tty->print_cr("r11 = 0x%016lx", regs[4]);
5653 tty->print_cr("r12 = 0x%016lx", regs[3]);
5654 tty->print_cr("r13 = 0x%016lx", regs[2]);
5655 tty->print_cr("r14 = 0x%016lx", regs[1]);
5656 tty->print_cr("r15 = 0x%016lx", regs[0]);
5657 BREAKPOINT;
5658 }
5659 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
5660 } else {
5661 ttyLocker ttyl;
5662 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
5663 msg);
5664 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
5665 }
5666 }
5668 #endif // _LP64
5670 // Now versions that are common to 32/64 bit
5672 void MacroAssembler::addptr(Register dst, int32_t imm32) {
5673 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
5674 }
5676 void MacroAssembler::addptr(Register dst, Register src) {
5677 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5678 }
5680 void MacroAssembler::addptr(Address dst, Register src) {
5681 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
5682 }
5684 void MacroAssembler::align(int modulus) {
5685 if (offset() % modulus != 0) {
5686 nop(modulus - (offset() % modulus));
5687 }
5688 }
5690 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
5691 if (reachable(src)) {
5692 andpd(dst, as_Address(src));
5693 } else {
5694 lea(rscratch1, src);
5695 andpd(dst, Address(rscratch1, 0));
5696 }
5697 }
5699 void MacroAssembler::andptr(Register dst, int32_t imm32) {
5700 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
5701 }
5703 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
5704 pushf();
5705 if (os::is_MP())
5706 lock();
5707 incrementl(counter_addr);
5708 popf();
5709 }
5711 // Writes to stack successive pages until offset reached to check for
5712 // stack overflow + shadow pages. This clobbers tmp.
5713 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5714 movptr(tmp, rsp);
5715 // Bang stack for total size given plus shadow page size.
5716 // Bang one page at a time because large size can bang beyond yellow and
5717 // red zones.
5718 Label loop;
5719 bind(loop);
5720 movl(Address(tmp, (-os::vm_page_size())), size );
5721 subptr(tmp, os::vm_page_size());
5722 subl(size, os::vm_page_size());
5723 jcc(Assembler::greater, loop);
5725 // Bang down shadow pages too.
5726 // The -1 because we already subtracted 1 page.
5727 for (int i = 0; i< StackShadowPages-1; i++) {
5728 // this could be any sized move but this is can be a debugging crumb
5729 // so the bigger the better.
5730 movptr(Address(tmp, (-i*os::vm_page_size())), size );
5731 }
5732 }
5734 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
5735 assert(UseBiasedLocking, "why call this otherwise?");
5737 // Check for biased locking unlock case, which is a no-op
5738 // Note: we do not have to check the thread ID for two reasons.
5739 // First, the interpreter checks for IllegalMonitorStateException at
5740 // a higher level. Second, if the bias was revoked while we held the
5741 // lock, the object could not be rebiased toward another thread, so
5742 // the bias bit would be clear.
5743 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
5744 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
5745 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
5746 jcc(Assembler::equal, done);
5747 }
5749 void MacroAssembler::c2bool(Register x) {
5750 // implements x == 0 ? 0 : 1
5751 // note: must only look at least-significant byte of x
5752 // since C-style booleans are stored in one byte
5753 // only! (was bug)
5754 andl(x, 0xFF);
5755 setb(Assembler::notZero, x);
5756 }
5758 // Wouldn't need if AddressLiteral version had new name
5759 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
5760 Assembler::call(L, rtype);
5761 }
5763 void MacroAssembler::call(Register entry) {
5764 Assembler::call(entry);
5765 }
5767 void MacroAssembler::call(AddressLiteral entry) {
5768 if (reachable(entry)) {
5769 Assembler::call_literal(entry.target(), entry.rspec());
5770 } else {
5771 lea(rscratch1, entry);
5772 Assembler::call(rscratch1);
5773 }
5774 }
5776 // Implementation of call_VM versions
5778 void MacroAssembler::call_VM(Register oop_result,
5779 address entry_point,
5780 bool check_exceptions) {
5781 Label C, E;
5782 call(C, relocInfo::none);
5783 jmp(E);
5785 bind(C);
5786 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
5787 ret(0);
5789 bind(E);
5790 }
5792 void MacroAssembler::call_VM(Register oop_result,
5793 address entry_point,
5794 Register arg_1,
5795 bool check_exceptions) {
5796 Label C, E;
5797 call(C, relocInfo::none);
5798 jmp(E);
5800 bind(C);
5801 pass_arg1(this, arg_1);
5802 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
5803 ret(0);
5805 bind(E);
5806 }
5808 void MacroAssembler::call_VM(Register oop_result,
5809 address entry_point,
5810 Register arg_1,
5811 Register arg_2,
5812 bool check_exceptions) {
5813 Label C, E;
5814 call(C, relocInfo::none);
5815 jmp(E);
5817 bind(C);
5819 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5821 pass_arg2(this, arg_2);
5822 pass_arg1(this, arg_1);
5823 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
5824 ret(0);
5826 bind(E);
5827 }
5829 void MacroAssembler::call_VM(Register oop_result,
5830 address entry_point,
5831 Register arg_1,
5832 Register arg_2,
5833 Register arg_3,
5834 bool check_exceptions) {
5835 Label C, E;
5836 call(C, relocInfo::none);
5837 jmp(E);
5839 bind(C);
5841 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5842 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5843 pass_arg3(this, arg_3);
5845 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5846 pass_arg2(this, arg_2);
5848 pass_arg1(this, arg_1);
5849 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
5850 ret(0);
5852 bind(E);
5853 }
5855 void MacroAssembler::call_VM(Register oop_result,
5856 Register last_java_sp,
5857 address entry_point,
5858 int number_of_arguments,
5859 bool check_exceptions) {
5860 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
5861 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
5862 }
5864 void MacroAssembler::call_VM(Register oop_result,
5865 Register last_java_sp,
5866 address entry_point,
5867 Register arg_1,
5868 bool check_exceptions) {
5869 pass_arg1(this, arg_1);
5870 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
5871 }
5873 void MacroAssembler::call_VM(Register oop_result,
5874 Register last_java_sp,
5875 address entry_point,
5876 Register arg_1,
5877 Register arg_2,
5878 bool check_exceptions) {
5880 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5881 pass_arg2(this, arg_2);
5882 pass_arg1(this, arg_1);
5883 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
5884 }
5886 void MacroAssembler::call_VM(Register oop_result,
5887 Register last_java_sp,
5888 address entry_point,
5889 Register arg_1,
5890 Register arg_2,
5891 Register arg_3,
5892 bool check_exceptions) {
5893 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5894 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5895 pass_arg3(this, arg_3);
5896 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5897 pass_arg2(this, arg_2);
5898 pass_arg1(this, arg_1);
5899 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
5900 }
5902 void MacroAssembler::super_call_VM(Register oop_result,
5903 Register last_java_sp,
5904 address entry_point,
5905 int number_of_arguments,
5906 bool check_exceptions) {
5907 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
5908 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
5909 }
5911 void MacroAssembler::super_call_VM(Register oop_result,
5912 Register last_java_sp,
5913 address entry_point,
5914 Register arg_1,
5915 bool check_exceptions) {
5916 pass_arg1(this, arg_1);
5917 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
5918 }
5920 void MacroAssembler::super_call_VM(Register oop_result,
5921 Register last_java_sp,
5922 address entry_point,
5923 Register arg_1,
5924 Register arg_2,
5925 bool check_exceptions) {
5927 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5928 pass_arg2(this, arg_2);
5929 pass_arg1(this, arg_1);
5930 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
5931 }
5933 void MacroAssembler::super_call_VM(Register oop_result,
5934 Register last_java_sp,
5935 address entry_point,
5936 Register arg_1,
5937 Register arg_2,
5938 Register arg_3,
5939 bool check_exceptions) {
5940 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
5941 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
5942 pass_arg3(this, arg_3);
5943 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
5944 pass_arg2(this, arg_2);
5945 pass_arg1(this, arg_1);
5946 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
5947 }
5949 void MacroAssembler::call_VM_base(Register oop_result,
5950 Register java_thread,
5951 Register last_java_sp,
5952 address entry_point,
5953 int number_of_arguments,
5954 bool check_exceptions) {
5955 // determine java_thread register
5956 if (!java_thread->is_valid()) {
5957 #ifdef _LP64
5958 java_thread = r15_thread;
5959 #else
5960 java_thread = rdi;
5961 get_thread(java_thread);
5962 #endif // LP64
5963 }
5964 // determine last_java_sp register
5965 if (!last_java_sp->is_valid()) {
5966 last_java_sp = rsp;
5967 }
5968 // debugging support
5969 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
5970 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
5971 #ifdef ASSERT
5972 LP64_ONLY(if (UseCompressedOops) verify_heapbase("call_VM_base");)
5973 #endif // ASSERT
5975 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
5976 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
5978 // push java thread (becomes first argument of C function)
5980 NOT_LP64(push(java_thread); number_of_arguments++);
5981 LP64_ONLY(mov(c_rarg0, r15_thread));
5983 // set last Java frame before call
5984 assert(last_java_sp != rbp, "can't use ebp/rbp");
5986 // Only interpreter should have to set fp
5987 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
5989 // do the call, remove parameters
5990 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
5992 // restore the thread (cannot use the pushed argument since arguments
5993 // may be overwritten by C code generated by an optimizing compiler);
5994 // however can use the register value directly if it is callee saved.
5995 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
5996 // rdi & rsi (also r15) are callee saved -> nothing to do
5997 #ifdef ASSERT
5998 guarantee(java_thread != rax, "change this code");
5999 push(rax);
6000 { Label L;
6001 get_thread(rax);
6002 cmpptr(java_thread, rax);
6003 jcc(Assembler::equal, L);
6004 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
6005 bind(L);
6006 }
6007 pop(rax);
6008 #endif
6009 } else {
6010 get_thread(java_thread);
6011 }
6012 // reset last Java frame
6013 // Only interpreter should have to clear fp
6014 reset_last_Java_frame(java_thread, true, false);
6016 #ifndef CC_INTERP
6017 // C++ interp handles this in the interpreter
6018 check_and_handle_popframe(java_thread);
6019 check_and_handle_earlyret(java_thread);
6020 #endif /* CC_INTERP */
6022 if (check_exceptions) {
6023 // check for pending exceptions (java_thread is set upon return)
6024 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
6025 #ifndef _LP64
6026 jump_cc(Assembler::notEqual,
6027 RuntimeAddress(StubRoutines::forward_exception_entry()));
6028 #else
6029 // This used to conditionally jump to forward_exception however it is
6030 // possible if we relocate that the branch will not reach. So we must jump
6031 // around so we can always reach
6033 Label ok;
6034 jcc(Assembler::equal, ok);
6035 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
6036 bind(ok);
6037 #endif // LP64
6038 }
6040 // get oop result if there is one and reset the value in the thread
6041 if (oop_result->is_valid()) {
6042 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
6043 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
6044 verify_oop(oop_result, "broken oop in call_VM_base");
6045 }
6046 }
6048 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
6050 // Calculate the value for last_Java_sp
6051 // somewhat subtle. call_VM does an intermediate call
6052 // which places a return address on the stack just under the
6053 // stack pointer as the user finsihed with it. This allows
6054 // use to retrieve last_Java_pc from last_Java_sp[-1].
6055 // On 32bit we then have to push additional args on the stack to accomplish
6056 // the actual requested call. On 64bit call_VM only can use register args
6057 // so the only extra space is the return address that call_VM created.
6058 // This hopefully explains the calculations here.
6060 #ifdef _LP64
6061 // We've pushed one address, correct last_Java_sp
6062 lea(rax, Address(rsp, wordSize));
6063 #else
6064 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
6065 #endif // LP64
6067 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
6069 }
6071 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
6072 call_VM_leaf_base(entry_point, number_of_arguments);
6073 }
6075 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
6076 pass_arg0(this, arg_0);
6077 call_VM_leaf(entry_point, 1);
6078 }
6080 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
6082 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6083 pass_arg1(this, arg_1);
6084 pass_arg0(this, arg_0);
6085 call_VM_leaf(entry_point, 2);
6086 }
6088 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
6089 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6090 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6091 pass_arg2(this, arg_2);
6092 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6093 pass_arg1(this, arg_1);
6094 pass_arg0(this, arg_0);
6095 call_VM_leaf(entry_point, 3);
6096 }
6098 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
6099 pass_arg0(this, arg_0);
6100 MacroAssembler::call_VM_leaf_base(entry_point, 1);
6101 }
6103 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
6105 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6106 pass_arg1(this, arg_1);
6107 pass_arg0(this, arg_0);
6108 MacroAssembler::call_VM_leaf_base(entry_point, 2);
6109 }
6111 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
6112 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6113 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6114 pass_arg2(this, arg_2);
6115 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6116 pass_arg1(this, arg_1);
6117 pass_arg0(this, arg_0);
6118 MacroAssembler::call_VM_leaf_base(entry_point, 3);
6119 }
6121 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
6122 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
6123 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
6124 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
6125 pass_arg3(this, arg_3);
6126 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
6127 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
6128 pass_arg2(this, arg_2);
6129 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
6130 pass_arg1(this, arg_1);
6131 pass_arg0(this, arg_0);
6132 MacroAssembler::call_VM_leaf_base(entry_point, 4);
6133 }
6135 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
6136 }
6138 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
6139 }
6141 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
6142 if (reachable(src1)) {
6143 cmpl(as_Address(src1), imm);
6144 } else {
6145 lea(rscratch1, src1);
6146 cmpl(Address(rscratch1, 0), imm);
6147 }
6148 }
6150 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
6151 assert(!src2.is_lval(), "use cmpptr");
6152 if (reachable(src2)) {
6153 cmpl(src1, as_Address(src2));
6154 } else {
6155 lea(rscratch1, src2);
6156 cmpl(src1, Address(rscratch1, 0));
6157 }
6158 }
6160 void MacroAssembler::cmp32(Register src1, int32_t imm) {
6161 Assembler::cmpl(src1, imm);
6162 }
6164 void MacroAssembler::cmp32(Register src1, Address src2) {
6165 Assembler::cmpl(src1, src2);
6166 }
6168 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6169 ucomisd(opr1, opr2);
6171 Label L;
6172 if (unordered_is_less) {
6173 movl(dst, -1);
6174 jcc(Assembler::parity, L);
6175 jcc(Assembler::below , L);
6176 movl(dst, 0);
6177 jcc(Assembler::equal , L);
6178 increment(dst);
6179 } else { // unordered is greater
6180 movl(dst, 1);
6181 jcc(Assembler::parity, L);
6182 jcc(Assembler::above , L);
6183 movl(dst, 0);
6184 jcc(Assembler::equal , L);
6185 decrementl(dst);
6186 }
6187 bind(L);
6188 }
6190 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
6191 ucomiss(opr1, opr2);
6193 Label L;
6194 if (unordered_is_less) {
6195 movl(dst, -1);
6196 jcc(Assembler::parity, L);
6197 jcc(Assembler::below , L);
6198 movl(dst, 0);
6199 jcc(Assembler::equal , L);
6200 increment(dst);
6201 } else { // unordered is greater
6202 movl(dst, 1);
6203 jcc(Assembler::parity, L);
6204 jcc(Assembler::above , L);
6205 movl(dst, 0);
6206 jcc(Assembler::equal , L);
6207 decrementl(dst);
6208 }
6209 bind(L);
6210 }
6213 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
6214 if (reachable(src1)) {
6215 cmpb(as_Address(src1), imm);
6216 } else {
6217 lea(rscratch1, src1);
6218 cmpb(Address(rscratch1, 0), imm);
6219 }
6220 }
6222 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
6223 #ifdef _LP64
6224 if (src2.is_lval()) {
6225 movptr(rscratch1, src2);
6226 Assembler::cmpq(src1, rscratch1);
6227 } else if (reachable(src2)) {
6228 cmpq(src1, as_Address(src2));
6229 } else {
6230 lea(rscratch1, src2);
6231 Assembler::cmpq(src1, Address(rscratch1, 0));
6232 }
6233 #else
6234 if (src2.is_lval()) {
6235 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6236 } else {
6237 cmpl(src1, as_Address(src2));
6238 }
6239 #endif // _LP64
6240 }
6242 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
6243 assert(src2.is_lval(), "not a mem-mem compare");
6244 #ifdef _LP64
6245 // moves src2's literal address
6246 movptr(rscratch1, src2);
6247 Assembler::cmpq(src1, rscratch1);
6248 #else
6249 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
6250 #endif // _LP64
6251 }
6253 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
6254 if (reachable(adr)) {
6255 if (os::is_MP())
6256 lock();
6257 cmpxchgptr(reg, as_Address(adr));
6258 } else {
6259 lea(rscratch1, adr);
6260 if (os::is_MP())
6261 lock();
6262 cmpxchgptr(reg, Address(rscratch1, 0));
6263 }
6264 }
6266 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
6267 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
6268 }
6270 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
6271 if (reachable(src)) {
6272 comisd(dst, as_Address(src));
6273 } else {
6274 lea(rscratch1, src);
6275 comisd(dst, Address(rscratch1, 0));
6276 }
6277 }
6279 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
6280 if (reachable(src)) {
6281 comiss(dst, as_Address(src));
6282 } else {
6283 lea(rscratch1, src);
6284 comiss(dst, Address(rscratch1, 0));
6285 }
6286 }
6289 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
6290 Condition negated_cond = negate_condition(cond);
6291 Label L;
6292 jcc(negated_cond, L);
6293 atomic_incl(counter_addr);
6294 bind(L);
6295 }
6297 int MacroAssembler::corrected_idivl(Register reg) {
6298 // Full implementation of Java idiv and irem; checks for
6299 // special case as described in JVM spec., p.243 & p.271.
6300 // The function returns the (pc) offset of the idivl
6301 // instruction - may be needed for implicit exceptions.
6302 //
6303 // normal case special case
6304 //
6305 // input : rax,: dividend min_int
6306 // reg: divisor (may not be rax,/rdx) -1
6307 //
6308 // output: rax,: quotient (= rax, idiv reg) min_int
6309 // rdx: remainder (= rax, irem reg) 0
6310 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
6311 const int min_int = 0x80000000;
6312 Label normal_case, special_case;
6314 // check for special case
6315 cmpl(rax, min_int);
6316 jcc(Assembler::notEqual, normal_case);
6317 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
6318 cmpl(reg, -1);
6319 jcc(Assembler::equal, special_case);
6321 // handle normal case
6322 bind(normal_case);
6323 cdql();
6324 int idivl_offset = offset();
6325 idivl(reg);
6327 // normal and special case exit
6328 bind(special_case);
6330 return idivl_offset;
6331 }
6335 void MacroAssembler::decrementl(Register reg, int value) {
6336 if (value == min_jint) {subl(reg, value) ; return; }
6337 if (value < 0) { incrementl(reg, -value); return; }
6338 if (value == 0) { ; return; }
6339 if (value == 1 && UseIncDec) { decl(reg) ; return; }
6340 /* else */ { subl(reg, value) ; return; }
6341 }
6343 void MacroAssembler::decrementl(Address dst, int value) {
6344 if (value == min_jint) {subl(dst, value) ; return; }
6345 if (value < 0) { incrementl(dst, -value); return; }
6346 if (value == 0) { ; return; }
6347 if (value == 1 && UseIncDec) { decl(dst) ; return; }
6348 /* else */ { subl(dst, value) ; return; }
6349 }
6351 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
6352 assert (shift_value > 0, "illegal shift value");
6353 Label _is_positive;
6354 testl (reg, reg);
6355 jcc (Assembler::positive, _is_positive);
6356 int offset = (1 << shift_value) - 1 ;
6358 if (offset == 1) {
6359 incrementl(reg);
6360 } else {
6361 addl(reg, offset);
6362 }
6364 bind (_is_positive);
6365 sarl(reg, shift_value);
6366 }
6368 // !defined(COMPILER2) is because of stupid core builds
6369 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
6370 void MacroAssembler::empty_FPU_stack() {
6371 if (VM_Version::supports_mmx()) {
6372 emms();
6373 } else {
6374 for (int i = 8; i-- > 0; ) ffree(i);
6375 }
6376 }
6377 #endif // !LP64 || C1 || !C2
6380 // Defines obj, preserves var_size_in_bytes
6381 void MacroAssembler::eden_allocate(Register obj,
6382 Register var_size_in_bytes,
6383 int con_size_in_bytes,
6384 Register t1,
6385 Label& slow_case) {
6386 assert(obj == rax, "obj must be in rax, for cmpxchg");
6387 assert_different_registers(obj, var_size_in_bytes, t1);
6388 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
6389 jmp(slow_case);
6390 } else {
6391 Register end = t1;
6392 Label retry;
6393 bind(retry);
6394 ExternalAddress heap_top((address) Universe::heap()->top_addr());
6395 movptr(obj, heap_top);
6396 if (var_size_in_bytes == noreg) {
6397 lea(end, Address(obj, con_size_in_bytes));
6398 } else {
6399 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
6400 }
6401 // if end < obj then we wrapped around => object too long => slow case
6402 cmpptr(end, obj);
6403 jcc(Assembler::below, slow_case);
6404 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
6405 jcc(Assembler::above, slow_case);
6406 // Compare obj with the top addr, and if still equal, store the new top addr in
6407 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
6408 // it otherwise. Use lock prefix for atomicity on MPs.
6409 locked_cmpxchgptr(end, heap_top);
6410 jcc(Assembler::notEqual, retry);
6411 }
6412 }
6414 void MacroAssembler::enter() {
6415 push(rbp);
6416 mov(rbp, rsp);
6417 }
6419 void MacroAssembler::fcmp(Register tmp) {
6420 fcmp(tmp, 1, true, true);
6421 }
6423 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
6424 assert(!pop_right || pop_left, "usage error");
6425 if (VM_Version::supports_cmov()) {
6426 assert(tmp == noreg, "unneeded temp");
6427 if (pop_left) {
6428 fucomip(index);
6429 } else {
6430 fucomi(index);
6431 }
6432 if (pop_right) {
6433 fpop();
6434 }
6435 } else {
6436 assert(tmp != noreg, "need temp");
6437 if (pop_left) {
6438 if (pop_right) {
6439 fcompp();
6440 } else {
6441 fcomp(index);
6442 }
6443 } else {
6444 fcom(index);
6445 }
6446 // convert FPU condition into eflags condition via rax,
6447 save_rax(tmp);
6448 fwait(); fnstsw_ax();
6449 sahf();
6450 restore_rax(tmp);
6451 }
6452 // condition codes set as follows:
6453 //
6454 // CF (corresponds to C0) if x < y
6455 // PF (corresponds to C2) if unordered
6456 // ZF (corresponds to C3) if x = y
6457 }
6459 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
6460 fcmp2int(dst, unordered_is_less, 1, true, true);
6461 }
6463 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
6464 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
6465 Label L;
6466 if (unordered_is_less) {
6467 movl(dst, -1);
6468 jcc(Assembler::parity, L);
6469 jcc(Assembler::below , L);
6470 movl(dst, 0);
6471 jcc(Assembler::equal , L);
6472 increment(dst);
6473 } else { // unordered is greater
6474 movl(dst, 1);
6475 jcc(Assembler::parity, L);
6476 jcc(Assembler::above , L);
6477 movl(dst, 0);
6478 jcc(Assembler::equal , L);
6479 decrementl(dst);
6480 }
6481 bind(L);
6482 }
6484 void MacroAssembler::fld_d(AddressLiteral src) {
6485 fld_d(as_Address(src));
6486 }
6488 void MacroAssembler::fld_s(AddressLiteral src) {
6489 fld_s(as_Address(src));
6490 }
6492 void MacroAssembler::fld_x(AddressLiteral src) {
6493 Assembler::fld_x(as_Address(src));
6494 }
6496 void MacroAssembler::fldcw(AddressLiteral src) {
6497 Assembler::fldcw(as_Address(src));
6498 }
6500 void MacroAssembler::fpop() {
6501 ffree();
6502 fincstp();
6503 }
6505 void MacroAssembler::fremr(Register tmp) {
6506 save_rax(tmp);
6507 { Label L;
6508 bind(L);
6509 fprem();
6510 fwait(); fnstsw_ax();
6511 #ifdef _LP64
6512 testl(rax, 0x400);
6513 jcc(Assembler::notEqual, L);
6514 #else
6515 sahf();
6516 jcc(Assembler::parity, L);
6517 #endif // _LP64
6518 }
6519 restore_rax(tmp);
6520 // Result is in ST0.
6521 // Note: fxch & fpop to get rid of ST1
6522 // (otherwise FPU stack could overflow eventually)
6523 fxch(1);
6524 fpop();
6525 }
6528 void MacroAssembler::incrementl(AddressLiteral dst) {
6529 if (reachable(dst)) {
6530 incrementl(as_Address(dst));
6531 } else {
6532 lea(rscratch1, dst);
6533 incrementl(Address(rscratch1, 0));
6534 }
6535 }
6537 void MacroAssembler::incrementl(ArrayAddress dst) {
6538 incrementl(as_Address(dst));
6539 }
6541 void MacroAssembler::incrementl(Register reg, int value) {
6542 if (value == min_jint) {addl(reg, value) ; return; }
6543 if (value < 0) { decrementl(reg, -value); return; }
6544 if (value == 0) { ; return; }
6545 if (value == 1 && UseIncDec) { incl(reg) ; return; }
6546 /* else */ { addl(reg, value) ; return; }
6547 }
6549 void MacroAssembler::incrementl(Address dst, int value) {
6550 if (value == min_jint) {addl(dst, value) ; return; }
6551 if (value < 0) { decrementl(dst, -value); return; }
6552 if (value == 0) { ; return; }
6553 if (value == 1 && UseIncDec) { incl(dst) ; return; }
6554 /* else */ { addl(dst, value) ; return; }
6555 }
6557 void MacroAssembler::jump(AddressLiteral dst) {
6558 if (reachable(dst)) {
6559 jmp_literal(dst.target(), dst.rspec());
6560 } else {
6561 lea(rscratch1, dst);
6562 jmp(rscratch1);
6563 }
6564 }
6566 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
6567 if (reachable(dst)) {
6568 InstructionMark im(this);
6569 relocate(dst.reloc());
6570 const int short_size = 2;
6571 const int long_size = 6;
6572 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos);
6573 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
6574 // 0111 tttn #8-bit disp
6575 emit_byte(0x70 | cc);
6576 emit_byte((offs - short_size) & 0xFF);
6577 } else {
6578 // 0000 1111 1000 tttn #32-bit disp
6579 emit_byte(0x0F);
6580 emit_byte(0x80 | cc);
6581 emit_long(offs - long_size);
6582 }
6583 } else {
6584 #ifdef ASSERT
6585 warning("reversing conditional branch");
6586 #endif /* ASSERT */
6587 Label skip;
6588 jccb(reverse[cc], skip);
6589 lea(rscratch1, dst);
6590 Assembler::jmp(rscratch1);
6591 bind(skip);
6592 }
6593 }
6595 void MacroAssembler::ldmxcsr(AddressLiteral src) {
6596 if (reachable(src)) {
6597 Assembler::ldmxcsr(as_Address(src));
6598 } else {
6599 lea(rscratch1, src);
6600 Assembler::ldmxcsr(Address(rscratch1, 0));
6601 }
6602 }
6604 int MacroAssembler::load_signed_byte(Register dst, Address src) {
6605 int off;
6606 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6607 off = offset();
6608 movsbl(dst, src); // movsxb
6609 } else {
6610 off = load_unsigned_byte(dst, src);
6611 shll(dst, 24);
6612 sarl(dst, 24);
6613 }
6614 return off;
6615 }
6617 // Note: load_signed_short used to be called load_signed_word.
6618 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
6619 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
6620 // The term "word" in HotSpot means a 32- or 64-bit machine word.
6621 int MacroAssembler::load_signed_short(Register dst, Address src) {
6622 int off;
6623 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6624 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
6625 // version but this is what 64bit has always done. This seems to imply
6626 // that users are only using 32bits worth.
6627 off = offset();
6628 movswl(dst, src); // movsxw
6629 } else {
6630 off = load_unsigned_short(dst, src);
6631 shll(dst, 16);
6632 sarl(dst, 16);
6633 }
6634 return off;
6635 }
6637 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
6638 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6639 // and "3.9 Partial Register Penalties", p. 22).
6640 int off;
6641 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
6642 off = offset();
6643 movzbl(dst, src); // movzxb
6644 } else {
6645 xorl(dst, dst);
6646 off = offset();
6647 movb(dst, src);
6648 }
6649 return off;
6650 }
6652 // Note: load_unsigned_short used to be called load_unsigned_word.
6653 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
6654 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
6655 // and "3.9 Partial Register Penalties", p. 22).
6656 int off;
6657 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
6658 off = offset();
6659 movzwl(dst, src); // movzxw
6660 } else {
6661 xorl(dst, dst);
6662 off = offset();
6663 movw(dst, src);
6664 }
6665 return off;
6666 }
6668 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
6669 switch (size_in_bytes) {
6670 #ifndef _LP64
6671 case 8:
6672 assert(dst2 != noreg, "second dest register required");
6673 movl(dst, src);
6674 movl(dst2, src.plus_disp(BytesPerInt));
6675 break;
6676 #else
6677 case 8: movq(dst, src); break;
6678 #endif
6679 case 4: movl(dst, src); break;
6680 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
6681 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
6682 default: ShouldNotReachHere();
6683 }
6684 }
6686 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
6687 switch (size_in_bytes) {
6688 #ifndef _LP64
6689 case 8:
6690 assert(src2 != noreg, "second source register required");
6691 movl(dst, src);
6692 movl(dst.plus_disp(BytesPerInt), src2);
6693 break;
6694 #else
6695 case 8: movq(dst, src); break;
6696 #endif
6697 case 4: movl(dst, src); break;
6698 case 2: movw(dst, src); break;
6699 case 1: movb(dst, src); break;
6700 default: ShouldNotReachHere();
6701 }
6702 }
6704 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
6705 if (reachable(dst)) {
6706 movl(as_Address(dst), src);
6707 } else {
6708 lea(rscratch1, dst);
6709 movl(Address(rscratch1, 0), src);
6710 }
6711 }
6713 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
6714 if (reachable(src)) {
6715 movl(dst, as_Address(src));
6716 } else {
6717 lea(rscratch1, src);
6718 movl(dst, Address(rscratch1, 0));
6719 }
6720 }
6722 // C++ bool manipulation
6724 void MacroAssembler::movbool(Register dst, Address src) {
6725 if(sizeof(bool) == 1)
6726 movb(dst, src);
6727 else if(sizeof(bool) == 2)
6728 movw(dst, src);
6729 else if(sizeof(bool) == 4)
6730 movl(dst, src);
6731 else
6732 // unsupported
6733 ShouldNotReachHere();
6734 }
6736 void MacroAssembler::movbool(Address dst, bool boolconst) {
6737 if(sizeof(bool) == 1)
6738 movb(dst, (int) boolconst);
6739 else if(sizeof(bool) == 2)
6740 movw(dst, (int) boolconst);
6741 else if(sizeof(bool) == 4)
6742 movl(dst, (int) boolconst);
6743 else
6744 // unsupported
6745 ShouldNotReachHere();
6746 }
6748 void MacroAssembler::movbool(Address dst, Register src) {
6749 if(sizeof(bool) == 1)
6750 movb(dst, src);
6751 else if(sizeof(bool) == 2)
6752 movw(dst, src);
6753 else if(sizeof(bool) == 4)
6754 movl(dst, src);
6755 else
6756 // unsupported
6757 ShouldNotReachHere();
6758 }
6760 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
6761 movb(as_Address(dst), src);
6762 }
6764 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
6765 if (reachable(src)) {
6766 if (UseXmmLoadAndClearUpper) {
6767 movsd (dst, as_Address(src));
6768 } else {
6769 movlpd(dst, as_Address(src));
6770 }
6771 } else {
6772 lea(rscratch1, src);
6773 if (UseXmmLoadAndClearUpper) {
6774 movsd (dst, Address(rscratch1, 0));
6775 } else {
6776 movlpd(dst, Address(rscratch1, 0));
6777 }
6778 }
6779 }
6781 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
6782 if (reachable(src)) {
6783 movss(dst, as_Address(src));
6784 } else {
6785 lea(rscratch1, src);
6786 movss(dst, Address(rscratch1, 0));
6787 }
6788 }
6790 void MacroAssembler::movptr(Register dst, Register src) {
6791 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6792 }
6794 void MacroAssembler::movptr(Register dst, Address src) {
6795 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6796 }
6798 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
6799 void MacroAssembler::movptr(Register dst, intptr_t src) {
6800 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
6801 }
6803 void MacroAssembler::movptr(Address dst, Register src) {
6804 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
6805 }
6807 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
6808 if (reachable(src)) {
6809 movss(dst, as_Address(src));
6810 } else {
6811 lea(rscratch1, src);
6812 movss(dst, Address(rscratch1, 0));
6813 }
6814 }
6816 void MacroAssembler::null_check(Register reg, int offset) {
6817 if (needs_explicit_null_check(offset)) {
6818 // provoke OS NULL exception if reg = NULL by
6819 // accessing M[reg] w/o changing any (non-CC) registers
6820 // NOTE: cmpl is plenty here to provoke a segv
6821 cmpptr(rax, Address(reg, 0));
6822 // Note: should probably use testl(rax, Address(reg, 0));
6823 // may be shorter code (however, this version of
6824 // testl needs to be implemented first)
6825 } else {
6826 // nothing to do, (later) access of M[reg + offset]
6827 // will provoke OS NULL exception if reg = NULL
6828 }
6829 }
6831 void MacroAssembler::os_breakpoint() {
6832 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
6833 // (e.g., MSVC can't call ps() otherwise)
6834 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
6835 }
6837 void MacroAssembler::pop_CPU_state() {
6838 pop_FPU_state();
6839 pop_IU_state();
6840 }
6842 void MacroAssembler::pop_FPU_state() {
6843 NOT_LP64(frstor(Address(rsp, 0));)
6844 LP64_ONLY(fxrstor(Address(rsp, 0));)
6845 addptr(rsp, FPUStateSizeInWords * wordSize);
6846 }
6848 void MacroAssembler::pop_IU_state() {
6849 popa();
6850 LP64_ONLY(addq(rsp, 8));
6851 popf();
6852 }
6854 // Save Integer and Float state
6855 // Warning: Stack must be 16 byte aligned (64bit)
6856 void MacroAssembler::push_CPU_state() {
6857 push_IU_state();
6858 push_FPU_state();
6859 }
6861 void MacroAssembler::push_FPU_state() {
6862 subptr(rsp, FPUStateSizeInWords * wordSize);
6863 #ifndef _LP64
6864 fnsave(Address(rsp, 0));
6865 fwait();
6866 #else
6867 fxsave(Address(rsp, 0));
6868 #endif // LP64
6869 }
6871 void MacroAssembler::push_IU_state() {
6872 // Push flags first because pusha kills them
6873 pushf();
6874 // Make sure rsp stays 16-byte aligned
6875 LP64_ONLY(subq(rsp, 8));
6876 pusha();
6877 }
6879 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
6880 // determine java_thread register
6881 if (!java_thread->is_valid()) {
6882 java_thread = rdi;
6883 get_thread(java_thread);
6884 }
6885 // we must set sp to zero to clear frame
6886 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
6887 if (clear_fp) {
6888 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
6889 }
6891 if (clear_pc)
6892 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
6894 }
6896 void MacroAssembler::restore_rax(Register tmp) {
6897 if (tmp == noreg) pop(rax);
6898 else if (tmp != rax) mov(rax, tmp);
6899 }
6901 void MacroAssembler::round_to(Register reg, int modulus) {
6902 addptr(reg, modulus - 1);
6903 andptr(reg, -modulus);
6904 }
6906 void MacroAssembler::save_rax(Register tmp) {
6907 if (tmp == noreg) push(rax);
6908 else if (tmp != rax) mov(tmp, rax);
6909 }
6911 // Write serialization page so VM thread can do a pseudo remote membar.
6912 // We use the current thread pointer to calculate a thread specific
6913 // offset to write to within the page. This minimizes bus traffic
6914 // due to cache line collision.
6915 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
6916 movl(tmp, thread);
6917 shrl(tmp, os::get_serialize_page_shift_count());
6918 andl(tmp, (os::vm_page_size() - sizeof(int)));
6920 Address index(noreg, tmp, Address::times_1);
6921 ExternalAddress page(os::get_memory_serialize_page());
6923 // Size of store must match masking code above
6924 movl(as_Address(ArrayAddress(page, index)), tmp);
6925 }
6927 // Calls to C land
6928 //
6929 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
6930 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
6931 // has to be reset to 0. This is required to allow proper stack traversal.
6932 void MacroAssembler::set_last_Java_frame(Register java_thread,
6933 Register last_java_sp,
6934 Register last_java_fp,
6935 address last_java_pc) {
6936 // determine java_thread register
6937 if (!java_thread->is_valid()) {
6938 java_thread = rdi;
6939 get_thread(java_thread);
6940 }
6941 // determine last_java_sp register
6942 if (!last_java_sp->is_valid()) {
6943 last_java_sp = rsp;
6944 }
6946 // last_java_fp is optional
6948 if (last_java_fp->is_valid()) {
6949 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
6950 }
6952 // last_java_pc is optional
6954 if (last_java_pc != NULL) {
6955 lea(Address(java_thread,
6956 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
6957 InternalAddress(last_java_pc));
6959 }
6960 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
6961 }
6963 void MacroAssembler::shlptr(Register dst, int imm8) {
6964 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
6965 }
6967 void MacroAssembler::shrptr(Register dst, int imm8) {
6968 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
6969 }
6971 void MacroAssembler::sign_extend_byte(Register reg) {
6972 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
6973 movsbl(reg, reg); // movsxb
6974 } else {
6975 shll(reg, 24);
6976 sarl(reg, 24);
6977 }
6978 }
6980 void MacroAssembler::sign_extend_short(Register reg) {
6981 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
6982 movswl(reg, reg); // movsxw
6983 } else {
6984 shll(reg, 16);
6985 sarl(reg, 16);
6986 }
6987 }
6989 void MacroAssembler::testl(Register dst, AddressLiteral src) {
6990 assert(reachable(src), "Address should be reachable");
6991 testl(dst, as_Address(src));
6992 }
6994 //////////////////////////////////////////////////////////////////////////////////
6995 #ifndef SERIALGC
6997 void MacroAssembler::g1_write_barrier_pre(Register obj,
6998 Register pre_val,
6999 Register thread,
7000 Register tmp,
7001 bool tosca_live,
7002 bool expand_call) {
7004 // If expand_call is true then we expand the call_VM_leaf macro
7005 // directly to skip generating the check by
7006 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
7008 #ifdef _LP64
7009 assert(thread == r15_thread, "must be");
7010 #endif // _LP64
7012 Label done;
7013 Label runtime;
7015 assert(pre_val != noreg, "check this code");
7017 if (obj != noreg) {
7018 assert_different_registers(obj, pre_val, tmp);
7019 assert(pre_val != rax, "check this code");
7020 }
7022 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
7023 PtrQueue::byte_offset_of_active()));
7024 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
7025 PtrQueue::byte_offset_of_index()));
7026 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
7027 PtrQueue::byte_offset_of_buf()));
7030 // Is marking active?
7031 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
7032 cmpl(in_progress, 0);
7033 } else {
7034 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
7035 cmpb(in_progress, 0);
7036 }
7037 jcc(Assembler::equal, done);
7039 // Do we need to load the previous value?
7040 if (obj != noreg) {
7041 load_heap_oop(pre_val, Address(obj, 0));
7042 }
7044 // Is the previous value null?
7045 cmpptr(pre_val, (int32_t) NULL_WORD);
7046 jcc(Assembler::equal, done);
7048 // Can we store original value in the thread's buffer?
7049 // Is index == 0?
7050 // (The index field is typed as size_t.)
7052 movptr(tmp, index); // tmp := *index_adr
7053 cmpptr(tmp, 0); // tmp == 0?
7054 jcc(Assembler::equal, runtime); // If yes, goto runtime
7056 subptr(tmp, wordSize); // tmp := tmp - wordSize
7057 movptr(index, tmp); // *index_adr := tmp
7058 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
7060 // Record the previous value
7061 movptr(Address(tmp, 0), pre_val);
7062 jmp(done);
7064 bind(runtime);
7065 // save the live input values
7066 if(tosca_live) push(rax);
7068 if (obj != noreg && obj != rax)
7069 push(obj);
7071 if (pre_val != rax)
7072 push(pre_val);
7074 // Calling the runtime using the regular call_VM_leaf mechanism generates
7075 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
7076 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
7077 //
7078 // If we care generating the pre-barrier without a frame (e.g. in the
7079 // intrinsified Reference.get() routine) then ebp might be pointing to
7080 // the caller frame and so this check will most likely fail at runtime.
7081 //
7082 // Expanding the call directly bypasses the generation of the check.
7083 // So when we do not have have a full interpreter frame on the stack
7084 // expand_call should be passed true.
7086 NOT_LP64( push(thread); )
7088 if (expand_call) {
7089 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
7090 pass_arg1(this, thread);
7091 pass_arg0(this, pre_val);
7092 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
7093 } else {
7094 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
7095 }
7097 NOT_LP64( pop(thread); )
7099 // save the live input values
7100 if (pre_val != rax)
7101 pop(pre_val);
7103 if (obj != noreg && obj != rax)
7104 pop(obj);
7106 if(tosca_live) pop(rax);
7108 bind(done);
7109 }
7111 void MacroAssembler::g1_write_barrier_post(Register store_addr,
7112 Register new_val,
7113 Register thread,
7114 Register tmp,
7115 Register tmp2) {
7116 #ifdef _LP64
7117 assert(thread == r15_thread, "must be");
7118 #endif // _LP64
7120 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
7121 PtrQueue::byte_offset_of_index()));
7122 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
7123 PtrQueue::byte_offset_of_buf()));
7125 BarrierSet* bs = Universe::heap()->barrier_set();
7126 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
7127 Label done;
7128 Label runtime;
7130 // Does store cross heap regions?
7132 movptr(tmp, store_addr);
7133 xorptr(tmp, new_val);
7134 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
7135 jcc(Assembler::equal, done);
7137 // crosses regions, storing NULL?
7139 cmpptr(new_val, (int32_t) NULL_WORD);
7140 jcc(Assembler::equal, done);
7142 // storing region crossing non-NULL, is card already dirty?
7144 ExternalAddress cardtable((address) ct->byte_map_base);
7145 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
7146 #ifdef _LP64
7147 const Register card_addr = tmp;
7149 movq(card_addr, store_addr);
7150 shrq(card_addr, CardTableModRefBS::card_shift);
7152 lea(tmp2, cardtable);
7154 // get the address of the card
7155 addq(card_addr, tmp2);
7156 #else
7157 const Register card_index = tmp;
7159 movl(card_index, store_addr);
7160 shrl(card_index, CardTableModRefBS::card_shift);
7162 Address index(noreg, card_index, Address::times_1);
7163 const Register card_addr = tmp;
7164 lea(card_addr, as_Address(ArrayAddress(cardtable, index)));
7165 #endif
7166 cmpb(Address(card_addr, 0), 0);
7167 jcc(Assembler::equal, done);
7169 // storing a region crossing, non-NULL oop, card is clean.
7170 // dirty card and log.
7172 movb(Address(card_addr, 0), 0);
7174 cmpl(queue_index, 0);
7175 jcc(Assembler::equal, runtime);
7176 subl(queue_index, wordSize);
7177 movptr(tmp2, buffer);
7178 #ifdef _LP64
7179 movslq(rscratch1, queue_index);
7180 addq(tmp2, rscratch1);
7181 movq(Address(tmp2, 0), card_addr);
7182 #else
7183 addl(tmp2, queue_index);
7184 movl(Address(tmp2, 0), card_index);
7185 #endif
7186 jmp(done);
7188 bind(runtime);
7189 // save the live input values
7190 push(store_addr);
7191 push(new_val);
7192 #ifdef _LP64
7193 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
7194 #else
7195 push(thread);
7196 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
7197 pop(thread);
7198 #endif
7199 pop(new_val);
7200 pop(store_addr);
7202 bind(done);
7203 }
7205 #endif // SERIALGC
7206 //////////////////////////////////////////////////////////////////////////////////
7209 void MacroAssembler::store_check(Register obj) {
7210 // Does a store check for the oop in register obj. The content of
7211 // register obj is destroyed afterwards.
7212 store_check_part_1(obj);
7213 store_check_part_2(obj);
7214 }
7216 void MacroAssembler::store_check(Register obj, Address dst) {
7217 store_check(obj);
7218 }
7221 // split the store check operation so that other instructions can be scheduled inbetween
7222 void MacroAssembler::store_check_part_1(Register obj) {
7223 BarrierSet* bs = Universe::heap()->barrier_set();
7224 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7225 shrptr(obj, CardTableModRefBS::card_shift);
7226 }
7228 void MacroAssembler::store_check_part_2(Register obj) {
7229 BarrierSet* bs = Universe::heap()->barrier_set();
7230 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
7231 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
7232 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
7234 // The calculation for byte_map_base is as follows:
7235 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
7236 // So this essentially converts an address to a displacement and
7237 // it will never need to be relocated. On 64bit however the value may be too
7238 // large for a 32bit displacement
7240 intptr_t disp = (intptr_t) ct->byte_map_base;
7241 if (is_simm32(disp)) {
7242 Address cardtable(noreg, obj, Address::times_1, disp);
7243 movb(cardtable, 0);
7244 } else {
7245 // By doing it as an ExternalAddress disp could be converted to a rip-relative
7246 // displacement and done in a single instruction given favorable mapping and
7247 // a smarter version of as_Address. Worst case it is two instructions which
7248 // is no worse off then loading disp into a register and doing as a simple
7249 // Address() as above.
7250 // We can't do as ExternalAddress as the only style since if disp == 0 we'll
7251 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case
7252 // in some cases we'll get a single instruction version.
7254 ExternalAddress cardtable((address)disp);
7255 Address index(noreg, obj, Address::times_1);
7256 movb(as_Address(ArrayAddress(cardtable, index)), 0);
7257 }
7258 }
7260 void MacroAssembler::subptr(Register dst, int32_t imm32) {
7261 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
7262 }
7264 void MacroAssembler::subptr(Register dst, Register src) {
7265 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
7266 }
7268 // C++ bool manipulation
7269 void MacroAssembler::testbool(Register dst) {
7270 if(sizeof(bool) == 1)
7271 testb(dst, 0xff);
7272 else if(sizeof(bool) == 2) {
7273 // testw implementation needed for two byte bools
7274 ShouldNotReachHere();
7275 } else if(sizeof(bool) == 4)
7276 testl(dst, dst);
7277 else
7278 // unsupported
7279 ShouldNotReachHere();
7280 }
7282 void MacroAssembler::testptr(Register dst, Register src) {
7283 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
7284 }
7286 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
7287 void MacroAssembler::tlab_allocate(Register obj,
7288 Register var_size_in_bytes,
7289 int con_size_in_bytes,
7290 Register t1,
7291 Register t2,
7292 Label& slow_case) {
7293 assert_different_registers(obj, t1, t2);
7294 assert_different_registers(obj, var_size_in_bytes, t1);
7295 Register end = t2;
7296 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
7298 verify_tlab();
7300 NOT_LP64(get_thread(thread));
7302 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
7303 if (var_size_in_bytes == noreg) {
7304 lea(end, Address(obj, con_size_in_bytes));
7305 } else {
7306 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
7307 }
7308 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
7309 jcc(Assembler::above, slow_case);
7311 // update the tlab top pointer
7312 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
7314 // recover var_size_in_bytes if necessary
7315 if (var_size_in_bytes == end) {
7316 subptr(var_size_in_bytes, obj);
7317 }
7318 verify_tlab();
7319 }
7321 // Preserves rbx, and rdx.
7322 Register MacroAssembler::tlab_refill(Label& retry,
7323 Label& try_eden,
7324 Label& slow_case) {
7325 Register top = rax;
7326 Register t1 = rcx;
7327 Register t2 = rsi;
7328 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
7329 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
7330 Label do_refill, discard_tlab;
7332 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
7333 // No allocation in the shared eden.
7334 jmp(slow_case);
7335 }
7337 NOT_LP64(get_thread(thread_reg));
7339 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
7340 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
7342 // calculate amount of free space
7343 subptr(t1, top);
7344 shrptr(t1, LogHeapWordSize);
7346 // Retain tlab and allocate object in shared space if
7347 // the amount free in the tlab is too large to discard.
7348 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
7349 jcc(Assembler::lessEqual, discard_tlab);
7351 // Retain
7352 // %%% yuck as movptr...
7353 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
7354 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
7355 if (TLABStats) {
7356 // increment number of slow_allocations
7357 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
7358 }
7359 jmp(try_eden);
7361 bind(discard_tlab);
7362 if (TLABStats) {
7363 // increment number of refills
7364 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
7365 // accumulate wastage -- t1 is amount free in tlab
7366 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
7367 }
7369 // if tlab is currently allocated (top or end != null) then
7370 // fill [top, end + alignment_reserve) with array object
7371 testptr(top, top);
7372 jcc(Assembler::zero, do_refill);
7374 // set up the mark word
7375 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
7376 // set the length to the remaining space
7377 subptr(t1, typeArrayOopDesc::header_size(T_INT));
7378 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
7379 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
7380 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
7381 // set klass to intArrayKlass
7382 // dubious reloc why not an oop reloc?
7383 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
7384 // store klass last. concurrent gcs assumes klass length is valid if
7385 // klass field is not null.
7386 store_klass(top, t1);
7388 movptr(t1, top);
7389 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
7390 incr_allocated_bytes(thread_reg, t1, 0);
7392 // refill the tlab with an eden allocation
7393 bind(do_refill);
7394 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7395 shlptr(t1, LogHeapWordSize);
7396 // allocate new tlab, address returned in top
7397 eden_allocate(top, t1, 0, t2, slow_case);
7399 // Check that t1 was preserved in eden_allocate.
7400 #ifdef ASSERT
7401 if (UseTLAB) {
7402 Label ok;
7403 Register tsize = rsi;
7404 assert_different_registers(tsize, thread_reg, t1);
7405 push(tsize);
7406 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
7407 shlptr(tsize, LogHeapWordSize);
7408 cmpptr(t1, tsize);
7409 jcc(Assembler::equal, ok);
7410 stop("assert(t1 != tlab size)");
7411 should_not_reach_here();
7413 bind(ok);
7414 pop(tsize);
7415 }
7416 #endif
7417 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
7418 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
7419 addptr(top, t1);
7420 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
7421 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
7422 verify_tlab();
7423 jmp(retry);
7425 return thread_reg; // for use by caller
7426 }
7428 void MacroAssembler::incr_allocated_bytes(Register thread,
7429 Register var_size_in_bytes,
7430 int con_size_in_bytes,
7431 Register t1) {
7432 #ifdef _LP64
7433 if (var_size_in_bytes->is_valid()) {
7434 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
7435 } else {
7436 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
7437 }
7438 #else
7439 if (!thread->is_valid()) {
7440 assert(t1->is_valid(), "need temp reg");
7441 thread = t1;
7442 get_thread(thread);
7443 }
7445 if (var_size_in_bytes->is_valid()) {
7446 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
7447 } else {
7448 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
7449 }
7450 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
7451 #endif
7452 }
7454 static const double pi_4 = 0.7853981633974483;
7456 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
7457 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
7458 // was attempted in this code; unfortunately it appears that the
7459 // switch to 80-bit precision and back causes this to be
7460 // unprofitable compared with simply performing a runtime call if
7461 // the argument is out of the (-pi/4, pi/4) range.
7463 Register tmp = noreg;
7464 if (!VM_Version::supports_cmov()) {
7465 // fcmp needs a temporary so preserve rbx,
7466 tmp = rbx;
7467 push(tmp);
7468 }
7470 Label slow_case, done;
7472 ExternalAddress pi4_adr = (address)&pi_4;
7473 if (reachable(pi4_adr)) {
7474 // x ?<= pi/4
7475 fld_d(pi4_adr);
7476 fld_s(1); // Stack: X PI/4 X
7477 fabs(); // Stack: |X| PI/4 X
7478 fcmp(tmp);
7479 jcc(Assembler::above, slow_case);
7481 // fastest case: -pi/4 <= x <= pi/4
7482 switch(trig) {
7483 case 's':
7484 fsin();
7485 break;
7486 case 'c':
7487 fcos();
7488 break;
7489 case 't':
7490 ftan();
7491 break;
7492 default:
7493 assert(false, "bad intrinsic");
7494 break;
7495 }
7496 jmp(done);
7497 }
7499 // slow case: runtime call
7500 bind(slow_case);
7501 // Preserve registers across runtime call
7502 pusha();
7503 int incoming_argument_and_return_value_offset = -1;
7504 if (num_fpu_regs_in_use > 1) {
7505 // Must preserve all other FPU regs (could alternatively convert
7506 // SharedRuntime::dsin and dcos into assembly routines known not to trash
7507 // FPU state, but can not trust C compiler)
7508 NEEDS_CLEANUP;
7509 // NOTE that in this case we also push the incoming argument to
7510 // the stack and restore it later; we also use this stack slot to
7511 // hold the return value from dsin or dcos.
7512 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7513 subptr(rsp, sizeof(jdouble));
7514 fstp_d(Address(rsp, 0));
7515 }
7516 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
7517 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
7518 }
7519 subptr(rsp, sizeof(jdouble));
7520 fstp_d(Address(rsp, 0));
7521 #ifdef _LP64
7522 movdbl(xmm0, Address(rsp, 0));
7523 #endif // _LP64
7525 // NOTE: we must not use call_VM_leaf here because that requires a
7526 // complete interpreter frame in debug mode -- same bug as 4387334
7527 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
7528 // do proper 64bit abi
7530 NEEDS_CLEANUP;
7531 // Need to add stack banging before this runtime call if it needs to
7532 // be taken; however, there is no generic stack banging routine at
7533 // the MacroAssembler level
7534 switch(trig) {
7535 case 's':
7536 {
7537 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0);
7538 }
7539 break;
7540 case 'c':
7541 {
7542 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0);
7543 }
7544 break;
7545 case 't':
7546 {
7547 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0);
7548 }
7549 break;
7550 default:
7551 assert(false, "bad intrinsic");
7552 break;
7553 }
7554 #ifdef _LP64
7555 movsd(Address(rsp, 0), xmm0);
7556 fld_d(Address(rsp, 0));
7557 #endif // _LP64
7558 addptr(rsp, sizeof(jdouble));
7559 if (num_fpu_regs_in_use > 1) {
7560 // Must save return value to stack and then restore entire FPU stack
7561 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
7562 for (int i = 0; i < num_fpu_regs_in_use; i++) {
7563 fld_d(Address(rsp, 0));
7564 addptr(rsp, sizeof(jdouble));
7565 }
7566 }
7567 popa();
7569 // Come here with result in F-TOS
7570 bind(done);
7572 if (tmp != noreg) {
7573 pop(tmp);
7574 }
7575 }
7578 // Look up the method for a megamorphic invokeinterface call.
7579 // The target method is determined by <intf_klass, itable_index>.
7580 // The receiver klass is in recv_klass.
7581 // On success, the result will be in method_result, and execution falls through.
7582 // On failure, execution transfers to the given label.
7583 void MacroAssembler::lookup_interface_method(Register recv_klass,
7584 Register intf_klass,
7585 RegisterOrConstant itable_index,
7586 Register method_result,
7587 Register scan_temp,
7588 Label& L_no_such_interface) {
7589 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
7590 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
7591 "caller must use same register for non-constant itable index as for method");
7593 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
7594 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
7595 int itentry_off = itableMethodEntry::method_offset_in_bytes();
7596 int scan_step = itableOffsetEntry::size() * wordSize;
7597 int vte_size = vtableEntry::size() * wordSize;
7598 Address::ScaleFactor times_vte_scale = Address::times_ptr;
7599 assert(vte_size == wordSize, "else adjust times_vte_scale");
7601 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize));
7603 // %%% Could store the aligned, prescaled offset in the klassoop.
7604 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
7605 if (HeapWordsPerLong > 1) {
7606 // Round up to align_object_offset boundary
7607 // see code for instanceKlass::start_of_itable!
7608 round_to(scan_temp, BytesPerLong);
7609 }
7611 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
7612 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
7613 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
7615 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
7616 // if (scan->interface() == intf) {
7617 // result = (klass + scan->offset() + itable_index);
7618 // }
7619 // }
7620 Label search, found_method;
7622 for (int peel = 1; peel >= 0; peel--) {
7623 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
7624 cmpptr(intf_klass, method_result);
7626 if (peel) {
7627 jccb(Assembler::equal, found_method);
7628 } else {
7629 jccb(Assembler::notEqual, search);
7630 // (invert the test to fall through to found_method...)
7631 }
7633 if (!peel) break;
7635 bind(search);
7637 // Check that the previous entry is non-null. A null entry means that
7638 // the receiver class doesn't implement the interface, and wasn't the
7639 // same as when the caller was compiled.
7640 testptr(method_result, method_result);
7641 jcc(Assembler::zero, L_no_such_interface);
7642 addptr(scan_temp, scan_step);
7643 }
7645 bind(found_method);
7647 // Got a hit.
7648 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
7649 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
7650 }
7653 void MacroAssembler::check_klass_subtype(Register sub_klass,
7654 Register super_klass,
7655 Register temp_reg,
7656 Label& L_success) {
7657 Label L_failure;
7658 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
7659 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
7660 bind(L_failure);
7661 }
7664 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
7665 Register super_klass,
7666 Register temp_reg,
7667 Label* L_success,
7668 Label* L_failure,
7669 Label* L_slow_path,
7670 RegisterOrConstant super_check_offset) {
7671 assert_different_registers(sub_klass, super_klass, temp_reg);
7672 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
7673 if (super_check_offset.is_register()) {
7674 assert_different_registers(sub_klass, super_klass,
7675 super_check_offset.as_register());
7676 } else if (must_load_sco) {
7677 assert(temp_reg != noreg, "supply either a temp or a register offset");
7678 }
7680 Label L_fallthrough;
7681 int label_nulls = 0;
7682 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7683 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7684 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
7685 assert(label_nulls <= 1, "at most one NULL in the batch");
7687 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7688 Klass::secondary_super_cache_offset_in_bytes());
7689 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
7690 Klass::super_check_offset_offset_in_bytes());
7691 Address super_check_offset_addr(super_klass, sco_offset);
7693 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
7694 // range of a jccb. If this routine grows larger, reconsider at
7695 // least some of these.
7696 #define local_jcc(assembler_cond, label) \
7697 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
7698 else jcc( assembler_cond, label) /*omit semi*/
7700 // Hacked jmp, which may only be used just before L_fallthrough.
7701 #define final_jmp(label) \
7702 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
7703 else jmp(label) /*omit semi*/
7705 // If the pointers are equal, we are done (e.g., String[] elements).
7706 // This self-check enables sharing of secondary supertype arrays among
7707 // non-primary types such as array-of-interface. Otherwise, each such
7708 // type would need its own customized SSA.
7709 // We move this check to the front of the fast path because many
7710 // type checks are in fact trivially successful in this manner,
7711 // so we get a nicely predicted branch right at the start of the check.
7712 cmpptr(sub_klass, super_klass);
7713 local_jcc(Assembler::equal, *L_success);
7715 // Check the supertype display:
7716 if (must_load_sco) {
7717 // Positive movl does right thing on LP64.
7718 movl(temp_reg, super_check_offset_addr);
7719 super_check_offset = RegisterOrConstant(temp_reg);
7720 }
7721 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
7722 cmpptr(super_klass, super_check_addr); // load displayed supertype
7724 // This check has worked decisively for primary supers.
7725 // Secondary supers are sought in the super_cache ('super_cache_addr').
7726 // (Secondary supers are interfaces and very deeply nested subtypes.)
7727 // This works in the same check above because of a tricky aliasing
7728 // between the super_cache and the primary super display elements.
7729 // (The 'super_check_addr' can address either, as the case requires.)
7730 // Note that the cache is updated below if it does not help us find
7731 // what we need immediately.
7732 // So if it was a primary super, we can just fail immediately.
7733 // Otherwise, it's the slow path for us (no success at this point).
7735 if (super_check_offset.is_register()) {
7736 local_jcc(Assembler::equal, *L_success);
7737 cmpl(super_check_offset.as_register(), sc_offset);
7738 if (L_failure == &L_fallthrough) {
7739 local_jcc(Assembler::equal, *L_slow_path);
7740 } else {
7741 local_jcc(Assembler::notEqual, *L_failure);
7742 final_jmp(*L_slow_path);
7743 }
7744 } else if (super_check_offset.as_constant() == sc_offset) {
7745 // Need a slow path; fast failure is impossible.
7746 if (L_slow_path == &L_fallthrough) {
7747 local_jcc(Assembler::equal, *L_success);
7748 } else {
7749 local_jcc(Assembler::notEqual, *L_slow_path);
7750 final_jmp(*L_success);
7751 }
7752 } else {
7753 // No slow path; it's a fast decision.
7754 if (L_failure == &L_fallthrough) {
7755 local_jcc(Assembler::equal, *L_success);
7756 } else {
7757 local_jcc(Assembler::notEqual, *L_failure);
7758 final_jmp(*L_success);
7759 }
7760 }
7762 bind(L_fallthrough);
7764 #undef local_jcc
7765 #undef final_jmp
7766 }
7769 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
7770 Register super_klass,
7771 Register temp_reg,
7772 Register temp2_reg,
7773 Label* L_success,
7774 Label* L_failure,
7775 bool set_cond_codes) {
7776 assert_different_registers(sub_klass, super_klass, temp_reg);
7777 if (temp2_reg != noreg)
7778 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
7779 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
7781 Label L_fallthrough;
7782 int label_nulls = 0;
7783 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
7784 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
7785 assert(label_nulls <= 1, "at most one NULL in the batch");
7787 // a couple of useful fields in sub_klass:
7788 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
7789 Klass::secondary_supers_offset_in_bytes());
7790 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
7791 Klass::secondary_super_cache_offset_in_bytes());
7792 Address secondary_supers_addr(sub_klass, ss_offset);
7793 Address super_cache_addr( sub_klass, sc_offset);
7795 // Do a linear scan of the secondary super-klass chain.
7796 // This code is rarely used, so simplicity is a virtue here.
7797 // The repne_scan instruction uses fixed registers, which we must spill.
7798 // Don't worry too much about pre-existing connections with the input regs.
7800 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
7801 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
7803 // Get super_klass value into rax (even if it was in rdi or rcx).
7804 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
7805 if (super_klass != rax || UseCompressedOops) {
7806 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
7807 mov(rax, super_klass);
7808 }
7809 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
7810 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
7812 #ifndef PRODUCT
7813 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
7814 ExternalAddress pst_counter_addr((address) pst_counter);
7815 NOT_LP64( incrementl(pst_counter_addr) );
7816 LP64_ONLY( lea(rcx, pst_counter_addr) );
7817 LP64_ONLY( incrementl(Address(rcx, 0)) );
7818 #endif //PRODUCT
7820 // We will consult the secondary-super array.
7821 movptr(rdi, secondary_supers_addr);
7822 // Load the array length. (Positive movl does right thing on LP64.)
7823 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
7824 // Skip to start of data.
7825 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
7827 // Scan RCX words at [RDI] for an occurrence of RAX.
7828 // Set NZ/Z based on last compare.
7829 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
7830 // not change flags (only scas instruction which is repeated sets flags).
7831 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
7832 #ifdef _LP64
7833 // This part is tricky, as values in supers array could be 32 or 64 bit wide
7834 // and we store values in objArrays always encoded, thus we need to encode
7835 // the value of rax before repne. Note that rax is dead after the repne.
7836 if (UseCompressedOops) {
7837 encode_heap_oop_not_null(rax); // Changes flags.
7838 // The superclass is never null; it would be a basic system error if a null
7839 // pointer were to sneak in here. Note that we have already loaded the
7840 // Klass::super_check_offset from the super_klass in the fast path,
7841 // so if there is a null in that register, we are already in the afterlife.
7842 testl(rax,rax); // Set Z = 0
7843 repne_scanl();
7844 } else
7845 #endif // _LP64
7846 {
7847 testptr(rax,rax); // Set Z = 0
7848 repne_scan();
7849 }
7850 // Unspill the temp. registers:
7851 if (pushed_rdi) pop(rdi);
7852 if (pushed_rcx) pop(rcx);
7853 if (pushed_rax) pop(rax);
7855 if (set_cond_codes) {
7856 // Special hack for the AD files: rdi is guaranteed non-zero.
7857 assert(!pushed_rdi, "rdi must be left non-NULL");
7858 // Also, the condition codes are properly set Z/NZ on succeed/failure.
7859 }
7861 if (L_failure == &L_fallthrough)
7862 jccb(Assembler::notEqual, *L_failure);
7863 else jcc(Assembler::notEqual, *L_failure);
7865 // Success. Cache the super we found and proceed in triumph.
7866 movptr(super_cache_addr, super_klass);
7868 if (L_success != &L_fallthrough) {
7869 jmp(*L_success);
7870 }
7872 #undef IS_A_TEMP
7874 bind(L_fallthrough);
7875 }
7878 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
7879 ucomisd(dst, as_Address(src));
7880 }
7882 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
7883 ucomiss(dst, as_Address(src));
7884 }
7886 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
7887 if (reachable(src)) {
7888 xorpd(dst, as_Address(src));
7889 } else {
7890 lea(rscratch1, src);
7891 xorpd(dst, Address(rscratch1, 0));
7892 }
7893 }
7895 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
7896 if (reachable(src)) {
7897 xorps(dst, as_Address(src));
7898 } else {
7899 lea(rscratch1, src);
7900 xorps(dst, Address(rscratch1, 0));
7901 }
7902 }
7904 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
7905 if (VM_Version::supports_cmov()) {
7906 cmovl(cc, dst, src);
7907 } else {
7908 Label L;
7909 jccb(negate_condition(cc), L);
7910 movl(dst, src);
7911 bind(L);
7912 }
7913 }
7915 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
7916 if (VM_Version::supports_cmov()) {
7917 cmovl(cc, dst, src);
7918 } else {
7919 Label L;
7920 jccb(negate_condition(cc), L);
7921 movl(dst, src);
7922 bind(L);
7923 }
7924 }
7926 void MacroAssembler::verify_oop(Register reg, const char* s) {
7927 if (!VerifyOops) return;
7929 // Pass register number to verify_oop_subroutine
7930 char* b = new char[strlen(s) + 50];
7931 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
7932 #ifdef _LP64
7933 push(rscratch1); // save r10, trashed by movptr()
7934 #endif
7935 push(rax); // save rax,
7936 push(reg); // pass register argument
7937 ExternalAddress buffer((address) b);
7938 // avoid using pushptr, as it modifies scratch registers
7939 // and our contract is not to modify anything
7940 movptr(rax, buffer.addr());
7941 push(rax);
7942 // call indirectly to solve generation ordering problem
7943 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
7944 call(rax);
7945 // Caller pops the arguments (oop, message) and restores rax, r10
7946 }
7949 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
7950 Register tmp,
7951 int offset) {
7952 intptr_t value = *delayed_value_addr;
7953 if (value != 0)
7954 return RegisterOrConstant(value + offset);
7956 // load indirectly to solve generation ordering problem
7957 movptr(tmp, ExternalAddress((address) delayed_value_addr));
7959 #ifdef ASSERT
7960 { Label L;
7961 testptr(tmp, tmp);
7962 if (WizardMode) {
7963 jcc(Assembler::notZero, L);
7964 char* buf = new char[40];
7965 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
7966 stop(buf);
7967 } else {
7968 jccb(Assembler::notZero, L);
7969 hlt();
7970 }
7971 bind(L);
7972 }
7973 #endif
7975 if (offset != 0)
7976 addptr(tmp, offset);
7978 return RegisterOrConstant(tmp);
7979 }
7982 // registers on entry:
7983 // - rax ('check' register): required MethodType
7984 // - rcx: method handle
7985 // - rdx, rsi, or ?: killable temp
7986 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
7987 Register temp_reg,
7988 Label& wrong_method_type) {
7989 Address type_addr(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg));
7990 // compare method type against that of the receiver
7991 if (UseCompressedOops) {
7992 load_heap_oop(temp_reg, type_addr);
7993 cmpptr(mtype_reg, temp_reg);
7994 } else {
7995 cmpptr(mtype_reg, type_addr);
7996 }
7997 jcc(Assembler::notEqual, wrong_method_type);
7998 }
8001 // A method handle has a "vmslots" field which gives the size of its
8002 // argument list in JVM stack slots. This field is either located directly
8003 // in every method handle, or else is indirectly accessed through the
8004 // method handle's MethodType. This macro hides the distinction.
8005 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
8006 Register temp_reg) {
8007 assert_different_registers(vmslots_reg, mh_reg, temp_reg);
8008 // load mh.type.form.vmslots
8009 if (java_lang_invoke_MethodHandle::vmslots_offset_in_bytes() != 0) {
8010 // hoist vmslots into every mh to avoid dependent load chain
8011 movl(vmslots_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmslots_offset_in_bytes, temp_reg)));
8012 } else {
8013 Register temp2_reg = vmslots_reg;
8014 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::type_offset_in_bytes, temp_reg)));
8015 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodType::form_offset_in_bytes, temp_reg)));
8016 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_lang_invoke_MethodTypeForm::vmslots_offset_in_bytes, temp_reg)));
8017 }
8018 }
8021 // registers on entry:
8022 // - rcx: method handle
8023 // - rdx: killable temp (interpreted only)
8024 // - rax: killable temp (compiled only)
8025 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) {
8026 assert(mh_reg == rcx, "caller must put MH object in rcx");
8027 assert_different_registers(mh_reg, temp_reg);
8029 // pick out the interpreted side of the handler
8030 // NOTE: vmentry is not an oop!
8031 movptr(temp_reg, Address(mh_reg, delayed_value(java_lang_invoke_MethodHandle::vmentry_offset_in_bytes, temp_reg)));
8033 // off we go...
8034 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes()));
8036 // for the various stubs which take control at this point,
8037 // see MethodHandles::generate_method_handle_stub
8038 }
8041 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
8042 int extra_slot_offset) {
8043 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
8044 int stackElementSize = Interpreter::stackElementSize;
8045 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
8046 #ifdef ASSERT
8047 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
8048 assert(offset1 - offset == stackElementSize, "correct arithmetic");
8049 #endif
8050 Register scale_reg = noreg;
8051 Address::ScaleFactor scale_factor = Address::no_scale;
8052 if (arg_slot.is_constant()) {
8053 offset += arg_slot.as_constant() * stackElementSize;
8054 } else {
8055 scale_reg = arg_slot.as_register();
8056 scale_factor = Address::times(stackElementSize);
8057 }
8058 offset += wordSize; // return PC is on stack
8059 return Address(rsp, scale_reg, scale_factor, offset);
8060 }
8063 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
8064 if (!VerifyOops) return;
8066 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
8067 // Pass register number to verify_oop_subroutine
8068 char* b = new char[strlen(s) + 50];
8069 sprintf(b, "verify_oop_addr: %s", s);
8071 #ifdef _LP64
8072 push(rscratch1); // save r10, trashed by movptr()
8073 #endif
8074 push(rax); // save rax,
8075 // addr may contain rsp so we will have to adjust it based on the push
8076 // we just did (and on 64 bit we do two pushes)
8077 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
8078 // stores rax into addr which is backwards of what was intended.
8079 if (addr.uses(rsp)) {
8080 lea(rax, addr);
8081 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
8082 } else {
8083 pushptr(addr);
8084 }
8086 ExternalAddress buffer((address) b);
8087 // pass msg argument
8088 // avoid using pushptr, as it modifies scratch registers
8089 // and our contract is not to modify anything
8090 movptr(rax, buffer.addr());
8091 push(rax);
8093 // call indirectly to solve generation ordering problem
8094 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
8095 call(rax);
8096 // Caller pops the arguments (addr, message) and restores rax, r10.
8097 }
8099 void MacroAssembler::verify_tlab() {
8100 #ifdef ASSERT
8101 if (UseTLAB && VerifyOops) {
8102 Label next, ok;
8103 Register t1 = rsi;
8104 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
8106 push(t1);
8107 NOT_LP64(push(thread_reg));
8108 NOT_LP64(get_thread(thread_reg));
8110 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
8111 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
8112 jcc(Assembler::aboveEqual, next);
8113 stop("assert(top >= start)");
8114 should_not_reach_here();
8116 bind(next);
8117 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
8118 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
8119 jcc(Assembler::aboveEqual, ok);
8120 stop("assert(top <= end)");
8121 should_not_reach_here();
8123 bind(ok);
8124 NOT_LP64(pop(thread_reg));
8125 pop(t1);
8126 }
8127 #endif
8128 }
8130 class ControlWord {
8131 public:
8132 int32_t _value;
8134 int rounding_control() const { return (_value >> 10) & 3 ; }
8135 int precision_control() const { return (_value >> 8) & 3 ; }
8136 bool precision() const { return ((_value >> 5) & 1) != 0; }
8137 bool underflow() const { return ((_value >> 4) & 1) != 0; }
8138 bool overflow() const { return ((_value >> 3) & 1) != 0; }
8139 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
8140 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
8141 bool invalid() const { return ((_value >> 0) & 1) != 0; }
8143 void print() const {
8144 // rounding control
8145 const char* rc;
8146 switch (rounding_control()) {
8147 case 0: rc = "round near"; break;
8148 case 1: rc = "round down"; break;
8149 case 2: rc = "round up "; break;
8150 case 3: rc = "chop "; break;
8151 };
8152 // precision control
8153 const char* pc;
8154 switch (precision_control()) {
8155 case 0: pc = "24 bits "; break;
8156 case 1: pc = "reserved"; break;
8157 case 2: pc = "53 bits "; break;
8158 case 3: pc = "64 bits "; break;
8159 };
8160 // flags
8161 char f[9];
8162 f[0] = ' ';
8163 f[1] = ' ';
8164 f[2] = (precision ()) ? 'P' : 'p';
8165 f[3] = (underflow ()) ? 'U' : 'u';
8166 f[4] = (overflow ()) ? 'O' : 'o';
8167 f[5] = (zero_divide ()) ? 'Z' : 'z';
8168 f[6] = (denormalized()) ? 'D' : 'd';
8169 f[7] = (invalid ()) ? 'I' : 'i';
8170 f[8] = '\x0';
8171 // output
8172 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
8173 }
8175 };
8177 class StatusWord {
8178 public:
8179 int32_t _value;
8181 bool busy() const { return ((_value >> 15) & 1) != 0; }
8182 bool C3() const { return ((_value >> 14) & 1) != 0; }
8183 bool C2() const { return ((_value >> 10) & 1) != 0; }
8184 bool C1() const { return ((_value >> 9) & 1) != 0; }
8185 bool C0() const { return ((_value >> 8) & 1) != 0; }
8186 int top() const { return (_value >> 11) & 7 ; }
8187 bool error_status() const { return ((_value >> 7) & 1) != 0; }
8188 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
8189 bool precision() const { return ((_value >> 5) & 1) != 0; }
8190 bool underflow() const { return ((_value >> 4) & 1) != 0; }
8191 bool overflow() const { return ((_value >> 3) & 1) != 0; }
8192 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
8193 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
8194 bool invalid() const { return ((_value >> 0) & 1) != 0; }
8196 void print() const {
8197 // condition codes
8198 char c[5];
8199 c[0] = (C3()) ? '3' : '-';
8200 c[1] = (C2()) ? '2' : '-';
8201 c[2] = (C1()) ? '1' : '-';
8202 c[3] = (C0()) ? '0' : '-';
8203 c[4] = '\x0';
8204 // flags
8205 char f[9];
8206 f[0] = (error_status()) ? 'E' : '-';
8207 f[1] = (stack_fault ()) ? 'S' : '-';
8208 f[2] = (precision ()) ? 'P' : '-';
8209 f[3] = (underflow ()) ? 'U' : '-';
8210 f[4] = (overflow ()) ? 'O' : '-';
8211 f[5] = (zero_divide ()) ? 'Z' : '-';
8212 f[6] = (denormalized()) ? 'D' : '-';
8213 f[7] = (invalid ()) ? 'I' : '-';
8214 f[8] = '\x0';
8215 // output
8216 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
8217 }
8219 };
8221 class TagWord {
8222 public:
8223 int32_t _value;
8225 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
8227 void print() const {
8228 printf("%04x", _value & 0xFFFF);
8229 }
8231 };
8233 class FPU_Register {
8234 public:
8235 int32_t _m0;
8236 int32_t _m1;
8237 int16_t _ex;
8239 bool is_indefinite() const {
8240 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
8241 }
8243 void print() const {
8244 char sign = (_ex < 0) ? '-' : '+';
8245 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
8246 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
8247 };
8249 };
8251 class FPU_State {
8252 public:
8253 enum {
8254 register_size = 10,
8255 number_of_registers = 8,
8256 register_mask = 7
8257 };
8259 ControlWord _control_word;
8260 StatusWord _status_word;
8261 TagWord _tag_word;
8262 int32_t _error_offset;
8263 int32_t _error_selector;
8264 int32_t _data_offset;
8265 int32_t _data_selector;
8266 int8_t _register[register_size * number_of_registers];
8268 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
8269 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
8271 const char* tag_as_string(int tag) const {
8272 switch (tag) {
8273 case 0: return "valid";
8274 case 1: return "zero";
8275 case 2: return "special";
8276 case 3: return "empty";
8277 }
8278 ShouldNotReachHere();
8279 return NULL;
8280 }
8282 void print() const {
8283 // print computation registers
8284 { int t = _status_word.top();
8285 for (int i = 0; i < number_of_registers; i++) {
8286 int j = (i - t) & register_mask;
8287 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
8288 st(j)->print();
8289 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
8290 }
8291 }
8292 printf("\n");
8293 // print control registers
8294 printf("ctrl = "); _control_word.print(); printf("\n");
8295 printf("stat = "); _status_word .print(); printf("\n");
8296 printf("tags = "); _tag_word .print(); printf("\n");
8297 }
8299 };
8301 class Flag_Register {
8302 public:
8303 int32_t _value;
8305 bool overflow() const { return ((_value >> 11) & 1) != 0; }
8306 bool direction() const { return ((_value >> 10) & 1) != 0; }
8307 bool sign() const { return ((_value >> 7) & 1) != 0; }
8308 bool zero() const { return ((_value >> 6) & 1) != 0; }
8309 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
8310 bool parity() const { return ((_value >> 2) & 1) != 0; }
8311 bool carry() const { return ((_value >> 0) & 1) != 0; }
8313 void print() const {
8314 // flags
8315 char f[8];
8316 f[0] = (overflow ()) ? 'O' : '-';
8317 f[1] = (direction ()) ? 'D' : '-';
8318 f[2] = (sign ()) ? 'S' : '-';
8319 f[3] = (zero ()) ? 'Z' : '-';
8320 f[4] = (auxiliary_carry()) ? 'A' : '-';
8321 f[5] = (parity ()) ? 'P' : '-';
8322 f[6] = (carry ()) ? 'C' : '-';
8323 f[7] = '\x0';
8324 // output
8325 printf("%08x flags = %s", _value, f);
8326 }
8328 };
8330 class IU_Register {
8331 public:
8332 int32_t _value;
8334 void print() const {
8335 printf("%08x %11d", _value, _value);
8336 }
8338 };
8340 class IU_State {
8341 public:
8342 Flag_Register _eflags;
8343 IU_Register _rdi;
8344 IU_Register _rsi;
8345 IU_Register _rbp;
8346 IU_Register _rsp;
8347 IU_Register _rbx;
8348 IU_Register _rdx;
8349 IU_Register _rcx;
8350 IU_Register _rax;
8352 void print() const {
8353 // computation registers
8354 printf("rax, = "); _rax.print(); printf("\n");
8355 printf("rbx, = "); _rbx.print(); printf("\n");
8356 printf("rcx = "); _rcx.print(); printf("\n");
8357 printf("rdx = "); _rdx.print(); printf("\n");
8358 printf("rdi = "); _rdi.print(); printf("\n");
8359 printf("rsi = "); _rsi.print(); printf("\n");
8360 printf("rbp, = "); _rbp.print(); printf("\n");
8361 printf("rsp = "); _rsp.print(); printf("\n");
8362 printf("\n");
8363 // control registers
8364 printf("flgs = "); _eflags.print(); printf("\n");
8365 }
8366 };
8369 class CPU_State {
8370 public:
8371 FPU_State _fpu_state;
8372 IU_State _iu_state;
8374 void print() const {
8375 printf("--------------------------------------------------\n");
8376 _iu_state .print();
8377 printf("\n");
8378 _fpu_state.print();
8379 printf("--------------------------------------------------\n");
8380 }
8382 };
8385 static void _print_CPU_state(CPU_State* state) {
8386 state->print();
8387 };
8390 void MacroAssembler::print_CPU_state() {
8391 push_CPU_state();
8392 push(rsp); // pass CPU state
8393 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
8394 addptr(rsp, wordSize); // discard argument
8395 pop_CPU_state();
8396 }
8399 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
8400 static int counter = 0;
8401 FPU_State* fs = &state->_fpu_state;
8402 counter++;
8403 // For leaf calls, only verify that the top few elements remain empty.
8404 // We only need 1 empty at the top for C2 code.
8405 if( stack_depth < 0 ) {
8406 if( fs->tag_for_st(7) != 3 ) {
8407 printf("FPR7 not empty\n");
8408 state->print();
8409 assert(false, "error");
8410 return false;
8411 }
8412 return true; // All other stack states do not matter
8413 }
8415 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
8416 "bad FPU control word");
8418 // compute stack depth
8419 int i = 0;
8420 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
8421 int d = i;
8422 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
8423 // verify findings
8424 if (i != FPU_State::number_of_registers) {
8425 // stack not contiguous
8426 printf("%s: stack not contiguous at ST%d\n", s, i);
8427 state->print();
8428 assert(false, "error");
8429 return false;
8430 }
8431 // check if computed stack depth corresponds to expected stack depth
8432 if (stack_depth < 0) {
8433 // expected stack depth is -stack_depth or less
8434 if (d > -stack_depth) {
8435 // too many elements on the stack
8436 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
8437 state->print();
8438 assert(false, "error");
8439 return false;
8440 }
8441 } else {
8442 // expected stack depth is stack_depth
8443 if (d != stack_depth) {
8444 // wrong stack depth
8445 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
8446 state->print();
8447 assert(false, "error");
8448 return false;
8449 }
8450 }
8451 // everything is cool
8452 return true;
8453 }
8456 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
8457 if (!VerifyFPU) return;
8458 push_CPU_state();
8459 push(rsp); // pass CPU state
8460 ExternalAddress msg((address) s);
8461 // pass message string s
8462 pushptr(msg.addr());
8463 push(stack_depth); // pass stack depth
8464 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
8465 addptr(rsp, 3 * wordSize); // discard arguments
8466 // check for error
8467 { Label L;
8468 testl(rax, rax);
8469 jcc(Assembler::notZero, L);
8470 int3(); // break if error condition
8471 bind(L);
8472 }
8473 pop_CPU_state();
8474 }
8476 void MacroAssembler::load_klass(Register dst, Register src) {
8477 #ifdef _LP64
8478 if (UseCompressedOops) {
8479 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8480 decode_heap_oop_not_null(dst);
8481 } else
8482 #endif
8483 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8484 }
8486 void MacroAssembler::load_prototype_header(Register dst, Register src) {
8487 #ifdef _LP64
8488 if (UseCompressedOops) {
8489 assert (Universe::heap() != NULL, "java heap should be initialized");
8490 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8491 if (Universe::narrow_oop_shift() != 0) {
8492 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8493 if (LogMinObjAlignmentInBytes == Address::times_8) {
8494 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8495 } else {
8496 // OK to use shift since we don't need to preserve flags.
8497 shlq(dst, LogMinObjAlignmentInBytes);
8498 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8499 }
8500 } else {
8501 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8502 }
8503 } else
8504 #endif
8505 {
8506 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
8507 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
8508 }
8509 }
8511 void MacroAssembler::store_klass(Register dst, Register src) {
8512 #ifdef _LP64
8513 if (UseCompressedOops) {
8514 encode_heap_oop_not_null(src);
8515 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8516 } else
8517 #endif
8518 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
8519 }
8521 void MacroAssembler::load_heap_oop(Register dst, Address src) {
8522 #ifdef _LP64
8523 if (UseCompressedOops) {
8524 movl(dst, src);
8525 decode_heap_oop(dst);
8526 } else
8527 #endif
8528 movptr(dst, src);
8529 }
8531 // Doesn't do verfication, generates fixed size code
8532 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
8533 #ifdef _LP64
8534 if (UseCompressedOops) {
8535 movl(dst, src);
8536 decode_heap_oop_not_null(dst);
8537 } else
8538 #endif
8539 movptr(dst, src);
8540 }
8542 void MacroAssembler::store_heap_oop(Address dst, Register src) {
8543 #ifdef _LP64
8544 if (UseCompressedOops) {
8545 assert(!dst.uses(src), "not enough registers");
8546 encode_heap_oop(src);
8547 movl(dst, src);
8548 } else
8549 #endif
8550 movptr(dst, src);
8551 }
8553 // Used for storing NULLs.
8554 void MacroAssembler::store_heap_oop_null(Address dst) {
8555 #ifdef _LP64
8556 if (UseCompressedOops) {
8557 movl(dst, (int32_t)NULL_WORD);
8558 } else {
8559 movslq(dst, (int32_t)NULL_WORD);
8560 }
8561 #else
8562 movl(dst, (int32_t)NULL_WORD);
8563 #endif
8564 }
8566 #ifdef _LP64
8567 void MacroAssembler::store_klass_gap(Register dst, Register src) {
8568 if (UseCompressedOops) {
8569 // Store to klass gap in destination
8570 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
8571 }
8572 }
8574 #ifdef ASSERT
8575 void MacroAssembler::verify_heapbase(const char* msg) {
8576 assert (UseCompressedOops, "should be compressed");
8577 assert (Universe::heap() != NULL, "java heap should be initialized");
8578 if (CheckCompressedOops) {
8579 Label ok;
8580 push(rscratch1); // cmpptr trashes rscratch1
8581 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8582 jcc(Assembler::equal, ok);
8583 stop(msg);
8584 bind(ok);
8585 pop(rscratch1);
8586 }
8587 }
8588 #endif
8590 // Algorithm must match oop.inline.hpp encode_heap_oop.
8591 void MacroAssembler::encode_heap_oop(Register r) {
8592 #ifdef ASSERT
8593 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
8594 #endif
8595 verify_oop(r, "broken oop in encode_heap_oop");
8596 if (Universe::narrow_oop_base() == NULL) {
8597 if (Universe::narrow_oop_shift() != 0) {
8598 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8599 shrq(r, LogMinObjAlignmentInBytes);
8600 }
8601 return;
8602 }
8603 testq(r, r);
8604 cmovq(Assembler::equal, r, r12_heapbase);
8605 subq(r, r12_heapbase);
8606 shrq(r, LogMinObjAlignmentInBytes);
8607 }
8609 void MacroAssembler::encode_heap_oop_not_null(Register r) {
8610 #ifdef ASSERT
8611 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
8612 if (CheckCompressedOops) {
8613 Label ok;
8614 testq(r, r);
8615 jcc(Assembler::notEqual, ok);
8616 stop("null oop passed to encode_heap_oop_not_null");
8617 bind(ok);
8618 }
8619 #endif
8620 verify_oop(r, "broken oop in encode_heap_oop_not_null");
8621 if (Universe::narrow_oop_base() != NULL) {
8622 subq(r, r12_heapbase);
8623 }
8624 if (Universe::narrow_oop_shift() != 0) {
8625 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8626 shrq(r, LogMinObjAlignmentInBytes);
8627 }
8628 }
8630 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
8631 #ifdef ASSERT
8632 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
8633 if (CheckCompressedOops) {
8634 Label ok;
8635 testq(src, src);
8636 jcc(Assembler::notEqual, ok);
8637 stop("null oop passed to encode_heap_oop_not_null2");
8638 bind(ok);
8639 }
8640 #endif
8641 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
8642 if (dst != src) {
8643 movq(dst, src);
8644 }
8645 if (Universe::narrow_oop_base() != NULL) {
8646 subq(dst, r12_heapbase);
8647 }
8648 if (Universe::narrow_oop_shift() != 0) {
8649 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8650 shrq(dst, LogMinObjAlignmentInBytes);
8651 }
8652 }
8654 void MacroAssembler::decode_heap_oop(Register r) {
8655 #ifdef ASSERT
8656 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
8657 #endif
8658 if (Universe::narrow_oop_base() == NULL) {
8659 if (Universe::narrow_oop_shift() != 0) {
8660 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8661 shlq(r, LogMinObjAlignmentInBytes);
8662 }
8663 } else {
8664 Label done;
8665 shlq(r, LogMinObjAlignmentInBytes);
8666 jccb(Assembler::equal, done);
8667 addq(r, r12_heapbase);
8668 bind(done);
8669 }
8670 verify_oop(r, "broken oop in decode_heap_oop");
8671 }
8673 void MacroAssembler::decode_heap_oop_not_null(Register r) {
8674 // Note: it will change flags
8675 assert (UseCompressedOops, "should only be used for compressed headers");
8676 assert (Universe::heap() != NULL, "java heap should be initialized");
8677 // Cannot assert, unverified entry point counts instructions (see .ad file)
8678 // vtableStubs also counts instructions in pd_code_size_limit.
8679 // Also do not verify_oop as this is called by verify_oop.
8680 if (Universe::narrow_oop_shift() != 0) {
8681 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8682 shlq(r, LogMinObjAlignmentInBytes);
8683 if (Universe::narrow_oop_base() != NULL) {
8684 addq(r, r12_heapbase);
8685 }
8686 } else {
8687 assert (Universe::narrow_oop_base() == NULL, "sanity");
8688 }
8689 }
8691 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
8692 // Note: it will change flags
8693 assert (UseCompressedOops, "should only be used for compressed headers");
8694 assert (Universe::heap() != NULL, "java heap should be initialized");
8695 // Cannot assert, unverified entry point counts instructions (see .ad file)
8696 // vtableStubs also counts instructions in pd_code_size_limit.
8697 // Also do not verify_oop as this is called by verify_oop.
8698 if (Universe::narrow_oop_shift() != 0) {
8699 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
8700 if (LogMinObjAlignmentInBytes == Address::times_8) {
8701 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
8702 } else {
8703 if (dst != src) {
8704 movq(dst, src);
8705 }
8706 shlq(dst, LogMinObjAlignmentInBytes);
8707 if (Universe::narrow_oop_base() != NULL) {
8708 addq(dst, r12_heapbase);
8709 }
8710 }
8711 } else {
8712 assert (Universe::narrow_oop_base() == NULL, "sanity");
8713 if (dst != src) {
8714 movq(dst, src);
8715 }
8716 }
8717 }
8719 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
8720 assert (UseCompressedOops, "should only be used for compressed headers");
8721 assert (Universe::heap() != NULL, "java heap should be initialized");
8722 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8723 int oop_index = oop_recorder()->find_index(obj);
8724 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8725 mov_narrow_oop(dst, oop_index, rspec);
8726 }
8728 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
8729 assert (UseCompressedOops, "should only be used for compressed headers");
8730 assert (Universe::heap() != NULL, "java heap should be initialized");
8731 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8732 int oop_index = oop_recorder()->find_index(obj);
8733 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8734 mov_narrow_oop(dst, oop_index, rspec);
8735 }
8737 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
8738 assert (UseCompressedOops, "should only be used for compressed headers");
8739 assert (Universe::heap() != NULL, "java heap should be initialized");
8740 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8741 int oop_index = oop_recorder()->find_index(obj);
8742 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8743 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8744 }
8746 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
8747 assert (UseCompressedOops, "should only be used for compressed headers");
8748 assert (Universe::heap() != NULL, "java heap should be initialized");
8749 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
8750 int oop_index = oop_recorder()->find_index(obj);
8751 RelocationHolder rspec = oop_Relocation::spec(oop_index);
8752 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
8753 }
8755 void MacroAssembler::reinit_heapbase() {
8756 if (UseCompressedOops) {
8757 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr()));
8758 }
8759 }
8760 #endif // _LP64
8762 // IndexOf for constant substrings with size >= 8 chars
8763 // which don't need to be loaded through stack.
8764 void MacroAssembler::string_indexofC8(Register str1, Register str2,
8765 Register cnt1, Register cnt2,
8766 int int_cnt2, Register result,
8767 XMMRegister vec, Register tmp) {
8768 assert(UseSSE42Intrinsics, "SSE4.2 is required");
8770 // This method uses pcmpestri inxtruction with bound registers
8771 // inputs:
8772 // xmm - substring
8773 // rax - substring length (elements count)
8774 // mem - scanned string
8775 // rdx - string length (elements count)
8776 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
8777 // outputs:
8778 // rcx - matched index in string
8779 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
8781 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
8782 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
8783 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
8785 // Note, inline_string_indexOf() generates checks:
8786 // if (substr.count > string.count) return -1;
8787 // if (substr.count == 0) return 0;
8788 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
8790 // Load substring.
8791 movdqu(vec, Address(str2, 0));
8792 movl(cnt2, int_cnt2);
8793 movptr(result, str1); // string addr
8795 if (int_cnt2 > 8) {
8796 jmpb(SCAN_TO_SUBSTR);
8798 // Reload substr for rescan, this code
8799 // is executed only for large substrings (> 8 chars)
8800 bind(RELOAD_SUBSTR);
8801 movdqu(vec, Address(str2, 0));
8802 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
8804 bind(RELOAD_STR);
8805 // We came here after the beginning of the substring was
8806 // matched but the rest of it was not so we need to search
8807 // again. Start from the next element after the previous match.
8809 // cnt2 is number of substring reminding elements and
8810 // cnt1 is number of string reminding elements when cmp failed.
8811 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
8812 subl(cnt1, cnt2);
8813 addl(cnt1, int_cnt2);
8814 movl(cnt2, int_cnt2); // Now restore cnt2
8816 decrementl(cnt1); // Shift to next element
8817 cmpl(cnt1, cnt2);
8818 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
8820 addptr(result, 2);
8822 } // (int_cnt2 > 8)
8824 // Scan string for start of substr in 16-byte vectors
8825 bind(SCAN_TO_SUBSTR);
8826 pcmpestri(vec, Address(result, 0), 0x0d);
8827 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
8828 subl(cnt1, 8);
8829 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
8830 cmpl(cnt1, cnt2);
8831 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
8832 addptr(result, 16);
8833 jmpb(SCAN_TO_SUBSTR);
8835 // Found a potential substr
8836 bind(FOUND_CANDIDATE);
8837 // Matched whole vector if first element matched (tmp(rcx) == 0).
8838 if (int_cnt2 == 8) {
8839 jccb(Assembler::overflow, RET_FOUND); // OF == 1
8840 } else { // int_cnt2 > 8
8841 jccb(Assembler::overflow, FOUND_SUBSTR);
8842 }
8843 // After pcmpestri tmp(rcx) contains matched element index
8844 // Compute start addr of substr
8845 lea(result, Address(result, tmp, Address::times_2));
8847 // Make sure string is still long enough
8848 subl(cnt1, tmp);
8849 cmpl(cnt1, cnt2);
8850 if (int_cnt2 == 8) {
8851 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
8852 } else { // int_cnt2 > 8
8853 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
8854 }
8855 // Left less then substring.
8857 bind(RET_NOT_FOUND);
8858 movl(result, -1);
8859 jmpb(EXIT);
8861 if (int_cnt2 > 8) {
8862 // This code is optimized for the case when whole substring
8863 // is matched if its head is matched.
8864 bind(MATCH_SUBSTR_HEAD);
8865 pcmpestri(vec, Address(result, 0), 0x0d);
8866 // Reload only string if does not match
8867 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
8869 Label CONT_SCAN_SUBSTR;
8870 // Compare the rest of substring (> 8 chars).
8871 bind(FOUND_SUBSTR);
8872 // First 8 chars are already matched.
8873 negptr(cnt2);
8874 addptr(cnt2, 8);
8876 bind(SCAN_SUBSTR);
8877 subl(cnt1, 8);
8878 cmpl(cnt2, -8); // Do not read beyond substring
8879 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
8880 // Back-up strings to avoid reading beyond substring:
8881 // cnt1 = cnt1 - cnt2 + 8
8882 addl(cnt1, cnt2); // cnt2 is negative
8883 addl(cnt1, 8);
8884 movl(cnt2, 8); negptr(cnt2);
8885 bind(CONT_SCAN_SUBSTR);
8886 if (int_cnt2 < (int)G) {
8887 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
8888 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
8889 } else {
8890 // calculate index in register to avoid integer overflow (int_cnt2*2)
8891 movl(tmp, int_cnt2);
8892 addptr(tmp, cnt2);
8893 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
8894 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
8895 }
8896 // Need to reload strings pointers if not matched whole vector
8897 jccb(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
8898 addptr(cnt2, 8);
8899 jccb(Assembler::negative, SCAN_SUBSTR);
8900 // Fall through if found full substring
8902 } // (int_cnt2 > 8)
8904 bind(RET_FOUND);
8905 // Found result if we matched full small substring.
8906 // Compute substr offset
8907 subptr(result, str1);
8908 shrl(result, 1); // index
8909 bind(EXIT);
8911 } // string_indexofC8
8913 // Small strings are loaded through stack if they cross page boundary.
8914 void MacroAssembler::string_indexof(Register str1, Register str2,
8915 Register cnt1, Register cnt2,
8916 int int_cnt2, Register result,
8917 XMMRegister vec, Register tmp) {
8918 assert(UseSSE42Intrinsics, "SSE4.2 is required");
8919 //
8920 // int_cnt2 is length of small (< 8 chars) constant substring
8921 // or (-1) for non constant substring in which case its length
8922 // is in cnt2 register.
8923 //
8924 // Note, inline_string_indexOf() generates checks:
8925 // if (substr.count > string.count) return -1;
8926 // if (substr.count == 0) return 0;
8927 //
8928 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
8930 // This method uses pcmpestri inxtruction with bound registers
8931 // inputs:
8932 // xmm - substring
8933 // rax - substring length (elements count)
8934 // mem - scanned string
8935 // rdx - string length (elements count)
8936 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
8937 // outputs:
8938 // rcx - matched index in string
8939 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
8941 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
8942 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
8943 FOUND_CANDIDATE;
8945 { //========================================================
8946 // We don't know where these strings are located
8947 // and we can't read beyond them. Load them through stack.
8948 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
8950 movptr(tmp, rsp); // save old SP
8952 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
8953 if (int_cnt2 == 1) { // One char
8954 load_unsigned_short(result, Address(str2, 0));
8955 movdl(vec, result); // move 32 bits
8956 } else if (int_cnt2 == 2) { // Two chars
8957 movdl(vec, Address(str2, 0)); // move 32 bits
8958 } else if (int_cnt2 == 4) { // Four chars
8959 movq(vec, Address(str2, 0)); // move 64 bits
8960 } else { // cnt2 = { 3, 5, 6, 7 }
8961 // Array header size is 12 bytes in 32-bit VM
8962 // + 6 bytes for 3 chars == 18 bytes,
8963 // enough space to load vec and shift.
8964 assert(HeapWordSize*typeArrayKlass::header_size() >= 12,"sanity");
8965 movdqu(vec, Address(str2, (int_cnt2*2)-16));
8966 psrldq(vec, 16-(int_cnt2*2));
8967 }
8968 } else { // not constant substring
8969 cmpl(cnt2, 8);
8970 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
8972 // We can read beyond string if srt+16 does not cross page boundary
8973 // since heaps are aligned and mapped by pages.
8974 assert(os::vm_page_size() < (int)G, "default page should be small");
8975 movl(result, str2); // We need only low 32 bits
8976 andl(result, (os::vm_page_size()-1));
8977 cmpl(result, (os::vm_page_size()-16));
8978 jccb(Assembler::belowEqual, CHECK_STR);
8980 // Move small strings to stack to allow load 16 bytes into vec.
8981 subptr(rsp, 16);
8982 int stk_offset = wordSize-2;
8983 push(cnt2);
8985 bind(COPY_SUBSTR);
8986 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
8987 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
8988 decrement(cnt2);
8989 jccb(Assembler::notZero, COPY_SUBSTR);
8991 pop(cnt2);
8992 movptr(str2, rsp); // New substring address
8993 } // non constant
8995 bind(CHECK_STR);
8996 cmpl(cnt1, 8);
8997 jccb(Assembler::aboveEqual, BIG_STRINGS);
8999 // Check cross page boundary.
9000 movl(result, str1); // We need only low 32 bits
9001 andl(result, (os::vm_page_size()-1));
9002 cmpl(result, (os::vm_page_size()-16));
9003 jccb(Assembler::belowEqual, BIG_STRINGS);
9005 subptr(rsp, 16);
9006 int stk_offset = -2;
9007 if (int_cnt2 < 0) { // not constant
9008 push(cnt2);
9009 stk_offset += wordSize;
9010 }
9011 movl(cnt2, cnt1);
9013 bind(COPY_STR);
9014 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
9015 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
9016 decrement(cnt2);
9017 jccb(Assembler::notZero, COPY_STR);
9019 if (int_cnt2 < 0) { // not constant
9020 pop(cnt2);
9021 }
9022 movptr(str1, rsp); // New string address
9024 bind(BIG_STRINGS);
9025 // Load substring.
9026 if (int_cnt2 < 0) { // -1
9027 movdqu(vec, Address(str2, 0));
9028 push(cnt2); // substr count
9029 push(str2); // substr addr
9030 push(str1); // string addr
9031 } else {
9032 // Small (< 8 chars) constant substrings are loaded already.
9033 movl(cnt2, int_cnt2);
9034 }
9035 push(tmp); // original SP
9037 } // Finished loading
9039 //========================================================
9040 // Start search
9041 //
9043 movptr(result, str1); // string addr
9045 if (int_cnt2 < 0) { // Only for non constant substring
9046 jmpb(SCAN_TO_SUBSTR);
9048 // SP saved at sp+0
9049 // String saved at sp+1*wordSize
9050 // Substr saved at sp+2*wordSize
9051 // Substr count saved at sp+3*wordSize
9053 // Reload substr for rescan, this code
9054 // is executed only for large substrings (> 8 chars)
9055 bind(RELOAD_SUBSTR);
9056 movptr(str2, Address(rsp, 2*wordSize));
9057 movl(cnt2, Address(rsp, 3*wordSize));
9058 movdqu(vec, Address(str2, 0));
9059 // We came here after the beginning of the substring was
9060 // matched but the rest of it was not so we need to search
9061 // again. Start from the next element after the previous match.
9062 subptr(str1, result); // Restore counter
9063 shrl(str1, 1);
9064 addl(cnt1, str1);
9065 decrementl(cnt1); // Shift to next element
9066 cmpl(cnt1, cnt2);
9067 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
9069 addptr(result, 2);
9070 } // non constant
9072 // Scan string for start of substr in 16-byte vectors
9073 bind(SCAN_TO_SUBSTR);
9074 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
9075 pcmpestri(vec, Address(result, 0), 0x0d);
9076 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
9077 subl(cnt1, 8);
9078 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
9079 cmpl(cnt1, cnt2);
9080 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
9081 addptr(result, 16);
9083 bind(ADJUST_STR);
9084 cmpl(cnt1, 8); // Do not read beyond string
9085 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
9086 // Back-up string to avoid reading beyond string.
9087 lea(result, Address(result, cnt1, Address::times_2, -16));
9088 movl(cnt1, 8);
9089 jmpb(SCAN_TO_SUBSTR);
9091 // Found a potential substr
9092 bind(FOUND_CANDIDATE);
9093 // After pcmpestri tmp(rcx) contains matched element index
9095 // Make sure string is still long enough
9096 subl(cnt1, tmp);
9097 cmpl(cnt1, cnt2);
9098 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
9099 // Left less then substring.
9101 bind(RET_NOT_FOUND);
9102 movl(result, -1);
9103 jmpb(CLEANUP);
9105 bind(FOUND_SUBSTR);
9106 // Compute start addr of substr
9107 lea(result, Address(result, tmp, Address::times_2));
9109 if (int_cnt2 > 0) { // Constant substring
9110 // Repeat search for small substring (< 8 chars)
9111 // from new point without reloading substring.
9112 // Have to check that we don't read beyond string.
9113 cmpl(tmp, 8-int_cnt2);
9114 jccb(Assembler::greater, ADJUST_STR);
9115 // Fall through if matched whole substring.
9116 } else { // non constant
9117 assert(int_cnt2 == -1, "should be != 0");
9119 addl(tmp, cnt2);
9120 // Found result if we matched whole substring.
9121 cmpl(tmp, 8);
9122 jccb(Assembler::lessEqual, RET_FOUND);
9124 // Repeat search for small substring (<= 8 chars)
9125 // from new point 'str1' without reloading substring.
9126 cmpl(cnt2, 8);
9127 // Have to check that we don't read beyond string.
9128 jccb(Assembler::lessEqual, ADJUST_STR);
9130 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
9131 // Compare the rest of substring (> 8 chars).
9132 movptr(str1, result);
9134 cmpl(tmp, cnt2);
9135 // First 8 chars are already matched.
9136 jccb(Assembler::equal, CHECK_NEXT);
9138 bind(SCAN_SUBSTR);
9139 pcmpestri(vec, Address(str1, 0), 0x0d);
9140 // Need to reload strings pointers if not matched whole vector
9141 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
9143 bind(CHECK_NEXT);
9144 subl(cnt2, 8);
9145 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
9146 addptr(str1, 16);
9147 addptr(str2, 16);
9148 subl(cnt1, 8);
9149 cmpl(cnt2, 8); // Do not read beyond substring
9150 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
9151 // Back-up strings to avoid reading beyond substring.
9152 lea(str2, Address(str2, cnt2, Address::times_2, -16));
9153 lea(str1, Address(str1, cnt2, Address::times_2, -16));
9154 subl(cnt1, cnt2);
9155 movl(cnt2, 8);
9156 addl(cnt1, 8);
9157 bind(CONT_SCAN_SUBSTR);
9158 movdqu(vec, Address(str2, 0));
9159 jmpb(SCAN_SUBSTR);
9161 bind(RET_FOUND_LONG);
9162 movptr(str1, Address(rsp, wordSize));
9163 } // non constant
9165 bind(RET_FOUND);
9166 // Compute substr offset
9167 subptr(result, str1);
9168 shrl(result, 1); // index
9170 bind(CLEANUP);
9171 pop(rsp); // restore SP
9173 } // string_indexof
9175 // Compare strings.
9176 void MacroAssembler::string_compare(Register str1, Register str2,
9177 Register cnt1, Register cnt2, Register result,
9178 XMMRegister vec1) {
9179 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
9181 // Compute the minimum of the string lengths and the
9182 // difference of the string lengths (stack).
9183 // Do the conditional move stuff
9184 movl(result, cnt1);
9185 subl(cnt1, cnt2);
9186 push(cnt1);
9187 cmov32(Assembler::lessEqual, cnt2, result);
9189 // Is the minimum length zero?
9190 testl(cnt2, cnt2);
9191 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
9193 // Load first characters
9194 load_unsigned_short(result, Address(str1, 0));
9195 load_unsigned_short(cnt1, Address(str2, 0));
9197 // Compare first characters
9198 subl(result, cnt1);
9199 jcc(Assembler::notZero, POP_LABEL);
9200 decrementl(cnt2);
9201 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
9203 {
9204 // Check after comparing first character to see if strings are equivalent
9205 Label LSkip2;
9206 // Check if the strings start at same location
9207 cmpptr(str1, str2);
9208 jccb(Assembler::notEqual, LSkip2);
9210 // Check if the length difference is zero (from stack)
9211 cmpl(Address(rsp, 0), 0x0);
9212 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
9214 // Strings might not be equivalent
9215 bind(LSkip2);
9216 }
9218 Address::ScaleFactor scale = Address::times_2;
9219 int stride = 8;
9221 // Advance to next element
9222 addptr(str1, 16/stride);
9223 addptr(str2, 16/stride);
9225 if (UseSSE42Intrinsics) {
9226 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
9227 int pcmpmask = 0x19;
9228 // Setup to compare 16-byte vectors
9229 movl(result, cnt2);
9230 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
9231 jccb(Assembler::zero, COMPARE_TAIL);
9233 lea(str1, Address(str1, result, scale));
9234 lea(str2, Address(str2, result, scale));
9235 negptr(result);
9237 // pcmpestri
9238 // inputs:
9239 // vec1- substring
9240 // rax - negative string length (elements count)
9241 // mem - scaned string
9242 // rdx - string length (elements count)
9243 // pcmpmask - cmp mode: 11000 (string compare with negated result)
9244 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
9245 // outputs:
9246 // rcx - first mismatched element index
9247 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
9249 bind(COMPARE_WIDE_VECTORS);
9250 movdqu(vec1, Address(str1, result, scale));
9251 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
9252 // After pcmpestri cnt1(rcx) contains mismatched element index
9254 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
9255 addptr(result, stride);
9256 subptr(cnt2, stride);
9257 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
9259 // compare wide vectors tail
9260 testl(result, result);
9261 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
9263 movl(cnt2, stride);
9264 movl(result, stride);
9265 negptr(result);
9266 movdqu(vec1, Address(str1, result, scale));
9267 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
9268 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
9270 // Mismatched characters in the vectors
9271 bind(VECTOR_NOT_EQUAL);
9272 addptr(result, cnt1);
9273 movptr(cnt2, result);
9274 load_unsigned_short(result, Address(str1, cnt2, scale));
9275 load_unsigned_short(cnt1, Address(str2, cnt2, scale));
9276 subl(result, cnt1);
9277 jmpb(POP_LABEL);
9279 bind(COMPARE_TAIL); // limit is zero
9280 movl(cnt2, result);
9281 // Fallthru to tail compare
9282 }
9284 // Shift str2 and str1 to the end of the arrays, negate min
9285 lea(str1, Address(str1, cnt2, scale, 0));
9286 lea(str2, Address(str2, cnt2, scale, 0));
9287 negptr(cnt2);
9289 // Compare the rest of the elements
9290 bind(WHILE_HEAD_LABEL);
9291 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
9292 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
9293 subl(result, cnt1);
9294 jccb(Assembler::notZero, POP_LABEL);
9295 increment(cnt2);
9296 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
9298 // Strings are equal up to min length. Return the length difference.
9299 bind(LENGTH_DIFF_LABEL);
9300 pop(result);
9301 jmpb(DONE_LABEL);
9303 // Discard the stored length difference
9304 bind(POP_LABEL);
9305 pop(cnt1);
9307 // That's it
9308 bind(DONE_LABEL);
9309 }
9311 // Compare char[] arrays aligned to 4 bytes or substrings.
9312 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
9313 Register limit, Register result, Register chr,
9314 XMMRegister vec1, XMMRegister vec2) {
9315 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
9317 int length_offset = arrayOopDesc::length_offset_in_bytes();
9318 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
9320 // Check the input args
9321 cmpptr(ary1, ary2);
9322 jcc(Assembler::equal, TRUE_LABEL);
9324 if (is_array_equ) {
9325 // Need additional checks for arrays_equals.
9326 testptr(ary1, ary1);
9327 jcc(Assembler::zero, FALSE_LABEL);
9328 testptr(ary2, ary2);
9329 jcc(Assembler::zero, FALSE_LABEL);
9331 // Check the lengths
9332 movl(limit, Address(ary1, length_offset));
9333 cmpl(limit, Address(ary2, length_offset));
9334 jcc(Assembler::notEqual, FALSE_LABEL);
9335 }
9337 // count == 0
9338 testl(limit, limit);
9339 jcc(Assembler::zero, TRUE_LABEL);
9341 if (is_array_equ) {
9342 // Load array address
9343 lea(ary1, Address(ary1, base_offset));
9344 lea(ary2, Address(ary2, base_offset));
9345 }
9347 shll(limit, 1); // byte count != 0
9348 movl(result, limit); // copy
9350 if (UseSSE42Intrinsics) {
9351 // With SSE4.2, use double quad vector compare
9352 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
9354 // Compare 16-byte vectors
9355 andl(result, 0x0000000e); // tail count (in bytes)
9356 andl(limit, 0xfffffff0); // vector count (in bytes)
9357 jccb(Assembler::zero, COMPARE_TAIL);
9359 lea(ary1, Address(ary1, limit, Address::times_1));
9360 lea(ary2, Address(ary2, limit, Address::times_1));
9361 negptr(limit);
9363 bind(COMPARE_WIDE_VECTORS);
9364 movdqu(vec1, Address(ary1, limit, Address::times_1));
9365 movdqu(vec2, Address(ary2, limit, Address::times_1));
9366 pxor(vec1, vec2);
9368 ptest(vec1, vec1);
9369 jccb(Assembler::notZero, FALSE_LABEL);
9370 addptr(limit, 16);
9371 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
9373 testl(result, result);
9374 jccb(Assembler::zero, TRUE_LABEL);
9376 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
9377 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
9378 pxor(vec1, vec2);
9380 ptest(vec1, vec1);
9381 jccb(Assembler::notZero, FALSE_LABEL);
9382 jmpb(TRUE_LABEL);
9384 bind(COMPARE_TAIL); // limit is zero
9385 movl(limit, result);
9386 // Fallthru to tail compare
9387 }
9389 // Compare 4-byte vectors
9390 andl(limit, 0xfffffffc); // vector count (in bytes)
9391 jccb(Assembler::zero, COMPARE_CHAR);
9393 lea(ary1, Address(ary1, limit, Address::times_1));
9394 lea(ary2, Address(ary2, limit, Address::times_1));
9395 negptr(limit);
9397 bind(COMPARE_VECTORS);
9398 movl(chr, Address(ary1, limit, Address::times_1));
9399 cmpl(chr, Address(ary2, limit, Address::times_1));
9400 jccb(Assembler::notEqual, FALSE_LABEL);
9401 addptr(limit, 4);
9402 jcc(Assembler::notZero, COMPARE_VECTORS);
9404 // Compare trailing char (final 2 bytes), if any
9405 bind(COMPARE_CHAR);
9406 testl(result, 0x2); // tail char
9407 jccb(Assembler::zero, TRUE_LABEL);
9408 load_unsigned_short(chr, Address(ary1, 0));
9409 load_unsigned_short(limit, Address(ary2, 0));
9410 cmpl(chr, limit);
9411 jccb(Assembler::notEqual, FALSE_LABEL);
9413 bind(TRUE_LABEL);
9414 movl(result, 1); // return true
9415 jmpb(DONE);
9417 bind(FALSE_LABEL);
9418 xorl(result, result); // return false
9420 // That's it
9421 bind(DONE);
9422 }
9424 #ifdef PRODUCT
9425 #define BLOCK_COMMENT(str) /* nothing */
9426 #else
9427 #define BLOCK_COMMENT(str) block_comment(str)
9428 #endif
9430 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
9431 void MacroAssembler::generate_fill(BasicType t, bool aligned,
9432 Register to, Register value, Register count,
9433 Register rtmp, XMMRegister xtmp) {
9434 assert_different_registers(to, value, count, rtmp);
9435 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
9436 Label L_fill_2_bytes, L_fill_4_bytes;
9438 int shift = -1;
9439 switch (t) {
9440 case T_BYTE:
9441 shift = 2;
9442 break;
9443 case T_SHORT:
9444 shift = 1;
9445 break;
9446 case T_INT:
9447 shift = 0;
9448 break;
9449 default: ShouldNotReachHere();
9450 }
9452 if (t == T_BYTE) {
9453 andl(value, 0xff);
9454 movl(rtmp, value);
9455 shll(rtmp, 8);
9456 orl(value, rtmp);
9457 }
9458 if (t == T_SHORT) {
9459 andl(value, 0xffff);
9460 }
9461 if (t == T_BYTE || t == T_SHORT) {
9462 movl(rtmp, value);
9463 shll(rtmp, 16);
9464 orl(value, rtmp);
9465 }
9467 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
9468 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
9469 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
9470 // align source address at 4 bytes address boundary
9471 if (t == T_BYTE) {
9472 // One byte misalignment happens only for byte arrays
9473 testptr(to, 1);
9474 jccb(Assembler::zero, L_skip_align1);
9475 movb(Address(to, 0), value);
9476 increment(to);
9477 decrement(count);
9478 BIND(L_skip_align1);
9479 }
9480 // Two bytes misalignment happens only for byte and short (char) arrays
9481 testptr(to, 2);
9482 jccb(Assembler::zero, L_skip_align2);
9483 movw(Address(to, 0), value);
9484 addptr(to, 2);
9485 subl(count, 1<<(shift-1));
9486 BIND(L_skip_align2);
9487 }
9488 if (UseSSE < 2) {
9489 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
9490 // Fill 32-byte chunks
9491 subl(count, 8 << shift);
9492 jcc(Assembler::less, L_check_fill_8_bytes);
9493 align(16);
9495 BIND(L_fill_32_bytes_loop);
9497 for (int i = 0; i < 32; i += 4) {
9498 movl(Address(to, i), value);
9499 }
9501 addptr(to, 32);
9502 subl(count, 8 << shift);
9503 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
9504 BIND(L_check_fill_8_bytes);
9505 addl(count, 8 << shift);
9506 jccb(Assembler::zero, L_exit);
9507 jmpb(L_fill_8_bytes);
9509 //
9510 // length is too short, just fill qwords
9511 //
9512 BIND(L_fill_8_bytes_loop);
9513 movl(Address(to, 0), value);
9514 movl(Address(to, 4), value);
9515 addptr(to, 8);
9516 BIND(L_fill_8_bytes);
9517 subl(count, 1 << (shift + 1));
9518 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
9519 // fall through to fill 4 bytes
9520 } else {
9521 Label L_fill_32_bytes;
9522 if (!UseUnalignedLoadStores) {
9523 // align to 8 bytes, we know we are 4 byte aligned to start
9524 testptr(to, 4);
9525 jccb(Assembler::zero, L_fill_32_bytes);
9526 movl(Address(to, 0), value);
9527 addptr(to, 4);
9528 subl(count, 1<<shift);
9529 }
9530 BIND(L_fill_32_bytes);
9531 {
9532 assert( UseSSE >= 2, "supported cpu only" );
9533 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
9534 // Fill 32-byte chunks
9535 movdl(xtmp, value);
9536 pshufd(xtmp, xtmp, 0);
9538 subl(count, 8 << shift);
9539 jcc(Assembler::less, L_check_fill_8_bytes);
9540 align(16);
9542 BIND(L_fill_32_bytes_loop);
9544 if (UseUnalignedLoadStores) {
9545 movdqu(Address(to, 0), xtmp);
9546 movdqu(Address(to, 16), xtmp);
9547 } else {
9548 movq(Address(to, 0), xtmp);
9549 movq(Address(to, 8), xtmp);
9550 movq(Address(to, 16), xtmp);
9551 movq(Address(to, 24), xtmp);
9552 }
9554 addptr(to, 32);
9555 subl(count, 8 << shift);
9556 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
9557 BIND(L_check_fill_8_bytes);
9558 addl(count, 8 << shift);
9559 jccb(Assembler::zero, L_exit);
9560 jmpb(L_fill_8_bytes);
9562 //
9563 // length is too short, just fill qwords
9564 //
9565 BIND(L_fill_8_bytes_loop);
9566 movq(Address(to, 0), xtmp);
9567 addptr(to, 8);
9568 BIND(L_fill_8_bytes);
9569 subl(count, 1 << (shift + 1));
9570 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
9571 }
9572 }
9573 // fill trailing 4 bytes
9574 BIND(L_fill_4_bytes);
9575 testl(count, 1<<shift);
9576 jccb(Assembler::zero, L_fill_2_bytes);
9577 movl(Address(to, 0), value);
9578 if (t == T_BYTE || t == T_SHORT) {
9579 addptr(to, 4);
9580 BIND(L_fill_2_bytes);
9581 // fill trailing 2 bytes
9582 testl(count, 1<<(shift-1));
9583 jccb(Assembler::zero, L_fill_byte);
9584 movw(Address(to, 0), value);
9585 if (t == T_BYTE) {
9586 addptr(to, 2);
9587 BIND(L_fill_byte);
9588 // fill trailing byte
9589 testl(count, 1);
9590 jccb(Assembler::zero, L_exit);
9591 movb(Address(to, 0), value);
9592 } else {
9593 BIND(L_fill_byte);
9594 }
9595 } else {
9596 BIND(L_fill_2_bytes);
9597 }
9598 BIND(L_exit);
9599 }
9600 #undef BIND
9601 #undef BLOCK_COMMENT
9604 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9605 switch (cond) {
9606 // Note some conditions are synonyms for others
9607 case Assembler::zero: return Assembler::notZero;
9608 case Assembler::notZero: return Assembler::zero;
9609 case Assembler::less: return Assembler::greaterEqual;
9610 case Assembler::lessEqual: return Assembler::greater;
9611 case Assembler::greater: return Assembler::lessEqual;
9612 case Assembler::greaterEqual: return Assembler::less;
9613 case Assembler::below: return Assembler::aboveEqual;
9614 case Assembler::belowEqual: return Assembler::above;
9615 case Assembler::above: return Assembler::belowEqual;
9616 case Assembler::aboveEqual: return Assembler::below;
9617 case Assembler::overflow: return Assembler::noOverflow;
9618 case Assembler::noOverflow: return Assembler::overflow;
9619 case Assembler::negative: return Assembler::positive;
9620 case Assembler::positive: return Assembler::negative;
9621 case Assembler::parity: return Assembler::noParity;
9622 case Assembler::noParity: return Assembler::parity;
9623 }
9624 ShouldNotReachHere(); return Assembler::overflow;
9625 }
9627 SkipIfEqual::SkipIfEqual(
9628 MacroAssembler* masm, const bool* flag_addr, bool value) {
9629 _masm = masm;
9630 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9631 _masm->jcc(Assembler::equal, _label);
9632 }
9634 SkipIfEqual::~SkipIfEqual() {
9635 _masm->bind(_label);
9636 }