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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp@da91efe96a93
src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
Sat, 01 Sep 2012 13:25:18 -0400
- author
- coleenp
- date
- Sat, 01 Sep 2012 13:25:18 -0400
- changeset 4037
- da91efe96a93
- parent 3969
- 1d7922586cf6
- child 4051
- 8a02ca5e5576
- permissions
- -rw-r--r--
6964458: Reimplement class meta-data storage to use native memory
Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes
Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland
Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
1 /*
2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc_interface/collectedHeap.hpp"
35 #include "memory/barrierSet.hpp"
36 #include "memory/cardTableModRefBS.hpp"
37 #include "nativeInst_x86.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/sharedRuntime.hpp"
42 // These masks are used to provide 128-bit aligned bitmasks to the XMM
43 // instructions, to allow sign-masking or sign-bit flipping. They allow
44 // fast versions of NegF/NegD and AbsF/AbsD.
46 // Note: 'double' and 'long long' have 32-bits alignment on x86.
47 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
48 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
49 // of 128-bits operands for SSE instructions.
50 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
51 // Store the value to a 128-bits operand.
52 operand[0] = lo;
53 operand[1] = hi;
54 return operand;
55 }
57 // Buffer for 128-bits masks used by SSE instructions.
58 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
60 // Static initialization during VM startup.
61 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
62 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
63 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
64 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
68 NEEDS_CLEANUP // remove this definitions ?
69 const Register IC_Klass = rax; // where the IC klass is cached
70 const Register SYNC_header = rax; // synchronization header
71 const Register SHIFT_count = rcx; // where count for shift operations must be
73 #define __ _masm->
76 static void select_different_registers(Register preserve,
77 Register extra,
78 Register &tmp1,
79 Register &tmp2) {
80 if (tmp1 == preserve) {
81 assert_different_registers(tmp1, tmp2, extra);
82 tmp1 = extra;
83 } else if (tmp2 == preserve) {
84 assert_different_registers(tmp1, tmp2, extra);
85 tmp2 = extra;
86 }
87 assert_different_registers(preserve, tmp1, tmp2);
88 }
92 static void select_different_registers(Register preserve,
93 Register extra,
94 Register &tmp1,
95 Register &tmp2,
96 Register &tmp3) {
97 if (tmp1 == preserve) {
98 assert_different_registers(tmp1, tmp2, tmp3, extra);
99 tmp1 = extra;
100 } else if (tmp2 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp2 = extra;
103 } else if (tmp3 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp3 = extra;
106 }
107 assert_different_registers(preserve, tmp1, tmp2, tmp3);
108 }
112 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
113 if (opr->is_constant()) {
114 LIR_Const* constant = opr->as_constant_ptr();
115 switch (constant->type()) {
116 case T_INT: {
117 return true;
118 }
120 default:
121 return false;
122 }
123 }
124 return false;
125 }
128 LIR_Opr LIR_Assembler::receiverOpr() {
129 return FrameMap::receiver_opr;
130 }
132 LIR_Opr LIR_Assembler::osrBufferPointer() {
133 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
134 }
136 //--------------fpu register translations-----------------------
139 address LIR_Assembler::float_constant(float f) {
140 address const_addr = __ float_constant(f);
141 if (const_addr == NULL) {
142 bailout("const section overflow");
143 return __ code()->consts()->start();
144 } else {
145 return const_addr;
146 }
147 }
150 address LIR_Assembler::double_constant(double d) {
151 address const_addr = __ double_constant(d);
152 if (const_addr == NULL) {
153 bailout("const section overflow");
154 return __ code()->consts()->start();
155 } else {
156 return const_addr;
157 }
158 }
161 void LIR_Assembler::set_24bit_FPU() {
162 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
163 }
165 void LIR_Assembler::reset_FPU() {
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
167 }
169 void LIR_Assembler::fpop() {
170 __ fpop();
171 }
173 void LIR_Assembler::fxch(int i) {
174 __ fxch(i);
175 }
177 void LIR_Assembler::fld(int i) {
178 __ fld_s(i);
179 }
181 void LIR_Assembler::ffree(int i) {
182 __ ffree(i);
183 }
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject());
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
207 } else {
208 ShouldNotReachHere();
209 }
210 }
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
224 //-------------------------------------------
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
243 Register base = addr->base()->as_pointer_register();
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes());
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (2 * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is NULL");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 Register receiver = FrameMap::receiver_opr->as_register();
341 Register ic_klass = IC_Klass;
342 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
343 const bool do_post_padding = VerifyOops || UseCompressedOops;
344 if (!do_post_padding) {
345 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
346 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
347 __ nop();
348 }
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_mirror_id);
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() {
378 // if rounding, must let FrameMap know!
380 // The frame_map records size in slots (32bit word)
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size);
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
403 int offset = code_offset();
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
416 __ end_a_stub();
418 return offset;
419 }
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
431 int offset = code_offset();
433 // Fetch the exception from TLS and clear out exception related thread state
434 __ get_thread(rsi);
435 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
436 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
437 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439 __ bind(_unwind_handler_entry);
440 __ verify_not_null_oop(rax);
441 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
442 __ mov(rsi, rax); // Preserve the exception
443 }
445 // Preform needed unlocking
446 MonitorExitStub* stub = NULL;
447 if (method()->is_synchronized()) {
448 monitor_address(0, FrameMap::rax_opr);
449 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
450 __ unlock_object(rdi, rbx, rax, *stub->entry());
451 __ bind(*stub->continuation());
452 }
454 if (compilation()->env()->dtrace_method_probes()) {
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
458 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
459 }
461 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
462 __ mov(rax, rsi); // Restore the exception
463 }
465 // remove the activation and dispatch to the unwind handler
466 __ remove_frame(initial_frame_size_in_bytes());
467 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
469 // Emit the slow path assembly
470 if (stub != NULL) {
471 stub->emit_code(this);
472 }
474 return offset;
475 }
478 int LIR_Assembler::emit_deopt_handler() {
479 // if the last instruction is a call (typically to do a throw which
480 // is coming at the end after block reordering) the return address
481 // must still point into the code area in order to avoid assertion
482 // failures when searching for the corresponding bci => add a nop
483 // (was bug 5/14/1999 - gri)
484 __ nop();
486 // generate code for exception handler
487 address handler_base = __ start_a_stub(deopt_handler_size);
488 if (handler_base == NULL) {
489 // not enough space left for the handler
490 bailout("deopt handler overflow");
491 return -1;
492 }
494 int offset = code_offset();
495 InternalAddress here(__ pc());
497 __ pushptr(here.addr());
498 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
499 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
500 __ end_a_stub();
502 return offset;
503 }
506 // This is the fast version of java.lang.String.compare; it has not
507 // OSR-entry and therefore, we generate a slow version for OSR's
508 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
509 __ movptr (rbx, rcx); // receiver is in rcx
510 __ movptr (rax, arg1->as_register());
512 // Get addresses of first characters from both Strings
513 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
514 if (java_lang_String::has_offset_field()) {
515 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
516 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
517 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
518 } else {
519 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
520 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
521 }
523 // rbx, may be NULL
524 add_debug_info_for_null_check_here(info);
525 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
526 if (java_lang_String::has_offset_field()) {
527 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
528 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
529 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
530 } else {
531 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
532 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
533 }
535 // compute minimum length (in rax) and difference of lengths (on top of stack)
536 __ mov (rcx, rbx);
537 __ subptr(rbx, rax); // subtract lengths
538 __ push (rbx); // result
539 __ cmov (Assembler::lessEqual, rax, rcx);
541 // is minimum length 0?
542 Label noLoop, haveResult;
543 __ testptr (rax, rax);
544 __ jcc (Assembler::zero, noLoop);
546 // compare first characters
547 __ load_unsigned_short(rcx, Address(rdi, 0));
548 __ load_unsigned_short(rbx, Address(rsi, 0));
549 __ subl(rcx, rbx);
550 __ jcc(Assembler::notZero, haveResult);
551 // starting loop
552 __ decrement(rax); // we already tested index: skip one
553 __ jcc(Assembler::zero, noLoop);
555 // set rsi.edi to the end of the arrays (arrays have same length)
556 // negate the index
558 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
559 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
560 __ negptr(rax);
562 // compare the strings in a loop
564 Label loop;
565 __ align(wordSize);
566 __ bind(loop);
567 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
568 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
569 __ subl(rcx, rbx);
570 __ jcc(Assembler::notZero, haveResult);
571 __ increment(rax);
572 __ jcc(Assembler::notZero, loop);
574 // strings are equal up to min length
576 __ bind(noLoop);
577 __ pop(rax);
578 return_op(LIR_OprFact::illegalOpr);
580 __ bind(haveResult);
581 // leave instruction is going to discard the TOS value
582 __ mov (rax, rcx); // result of call is in rax,
583 }
586 void LIR_Assembler::return_op(LIR_Opr result) {
587 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
588 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
589 assert(result->fpu() == 0, "result must already be on TOS");
590 }
592 // Pop the stack before the safepoint code
593 __ remove_frame(initial_frame_size_in_bytes());
595 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
597 // Note: we do not need to round double result; float result has the right precision
598 // the poll sets the condition code, but no data registers
599 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
600 relocInfo::poll_return_type);
602 if (Assembler::is_polling_page_far()) {
603 __ lea(rscratch1, polling_page);
604 __ relocate(relocInfo::poll_return_type);
605 __ testl(rax, Address(rscratch1, 0));
606 } else {
607 __ testl(rax, polling_page);
608 }
609 __ ret(0);
610 }
613 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
614 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
615 relocInfo::poll_type);
616 guarantee(info != NULL, "Shouldn't be NULL");
617 int offset = __ offset();
618 if (Assembler::is_polling_page_far()) {
619 __ lea(rscratch1, polling_page);
620 offset = __ offset();
621 add_debug_info_for_branch(info);
622 __ testl(rax, Address(rscratch1, 0));
623 } else {
624 add_debug_info_for_branch(info);
625 __ testl(rax, polling_page);
626 }
627 return offset;
628 }
631 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
632 if (from_reg != to_reg) __ mov(to_reg, from_reg);
633 }
635 void LIR_Assembler::swap_reg(Register a, Register b) {
636 __ xchgptr(a, b);
637 }
640 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
641 assert(src->is_constant(), "should not call otherwise");
642 assert(dest->is_register(), "should not call otherwise");
643 LIR_Const* c = src->as_constant_ptr();
645 switch (c->type()) {
646 case T_INT: {
647 assert(patch_code == lir_patch_none, "no patching handled here");
648 __ movl(dest->as_register(), c->as_jint());
649 break;
650 }
652 case T_ADDRESS: {
653 assert(patch_code == lir_patch_none, "no patching handled here");
654 __ movptr(dest->as_register(), c->as_jint());
655 break;
656 }
658 case T_LONG: {
659 assert(patch_code == lir_patch_none, "no patching handled here");
660 #ifdef _LP64
661 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
662 #else
663 __ movptr(dest->as_register_lo(), c->as_jint_lo());
664 __ movptr(dest->as_register_hi(), c->as_jint_hi());
665 #endif // _LP64
666 break;
667 }
669 case T_OBJECT: {
670 if (patch_code != lir_patch_none) {
671 jobject2reg_with_patching(dest->as_register(), info);
672 } else {
673 __ movoop(dest->as_register(), c->as_jobject());
674 }
675 break;
676 }
678 case T_METADATA: {
679 if (patch_code != lir_patch_none) {
680 klass2reg_with_patching(dest->as_register(), info);
681 } else {
682 __ mov_metadata(dest->as_register(), c->as_metadata());
683 }
684 break;
685 }
687 case T_FLOAT: {
688 if (dest->is_single_xmm()) {
689 if (c->is_zero_float()) {
690 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
691 } else {
692 __ movflt(dest->as_xmm_float_reg(),
693 InternalAddress(float_constant(c->as_jfloat())));
694 }
695 } else {
696 assert(dest->is_single_fpu(), "must be");
697 assert(dest->fpu_regnr() == 0, "dest must be TOS");
698 if (c->is_zero_float()) {
699 __ fldz();
700 } else if (c->is_one_float()) {
701 __ fld1();
702 } else {
703 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
704 }
705 }
706 break;
707 }
709 case T_DOUBLE: {
710 if (dest->is_double_xmm()) {
711 if (c->is_zero_double()) {
712 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
713 } else {
714 __ movdbl(dest->as_xmm_double_reg(),
715 InternalAddress(double_constant(c->as_jdouble())));
716 }
717 } else {
718 assert(dest->is_double_fpu(), "must be");
719 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
720 if (c->is_zero_double()) {
721 __ fldz();
722 } else if (c->is_one_double()) {
723 __ fld1();
724 } else {
725 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
726 }
727 }
728 break;
729 }
731 default:
732 ShouldNotReachHere();
733 }
734 }
736 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
737 assert(src->is_constant(), "should not call otherwise");
738 assert(dest->is_stack(), "should not call otherwise");
739 LIR_Const* c = src->as_constant_ptr();
741 switch (c->type()) {
742 case T_INT: // fall through
743 case T_FLOAT:
744 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
745 break;
747 case T_ADDRESS:
748 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
749 break;
751 case T_OBJECT:
752 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
753 break;
755 case T_LONG: // fall through
756 case T_DOUBLE:
757 #ifdef _LP64
758 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
759 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
760 #else
761 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
762 lo_word_offset_in_bytes), c->as_jint_lo_bits());
763 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
764 hi_word_offset_in_bytes), c->as_jint_hi_bits());
765 #endif // _LP64
766 break;
768 default:
769 ShouldNotReachHere();
770 }
771 }
773 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
774 assert(src->is_constant(), "should not call otherwise");
775 assert(dest->is_address(), "should not call otherwise");
776 LIR_Const* c = src->as_constant_ptr();
777 LIR_Address* addr = dest->as_address_ptr();
779 int null_check_here = code_offset();
780 switch (type) {
781 case T_INT: // fall through
782 case T_FLOAT:
783 __ movl(as_Address(addr), c->as_jint_bits());
784 break;
786 case T_ADDRESS:
787 __ movptr(as_Address(addr), c->as_jint_bits());
788 break;
790 case T_OBJECT: // fall through
791 case T_ARRAY:
792 if (c->as_jobject() == NULL) {
793 if (UseCompressedOops && !wide) {
794 __ movl(as_Address(addr), (int32_t)NULL_WORD);
795 } else {
796 __ movptr(as_Address(addr), NULL_WORD);
797 }
798 } else {
799 if (is_literal_address(addr)) {
800 ShouldNotReachHere();
801 __ movoop(as_Address(addr, noreg), c->as_jobject());
802 } else {
803 #ifdef _LP64
804 __ movoop(rscratch1, c->as_jobject());
805 if (UseCompressedOops && !wide) {
806 __ encode_heap_oop(rscratch1);
807 null_check_here = code_offset();
808 __ movl(as_Address_lo(addr), rscratch1);
809 } else {
810 null_check_here = code_offset();
811 __ movptr(as_Address_lo(addr), rscratch1);
812 }
813 #else
814 __ movoop(as_Address(addr), c->as_jobject());
815 #endif
816 }
817 }
818 break;
820 case T_LONG: // fall through
821 case T_DOUBLE:
822 #ifdef _LP64
823 if (is_literal_address(addr)) {
824 ShouldNotReachHere();
825 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
826 } else {
827 __ movptr(r10, (intptr_t)c->as_jlong_bits());
828 null_check_here = code_offset();
829 __ movptr(as_Address_lo(addr), r10);
830 }
831 #else
832 // Always reachable in 32bit so this doesn't produce useless move literal
833 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
834 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
835 #endif // _LP64
836 break;
838 case T_BOOLEAN: // fall through
839 case T_BYTE:
840 __ movb(as_Address(addr), c->as_jint() & 0xFF);
841 break;
843 case T_CHAR: // fall through
844 case T_SHORT:
845 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
846 break;
848 default:
849 ShouldNotReachHere();
850 };
852 if (info != NULL) {
853 add_debug_info_for_null_check(null_check_here, info);
854 }
855 }
858 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
859 assert(src->is_register(), "should not call otherwise");
860 assert(dest->is_register(), "should not call otherwise");
862 // move between cpu-registers
863 if (dest->is_single_cpu()) {
864 #ifdef _LP64
865 if (src->type() == T_LONG) {
866 // Can do LONG -> OBJECT
867 move_regs(src->as_register_lo(), dest->as_register());
868 return;
869 }
870 #endif
871 assert(src->is_single_cpu(), "must match");
872 if (src->type() == T_OBJECT) {
873 __ verify_oop(src->as_register());
874 }
875 move_regs(src->as_register(), dest->as_register());
877 } else if (dest->is_double_cpu()) {
878 #ifdef _LP64
879 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
880 // Surprising to me but we can see move of a long to t_object
881 __ verify_oop(src->as_register());
882 move_regs(src->as_register(), dest->as_register_lo());
883 return;
884 }
885 #endif
886 assert(src->is_double_cpu(), "must match");
887 Register f_lo = src->as_register_lo();
888 Register f_hi = src->as_register_hi();
889 Register t_lo = dest->as_register_lo();
890 Register t_hi = dest->as_register_hi();
891 #ifdef _LP64
892 assert(f_hi == f_lo, "must be same");
893 assert(t_hi == t_lo, "must be same");
894 move_regs(f_lo, t_lo);
895 #else
896 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
899 if (f_lo == t_hi && f_hi == t_lo) {
900 swap_reg(f_lo, f_hi);
901 } else if (f_hi == t_lo) {
902 assert(f_lo != t_hi, "overwriting register");
903 move_regs(f_hi, t_hi);
904 move_regs(f_lo, t_lo);
905 } else {
906 assert(f_hi != t_lo, "overwriting register");
907 move_regs(f_lo, t_lo);
908 move_regs(f_hi, t_hi);
909 }
910 #endif // LP64
912 // special moves from fpu-register to xmm-register
913 // necessary for method results
914 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
915 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
916 __ fld_s(Address(rsp, 0));
917 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
918 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
919 __ fld_d(Address(rsp, 0));
920 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
921 __ fstp_s(Address(rsp, 0));
922 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
923 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
924 __ fstp_d(Address(rsp, 0));
925 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
927 // move between xmm-registers
928 } else if (dest->is_single_xmm()) {
929 assert(src->is_single_xmm(), "must match");
930 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
931 } else if (dest->is_double_xmm()) {
932 assert(src->is_double_xmm(), "must match");
933 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
935 // move between fpu-registers (no instruction necessary because of fpu-stack)
936 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
937 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
938 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
939 } else {
940 ShouldNotReachHere();
941 }
942 }
944 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
945 assert(src->is_register(), "should not call otherwise");
946 assert(dest->is_stack(), "should not call otherwise");
948 if (src->is_single_cpu()) {
949 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
950 if (type == T_OBJECT || type == T_ARRAY) {
951 __ verify_oop(src->as_register());
952 __ movptr (dst, src->as_register());
953 } else {
954 __ movl (dst, src->as_register());
955 }
957 } else if (src->is_double_cpu()) {
958 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
959 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
960 __ movptr (dstLO, src->as_register_lo());
961 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
963 } else if (src->is_single_xmm()) {
964 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
965 __ movflt(dst_addr, src->as_xmm_float_reg());
967 } else if (src->is_double_xmm()) {
968 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
969 __ movdbl(dst_addr, src->as_xmm_double_reg());
971 } else if (src->is_single_fpu()) {
972 assert(src->fpu_regnr() == 0, "argument must be on TOS");
973 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
974 if (pop_fpu_stack) __ fstp_s (dst_addr);
975 else __ fst_s (dst_addr);
977 } else if (src->is_double_fpu()) {
978 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
979 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
980 if (pop_fpu_stack) __ fstp_d (dst_addr);
981 else __ fst_d (dst_addr);
983 } else {
984 ShouldNotReachHere();
985 }
986 }
989 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
990 LIR_Address* to_addr = dest->as_address_ptr();
991 PatchingStub* patch = NULL;
992 Register compressed_src = rscratch1;
994 if (type == T_ARRAY || type == T_OBJECT) {
995 __ verify_oop(src->as_register());
996 #ifdef _LP64
997 if (UseCompressedOops && !wide) {
998 __ movptr(compressed_src, src->as_register());
999 __ encode_heap_oop(compressed_src);
1000 }
1001 #endif
1002 }
1004 if (patch_code != lir_patch_none) {
1005 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1006 Address toa = as_Address(to_addr);
1007 assert(toa.disp() != 0, "must have");
1008 }
1010 int null_check_here = code_offset();
1011 switch (type) {
1012 case T_FLOAT: {
1013 if (src->is_single_xmm()) {
1014 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1015 } else {
1016 assert(src->is_single_fpu(), "must be");
1017 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1018 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1019 else __ fst_s (as_Address(to_addr));
1020 }
1021 break;
1022 }
1024 case T_DOUBLE: {
1025 if (src->is_double_xmm()) {
1026 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1027 } else {
1028 assert(src->is_double_fpu(), "must be");
1029 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1030 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1031 else __ fst_d (as_Address(to_addr));
1032 }
1033 break;
1034 }
1036 case T_ARRAY: // fall through
1037 case T_OBJECT: // fall through
1038 if (UseCompressedOops && !wide) {
1039 __ movl(as_Address(to_addr), compressed_src);
1040 } else {
1041 __ movptr(as_Address(to_addr), src->as_register());
1042 }
1043 break;
1044 case T_ADDRESS:
1045 __ movptr(as_Address(to_addr), src->as_register());
1046 break;
1047 case T_INT:
1048 __ movl(as_Address(to_addr), src->as_register());
1049 break;
1051 case T_LONG: {
1052 Register from_lo = src->as_register_lo();
1053 Register from_hi = src->as_register_hi();
1054 #ifdef _LP64
1055 __ movptr(as_Address_lo(to_addr), from_lo);
1056 #else
1057 Register base = to_addr->base()->as_register();
1058 Register index = noreg;
1059 if (to_addr->index()->is_register()) {
1060 index = to_addr->index()->as_register();
1061 }
1062 if (base == from_lo || index == from_lo) {
1063 assert(base != from_hi, "can't be");
1064 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1065 __ movl(as_Address_hi(to_addr), from_hi);
1066 if (patch != NULL) {
1067 patching_epilog(patch, lir_patch_high, base, info);
1068 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1069 patch_code = lir_patch_low;
1070 }
1071 __ movl(as_Address_lo(to_addr), from_lo);
1072 } else {
1073 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1074 __ movl(as_Address_lo(to_addr), from_lo);
1075 if (patch != NULL) {
1076 patching_epilog(patch, lir_patch_low, base, info);
1077 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1078 patch_code = lir_patch_high;
1079 }
1080 __ movl(as_Address_hi(to_addr), from_hi);
1081 }
1082 #endif // _LP64
1083 break;
1084 }
1086 case T_BYTE: // fall through
1087 case T_BOOLEAN: {
1088 Register src_reg = src->as_register();
1089 Address dst_addr = as_Address(to_addr);
1090 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1091 __ movb(dst_addr, src_reg);
1092 break;
1093 }
1095 case T_CHAR: // fall through
1096 case T_SHORT:
1097 __ movw(as_Address(to_addr), src->as_register());
1098 break;
1100 default:
1101 ShouldNotReachHere();
1102 }
1103 if (info != NULL) {
1104 add_debug_info_for_null_check(null_check_here, info);
1105 }
1107 if (patch_code != lir_patch_none) {
1108 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1109 }
1110 }
1113 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1114 assert(src->is_stack(), "should not call otherwise");
1115 assert(dest->is_register(), "should not call otherwise");
1117 if (dest->is_single_cpu()) {
1118 if (type == T_ARRAY || type == T_OBJECT) {
1119 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1120 __ verify_oop(dest->as_register());
1121 } else {
1122 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1123 }
1125 } else if (dest->is_double_cpu()) {
1126 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1127 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1128 __ movptr(dest->as_register_lo(), src_addr_LO);
1129 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1131 } else if (dest->is_single_xmm()) {
1132 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1133 __ movflt(dest->as_xmm_float_reg(), src_addr);
1135 } else if (dest->is_double_xmm()) {
1136 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1137 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1139 } else if (dest->is_single_fpu()) {
1140 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1141 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1142 __ fld_s(src_addr);
1144 } else if (dest->is_double_fpu()) {
1145 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1146 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1147 __ fld_d(src_addr);
1149 } else {
1150 ShouldNotReachHere();
1151 }
1152 }
1155 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1156 if (src->is_single_stack()) {
1157 if (type == T_OBJECT || type == T_ARRAY) {
1158 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1159 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1160 } else {
1161 #ifndef _LP64
1162 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1163 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1164 #else
1165 //no pushl on 64bits
1166 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1167 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1168 #endif
1169 }
1171 } else if (src->is_double_stack()) {
1172 #ifdef _LP64
1173 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1174 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1175 #else
1176 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1177 // push and pop the part at src + wordSize, adding wordSize for the previous push
1178 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1179 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1180 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1181 #endif // _LP64
1183 } else {
1184 ShouldNotReachHere();
1185 }
1186 }
1189 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1190 assert(src->is_address(), "should not call otherwise");
1191 assert(dest->is_register(), "should not call otherwise");
1193 LIR_Address* addr = src->as_address_ptr();
1194 Address from_addr = as_Address(addr);
1196 switch (type) {
1197 case T_BOOLEAN: // fall through
1198 case T_BYTE: // fall through
1199 case T_CHAR: // fall through
1200 case T_SHORT:
1201 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1202 // on pre P6 processors we may get partial register stalls
1203 // so blow away the value of to_rinfo before loading a
1204 // partial word into it. Do it here so that it precedes
1205 // the potential patch point below.
1206 __ xorptr(dest->as_register(), dest->as_register());
1207 }
1208 break;
1209 }
1211 PatchingStub* patch = NULL;
1212 if (patch_code != lir_patch_none) {
1213 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1214 assert(from_addr.disp() != 0, "must have");
1215 }
1216 if (info != NULL) {
1217 add_debug_info_for_null_check_here(info);
1218 }
1220 switch (type) {
1221 case T_FLOAT: {
1222 if (dest->is_single_xmm()) {
1223 __ movflt(dest->as_xmm_float_reg(), from_addr);
1224 } else {
1225 assert(dest->is_single_fpu(), "must be");
1226 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1227 __ fld_s(from_addr);
1228 }
1229 break;
1230 }
1232 case T_DOUBLE: {
1233 if (dest->is_double_xmm()) {
1234 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1235 } else {
1236 assert(dest->is_double_fpu(), "must be");
1237 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1238 __ fld_d(from_addr);
1239 }
1240 break;
1241 }
1243 case T_OBJECT: // fall through
1244 case T_ARRAY: // fall through
1245 if (UseCompressedOops && !wide) {
1246 __ movl(dest->as_register(), from_addr);
1247 } else {
1248 __ movptr(dest->as_register(), from_addr);
1249 }
1250 break;
1252 case T_ADDRESS:
1253 __ movptr(dest->as_register(), from_addr);
1254 break;
1255 case T_INT:
1256 __ movl(dest->as_register(), from_addr);
1257 break;
1259 case T_LONG: {
1260 Register to_lo = dest->as_register_lo();
1261 Register to_hi = dest->as_register_hi();
1262 #ifdef _LP64
1263 __ movptr(to_lo, as_Address_lo(addr));
1264 #else
1265 Register base = addr->base()->as_register();
1266 Register index = noreg;
1267 if (addr->index()->is_register()) {
1268 index = addr->index()->as_register();
1269 }
1270 if ((base == to_lo && index == to_hi) ||
1271 (base == to_hi && index == to_lo)) {
1272 // addresses with 2 registers are only formed as a result of
1273 // array access so this code will never have to deal with
1274 // patches or null checks.
1275 assert(info == NULL && patch == NULL, "must be");
1276 __ lea(to_hi, as_Address(addr));
1277 __ movl(to_lo, Address(to_hi, 0));
1278 __ movl(to_hi, Address(to_hi, BytesPerWord));
1279 } else if (base == to_lo || index == to_lo) {
1280 assert(base != to_hi, "can't be");
1281 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1282 __ movl(to_hi, as_Address_hi(addr));
1283 if (patch != NULL) {
1284 patching_epilog(patch, lir_patch_high, base, info);
1285 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1286 patch_code = lir_patch_low;
1287 }
1288 __ movl(to_lo, as_Address_lo(addr));
1289 } else {
1290 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1291 __ movl(to_lo, as_Address_lo(addr));
1292 if (patch != NULL) {
1293 patching_epilog(patch, lir_patch_low, base, info);
1294 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1295 patch_code = lir_patch_high;
1296 }
1297 __ movl(to_hi, as_Address_hi(addr));
1298 }
1299 #endif // _LP64
1300 break;
1301 }
1303 case T_BOOLEAN: // fall through
1304 case T_BYTE: {
1305 Register dest_reg = dest->as_register();
1306 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1307 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1308 __ movsbl(dest_reg, from_addr);
1309 } else {
1310 __ movb(dest_reg, from_addr);
1311 __ shll(dest_reg, 24);
1312 __ sarl(dest_reg, 24);
1313 }
1314 break;
1315 }
1317 case T_CHAR: {
1318 Register dest_reg = dest->as_register();
1319 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1320 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1321 __ movzwl(dest_reg, from_addr);
1322 } else {
1323 __ movw(dest_reg, from_addr);
1324 }
1325 break;
1326 }
1328 case T_SHORT: {
1329 Register dest_reg = dest->as_register();
1330 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1331 __ movswl(dest_reg, from_addr);
1332 } else {
1333 __ movw(dest_reg, from_addr);
1334 __ shll(dest_reg, 16);
1335 __ sarl(dest_reg, 16);
1336 }
1337 break;
1338 }
1340 default:
1341 ShouldNotReachHere();
1342 }
1344 if (patch != NULL) {
1345 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1346 }
1348 if (type == T_ARRAY || type == T_OBJECT) {
1349 #ifdef _LP64
1350 if (UseCompressedOops && !wide) {
1351 __ decode_heap_oop(dest->as_register());
1352 }
1353 #endif
1354 __ verify_oop(dest->as_register());
1355 }
1356 }
1359 void LIR_Assembler::prefetchr(LIR_Opr src) {
1360 LIR_Address* addr = src->as_address_ptr();
1361 Address from_addr = as_Address(addr);
1363 if (VM_Version::supports_sse()) {
1364 switch (ReadPrefetchInstr) {
1365 case 0:
1366 __ prefetchnta(from_addr); break;
1367 case 1:
1368 __ prefetcht0(from_addr); break;
1369 case 2:
1370 __ prefetcht2(from_addr); break;
1371 default:
1372 ShouldNotReachHere(); break;
1373 }
1374 } else if (VM_Version::supports_3dnow_prefetch()) {
1375 __ prefetchr(from_addr);
1376 }
1377 }
1380 void LIR_Assembler::prefetchw(LIR_Opr src) {
1381 LIR_Address* addr = src->as_address_ptr();
1382 Address from_addr = as_Address(addr);
1384 if (VM_Version::supports_sse()) {
1385 switch (AllocatePrefetchInstr) {
1386 case 0:
1387 __ prefetchnta(from_addr); break;
1388 case 1:
1389 __ prefetcht0(from_addr); break;
1390 case 2:
1391 __ prefetcht2(from_addr); break;
1392 case 3:
1393 __ prefetchw(from_addr); break;
1394 default:
1395 ShouldNotReachHere(); break;
1396 }
1397 } else if (VM_Version::supports_3dnow_prefetch()) {
1398 __ prefetchw(from_addr);
1399 }
1400 }
1403 NEEDS_CLEANUP; // This could be static?
1404 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1405 int elem_size = type2aelembytes(type);
1406 switch (elem_size) {
1407 case 1: return Address::times_1;
1408 case 2: return Address::times_2;
1409 case 4: return Address::times_4;
1410 case 8: return Address::times_8;
1411 }
1412 ShouldNotReachHere();
1413 return Address::no_scale;
1414 }
1417 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1418 switch (op->code()) {
1419 case lir_idiv:
1420 case lir_irem:
1421 arithmetic_idiv(op->code(),
1422 op->in_opr1(),
1423 op->in_opr2(),
1424 op->in_opr3(),
1425 op->result_opr(),
1426 op->info());
1427 break;
1428 default: ShouldNotReachHere(); break;
1429 }
1430 }
1432 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1433 #ifdef ASSERT
1434 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1435 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1436 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1437 #endif
1439 if (op->cond() == lir_cond_always) {
1440 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1441 __ jmp (*(op->label()));
1442 } else {
1443 Assembler::Condition acond = Assembler::zero;
1444 if (op->code() == lir_cond_float_branch) {
1445 assert(op->ublock() != NULL, "must have unordered successor");
1446 __ jcc(Assembler::parity, *(op->ublock()->label()));
1447 switch(op->cond()) {
1448 case lir_cond_equal: acond = Assembler::equal; break;
1449 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1450 case lir_cond_less: acond = Assembler::below; break;
1451 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1452 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1453 case lir_cond_greater: acond = Assembler::above; break;
1454 default: ShouldNotReachHere();
1455 }
1456 } else {
1457 switch (op->cond()) {
1458 case lir_cond_equal: acond = Assembler::equal; break;
1459 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1460 case lir_cond_less: acond = Assembler::less; break;
1461 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1462 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1463 case lir_cond_greater: acond = Assembler::greater; break;
1464 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1465 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1466 default: ShouldNotReachHere();
1467 }
1468 }
1469 __ jcc(acond,*(op->label()));
1470 }
1471 }
1473 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1474 LIR_Opr src = op->in_opr();
1475 LIR_Opr dest = op->result_opr();
1477 switch (op->bytecode()) {
1478 case Bytecodes::_i2l:
1479 #ifdef _LP64
1480 __ movl2ptr(dest->as_register_lo(), src->as_register());
1481 #else
1482 move_regs(src->as_register(), dest->as_register_lo());
1483 move_regs(src->as_register(), dest->as_register_hi());
1484 __ sarl(dest->as_register_hi(), 31);
1485 #endif // LP64
1486 break;
1488 case Bytecodes::_l2i:
1489 #ifdef _LP64
1490 __ movl(dest->as_register(), src->as_register_lo());
1491 #else
1492 move_regs(src->as_register_lo(), dest->as_register());
1493 #endif
1494 break;
1496 case Bytecodes::_i2b:
1497 move_regs(src->as_register(), dest->as_register());
1498 __ sign_extend_byte(dest->as_register());
1499 break;
1501 case Bytecodes::_i2c:
1502 move_regs(src->as_register(), dest->as_register());
1503 __ andl(dest->as_register(), 0xFFFF);
1504 break;
1506 case Bytecodes::_i2s:
1507 move_regs(src->as_register(), dest->as_register());
1508 __ sign_extend_short(dest->as_register());
1509 break;
1512 case Bytecodes::_f2d:
1513 case Bytecodes::_d2f:
1514 if (dest->is_single_xmm()) {
1515 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1516 } else if (dest->is_double_xmm()) {
1517 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1518 } else {
1519 assert(src->fpu() == dest->fpu(), "register must be equal");
1520 // do nothing (float result is rounded later through spilling)
1521 }
1522 break;
1524 case Bytecodes::_i2f:
1525 case Bytecodes::_i2d:
1526 if (dest->is_single_xmm()) {
1527 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1528 } else if (dest->is_double_xmm()) {
1529 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1530 } else {
1531 assert(dest->fpu() == 0, "result must be on TOS");
1532 __ movl(Address(rsp, 0), src->as_register());
1533 __ fild_s(Address(rsp, 0));
1534 }
1535 break;
1537 case Bytecodes::_f2i:
1538 case Bytecodes::_d2i:
1539 if (src->is_single_xmm()) {
1540 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1541 } else if (src->is_double_xmm()) {
1542 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1543 } else {
1544 assert(src->fpu() == 0, "input must be on TOS");
1545 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1546 __ fist_s(Address(rsp, 0));
1547 __ movl(dest->as_register(), Address(rsp, 0));
1548 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1549 }
1551 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1552 assert(op->stub() != NULL, "stub required");
1553 __ cmpl(dest->as_register(), 0x80000000);
1554 __ jcc(Assembler::equal, *op->stub()->entry());
1555 __ bind(*op->stub()->continuation());
1556 break;
1558 case Bytecodes::_l2f:
1559 case Bytecodes::_l2d:
1560 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1561 assert(dest->fpu() == 0, "result must be on TOS");
1563 __ movptr(Address(rsp, 0), src->as_register_lo());
1564 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1565 __ fild_d(Address(rsp, 0));
1566 // float result is rounded later through spilling
1567 break;
1569 case Bytecodes::_f2l:
1570 case Bytecodes::_d2l:
1571 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1572 assert(src->fpu() == 0, "input must be on TOS");
1573 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1575 // instruction sequence too long to inline it here
1576 {
1577 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1578 }
1579 break;
1581 default: ShouldNotReachHere();
1582 }
1583 }
1585 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1586 if (op->init_check()) {
1587 __ cmpb(Address(op->klass()->as_register(),
1588 InstanceKlass::init_state_offset()),
1589 InstanceKlass::fully_initialized);
1590 add_debug_info_for_null_check_here(op->stub()->info());
1591 __ jcc(Assembler::notEqual, *op->stub()->entry());
1592 }
1593 __ allocate_object(op->obj()->as_register(),
1594 op->tmp1()->as_register(),
1595 op->tmp2()->as_register(),
1596 op->header_size(),
1597 op->object_size(),
1598 op->klass()->as_register(),
1599 *op->stub()->entry());
1600 __ bind(*op->stub()->continuation());
1601 }
1603 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1604 Register len = op->len()->as_register();
1605 LP64_ONLY( __ movslq(len, len); )
1607 if (UseSlowPath ||
1608 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1609 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1610 __ jmp(*op->stub()->entry());
1611 } else {
1612 Register tmp1 = op->tmp1()->as_register();
1613 Register tmp2 = op->tmp2()->as_register();
1614 Register tmp3 = op->tmp3()->as_register();
1615 if (len == tmp1) {
1616 tmp1 = tmp3;
1617 } else if (len == tmp2) {
1618 tmp2 = tmp3;
1619 } else if (len == tmp3) {
1620 // everything is ok
1621 } else {
1622 __ mov(tmp3, len);
1623 }
1624 __ allocate_array(op->obj()->as_register(),
1625 len,
1626 tmp1,
1627 tmp2,
1628 arrayOopDesc::header_size(op->type()),
1629 array_element_size(op->type()),
1630 op->klass()->as_register(),
1631 *op->stub()->entry());
1632 }
1633 __ bind(*op->stub()->continuation());
1634 }
1636 void LIR_Assembler::type_profile_helper(Register mdo,
1637 ciMethodData *md, ciProfileData *data,
1638 Register recv, Label* update_done) {
1639 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1640 Label next_test;
1641 // See if the receiver is receiver[n].
1642 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1643 __ jccb(Assembler::notEqual, next_test);
1644 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1645 __ addptr(data_addr, DataLayout::counter_increment);
1646 __ jmp(*update_done);
1647 __ bind(next_test);
1648 }
1650 // Didn't find receiver; find next empty slot and fill it in
1651 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1652 Label next_test;
1653 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1654 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1655 __ jccb(Assembler::notEqual, next_test);
1656 __ movptr(recv_addr, recv);
1657 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1658 __ jmp(*update_done);
1659 __ bind(next_test);
1660 }
1661 }
1663 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1664 // we always need a stub for the failure case.
1665 CodeStub* stub = op->stub();
1666 Register obj = op->object()->as_register();
1667 Register k_RInfo = op->tmp1()->as_register();
1668 Register klass_RInfo = op->tmp2()->as_register();
1669 Register dst = op->result_opr()->as_register();
1670 ciKlass* k = op->klass();
1671 Register Rtmp1 = noreg;
1673 // check if it needs to be profiled
1674 ciMethodData* md;
1675 ciProfileData* data;
1677 if (op->should_profile()) {
1678 ciMethod* method = op->profiled_method();
1679 assert(method != NULL, "Should have method");
1680 int bci = op->profiled_bci();
1681 md = method->method_data_or_null();
1682 assert(md != NULL, "Sanity");
1683 data = md->bci_to_data(bci);
1684 assert(data != NULL, "need data for type check");
1685 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1686 }
1687 Label profile_cast_success, profile_cast_failure;
1688 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1689 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1691 if (obj == k_RInfo) {
1692 k_RInfo = dst;
1693 } else if (obj == klass_RInfo) {
1694 klass_RInfo = dst;
1695 }
1696 if (k->is_loaded() && !UseCompressedOops) {
1697 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1698 } else {
1699 Rtmp1 = op->tmp3()->as_register();
1700 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1701 }
1703 assert_different_registers(obj, k_RInfo, klass_RInfo);
1704 if (!k->is_loaded()) {
1705 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1706 } else {
1707 #ifdef _LP64
1708 __ mov_metadata(k_RInfo, k->constant_encoding());
1709 #endif // _LP64
1710 }
1711 assert(obj != k_RInfo, "must be different");
1713 __ cmpptr(obj, (int32_t)NULL_WORD);
1714 if (op->should_profile()) {
1715 Label not_null;
1716 __ jccb(Assembler::notEqual, not_null);
1717 // Object is null; update MDO and exit
1718 Register mdo = klass_RInfo;
1719 __ mov_metadata(mdo, md->constant_encoding());
1720 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1721 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1722 __ orl(data_addr, header_bits);
1723 __ jmp(*obj_is_null);
1724 __ bind(not_null);
1725 } else {
1726 __ jcc(Assembler::equal, *obj_is_null);
1727 }
1728 __ verify_oop(obj);
1730 if (op->fast_check()) {
1731 // get object class
1732 // not a safepoint as obj null check happens earlier
1733 #ifdef _LP64
1734 if (UseCompressedKlassPointers) {
1735 __ load_klass(Rtmp1, obj);
1736 __ cmpptr(k_RInfo, Rtmp1);
1737 } else {
1738 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1739 }
1740 #else
1741 if (k->is_loaded()) {
1742 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1743 } else {
1744 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1745 }
1746 #endif
1747 __ jcc(Assembler::notEqual, *failure_target);
1748 // successful cast, fall through to profile or jump
1749 } else {
1750 // get object class
1751 // not a safepoint as obj null check happens earlier
1752 __ load_klass(klass_RInfo, obj);
1753 if (k->is_loaded()) {
1754 // See if we get an immediate positive hit
1755 #ifdef _LP64
1756 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1757 #else
1758 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1759 #endif // _LP64
1760 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1761 __ jcc(Assembler::notEqual, *failure_target);
1762 // successful cast, fall through to profile or jump
1763 } else {
1764 // See if we get an immediate positive hit
1765 __ jcc(Assembler::equal, *success_target);
1766 // check for self
1767 #ifdef _LP64
1768 __ cmpptr(klass_RInfo, k_RInfo);
1769 #else
1770 __ cmpklass(klass_RInfo, k->constant_encoding());
1771 #endif // _LP64
1772 __ jcc(Assembler::equal, *success_target);
1774 __ push(klass_RInfo);
1775 #ifdef _LP64
1776 __ push(k_RInfo);
1777 #else
1778 __ pushklass(k->constant_encoding());
1779 #endif // _LP64
1780 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1781 __ pop(klass_RInfo);
1782 __ pop(klass_RInfo);
1783 // result is a boolean
1784 __ cmpl(klass_RInfo, 0);
1785 __ jcc(Assembler::equal, *failure_target);
1786 // successful cast, fall through to profile or jump
1787 }
1788 } else {
1789 // perform the fast part of the checking logic
1790 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1791 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1792 __ push(klass_RInfo);
1793 __ push(k_RInfo);
1794 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1795 __ pop(klass_RInfo);
1796 __ pop(k_RInfo);
1797 // result is a boolean
1798 __ cmpl(k_RInfo, 0);
1799 __ jcc(Assembler::equal, *failure_target);
1800 // successful cast, fall through to profile or jump
1801 }
1802 }
1803 if (op->should_profile()) {
1804 Register mdo = klass_RInfo, recv = k_RInfo;
1805 __ bind(profile_cast_success);
1806 __ mov_metadata(mdo, md->constant_encoding());
1807 __ load_klass(recv, obj);
1808 Label update_done;
1809 type_profile_helper(mdo, md, data, recv, success);
1810 __ jmp(*success);
1812 __ bind(profile_cast_failure);
1813 __ mov_metadata(mdo, md->constant_encoding());
1814 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1815 __ subptr(counter_addr, DataLayout::counter_increment);
1816 __ jmp(*failure);
1817 }
1818 __ jmp(*success);
1819 }
1822 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1823 LIR_Code code = op->code();
1824 if (code == lir_store_check) {
1825 Register value = op->object()->as_register();
1826 Register array = op->array()->as_register();
1827 Register k_RInfo = op->tmp1()->as_register();
1828 Register klass_RInfo = op->tmp2()->as_register();
1829 Register Rtmp1 = op->tmp3()->as_register();
1831 CodeStub* stub = op->stub();
1833 // check if it needs to be profiled
1834 ciMethodData* md;
1835 ciProfileData* data;
1837 if (op->should_profile()) {
1838 ciMethod* method = op->profiled_method();
1839 assert(method != NULL, "Should have method");
1840 int bci = op->profiled_bci();
1841 md = method->method_data_or_null();
1842 assert(md != NULL, "Sanity");
1843 data = md->bci_to_data(bci);
1844 assert(data != NULL, "need data for type check");
1845 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1846 }
1847 Label profile_cast_success, profile_cast_failure, done;
1848 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1849 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1851 __ cmpptr(value, (int32_t)NULL_WORD);
1852 if (op->should_profile()) {
1853 Label not_null;
1854 __ jccb(Assembler::notEqual, not_null);
1855 // Object is null; update MDO and exit
1856 Register mdo = klass_RInfo;
1857 __ mov_metadata(mdo, md->constant_encoding());
1858 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1859 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1860 __ orl(data_addr, header_bits);
1861 __ jmp(done);
1862 __ bind(not_null);
1863 } else {
1864 __ jcc(Assembler::equal, done);
1865 }
1867 add_debug_info_for_null_check_here(op->info_for_exception());
1868 __ load_klass(k_RInfo, array);
1869 __ load_klass(klass_RInfo, value);
1871 // get instance klass (it's already uncompressed)
1872 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset()));
1873 // perform the fast part of the checking logic
1874 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1875 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1876 __ push(klass_RInfo);
1877 __ push(k_RInfo);
1878 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1879 __ pop(klass_RInfo);
1880 __ pop(k_RInfo);
1881 // result is a boolean
1882 __ cmpl(k_RInfo, 0);
1883 __ jcc(Assembler::equal, *failure_target);
1884 // fall through to the success case
1886 if (op->should_profile()) {
1887 Register mdo = klass_RInfo, recv = k_RInfo;
1888 __ bind(profile_cast_success);
1889 __ mov_metadata(mdo, md->constant_encoding());
1890 __ load_klass(recv, value);
1891 Label update_done;
1892 type_profile_helper(mdo, md, data, recv, &done);
1893 __ jmpb(done);
1895 __ bind(profile_cast_failure);
1896 __ mov_metadata(mdo, md->constant_encoding());
1897 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1898 __ subptr(counter_addr, DataLayout::counter_increment);
1899 __ jmp(*stub->entry());
1900 }
1902 __ bind(done);
1903 } else
1904 if (code == lir_checkcast) {
1905 Register obj = op->object()->as_register();
1906 Register dst = op->result_opr()->as_register();
1907 Label success;
1908 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1909 __ bind(success);
1910 if (dst != obj) {
1911 __ mov(dst, obj);
1912 }
1913 } else
1914 if (code == lir_instanceof) {
1915 Register obj = op->object()->as_register();
1916 Register dst = op->result_opr()->as_register();
1917 Label success, failure, done;
1918 emit_typecheck_helper(op, &success, &failure, &failure);
1919 __ bind(failure);
1920 __ xorptr(dst, dst);
1921 __ jmpb(done);
1922 __ bind(success);
1923 __ movptr(dst, 1);
1924 __ bind(done);
1925 } else {
1926 ShouldNotReachHere();
1927 }
1929 }
1932 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1933 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1934 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1935 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1936 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1937 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1938 Register addr = op->addr()->as_register();
1939 if (os::is_MP()) {
1940 __ lock();
1941 }
1942 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1944 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1945 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1946 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1947 Register newval = op->new_value()->as_register();
1948 Register cmpval = op->cmp_value()->as_register();
1949 assert(cmpval == rax, "wrong register");
1950 assert(newval != NULL, "new val must be register");
1951 assert(cmpval != newval, "cmp and new values must be in different registers");
1952 assert(cmpval != addr, "cmp and addr must be in different registers");
1953 assert(newval != addr, "new value and addr must be in different registers");
1955 if ( op->code() == lir_cas_obj) {
1956 #ifdef _LP64
1957 if (UseCompressedOops) {
1958 __ encode_heap_oop(cmpval);
1959 __ mov(rscratch1, newval);
1960 __ encode_heap_oop(rscratch1);
1961 if (os::is_MP()) {
1962 __ lock();
1963 }
1964 // cmpval (rax) is implicitly used by this instruction
1965 __ cmpxchgl(rscratch1, Address(addr, 0));
1966 } else
1967 #endif
1968 {
1969 if (os::is_MP()) {
1970 __ lock();
1971 }
1972 __ cmpxchgptr(newval, Address(addr, 0));
1973 }
1974 } else {
1975 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1976 if (os::is_MP()) {
1977 __ lock();
1978 }
1979 __ cmpxchgl(newval, Address(addr, 0));
1980 }
1981 #ifdef _LP64
1982 } else if (op->code() == lir_cas_long) {
1983 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1984 Register newval = op->new_value()->as_register_lo();
1985 Register cmpval = op->cmp_value()->as_register_lo();
1986 assert(cmpval == rax, "wrong register");
1987 assert(newval != NULL, "new val must be register");
1988 assert(cmpval != newval, "cmp and new values must be in different registers");
1989 assert(cmpval != addr, "cmp and addr must be in different registers");
1990 assert(newval != addr, "new value and addr must be in different registers");
1991 if (os::is_MP()) {
1992 __ lock();
1993 }
1994 __ cmpxchgq(newval, Address(addr, 0));
1995 #endif // _LP64
1996 } else {
1997 Unimplemented();
1998 }
1999 }
2001 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2002 Assembler::Condition acond, ncond;
2003 switch (condition) {
2004 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2005 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2006 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2007 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2008 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2009 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2010 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2011 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2012 default: ShouldNotReachHere();
2013 }
2015 if (opr1->is_cpu_register()) {
2016 reg2reg(opr1, result);
2017 } else if (opr1->is_stack()) {
2018 stack2reg(opr1, result, result->type());
2019 } else if (opr1->is_constant()) {
2020 const2reg(opr1, result, lir_patch_none, NULL);
2021 } else {
2022 ShouldNotReachHere();
2023 }
2025 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2026 // optimized version that does not require a branch
2027 if (opr2->is_single_cpu()) {
2028 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2029 __ cmov(ncond, result->as_register(), opr2->as_register());
2030 } else if (opr2->is_double_cpu()) {
2031 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2032 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2033 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2034 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2035 } else if (opr2->is_single_stack()) {
2036 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2037 } else if (opr2->is_double_stack()) {
2038 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2039 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2040 } else {
2041 ShouldNotReachHere();
2042 }
2044 } else {
2045 Label skip;
2046 __ jcc (acond, skip);
2047 if (opr2->is_cpu_register()) {
2048 reg2reg(opr2, result);
2049 } else if (opr2->is_stack()) {
2050 stack2reg(opr2, result, result->type());
2051 } else if (opr2->is_constant()) {
2052 const2reg(opr2, result, lir_patch_none, NULL);
2053 } else {
2054 ShouldNotReachHere();
2055 }
2056 __ bind(skip);
2057 }
2058 }
2061 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2062 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2064 if (left->is_single_cpu()) {
2065 assert(left == dest, "left and dest must be equal");
2066 Register lreg = left->as_register();
2068 if (right->is_single_cpu()) {
2069 // cpu register - cpu register
2070 Register rreg = right->as_register();
2071 switch (code) {
2072 case lir_add: __ addl (lreg, rreg); break;
2073 case lir_sub: __ subl (lreg, rreg); break;
2074 case lir_mul: __ imull(lreg, rreg); break;
2075 default: ShouldNotReachHere();
2076 }
2078 } else if (right->is_stack()) {
2079 // cpu register - stack
2080 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2081 switch (code) {
2082 case lir_add: __ addl(lreg, raddr); break;
2083 case lir_sub: __ subl(lreg, raddr); break;
2084 default: ShouldNotReachHere();
2085 }
2087 } else if (right->is_constant()) {
2088 // cpu register - constant
2089 jint c = right->as_constant_ptr()->as_jint();
2090 switch (code) {
2091 case lir_add: {
2092 __ incrementl(lreg, c);
2093 break;
2094 }
2095 case lir_sub: {
2096 __ decrementl(lreg, c);
2097 break;
2098 }
2099 default: ShouldNotReachHere();
2100 }
2102 } else {
2103 ShouldNotReachHere();
2104 }
2106 } else if (left->is_double_cpu()) {
2107 assert(left == dest, "left and dest must be equal");
2108 Register lreg_lo = left->as_register_lo();
2109 Register lreg_hi = left->as_register_hi();
2111 if (right->is_double_cpu()) {
2112 // cpu register - cpu register
2113 Register rreg_lo = right->as_register_lo();
2114 Register rreg_hi = right->as_register_hi();
2115 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2116 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2117 switch (code) {
2118 case lir_add:
2119 __ addptr(lreg_lo, rreg_lo);
2120 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2121 break;
2122 case lir_sub:
2123 __ subptr(lreg_lo, rreg_lo);
2124 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2125 break;
2126 case lir_mul:
2127 #ifdef _LP64
2128 __ imulq(lreg_lo, rreg_lo);
2129 #else
2130 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2131 __ imull(lreg_hi, rreg_lo);
2132 __ imull(rreg_hi, lreg_lo);
2133 __ addl (rreg_hi, lreg_hi);
2134 __ mull (rreg_lo);
2135 __ addl (lreg_hi, rreg_hi);
2136 #endif // _LP64
2137 break;
2138 default:
2139 ShouldNotReachHere();
2140 }
2142 } else if (right->is_constant()) {
2143 // cpu register - constant
2144 #ifdef _LP64
2145 jlong c = right->as_constant_ptr()->as_jlong_bits();
2146 __ movptr(r10, (intptr_t) c);
2147 switch (code) {
2148 case lir_add:
2149 __ addptr(lreg_lo, r10);
2150 break;
2151 case lir_sub:
2152 __ subptr(lreg_lo, r10);
2153 break;
2154 default:
2155 ShouldNotReachHere();
2156 }
2157 #else
2158 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2159 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2160 switch (code) {
2161 case lir_add:
2162 __ addptr(lreg_lo, c_lo);
2163 __ adcl(lreg_hi, c_hi);
2164 break;
2165 case lir_sub:
2166 __ subptr(lreg_lo, c_lo);
2167 __ sbbl(lreg_hi, c_hi);
2168 break;
2169 default:
2170 ShouldNotReachHere();
2171 }
2172 #endif // _LP64
2174 } else {
2175 ShouldNotReachHere();
2176 }
2178 } else if (left->is_single_xmm()) {
2179 assert(left == dest, "left and dest must be equal");
2180 XMMRegister lreg = left->as_xmm_float_reg();
2182 if (right->is_single_xmm()) {
2183 XMMRegister rreg = right->as_xmm_float_reg();
2184 switch (code) {
2185 case lir_add: __ addss(lreg, rreg); break;
2186 case lir_sub: __ subss(lreg, rreg); break;
2187 case lir_mul_strictfp: // fall through
2188 case lir_mul: __ mulss(lreg, rreg); break;
2189 case lir_div_strictfp: // fall through
2190 case lir_div: __ divss(lreg, rreg); break;
2191 default: ShouldNotReachHere();
2192 }
2193 } else {
2194 Address raddr;
2195 if (right->is_single_stack()) {
2196 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2197 } else if (right->is_constant()) {
2198 // hack for now
2199 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2200 } else {
2201 ShouldNotReachHere();
2202 }
2203 switch (code) {
2204 case lir_add: __ addss(lreg, raddr); break;
2205 case lir_sub: __ subss(lreg, raddr); break;
2206 case lir_mul_strictfp: // fall through
2207 case lir_mul: __ mulss(lreg, raddr); break;
2208 case lir_div_strictfp: // fall through
2209 case lir_div: __ divss(lreg, raddr); break;
2210 default: ShouldNotReachHere();
2211 }
2212 }
2214 } else if (left->is_double_xmm()) {
2215 assert(left == dest, "left and dest must be equal");
2217 XMMRegister lreg = left->as_xmm_double_reg();
2218 if (right->is_double_xmm()) {
2219 XMMRegister rreg = right->as_xmm_double_reg();
2220 switch (code) {
2221 case lir_add: __ addsd(lreg, rreg); break;
2222 case lir_sub: __ subsd(lreg, rreg); break;
2223 case lir_mul_strictfp: // fall through
2224 case lir_mul: __ mulsd(lreg, rreg); break;
2225 case lir_div_strictfp: // fall through
2226 case lir_div: __ divsd(lreg, rreg); break;
2227 default: ShouldNotReachHere();
2228 }
2229 } else {
2230 Address raddr;
2231 if (right->is_double_stack()) {
2232 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2233 } else if (right->is_constant()) {
2234 // hack for now
2235 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2236 } else {
2237 ShouldNotReachHere();
2238 }
2239 switch (code) {
2240 case lir_add: __ addsd(lreg, raddr); break;
2241 case lir_sub: __ subsd(lreg, raddr); break;
2242 case lir_mul_strictfp: // fall through
2243 case lir_mul: __ mulsd(lreg, raddr); break;
2244 case lir_div_strictfp: // fall through
2245 case lir_div: __ divsd(lreg, raddr); break;
2246 default: ShouldNotReachHere();
2247 }
2248 }
2250 } else if (left->is_single_fpu()) {
2251 assert(dest->is_single_fpu(), "fpu stack allocation required");
2253 if (right->is_single_fpu()) {
2254 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2256 } else {
2257 assert(left->fpu_regnr() == 0, "left must be on TOS");
2258 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2260 Address raddr;
2261 if (right->is_single_stack()) {
2262 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2263 } else if (right->is_constant()) {
2264 address const_addr = float_constant(right->as_jfloat());
2265 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2266 // hack for now
2267 raddr = __ as_Address(InternalAddress(const_addr));
2268 } else {
2269 ShouldNotReachHere();
2270 }
2272 switch (code) {
2273 case lir_add: __ fadd_s(raddr); break;
2274 case lir_sub: __ fsub_s(raddr); break;
2275 case lir_mul_strictfp: // fall through
2276 case lir_mul: __ fmul_s(raddr); break;
2277 case lir_div_strictfp: // fall through
2278 case lir_div: __ fdiv_s(raddr); break;
2279 default: ShouldNotReachHere();
2280 }
2281 }
2283 } else if (left->is_double_fpu()) {
2284 assert(dest->is_double_fpu(), "fpu stack allocation required");
2286 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2287 // Double values require special handling for strictfp mul/div on x86
2288 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2289 __ fmulp(left->fpu_regnrLo() + 1);
2290 }
2292 if (right->is_double_fpu()) {
2293 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2295 } else {
2296 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2297 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2299 Address raddr;
2300 if (right->is_double_stack()) {
2301 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2302 } else if (right->is_constant()) {
2303 // hack for now
2304 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2305 } else {
2306 ShouldNotReachHere();
2307 }
2309 switch (code) {
2310 case lir_add: __ fadd_d(raddr); break;
2311 case lir_sub: __ fsub_d(raddr); break;
2312 case lir_mul_strictfp: // fall through
2313 case lir_mul: __ fmul_d(raddr); break;
2314 case lir_div_strictfp: // fall through
2315 case lir_div: __ fdiv_d(raddr); break;
2316 default: ShouldNotReachHere();
2317 }
2318 }
2320 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2321 // Double values require special handling for strictfp mul/div on x86
2322 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2323 __ fmulp(dest->fpu_regnrLo() + 1);
2324 }
2326 } else if (left->is_single_stack() || left->is_address()) {
2327 assert(left == dest, "left and dest must be equal");
2329 Address laddr;
2330 if (left->is_single_stack()) {
2331 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2332 } else if (left->is_address()) {
2333 laddr = as_Address(left->as_address_ptr());
2334 } else {
2335 ShouldNotReachHere();
2336 }
2338 if (right->is_single_cpu()) {
2339 Register rreg = right->as_register();
2340 switch (code) {
2341 case lir_add: __ addl(laddr, rreg); break;
2342 case lir_sub: __ subl(laddr, rreg); break;
2343 default: ShouldNotReachHere();
2344 }
2345 } else if (right->is_constant()) {
2346 jint c = right->as_constant_ptr()->as_jint();
2347 switch (code) {
2348 case lir_add: {
2349 __ incrementl(laddr, c);
2350 break;
2351 }
2352 case lir_sub: {
2353 __ decrementl(laddr, c);
2354 break;
2355 }
2356 default: ShouldNotReachHere();
2357 }
2358 } else {
2359 ShouldNotReachHere();
2360 }
2362 } else {
2363 ShouldNotReachHere();
2364 }
2365 }
2367 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2368 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2369 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2370 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2372 bool left_is_tos = (left_index == 0);
2373 bool dest_is_tos = (dest_index == 0);
2374 int non_tos_index = (left_is_tos ? right_index : left_index);
2376 switch (code) {
2377 case lir_add:
2378 if (pop_fpu_stack) __ faddp(non_tos_index);
2379 else if (dest_is_tos) __ fadd (non_tos_index);
2380 else __ fadda(non_tos_index);
2381 break;
2383 case lir_sub:
2384 if (left_is_tos) {
2385 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2386 else if (dest_is_tos) __ fsub (non_tos_index);
2387 else __ fsubra(non_tos_index);
2388 } else {
2389 if (pop_fpu_stack) __ fsubp (non_tos_index);
2390 else if (dest_is_tos) __ fsubr (non_tos_index);
2391 else __ fsuba (non_tos_index);
2392 }
2393 break;
2395 case lir_mul_strictfp: // fall through
2396 case lir_mul:
2397 if (pop_fpu_stack) __ fmulp(non_tos_index);
2398 else if (dest_is_tos) __ fmul (non_tos_index);
2399 else __ fmula(non_tos_index);
2400 break;
2402 case lir_div_strictfp: // fall through
2403 case lir_div:
2404 if (left_is_tos) {
2405 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2406 else if (dest_is_tos) __ fdiv (non_tos_index);
2407 else __ fdivra(non_tos_index);
2408 } else {
2409 if (pop_fpu_stack) __ fdivp (non_tos_index);
2410 else if (dest_is_tos) __ fdivr (non_tos_index);
2411 else __ fdiva (non_tos_index);
2412 }
2413 break;
2415 case lir_rem:
2416 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2417 __ fremr(noreg);
2418 break;
2420 default:
2421 ShouldNotReachHere();
2422 }
2423 }
2426 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2427 if (value->is_double_xmm()) {
2428 switch(code) {
2429 case lir_abs :
2430 {
2431 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2432 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2433 }
2434 __ andpd(dest->as_xmm_double_reg(),
2435 ExternalAddress((address)double_signmask_pool));
2436 }
2437 break;
2439 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2440 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2441 default : ShouldNotReachHere();
2442 }
2444 } else if (value->is_double_fpu()) {
2445 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2446 switch(code) {
2447 case lir_log : __ flog() ; break;
2448 case lir_log10 : __ flog10() ; break;
2449 case lir_abs : __ fabs() ; break;
2450 case lir_sqrt : __ fsqrt(); break;
2451 case lir_sin :
2452 // Should consider not saving rbx, if not necessary
2453 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2454 break;
2455 case lir_cos :
2456 // Should consider not saving rbx, if not necessary
2457 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2458 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2459 break;
2460 case lir_tan :
2461 // Should consider not saving rbx, if not necessary
2462 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2463 break;
2464 case lir_exp :
2465 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2466 break;
2467 case lir_pow :
2468 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2469 break;
2470 default : ShouldNotReachHere();
2471 }
2472 } else {
2473 Unimplemented();
2474 }
2475 }
2477 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2478 // assert(left->destroys_register(), "check");
2479 if (left->is_single_cpu()) {
2480 Register reg = left->as_register();
2481 if (right->is_constant()) {
2482 int val = right->as_constant_ptr()->as_jint();
2483 switch (code) {
2484 case lir_logic_and: __ andl (reg, val); break;
2485 case lir_logic_or: __ orl (reg, val); break;
2486 case lir_logic_xor: __ xorl (reg, val); break;
2487 default: ShouldNotReachHere();
2488 }
2489 } else if (right->is_stack()) {
2490 // added support for stack operands
2491 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2492 switch (code) {
2493 case lir_logic_and: __ andl (reg, raddr); break;
2494 case lir_logic_or: __ orl (reg, raddr); break;
2495 case lir_logic_xor: __ xorl (reg, raddr); break;
2496 default: ShouldNotReachHere();
2497 }
2498 } else {
2499 Register rright = right->as_register();
2500 switch (code) {
2501 case lir_logic_and: __ andptr (reg, rright); break;
2502 case lir_logic_or : __ orptr (reg, rright); break;
2503 case lir_logic_xor: __ xorptr (reg, rright); break;
2504 default: ShouldNotReachHere();
2505 }
2506 }
2507 move_regs(reg, dst->as_register());
2508 } else {
2509 Register l_lo = left->as_register_lo();
2510 Register l_hi = left->as_register_hi();
2511 if (right->is_constant()) {
2512 #ifdef _LP64
2513 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2514 switch (code) {
2515 case lir_logic_and:
2516 __ andq(l_lo, rscratch1);
2517 break;
2518 case lir_logic_or:
2519 __ orq(l_lo, rscratch1);
2520 break;
2521 case lir_logic_xor:
2522 __ xorq(l_lo, rscratch1);
2523 break;
2524 default: ShouldNotReachHere();
2525 }
2526 #else
2527 int r_lo = right->as_constant_ptr()->as_jint_lo();
2528 int r_hi = right->as_constant_ptr()->as_jint_hi();
2529 switch (code) {
2530 case lir_logic_and:
2531 __ andl(l_lo, r_lo);
2532 __ andl(l_hi, r_hi);
2533 break;
2534 case lir_logic_or:
2535 __ orl(l_lo, r_lo);
2536 __ orl(l_hi, r_hi);
2537 break;
2538 case lir_logic_xor:
2539 __ xorl(l_lo, r_lo);
2540 __ xorl(l_hi, r_hi);
2541 break;
2542 default: ShouldNotReachHere();
2543 }
2544 #endif // _LP64
2545 } else {
2546 #ifdef _LP64
2547 Register r_lo;
2548 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2549 r_lo = right->as_register();
2550 } else {
2551 r_lo = right->as_register_lo();
2552 }
2553 #else
2554 Register r_lo = right->as_register_lo();
2555 Register r_hi = right->as_register_hi();
2556 assert(l_lo != r_hi, "overwriting registers");
2557 #endif
2558 switch (code) {
2559 case lir_logic_and:
2560 __ andptr(l_lo, r_lo);
2561 NOT_LP64(__ andptr(l_hi, r_hi);)
2562 break;
2563 case lir_logic_or:
2564 __ orptr(l_lo, r_lo);
2565 NOT_LP64(__ orptr(l_hi, r_hi);)
2566 break;
2567 case lir_logic_xor:
2568 __ xorptr(l_lo, r_lo);
2569 NOT_LP64(__ xorptr(l_hi, r_hi);)
2570 break;
2571 default: ShouldNotReachHere();
2572 }
2573 }
2575 Register dst_lo = dst->as_register_lo();
2576 Register dst_hi = dst->as_register_hi();
2578 #ifdef _LP64
2579 move_regs(l_lo, dst_lo);
2580 #else
2581 if (dst_lo == l_hi) {
2582 assert(dst_hi != l_lo, "overwriting registers");
2583 move_regs(l_hi, dst_hi);
2584 move_regs(l_lo, dst_lo);
2585 } else {
2586 assert(dst_lo != l_hi, "overwriting registers");
2587 move_regs(l_lo, dst_lo);
2588 move_regs(l_hi, dst_hi);
2589 }
2590 #endif // _LP64
2591 }
2592 }
2595 // we assume that rax, and rdx can be overwritten
2596 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2598 assert(left->is_single_cpu(), "left must be register");
2599 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2600 assert(result->is_single_cpu(), "result must be register");
2602 // assert(left->destroys_register(), "check");
2603 // assert(right->destroys_register(), "check");
2605 Register lreg = left->as_register();
2606 Register dreg = result->as_register();
2608 if (right->is_constant()) {
2609 int divisor = right->as_constant_ptr()->as_jint();
2610 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2611 if (code == lir_idiv) {
2612 assert(lreg == rax, "must be rax,");
2613 assert(temp->as_register() == rdx, "tmp register must be rdx");
2614 __ cdql(); // sign extend into rdx:rax
2615 if (divisor == 2) {
2616 __ subl(lreg, rdx);
2617 } else {
2618 __ andl(rdx, divisor - 1);
2619 __ addl(lreg, rdx);
2620 }
2621 __ sarl(lreg, log2_intptr(divisor));
2622 move_regs(lreg, dreg);
2623 } else if (code == lir_irem) {
2624 Label done;
2625 __ mov(dreg, lreg);
2626 __ andl(dreg, 0x80000000 | (divisor - 1));
2627 __ jcc(Assembler::positive, done);
2628 __ decrement(dreg);
2629 __ orl(dreg, ~(divisor - 1));
2630 __ increment(dreg);
2631 __ bind(done);
2632 } else {
2633 ShouldNotReachHere();
2634 }
2635 } else {
2636 Register rreg = right->as_register();
2637 assert(lreg == rax, "left register must be rax,");
2638 assert(rreg != rdx, "right register must not be rdx");
2639 assert(temp->as_register() == rdx, "tmp register must be rdx");
2641 move_regs(lreg, rax);
2643 int idivl_offset = __ corrected_idivl(rreg);
2644 add_debug_info_for_div0(idivl_offset, info);
2645 if (code == lir_irem) {
2646 move_regs(rdx, dreg); // result is in rdx
2647 } else {
2648 move_regs(rax, dreg);
2649 }
2650 }
2651 }
2654 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2655 if (opr1->is_single_cpu()) {
2656 Register reg1 = opr1->as_register();
2657 if (opr2->is_single_cpu()) {
2658 // cpu register - cpu register
2659 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2660 __ cmpptr(reg1, opr2->as_register());
2661 } else {
2662 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2663 __ cmpl(reg1, opr2->as_register());
2664 }
2665 } else if (opr2->is_stack()) {
2666 // cpu register - stack
2667 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2668 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2669 } else {
2670 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2671 }
2672 } else if (opr2->is_constant()) {
2673 // cpu register - constant
2674 LIR_Const* c = opr2->as_constant_ptr();
2675 if (c->type() == T_INT) {
2676 __ cmpl(reg1, c->as_jint());
2677 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2678 // In 64bit oops are single register
2679 jobject o = c->as_jobject();
2680 if (o == NULL) {
2681 __ cmpptr(reg1, (int32_t)NULL_WORD);
2682 } else {
2683 #ifdef _LP64
2684 __ movoop(rscratch1, o);
2685 __ cmpptr(reg1, rscratch1);
2686 #else
2687 __ cmpoop(reg1, c->as_jobject());
2688 #endif // _LP64
2689 }
2690 } else {
2691 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2692 }
2693 // cpu register - address
2694 } else if (opr2->is_address()) {
2695 if (op->info() != NULL) {
2696 add_debug_info_for_null_check_here(op->info());
2697 }
2698 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2699 } else {
2700 ShouldNotReachHere();
2701 }
2703 } else if(opr1->is_double_cpu()) {
2704 Register xlo = opr1->as_register_lo();
2705 Register xhi = opr1->as_register_hi();
2706 if (opr2->is_double_cpu()) {
2707 #ifdef _LP64
2708 __ cmpptr(xlo, opr2->as_register_lo());
2709 #else
2710 // cpu register - cpu register
2711 Register ylo = opr2->as_register_lo();
2712 Register yhi = opr2->as_register_hi();
2713 __ subl(xlo, ylo);
2714 __ sbbl(xhi, yhi);
2715 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2716 __ orl(xhi, xlo);
2717 }
2718 #endif // _LP64
2719 } else if (opr2->is_constant()) {
2720 // cpu register - constant 0
2721 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2722 #ifdef _LP64
2723 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2724 #else
2725 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2726 __ orl(xhi, xlo);
2727 #endif // _LP64
2728 } else {
2729 ShouldNotReachHere();
2730 }
2732 } else if (opr1->is_single_xmm()) {
2733 XMMRegister reg1 = opr1->as_xmm_float_reg();
2734 if (opr2->is_single_xmm()) {
2735 // xmm register - xmm register
2736 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2737 } else if (opr2->is_stack()) {
2738 // xmm register - stack
2739 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2740 } else if (opr2->is_constant()) {
2741 // xmm register - constant
2742 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2743 } else if (opr2->is_address()) {
2744 // xmm register - address
2745 if (op->info() != NULL) {
2746 add_debug_info_for_null_check_here(op->info());
2747 }
2748 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2749 } else {
2750 ShouldNotReachHere();
2751 }
2753 } else if (opr1->is_double_xmm()) {
2754 XMMRegister reg1 = opr1->as_xmm_double_reg();
2755 if (opr2->is_double_xmm()) {
2756 // xmm register - xmm register
2757 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2758 } else if (opr2->is_stack()) {
2759 // xmm register - stack
2760 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2761 } else if (opr2->is_constant()) {
2762 // xmm register - constant
2763 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2764 } else if (opr2->is_address()) {
2765 // xmm register - address
2766 if (op->info() != NULL) {
2767 add_debug_info_for_null_check_here(op->info());
2768 }
2769 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2770 } else {
2771 ShouldNotReachHere();
2772 }
2774 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2775 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2776 assert(opr2->is_fpu_register(), "both must be registers");
2777 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2779 } else if (opr1->is_address() && opr2->is_constant()) {
2780 LIR_Const* c = opr2->as_constant_ptr();
2781 #ifdef _LP64
2782 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2783 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2784 __ movoop(rscratch1, c->as_jobject());
2785 }
2786 #endif // LP64
2787 if (op->info() != NULL) {
2788 add_debug_info_for_null_check_here(op->info());
2789 }
2790 // special case: address - constant
2791 LIR_Address* addr = opr1->as_address_ptr();
2792 if (c->type() == T_INT) {
2793 __ cmpl(as_Address(addr), c->as_jint());
2794 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2795 #ifdef _LP64
2796 // %%% Make this explode if addr isn't reachable until we figure out a
2797 // better strategy by giving noreg as the temp for as_Address
2798 __ cmpptr(rscratch1, as_Address(addr, noreg));
2799 #else
2800 __ cmpoop(as_Address(addr), c->as_jobject());
2801 #endif // _LP64
2802 } else {
2803 ShouldNotReachHere();
2804 }
2806 } else {
2807 ShouldNotReachHere();
2808 }
2809 }
2811 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2812 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2813 if (left->is_single_xmm()) {
2814 assert(right->is_single_xmm(), "must match");
2815 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2816 } else if (left->is_double_xmm()) {
2817 assert(right->is_double_xmm(), "must match");
2818 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2820 } else {
2821 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2822 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2824 assert(left->fpu() == 0, "left must be on TOS");
2825 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2826 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2827 }
2828 } else {
2829 assert(code == lir_cmp_l2i, "check");
2830 #ifdef _LP64
2831 Label done;
2832 Register dest = dst->as_register();
2833 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2834 __ movl(dest, -1);
2835 __ jccb(Assembler::less, done);
2836 __ set_byte_if_not_zero(dest);
2837 __ movzbl(dest, dest);
2838 __ bind(done);
2839 #else
2840 __ lcmp2int(left->as_register_hi(),
2841 left->as_register_lo(),
2842 right->as_register_hi(),
2843 right->as_register_lo());
2844 move_regs(left->as_register_hi(), dst->as_register());
2845 #endif // _LP64
2846 }
2847 }
2850 void LIR_Assembler::align_call(LIR_Code code) {
2851 if (os::is_MP()) {
2852 // make sure that the displacement word of the call ends up word aligned
2853 int offset = __ offset();
2854 switch (code) {
2855 case lir_static_call:
2856 case lir_optvirtual_call:
2857 case lir_dynamic_call:
2858 offset += NativeCall::displacement_offset;
2859 break;
2860 case lir_icvirtual_call:
2861 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2862 break;
2863 case lir_virtual_call: // currently, sparc-specific for niagara
2864 default: ShouldNotReachHere();
2865 }
2866 while (offset++ % BytesPerWord != 0) {
2867 __ nop();
2868 }
2869 }
2870 }
2873 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2874 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2875 "must be aligned");
2876 __ call(AddressLiteral(op->addr(), rtype));
2877 add_call_info(code_offset(), op->info());
2878 }
2881 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2882 __ ic_call(op->addr());
2883 add_call_info(code_offset(), op->info());
2884 assert(!os::is_MP() ||
2885 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2886 "must be aligned");
2887 }
2890 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2891 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2892 ShouldNotReachHere();
2893 }
2896 void LIR_Assembler::emit_static_call_stub() {
2897 address call_pc = __ pc();
2898 address stub = __ start_a_stub(call_stub_size);
2899 if (stub == NULL) {
2900 bailout("static call stub overflow");
2901 return;
2902 }
2904 int start = __ offset();
2905 if (os::is_MP()) {
2906 // make sure that the displacement word of the call ends up word aligned
2907 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2908 while (offset++ % BytesPerWord != 0) {
2909 __ nop();
2910 }
2911 }
2912 __ relocate(static_stub_Relocation::spec(call_pc));
2913 __ mov_metadata(rbx, (Metadata*)NULL);
2914 // must be set to -1 at code generation time
2915 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2916 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2917 __ jump(RuntimeAddress(__ pc()));
2919 assert(__ offset() - start <= call_stub_size, "stub too big");
2920 __ end_a_stub();
2921 }
2924 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2925 assert(exceptionOop->as_register() == rax, "must match");
2926 assert(exceptionPC->as_register() == rdx, "must match");
2928 // exception object is not added to oop map by LinearScan
2929 // (LinearScan assumes that no oops are in fixed registers)
2930 info->add_register_oop(exceptionOop);
2931 Runtime1::StubID unwind_id;
2933 // get current pc information
2934 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2935 int pc_for_athrow_offset = __ offset();
2936 InternalAddress pc_for_athrow(__ pc());
2937 __ lea(exceptionPC->as_register(), pc_for_athrow);
2938 add_call_info(pc_for_athrow_offset, info); // for exception handler
2940 __ verify_not_null_oop(rax);
2941 // search an exception handler (rax: exception oop, rdx: throwing pc)
2942 if (compilation()->has_fpu_code()) {
2943 unwind_id = Runtime1::handle_exception_id;
2944 } else {
2945 unwind_id = Runtime1::handle_exception_nofpu_id;
2946 }
2947 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2949 // enough room for two byte trap
2950 __ nop();
2951 }
2954 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2955 assert(exceptionOop->as_register() == rax, "must match");
2957 __ jmp(_unwind_handler_entry);
2958 }
2961 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2963 // optimized version for linear scan:
2964 // * count must be already in ECX (guaranteed by LinearScan)
2965 // * left and dest must be equal
2966 // * tmp must be unused
2967 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2968 assert(left == dest, "left and dest must be equal");
2969 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2971 if (left->is_single_cpu()) {
2972 Register value = left->as_register();
2973 assert(value != SHIFT_count, "left cannot be ECX");
2975 switch (code) {
2976 case lir_shl: __ shll(value); break;
2977 case lir_shr: __ sarl(value); break;
2978 case lir_ushr: __ shrl(value); break;
2979 default: ShouldNotReachHere();
2980 }
2981 } else if (left->is_double_cpu()) {
2982 Register lo = left->as_register_lo();
2983 Register hi = left->as_register_hi();
2984 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2985 #ifdef _LP64
2986 switch (code) {
2987 case lir_shl: __ shlptr(lo); break;
2988 case lir_shr: __ sarptr(lo); break;
2989 case lir_ushr: __ shrptr(lo); break;
2990 default: ShouldNotReachHere();
2991 }
2992 #else
2994 switch (code) {
2995 case lir_shl: __ lshl(hi, lo); break;
2996 case lir_shr: __ lshr(hi, lo, true); break;
2997 case lir_ushr: __ lshr(hi, lo, false); break;
2998 default: ShouldNotReachHere();
2999 }
3000 #endif // LP64
3001 } else {
3002 ShouldNotReachHere();
3003 }
3004 }
3007 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3008 if (dest->is_single_cpu()) {
3009 // first move left into dest so that left is not destroyed by the shift
3010 Register value = dest->as_register();
3011 count = count & 0x1F; // Java spec
3013 move_regs(left->as_register(), value);
3014 switch (code) {
3015 case lir_shl: __ shll(value, count); break;
3016 case lir_shr: __ sarl(value, count); break;
3017 case lir_ushr: __ shrl(value, count); break;
3018 default: ShouldNotReachHere();
3019 }
3020 } else if (dest->is_double_cpu()) {
3021 #ifndef _LP64
3022 Unimplemented();
3023 #else
3024 // first move left into dest so that left is not destroyed by the shift
3025 Register value = dest->as_register_lo();
3026 count = count & 0x1F; // Java spec
3028 move_regs(left->as_register_lo(), value);
3029 switch (code) {
3030 case lir_shl: __ shlptr(value, count); break;
3031 case lir_shr: __ sarptr(value, count); break;
3032 case lir_ushr: __ shrptr(value, count); break;
3033 default: ShouldNotReachHere();
3034 }
3035 #endif // _LP64
3036 } else {
3037 ShouldNotReachHere();
3038 }
3039 }
3042 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3043 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3044 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3045 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3046 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3047 }
3050 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3051 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3052 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3053 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3054 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3055 }
3058 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3059 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3060 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3061 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3062 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3063 }
3066 // This code replaces a call to arraycopy; no exception may
3067 // be thrown in this code, they must be thrown in the System.arraycopy
3068 // activation frame; we could save some checks if this would not be the case
3069 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3070 ciArrayKlass* default_type = op->expected_type();
3071 Register src = op->src()->as_register();
3072 Register dst = op->dst()->as_register();
3073 Register src_pos = op->src_pos()->as_register();
3074 Register dst_pos = op->dst_pos()->as_register();
3075 Register length = op->length()->as_register();
3076 Register tmp = op->tmp()->as_register();
3078 CodeStub* stub = op->stub();
3079 int flags = op->flags();
3080 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3081 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3083 // if we don't know anything, just go through the generic arraycopy
3084 if (default_type == NULL) {
3085 Label done;
3086 // save outgoing arguments on stack in case call to System.arraycopy is needed
3087 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3088 // for interpreter calling conventions. Now we have to do it in new style conventions.
3089 // For the moment until C1 gets the new register allocator I just force all the
3090 // args to the right place (except the register args) and then on the back side
3091 // reload the register args properly if we go slow path. Yuck
3093 // These are proper for the calling convention
3094 store_parameter(length, 2);
3095 store_parameter(dst_pos, 1);
3096 store_parameter(dst, 0);
3098 // these are just temporary placements until we need to reload
3099 store_parameter(src_pos, 3);
3100 store_parameter(src, 4);
3101 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3103 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3105 address copyfunc_addr = StubRoutines::generic_arraycopy();
3107 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3108 #ifdef _LP64
3109 // The arguments are in java calling convention so we can trivially shift them to C
3110 // convention
3111 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3112 __ mov(c_rarg0, j_rarg0);
3113 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3114 __ mov(c_rarg1, j_rarg1);
3115 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3116 __ mov(c_rarg2, j_rarg2);
3117 assert_different_registers(c_rarg3, j_rarg4);
3118 __ mov(c_rarg3, j_rarg3);
3119 #ifdef _WIN64
3120 // Allocate abi space for args but be sure to keep stack aligned
3121 __ subptr(rsp, 6*wordSize);
3122 store_parameter(j_rarg4, 4);
3123 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3124 __ call(RuntimeAddress(C_entry));
3125 } else {
3126 #ifndef PRODUCT
3127 if (PrintC1Statistics) {
3128 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3129 }
3130 #endif
3131 __ call(RuntimeAddress(copyfunc_addr));
3132 }
3133 __ addptr(rsp, 6*wordSize);
3134 #else
3135 __ mov(c_rarg4, j_rarg4);
3136 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3137 __ call(RuntimeAddress(C_entry));
3138 } else {
3139 #ifndef PRODUCT
3140 if (PrintC1Statistics) {
3141 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3142 }
3143 #endif
3144 __ call(RuntimeAddress(copyfunc_addr));
3145 }
3146 #endif // _WIN64
3147 #else
3148 __ push(length);
3149 __ push(dst_pos);
3150 __ push(dst);
3151 __ push(src_pos);
3152 __ push(src);
3154 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3155 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3156 } else {
3157 #ifndef PRODUCT
3158 if (PrintC1Statistics) {
3159 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3160 }
3161 #endif
3162 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3163 }
3165 #endif // _LP64
3167 __ cmpl(rax, 0);
3168 __ jcc(Assembler::equal, *stub->continuation());
3170 if (copyfunc_addr != NULL) {
3171 __ mov(tmp, rax);
3172 __ xorl(tmp, -1);
3173 }
3175 // Reload values from the stack so they are where the stub
3176 // expects them.
3177 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3178 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3179 __ movptr (length, Address(rsp, 2*BytesPerWord));
3180 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3181 __ movptr (src, Address(rsp, 4*BytesPerWord));
3183 if (copyfunc_addr != NULL) {
3184 __ subl(length, tmp);
3185 __ addl(src_pos, tmp);
3186 __ addl(dst_pos, tmp);
3187 }
3188 __ jmp(*stub->entry());
3190 __ bind(*stub->continuation());
3191 return;
3192 }
3194 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3196 int elem_size = type2aelembytes(basic_type);
3197 int shift_amount;
3198 Address::ScaleFactor scale;
3200 switch (elem_size) {
3201 case 1 :
3202 shift_amount = 0;
3203 scale = Address::times_1;
3204 break;
3205 case 2 :
3206 shift_amount = 1;
3207 scale = Address::times_2;
3208 break;
3209 case 4 :
3210 shift_amount = 2;
3211 scale = Address::times_4;
3212 break;
3213 case 8 :
3214 shift_amount = 3;
3215 scale = Address::times_8;
3216 break;
3217 default:
3218 ShouldNotReachHere();
3219 }
3221 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3222 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3223 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3224 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3226 // length and pos's are all sign extended at this point on 64bit
3228 // test for NULL
3229 if (flags & LIR_OpArrayCopy::src_null_check) {
3230 __ testptr(src, src);
3231 __ jcc(Assembler::zero, *stub->entry());
3232 }
3233 if (flags & LIR_OpArrayCopy::dst_null_check) {
3234 __ testptr(dst, dst);
3235 __ jcc(Assembler::zero, *stub->entry());
3236 }
3238 // check if negative
3239 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3240 __ testl(src_pos, src_pos);
3241 __ jcc(Assembler::less, *stub->entry());
3242 }
3243 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3244 __ testl(dst_pos, dst_pos);
3245 __ jcc(Assembler::less, *stub->entry());
3246 }
3248 if (flags & LIR_OpArrayCopy::src_range_check) {
3249 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3250 __ cmpl(tmp, src_length_addr);
3251 __ jcc(Assembler::above, *stub->entry());
3252 }
3253 if (flags & LIR_OpArrayCopy::dst_range_check) {
3254 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3255 __ cmpl(tmp, dst_length_addr);
3256 __ jcc(Assembler::above, *stub->entry());
3257 }
3259 if (flags & LIR_OpArrayCopy::length_positive_check) {
3260 __ testl(length, length);
3261 __ jcc(Assembler::less, *stub->entry());
3262 __ jcc(Assembler::zero, *stub->continuation());
3263 }
3265 #ifdef _LP64
3266 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3267 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3268 #endif
3270 if (flags & LIR_OpArrayCopy::type_check) {
3271 // We don't know the array types are compatible
3272 if (basic_type != T_OBJECT) {
3273 // Simple test for basic type arrays
3274 if (UseCompressedKlassPointers) {
3275 __ movl(tmp, src_klass_addr);
3276 __ cmpl(tmp, dst_klass_addr);
3277 } else {
3278 __ movptr(tmp, src_klass_addr);
3279 __ cmpptr(tmp, dst_klass_addr);
3280 }
3281 __ jcc(Assembler::notEqual, *stub->entry());
3282 } else {
3283 // For object arrays, if src is a sub class of dst then we can
3284 // safely do the copy.
3285 Label cont, slow;
3287 __ push(src);
3288 __ push(dst);
3290 __ load_klass(src, src);
3291 __ load_klass(dst, dst);
3293 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3295 __ push(src);
3296 __ push(dst);
3297 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3298 __ pop(dst);
3299 __ pop(src);
3301 __ cmpl(src, 0);
3302 __ jcc(Assembler::notEqual, cont);
3304 __ bind(slow);
3305 __ pop(dst);
3306 __ pop(src);
3308 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3309 if (copyfunc_addr != NULL) { // use stub if available
3310 // src is not a sub class of dst so we have to do a
3311 // per-element check.
3313 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3314 if ((flags & mask) != mask) {
3315 // Check that at least both of them object arrays.
3316 assert(flags & mask, "one of the two should be known to be an object array");
3318 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3319 __ load_klass(tmp, src);
3320 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3321 __ load_klass(tmp, dst);
3322 }
3323 int lh_offset = in_bytes(Klass::layout_helper_offset());
3324 Address klass_lh_addr(tmp, lh_offset);
3325 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3326 __ cmpl(klass_lh_addr, objArray_lh);
3327 __ jcc(Assembler::notEqual, *stub->entry());
3328 }
3330 // Spill because stubs can use any register they like and it's
3331 // easier to restore just those that we care about.
3332 store_parameter(dst, 0);
3333 store_parameter(dst_pos, 1);
3334 store_parameter(length, 2);
3335 store_parameter(src_pos, 3);
3336 store_parameter(src, 4);
3338 #ifndef _LP64
3339 __ movptr(tmp, dst_klass_addr);
3340 __ movptr(tmp, Address(tmp, objArrayKlass::element_klass_offset()));
3341 __ push(tmp);
3342 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3343 __ push(tmp);
3344 __ push(length);
3345 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3346 __ push(tmp);
3347 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3348 __ push(tmp);
3350 __ call_VM_leaf(copyfunc_addr, 5);
3351 #else
3352 __ movl2ptr(length, length); //higher 32bits must be null
3354 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3355 assert_different_registers(c_rarg0, dst, dst_pos, length);
3356 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3357 assert_different_registers(c_rarg1, dst, length);
3359 __ mov(c_rarg2, length);
3360 assert_different_registers(c_rarg2, dst);
3362 #ifdef _WIN64
3363 // Allocate abi space for args but be sure to keep stack aligned
3364 __ subptr(rsp, 6*wordSize);
3365 __ load_klass(c_rarg3, dst);
3366 __ movptr(c_rarg3, Address(c_rarg3, objArrayKlass::element_klass_offset()));
3367 store_parameter(c_rarg3, 4);
3368 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3369 __ call(RuntimeAddress(copyfunc_addr));
3370 __ addptr(rsp, 6*wordSize);
3371 #else
3372 __ load_klass(c_rarg4, dst);
3373 __ movptr(c_rarg4, Address(c_rarg4, objArrayKlass::element_klass_offset()));
3374 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3375 __ call(RuntimeAddress(copyfunc_addr));
3376 #endif
3378 #endif
3380 #ifndef PRODUCT
3381 if (PrintC1Statistics) {
3382 Label failed;
3383 __ testl(rax, rax);
3384 __ jcc(Assembler::notZero, failed);
3385 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3386 __ bind(failed);
3387 }
3388 #endif
3390 __ testl(rax, rax);
3391 __ jcc(Assembler::zero, *stub->continuation());
3393 #ifndef PRODUCT
3394 if (PrintC1Statistics) {
3395 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3396 }
3397 #endif
3399 __ mov(tmp, rax);
3401 __ xorl(tmp, -1);
3403 // Restore previously spilled arguments
3404 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3405 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3406 __ movptr (length, Address(rsp, 2*BytesPerWord));
3407 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3408 __ movptr (src, Address(rsp, 4*BytesPerWord));
3411 __ subl(length, tmp);
3412 __ addl(src_pos, tmp);
3413 __ addl(dst_pos, tmp);
3414 }
3416 __ jmp(*stub->entry());
3418 __ bind(cont);
3419 __ pop(dst);
3420 __ pop(src);
3421 }
3422 }
3424 #ifdef ASSERT
3425 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3426 // Sanity check the known type with the incoming class. For the
3427 // primitive case the types must match exactly with src.klass and
3428 // dst.klass each exactly matching the default type. For the
3429 // object array case, if no type check is needed then either the
3430 // dst type is exactly the expected type and the src type is a
3431 // subtype which we can't check or src is the same array as dst
3432 // but not necessarily exactly of type default_type.
3433 Label known_ok, halt;
3434 __ mov_metadata(tmp, default_type->constant_encoding());
3435 #ifdef _LP64
3436 if (UseCompressedKlassPointers) {
3437 __ encode_heap_oop(tmp);
3438 }
3439 #endif
3441 if (basic_type != T_OBJECT) {
3443 if (UseCompressedKlassPointers) __ cmpl(tmp, dst_klass_addr);
3444 else __ cmpptr(tmp, dst_klass_addr);
3445 __ jcc(Assembler::notEqual, halt);
3446 if (UseCompressedKlassPointers) __ cmpl(tmp, src_klass_addr);
3447 else __ cmpptr(tmp, src_klass_addr);
3448 __ jcc(Assembler::equal, known_ok);
3449 } else {
3450 if (UseCompressedKlassPointers) __ cmpl(tmp, dst_klass_addr);
3451 else __ cmpptr(tmp, dst_klass_addr);
3452 __ jcc(Assembler::equal, known_ok);
3453 __ cmpptr(src, dst);
3454 __ jcc(Assembler::equal, known_ok);
3455 }
3456 __ bind(halt);
3457 __ stop("incorrect type information in arraycopy");
3458 __ bind(known_ok);
3459 }
3460 #endif
3462 #ifndef PRODUCT
3463 if (PrintC1Statistics) {
3464 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3465 }
3466 #endif
3468 #ifdef _LP64
3469 assert_different_registers(c_rarg0, dst, dst_pos, length);
3470 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3471 assert_different_registers(c_rarg1, length);
3472 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3473 __ mov(c_rarg2, length);
3475 #else
3476 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3477 store_parameter(tmp, 0);
3478 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3479 store_parameter(tmp, 1);
3480 store_parameter(length, 2);
3481 #endif // _LP64
3483 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3484 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3485 const char *name;
3486 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3487 __ call_VM_leaf(entry, 0);
3489 __ bind(*stub->continuation());
3490 }
3493 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3494 Register obj = op->obj_opr()->as_register(); // may not be an oop
3495 Register hdr = op->hdr_opr()->as_register();
3496 Register lock = op->lock_opr()->as_register();
3497 if (!UseFastLocking) {
3498 __ jmp(*op->stub()->entry());
3499 } else if (op->code() == lir_lock) {
3500 Register scratch = noreg;
3501 if (UseBiasedLocking) {
3502 scratch = op->scratch_opr()->as_register();
3503 }
3504 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3505 // add debug info for NullPointerException only if one is possible
3506 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3507 if (op->info() != NULL) {
3508 add_debug_info_for_null_check(null_check_offset, op->info());
3509 }
3510 // done
3511 } else if (op->code() == lir_unlock) {
3512 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3513 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3514 } else {
3515 Unimplemented();
3516 }
3517 __ bind(*op->stub()->continuation());
3518 }
3521 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3522 ciMethod* method = op->profiled_method();
3523 int bci = op->profiled_bci();
3524 ciMethod* callee = op->profiled_callee();
3526 // Update counter for all call types
3527 ciMethodData* md = method->method_data_or_null();
3528 assert(md != NULL, "Sanity");
3529 ciProfileData* data = md->bci_to_data(bci);
3530 assert(data->is_CounterData(), "need CounterData for calls");
3531 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3532 Register mdo = op->mdo()->as_register();
3533 __ mov_metadata(mdo, md->constant_encoding());
3534 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3535 Bytecodes::Code bc = method->java_code_at_bci(bci);
3536 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3537 // Perform additional virtual call profiling for invokevirtual and
3538 // invokeinterface bytecodes
3539 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3540 !callee_is_static && // required for optimized MH invokes
3541 C1ProfileVirtualCalls) {
3542 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3543 Register recv = op->recv()->as_register();
3544 assert_different_registers(mdo, recv);
3545 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3546 ciKlass* known_klass = op->known_holder();
3547 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3548 // We know the type that will be seen at this call site; we can
3549 // statically update the MethodData* rather than needing to do
3550 // dynamic tests on the receiver type
3552 // NOTE: we should probably put a lock around this search to
3553 // avoid collisions by concurrent compilations
3554 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3555 uint i;
3556 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3557 ciKlass* receiver = vc_data->receiver(i);
3558 if (known_klass->equals(receiver)) {
3559 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3560 __ addptr(data_addr, DataLayout::counter_increment);
3561 return;
3562 }
3563 }
3565 // Receiver type not found in profile data; select an empty slot
3567 // Note that this is less efficient than it should be because it
3568 // always does a write to the receiver part of the
3569 // VirtualCallData rather than just the first time
3570 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3571 ciKlass* receiver = vc_data->receiver(i);
3572 if (receiver == NULL) {
3573 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3574 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3575 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3576 __ addptr(data_addr, DataLayout::counter_increment);
3577 return;
3578 }
3579 }
3580 } else {
3581 __ load_klass(recv, recv);
3582 Label update_done;
3583 type_profile_helper(mdo, md, data, recv, &update_done);
3584 // Receiver did not match any saved receiver and there is no empty row for it.
3585 // Increment total counter to indicate polymorphic case.
3586 __ addptr(counter_addr, DataLayout::counter_increment);
3588 __ bind(update_done);
3589 }
3590 } else {
3591 // Static call
3592 __ addptr(counter_addr, DataLayout::counter_increment);
3593 }
3594 }
3596 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3597 Unimplemented();
3598 }
3601 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3602 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3603 }
3606 void LIR_Assembler::align_backward_branch_target() {
3607 __ align(BytesPerWord);
3608 }
3611 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3612 if (left->is_single_cpu()) {
3613 __ negl(left->as_register());
3614 move_regs(left->as_register(), dest->as_register());
3616 } else if (left->is_double_cpu()) {
3617 Register lo = left->as_register_lo();
3618 #ifdef _LP64
3619 Register dst = dest->as_register_lo();
3620 __ movptr(dst, lo);
3621 __ negptr(dst);
3622 #else
3623 Register hi = left->as_register_hi();
3624 __ lneg(hi, lo);
3625 if (dest->as_register_lo() == hi) {
3626 assert(dest->as_register_hi() != lo, "destroying register");
3627 move_regs(hi, dest->as_register_hi());
3628 move_regs(lo, dest->as_register_lo());
3629 } else {
3630 move_regs(lo, dest->as_register_lo());
3631 move_regs(hi, dest->as_register_hi());
3632 }
3633 #endif // _LP64
3635 } else if (dest->is_single_xmm()) {
3636 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3637 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3638 }
3639 __ xorps(dest->as_xmm_float_reg(),
3640 ExternalAddress((address)float_signflip_pool));
3642 } else if (dest->is_double_xmm()) {
3643 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3644 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3645 }
3646 __ xorpd(dest->as_xmm_double_reg(),
3647 ExternalAddress((address)double_signflip_pool));
3649 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3650 assert(left->fpu() == 0, "arg must be on TOS");
3651 assert(dest->fpu() == 0, "dest must be TOS");
3652 __ fchs();
3654 } else {
3655 ShouldNotReachHere();
3656 }
3657 }
3660 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3661 assert(addr->is_address() && dest->is_register(), "check");
3662 Register reg;
3663 reg = dest->as_pointer_register();
3664 __ lea(reg, as_Address(addr->as_address_ptr()));
3665 }
3669 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3670 assert(!tmp->is_valid(), "don't need temporary");
3671 __ call(RuntimeAddress(dest));
3672 if (info != NULL) {
3673 add_call_info_here(info);
3674 }
3675 }
3678 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3679 assert(type == T_LONG, "only for volatile long fields");
3681 if (info != NULL) {
3682 add_debug_info_for_null_check_here(info);
3683 }
3685 if (src->is_double_xmm()) {
3686 if (dest->is_double_cpu()) {
3687 #ifdef _LP64
3688 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3689 #else
3690 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3691 __ psrlq(src->as_xmm_double_reg(), 32);
3692 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3693 #endif // _LP64
3694 } else if (dest->is_double_stack()) {
3695 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3696 } else if (dest->is_address()) {
3697 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3698 } else {
3699 ShouldNotReachHere();
3700 }
3702 } else if (dest->is_double_xmm()) {
3703 if (src->is_double_stack()) {
3704 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3705 } else if (src->is_address()) {
3706 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3707 } else {
3708 ShouldNotReachHere();
3709 }
3711 } else if (src->is_double_fpu()) {
3712 assert(src->fpu_regnrLo() == 0, "must be TOS");
3713 if (dest->is_double_stack()) {
3714 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3715 } else if (dest->is_address()) {
3716 __ fistp_d(as_Address(dest->as_address_ptr()));
3717 } else {
3718 ShouldNotReachHere();
3719 }
3721 } else if (dest->is_double_fpu()) {
3722 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3723 if (src->is_double_stack()) {
3724 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3725 } else if (src->is_address()) {
3726 __ fild_d(as_Address(src->as_address_ptr()));
3727 } else {
3728 ShouldNotReachHere();
3729 }
3730 } else {
3731 ShouldNotReachHere();
3732 }
3733 }
3736 void LIR_Assembler::membar() {
3737 // QQQ sparc TSO uses this,
3738 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3739 }
3741 void LIR_Assembler::membar_acquire() {
3742 // No x86 machines currently require load fences
3743 // __ load_fence();
3744 }
3746 void LIR_Assembler::membar_release() {
3747 // No x86 machines currently require store fences
3748 // __ store_fence();
3749 }
3751 void LIR_Assembler::membar_loadload() {
3752 // no-op
3753 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3754 }
3756 void LIR_Assembler::membar_storestore() {
3757 // no-op
3758 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3759 }
3761 void LIR_Assembler::membar_loadstore() {
3762 // no-op
3763 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3764 }
3766 void LIR_Assembler::membar_storeload() {
3767 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3768 }
3770 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3771 assert(result_reg->is_register(), "check");
3772 #ifdef _LP64
3773 // __ get_thread(result_reg->as_register_lo());
3774 __ mov(result_reg->as_register(), r15_thread);
3775 #else
3776 __ get_thread(result_reg->as_register());
3777 #endif // _LP64
3778 }
3781 void LIR_Assembler::peephole(LIR_List*) {
3782 // do nothing for now
3783 }
3786 #undef __
