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src/cpu/x86/vm/vm_version_x86.hpp@d8ce2825b193
src/cpu/x86/vm/vm_version_x86.hpp
Sat, 29 Sep 2012 06:40:00 -0400
- author
- coleenp
- date
- Sat, 29 Sep 2012 06:40:00 -0400
- changeset 4142
- d8ce2825b193
- parent 3560
- 4a24c4f648bd
- child 4153
- b9a9ed0f8eeb
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- -rw-r--r--
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
Summary: Capitalize these metadata types (and objArrayKlass)
Reviewed-by: stefank, twisti, kvn
1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VM_VERSION_X86_HPP
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
31 class VM_Version : public Abstract_VM_Version {
32 public:
33 // cpuid result register layouts. These are all unions of a uint32_t
34 // (in case anyone wants access to the register as a whole) and a bitfield.
36 union StdCpuid1Eax {
37 uint32_t value;
38 struct {
39 uint32_t stepping : 4,
40 model : 4,
41 family : 4,
42 proc_type : 2,
43 : 2,
44 ext_model : 4,
45 ext_family : 8,
46 : 4;
47 } bits;
48 };
50 union StdCpuid1Ebx { // example, unused
51 uint32_t value;
52 struct {
53 uint32_t brand_id : 8,
54 clflush_size : 8,
55 threads_per_cpu : 8,
56 apic_id : 8;
57 } bits;
58 };
60 union StdCpuid1Ecx {
61 uint32_t value;
62 struct {
63 uint32_t sse3 : 1,
64 : 2,
65 monitor : 1,
66 : 1,
67 vmx : 1,
68 : 1,
69 est : 1,
70 : 1,
71 ssse3 : 1,
72 cid : 1,
73 : 2,
74 cmpxchg16: 1,
75 : 4,
76 dca : 1,
77 sse4_1 : 1,
78 sse4_2 : 1,
79 : 2,
80 popcnt : 1,
81 : 3,
82 osxsave : 1,
83 avx : 1,
84 : 3;
85 } bits;
86 };
88 union StdCpuid1Edx {
89 uint32_t value;
90 struct {
91 uint32_t : 4,
92 tsc : 1,
93 : 3,
94 cmpxchg8 : 1,
95 : 6,
96 cmov : 1,
97 : 3,
98 clflush : 1,
99 : 3,
100 mmx : 1,
101 fxsr : 1,
102 sse : 1,
103 sse2 : 1,
104 : 1,
105 ht : 1,
106 : 3;
107 } bits;
108 };
110 union DcpCpuid4Eax {
111 uint32_t value;
112 struct {
113 uint32_t cache_type : 5,
114 : 21,
115 cores_per_cpu : 6;
116 } bits;
117 };
119 union DcpCpuid4Ebx {
120 uint32_t value;
121 struct {
122 uint32_t L1_line_size : 12,
123 partitions : 10,
124 associativity : 10;
125 } bits;
126 };
128 union TplCpuidBEbx {
129 uint32_t value;
130 struct {
131 uint32_t logical_cpus : 16,
132 : 16;
133 } bits;
134 };
136 union ExtCpuid1Ecx {
137 uint32_t value;
138 struct {
139 uint32_t LahfSahf : 1,
140 CmpLegacy : 1,
141 : 4,
142 lzcnt : 1,
143 sse4a : 1,
144 misalignsse : 1,
145 prefetchw : 1,
146 : 22;
147 } bits;
148 };
150 union ExtCpuid1Edx {
151 uint32_t value;
152 struct {
153 uint32_t : 22,
154 mmx_amd : 1,
155 mmx : 1,
156 fxsr : 1,
157 : 4,
158 long_mode : 1,
159 tdnow2 : 1,
160 tdnow : 1;
161 } bits;
162 };
164 union ExtCpuid5Ex {
165 uint32_t value;
166 struct {
167 uint32_t L1_line_size : 8,
168 L1_tag_lines : 8,
169 L1_assoc : 8,
170 L1_size : 8;
171 } bits;
172 };
174 union ExtCpuid7Edx {
175 uint32_t value;
176 struct {
177 uint32_t : 8,
178 tsc_invariance : 1,
179 : 23;
180 } bits;
181 };
183 union ExtCpuid8Ecx {
184 uint32_t value;
185 struct {
186 uint32_t cores_per_cpu : 8,
187 : 24;
188 } bits;
189 };
191 union SefCpuid7Eax {
192 uint32_t value;
193 };
195 union SefCpuid7Ebx {
196 uint32_t value;
197 struct {
198 uint32_t fsgsbase : 1,
199 : 2,
200 bmi1 : 1,
201 : 1,
202 avx2 : 1,
203 : 2,
204 bmi2 : 1,
205 : 23;
206 } bits;
207 };
209 union XemXcr0Eax {
210 uint32_t value;
211 struct {
212 uint32_t x87 : 1,
213 sse : 1,
214 ymm : 1,
215 : 29;
216 } bits;
217 };
219 protected:
220 static int _cpu;
221 static int _model;
222 static int _stepping;
223 static int _cpuFeatures; // features returned by the "cpuid" instruction
224 // 0 if this instruction is not available
225 static const char* _features_str;
227 enum {
228 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX)
229 CPU_CMOV = (1 << 1),
230 CPU_FXSR = (1 << 2),
231 CPU_HT = (1 << 3),
232 CPU_MMX = (1 << 4),
233 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
234 // may not necessarily support other 3dnow instructions
235 CPU_SSE = (1 << 6),
236 CPU_SSE2 = (1 << 7),
237 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
238 CPU_SSSE3 = (1 << 9),
239 CPU_SSE4A = (1 << 10),
240 CPU_SSE4_1 = (1 << 11),
241 CPU_SSE4_2 = (1 << 12),
242 CPU_POPCNT = (1 << 13),
243 CPU_LZCNT = (1 << 14),
244 CPU_TSC = (1 << 15),
245 CPU_TSCINV = (1 << 16),
246 CPU_AVX = (1 << 17),
247 CPU_AVX2 = (1 << 18)
248 } cpuFeatureFlags;
250 enum {
251 // AMD
252 CPU_FAMILY_AMD_11H = 0x11,
253 // Intel
254 CPU_FAMILY_INTEL_CORE = 6,
255 CPU_MODEL_NEHALEM = 0x1e,
256 CPU_MODEL_NEHALEM_EP = 0x1a,
257 CPU_MODEL_NEHALEM_EX = 0x2e,
258 CPU_MODEL_WESTMERE = 0x25,
259 CPU_MODEL_WESTMERE_EP = 0x2c,
260 CPU_MODEL_WESTMERE_EX = 0x2f,
261 CPU_MODEL_SANDYBRIDGE = 0x2a,
262 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
263 CPU_MODEL_IVYBRIDGE_EP = 0x3a
264 } cpuExtendedFamily;
266 // cpuid information block. All info derived from executing cpuid with
267 // various function numbers is stored here. Intel and AMD info is
268 // merged in this block: accessor methods disentangle it.
269 //
270 // The info block is laid out in subblocks of 4 dwords corresponding to
271 // eax, ebx, ecx and edx, whether or not they contain anything useful.
272 struct CpuidInfo {
273 // cpuid function 0
274 uint32_t std_max_function;
275 uint32_t std_vendor_name_0;
276 uint32_t std_vendor_name_1;
277 uint32_t std_vendor_name_2;
279 // cpuid function 1
280 StdCpuid1Eax std_cpuid1_eax;
281 StdCpuid1Ebx std_cpuid1_ebx;
282 StdCpuid1Ecx std_cpuid1_ecx;
283 StdCpuid1Edx std_cpuid1_edx;
285 // cpuid function 4 (deterministic cache parameters)
286 DcpCpuid4Eax dcp_cpuid4_eax;
287 DcpCpuid4Ebx dcp_cpuid4_ebx;
288 uint32_t dcp_cpuid4_ecx; // unused currently
289 uint32_t dcp_cpuid4_edx; // unused currently
291 // cpuid function 7 (structured extended features)
292 SefCpuid7Eax sef_cpuid7_eax;
293 SefCpuid7Ebx sef_cpuid7_ebx;
294 uint32_t sef_cpuid7_ecx; // unused currently
295 uint32_t sef_cpuid7_edx; // unused currently
297 // cpuid function 0xB (processor topology)
298 // ecx = 0
299 uint32_t tpl_cpuidB0_eax;
300 TplCpuidBEbx tpl_cpuidB0_ebx;
301 uint32_t tpl_cpuidB0_ecx; // unused currently
302 uint32_t tpl_cpuidB0_edx; // unused currently
304 // ecx = 1
305 uint32_t tpl_cpuidB1_eax;
306 TplCpuidBEbx tpl_cpuidB1_ebx;
307 uint32_t tpl_cpuidB1_ecx; // unused currently
308 uint32_t tpl_cpuidB1_edx; // unused currently
310 // ecx = 2
311 uint32_t tpl_cpuidB2_eax;
312 TplCpuidBEbx tpl_cpuidB2_ebx;
313 uint32_t tpl_cpuidB2_ecx; // unused currently
314 uint32_t tpl_cpuidB2_edx; // unused currently
316 // cpuid function 0x80000000 // example, unused
317 uint32_t ext_max_function;
318 uint32_t ext_vendor_name_0;
319 uint32_t ext_vendor_name_1;
320 uint32_t ext_vendor_name_2;
322 // cpuid function 0x80000001
323 uint32_t ext_cpuid1_eax; // reserved
324 uint32_t ext_cpuid1_ebx; // reserved
325 ExtCpuid1Ecx ext_cpuid1_ecx;
326 ExtCpuid1Edx ext_cpuid1_edx;
328 // cpuid functions 0x80000002 thru 0x80000004: example, unused
329 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
330 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
331 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
333 // cpuid function 0x80000005 // AMD L1, Intel reserved
334 uint32_t ext_cpuid5_eax; // unused currently
335 uint32_t ext_cpuid5_ebx; // reserved
336 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
337 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
339 // cpuid function 0x80000007
340 uint32_t ext_cpuid7_eax; // reserved
341 uint32_t ext_cpuid7_ebx; // reserved
342 uint32_t ext_cpuid7_ecx; // reserved
343 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
345 // cpuid function 0x80000008
346 uint32_t ext_cpuid8_eax; // unused currently
347 uint32_t ext_cpuid8_ebx; // reserved
348 ExtCpuid8Ecx ext_cpuid8_ecx;
349 uint32_t ext_cpuid8_edx; // reserved
351 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
352 XemXcr0Eax xem_xcr0_eax;
353 uint32_t xem_xcr0_edx; // reserved
354 };
356 // The actual cpuid info block
357 static CpuidInfo _cpuid_info;
359 // Extractors and predicates
360 static uint32_t extended_cpu_family() {
361 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
362 result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
363 return result;
364 }
366 static uint32_t extended_cpu_model() {
367 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
368 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
369 return result;
370 }
372 static uint32_t cpu_stepping() {
373 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
374 return result;
375 }
377 static uint logical_processor_count() {
378 uint result = threads_per_core();
379 return result;
380 }
382 static uint32_t feature_flags() {
383 uint32_t result = 0;
384 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
385 result |= CPU_CX8;
386 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
387 result |= CPU_CMOV;
388 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
389 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
390 result |= CPU_FXSR;
391 // HT flag is set for multi-core processors also.
392 if (threads_per_core() > 1)
393 result |= CPU_HT;
394 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
395 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
396 result |= CPU_MMX;
397 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
398 result |= CPU_SSE;
399 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
400 result |= CPU_SSE2;
401 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
402 result |= CPU_SSE3;
403 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
404 result |= CPU_SSSE3;
405 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
406 result |= CPU_SSE4_1;
407 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
408 result |= CPU_SSE4_2;
409 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
410 result |= CPU_POPCNT;
411 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
412 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
413 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
414 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
415 result |= CPU_AVX;
416 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
417 result |= CPU_AVX2;
418 }
419 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
420 result |= CPU_TSC;
421 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
422 result |= CPU_TSCINV;
424 // AMD features.
425 if (is_amd()) {
426 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
427 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
428 result |= CPU_3DNOW_PREFETCH;
429 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
430 result |= CPU_LZCNT;
431 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
432 result |= CPU_SSE4A;
433 }
435 return result;
436 }
438 static void get_processor_features();
440 public:
441 // Offsets for cpuid asm stub
442 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
443 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
444 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
445 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
446 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
447 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
448 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
449 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
450 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
451 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
452 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
453 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
455 // Initialization
456 static void initialize();
458 // Asserts
459 static void assert_is_initialized() {
460 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
461 }
463 //
464 // Processor family:
465 // 3 - 386
466 // 4 - 486
467 // 5 - Pentium
468 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
469 // Pentium M, Core Solo, Core Duo, Core2 Duo
470 // family 6 model: 9, 13, 14, 15
471 // 0x0f - Pentium 4, Opteron
472 //
473 // Note: The cpu family should be used to select between
474 // instruction sequences which are valid on all Intel
475 // processors. Use the feature test functions below to
476 // determine whether a particular instruction is supported.
477 //
478 static int cpu_family() { return _cpu;}
479 static bool is_P6() { return cpu_family() >= 6; }
480 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
481 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
483 static bool supports_processor_topology() {
484 return (_cpuid_info.std_max_function >= 0xB) &&
485 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
486 // Some cpus have max cpuid >= 0xB but do not support processor topology.
487 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
488 }
490 static uint cores_per_cpu() {
491 uint result = 1;
492 if (is_intel()) {
493 if (supports_processor_topology()) {
494 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
495 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
496 } else {
497 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
498 }
499 } else if (is_amd()) {
500 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
501 }
502 return result;
503 }
505 static uint threads_per_core() {
506 uint result = 1;
507 if (is_intel() && supports_processor_topology()) {
508 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
509 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
510 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
511 cores_per_cpu();
512 }
513 return result;
514 }
516 static intx prefetch_data_size() {
517 intx result = 0;
518 if (is_intel()) {
519 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
520 } else if (is_amd()) {
521 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
522 }
523 if (result < 32) // not defined ?
524 result = 32; // 32 bytes by default on x86 and other x64
525 return result;
526 }
528 //
529 // Feature identification
530 //
531 static bool supports_cpuid() { return _cpuFeatures != 0; }
532 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
533 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; }
534 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; }
535 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; }
536 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; }
537 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; }
538 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; }
539 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; }
540 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; }
541 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; }
542 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; }
543 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; }
544 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; }
545 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; }
546 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; }
548 // Intel features
549 static bool is_intel_family_core() { return is_intel() &&
550 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
552 static bool is_intel_tsc_synched_at_init() {
553 if (is_intel_family_core()) {
554 uint32_t ext_model = extended_cpu_model();
555 if (ext_model == CPU_MODEL_NEHALEM_EP ||
556 ext_model == CPU_MODEL_WESTMERE_EP ||
557 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
558 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
559 // <= 2-socket invariant tsc support. EX versions are usually used
560 // in > 2-socket systems and likely don't synchronize tscs at
561 // initialization.
562 // Code that uses tsc values must be prepared for them to arbitrarily
563 // jump forward or backward.
564 return true;
565 }
566 }
567 return false;
568 }
570 // AMD features
571 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
572 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
573 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; }
574 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; }
576 static bool is_amd_Barcelona() { return is_amd() &&
577 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
579 // Intel and AMD newer cores support fast timestamps well
580 static bool supports_tscinv_bit() {
581 return (_cpuFeatures & CPU_TSCINV) != 0;
582 }
583 static bool supports_tscinv() {
584 return supports_tscinv_bit() &&
585 ( (is_amd() && !is_amd_Barcelona()) ||
586 is_intel_tsc_synched_at_init() );
587 }
589 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
590 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
591 supports_sse3() && _model != 0x1C; }
593 static bool supports_compare_and_exchange() { return true; }
595 static const char* cpu_features() { return _features_str; }
597 static intx allocate_prefetch_distance() {
598 // This method should be called before allocate_prefetch_style().
599 //
600 // Hardware prefetching (distance/size in bytes):
601 // Pentium 3 - 64 / 32
602 // Pentium 4 - 256 / 128
603 // Athlon - 64 / 32 ????
604 // Opteron - 128 / 64 only when 2 sequential cache lines accessed
605 // Core - 128 / 64
606 //
607 // Software prefetching (distance in bytes / instruction with best score):
608 // Pentium 3 - 128 / prefetchnta
609 // Pentium 4 - 512 / prefetchnta
610 // Athlon - 128 / prefetchnta
611 // Opteron - 256 / prefetchnta
612 // Core - 256 / prefetchnta
613 // It will be used only when AllocatePrefetchStyle > 0
615 intx count = AllocatePrefetchDistance;
616 if (count < 0) { // default ?
617 if (is_amd()) { // AMD
618 if (supports_sse2())
619 count = 256; // Opteron
620 else
621 count = 128; // Athlon
622 } else { // Intel
623 if (supports_sse2())
624 if (cpu_family() == 6) {
625 count = 256; // Pentium M, Core, Core2
626 } else {
627 count = 512; // Pentium 4
628 }
629 else
630 count = 128; // Pentium 3 (and all other old CPUs)
631 }
632 }
633 return count;
634 }
635 static intx allocate_prefetch_style() {
636 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
637 // Return 0 if AllocatePrefetchDistance was not defined.
638 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
639 }
641 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
642 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
643 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
644 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
646 // gc copy/scan is disabled if prefetchw isn't supported, because
647 // Prefetch::write emits an inlined prefetchw on Linux.
648 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
649 // The used prefetcht0 instruction works for both amd64 and em64t.
650 static intx prefetch_copy_interval_in_bytes() {
651 intx interval = PrefetchCopyIntervalInBytes;
652 return interval >= 0 ? interval : 576;
653 }
654 static intx prefetch_scan_interval_in_bytes() {
655 intx interval = PrefetchScanIntervalInBytes;
656 return interval >= 0 ? interval : 576;
657 }
658 static intx prefetch_fields_ahead() {
659 intx count = PrefetchFieldsAhead;
660 return count >= 0 ? count : 1;
661 }
662 };
664 #endif // CPU_X86_VM_VM_VERSION_X86_HPP
