Mercurial > jdk8-mips64-public > hotspot / file revision
src/cpu/mips/vm/nativeInst_mips.cpp@d885f8d65c58
src/cpu/mips/vm/nativeInst_mips.cpp
Tue, 26 Jul 2016 17:06:17 +0800
- author
- fujie
- date
- Tue, 26 Jul 2016 17:06:17 +0800
- changeset 41
- d885f8d65c58
- parent 1
- 2d8a650513c2
- child 129
- ef84e7428333
- permissions
- -rw-r--r--
Add multiply word to GPR instruction (mul) in MIPS assembler.
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "nativeInst_mips.hpp"
30 #include "oops/oop.inline.hpp"
31 #include "runtime/handles.hpp"
32 #include "runtime/sharedRuntime.hpp"
33 #include "runtime/stubRoutines.hpp"
34 #include "utilities/ostream.hpp"
35 #ifdef COMPILER1
36 #include "c1/c1_Runtime1.hpp"
37 #endif
39 #include <sys/mman.h>
41 void NativeInstruction::wrote(int offset) {
42 ICache::invalidate_word(addr_at(offset));
43 }
45 void NativeInstruction::set_long_at(int offset, long i) {
46 address addr = addr_at(offset);
47 *(long*)addr = i;
48 //ICache::invalidate_word(addr);
49 }
51 static int illegal_instruction_bits = 0;
53 int NativeInstruction::illegal_instruction() {
54 if (illegal_instruction_bits == 0) {
55 ResourceMark rm;
56 char buf[40];
57 CodeBuffer cbuf((address)&buf[0], 20);
58 MacroAssembler* a = new MacroAssembler(&cbuf);
59 address ia = a->pc();
60 a->brk(11);
61 int bits = *(int*)ia;
62 illegal_instruction_bits = bits;
63 }
64 return illegal_instruction_bits;
65 }
67 bool NativeInstruction::is_int_branch() {
68 switch(Assembler::opcode(insn_word())) {
69 case Assembler::beq_op:
70 case Assembler::beql_op:
71 case Assembler::bgtz_op:
72 case Assembler::bgtzl_op:
73 case Assembler::blez_op:
74 case Assembler::blezl_op:
75 case Assembler::bne_op:
76 case Assembler::bnel_op:
77 return true;
78 case Assembler::regimm_op:
79 switch(Assembler::rt(insn_word())) {
80 case Assembler::bgez_op:
81 case Assembler::bgezal_op:
82 case Assembler::bgezall_op:
83 case Assembler::bgezl_op:
84 case Assembler::bltz_op:
85 case Assembler::bltzal_op:
86 case Assembler::bltzall_op:
87 case Assembler::bltzl_op:
88 return true;
89 }
90 }
92 return false;
93 }
95 bool NativeInstruction::is_float_branch() {
96 if (!is_op(Assembler::cop1_op) ||
97 !is_rs((Register)Assembler::bc_op)) return false;
99 switch(Assembler::rt(insn_word())) {
100 case Assembler::bcf_op:
101 case Assembler::bcfl_op:
102 case Assembler::bct_op:
103 case Assembler::bctl_op:
104 return true;
105 }
107 return false;
108 }
111 //-------------------------------------------------------------------
113 void NativeCall::verify() {
114 // make sure code pattern is actually a call instruction
115 #ifndef _LP64
116 if ( !is_op(Assembler::lui_op) ||
117 !is_op(int_at(4), Assembler::addiu_op) ||
118 !is_special_op(int_at(8), Assembler::jalr_op) ) {
119 fatal("not a call");
120 }
121 #else
122 /* li64 or li48 */
123 int li_64 = 0;
124 int li_48 = 0;
126 if ( is_op (Assembler::lui_op) &&
127 is_op (int_at(4), Assembler::ori_op) &&
128 is_special_op(int_at(8), Assembler::dsll_op) &&
129 is_op (int_at(12), Assembler::ori_op) &&
130 is_special_op(int_at(16), Assembler::dsll_op) &&
131 is_op (int_at(20), Assembler::ori_op) &&
132 is_special_op(int_at(24), Assembler::jalr_op) ) {
133 li_64 = 1;
134 }
136 if ( is_op (Assembler::lui_op) &&
137 is_op (int_at(4), Assembler::ori_op) &&
138 is_special_op(int_at(8), Assembler::dsll_op) &&
139 is_op (int_at(12), Assembler::ori_op) &&
140 is_special_op(int_at(16), Assembler::jalr_op) ) {
141 li_48 = 1;
142 }
144 if (!li_64 && !li_48) {
145 tty->print_cr("NativeCall::verify addr=%lx", addr_at(0));
146 fatal("not a call");
147 }
148 #endif
149 }
151 address NativeCall::destination() const {
152 #ifndef _LP64
153 return (address)Assembler::merge(int_at(4)&0xffff, long_at(0)&0xffff);
154 #else
155 /* li64 or li48 */
156 if (is_special_op(int_at(16), Assembler::dsll_op)) {
157 return (address)Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
158 (intptr_t)(int_at(12) & 0xffff),
159 (intptr_t)(int_at(4) & 0xffff),
160 (intptr_t)(int_at(0) & 0xffff));
161 } else if (is_special_op(int_at(16), Assembler::jalr_op)) {
162 return (address)Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
163 (intptr_t)(int_at(4) & 0xffff),
164 (intptr_t)(int_at(0) & 0xffff),
165 (intptr_t)0);
166 }
167 #endif
168 }
170 /* 2013/6/14 Jin: manual implementation of GSSQ
171 *
172 * 00000001200009c0 <atomic_store128>:
173 * 1200009c0: 0085202d daddu a0, a0, a1
174 * 1200009c4: e8860027 gssq a2, a3, 0(a0)
175 * 1200009c8: 03e00008 jr ra
176 * 1200009cc: 00000000 nop
177 */
178 typedef void (* atomic_store128_ptr)(long *addr, int offset, long low64, long hi64);
180 static int *buf;
182 static atomic_store128_ptr get_atomic_store128_func()
183 {
184 static atomic_store128_ptr p = NULL;
185 if (p != NULL)
186 return p;
188 buf = (int *)mmap(NULL, 1024, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS,
189 -1, 0);
190 buf[0] = 0x0085202d;
191 buf[1] = (0x3a << 26) | (4 << 21) | (6 << 16) | 0x27; /* gssq $a2, $a3, 0($a0) */
192 buf[2] = 0x03e00008;
193 buf[3] = 0;
195 p = (atomic_store128_ptr)buf;
196 return p;
197 }
199 void NativeCall::set_destination(address dest) {
200 #ifndef _LP64
201 OrderAccess::fence();
202 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high((intptr_t)dest) & 0xffff));
203 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
204 ICache::invalidate_range(addr_at(0), 8);
205 #else
206 OrderAccess::fence();
207 /* 2013/6/13 Jin: ensure 100% atomicity */
208 guarantee(!os::is_MP() || (((long)addr_at(0) % 16) == 0), "destination must be aligned for GSSD");
210 /* li64 or li48 */
211 if (is_special_op(int_at(16), Assembler::dsll_op)) {
212 int first_word = int_at(0);
213 set_int_at(0, 0x1000ffff); /* .1: b .1 */
214 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 32) & 0xffff));
215 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 16) & 0xffff));
216 set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
217 set_int_at(0, (first_word & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 48) & 0xffff));
218 ICache::invalidate_range(addr_at(0), 24);
219 } else if (is_special_op(int_at(16), Assembler::jalr_op)) {
220 int insts[4];
221 insts[0] = (int_at(0) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 32) & 0xffff);
222 insts[1] = (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 16) & 0xffff);
223 insts[2] = int_at(8);
224 insts[3] = (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff);
226 atomic_store128_ptr func = get_atomic_store128_func();
227 (*func)((long *)addr_at(0), 0, *(long *)&insts[0], *(long *)&insts[2]);
228 } else {
229 fatal("not a call");
230 }
231 #endif
232 }
234 void NativeCall::print() {
235 tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
236 instruction_address(), destination());
237 }
239 // Inserts a native call instruction at a given pc
240 void NativeCall::insert(address code_pos, address entry) {
241 NativeCall *call = nativeCall_at(code_pos);
242 CodeBuffer cb(call->addr_at(0), instruction_size);
243 MacroAssembler masm(&cb);
244 #define __ masm.
245 #ifndef _LP64
246 __ lui(T9, Assembler::split_high((int)entry));
247 __ addiu(T9, T9, Assembler::split_low((int)entry));
248 #else
249 __ li48(T9, (long)entry);
250 #endif
251 __ jalr ();
252 __ delayed()->nop();
253 #undef __
255 ICache::invalidate_range(call->addr_at(0), instruction_size);
256 }
258 // MT-safe patching of a call instruction.
259 // First patches first word of instruction to two jmp's that jmps to them
260 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
261 // the jmp's with the first 4 byte of the new instruction.
262 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
263 Unimplemented();
264 }
266 //-------------------------------------------------------------------
268 void NativeMovConstReg::verify() {
269 #ifndef _LP64
270 if ( !is_op(Assembler::lui_op) ||
271 !is_op(int_at(4), Assembler::addiu_op) )
272 fatal("not a mov reg, imm32")
273 #else
274 /* li64 or li48 */
275 int li_64 = 0;
276 int li_48 = 0;
278 if ( is_op(Assembler::lui_op) &&
279 is_op(int_at(4), Assembler::ori_op) &&
280 is_special_op(int_at(8), Assembler::dsll_op) &&
281 is_op(int_at(12), Assembler::ori_op) &&
282 is_special_op(int_at(16), Assembler::dsll_op) &&
283 is_op(int_at(20), Assembler::ori_op) )
284 {
285 li_64 = 1;
286 }
288 if ( is_op(Assembler::lui_op) &&
289 is_op (int_at(4), Assembler::ori_op) &&
290 is_special_op(int_at(8), Assembler::dsll_op) &&
291 is_op (int_at(12), Assembler::ori_op) ) {
292 li_48 = 1;
293 }
295 if (!li_64 && !li_48) {
296 fatal("not a mov reg, imm64/imm48");
297 }
298 #endif
299 }
301 void NativeMovConstReg::print() {
302 tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
303 instruction_address(), data());
304 }
306 intptr_t NativeMovConstReg::data() const {
307 #ifndef _LP64
308 return Assembler::merge(int_at(4)&0xffff, long_at(0)&0xffff);
309 #else
310 /* li64 or li48 */
311 if (is_special_op(int_at(16), Assembler::dsll_op) && is_op(long_at(20), Assembler::ori_op)) {
312 return Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
313 (intptr_t)(int_at(12) & 0xffff),
314 (intptr_t)(int_at(4) & 0xffff),
315 (intptr_t)(int_at(0) & 0xffff));
316 } else {
317 return Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
318 (intptr_t)(int_at(4) & 0xffff),
319 (intptr_t)(int_at(0) & 0xffff),
320 (intptr_t)0);
321 }
322 #endif
323 }
325 void NativeMovConstReg::set_data(intptr_t x) {
326 /*
327 #ifndef CORE
328 // also store the value into an oop_Relocation cell, if any
329 CodeBlob* cb = CodeCache::find_blob(instruction_address());
330 nmethod* nm = cb ? cb->as_nmethod_or_null() : NULL;
331 if (nm != NULL) {
332 RelocIterator iter(nm, instruction_address(), instruction_address() + 1);
333 oop* oop_addr = NULL;
334 while (iter.next()) {
335 if (iter.type() == relocInfo::oop_type) {
336 oop_Relocation *r = iter.oop_reloc();
337 if (oop_addr == NULL && r->oop_index()!=0) {
338 oop_addr = r->oop_addr();
339 *oop_addr = (oop)x;
340 } else {
341 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
342 }
343 }
344 }
345 }
346 #endif
347 */
349 #ifndef _LP64
350 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high(x) & 0xffff));
351 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low(x) & 0xffff));
352 ICache::invalidate_range(addr_at(0), 8);
353 #else
354 /* li64 or li48 */
355 if (is_special_op(int_at(16), Assembler::dsll_op) && is_op(long_at(20), Assembler::ori_op)) {
356 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 48) & 0xffff));
357 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 32) & 0xffff));
358 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 16) & 0xffff));
359 set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)x) & 0xffff));
360 } else {
361 //assert(is_simm16(dest >> 32), "Not a 48-bit address");
362 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 32) & 0xffff));
363 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)x >> 16) & 0xffff));
364 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)x) & 0xffff));
365 }
366 ICache::invalidate_range(addr_at(0), 24);
367 #endif
368 }
370 //-------------------------------------------------------------------
372 int NativeMovRegMem::offset() const{
373 if (is_immediate())
374 return (short)(int_at(instruction_offset)&0xffff);
375 else
376 return Assembler::merge(int_at(hiword_offset)&0xffff, long_at(instruction_offset)&0xffff);
377 }
379 void NativeMovRegMem::set_offset(int x) {
380 if (is_immediate()) {
381 assert(Assembler::is_simm16(x), "just check");
382 set_int_at(0, (int_at(0)&0xffff0000) | (x&0xffff) );
383 if (is_64ldst()) {
384 assert(Assembler::is_simm16(x+4), "just check");
385 set_int_at(4, (int_at(4)&0xffff0000) | ((x+4)&0xffff) );
386 }
387 } else {
388 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high(x) & 0xffff));
389 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low(x) & 0xffff));
390 }
391 ICache::invalidate_range(addr_at(0), 8);
392 }
394 void NativeMovRegMem::verify() {
395 int offset = 0;
397 if ( Assembler::opcode(int_at(0)) == Assembler::lui_op ) {
398 #ifndef _LP64
399 if ( (Assembler::opcode(int_at(4)) != Assembler::addiu_op) ||
400 (Assembler::opcode(int_at(8)) != Assembler::special_op) ||
401 (Assembler::special(int_at(8)) != Assembler::add_op))
402 #else
403 /* Jin: fit MIPS64 */
404 if ( (Assembler::opcode(int_at(4)) != Assembler::addiu_op &&
405 Assembler::opcode(int_at(4)) != Assembler::daddiu_op ) ||
406 (Assembler::opcode(int_at(8)) != Assembler::special_op) ||
407 (Assembler::special(int_at(8)) != Assembler::add_op
408 && Assembler::special(int_at(8)) != Assembler::dadd_op))
409 #endif
410 fatal ("not a mov [reg+offs], reg instruction");
411 offset += 12;
412 }
414 switch(Assembler::opcode(int_at(offset))) {
415 case Assembler::lb_op:
416 case Assembler::lbu_op:
417 case Assembler::lh_op:
418 case Assembler::lhu_op:
419 case Assembler::lw_op:
420 LP64_ONLY(case Assembler::ld_op:)
421 case Assembler::lwc1_op:
422 LP64_ONLY(case Assembler::ldc1_op:)
423 case Assembler::sb_op:
424 case Assembler::sh_op:
425 case Assembler::sw_op:
426 LP64_ONLY(case Assembler::sd_op:)
427 case Assembler::swc1_op:
428 LP64_ONLY(case Assembler::sdc1_op:)
429 break;
430 default:
431 fatal ("not a mov [reg+offs], reg instruction");
432 }
433 }
436 void NativeMovRegMem::print() {
437 tty->print_cr("0x%x: mov reg, [reg + %x]", instruction_address(), offset());
438 }
442 void NativeIllegalInstruction::insert(address code_pos) {
443 CodeBuffer cb(code_pos, instruction_size);
444 MacroAssembler masm(&cb);
445 #define __ masm.
446 __ brk(11);
447 #undef __
449 ICache::invalidate_range(code_pos, instruction_size);
450 }
452 void NativeGeneralJump::verify() {
453 assert(((NativeInstruction *)this)->is_jump() ||
454 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
455 }
458 void NativeGeneralJump::set_jump_destination(address dest) {
459 //tty->print_cr("NativeGeneralJump::set_jump_destination dest=%lx", dest);
460 OrderAccess::fence();
462 if (is_short()) {
463 assert(Assembler::is_simm16(dest-addr_at(4)), "change this code");
464 set_int_at(0, (int_at(0) & 0xffff0000) | (dest - addr_at(4)) & 0xffff );
465 ICache::invalidate_range(addr_at(0), 4);
466 #ifdef _LP64
467 } else if (is_b_far()) {
468 int offset = dest - addr_at(12);
469 set_int_at(12, (int_at(12) & 0xffff0000) | (offset >> 16));
470 set_int_at(16, (int_at(16) & 0xffff0000) | (offset & 0xffff));
471 #endif
472 } else {
473 #ifndef _LP64
474 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_high((intptr_t)dest) & 0xffff));
475 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
476 ICache::invalidate_range(addr_at(0), 8);
477 #else
478 /* li64 or li48 */
479 if (is_special_op(int_at(16), Assembler::dsll_op)) {
480 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 48) & 0xffff));
481 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 32) & 0xffff));
482 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 16) & 0xffff));
483 set_int_at(20, (int_at(20) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
484 } else {
485 int jr_word = int_at(16);
486 set_int_at(16, 0x1000fffb); /* .1: --; --; --; --; b .1; nop */
488 set_int_at(0, (int_at(0) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 32) & 0xffff));
489 set_int_at(4, (int_at(4) & 0xffff0000) | (Assembler::split_low((intptr_t)dest >> 16) & 0xffff));
490 set_int_at(12, (int_at(12) & 0xffff0000) | (Assembler::split_low((intptr_t)dest) & 0xffff));
491 set_int_at(16, jr_word); /* .1: --; --; --; --; jr ; nop */
492 }
494 ICache::invalidate_range(addr_at(0), 24);
495 #endif
496 }
497 }
499 // we now use b to do this. be careful when using this method
500 // by yjl 9/16/2005
501 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
502 CodeBuffer cb(code_pos, instruction_size);
503 MacroAssembler masm(&cb);
504 #define __ masm.
505 #ifdef _LP64
506 if (Assembler::is_simm16((entry - code_pos - 4) / 4))
507 {
508 __ b(entry);
509 __ delayed()->nop();
510 }
511 else
512 {
513 /* a simplified b_far */
514 int offset = entry - code_pos;
516 // FIXME: need to preserve RA?
517 __ emit_long(0x4110001); //__ emit_long(Assembler::insn_ORRI(Assembler::regimm_op, 0, Assembler::bgezal_op, 1));
518 __ lui(T9, (offset - 8) >> 16); // delay slot
519 __ ori(T9, T9, (offset - 8) & 0xffff);
520 __ daddu(T9, T9, RA);
521 __ jr(T9);
522 __ nop();
523 }
524 #else
525 __ b(entry);
526 __ delayed()->nop();
527 #endif
528 #undef __
530 ICache::invalidate_range(code_pos, instruction_size);
531 }
533 #ifdef _LP64
534 bool NativeGeneralJump::is_b_far() {
535 /*
536 0x000000556809f198: dadd at, ra, zero
537 0x000000556809f19c: [4110001]bgezal zero, 0x000000556809f1a4
539 0x000000556809f1a0: nop
540 0x000000556809f1a4: lui t9, 0xfffffffd
541 0x000000556809f1a8: ori t9, t9, 0x14dc
542 0x000000556809f1ac: daddu t9, t9, ra
543 0x000000556809f1b0: dadd ra, at, zero
544 0x000000556809f1b4: jr t9
545 0x000000556809f1b8: nop
546 ;; ImplicitNullCheckStub slow case
547 0x000000556809f1bc: lui t9, 0x55
548 */
549 return is_op(int_at(12), Assembler::lui_op);
550 }
551 #endif
553 address NativeGeneralJump::jump_destination() {
554 if ( is_short() ) {
555 return addr_at(4) + Assembler::imm_off(int_at(instruction_offset)) * 4;
556 }
557 #ifndef _LP64
558 return (address)Assembler::merge(int_at(4)&0xffff, long_at(instruction_offset)&0xffff);
559 #else
560 /* 2012/4/19 Jin: Assembler::merge() is not correct in MIPS_64!
562 Example:
563 hi16 = 0xfffd,
564 lo16 = f7a4,
566 offset=0xfffdf7a4 (Right)
567 Assembler::merge = 0xfffcf7a4 (Wrong)
568 */
569 if ( is_b_far() ) {
570 int hi16 = int_at(12)&0xffff;
571 int low16 = int_at(16)&0xffff;
572 address target = addr_at(12) + (hi16 << 16) + low16;
573 return target;
574 }
576 /* li64 or li48 */
577 if (is_special_op(int_at(16), Assembler::dsll_op)) {
578 return (address)Assembler::merge( (intptr_t)(int_at(20) & 0xffff),
579 (intptr_t)(int_at(12) & 0xffff),
580 (intptr_t)(int_at(4) & 0xffff),
581 (intptr_t)(int_at(0) & 0xffff));
582 } else {
583 return (address)Assembler::merge( (intptr_t)(int_at(12) & 0xffff),
584 (intptr_t)(int_at(4) & 0xffff),
585 (intptr_t)(int_at(0) & 0xffff),
586 ((int_at(0) & 0xffff) >= 0x8000) ? (intptr_t)0xffff : (intptr_t)0); /* sign-extended to 64-bit*/
587 }
588 #endif
589 }
591 // MT-safe patching of a long jump instruction.
592 // First patches first word of instruction to two jmp's that jmps to them
593 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
594 // the jmp's with the first 4 byte of the new instruction.
595 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
596 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr);
597 assert(NativeGeneralJump::instruction_size == NativeCall::instruction_size,
598 "note::Runtime1::patch_code uses NativeCall::instruction_size");
600 /* 2013/6/13 Jin: ensure 100% atomicity */
601 guarantee(!os::is_MP() || (((long)instr_addr % BytesPerWord) == 0), "destination must be aligned for SD");
603 int *p = (int *)instr_addr;
604 int jr_word = p[4];
606 p[4] = 0x1000fffb; /* .1: --; --; --; --; b .1; nop */
607 memcpy(instr_addr, code_buffer, NativeCall::instruction_size - 8);
608 *(long *)(instr_addr + 16) = *(long *)(code_buffer + 16);
609 }
611 /* Must ensure atomicity */
612 void NativeGeneralJump::patch_verified_entry(address entry, address verified_entry, address dest) {
613 /* 2013/11/5 Jin: ensure 100% atomicity.
614 * The destination is fixed and can be cached in JavaThread.
615 */
616 guarantee(!os::is_MP() || (((long)verified_entry % BytesPerWord) == 0), "destination must be aligned for SD");
618 int code_buffer[4];
620 CodeBuffer cb((address)code_buffer, instruction_size);
621 MacroAssembler masm(&cb);
622 #define __ masm.
623 __ ld(T9, TREG, in_bytes(JavaThread::handle_wrong_method_stub_offset()));
624 __ jr(T9);
625 __ delayed()->nop();
626 __ nop();
628 atomic_store128_ptr func = get_atomic_store128_func();
629 (*func)((long *)verified_entry, 0, *(long *)&code_buffer[0], *(long *)&code_buffer[2]);
631 ICache::invalidate_range(verified_entry, instruction_size);
632 }
634 bool NativeInstruction::is_jump()
635 {
636 #ifndef _LP64
637 return ((int_at(0) & NativeGeneralJump::b_mask) == NativeGeneralJump::beq_opcode) ||
638 (is_op(int_at(0), Assembler::lui_op) &&
639 is_op(int_at(4), Assembler::addiu_op) &&
640 is_special_op(int_at(8), Assembler::jr_op));
641 #else
642 // lui rd, imm(63...48);
643 // ori rd, rd, imm(47...32);
644 // dsll rd, rd, 16;
645 // ori rd, rd, imm(31...16);
646 // dsll rd, rd, 16;
647 // ori rd, rd, imm(15...0);
648 // jalr rd
649 // nop
650 //
651 if ((int_at(0) & NativeGeneralJump::b_mask) == NativeGeneralJump::beq_opcode)
652 return true;
653 if (is_op(int_at(4), Assembler::lui_op)) /* simplified b_far */
654 return true;
655 if (is_op(int_at(12), Assembler::lui_op)) /* original b_far */
656 return true;
657 if (is_op(int_at(0), Assembler::lui_op) &&
658 is_op(int_at(4), Assembler::ori_op) &&
659 is_special_op(int_at(8), Assembler::dsll_op) &&
660 is_op(int_at(12), Assembler::ori_op) &&
661 is_special_op(int_at(16), Assembler::dsll_op) &&
662 is_op(int_at(20), Assembler::ori_op))
663 return true;
664 if (is_op(int_at(0), Assembler::lui_op) &&
665 is_op(int_at(4), Assembler::ori_op) &&
666 is_special_op(int_at(8), Assembler::dsll_op) &&
667 is_op(int_at(12), Assembler::ori_op))
668 return true;
669 return false;
670 #endif
671 }
673 bool NativeInstruction::is_dtrace_trap() {
674 //return (*(int32_t*)this & 0xff) == 0xcc;
675 Unimplemented();
676 return false;
677 }
679 // is mips we have to use two instruction to poll, however, we don't want to bother checking two instructions
680 // instead, we use a lw $0, at() as the second instruction, and only check this.
681 // change ZERO -> AT, only in godson-2e @jerome,11/25/2006
682 bool NativeInstruction::is_safepoint_poll() {
683 #ifdef _LP64
684 /*
685 0x0000005565d28868: lui t2, 0x0 ; -24
686 0x0000005565d2886c: ori t2, t2, 0x55 ; -20
687 0x0000005565d28870: dsll t2, t2, 16 ; -16
688 0x0000005565d28874: ori t2, t2, 0x6428 ; -12
689 0x0000005565d28878: dsll t2, t2, 16 ; -8
690 0x0000005565d2887c: ori t2, t2, 0x100 ; -4
691 0x0000005565d28880: lw at, 0x0(t2) <-- PC
692 */
693 #ifndef OPT_SAFEPOINT
694 /* li64 or li48 */
695 if (is_op(Assembler::lw_op) && is_rt(AT)) {
696 return true;
697 } else if (is_special_op(long_at(-16), Assembler::dsll_op)) {
698 /* li64 */
699 return (is_op(int_at(-24), Assembler::lui_op) &&
700 is_op(int_at(-20), Assembler::ori_op) &&
701 is_special_op(int_at(-16), Assembler::dsll_op) &&
702 is_op(int_at(-12), Assembler::ori_op) &&
703 is_special_op(int_at(-8), Assembler::dsll_op) &&
704 is_op(int_at(-4), Assembler::ori_op) &&
705 is_op(Assembler::lw_op) &&
706 is_rt(AT));
707 } else if (is_op(int_at(-16), Assembler::lui_op)) {
708 /* li48 */
709 return is_op(int_at(-16), Assembler::lui_op) &&
710 is_op(int_at(-12), Assembler::ori_op) &&
711 is_special_op(int_at(-8), Assembler::dsll_op) &&
712 is_op(int_at(-4), Assembler::ori_op) &&
713 is_op(Assembler::lw_op) &&
714 is_rt(AT);
715 } else {
716 return false;
717 }
718 #else // OPT_SAFEPOINT
719 return is_op(int_at(-4), Assembler::lui_op) &&
720 is_op(Assembler::lw_op) &&
721 is_rt(AT);
722 #endif
723 #else
724 return is_op(int_at(-4), Assembler::lui_op) &&
725 is_op(Assembler::lw_op) &&
726 is_rt(AT);
727 #endif
728 }
