Thu, 26 Mar 2009 14:31:45 -0700
6822204: volatile fences should prefer lock:addl to actual mfence instructions
Reviewed-by: kvn, phh
1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
242 #define __ _masm.
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
282 static int sizeof_FFree_Float_Stack_All = -1;
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
295 //
296 // Compute padding required for nodes which need alignment
297 //
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
607 }
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
669 emit_opcode(cbuf, 0x58 | EBP_enc);
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
690 size++; // popl rbp,
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
708 int MachEpilogNode::safepoint_offset() const { return 0; }
710 //=============================================================================
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
886 // Generate spill code!
887 int size = 0;
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1042 assert( size > 0, "missed a case" );
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1063 Unimplemented();
1064 }
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1133 //=============================================================================
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1284 int Matcher::regnum_to_fpu_offset(int regnum) {
1285 return regnum - 32; // The FP registers are in the second chunk
1286 }
1288 bool is_positive_zero_float(jfloat f) {
1289 return jint_cast(f) == jint_cast(0.0F);
1290 }
1292 bool is_positive_one_float(jfloat f) {
1293 return jint_cast(f) == jint_cast(1.0F);
1294 }
1296 bool is_positive_zero_double(jdouble d) {
1297 return jlong_cast(d) == jlong_cast(0.0);
1298 }
1300 bool is_positive_one_double(jdouble d) {
1301 return jlong_cast(d) == jlong_cast(1.0);
1302 }
1304 // This is UltraSparc specific, true just means we have fast l2f conversion
1305 const bool Matcher::convL2FSupported(void) {
1306 return true;
1307 }
1309 // Vector width in bytes
1310 const uint Matcher::vector_width_in_bytes(void) {
1311 return UseSSE >= 2 ? 8 : 0;
1312 }
1314 // Vector ideal reg
1315 const uint Matcher::vector_ideal_reg(void) {
1316 return Op_RegD;
1317 }
1319 // Is this branch offset short enough that a short branch can be used?
1320 //
1321 // NOTE: If the platform does not provide any short branch variants, then
1322 // this method should return false for offset 0.
1323 bool Matcher::is_short_branch_offset(int rule, int offset) {
1324 // the short version of jmpConUCF2 contains multiple branches,
1325 // making the reach slightly less
1326 if (rule == jmpConUCF2_rule)
1327 return (-126 <= offset && offset <= 125);
1328 return (-128 <= offset && offset <= 127);
1329 }
1331 const bool Matcher::isSimpleConstant64(jlong value) {
1332 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1333 return false;
1334 }
1336 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1337 const bool Matcher::init_array_count_is_in_bytes = false;
1339 // Threshold size for cleararray.
1340 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1342 // Should the Matcher clone shifts on addressing modes, expecting them to
1343 // be subsumed into complex addressing expressions or compute them into
1344 // registers? True for Intel but false for most RISCs
1345 const bool Matcher::clone_shift_expressions = true;
1347 // Is it better to copy float constants, or load them directly from memory?
1348 // Intel can load a float constant from a direct address, requiring no
1349 // extra registers. Most RISCs will have to materialize an address into a
1350 // register first, so they would do better to copy the constant from stack.
1351 const bool Matcher::rematerialize_float_constants = true;
1353 // If CPU can load and store mis-aligned doubles directly then no fixup is
1354 // needed. Else we split the double into 2 integer pieces and move it
1355 // piece-by-piece. Only happens when passing doubles into C code as the
1356 // Java calling convention forces doubles to be aligned.
1357 const bool Matcher::misaligned_doubles_ok = true;
1360 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1361 // Get the memory operand from the node
1362 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1363 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1364 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1365 uint opcnt = 1; // First operand
1366 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1367 while( idx >= skipped+num_edges ) {
1368 skipped += num_edges;
1369 opcnt++; // Bump operand count
1370 assert( opcnt < numopnds, "Accessing non-existent operand" );
1371 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1372 }
1374 MachOper *memory = node->_opnds[opcnt];
1375 MachOper *new_memory = NULL;
1376 switch (memory->opcode()) {
1377 case DIRECT:
1378 case INDOFFSET32X:
1379 // No transformation necessary.
1380 return;
1381 case INDIRECT:
1382 new_memory = new (C) indirect_win95_safeOper( );
1383 break;
1384 case INDOFFSET8:
1385 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1386 break;
1387 case INDOFFSET32:
1388 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1389 break;
1390 case INDINDEXOFFSET:
1391 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1392 break;
1393 case INDINDEXSCALE:
1394 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1395 break;
1396 case INDINDEXSCALEOFFSET:
1397 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1398 break;
1399 case LOAD_LONG_INDIRECT:
1400 case LOAD_LONG_INDOFFSET32:
1401 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1402 return;
1403 default:
1404 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1405 return;
1406 }
1407 node->_opnds[opcnt] = new_memory;
1408 }
1410 // Advertise here if the CPU requires explicit rounding operations
1411 // to implement the UseStrictFP mode.
1412 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1414 // Do floats take an entire double register or just half?
1415 const bool Matcher::float_in_double = true;
1416 // Do ints take an entire long register or just half?
1417 const bool Matcher::int_in_long = false;
1419 // Return whether or not this register is ever used as an argument. This
1420 // function is used on startup to build the trampoline stubs in generateOptoStub.
1421 // Registers not mentioned will be killed by the VM call in the trampoline, and
1422 // arguments in those registers not be available to the callee.
1423 bool Matcher::can_be_java_arg( int reg ) {
1424 if( reg == ECX_num || reg == EDX_num ) return true;
1425 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1426 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1427 return false;
1428 }
1430 bool Matcher::is_spillable_arg( int reg ) {
1431 return can_be_java_arg(reg);
1432 }
1434 // Register for DIVI projection of divmodI
1435 RegMask Matcher::divI_proj_mask() {
1436 return EAX_REG_mask;
1437 }
1439 // Register for MODI projection of divmodI
1440 RegMask Matcher::modI_proj_mask() {
1441 return EDX_REG_mask;
1442 }
1444 // Register for DIVL projection of divmodL
1445 RegMask Matcher::divL_proj_mask() {
1446 ShouldNotReachHere();
1447 return RegMask();
1448 }
1450 // Register for MODL projection of divmodL
1451 RegMask Matcher::modL_proj_mask() {
1452 ShouldNotReachHere();
1453 return RegMask();
1454 }
1456 %}
1458 //----------ENCODING BLOCK-----------------------------------------------------
1459 // This block specifies the encoding classes used by the compiler to output
1460 // byte streams. Encoding classes generate functions which are called by
1461 // Machine Instruction Nodes in order to generate the bit encoding of the
1462 // instruction. Operands specify their base encoding interface with the
1463 // interface keyword. There are currently supported four interfaces,
1464 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1465 // operand to generate a function which returns its register number when
1466 // queried. CONST_INTER causes an operand to generate a function which
1467 // returns the value of the constant when queried. MEMORY_INTER causes an
1468 // operand to generate four functions which return the Base Register, the
1469 // Index Register, the Scale Value, and the Offset Value of the operand when
1470 // queried. COND_INTER causes an operand to generate six functions which
1471 // return the encoding code (ie - encoding bits for the instruction)
1472 // associated with each basic boolean condition for a conditional instruction.
1473 // Instructions specify two basic values for encoding. They use the
1474 // ins_encode keyword to specify their encoding class (which must be one of
1475 // the class names specified in the encoding block), and they use the
1476 // opcode keyword to specify, in order, their primary, secondary, and
1477 // tertiary opcode. Only the opcode sections which a particular instruction
1478 // needs for encoding need to be specified.
1479 encode %{
1480 // Build emit functions for each basic byte or larger field in the intel
1481 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1482 // code in the enc_class source block. Emit functions will live in the
1483 // main source block for now. In future, we can generalize this by
1484 // adding a syntax that specifies the sizes of fields in an order,
1485 // so that the adlc can build the emit functions automagically
1487 // Emit primary opcode
1488 enc_class OpcP %{
1489 emit_opcode(cbuf, $primary);
1490 %}
1492 // Emit secondary opcode
1493 enc_class OpcS %{
1494 emit_opcode(cbuf, $secondary);
1495 %}
1497 // Emit opcode directly
1498 enc_class Opcode(immI d8) %{
1499 emit_opcode(cbuf, $d8$$constant);
1500 %}
1502 enc_class SizePrefix %{
1503 emit_opcode(cbuf,0x66);
1504 %}
1506 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1507 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1508 %}
1510 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1511 emit_opcode(cbuf,$opcode$$constant);
1512 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1513 %}
1515 enc_class mov_r32_imm0( eRegI dst ) %{
1516 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1517 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1518 %}
1520 enc_class cdq_enc %{
1521 // Full implementation of Java idiv and irem; checks for
1522 // special case as described in JVM spec., p.243 & p.271.
1523 //
1524 // normal case special case
1525 //
1526 // input : rax,: dividend min_int
1527 // reg: divisor -1
1528 //
1529 // output: rax,: quotient (= rax, idiv reg) min_int
1530 // rdx: remainder (= rax, irem reg) 0
1531 //
1532 // Code sequnce:
1533 //
1534 // 81 F8 00 00 00 80 cmp rax,80000000h
1535 // 0F 85 0B 00 00 00 jne normal_case
1536 // 33 D2 xor rdx,edx
1537 // 83 F9 FF cmp rcx,0FFh
1538 // 0F 84 03 00 00 00 je done
1539 // normal_case:
1540 // 99 cdq
1541 // F7 F9 idiv rax,ecx
1542 // done:
1543 //
1544 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1545 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1546 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1547 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1548 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1549 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1550 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1551 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1552 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1553 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1554 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1555 // normal_case:
1556 emit_opcode(cbuf,0x99); // cdq
1557 // idiv (note: must be emitted by the user of this rule)
1558 // normal:
1559 %}
1561 // Dense encoding for older common ops
1562 enc_class Opc_plus(immI opcode, eRegI reg) %{
1563 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1564 %}
1567 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1568 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1569 // Check for 8-bit immediate, and set sign extend bit in opcode
1570 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1571 emit_opcode(cbuf, $primary | 0x02);
1572 }
1573 else { // If 32-bit immediate
1574 emit_opcode(cbuf, $primary);
1575 }
1576 %}
1578 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1579 // Emit primary opcode and set sign-extend bit
1580 // Check for 8-bit immediate, and set sign extend bit in opcode
1581 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1582 emit_opcode(cbuf, $primary | 0x02); }
1583 else { // If 32-bit immediate
1584 emit_opcode(cbuf, $primary);
1585 }
1586 // Emit r/m byte with secondary opcode, after primary opcode.
1587 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1588 %}
1590 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1591 // Check for 8-bit immediate, and set sign extend bit in opcode
1592 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1593 $$$emit8$imm$$constant;
1594 }
1595 else { // If 32-bit immediate
1596 // Output immediate
1597 $$$emit32$imm$$constant;
1598 }
1599 %}
1601 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1602 // Emit primary opcode and set sign-extend bit
1603 // Check for 8-bit immediate, and set sign extend bit in opcode
1604 int con = (int)$imm$$constant; // Throw away top bits
1605 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1606 // Emit r/m byte with secondary opcode, after primary opcode.
1607 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1608 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1609 else emit_d32(cbuf,con);
1610 %}
1612 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1613 // Emit primary opcode and set sign-extend bit
1614 // Check for 8-bit immediate, and set sign extend bit in opcode
1615 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1616 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1617 // Emit r/m byte with tertiary opcode, after primary opcode.
1618 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1619 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1620 else emit_d32(cbuf,con);
1621 %}
1623 enc_class Lbl (label labl) %{ // JMP, CALL
1624 Label *l = $labl$$label;
1625 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1626 %}
1628 enc_class LblShort (label labl) %{ // JMP, CALL
1629 Label *l = $labl$$label;
1630 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1631 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1632 emit_d8(cbuf, disp);
1633 %}
1635 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1636 emit_cc(cbuf, $secondary, $dst$$reg );
1637 %}
1639 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1640 int destlo = $dst$$reg;
1641 int desthi = HIGH_FROM_LOW(destlo);
1642 // bswap lo
1643 emit_opcode(cbuf, 0x0F);
1644 emit_cc(cbuf, 0xC8, destlo);
1645 // bswap hi
1646 emit_opcode(cbuf, 0x0F);
1647 emit_cc(cbuf, 0xC8, desthi);
1648 // xchg lo and hi
1649 emit_opcode(cbuf, 0x87);
1650 emit_rm(cbuf, 0x3, destlo, desthi);
1651 %}
1653 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1654 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1655 %}
1657 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1658 Label *l = $labl$$label;
1659 $$$emit8$primary;
1660 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1661 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1662 %}
1664 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1665 Label *l = $labl$$label;
1666 emit_cc(cbuf, $primary, $cop$$cmpcode);
1667 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1668 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1669 emit_d8(cbuf, disp);
1670 %}
1672 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1673 $$$emit8$primary;
1674 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1675 %}
1677 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1678 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1679 emit_d8(cbuf, op >> 8 );
1680 emit_d8(cbuf, op & 255);
1681 %}
1683 // emulate a CMOV with a conditional branch around a MOV
1684 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1685 // Invert sense of branch from sense of CMOV
1686 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1687 emit_d8( cbuf, $brOffs$$constant );
1688 %}
1690 enc_class enc_PartialSubtypeCheck( ) %{
1691 Register Redi = as_Register(EDI_enc); // result register
1692 Register Reax = as_Register(EAX_enc); // super class
1693 Register Recx = as_Register(ECX_enc); // killed
1694 Register Resi = as_Register(ESI_enc); // sub class
1695 Label miss;
1697 MacroAssembler _masm(&cbuf);
1698 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1699 NULL, &miss,
1700 /*set_cond_codes:*/ true);
1701 if ($primary) {
1702 __ xorptr(Redi, Redi);
1703 }
1704 __ bind(miss);
1705 %}
1707 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1708 MacroAssembler masm(&cbuf);
1709 int start = masm.offset();
1710 if (UseSSE >= 2) {
1711 if (VerifyFPU) {
1712 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1713 }
1714 } else {
1715 // External c_calling_convention expects the FPU stack to be 'clean'.
1716 // Compiled code leaves it dirty. Do cleanup now.
1717 masm.empty_FPU_stack();
1718 }
1719 if (sizeof_FFree_Float_Stack_All == -1) {
1720 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1721 } else {
1722 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1723 }
1724 %}
1726 enc_class Verify_FPU_For_Leaf %{
1727 if( VerifyFPU ) {
1728 MacroAssembler masm(&cbuf);
1729 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1730 }
1731 %}
1733 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1734 // This is the instruction starting address for relocation info.
1735 cbuf.set_inst_mark();
1736 $$$emit8$primary;
1737 // CALL directly to the runtime
1738 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1739 runtime_call_Relocation::spec(), RELOC_IMM32 );
1741 if (UseSSE >= 2) {
1742 MacroAssembler _masm(&cbuf);
1743 BasicType rt = tf()->return_type();
1745 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1746 // A C runtime call where the return value is unused. In SSE2+
1747 // mode the result needs to be removed from the FPU stack. It's
1748 // likely that this function call could be removed by the
1749 // optimizer if the C function is a pure function.
1750 __ ffree(0);
1751 } else if (rt == T_FLOAT) {
1752 __ lea(rsp, Address(rsp, -4));
1753 __ fstp_s(Address(rsp, 0));
1754 __ movflt(xmm0, Address(rsp, 0));
1755 __ lea(rsp, Address(rsp, 4));
1756 } else if (rt == T_DOUBLE) {
1757 __ lea(rsp, Address(rsp, -8));
1758 __ fstp_d(Address(rsp, 0));
1759 __ movdbl(xmm0, Address(rsp, 0));
1760 __ lea(rsp, Address(rsp, 8));
1761 }
1762 }
1763 %}
1766 enc_class pre_call_FPU %{
1767 // If method sets FPU control word restore it here
1768 if( Compile::current()->in_24_bit_fp_mode() ) {
1769 MacroAssembler masm(&cbuf);
1770 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1771 }
1772 %}
1774 enc_class post_call_FPU %{
1775 // If method sets FPU control word do it here also
1776 if( Compile::current()->in_24_bit_fp_mode() ) {
1777 MacroAssembler masm(&cbuf);
1778 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1779 }
1780 %}
1782 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1783 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1784 // who we intended to call.
1785 cbuf.set_inst_mark();
1786 $$$emit8$primary;
1787 if ( !_method ) {
1788 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1789 runtime_call_Relocation::spec(), RELOC_IMM32 );
1790 } else if(_optimized_virtual) {
1791 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1792 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1793 } else {
1794 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1795 static_call_Relocation::spec(), RELOC_IMM32 );
1796 }
1797 if( _method ) { // Emit stub for static call
1798 emit_java_to_interp(cbuf);
1799 }
1800 %}
1802 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1803 // !!!!!
1804 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1805 // emit_call_dynamic_prologue( cbuf );
1806 cbuf.set_inst_mark();
1807 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1808 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1809 address virtual_call_oop_addr = cbuf.inst_mark();
1810 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1811 // who we intended to call.
1812 cbuf.set_inst_mark();
1813 $$$emit8$primary;
1814 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1815 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1816 %}
1818 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1819 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1820 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1822 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1823 cbuf.set_inst_mark();
1824 $$$emit8$primary;
1825 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1826 emit_d8(cbuf, disp); // Displacement
1828 %}
1830 enc_class Xor_Reg (eRegI dst) %{
1831 emit_opcode(cbuf, 0x33);
1832 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1833 %}
1835 // Following encoding is no longer used, but may be restored if calling
1836 // convention changes significantly.
1837 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1838 //
1839 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1840 // // int ic_reg = Matcher::inline_cache_reg();
1841 // // int ic_encode = Matcher::_regEncode[ic_reg];
1842 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1843 // // int imo_encode = Matcher::_regEncode[imo_reg];
1844 //
1845 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1846 // // // so we load it immediately before the call
1847 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1848 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1849 //
1850 // // xor rbp,ebp
1851 // emit_opcode(cbuf, 0x33);
1852 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1853 //
1854 // // CALL to interpreter.
1855 // cbuf.set_inst_mark();
1856 // $$$emit8$primary;
1857 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1858 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1859 // %}
1861 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1862 $$$emit8$primary;
1863 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1864 $$$emit8$shift$$constant;
1865 %}
1867 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1868 // Load immediate does not have a zero or sign extended version
1869 // for 8-bit immediates
1870 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1871 $$$emit32$src$$constant;
1872 %}
1874 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, $primary + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1881 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 int dst_enc = $dst$$reg;
1885 int src_con = $src$$constant & 0x0FFFFFFFFL;
1886 if (src_con == 0) {
1887 // xor dst, dst
1888 emit_opcode(cbuf, 0x33);
1889 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1890 } else {
1891 emit_opcode(cbuf, $primary + dst_enc);
1892 emit_d32(cbuf, src_con);
1893 }
1894 %}
1896 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1897 // Load immediate does not have a zero or sign extended version
1898 // for 8-bit immediates
1899 int dst_enc = $dst$$reg + 2;
1900 int src_con = ((julong)($src$$constant)) >> 32;
1901 if (src_con == 0) {
1902 // xor dst, dst
1903 emit_opcode(cbuf, 0x33);
1904 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1905 } else {
1906 emit_opcode(cbuf, $primary + dst_enc);
1907 emit_d32(cbuf, src_con);
1908 }
1909 %}
1912 enc_class LdImmD (immD src) %{ // Load Immediate
1913 if( is_positive_zero_double($src$$constant)) {
1914 // FLDZ
1915 emit_opcode(cbuf,0xD9);
1916 emit_opcode(cbuf,0xEE);
1917 } else if( is_positive_one_double($src$$constant)) {
1918 // FLD1
1919 emit_opcode(cbuf,0xD9);
1920 emit_opcode(cbuf,0xE8);
1921 } else {
1922 emit_opcode(cbuf,0xDD);
1923 emit_rm(cbuf, 0x0, 0x0, 0x5);
1924 emit_double_constant(cbuf, $src$$constant);
1925 }
1926 %}
1929 enc_class LdImmF (immF src) %{ // Load Immediate
1930 if( is_positive_zero_float($src$$constant)) {
1931 emit_opcode(cbuf,0xD9);
1932 emit_opcode(cbuf,0xEE);
1933 } else if( is_positive_one_float($src$$constant)) {
1934 emit_opcode(cbuf,0xD9);
1935 emit_opcode(cbuf,0xE8);
1936 } else {
1937 $$$emit8$primary;
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 // First load to TOS, then move to dst
1941 emit_rm(cbuf, 0x0, 0x0, 0x5);
1942 emit_float_constant(cbuf, $src$$constant);
1943 }
1944 %}
1946 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1947 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1948 emit_float_constant(cbuf, $con$$constant);
1949 %}
1951 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1952 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1953 emit_double_constant(cbuf, $con$$constant);
1954 %}
1956 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1957 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1958 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1959 emit_opcode(cbuf, 0x0F);
1960 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1961 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1962 emit_double_constant(cbuf, $con$$constant);
1963 %}
1965 enc_class Opc_MemImm_F(immF src) %{
1966 cbuf.set_inst_mark();
1967 $$$emit8$primary;
1968 emit_rm(cbuf, 0x0, $secondary, 0x5);
1969 emit_float_constant(cbuf, $src$$constant);
1970 %}
1973 enc_class MovI2X_reg(regX dst, eRegI src) %{
1974 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1975 emit_opcode(cbuf, 0x0F );
1976 emit_opcode(cbuf, 0x6E );
1977 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1978 %}
1980 enc_class MovX2I_reg(eRegI dst, regX src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x7E );
1984 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1985 %}
1987 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1988 { // MOVD $dst,$src.lo
1989 emit_opcode(cbuf,0x66);
1990 emit_opcode(cbuf,0x0F);
1991 emit_opcode(cbuf,0x6E);
1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1993 }
1994 { // MOVD $tmp,$src.hi
1995 emit_opcode(cbuf,0x66);
1996 emit_opcode(cbuf,0x0F);
1997 emit_opcode(cbuf,0x6E);
1998 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
1999 }
2000 { // PUNPCKLDQ $dst,$tmp
2001 emit_opcode(cbuf,0x66);
2002 emit_opcode(cbuf,0x0F);
2003 emit_opcode(cbuf,0x62);
2004 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2005 }
2006 %}
2008 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2009 { // MOVD $dst.lo,$src
2010 emit_opcode(cbuf,0x66);
2011 emit_opcode(cbuf,0x0F);
2012 emit_opcode(cbuf,0x7E);
2013 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2014 }
2015 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2016 emit_opcode(cbuf,0xF2);
2017 emit_opcode(cbuf,0x0F);
2018 emit_opcode(cbuf,0x70);
2019 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2020 emit_d8(cbuf, 0x4E);
2021 }
2022 { // MOVD $dst.hi,$tmp
2023 emit_opcode(cbuf,0x66);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x7E);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2027 }
2028 %}
2031 // Encode a reg-reg copy. If it is useless, then empty encoding.
2032 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2033 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2034 %}
2036 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2037 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2038 %}
2040 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2041 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2042 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2043 %}
2045 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2046 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2047 %}
2049 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2050 $$$emit8$primary;
2051 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2052 %}
2054 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2055 $$$emit8$secondary;
2056 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2057 %}
2059 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2060 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2061 %}
2063 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2064 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2065 %}
2067 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2068 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2069 %}
2071 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2072 // Output immediate
2073 $$$emit32$src$$constant;
2074 %}
2076 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2077 // Output Float immediate bits
2078 jfloat jf = $src$$constant;
2079 int jf_as_bits = jint_cast( jf );
2080 emit_d32(cbuf, jf_as_bits);
2081 %}
2083 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2090 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2091 // Output immediate
2092 $$$emit16$src$$constant;
2093 %}
2095 enc_class Con_d32(immI src) %{
2096 emit_d32(cbuf,$src$$constant);
2097 %}
2099 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2100 // Output immediate memory reference
2101 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2102 emit_d32(cbuf, 0x00);
2103 %}
2105 enc_class lock_prefix( ) %{
2106 if( os::is_MP() )
2107 emit_opcode(cbuf,0xF0); // [Lock]
2108 %}
2110 // Cmp-xchg long value.
2111 // Note: we need to swap rbx, and rcx before and after the
2112 // cmpxchg8 instruction because the instruction uses
2113 // rcx as the high order word of the new value to store but
2114 // our register encoding uses rbx,.
2115 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2117 // XCHG rbx,ecx
2118 emit_opcode(cbuf,0x87);
2119 emit_opcode(cbuf,0xD9);
2120 // [Lock]
2121 if( os::is_MP() )
2122 emit_opcode(cbuf,0xF0);
2123 // CMPXCHG8 [Eptr]
2124 emit_opcode(cbuf,0x0F);
2125 emit_opcode(cbuf,0xC7);
2126 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2127 // XCHG rbx,ecx
2128 emit_opcode(cbuf,0x87);
2129 emit_opcode(cbuf,0xD9);
2130 %}
2132 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2133 // [Lock]
2134 if( os::is_MP() )
2135 emit_opcode(cbuf,0xF0);
2137 // CMPXCHG [Eptr]
2138 emit_opcode(cbuf,0x0F);
2139 emit_opcode(cbuf,0xB1);
2140 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2141 %}
2143 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2144 int res_encoding = $res$$reg;
2146 // MOV res,0
2147 emit_opcode( cbuf, 0xB8 + res_encoding);
2148 emit_d32( cbuf, 0 );
2149 // JNE,s fail
2150 emit_opcode(cbuf,0x75);
2151 emit_d8(cbuf, 5 );
2152 // MOV res,1
2153 emit_opcode( cbuf, 0xB8 + res_encoding);
2154 emit_d32( cbuf, 1 );
2155 // fail:
2156 %}
2158 enc_class set_instruction_start( ) %{
2159 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2160 %}
2162 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2163 int reg_encoding = $ereg$$reg;
2164 int base = $mem$$base;
2165 int index = $mem$$index;
2166 int scale = $mem$$scale;
2167 int displace = $mem$$disp;
2168 bool disp_is_oop = $mem->disp_is_oop();
2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2170 %}
2172 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2173 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2174 int base = $mem$$base;
2175 int index = $mem$$index;
2176 int scale = $mem$$scale;
2177 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2178 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2179 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2180 %}
2182 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2183 int r1, r2;
2184 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2185 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2186 emit_opcode(cbuf,0x0F);
2187 emit_opcode(cbuf,$tertiary);
2188 emit_rm(cbuf, 0x3, r1, r2);
2189 emit_d8(cbuf,$cnt$$constant);
2190 emit_d8(cbuf,$primary);
2191 emit_rm(cbuf, 0x3, $secondary, r1);
2192 emit_d8(cbuf,$cnt$$constant);
2193 %}
2195 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2196 emit_opcode( cbuf, 0x8B ); // Move
2197 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2198 emit_d8(cbuf,$primary);
2199 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2200 emit_d8(cbuf,$cnt$$constant-32);
2201 emit_d8(cbuf,$primary);
2202 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2203 emit_d8(cbuf,31);
2204 %}
2206 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2207 int r1, r2;
2208 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2209 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2211 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2212 emit_rm(cbuf, 0x3, r1, r2);
2213 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2214 emit_opcode(cbuf,$primary);
2215 emit_rm(cbuf, 0x3, $secondary, r1);
2216 emit_d8(cbuf,$cnt$$constant-32);
2217 }
2218 emit_opcode(cbuf,0x33); // XOR r2,r2
2219 emit_rm(cbuf, 0x3, r2, r2);
2220 %}
2222 // Clone of RegMem but accepts an extra parameter to access each
2223 // half of a double in memory; it never needs relocation info.
2224 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2225 emit_opcode(cbuf,$opcode$$constant);
2226 int reg_encoding = $rm_reg$$reg;
2227 int base = $mem$$base;
2228 int index = $mem$$index;
2229 int scale = $mem$$scale;
2230 int displace = $mem$$disp + $disp_for_half$$constant;
2231 bool disp_is_oop = false;
2232 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2233 %}
2235 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2236 //
2237 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2238 // and it never needs relocation information.
2239 // Frequently used to move data between FPU's Stack Top and memory.
2240 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2241 int rm_byte_opcode = $rm_opcode$$constant;
2242 int base = $mem$$base;
2243 int index = $mem$$index;
2244 int scale = $mem$$scale;
2245 int displace = $mem$$disp;
2246 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2247 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2248 %}
2250 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2251 int rm_byte_opcode = $rm_opcode$$constant;
2252 int base = $mem$$base;
2253 int index = $mem$$index;
2254 int scale = $mem$$scale;
2255 int displace = $mem$$disp;
2256 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2257 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2258 %}
2260 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2261 int reg_encoding = $dst$$reg;
2262 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2263 int index = 0x04; // 0x04 indicates no index
2264 int scale = 0x00; // 0x00 indicates no scale
2265 int displace = $src1$$constant; // 0x00 indicates no displacement
2266 bool disp_is_oop = false;
2267 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2268 %}
2270 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2271 // Compare dst,src
2272 emit_opcode(cbuf,0x3B);
2273 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2274 // jmp dst < src around move
2275 emit_opcode(cbuf,0x7C);
2276 emit_d8(cbuf,2);
2277 // move dst,src
2278 emit_opcode(cbuf,0x8B);
2279 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2280 %}
2282 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2283 // Compare dst,src
2284 emit_opcode(cbuf,0x3B);
2285 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2286 // jmp dst > src around move
2287 emit_opcode(cbuf,0x7F);
2288 emit_d8(cbuf,2);
2289 // move dst,src
2290 emit_opcode(cbuf,0x8B);
2291 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2292 %}
2294 enc_class enc_FP_store(memory mem, regD src) %{
2295 // If src is FPR1, we can just FST to store it.
2296 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2297 int reg_encoding = 0x2; // Just store
2298 int base = $mem$$base;
2299 int index = $mem$$index;
2300 int scale = $mem$$scale;
2301 int displace = $mem$$disp;
2302 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2303 if( $src$$reg != FPR1L_enc ) {
2304 reg_encoding = 0x3; // Store & pop
2305 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2306 emit_d8( cbuf, 0xC0-1+$src$$reg );
2307 }
2308 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2309 emit_opcode(cbuf,$primary);
2310 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2311 %}
2313 enc_class neg_reg(eRegI dst) %{
2314 // NEG $dst
2315 emit_opcode(cbuf,0xF7);
2316 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2317 %}
2319 enc_class setLT_reg(eCXRegI dst) %{
2320 // SETLT $dst
2321 emit_opcode(cbuf,0x0F);
2322 emit_opcode(cbuf,0x9C);
2323 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2324 %}
2326 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2327 int tmpReg = $tmp$$reg;
2329 // SUB $p,$q
2330 emit_opcode(cbuf,0x2B);
2331 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2332 // SBB $tmp,$tmp
2333 emit_opcode(cbuf,0x1B);
2334 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2335 // AND $tmp,$y
2336 emit_opcode(cbuf,0x23);
2337 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2338 // ADD $p,$tmp
2339 emit_opcode(cbuf,0x03);
2340 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2341 %}
2343 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2344 int tmpReg = $tmp$$reg;
2346 // SUB $p,$q
2347 emit_opcode(cbuf,0x2B);
2348 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2349 // SBB $tmp,$tmp
2350 emit_opcode(cbuf,0x1B);
2351 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2352 // AND $tmp,$y
2353 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2354 emit_opcode(cbuf,0x23);
2355 int reg_encoding = tmpReg;
2356 int base = $mem$$base;
2357 int index = $mem$$index;
2358 int scale = $mem$$scale;
2359 int displace = $mem$$disp;
2360 bool disp_is_oop = $mem->disp_is_oop();
2361 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2362 // ADD $p,$tmp
2363 emit_opcode(cbuf,0x03);
2364 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2365 %}
2367 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2368 // TEST shift,32
2369 emit_opcode(cbuf,0xF7);
2370 emit_rm(cbuf, 0x3, 0, ECX_enc);
2371 emit_d32(cbuf,0x20);
2372 // JEQ,s small
2373 emit_opcode(cbuf, 0x74);
2374 emit_d8(cbuf, 0x04);
2375 // MOV $dst.hi,$dst.lo
2376 emit_opcode( cbuf, 0x8B );
2377 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2378 // CLR $dst.lo
2379 emit_opcode(cbuf, 0x33);
2380 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2381 // small:
2382 // SHLD $dst.hi,$dst.lo,$shift
2383 emit_opcode(cbuf,0x0F);
2384 emit_opcode(cbuf,0xA5);
2385 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2386 // SHL $dst.lo,$shift"
2387 emit_opcode(cbuf,0xD3);
2388 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2389 %}
2391 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2392 // TEST shift,32
2393 emit_opcode(cbuf,0xF7);
2394 emit_rm(cbuf, 0x3, 0, ECX_enc);
2395 emit_d32(cbuf,0x20);
2396 // JEQ,s small
2397 emit_opcode(cbuf, 0x74);
2398 emit_d8(cbuf, 0x04);
2399 // MOV $dst.lo,$dst.hi
2400 emit_opcode( cbuf, 0x8B );
2401 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2402 // CLR $dst.hi
2403 emit_opcode(cbuf, 0x33);
2404 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2405 // small:
2406 // SHRD $dst.lo,$dst.hi,$shift
2407 emit_opcode(cbuf,0x0F);
2408 emit_opcode(cbuf,0xAD);
2409 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2410 // SHR $dst.hi,$shift"
2411 emit_opcode(cbuf,0xD3);
2412 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2413 %}
2415 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2416 // TEST shift,32
2417 emit_opcode(cbuf,0xF7);
2418 emit_rm(cbuf, 0x3, 0, ECX_enc);
2419 emit_d32(cbuf,0x20);
2420 // JEQ,s small
2421 emit_opcode(cbuf, 0x74);
2422 emit_d8(cbuf, 0x05);
2423 // MOV $dst.lo,$dst.hi
2424 emit_opcode( cbuf, 0x8B );
2425 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2426 // SAR $dst.hi,31
2427 emit_opcode(cbuf, 0xC1);
2428 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2429 emit_d8(cbuf, 0x1F );
2430 // small:
2431 // SHRD $dst.lo,$dst.hi,$shift
2432 emit_opcode(cbuf,0x0F);
2433 emit_opcode(cbuf,0xAD);
2434 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2435 // SAR $dst.hi,$shift"
2436 emit_opcode(cbuf,0xD3);
2437 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2438 %}
2441 // ----------------- Encodings for floating point unit -----------------
2442 // May leave result in FPU-TOS or FPU reg depending on opcodes
2443 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2444 $$$emit8$primary;
2445 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2446 %}
2448 // Pop argument in FPR0 with FSTP ST(0)
2449 enc_class PopFPU() %{
2450 emit_opcode( cbuf, 0xDD );
2451 emit_d8( cbuf, 0xD8 );
2452 %}
2454 // !!!!! equivalent to Pop_Reg_F
2455 enc_class Pop_Reg_D( regD dst ) %{
2456 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2457 emit_d8( cbuf, 0xD8+$dst$$reg );
2458 %}
2460 enc_class Push_Reg_D( regD dst ) %{
2461 emit_opcode( cbuf, 0xD9 );
2462 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2463 %}
2465 enc_class strictfp_bias1( regD dst ) %{
2466 emit_opcode( cbuf, 0xDB ); // FLD m80real
2467 emit_opcode( cbuf, 0x2D );
2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2470 emit_opcode( cbuf, 0xC8+$dst$$reg );
2471 %}
2473 enc_class strictfp_bias2( regD dst ) %{
2474 emit_opcode( cbuf, 0xDB ); // FLD m80real
2475 emit_opcode( cbuf, 0x2D );
2476 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2477 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2478 emit_opcode( cbuf, 0xC8+$dst$$reg );
2479 %}
2481 // Special case for moving an integer register to a stack slot.
2482 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2483 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2484 %}
2486 // Special case for moving a register to a stack slot.
2487 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2488 // Opcode already emitted
2489 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2490 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2491 emit_d32(cbuf, $dst$$disp); // Displacement
2492 %}
2494 // Push the integer in stackSlot 'src' onto FP-stack
2495 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2496 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2497 %}
2499 // Push the float in stackSlot 'src' onto FP-stack
2500 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2501 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2502 %}
2504 // Push the double in stackSlot 'src' onto FP-stack
2505 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2506 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2507 %}
2509 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2510 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2511 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2512 %}
2514 // Same as Pop_Mem_F except for opcode
2515 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2516 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2517 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2518 %}
2520 enc_class Pop_Reg_F( regF dst ) %{
2521 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2522 emit_d8( cbuf, 0xD8+$dst$$reg );
2523 %}
2525 enc_class Push_Reg_F( regF dst ) %{
2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2527 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2528 %}
2530 // Push FPU's float to a stack-slot, and pop FPU-stack
2531 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2532 int pop = 0x02;
2533 if ($src$$reg != FPR1L_enc) {
2534 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2535 emit_d8( cbuf, 0xC0-1+$src$$reg );
2536 pop = 0x03;
2537 }
2538 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2539 %}
2541 // Push FPU's double to a stack-slot, and pop FPU-stack
2542 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2543 int pop = 0x02;
2544 if ($src$$reg != FPR1L_enc) {
2545 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2546 emit_d8( cbuf, 0xC0-1+$src$$reg );
2547 pop = 0x03;
2548 }
2549 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2550 %}
2552 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2553 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2554 int pop = 0xD0 - 1; // -1 since we skip FLD
2555 if ($src$$reg != FPR1L_enc) {
2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2557 emit_d8( cbuf, 0xC0-1+$src$$reg );
2558 pop = 0xD8;
2559 }
2560 emit_opcode( cbuf, 0xDD );
2561 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2562 %}
2565 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2566 MacroAssembler masm(&cbuf);
2567 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2568 masm.fmul( $src2$$reg+0); // value at TOS
2569 masm.fadd( $src$$reg+0); // value at TOS
2570 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2571 %}
2574 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2575 // load dst in FPR0
2576 emit_opcode( cbuf, 0xD9 );
2577 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2578 if ($src$$reg != FPR1L_enc) {
2579 // fincstp
2580 emit_opcode (cbuf, 0xD9);
2581 emit_opcode (cbuf, 0xF7);
2582 // swap src with FPR1:
2583 // FXCH FPR1 with src
2584 emit_opcode(cbuf, 0xD9);
2585 emit_d8(cbuf, 0xC8-1+$src$$reg );
2586 // fdecstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF6);
2589 }
2590 %}
2592 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2593 // Allocate a word
2594 emit_opcode(cbuf,0x83); // SUB ESP,8
2595 emit_opcode(cbuf,0xEC);
2596 emit_d8(cbuf,0x08);
2598 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2599 emit_opcode (cbuf, 0x0F );
2600 emit_opcode (cbuf, 0x11 );
2601 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2603 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2604 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2606 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2607 emit_opcode (cbuf, 0x0F );
2608 emit_opcode (cbuf, 0x11 );
2609 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2611 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2612 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2614 %}
2616 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2617 // Allocate a word
2618 emit_opcode(cbuf,0x83); // SUB ESP,4
2619 emit_opcode(cbuf,0xEC);
2620 emit_d8(cbuf,0x04);
2622 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2623 emit_opcode (cbuf, 0x0F );
2624 emit_opcode (cbuf, 0x11 );
2625 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2627 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2628 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2630 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2631 emit_opcode (cbuf, 0x0F );
2632 emit_opcode (cbuf, 0x11 );
2633 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2635 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2636 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2638 %}
2640 enc_class Push_ResultXD(regXD dst) %{
2641 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2643 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2644 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2645 emit_opcode (cbuf, 0x0F );
2646 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2647 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2649 emit_opcode(cbuf,0x83); // ADD ESP,8
2650 emit_opcode(cbuf,0xC4);
2651 emit_d8(cbuf,0x08);
2652 %}
2654 enc_class Push_ResultX(regX dst, immI d8) %{
2655 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2657 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2658 emit_opcode (cbuf, 0x0F );
2659 emit_opcode (cbuf, 0x10 );
2660 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2662 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2663 emit_opcode(cbuf,0xC4);
2664 emit_d8(cbuf,$d8$$constant);
2665 %}
2667 enc_class Push_SrcXD(regXD src) %{
2668 // Allocate a word
2669 emit_opcode(cbuf,0x83); // SUB ESP,8
2670 emit_opcode(cbuf,0xEC);
2671 emit_d8(cbuf,0x08);
2673 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2674 emit_opcode (cbuf, 0x0F );
2675 emit_opcode (cbuf, 0x11 );
2676 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2678 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2679 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2680 %}
2682 enc_class push_stack_temp_qword() %{
2683 emit_opcode(cbuf,0x83); // SUB ESP,8
2684 emit_opcode(cbuf,0xEC);
2685 emit_d8 (cbuf,0x08);
2686 %}
2688 enc_class pop_stack_temp_qword() %{
2689 emit_opcode(cbuf,0x83); // ADD ESP,8
2690 emit_opcode(cbuf,0xC4);
2691 emit_d8 (cbuf,0x08);
2692 %}
2694 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2695 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2696 emit_opcode (cbuf, 0x0F );
2697 emit_opcode (cbuf, 0x11 );
2698 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2700 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2701 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2702 %}
2704 // Compute X^Y using Intel's fast hardware instructions, if possible.
2705 // Otherwise return a NaN.
2706 enc_class pow_exp_core_encoding %{
2707 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2708 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2710 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2711 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2712 emit_opcode(cbuf,0x1C);
2713 emit_d8(cbuf,0x24);
2714 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2716 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2717 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2718 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2719 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2720 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2721 emit_d32(cbuf,0xFFFFF800);
2722 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2723 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2724 emit_d32(cbuf,1023);
2725 emit_opcode(cbuf,0x8B); // mov rbx,eax
2726 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2727 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2728 emit_rm(cbuf,0x3,0x4,EAX_enc);
2729 emit_d8(cbuf,20);
2730 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2731 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2732 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2733 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2734 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2735 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2736 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2737 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2738 emit_d32(cbuf,0);
2739 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2740 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2741 %}
2743 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2744 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2746 enc_class Push_Result_Mod_D( regD src) %{
2747 if ($src$$reg != FPR1L_enc) {
2748 // fincstp
2749 emit_opcode (cbuf, 0xD9);
2750 emit_opcode (cbuf, 0xF7);
2751 // FXCH FPR1 with src
2752 emit_opcode(cbuf, 0xD9);
2753 emit_d8(cbuf, 0xC8-1+$src$$reg );
2754 // fdecstp
2755 emit_opcode (cbuf, 0xD9);
2756 emit_opcode (cbuf, 0xF6);
2757 }
2758 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2759 // // FSTP FPR$dst$$reg
2760 // emit_opcode( cbuf, 0xDD );
2761 // emit_d8( cbuf, 0xD8+$dst$$reg );
2762 %}
2764 enc_class fnstsw_sahf_skip_parity() %{
2765 // fnstsw ax
2766 emit_opcode( cbuf, 0xDF );
2767 emit_opcode( cbuf, 0xE0 );
2768 // sahf
2769 emit_opcode( cbuf, 0x9E );
2770 // jnp ::skip
2771 emit_opcode( cbuf, 0x7B );
2772 emit_opcode( cbuf, 0x05 );
2773 %}
2775 enc_class emitModD() %{
2776 // fprem must be iterative
2777 // :: loop
2778 // fprem
2779 emit_opcode( cbuf, 0xD9 );
2780 emit_opcode( cbuf, 0xF8 );
2781 // wait
2782 emit_opcode( cbuf, 0x9b );
2783 // fnstsw ax
2784 emit_opcode( cbuf, 0xDF );
2785 emit_opcode( cbuf, 0xE0 );
2786 // sahf
2787 emit_opcode( cbuf, 0x9E );
2788 // jp ::loop
2789 emit_opcode( cbuf, 0x0F );
2790 emit_opcode( cbuf, 0x8A );
2791 emit_opcode( cbuf, 0xF4 );
2792 emit_opcode( cbuf, 0xFF );
2793 emit_opcode( cbuf, 0xFF );
2794 emit_opcode( cbuf, 0xFF );
2795 %}
2797 enc_class fpu_flags() %{
2798 // fnstsw_ax
2799 emit_opcode( cbuf, 0xDF);
2800 emit_opcode( cbuf, 0xE0);
2801 // test ax,0x0400
2802 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2803 emit_opcode( cbuf, 0xA9 );
2804 emit_d16 ( cbuf, 0x0400 );
2805 // // // This sequence works, but stalls for 12-16 cycles on PPro
2806 // // test rax,0x0400
2807 // emit_opcode( cbuf, 0xA9 );
2808 // emit_d32 ( cbuf, 0x00000400 );
2809 //
2810 // jz exit (no unordered comparison)
2811 emit_opcode( cbuf, 0x74 );
2812 emit_d8 ( cbuf, 0x02 );
2813 // mov ah,1 - treat as LT case (set carry flag)
2814 emit_opcode( cbuf, 0xB4 );
2815 emit_d8 ( cbuf, 0x01 );
2816 // sahf
2817 emit_opcode( cbuf, 0x9E);
2818 %}
2820 enc_class cmpF_P6_fixup() %{
2821 // Fixup the integer flags in case comparison involved a NaN
2822 //
2823 // JNP exit (no unordered comparison, P-flag is set by NaN)
2824 emit_opcode( cbuf, 0x7B );
2825 emit_d8 ( cbuf, 0x03 );
2826 // MOV AH,1 - treat as LT case (set carry flag)
2827 emit_opcode( cbuf, 0xB4 );
2828 emit_d8 ( cbuf, 0x01 );
2829 // SAHF
2830 emit_opcode( cbuf, 0x9E);
2831 // NOP // target for branch to avoid branch to branch
2832 emit_opcode( cbuf, 0x90);
2833 %}
2835 // fnstsw_ax();
2836 // sahf();
2837 // movl(dst, nan_result);
2838 // jcc(Assembler::parity, exit);
2839 // movl(dst, less_result);
2840 // jcc(Assembler::below, exit);
2841 // movl(dst, equal_result);
2842 // jcc(Assembler::equal, exit);
2843 // movl(dst, greater_result);
2845 // less_result = 1;
2846 // greater_result = -1;
2847 // equal_result = 0;
2848 // nan_result = -1;
2850 enc_class CmpF_Result(eRegI dst) %{
2851 // fnstsw_ax();
2852 emit_opcode( cbuf, 0xDF);
2853 emit_opcode( cbuf, 0xE0);
2854 // sahf
2855 emit_opcode( cbuf, 0x9E);
2856 // movl(dst, nan_result);
2857 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2858 emit_d32( cbuf, -1 );
2859 // jcc(Assembler::parity, exit);
2860 emit_opcode( cbuf, 0x7A );
2861 emit_d8 ( cbuf, 0x13 );
2862 // movl(dst, less_result);
2863 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2864 emit_d32( cbuf, -1 );
2865 // jcc(Assembler::below, exit);
2866 emit_opcode( cbuf, 0x72 );
2867 emit_d8 ( cbuf, 0x0C );
2868 // movl(dst, equal_result);
2869 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2870 emit_d32( cbuf, 0 );
2871 // jcc(Assembler::equal, exit);
2872 emit_opcode( cbuf, 0x74 );
2873 emit_d8 ( cbuf, 0x05 );
2874 // movl(dst, greater_result);
2875 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2876 emit_d32( cbuf, 1 );
2877 %}
2880 // XMM version of CmpF_Result. Because the XMM compare
2881 // instructions set the EFLAGS directly. It becomes simpler than
2882 // the float version above.
2883 enc_class CmpX_Result(eRegI dst) %{
2884 MacroAssembler _masm(&cbuf);
2885 Label nan, inc, done;
2887 __ jccb(Assembler::parity, nan);
2888 __ jccb(Assembler::equal, done);
2889 __ jccb(Assembler::above, inc);
2890 __ bind(nan);
2891 __ decrement(as_Register($dst$$reg)); // NO L qqq
2892 __ jmpb(done);
2893 __ bind(inc);
2894 __ increment(as_Register($dst$$reg)); // NO L qqq
2895 __ bind(done);
2896 %}
2898 // Compare the longs and set flags
2899 // BROKEN! Do Not use as-is
2900 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2901 // CMP $src1.hi,$src2.hi
2902 emit_opcode( cbuf, 0x3B );
2903 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2904 // JNE,s done
2905 emit_opcode(cbuf,0x75);
2906 emit_d8(cbuf, 2 );
2907 // CMP $src1.lo,$src2.lo
2908 emit_opcode( cbuf, 0x3B );
2909 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2910 // done:
2911 %}
2913 enc_class convert_int_long( regL dst, eRegI src ) %{
2914 // mov $dst.lo,$src
2915 int dst_encoding = $dst$$reg;
2916 int src_encoding = $src$$reg;
2917 encode_Copy( cbuf, dst_encoding , src_encoding );
2918 // mov $dst.hi,$src
2919 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2920 // sar $dst.hi,31
2921 emit_opcode( cbuf, 0xC1 );
2922 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2923 emit_d8(cbuf, 0x1F );
2924 %}
2926 enc_class convert_long_double( eRegL src ) %{
2927 // push $src.hi
2928 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2929 // push $src.lo
2930 emit_opcode(cbuf, 0x50+$src$$reg );
2931 // fild 64-bits at [SP]
2932 emit_opcode(cbuf,0xdf);
2933 emit_d8(cbuf, 0x6C);
2934 emit_d8(cbuf, 0x24);
2935 emit_d8(cbuf, 0x00);
2936 // pop stack
2937 emit_opcode(cbuf, 0x83); // add SP, #8
2938 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2939 emit_d8(cbuf, 0x8);
2940 %}
2942 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2943 // IMUL EDX:EAX,$src1
2944 emit_opcode( cbuf, 0xF7 );
2945 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2946 // SAR EDX,$cnt-32
2947 int shift_count = ((int)$cnt$$constant) - 32;
2948 if (shift_count > 0) {
2949 emit_opcode(cbuf, 0xC1);
2950 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2951 emit_d8(cbuf, shift_count);
2952 }
2953 %}
2955 // this version doesn't have add sp, 8
2956 enc_class convert_long_double2( eRegL src ) %{
2957 // push $src.hi
2958 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2959 // push $src.lo
2960 emit_opcode(cbuf, 0x50+$src$$reg );
2961 // fild 64-bits at [SP]
2962 emit_opcode(cbuf,0xdf);
2963 emit_d8(cbuf, 0x6C);
2964 emit_d8(cbuf, 0x24);
2965 emit_d8(cbuf, 0x00);
2966 %}
2968 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2969 // Basic idea: long = (long)int * (long)int
2970 // IMUL EDX:EAX, src
2971 emit_opcode( cbuf, 0xF7 );
2972 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2973 %}
2975 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2977 // MUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2980 %}
2982 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2983 // Basic idea: lo(result) = lo(x_lo * y_lo)
2984 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2985 // MOV $tmp,$src.lo
2986 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2987 // IMUL $tmp,EDX
2988 emit_opcode( cbuf, 0x0F );
2989 emit_opcode( cbuf, 0xAF );
2990 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2991 // MOV EDX,$src.hi
2992 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2993 // IMUL EDX,EAX
2994 emit_opcode( cbuf, 0x0F );
2995 emit_opcode( cbuf, 0xAF );
2996 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2997 // ADD $tmp,EDX
2998 emit_opcode( cbuf, 0x03 );
2999 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3000 // MUL EDX:EAX,$src.lo
3001 emit_opcode( cbuf, 0xF7 );
3002 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3003 // ADD EDX,ESI
3004 emit_opcode( cbuf, 0x03 );
3005 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3006 %}
3008 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3009 // Basic idea: lo(result) = lo(src * y_lo)
3010 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3011 // IMUL $tmp,EDX,$src
3012 emit_opcode( cbuf, 0x6B );
3013 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3014 emit_d8( cbuf, (int)$src$$constant );
3015 // MOV EDX,$src
3016 emit_opcode(cbuf, 0xB8 + EDX_enc);
3017 emit_d32( cbuf, (int)$src$$constant );
3018 // MUL EDX:EAX,EDX
3019 emit_opcode( cbuf, 0xF7 );
3020 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3021 // ADD EDX,ESI
3022 emit_opcode( cbuf, 0x03 );
3023 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3024 %}
3026 enc_class long_div( eRegL src1, eRegL src2 ) %{
3027 // PUSH src1.hi
3028 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3029 // PUSH src1.lo
3030 emit_opcode(cbuf, 0x50+$src1$$reg );
3031 // PUSH src2.hi
3032 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3033 // PUSH src2.lo
3034 emit_opcode(cbuf, 0x50+$src2$$reg );
3035 // CALL directly to the runtime
3036 cbuf.set_inst_mark();
3037 emit_opcode(cbuf,0xE8); // Call into runtime
3038 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3039 // Restore stack
3040 emit_opcode(cbuf, 0x83); // add SP, #framesize
3041 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3042 emit_d8(cbuf, 4*4);
3043 %}
3045 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3046 // PUSH src1.hi
3047 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3048 // PUSH src1.lo
3049 emit_opcode(cbuf, 0x50+$src1$$reg );
3050 // PUSH src2.hi
3051 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3052 // PUSH src2.lo
3053 emit_opcode(cbuf, 0x50+$src2$$reg );
3054 // CALL directly to the runtime
3055 cbuf.set_inst_mark();
3056 emit_opcode(cbuf,0xE8); // Call into runtime
3057 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3058 // Restore stack
3059 emit_opcode(cbuf, 0x83); // add SP, #framesize
3060 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3061 emit_d8(cbuf, 4*4);
3062 %}
3064 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3065 // MOV $tmp,$src.lo
3066 emit_opcode(cbuf, 0x8B);
3067 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3068 // OR $tmp,$src.hi
3069 emit_opcode(cbuf, 0x0B);
3070 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3071 %}
3073 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3074 // CMP $src1.lo,$src2.lo
3075 emit_opcode( cbuf, 0x3B );
3076 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3077 // JNE,s skip
3078 emit_cc(cbuf, 0x70, 0x5);
3079 emit_d8(cbuf,2);
3080 // CMP $src1.hi,$src2.hi
3081 emit_opcode( cbuf, 0x3B );
3082 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3083 %}
3085 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3086 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3087 emit_opcode( cbuf, 0x3B );
3088 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3089 // MOV $tmp,$src1.hi
3090 emit_opcode( cbuf, 0x8B );
3091 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3092 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3093 emit_opcode( cbuf, 0x1B );
3094 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3095 %}
3097 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3098 // XOR $tmp,$tmp
3099 emit_opcode(cbuf,0x33); // XOR
3100 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3101 // CMP $tmp,$src.lo
3102 emit_opcode( cbuf, 0x3B );
3103 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3104 // SBB $tmp,$src.hi
3105 emit_opcode( cbuf, 0x1B );
3106 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3107 %}
3109 // Sniff, sniff... smells like Gnu Superoptimizer
3110 enc_class neg_long( eRegL dst ) %{
3111 emit_opcode(cbuf,0xF7); // NEG hi
3112 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3113 emit_opcode(cbuf,0xF7); // NEG lo
3114 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3115 emit_opcode(cbuf,0x83); // SBB hi,0
3116 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3117 emit_d8 (cbuf,0 );
3118 %}
3120 enc_class movq_ld(regXD dst, memory mem) %{
3121 MacroAssembler _masm(&cbuf);
3122 __ movq($dst$$XMMRegister, $mem$$Address);
3123 %}
3125 enc_class movq_st(memory mem, regXD src) %{
3126 MacroAssembler _masm(&cbuf);
3127 __ movq($mem$$Address, $src$$XMMRegister);
3128 %}
3130 enc_class pshufd_8x8(regX dst, regX src) %{
3131 MacroAssembler _masm(&cbuf);
3133 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3134 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3135 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3136 %}
3138 enc_class pshufd_4x16(regX dst, regX src) %{
3139 MacroAssembler _masm(&cbuf);
3141 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3142 %}
3144 enc_class pshufd(regXD dst, regXD src, int mode) %{
3145 MacroAssembler _masm(&cbuf);
3147 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3148 %}
3150 enc_class pxor(regXD dst, regXD src) %{
3151 MacroAssembler _masm(&cbuf);
3153 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3154 %}
3156 enc_class mov_i2x(regXD dst, eRegI src) %{
3157 MacroAssembler _masm(&cbuf);
3159 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3160 %}
3163 // Because the transitions from emitted code to the runtime
3164 // monitorenter/exit helper stubs are so slow it's critical that
3165 // we inline both the stack-locking fast-path and the inflated fast path.
3166 //
3167 // See also: cmpFastLock and cmpFastUnlock.
3168 //
3169 // What follows is a specialized inline transliteration of the code
3170 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3171 // another option would be to emit TrySlowEnter and TrySlowExit methods
3172 // at startup-time. These methods would accept arguments as
3173 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3174 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3175 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3176 // In practice, however, the # of lock sites is bounded and is usually small.
3177 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3178 // if the processor uses simple bimodal branch predictors keyed by EIP
3179 // Since the helper routines would be called from multiple synchronization
3180 // sites.
3181 //
3182 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3183 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3184 // to those specialized methods. That'd give us a mostly platform-independent
3185 // implementation that the JITs could optimize and inline at their pleasure.
3186 // Done correctly, the only time we'd need to cross to native could would be
3187 // to park() or unpark() threads. We'd also need a few more unsafe operators
3188 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3189 // (b) explicit barriers or fence operations.
3190 //
3191 // TODO:
3192 //
3193 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3194 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3195 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3196 // the lock operators would typically be faster than reifying Self.
3197 //
3198 // * Ideally I'd define the primitives as:
3199 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3200 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3201 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3202 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3203 // Furthermore the register assignments are overconstrained, possibly resulting in
3204 // sub-optimal code near the synchronization site.
3205 //
3206 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3207 // Alternately, use a better sp-proximity test.
3208 //
3209 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3210 // Either one is sufficient to uniquely identify a thread.
3211 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3212 //
3213 // * Intrinsify notify() and notifyAll() for the common cases where the
3214 // object is locked by the calling thread but the waitlist is empty.
3215 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3216 //
3217 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3218 // But beware of excessive branch density on AMD Opterons.
3219 //
3220 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3221 // or failure of the fast-path. If the fast-path fails then we pass
3222 // control to the slow-path, typically in C. In Fast_Lock and
3223 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3224 // will emit a conditional branch immediately after the node.
3225 // So we have branches to branches and lots of ICC.ZF games.
3226 // Instead, it might be better to have C2 pass a "FailureLabel"
3227 // into Fast_Lock and Fast_Unlock. In the case of success, control
3228 // will drop through the node. ICC.ZF is undefined at exit.
3229 // In the case of failure, the node will branch directly to the
3230 // FailureLabel
3233 // obj: object to lock
3234 // box: on-stack box address (displaced header location) - KILLED
3235 // rax,: tmp -- KILLED
3236 // scr: tmp -- KILLED
3237 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3239 Register objReg = as_Register($obj$$reg);
3240 Register boxReg = as_Register($box$$reg);
3241 Register tmpReg = as_Register($tmp$$reg);
3242 Register scrReg = as_Register($scr$$reg);
3244 // Ensure the register assignents are disjoint
3245 guarantee (objReg != boxReg, "") ;
3246 guarantee (objReg != tmpReg, "") ;
3247 guarantee (objReg != scrReg, "") ;
3248 guarantee (boxReg != tmpReg, "") ;
3249 guarantee (boxReg != scrReg, "") ;
3250 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3252 MacroAssembler masm(&cbuf);
3254 if (_counters != NULL) {
3255 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3256 }
3257 if (EmitSync & 1) {
3258 // set box->dhw = unused_mark (3)
3259 // Force all sync thru slow-path: slow_enter() and slow_exit()
3260 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3261 masm.cmpptr (rsp, (int32_t)0) ;
3262 } else
3263 if (EmitSync & 2) {
3264 Label DONE_LABEL ;
3265 if (UseBiasedLocking) {
3266 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3267 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3268 }
3270 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3271 masm.orptr (tmpReg, 0x1);
3272 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3273 if (os::is_MP()) { masm.lock(); }
3274 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3275 masm.jcc(Assembler::equal, DONE_LABEL);
3276 // Recursive locking
3277 masm.subptr(tmpReg, rsp);
3278 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3279 masm.movptr(Address(boxReg, 0), tmpReg);
3280 masm.bind(DONE_LABEL) ;
3281 } else {
3282 // Possible cases that we'll encounter in fast_lock
3283 // ------------------------------------------------
3284 // * Inflated
3285 // -- unlocked
3286 // -- Locked
3287 // = by self
3288 // = by other
3289 // * biased
3290 // -- by Self
3291 // -- by other
3292 // * neutral
3293 // * stack-locked
3294 // -- by self
3295 // = sp-proximity test hits
3296 // = sp-proximity test generates false-negative
3297 // -- by other
3298 //
3300 Label IsInflated, DONE_LABEL, PopDone ;
3302 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3303 // order to reduce the number of conditional branches in the most common cases.
3304 // Beware -- there's a subtle invariant that fetch of the markword
3305 // at [FETCH], below, will never observe a biased encoding (*101b).
3306 // If this invariant is not held we risk exclusion (safety) failure.
3307 if (UseBiasedLocking && !UseOptoBiasInlining) {
3308 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3309 }
3311 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3312 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3313 masm.jccb (Assembler::notZero, IsInflated) ;
3315 // Attempt stack-locking ...
3316 masm.orptr (tmpReg, 0x1);
3317 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3318 if (os::is_MP()) { masm.lock(); }
3319 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3320 if (_counters != NULL) {
3321 masm.cond_inc32(Assembler::equal,
3322 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3323 }
3324 masm.jccb (Assembler::equal, DONE_LABEL);
3326 // Recursive locking
3327 masm.subptr(tmpReg, rsp);
3328 masm.andptr(tmpReg, 0xFFFFF003 );
3329 masm.movptr(Address(boxReg, 0), tmpReg);
3330 if (_counters != NULL) {
3331 masm.cond_inc32(Assembler::equal,
3332 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3333 }
3334 masm.jmp (DONE_LABEL) ;
3336 masm.bind (IsInflated) ;
3338 // The object is inflated.
3339 //
3340 // TODO-FIXME: eliminate the ugly use of manifest constants:
3341 // Use markOopDesc::monitor_value instead of "2".
3342 // use markOop::unused_mark() instead of "3".
3343 // The tmpReg value is an objectMonitor reference ORed with
3344 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3345 // objectmonitor pointer by masking off the "2" bit or we can just
3346 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3347 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3348 //
3349 // I use the latter as it avoids AGI stalls.
3350 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3351 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3352 //
3353 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3355 // boxReg refers to the on-stack BasicLock in the current frame.
3356 // We'd like to write:
3357 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3358 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3359 // additional latency as we have another ST in the store buffer that must drain.
3361 if (EmitSync & 8192) {
3362 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3363 masm.get_thread (scrReg) ;
3364 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3365 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3366 if (os::is_MP()) { masm.lock(); }
3367 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3368 } else
3369 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3370 masm.movptr(scrReg, boxReg) ;
3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3373 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3374 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3375 // prefetchw [eax + Offset(_owner)-2]
3376 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3377 }
3379 if ((EmitSync & 64) == 0) {
3380 // Optimistic form: consider XORL tmpReg,tmpReg
3381 masm.movptr(tmpReg, NULL_WORD) ;
3382 } else {
3383 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3384 // Test-And-CAS instead of CAS
3385 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3386 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3387 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3388 }
3390 // Appears unlocked - try to swing _owner from null to non-null.
3391 // Ideally, I'd manifest "Self" with get_thread and then attempt
3392 // to CAS the register containing Self into m->Owner.
3393 // But we don't have enough registers, so instead we can either try to CAS
3394 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3395 // we later store "Self" into m->Owner. Transiently storing a stack address
3396 // (rsp or the address of the box) into m->owner is harmless.
3397 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3398 if (os::is_MP()) { masm.lock(); }
3399 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3400 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3401 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3402 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3403 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3404 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3406 // If the CAS fails we can either retry or pass control to the slow-path.
3407 // We use the latter tactic.
3408 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3409 // If the CAS was successful ...
3410 // Self has acquired the lock
3411 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3412 // Intentional fall-through into DONE_LABEL ...
3413 } else {
3414 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3415 masm.movptr(boxReg, tmpReg) ;
3417 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3418 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3419 // prefetchw [eax + Offset(_owner)-2]
3420 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3421 }
3423 if ((EmitSync & 64) == 0) {
3424 // Optimistic form
3425 masm.xorptr (tmpReg, tmpReg) ;
3426 } else {
3427 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3428 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3429 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3430 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3431 }
3433 // Appears unlocked - try to swing _owner from null to non-null.
3434 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3435 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3436 masm.get_thread (scrReg) ;
3437 if (os::is_MP()) { masm.lock(); }
3438 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3440 // If the CAS fails we can either retry or pass control to the slow-path.
3441 // We use the latter tactic.
3442 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3443 // If the CAS was successful ...
3444 // Self has acquired the lock
3445 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3446 // Intentional fall-through into DONE_LABEL ...
3447 }
3449 // DONE_LABEL is a hot target - we'd really like to place it at the
3450 // start of cache line by padding with NOPs.
3451 // See the AMD and Intel software optimization manuals for the
3452 // most efficient "long" NOP encodings.
3453 // Unfortunately none of our alignment mechanisms suffice.
3454 masm.bind(DONE_LABEL);
3456 // Avoid branch-to-branch on AMD processors
3457 // This appears to be superstition.
3458 if (EmitSync & 32) masm.nop() ;
3461 // At DONE_LABEL the icc ZFlag is set as follows ...
3462 // Fast_Unlock uses the same protocol.
3463 // ZFlag == 1 -> Success
3464 // ZFlag == 0 -> Failure - force control through the slow-path
3465 }
3466 %}
3468 // obj: object to unlock
3469 // box: box address (displaced header location), killed. Must be EAX.
3470 // rbx,: killed tmp; cannot be obj nor box.
3471 //
3472 // Some commentary on balanced locking:
3473 //
3474 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3475 // Methods that don't have provably balanced locking are forced to run in the
3476 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3477 // The interpreter provides two properties:
3478 // I1: At return-time the interpreter automatically and quietly unlocks any
3479 // objects acquired the current activation (frame). Recall that the
3480 // interpreter maintains an on-stack list of locks currently held by
3481 // a frame.
3482 // I2: If a method attempts to unlock an object that is not held by the
3483 // the frame the interpreter throws IMSX.
3484 //
3485 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3486 // B() doesn't have provably balanced locking so it runs in the interpreter.
3487 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3488 // is still locked by A().
3489 //
3490 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3491 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3492 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3493 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3495 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3497 Register objReg = as_Register($obj$$reg);
3498 Register boxReg = as_Register($box$$reg);
3499 Register tmpReg = as_Register($tmp$$reg);
3501 guarantee (objReg != boxReg, "") ;
3502 guarantee (objReg != tmpReg, "") ;
3503 guarantee (boxReg != tmpReg, "") ;
3504 guarantee (boxReg == as_Register(EAX_enc), "") ;
3505 MacroAssembler masm(&cbuf);
3507 if (EmitSync & 4) {
3508 // Disable - inhibit all inlining. Force control through the slow-path
3509 masm.cmpptr (rsp, 0) ;
3510 } else
3511 if (EmitSync & 8) {
3512 Label DONE_LABEL ;
3513 if (UseBiasedLocking) {
3514 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3515 }
3516 // classic stack-locking code ...
3517 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3518 masm.testptr(tmpReg, tmpReg) ;
3519 masm.jcc (Assembler::zero, DONE_LABEL) ;
3520 if (os::is_MP()) { masm.lock(); }
3521 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3522 masm.bind(DONE_LABEL);
3523 } else {
3524 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3526 // Critically, the biased locking test must have precedence over
3527 // and appear before the (box->dhw == 0) recursive stack-lock test.
3528 if (UseBiasedLocking && !UseOptoBiasInlining) {
3529 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3530 }
3532 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3533 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3534 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3536 masm.testptr(tmpReg, 0x02) ; // Inflated?
3537 masm.jccb (Assembler::zero, Stacked) ;
3539 masm.bind (Inflated) ;
3540 // It's inflated.
3541 // Despite our balanced locking property we still check that m->_owner == Self
3542 // as java routines or native JNI code called by this thread might
3543 // have released the lock.
3544 // Refer to the comments in synchronizer.cpp for how we might encode extra
3545 // state in _succ so we can avoid fetching EntryList|cxq.
3546 //
3547 // I'd like to add more cases in fast_lock() and fast_unlock() --
3548 // such as recursive enter and exit -- but we have to be wary of
3549 // I$ bloat, T$ effects and BP$ effects.
3550 //
3551 // If there's no contention try a 1-0 exit. That is, exit without
3552 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3553 // we detect and recover from the race that the 1-0 exit admits.
3554 //
3555 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3556 // before it STs null into _owner, releasing the lock. Updates
3557 // to data protected by the critical section must be visible before
3558 // we drop the lock (and thus before any other thread could acquire
3559 // the lock and observe the fields protected by the lock).
3560 // IA32's memory-model is SPO, so STs are ordered with respect to
3561 // each other and there's no need for an explicit barrier (fence).
3562 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3564 masm.get_thread (boxReg) ;
3565 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3566 // prefetchw [ebx + Offset(_owner)-2]
3567 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3568 }
3570 // Note that we could employ various encoding schemes to reduce
3571 // the number of loads below (currently 4) to just 2 or 3.
3572 // Refer to the comments in synchronizer.cpp.
3573 // In practice the chain of fetches doesn't seem to impact performance, however.
3574 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3575 // Attempt to reduce branch density - AMD's branch predictor.
3576 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3577 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3578 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3579 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3580 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3581 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3582 masm.jmpb (DONE_LABEL) ;
3583 } else {
3584 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3586 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3587 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3588 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3589 masm.jccb (Assembler::notZero, CheckSucc) ;
3590 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3591 masm.jmpb (DONE_LABEL) ;
3592 }
3594 // The Following code fragment (EmitSync & 65536) improves the performance of
3595 // contended applications and contended synchronization microbenchmarks.
3596 // Unfortunately the emission of the code - even though not executed - causes regressions
3597 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3598 // with an equal number of never-executed NOPs results in the same regression.
3599 // We leave it off by default.
3601 if ((EmitSync & 65536) != 0) {
3602 Label LSuccess, LGoSlowPath ;
3604 masm.bind (CheckSucc) ;
3606 // Optional pre-test ... it's safe to elide this
3607 if ((EmitSync & 16) == 0) {
3608 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3609 masm.jccb (Assembler::zero, LGoSlowPath) ;
3610 }
3612 // We have a classic Dekker-style idiom:
3613 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3614 // There are a number of ways to implement the barrier:
3615 // (1) lock:andl &m->_owner, 0
3616 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3617 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3618 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3619 // (2) If supported, an explicit MFENCE is appealing.
3620 // In older IA32 processors MFENCE is slower than lock:add or xchg
3621 // particularly if the write-buffer is full as might be the case if
3622 // if stores closely precede the fence or fence-equivalent instruction.
3623 // In more modern implementations MFENCE appears faster, however.
3624 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3625 // The $lines underlying the top-of-stack should be in M-state.
3626 // The locked add instruction is serializing, of course.
3627 // (4) Use xchg, which is serializing
3628 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3629 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3630 // The integer condition codes will tell us if succ was 0.
3631 // Since _succ and _owner should reside in the same $line and
3632 // we just stored into _owner, it's likely that the $line
3633 // remains in M-state for the lock:orl.
3634 //
3635 // We currently use (3), although it's likely that switching to (2)
3636 // is correct for the future.
3638 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3639 if (os::is_MP()) {
3640 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3641 masm.mfence();
3642 } else {
3643 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3644 }
3645 }
3646 // Ratify _succ remains non-null
3647 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3648 masm.jccb (Assembler::notZero, LSuccess) ;
3650 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3651 if (os::is_MP()) { masm.lock(); }
3652 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3653 masm.jccb (Assembler::notEqual, LSuccess) ;
3654 // Since we're low on registers we installed rsp as a placeholding in _owner.
3655 // Now install Self over rsp. This is safe as we're transitioning from
3656 // non-null to non=null
3657 masm.get_thread (boxReg) ;
3658 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3659 // Intentional fall-through into LGoSlowPath ...
3661 masm.bind (LGoSlowPath) ;
3662 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3663 masm.jmpb (DONE_LABEL) ;
3665 masm.bind (LSuccess) ;
3666 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3667 masm.jmpb (DONE_LABEL) ;
3668 }
3670 masm.bind (Stacked) ;
3671 // It's not inflated and it's not recursively stack-locked and it's not biased.
3672 // It must be stack-locked.
3673 // Try to reset the header to displaced header.
3674 // The "box" value on the stack is stable, so we can reload
3675 // and be assured we observe the same value as above.
3676 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3677 if (os::is_MP()) { masm.lock(); }
3678 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3679 // Intention fall-thru into DONE_LABEL
3682 // DONE_LABEL is a hot target - we'd really like to place it at the
3683 // start of cache line by padding with NOPs.
3684 // See the AMD and Intel software optimization manuals for the
3685 // most efficient "long" NOP encodings.
3686 // Unfortunately none of our alignment mechanisms suffice.
3687 if ((EmitSync & 65536) == 0) {
3688 masm.bind (CheckSucc) ;
3689 }
3690 masm.bind(DONE_LABEL);
3692 // Avoid branch to branch on AMD processors
3693 if (EmitSync & 32768) { masm.nop() ; }
3694 }
3695 %}
3697 enc_class enc_String_Compare() %{
3698 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3699 POP_LABEL, DONE_LABEL, CONT_LABEL,
3700 WHILE_HEAD_LABEL;
3701 MacroAssembler masm(&cbuf);
3703 // Get the first character position in both strings
3704 // [8] char array, [12] offset, [16] count
3705 int value_offset = java_lang_String::value_offset_in_bytes();
3706 int offset_offset = java_lang_String::offset_offset_in_bytes();
3707 int count_offset = java_lang_String::count_offset_in_bytes();
3708 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3710 masm.movptr(rax, Address(rsi, value_offset));
3711 masm.movl(rcx, Address(rsi, offset_offset));
3712 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3713 masm.movptr(rbx, Address(rdi, value_offset));
3714 masm.movl(rcx, Address(rdi, offset_offset));
3715 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3717 // Compute the minimum of the string lengths(rsi) and the
3718 // difference of the string lengths (stack)
3721 if (VM_Version::supports_cmov()) {
3722 masm.movl(rdi, Address(rdi, count_offset));
3723 masm.movl(rsi, Address(rsi, count_offset));
3724 masm.movl(rcx, rdi);
3725 masm.subl(rdi, rsi);
3726 masm.push(rdi);
3727 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3728 } else {
3729 masm.movl(rdi, Address(rdi, count_offset));
3730 masm.movl(rcx, Address(rsi, count_offset));
3731 masm.movl(rsi, rdi);
3732 masm.subl(rdi, rcx);
3733 masm.push(rdi);
3734 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL);
3735 masm.movl(rsi, rcx);
3736 // rsi holds min, rcx is unused
3737 }
3739 // Is the minimum length zero?
3740 masm.bind(ECX_GOOD_LABEL);
3741 masm.testl(rsi, rsi);
3742 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3744 // Load first characters
3745 masm.load_unsigned_short(rcx, Address(rbx, 0));
3746 masm.load_unsigned_short(rdi, Address(rax, 0));
3748 // Compare first characters
3749 masm.subl(rcx, rdi);
3750 masm.jcc(Assembler::notZero, POP_LABEL);
3751 masm.decrementl(rsi);
3752 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3754 {
3755 // Check after comparing first character to see if strings are equivalent
3756 Label LSkip2;
3757 // Check if the strings start at same location
3758 masm.cmpptr(rbx,rax);
3759 masm.jcc(Assembler::notEqual, LSkip2);
3761 // Check if the length difference is zero (from stack)
3762 masm.cmpl(Address(rsp, 0), 0x0);
3763 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3765 // Strings might not be equivalent
3766 masm.bind(LSkip2);
3767 }
3769 // Shift rax, and rbx, to the end of the arrays, negate min
3770 masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
3771 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
3772 masm.negl(rsi);
3774 // Compare the rest of the characters
3775 masm.bind(WHILE_HEAD_LABEL);
3776 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0));
3777 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0));
3778 masm.subl(rcx, rdi);
3779 masm.jcc(Assembler::notZero, POP_LABEL);
3780 masm.incrementl(rsi);
3781 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3783 // Strings are equal up to min length. Return the length difference.
3784 masm.bind(LENGTH_DIFF_LABEL);
3785 masm.pop(rcx);
3786 masm.jmp(DONE_LABEL);
3788 // Discard the stored length difference
3789 masm.bind(POP_LABEL);
3790 masm.addptr(rsp, 4);
3792 // That's it
3793 masm.bind(DONE_LABEL);
3794 %}
3796 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result) %{
3797 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
3798 MacroAssembler masm(&cbuf);
3800 Register ary1Reg = as_Register($ary1$$reg);
3801 Register ary2Reg = as_Register($ary2$$reg);
3802 Register tmp1Reg = as_Register($tmp1$$reg);
3803 Register tmp2Reg = as_Register($tmp2$$reg);
3804 Register resultReg = as_Register($result$$reg);
3806 int length_offset = arrayOopDesc::length_offset_in_bytes();
3807 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3809 // Check the input args
3810 masm.cmpl(ary1Reg, ary2Reg);
3811 masm.jcc(Assembler::equal, TRUE_LABEL);
3812 masm.testl(ary1Reg, ary1Reg);
3813 masm.jcc(Assembler::zero, FALSE_LABEL);
3814 masm.testl(ary2Reg, ary2Reg);
3815 masm.jcc(Assembler::zero, FALSE_LABEL);
3817 // Check the lengths
3818 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
3819 masm.movl(resultReg, Address(ary2Reg, length_offset));
3820 masm.cmpl(tmp2Reg, resultReg);
3821 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3822 masm.testl(resultReg, resultReg);
3823 masm.jcc(Assembler::zero, TRUE_LABEL);
3825 // Get the number of 4 byte vectors to compare
3826 masm.shrl(resultReg, 1);
3828 // Check for odd-length arrays
3829 masm.andl(tmp2Reg, 1);
3830 masm.testl(tmp2Reg, tmp2Reg);
3831 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR);
3833 // Compare 2-byte "tail" at end of arrays
3834 masm.load_unsigned_short(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3835 masm.load_unsigned_short(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3836 masm.cmpl(tmp1Reg, tmp2Reg);
3837 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3838 masm.testl(resultReg, resultReg);
3839 masm.jcc(Assembler::zero, TRUE_LABEL);
3841 // Setup compare loop
3842 masm.bind(COMPARE_LOOP_HDR);
3843 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
3844 masm.leal(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3845 masm.leal(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3846 masm.negl(resultReg);
3848 // 4-byte-wide compare loop
3849 masm.bind(COMPARE_LOOP);
3850 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
3851 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
3852 masm.cmpl(ary1Reg, ary2Reg);
3853 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3854 masm.increment(resultReg);
3855 masm.jcc(Assembler::notZero, COMPARE_LOOP);
3857 masm.bind(TRUE_LABEL);
3858 masm.movl(resultReg, 1); // return true
3859 masm.jmp(DONE_LABEL);
3861 masm.bind(FALSE_LABEL);
3862 masm.xorl(resultReg, resultReg); // return false
3864 // That's it
3865 masm.bind(DONE_LABEL);
3866 %}
3868 enc_class enc_pop_rdx() %{
3869 emit_opcode(cbuf,0x5A);
3870 %}
3872 enc_class enc_rethrow() %{
3873 cbuf.set_inst_mark();
3874 emit_opcode(cbuf, 0xE9); // jmp entry
3875 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3876 runtime_call_Relocation::spec(), RELOC_IMM32 );
3877 %}
3880 // Convert a double to an int. Java semantics require we do complex
3881 // manglelations in the corner cases. So we set the rounding mode to
3882 // 'zero', store the darned double down as an int, and reset the
3883 // rounding mode to 'nearest'. The hardware throws an exception which
3884 // patches up the correct value directly to the stack.
3885 enc_class D2I_encoding( regD src ) %{
3886 // Flip to round-to-zero mode. We attempted to allow invalid-op
3887 // exceptions here, so that a NAN or other corner-case value will
3888 // thrown an exception (but normal values get converted at full speed).
3889 // However, I2C adapters and other float-stack manglers leave pending
3890 // invalid-op exceptions hanging. We would have to clear them before
3891 // enabling them and that is more expensive than just testing for the
3892 // invalid value Intel stores down in the corner cases.
3893 emit_opcode(cbuf,0xD9); // FLDCW trunc
3894 emit_opcode(cbuf,0x2D);
3895 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3896 // Allocate a word
3897 emit_opcode(cbuf,0x83); // SUB ESP,4
3898 emit_opcode(cbuf,0xEC);
3899 emit_d8(cbuf,0x04);
3900 // Encoding assumes a double has been pushed into FPR0.
3901 // Store down the double as an int, popping the FPU stack
3902 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3903 emit_opcode(cbuf,0x1C);
3904 emit_d8(cbuf,0x24);
3905 // Restore the rounding mode; mask the exception
3906 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3907 emit_opcode(cbuf,0x2D);
3908 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3909 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3910 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3912 // Load the converted int; adjust CPU stack
3913 emit_opcode(cbuf,0x58); // POP EAX
3914 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3915 emit_d32 (cbuf,0x80000000); // 0x80000000
3916 emit_opcode(cbuf,0x75); // JNE around_slow_call
3917 emit_d8 (cbuf,0x07); // Size of slow_call
3918 // Push src onto stack slow-path
3919 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3920 emit_d8 (cbuf,0xC0-1+$src$$reg );
3921 // CALL directly to the runtime
3922 cbuf.set_inst_mark();
3923 emit_opcode(cbuf,0xE8); // Call into runtime
3924 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3925 // Carry on here...
3926 %}
3928 enc_class D2L_encoding( regD src ) %{
3929 emit_opcode(cbuf,0xD9); // FLDCW trunc
3930 emit_opcode(cbuf,0x2D);
3931 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3932 // Allocate a word
3933 emit_opcode(cbuf,0x83); // SUB ESP,8
3934 emit_opcode(cbuf,0xEC);
3935 emit_d8(cbuf,0x08);
3936 // Encoding assumes a double has been pushed into FPR0.
3937 // Store down the double as a long, popping the FPU stack
3938 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3939 emit_opcode(cbuf,0x3C);
3940 emit_d8(cbuf,0x24);
3941 // Restore the rounding mode; mask the exception
3942 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3943 emit_opcode(cbuf,0x2D);
3944 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3945 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3946 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3948 // Load the converted int; adjust CPU stack
3949 emit_opcode(cbuf,0x58); // POP EAX
3950 emit_opcode(cbuf,0x5A); // POP EDX
3951 emit_opcode(cbuf,0x81); // CMP EDX,imm
3952 emit_d8 (cbuf,0xFA); // rdx
3953 emit_d32 (cbuf,0x80000000); // 0x80000000
3954 emit_opcode(cbuf,0x75); // JNE around_slow_call
3955 emit_d8 (cbuf,0x07+4); // Size of slow_call
3956 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3957 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3958 emit_opcode(cbuf,0x75); // JNE around_slow_call
3959 emit_d8 (cbuf,0x07); // Size of slow_call
3960 // Push src onto stack slow-path
3961 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3962 emit_d8 (cbuf,0xC0-1+$src$$reg );
3963 // CALL directly to the runtime
3964 cbuf.set_inst_mark();
3965 emit_opcode(cbuf,0xE8); // Call into runtime
3966 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3967 // Carry on here...
3968 %}
3970 enc_class X2L_encoding( regX src ) %{
3971 // Allocate a word
3972 emit_opcode(cbuf,0x83); // SUB ESP,8
3973 emit_opcode(cbuf,0xEC);
3974 emit_d8(cbuf,0x08);
3976 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3977 emit_opcode (cbuf, 0x0F );
3978 emit_opcode (cbuf, 0x11 );
3979 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3981 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3982 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3984 emit_opcode(cbuf,0xD9); // FLDCW trunc
3985 emit_opcode(cbuf,0x2D);
3986 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3988 // Encoding assumes a double has been pushed into FPR0.
3989 // Store down the double as a long, popping the FPU stack
3990 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3991 emit_opcode(cbuf,0x3C);
3992 emit_d8(cbuf,0x24);
3994 // Restore the rounding mode; mask the exception
3995 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3996 emit_opcode(cbuf,0x2D);
3997 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3998 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3999 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4001 // Load the converted int; adjust CPU stack
4002 emit_opcode(cbuf,0x58); // POP EAX
4004 emit_opcode(cbuf,0x5A); // POP EDX
4006 emit_opcode(cbuf,0x81); // CMP EDX,imm
4007 emit_d8 (cbuf,0xFA); // rdx
4008 emit_d32 (cbuf,0x80000000);// 0x80000000
4010 emit_opcode(cbuf,0x75); // JNE around_slow_call
4011 emit_d8 (cbuf,0x13+4); // Size of slow_call
4013 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4014 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4016 emit_opcode(cbuf,0x75); // JNE around_slow_call
4017 emit_d8 (cbuf,0x13); // Size of slow_call
4019 // Allocate a word
4020 emit_opcode(cbuf,0x83); // SUB ESP,4
4021 emit_opcode(cbuf,0xEC);
4022 emit_d8(cbuf,0x04);
4024 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4025 emit_opcode (cbuf, 0x0F );
4026 emit_opcode (cbuf, 0x11 );
4027 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4029 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4030 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4032 emit_opcode(cbuf,0x83); // ADD ESP,4
4033 emit_opcode(cbuf,0xC4);
4034 emit_d8(cbuf,0x04);
4036 // CALL directly to the runtime
4037 cbuf.set_inst_mark();
4038 emit_opcode(cbuf,0xE8); // Call into runtime
4039 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4040 // Carry on here...
4041 %}
4043 enc_class XD2L_encoding( regXD src ) %{
4044 // Allocate a word
4045 emit_opcode(cbuf,0x83); // SUB ESP,8
4046 emit_opcode(cbuf,0xEC);
4047 emit_d8(cbuf,0x08);
4049 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4050 emit_opcode (cbuf, 0x0F );
4051 emit_opcode (cbuf, 0x11 );
4052 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4054 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4055 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4057 emit_opcode(cbuf,0xD9); // FLDCW trunc
4058 emit_opcode(cbuf,0x2D);
4059 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4061 // Encoding assumes a double has been pushed into FPR0.
4062 // Store down the double as a long, popping the FPU stack
4063 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4064 emit_opcode(cbuf,0x3C);
4065 emit_d8(cbuf,0x24);
4067 // Restore the rounding mode; mask the exception
4068 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4069 emit_opcode(cbuf,0x2D);
4070 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4071 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4072 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4074 // Load the converted int; adjust CPU stack
4075 emit_opcode(cbuf,0x58); // POP EAX
4077 emit_opcode(cbuf,0x5A); // POP EDX
4079 emit_opcode(cbuf,0x81); // CMP EDX,imm
4080 emit_d8 (cbuf,0xFA); // rdx
4081 emit_d32 (cbuf,0x80000000); // 0x80000000
4083 emit_opcode(cbuf,0x75); // JNE around_slow_call
4084 emit_d8 (cbuf,0x13+4); // Size of slow_call
4086 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4087 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4089 emit_opcode(cbuf,0x75); // JNE around_slow_call
4090 emit_d8 (cbuf,0x13); // Size of slow_call
4092 // Push src onto stack slow-path
4093 // Allocate a word
4094 emit_opcode(cbuf,0x83); // SUB ESP,8
4095 emit_opcode(cbuf,0xEC);
4096 emit_d8(cbuf,0x08);
4098 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4099 emit_opcode (cbuf, 0x0F );
4100 emit_opcode (cbuf, 0x11 );
4101 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4103 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4104 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4106 emit_opcode(cbuf,0x83); // ADD ESP,8
4107 emit_opcode(cbuf,0xC4);
4108 emit_d8(cbuf,0x08);
4110 // CALL directly to the runtime
4111 cbuf.set_inst_mark();
4112 emit_opcode(cbuf,0xE8); // Call into runtime
4113 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4114 // Carry on here...
4115 %}
4117 enc_class D2X_encoding( regX dst, regD src ) %{
4118 // Allocate a word
4119 emit_opcode(cbuf,0x83); // SUB ESP,4
4120 emit_opcode(cbuf,0xEC);
4121 emit_d8(cbuf,0x04);
4122 int pop = 0x02;
4123 if ($src$$reg != FPR1L_enc) {
4124 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4125 emit_d8( cbuf, 0xC0-1+$src$$reg );
4126 pop = 0x03;
4127 }
4128 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4130 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4131 emit_opcode (cbuf, 0x0F );
4132 emit_opcode (cbuf, 0x10 );
4133 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4135 emit_opcode(cbuf,0x83); // ADD ESP,4
4136 emit_opcode(cbuf,0xC4);
4137 emit_d8(cbuf,0x04);
4138 // Carry on here...
4139 %}
4141 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4142 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4144 // Compare the result to see if we need to go to the slow path
4145 emit_opcode(cbuf,0x81); // CMP dst,imm
4146 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4147 emit_d32 (cbuf,0x80000000); // 0x80000000
4149 emit_opcode(cbuf,0x75); // JNE around_slow_call
4150 emit_d8 (cbuf,0x13); // Size of slow_call
4151 // Store xmm to a temp memory
4152 // location and push it onto stack.
4154 emit_opcode(cbuf,0x83); // SUB ESP,4
4155 emit_opcode(cbuf,0xEC);
4156 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4158 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4159 emit_opcode (cbuf, 0x0F );
4160 emit_opcode (cbuf, 0x11 );
4161 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4163 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4164 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4166 emit_opcode(cbuf,0x83); // ADD ESP,4
4167 emit_opcode(cbuf,0xC4);
4168 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4170 // CALL directly to the runtime
4171 cbuf.set_inst_mark();
4172 emit_opcode(cbuf,0xE8); // Call into runtime
4173 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4175 // Carry on here...
4176 %}
4178 enc_class X2D_encoding( regD dst, regX src ) %{
4179 // Allocate a word
4180 emit_opcode(cbuf,0x83); // SUB ESP,4
4181 emit_opcode(cbuf,0xEC);
4182 emit_d8(cbuf,0x04);
4184 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4185 emit_opcode (cbuf, 0x0F );
4186 emit_opcode (cbuf, 0x11 );
4187 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4189 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4190 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4192 emit_opcode(cbuf,0x83); // ADD ESP,4
4193 emit_opcode(cbuf,0xC4);
4194 emit_d8(cbuf,0x04);
4196 // Carry on here...
4197 %}
4199 enc_class AbsXF_encoding(regX dst) %{
4200 address signmask_address=(address)float_signmask_pool;
4201 // andpd:\tANDPS $dst,[signconst]
4202 emit_opcode(cbuf, 0x0F);
4203 emit_opcode(cbuf, 0x54);
4204 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4205 emit_d32(cbuf, (int)signmask_address);
4206 %}
4208 enc_class AbsXD_encoding(regXD dst) %{
4209 address signmask_address=(address)double_signmask_pool;
4210 // andpd:\tANDPD $dst,[signconst]
4211 emit_opcode(cbuf, 0x66);
4212 emit_opcode(cbuf, 0x0F);
4213 emit_opcode(cbuf, 0x54);
4214 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4215 emit_d32(cbuf, (int)signmask_address);
4216 %}
4218 enc_class NegXF_encoding(regX dst) %{
4219 address signmask_address=(address)float_signflip_pool;
4220 // andpd:\tXORPS $dst,[signconst]
4221 emit_opcode(cbuf, 0x0F);
4222 emit_opcode(cbuf, 0x57);
4223 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4224 emit_d32(cbuf, (int)signmask_address);
4225 %}
4227 enc_class NegXD_encoding(regXD dst) %{
4228 address signmask_address=(address)double_signflip_pool;
4229 // andpd:\tXORPD $dst,[signconst]
4230 emit_opcode(cbuf, 0x66);
4231 emit_opcode(cbuf, 0x0F);
4232 emit_opcode(cbuf, 0x57);
4233 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4234 emit_d32(cbuf, (int)signmask_address);
4235 %}
4237 enc_class FMul_ST_reg( eRegF src1 ) %{
4238 // Operand was loaded from memory into fp ST (stack top)
4239 // FMUL ST,$src /* D8 C8+i */
4240 emit_opcode(cbuf, 0xD8);
4241 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4242 %}
4244 enc_class FAdd_ST_reg( eRegF src2 ) %{
4245 // FADDP ST,src2 /* D8 C0+i */
4246 emit_opcode(cbuf, 0xD8);
4247 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4248 //could use FADDP src2,fpST /* DE C0+i */
4249 %}
4251 enc_class FAddP_reg_ST( eRegF src2 ) %{
4252 // FADDP src2,ST /* DE C0+i */
4253 emit_opcode(cbuf, 0xDE);
4254 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4255 %}
4257 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4258 // Operand has been loaded into fp ST (stack top)
4259 // FSUB ST,$src1
4260 emit_opcode(cbuf, 0xD8);
4261 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4263 // FDIV
4264 emit_opcode(cbuf, 0xD8);
4265 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4266 %}
4268 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4269 // Operand was loaded from memory into fp ST (stack top)
4270 // FADD ST,$src /* D8 C0+i */
4271 emit_opcode(cbuf, 0xD8);
4272 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4274 // FMUL ST,src2 /* D8 C*+i */
4275 emit_opcode(cbuf, 0xD8);
4276 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4277 %}
4280 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4281 // Operand was loaded from memory into fp ST (stack top)
4282 // FADD ST,$src /* D8 C0+i */
4283 emit_opcode(cbuf, 0xD8);
4284 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4286 // FMULP src2,ST /* DE C8+i */
4287 emit_opcode(cbuf, 0xDE);
4288 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4289 %}
4291 // Atomically load the volatile long
4292 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4293 emit_opcode(cbuf,0xDF);
4294 int rm_byte_opcode = 0x05;
4295 int base = $mem$$base;
4296 int index = $mem$$index;
4297 int scale = $mem$$scale;
4298 int displace = $mem$$disp;
4299 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4300 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4301 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4302 %}
4304 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4305 { // Atomic long load
4306 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4307 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4308 emit_opcode(cbuf,0x0F);
4309 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4310 int base = $mem$$base;
4311 int index = $mem$$index;
4312 int scale = $mem$$scale;
4313 int displace = $mem$$disp;
4314 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4315 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4316 }
4317 { // MOVSD $dst,$tmp ! atomic long store
4318 emit_opcode(cbuf,0xF2);
4319 emit_opcode(cbuf,0x0F);
4320 emit_opcode(cbuf,0x11);
4321 int base = $dst$$base;
4322 int index = $dst$$index;
4323 int scale = $dst$$scale;
4324 int displace = $dst$$disp;
4325 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4326 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4327 }
4328 %}
4330 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4331 { // Atomic long load
4332 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4333 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4334 emit_opcode(cbuf,0x0F);
4335 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4336 int base = $mem$$base;
4337 int index = $mem$$index;
4338 int scale = $mem$$scale;
4339 int displace = $mem$$disp;
4340 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4341 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4342 }
4343 { // MOVD $dst.lo,$tmp
4344 emit_opcode(cbuf,0x66);
4345 emit_opcode(cbuf,0x0F);
4346 emit_opcode(cbuf,0x7E);
4347 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4348 }
4349 { // PSRLQ $tmp,32
4350 emit_opcode(cbuf,0x66);
4351 emit_opcode(cbuf,0x0F);
4352 emit_opcode(cbuf,0x73);
4353 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4354 emit_d8(cbuf, 0x20);
4355 }
4356 { // MOVD $dst.hi,$tmp
4357 emit_opcode(cbuf,0x66);
4358 emit_opcode(cbuf,0x0F);
4359 emit_opcode(cbuf,0x7E);
4360 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4361 }
4362 %}
4364 // Volatile Store Long. Must be atomic, so move it into
4365 // the FP TOS and then do a 64-bit FIST. Has to probe the
4366 // target address before the store (for null-ptr checks)
4367 // so the memory operand is used twice in the encoding.
4368 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4369 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4370 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4371 emit_opcode(cbuf,0xDF);
4372 int rm_byte_opcode = 0x07;
4373 int base = $mem$$base;
4374 int index = $mem$$index;
4375 int scale = $mem$$scale;
4376 int displace = $mem$$disp;
4377 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4378 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4379 %}
4381 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4382 { // Atomic long load
4383 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4384 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4385 emit_opcode(cbuf,0x0F);
4386 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4387 int base = $src$$base;
4388 int index = $src$$index;
4389 int scale = $src$$scale;
4390 int displace = $src$$disp;
4391 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4392 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4393 }
4394 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4395 { // MOVSD $mem,$tmp ! atomic long store
4396 emit_opcode(cbuf,0xF2);
4397 emit_opcode(cbuf,0x0F);
4398 emit_opcode(cbuf,0x11);
4399 int base = $mem$$base;
4400 int index = $mem$$index;
4401 int scale = $mem$$scale;
4402 int displace = $mem$$disp;
4403 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4404 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4405 }
4406 %}
4408 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4409 { // MOVD $tmp,$src.lo
4410 emit_opcode(cbuf,0x66);
4411 emit_opcode(cbuf,0x0F);
4412 emit_opcode(cbuf,0x6E);
4413 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4414 }
4415 { // MOVD $tmp2,$src.hi
4416 emit_opcode(cbuf,0x66);
4417 emit_opcode(cbuf,0x0F);
4418 emit_opcode(cbuf,0x6E);
4419 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4420 }
4421 { // PUNPCKLDQ $tmp,$tmp2
4422 emit_opcode(cbuf,0x66);
4423 emit_opcode(cbuf,0x0F);
4424 emit_opcode(cbuf,0x62);
4425 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4426 }
4427 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4428 { // MOVSD $mem,$tmp ! atomic long store
4429 emit_opcode(cbuf,0xF2);
4430 emit_opcode(cbuf,0x0F);
4431 emit_opcode(cbuf,0x11);
4432 int base = $mem$$base;
4433 int index = $mem$$index;
4434 int scale = $mem$$scale;
4435 int displace = $mem$$disp;
4436 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4437 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4438 }
4439 %}
4441 // Safepoint Poll. This polls the safepoint page, and causes an
4442 // exception if it is not readable. Unfortunately, it kills the condition code
4443 // in the process
4444 // We current use TESTL [spp],EDI
4445 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4447 enc_class Safepoint_Poll() %{
4448 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4449 emit_opcode(cbuf,0x85);
4450 emit_rm (cbuf, 0x0, 0x7, 0x5);
4451 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4452 %}
4453 %}
4456 //----------FRAME--------------------------------------------------------------
4457 // Definition of frame structure and management information.
4458 //
4459 // S T A C K L A Y O U T Allocators stack-slot number
4460 // | (to get allocators register number
4461 // G Owned by | | v add OptoReg::stack0())
4462 // r CALLER | |
4463 // o | +--------+ pad to even-align allocators stack-slot
4464 // w V | pad0 | numbers; owned by CALLER
4465 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4466 // h ^ | in | 5
4467 // | | args | 4 Holes in incoming args owned by SELF
4468 // | | | | 3
4469 // | | +--------+
4470 // V | | old out| Empty on Intel, window on Sparc
4471 // | old |preserve| Must be even aligned.
4472 // | SP-+--------+----> Matcher::_old_SP, even aligned
4473 // | | in | 3 area for Intel ret address
4474 // Owned by |preserve| Empty on Sparc.
4475 // SELF +--------+
4476 // | | pad2 | 2 pad to align old SP
4477 // | +--------+ 1
4478 // | | locks | 0
4479 // | +--------+----> OptoReg::stack0(), even aligned
4480 // | | pad1 | 11 pad to align new SP
4481 // | +--------+
4482 // | | | 10
4483 // | | spills | 9 spills
4484 // V | | 8 (pad0 slot for callee)
4485 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4486 // ^ | out | 7
4487 // | | args | 6 Holes in outgoing args owned by CALLEE
4488 // Owned by +--------+
4489 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4490 // | new |preserve| Must be even-aligned.
4491 // | SP-+--------+----> Matcher::_new_SP, even aligned
4492 // | | |
4493 //
4494 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4495 // known from SELF's arguments and the Java calling convention.
4496 // Region 6-7 is determined per call site.
4497 // Note 2: If the calling convention leaves holes in the incoming argument
4498 // area, those holes are owned by SELF. Holes in the outgoing area
4499 // are owned by the CALLEE. Holes should not be nessecary in the
4500 // incoming area, as the Java calling convention is completely under
4501 // the control of the AD file. Doubles can be sorted and packed to
4502 // avoid holes. Holes in the outgoing arguments may be nessecary for
4503 // varargs C calling conventions.
4504 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4505 // even aligned with pad0 as needed.
4506 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4507 // region 6-11 is even aligned; it may be padded out more so that
4508 // the region from SP to FP meets the minimum stack alignment.
4510 frame %{
4511 // What direction does stack grow in (assumed to be same for C & Java)
4512 stack_direction(TOWARDS_LOW);
4514 // These three registers define part of the calling convention
4515 // between compiled code and the interpreter.
4516 inline_cache_reg(EAX); // Inline Cache Register
4517 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4519 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4520 cisc_spilling_operand_name(indOffset32);
4522 // Number of stack slots consumed by locking an object
4523 sync_stack_slots(1);
4525 // Compiled code's Frame Pointer
4526 frame_pointer(ESP);
4527 // Interpreter stores its frame pointer in a register which is
4528 // stored to the stack by I2CAdaptors.
4529 // I2CAdaptors convert from interpreted java to compiled java.
4530 interpreter_frame_pointer(EBP);
4532 // Stack alignment requirement
4533 // Alignment size in bytes (128-bit -> 16 bytes)
4534 stack_alignment(StackAlignmentInBytes);
4536 // Number of stack slots between incoming argument block and the start of
4537 // a new frame. The PROLOG must add this many slots to the stack. The
4538 // EPILOG must remove this many slots. Intel needs one slot for
4539 // return address and one for rbp, (must save rbp)
4540 in_preserve_stack_slots(2+VerifyStackAtCalls);
4542 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4543 // for calls to C. Supports the var-args backing area for register parms.
4544 varargs_C_out_slots_killed(0);
4546 // The after-PROLOG location of the return address. Location of
4547 // return address specifies a type (REG or STACK) and a number
4548 // representing the register number (i.e. - use a register name) or
4549 // stack slot.
4550 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4551 // Otherwise, it is above the locks and verification slot and alignment word
4552 return_addr(STACK - 1 +
4553 round_to(1+VerifyStackAtCalls+
4554 Compile::current()->fixed_slots(),
4555 (StackAlignmentInBytes/wordSize)));
4557 // Body of function which returns an integer array locating
4558 // arguments either in registers or in stack slots. Passed an array
4559 // of ideal registers called "sig" and a "length" count. Stack-slot
4560 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4561 // arguments for a CALLEE. Incoming stack arguments are
4562 // automatically biased by the preserve_stack_slots field above.
4563 calling_convention %{
4564 // No difference between ingoing/outgoing just pass false
4565 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4566 %}
4569 // Body of function which returns an integer array locating
4570 // arguments either in registers or in stack slots. Passed an array
4571 // of ideal registers called "sig" and a "length" count. Stack-slot
4572 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4573 // arguments for a CALLEE. Incoming stack arguments are
4574 // automatically biased by the preserve_stack_slots field above.
4575 c_calling_convention %{
4576 // This is obviously always outgoing
4577 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4578 %}
4580 // Location of C & interpreter return values
4581 c_return_value %{
4582 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4583 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4584 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4586 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4587 // that C functions return float and double results in XMM0.
4588 if( ideal_reg == Op_RegD && UseSSE>=2 )
4589 return OptoRegPair(XMM0b_num,XMM0a_num);
4590 if( ideal_reg == Op_RegF && UseSSE>=2 )
4591 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4593 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4594 %}
4596 // Location of return values
4597 return_value %{
4598 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4599 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4600 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4601 if( ideal_reg == Op_RegD && UseSSE>=2 )
4602 return OptoRegPair(XMM0b_num,XMM0a_num);
4603 if( ideal_reg == Op_RegF && UseSSE>=1 )
4604 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4605 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4606 %}
4608 %}
4610 //----------ATTRIBUTES---------------------------------------------------------
4611 //----------Operand Attributes-------------------------------------------------
4612 op_attrib op_cost(0); // Required cost attribute
4614 //----------Instruction Attributes---------------------------------------------
4615 ins_attrib ins_cost(100); // Required cost attribute
4616 ins_attrib ins_size(8); // Required size attribute (in bits)
4617 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4618 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4619 // non-matching short branch variant of some
4620 // long branch?
4621 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4622 // specifies the alignment that some part of the instruction (not
4623 // necessarily the start) requires. If > 1, a compute_padding()
4624 // function must be provided for the instruction
4626 //----------OPERANDS-----------------------------------------------------------
4627 // Operand definitions must precede instruction definitions for correct parsing
4628 // in the ADLC because operands constitute user defined types which are used in
4629 // instruction definitions.
4631 //----------Simple Operands----------------------------------------------------
4632 // Immediate Operands
4633 // Integer Immediate
4634 operand immI() %{
4635 match(ConI);
4637 op_cost(10);
4638 format %{ %}
4639 interface(CONST_INTER);
4640 %}
4642 // Constant for test vs zero
4643 operand immI0() %{
4644 predicate(n->get_int() == 0);
4645 match(ConI);
4647 op_cost(0);
4648 format %{ %}
4649 interface(CONST_INTER);
4650 %}
4652 // Constant for increment
4653 operand immI1() %{
4654 predicate(n->get_int() == 1);
4655 match(ConI);
4657 op_cost(0);
4658 format %{ %}
4659 interface(CONST_INTER);
4660 %}
4662 // Constant for decrement
4663 operand immI_M1() %{
4664 predicate(n->get_int() == -1);
4665 match(ConI);
4667 op_cost(0);
4668 format %{ %}
4669 interface(CONST_INTER);
4670 %}
4672 // Valid scale values for addressing modes
4673 operand immI2() %{
4674 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4675 match(ConI);
4677 format %{ %}
4678 interface(CONST_INTER);
4679 %}
4681 operand immI8() %{
4682 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4683 match(ConI);
4685 op_cost(5);
4686 format %{ %}
4687 interface(CONST_INTER);
4688 %}
4690 operand immI16() %{
4691 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4692 match(ConI);
4694 op_cost(10);
4695 format %{ %}
4696 interface(CONST_INTER);
4697 %}
4699 // Constant for long shifts
4700 operand immI_32() %{
4701 predicate( n->get_int() == 32 );
4702 match(ConI);
4704 op_cost(0);
4705 format %{ %}
4706 interface(CONST_INTER);
4707 %}
4709 operand immI_1_31() %{
4710 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4711 match(ConI);
4713 op_cost(0);
4714 format %{ %}
4715 interface(CONST_INTER);
4716 %}
4718 operand immI_32_63() %{
4719 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4720 match(ConI);
4721 op_cost(0);
4723 format %{ %}
4724 interface(CONST_INTER);
4725 %}
4727 operand immI_1() %{
4728 predicate( n->get_int() == 1 );
4729 match(ConI);
4731 op_cost(0);
4732 format %{ %}
4733 interface(CONST_INTER);
4734 %}
4736 operand immI_2() %{
4737 predicate( n->get_int() == 2 );
4738 match(ConI);
4740 op_cost(0);
4741 format %{ %}
4742 interface(CONST_INTER);
4743 %}
4745 operand immI_3() %{
4746 predicate( n->get_int() == 3 );
4747 match(ConI);
4749 op_cost(0);
4750 format %{ %}
4751 interface(CONST_INTER);
4752 %}
4754 // Pointer Immediate
4755 operand immP() %{
4756 match(ConP);
4758 op_cost(10);
4759 format %{ %}
4760 interface(CONST_INTER);
4761 %}
4763 // NULL Pointer Immediate
4764 operand immP0() %{
4765 predicate( n->get_ptr() == 0 );
4766 match(ConP);
4767 op_cost(0);
4769 format %{ %}
4770 interface(CONST_INTER);
4771 %}
4773 // Long Immediate
4774 operand immL() %{
4775 match(ConL);
4777 op_cost(20);
4778 format %{ %}
4779 interface(CONST_INTER);
4780 %}
4782 // Long Immediate zero
4783 operand immL0() %{
4784 predicate( n->get_long() == 0L );
4785 match(ConL);
4786 op_cost(0);
4788 format %{ %}
4789 interface(CONST_INTER);
4790 %}
4792 // Long Immediate zero
4793 operand immL_M1() %{
4794 predicate( n->get_long() == -1L );
4795 match(ConL);
4796 op_cost(0);
4798 format %{ %}
4799 interface(CONST_INTER);
4800 %}
4802 // Long immediate from 0 to 127.
4803 // Used for a shorter form of long mul by 10.
4804 operand immL_127() %{
4805 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4806 match(ConL);
4807 op_cost(0);
4809 format %{ %}
4810 interface(CONST_INTER);
4811 %}
4813 // Long Immediate: low 32-bit mask
4814 operand immL_32bits() %{
4815 predicate(n->get_long() == 0xFFFFFFFFL);
4816 match(ConL);
4817 op_cost(0);
4819 format %{ %}
4820 interface(CONST_INTER);
4821 %}
4823 // Long Immediate: low 32-bit mask
4824 operand immL32() %{
4825 predicate(n->get_long() == (int)(n->get_long()));
4826 match(ConL);
4827 op_cost(20);
4829 format %{ %}
4830 interface(CONST_INTER);
4831 %}
4833 //Double Immediate zero
4834 operand immD0() %{
4835 // Do additional (and counter-intuitive) test against NaN to work around VC++
4836 // bug that generates code such that NaNs compare equal to 0.0
4837 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4838 match(ConD);
4840 op_cost(5);
4841 format %{ %}
4842 interface(CONST_INTER);
4843 %}
4845 // Double Immediate
4846 operand immD1() %{
4847 predicate( UseSSE<=1 && n->getd() == 1.0 );
4848 match(ConD);
4850 op_cost(5);
4851 format %{ %}
4852 interface(CONST_INTER);
4853 %}
4855 // Double Immediate
4856 operand immD() %{
4857 predicate(UseSSE<=1);
4858 match(ConD);
4860 op_cost(5);
4861 format %{ %}
4862 interface(CONST_INTER);
4863 %}
4865 operand immXD() %{
4866 predicate(UseSSE>=2);
4867 match(ConD);
4869 op_cost(5);
4870 format %{ %}
4871 interface(CONST_INTER);
4872 %}
4874 // Double Immediate zero
4875 operand immXD0() %{
4876 // Do additional (and counter-intuitive) test against NaN to work around VC++
4877 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4878 // compare equal to -0.0.
4879 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4880 match(ConD);
4882 format %{ %}
4883 interface(CONST_INTER);
4884 %}
4886 // Float Immediate zero
4887 operand immF0() %{
4888 predicate( UseSSE == 0 && n->getf() == 0.0 );
4889 match(ConF);
4891 op_cost(5);
4892 format %{ %}
4893 interface(CONST_INTER);
4894 %}
4896 // Float Immediate
4897 operand immF() %{
4898 predicate( UseSSE == 0 );
4899 match(ConF);
4901 op_cost(5);
4902 format %{ %}
4903 interface(CONST_INTER);
4904 %}
4906 // Float Immediate
4907 operand immXF() %{
4908 predicate(UseSSE >= 1);
4909 match(ConF);
4911 op_cost(5);
4912 format %{ %}
4913 interface(CONST_INTER);
4914 %}
4916 // Float Immediate zero. Zero and not -0.0
4917 operand immXF0() %{
4918 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4919 match(ConF);
4921 op_cost(5);
4922 format %{ %}
4923 interface(CONST_INTER);
4924 %}
4926 // Immediates for special shifts (sign extend)
4928 // Constants for increment
4929 operand immI_16() %{
4930 predicate( n->get_int() == 16 );
4931 match(ConI);
4933 format %{ %}
4934 interface(CONST_INTER);
4935 %}
4937 operand immI_24() %{
4938 predicate( n->get_int() == 24 );
4939 match(ConI);
4941 format %{ %}
4942 interface(CONST_INTER);
4943 %}
4945 // Constant for byte-wide masking
4946 operand immI_255() %{
4947 predicate( n->get_int() == 255 );
4948 match(ConI);
4950 format %{ %}
4951 interface(CONST_INTER);
4952 %}
4954 // Register Operands
4955 // Integer Register
4956 operand eRegI() %{
4957 constraint(ALLOC_IN_RC(e_reg));
4958 match(RegI);
4959 match(xRegI);
4960 match(eAXRegI);
4961 match(eBXRegI);
4962 match(eCXRegI);
4963 match(eDXRegI);
4964 match(eDIRegI);
4965 match(eSIRegI);
4967 format %{ %}
4968 interface(REG_INTER);
4969 %}
4971 // Subset of Integer Register
4972 operand xRegI(eRegI reg) %{
4973 constraint(ALLOC_IN_RC(x_reg));
4974 match(reg);
4975 match(eAXRegI);
4976 match(eBXRegI);
4977 match(eCXRegI);
4978 match(eDXRegI);
4980 format %{ %}
4981 interface(REG_INTER);
4982 %}
4984 // Special Registers
4985 operand eAXRegI(xRegI reg) %{
4986 constraint(ALLOC_IN_RC(eax_reg));
4987 match(reg);
4988 match(eRegI);
4990 format %{ "EAX" %}
4991 interface(REG_INTER);
4992 %}
4994 // Special Registers
4995 operand eBXRegI(xRegI reg) %{
4996 constraint(ALLOC_IN_RC(ebx_reg));
4997 match(reg);
4998 match(eRegI);
5000 format %{ "EBX" %}
5001 interface(REG_INTER);
5002 %}
5004 operand eCXRegI(xRegI reg) %{
5005 constraint(ALLOC_IN_RC(ecx_reg));
5006 match(reg);
5007 match(eRegI);
5009 format %{ "ECX" %}
5010 interface(REG_INTER);
5011 %}
5013 operand eDXRegI(xRegI reg) %{
5014 constraint(ALLOC_IN_RC(edx_reg));
5015 match(reg);
5016 match(eRegI);
5018 format %{ "EDX" %}
5019 interface(REG_INTER);
5020 %}
5022 operand eDIRegI(xRegI reg) %{
5023 constraint(ALLOC_IN_RC(edi_reg));
5024 match(reg);
5025 match(eRegI);
5027 format %{ "EDI" %}
5028 interface(REG_INTER);
5029 %}
5031 operand naxRegI() %{
5032 constraint(ALLOC_IN_RC(nax_reg));
5033 match(RegI);
5034 match(eCXRegI);
5035 match(eDXRegI);
5036 match(eSIRegI);
5037 match(eDIRegI);
5039 format %{ %}
5040 interface(REG_INTER);
5041 %}
5043 operand nadxRegI() %{
5044 constraint(ALLOC_IN_RC(nadx_reg));
5045 match(RegI);
5046 match(eBXRegI);
5047 match(eCXRegI);
5048 match(eSIRegI);
5049 match(eDIRegI);
5051 format %{ %}
5052 interface(REG_INTER);
5053 %}
5055 operand ncxRegI() %{
5056 constraint(ALLOC_IN_RC(ncx_reg));
5057 match(RegI);
5058 match(eAXRegI);
5059 match(eDXRegI);
5060 match(eSIRegI);
5061 match(eDIRegI);
5063 format %{ %}
5064 interface(REG_INTER);
5065 %}
5067 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5068 // //
5069 operand eSIRegI(xRegI reg) %{
5070 constraint(ALLOC_IN_RC(esi_reg));
5071 match(reg);
5072 match(eRegI);
5074 format %{ "ESI" %}
5075 interface(REG_INTER);
5076 %}
5078 // Pointer Register
5079 operand anyRegP() %{
5080 constraint(ALLOC_IN_RC(any_reg));
5081 match(RegP);
5082 match(eAXRegP);
5083 match(eBXRegP);
5084 match(eCXRegP);
5085 match(eDIRegP);
5086 match(eRegP);
5088 format %{ %}
5089 interface(REG_INTER);
5090 %}
5092 operand eRegP() %{
5093 constraint(ALLOC_IN_RC(e_reg));
5094 match(RegP);
5095 match(eAXRegP);
5096 match(eBXRegP);
5097 match(eCXRegP);
5098 match(eDIRegP);
5100 format %{ %}
5101 interface(REG_INTER);
5102 %}
5104 // On windows95, EBP is not safe to use for implicit null tests.
5105 operand eRegP_no_EBP() %{
5106 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5107 match(RegP);
5108 match(eAXRegP);
5109 match(eBXRegP);
5110 match(eCXRegP);
5111 match(eDIRegP);
5113 op_cost(100);
5114 format %{ %}
5115 interface(REG_INTER);
5116 %}
5118 operand naxRegP() %{
5119 constraint(ALLOC_IN_RC(nax_reg));
5120 match(RegP);
5121 match(eBXRegP);
5122 match(eDXRegP);
5123 match(eCXRegP);
5124 match(eSIRegP);
5125 match(eDIRegP);
5127 format %{ %}
5128 interface(REG_INTER);
5129 %}
5131 operand nabxRegP() %{
5132 constraint(ALLOC_IN_RC(nabx_reg));
5133 match(RegP);
5134 match(eCXRegP);
5135 match(eDXRegP);
5136 match(eSIRegP);
5137 match(eDIRegP);
5139 format %{ %}
5140 interface(REG_INTER);
5141 %}
5143 operand pRegP() %{
5144 constraint(ALLOC_IN_RC(p_reg));
5145 match(RegP);
5146 match(eBXRegP);
5147 match(eDXRegP);
5148 match(eSIRegP);
5149 match(eDIRegP);
5151 format %{ %}
5152 interface(REG_INTER);
5153 %}
5155 // Special Registers
5156 // Return a pointer value
5157 operand eAXRegP(eRegP reg) %{
5158 constraint(ALLOC_IN_RC(eax_reg));
5159 match(reg);
5160 format %{ "EAX" %}
5161 interface(REG_INTER);
5162 %}
5164 // Used in AtomicAdd
5165 operand eBXRegP(eRegP reg) %{
5166 constraint(ALLOC_IN_RC(ebx_reg));
5167 match(reg);
5168 format %{ "EBX" %}
5169 interface(REG_INTER);
5170 %}
5172 // Tail-call (interprocedural jump) to interpreter
5173 operand eCXRegP(eRegP reg) %{
5174 constraint(ALLOC_IN_RC(ecx_reg));
5175 match(reg);
5176 format %{ "ECX" %}
5177 interface(REG_INTER);
5178 %}
5180 operand eSIRegP(eRegP reg) %{
5181 constraint(ALLOC_IN_RC(esi_reg));
5182 match(reg);
5183 format %{ "ESI" %}
5184 interface(REG_INTER);
5185 %}
5187 // Used in rep stosw
5188 operand eDIRegP(eRegP reg) %{
5189 constraint(ALLOC_IN_RC(edi_reg));
5190 match(reg);
5191 format %{ "EDI" %}
5192 interface(REG_INTER);
5193 %}
5195 operand eBPRegP() %{
5196 constraint(ALLOC_IN_RC(ebp_reg));
5197 match(RegP);
5198 format %{ "EBP" %}
5199 interface(REG_INTER);
5200 %}
5202 operand eRegL() %{
5203 constraint(ALLOC_IN_RC(long_reg));
5204 match(RegL);
5205 match(eADXRegL);
5207 format %{ %}
5208 interface(REG_INTER);
5209 %}
5211 operand eADXRegL( eRegL reg ) %{
5212 constraint(ALLOC_IN_RC(eadx_reg));
5213 match(reg);
5215 format %{ "EDX:EAX" %}
5216 interface(REG_INTER);
5217 %}
5219 operand eBCXRegL( eRegL reg ) %{
5220 constraint(ALLOC_IN_RC(ebcx_reg));
5221 match(reg);
5223 format %{ "EBX:ECX" %}
5224 interface(REG_INTER);
5225 %}
5227 // Special case for integer high multiply
5228 operand eADXRegL_low_only() %{
5229 constraint(ALLOC_IN_RC(eadx_reg));
5230 match(RegL);
5232 format %{ "EAX" %}
5233 interface(REG_INTER);
5234 %}
5236 // Flags register, used as output of compare instructions
5237 operand eFlagsReg() %{
5238 constraint(ALLOC_IN_RC(int_flags));
5239 match(RegFlags);
5241 format %{ "EFLAGS" %}
5242 interface(REG_INTER);
5243 %}
5245 // Flags register, used as output of FLOATING POINT compare instructions
5246 operand eFlagsRegU() %{
5247 constraint(ALLOC_IN_RC(int_flags));
5248 match(RegFlags);
5250 format %{ "EFLAGS_U" %}
5251 interface(REG_INTER);
5252 %}
5254 operand eFlagsRegUCF() %{
5255 constraint(ALLOC_IN_RC(int_flags));
5256 match(RegFlags);
5257 predicate(false);
5259 format %{ "EFLAGS_U_CF" %}
5260 interface(REG_INTER);
5261 %}
5263 // Condition Code Register used by long compare
5264 operand flagsReg_long_LTGE() %{
5265 constraint(ALLOC_IN_RC(int_flags));
5266 match(RegFlags);
5267 format %{ "FLAGS_LTGE" %}
5268 interface(REG_INTER);
5269 %}
5270 operand flagsReg_long_EQNE() %{
5271 constraint(ALLOC_IN_RC(int_flags));
5272 match(RegFlags);
5273 format %{ "FLAGS_EQNE" %}
5274 interface(REG_INTER);
5275 %}
5276 operand flagsReg_long_LEGT() %{
5277 constraint(ALLOC_IN_RC(int_flags));
5278 match(RegFlags);
5279 format %{ "FLAGS_LEGT" %}
5280 interface(REG_INTER);
5281 %}
5283 // Float register operands
5284 operand regD() %{
5285 predicate( UseSSE < 2 );
5286 constraint(ALLOC_IN_RC(dbl_reg));
5287 match(RegD);
5288 match(regDPR1);
5289 match(regDPR2);
5290 format %{ %}
5291 interface(REG_INTER);
5292 %}
5294 operand regDPR1(regD reg) %{
5295 predicate( UseSSE < 2 );
5296 constraint(ALLOC_IN_RC(dbl_reg0));
5297 match(reg);
5298 format %{ "FPR1" %}
5299 interface(REG_INTER);
5300 %}
5302 operand regDPR2(regD reg) %{
5303 predicate( UseSSE < 2 );
5304 constraint(ALLOC_IN_RC(dbl_reg1));
5305 match(reg);
5306 format %{ "FPR2" %}
5307 interface(REG_INTER);
5308 %}
5310 operand regnotDPR1(regD reg) %{
5311 predicate( UseSSE < 2 );
5312 constraint(ALLOC_IN_RC(dbl_notreg0));
5313 match(reg);
5314 format %{ %}
5315 interface(REG_INTER);
5316 %}
5318 // XMM Double register operands
5319 operand regXD() %{
5320 predicate( UseSSE>=2 );
5321 constraint(ALLOC_IN_RC(xdb_reg));
5322 match(RegD);
5323 match(regXD6);
5324 match(regXD7);
5325 format %{ %}
5326 interface(REG_INTER);
5327 %}
5329 // XMM6 double register operands
5330 operand regXD6(regXD reg) %{
5331 predicate( UseSSE>=2 );
5332 constraint(ALLOC_IN_RC(xdb_reg6));
5333 match(reg);
5334 format %{ "XMM6" %}
5335 interface(REG_INTER);
5336 %}
5338 // XMM7 double register operands
5339 operand regXD7(regXD reg) %{
5340 predicate( UseSSE>=2 );
5341 constraint(ALLOC_IN_RC(xdb_reg7));
5342 match(reg);
5343 format %{ "XMM7" %}
5344 interface(REG_INTER);
5345 %}
5347 // Float register operands
5348 operand regF() %{
5349 predicate( UseSSE < 2 );
5350 constraint(ALLOC_IN_RC(flt_reg));
5351 match(RegF);
5352 match(regFPR1);
5353 format %{ %}
5354 interface(REG_INTER);
5355 %}
5357 // Float register operands
5358 operand regFPR1(regF reg) %{
5359 predicate( UseSSE < 2 );
5360 constraint(ALLOC_IN_RC(flt_reg0));
5361 match(reg);
5362 format %{ "FPR1" %}
5363 interface(REG_INTER);
5364 %}
5366 // XMM register operands
5367 operand regX() %{
5368 predicate( UseSSE>=1 );
5369 constraint(ALLOC_IN_RC(xmm_reg));
5370 match(RegF);
5371 format %{ %}
5372 interface(REG_INTER);
5373 %}
5376 //----------Memory Operands----------------------------------------------------
5377 // Direct Memory Operand
5378 operand direct(immP addr) %{
5379 match(addr);
5381 format %{ "[$addr]" %}
5382 interface(MEMORY_INTER) %{
5383 base(0xFFFFFFFF);
5384 index(0x4);
5385 scale(0x0);
5386 disp($addr);
5387 %}
5388 %}
5390 // Indirect Memory Operand
5391 operand indirect(eRegP reg) %{
5392 constraint(ALLOC_IN_RC(e_reg));
5393 match(reg);
5395 format %{ "[$reg]" %}
5396 interface(MEMORY_INTER) %{
5397 base($reg);
5398 index(0x4);
5399 scale(0x0);
5400 disp(0x0);
5401 %}
5402 %}
5404 // Indirect Memory Plus Short Offset Operand
5405 operand indOffset8(eRegP reg, immI8 off) %{
5406 match(AddP reg off);
5408 format %{ "[$reg + $off]" %}
5409 interface(MEMORY_INTER) %{
5410 base($reg);
5411 index(0x4);
5412 scale(0x0);
5413 disp($off);
5414 %}
5415 %}
5417 // Indirect Memory Plus Long Offset Operand
5418 operand indOffset32(eRegP reg, immI off) %{
5419 match(AddP reg off);
5421 format %{ "[$reg + $off]" %}
5422 interface(MEMORY_INTER) %{
5423 base($reg);
5424 index(0x4);
5425 scale(0x0);
5426 disp($off);
5427 %}
5428 %}
5430 // Indirect Memory Plus Long Offset Operand
5431 operand indOffset32X(eRegI reg, immP off) %{
5432 match(AddP off reg);
5434 format %{ "[$reg + $off]" %}
5435 interface(MEMORY_INTER) %{
5436 base($reg);
5437 index(0x4);
5438 scale(0x0);
5439 disp($off);
5440 %}
5441 %}
5443 // Indirect Memory Plus Index Register Plus Offset Operand
5444 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5445 match(AddP (AddP reg ireg) off);
5447 op_cost(10);
5448 format %{"[$reg + $off + $ireg]" %}
5449 interface(MEMORY_INTER) %{
5450 base($reg);
5451 index($ireg);
5452 scale(0x0);
5453 disp($off);
5454 %}
5455 %}
5457 // Indirect Memory Plus Index Register Plus Offset Operand
5458 operand indIndex(eRegP reg, eRegI ireg) %{
5459 match(AddP reg ireg);
5461 op_cost(10);
5462 format %{"[$reg + $ireg]" %}
5463 interface(MEMORY_INTER) %{
5464 base($reg);
5465 index($ireg);
5466 scale(0x0);
5467 disp(0x0);
5468 %}
5469 %}
5471 // // -------------------------------------------------------------------------
5472 // // 486 architecture doesn't support "scale * index + offset" with out a base
5473 // // -------------------------------------------------------------------------
5474 // // Scaled Memory Operands
5475 // // Indirect Memory Times Scale Plus Offset Operand
5476 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5477 // match(AddP off (LShiftI ireg scale));
5478 //
5479 // op_cost(10);
5480 // format %{"[$off + $ireg << $scale]" %}
5481 // interface(MEMORY_INTER) %{
5482 // base(0x4);
5483 // index($ireg);
5484 // scale($scale);
5485 // disp($off);
5486 // %}
5487 // %}
5489 // Indirect Memory Times Scale Plus Index Register
5490 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5491 match(AddP reg (LShiftI ireg scale));
5493 op_cost(10);
5494 format %{"[$reg + $ireg << $scale]" %}
5495 interface(MEMORY_INTER) %{
5496 base($reg);
5497 index($ireg);
5498 scale($scale);
5499 disp(0x0);
5500 %}
5501 %}
5503 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5504 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5505 match(AddP (AddP reg (LShiftI ireg scale)) off);
5507 op_cost(10);
5508 format %{"[$reg + $off + $ireg << $scale]" %}
5509 interface(MEMORY_INTER) %{
5510 base($reg);
5511 index($ireg);
5512 scale($scale);
5513 disp($off);
5514 %}
5515 %}
5517 //----------Load Long Memory Operands------------------------------------------
5518 // The load-long idiom will use it's address expression again after loading
5519 // the first word of the long. If the load-long destination overlaps with
5520 // registers used in the addressing expression, the 2nd half will be loaded
5521 // from a clobbered address. Fix this by requiring that load-long use
5522 // address registers that do not overlap with the load-long target.
5524 // load-long support
5525 operand load_long_RegP() %{
5526 constraint(ALLOC_IN_RC(esi_reg));
5527 match(RegP);
5528 match(eSIRegP);
5529 op_cost(100);
5530 format %{ %}
5531 interface(REG_INTER);
5532 %}
5534 // Indirect Memory Operand Long
5535 operand load_long_indirect(load_long_RegP reg) %{
5536 constraint(ALLOC_IN_RC(esi_reg));
5537 match(reg);
5539 format %{ "[$reg]" %}
5540 interface(MEMORY_INTER) %{
5541 base($reg);
5542 index(0x4);
5543 scale(0x0);
5544 disp(0x0);
5545 %}
5546 %}
5548 // Indirect Memory Plus Long Offset Operand
5549 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5550 match(AddP reg off);
5552 format %{ "[$reg + $off]" %}
5553 interface(MEMORY_INTER) %{
5554 base($reg);
5555 index(0x4);
5556 scale(0x0);
5557 disp($off);
5558 %}
5559 %}
5561 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5564 //----------Special Memory Operands--------------------------------------------
5565 // Stack Slot Operand - This operand is used for loading and storing temporary
5566 // values on the stack where a match requires a value to
5567 // flow through memory.
5568 operand stackSlotP(sRegP reg) %{
5569 constraint(ALLOC_IN_RC(stack_slots));
5570 // No match rule because this operand is only generated in matching
5571 format %{ "[$reg]" %}
5572 interface(MEMORY_INTER) %{
5573 base(0x4); // ESP
5574 index(0x4); // No Index
5575 scale(0x0); // No Scale
5576 disp($reg); // Stack Offset
5577 %}
5578 %}
5580 operand stackSlotI(sRegI reg) %{
5581 constraint(ALLOC_IN_RC(stack_slots));
5582 // No match rule because this operand is only generated in matching
5583 format %{ "[$reg]" %}
5584 interface(MEMORY_INTER) %{
5585 base(0x4); // ESP
5586 index(0x4); // No Index
5587 scale(0x0); // No Scale
5588 disp($reg); // Stack Offset
5589 %}
5590 %}
5592 operand stackSlotF(sRegF reg) %{
5593 constraint(ALLOC_IN_RC(stack_slots));
5594 // No match rule because this operand is only generated in matching
5595 format %{ "[$reg]" %}
5596 interface(MEMORY_INTER) %{
5597 base(0x4); // ESP
5598 index(0x4); // No Index
5599 scale(0x0); // No Scale
5600 disp($reg); // Stack Offset
5601 %}
5602 %}
5604 operand stackSlotD(sRegD reg) %{
5605 constraint(ALLOC_IN_RC(stack_slots));
5606 // No match rule because this operand is only generated in matching
5607 format %{ "[$reg]" %}
5608 interface(MEMORY_INTER) %{
5609 base(0x4); // ESP
5610 index(0x4); // No Index
5611 scale(0x0); // No Scale
5612 disp($reg); // Stack Offset
5613 %}
5614 %}
5616 operand stackSlotL(sRegL reg) %{
5617 constraint(ALLOC_IN_RC(stack_slots));
5618 // No match rule because this operand is only generated in matching
5619 format %{ "[$reg]" %}
5620 interface(MEMORY_INTER) %{
5621 base(0x4); // ESP
5622 index(0x4); // No Index
5623 scale(0x0); // No Scale
5624 disp($reg); // Stack Offset
5625 %}
5626 %}
5628 //----------Memory Operands - Win95 Implicit Null Variants----------------
5629 // Indirect Memory Operand
5630 operand indirect_win95_safe(eRegP_no_EBP reg)
5631 %{
5632 constraint(ALLOC_IN_RC(e_reg));
5633 match(reg);
5635 op_cost(100);
5636 format %{ "[$reg]" %}
5637 interface(MEMORY_INTER) %{
5638 base($reg);
5639 index(0x4);
5640 scale(0x0);
5641 disp(0x0);
5642 %}
5643 %}
5645 // Indirect Memory Plus Short Offset Operand
5646 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5647 %{
5648 match(AddP reg off);
5650 op_cost(100);
5651 format %{ "[$reg + $off]" %}
5652 interface(MEMORY_INTER) %{
5653 base($reg);
5654 index(0x4);
5655 scale(0x0);
5656 disp($off);
5657 %}
5658 %}
5660 // Indirect Memory Plus Long Offset Operand
5661 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5662 %{
5663 match(AddP reg off);
5665 op_cost(100);
5666 format %{ "[$reg + $off]" %}
5667 interface(MEMORY_INTER) %{
5668 base($reg);
5669 index(0x4);
5670 scale(0x0);
5671 disp($off);
5672 %}
5673 %}
5675 // Indirect Memory Plus Index Register Plus Offset Operand
5676 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5677 %{
5678 match(AddP (AddP reg ireg) off);
5680 op_cost(100);
5681 format %{"[$reg + $off + $ireg]" %}
5682 interface(MEMORY_INTER) %{
5683 base($reg);
5684 index($ireg);
5685 scale(0x0);
5686 disp($off);
5687 %}
5688 %}
5690 // Indirect Memory Times Scale Plus Index Register
5691 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5692 %{
5693 match(AddP reg (LShiftI ireg scale));
5695 op_cost(100);
5696 format %{"[$reg + $ireg << $scale]" %}
5697 interface(MEMORY_INTER) %{
5698 base($reg);
5699 index($ireg);
5700 scale($scale);
5701 disp(0x0);
5702 %}
5703 %}
5705 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5706 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5707 %{
5708 match(AddP (AddP reg (LShiftI ireg scale)) off);
5710 op_cost(100);
5711 format %{"[$reg + $off + $ireg << $scale]" %}
5712 interface(MEMORY_INTER) %{
5713 base($reg);
5714 index($ireg);
5715 scale($scale);
5716 disp($off);
5717 %}
5718 %}
5720 //----------Conditional Branch Operands----------------------------------------
5721 // Comparison Op - This is the operation of the comparison, and is limited to
5722 // the following set of codes:
5723 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5724 //
5725 // Other attributes of the comparison, such as unsignedness, are specified
5726 // by the comparison instruction that sets a condition code flags register.
5727 // That result is represented by a flags operand whose subtype is appropriate
5728 // to the unsignedness (etc.) of the comparison.
5729 //
5730 // Later, the instruction which matches both the Comparison Op (a Bool) and
5731 // the flags (produced by the Cmp) specifies the coding of the comparison op
5732 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5734 // Comparision Code
5735 operand cmpOp() %{
5736 match(Bool);
5738 format %{ "" %}
5739 interface(COND_INTER) %{
5740 equal(0x4, "e");
5741 not_equal(0x5, "ne");
5742 less(0xC, "l");
5743 greater_equal(0xD, "ge");
5744 less_equal(0xE, "le");
5745 greater(0xF, "g");
5746 %}
5747 %}
5749 // Comparison Code, unsigned compare. Used by FP also, with
5750 // C2 (unordered) turned into GT or LT already. The other bits
5751 // C0 and C3 are turned into Carry & Zero flags.
5752 operand cmpOpU() %{
5753 match(Bool);
5755 format %{ "" %}
5756 interface(COND_INTER) %{
5757 equal(0x4, "e");
5758 not_equal(0x5, "ne");
5759 less(0x2, "b");
5760 greater_equal(0x3, "nb");
5761 less_equal(0x6, "be");
5762 greater(0x7, "nbe");
5763 %}
5764 %}
5766 // Floating comparisons that don't require any fixup for the unordered case
5767 operand cmpOpUCF() %{
5768 match(Bool);
5769 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5770 n->as_Bool()->_test._test == BoolTest::ge ||
5771 n->as_Bool()->_test._test == BoolTest::le ||
5772 n->as_Bool()->_test._test == BoolTest::gt);
5773 format %{ "" %}
5774 interface(COND_INTER) %{
5775 equal(0x4, "e");
5776 not_equal(0x5, "ne");
5777 less(0x2, "b");
5778 greater_equal(0x3, "nb");
5779 less_equal(0x6, "be");
5780 greater(0x7, "nbe");
5781 %}
5782 %}
5785 // Floating comparisons that can be fixed up with extra conditional jumps
5786 operand cmpOpUCF2() %{
5787 match(Bool);
5788 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5789 n->as_Bool()->_test._test == BoolTest::eq);
5790 format %{ "" %}
5791 interface(COND_INTER) %{
5792 equal(0x4, "e");
5793 not_equal(0x5, "ne");
5794 less(0x2, "b");
5795 greater_equal(0x3, "nb");
5796 less_equal(0x6, "be");
5797 greater(0x7, "nbe");
5798 %}
5799 %}
5801 // Comparison Code for FP conditional move
5802 operand cmpOp_fcmov() %{
5803 match(Bool);
5805 format %{ "" %}
5806 interface(COND_INTER) %{
5807 equal (0x0C8);
5808 not_equal (0x1C8);
5809 less (0x0C0);
5810 greater_equal(0x1C0);
5811 less_equal (0x0D0);
5812 greater (0x1D0);
5813 %}
5814 %}
5816 // Comparision Code used in long compares
5817 operand cmpOp_commute() %{
5818 match(Bool);
5820 format %{ "" %}
5821 interface(COND_INTER) %{
5822 equal(0x4, "e");
5823 not_equal(0x5, "ne");
5824 less(0xF, "g");
5825 greater_equal(0xE, "le");
5826 less_equal(0xD, "ge");
5827 greater(0xC, "l");
5828 %}
5829 %}
5831 //----------OPERAND CLASSES----------------------------------------------------
5832 // Operand Classes are groups of operands that are used as to simplify
5833 // instruction definitions by not requiring the AD writer to specify separate
5834 // instructions for every form of operand when the instruction accepts
5835 // multiple operand types with the same basic encoding and format. The classic
5836 // case of this is memory operands.
5838 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5839 indIndex, indIndexScale, indIndexScaleOffset);
5841 // Long memory operations are encoded in 2 instructions and a +4 offset.
5842 // This means some kind of offset is always required and you cannot use
5843 // an oop as the offset (done when working on static globals).
5844 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5845 indIndex, indIndexScale, indIndexScaleOffset);
5848 //----------PIPELINE-----------------------------------------------------------
5849 // Rules which define the behavior of the target architectures pipeline.
5850 pipeline %{
5852 //----------ATTRIBUTES---------------------------------------------------------
5853 attributes %{
5854 variable_size_instructions; // Fixed size instructions
5855 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5856 instruction_unit_size = 1; // An instruction is 1 bytes long
5857 instruction_fetch_unit_size = 16; // The processor fetches one line
5858 instruction_fetch_units = 1; // of 16 bytes
5860 // List of nop instructions
5861 nops( MachNop );
5862 %}
5864 //----------RESOURCES----------------------------------------------------------
5865 // Resources are the functional units available to the machine
5867 // Generic P2/P3 pipeline
5868 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5869 // 3 instructions decoded per cycle.
5870 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5871 // 2 ALU op, only ALU0 handles mul/div instructions.
5872 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5873 MS0, MS1, MEM = MS0 | MS1,
5874 BR, FPU,
5875 ALU0, ALU1, ALU = ALU0 | ALU1 );
5877 //----------PIPELINE DESCRIPTION-----------------------------------------------
5878 // Pipeline Description specifies the stages in the machine's pipeline
5880 // Generic P2/P3 pipeline
5881 pipe_desc(S0, S1, S2, S3, S4, S5);
5883 //----------PIPELINE CLASSES---------------------------------------------------
5884 // Pipeline Classes describe the stages in which input and output are
5885 // referenced by the hardware pipeline.
5887 // Naming convention: ialu or fpu
5888 // Then: _reg
5889 // Then: _reg if there is a 2nd register
5890 // Then: _long if it's a pair of instructions implementing a long
5891 // Then: _fat if it requires the big decoder
5892 // Or: _mem if it requires the big decoder and a memory unit.
5894 // Integer ALU reg operation
5895 pipe_class ialu_reg(eRegI dst) %{
5896 single_instruction;
5897 dst : S4(write);
5898 dst : S3(read);
5899 DECODE : S0; // any decoder
5900 ALU : S3; // any alu
5901 %}
5903 // Long ALU reg operation
5904 pipe_class ialu_reg_long(eRegL dst) %{
5905 instruction_count(2);
5906 dst : S4(write);
5907 dst : S3(read);
5908 DECODE : S0(2); // any 2 decoders
5909 ALU : S3(2); // both alus
5910 %}
5912 // Integer ALU reg operation using big decoder
5913 pipe_class ialu_reg_fat(eRegI dst) %{
5914 single_instruction;
5915 dst : S4(write);
5916 dst : S3(read);
5917 D0 : S0; // big decoder only
5918 ALU : S3; // any alu
5919 %}
5921 // Long ALU reg operation using big decoder
5922 pipe_class ialu_reg_long_fat(eRegL dst) %{
5923 instruction_count(2);
5924 dst : S4(write);
5925 dst : S3(read);
5926 D0 : S0(2); // big decoder only; twice
5927 ALU : S3(2); // any 2 alus
5928 %}
5930 // Integer ALU reg-reg operation
5931 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5932 single_instruction;
5933 dst : S4(write);
5934 src : S3(read);
5935 DECODE : S0; // any decoder
5936 ALU : S3; // any alu
5937 %}
5939 // Long ALU reg-reg operation
5940 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5941 instruction_count(2);
5942 dst : S4(write);
5943 src : S3(read);
5944 DECODE : S0(2); // any 2 decoders
5945 ALU : S3(2); // both alus
5946 %}
5948 // Integer ALU reg-reg operation
5949 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5950 single_instruction;
5951 dst : S4(write);
5952 src : S3(read);
5953 D0 : S0; // big decoder only
5954 ALU : S3; // any alu
5955 %}
5957 // Long ALU reg-reg operation
5958 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5959 instruction_count(2);
5960 dst : S4(write);
5961 src : S3(read);
5962 D0 : S0(2); // big decoder only; twice
5963 ALU : S3(2); // both alus
5964 %}
5966 // Integer ALU reg-mem operation
5967 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5968 single_instruction;
5969 dst : S5(write);
5970 mem : S3(read);
5971 D0 : S0; // big decoder only
5972 ALU : S4; // any alu
5973 MEM : S3; // any mem
5974 %}
5976 // Long ALU reg-mem operation
5977 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5978 instruction_count(2);
5979 dst : S5(write);
5980 mem : S3(read);
5981 D0 : S0(2); // big decoder only; twice
5982 ALU : S4(2); // any 2 alus
5983 MEM : S3(2); // both mems
5984 %}
5986 // Integer mem operation (prefetch)
5987 pipe_class ialu_mem(memory mem)
5988 %{
5989 single_instruction;
5990 mem : S3(read);
5991 D0 : S0; // big decoder only
5992 MEM : S3; // any mem
5993 %}
5995 // Integer Store to Memory
5996 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5997 single_instruction;
5998 mem : S3(read);
5999 src : S5(read);
6000 D0 : S0; // big decoder only
6001 ALU : S4; // any alu
6002 MEM : S3;
6003 %}
6005 // Long Store to Memory
6006 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
6007 instruction_count(2);
6008 mem : S3(read);
6009 src : S5(read);
6010 D0 : S0(2); // big decoder only; twice
6011 ALU : S4(2); // any 2 alus
6012 MEM : S3(2); // Both mems
6013 %}
6015 // Integer Store to Memory
6016 pipe_class ialu_mem_imm(memory mem) %{
6017 single_instruction;
6018 mem : S3(read);
6019 D0 : S0; // big decoder only
6020 ALU : S4; // any alu
6021 MEM : S3;
6022 %}
6024 // Integer ALU0 reg-reg operation
6025 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6026 single_instruction;
6027 dst : S4(write);
6028 src : S3(read);
6029 D0 : S0; // Big decoder only
6030 ALU0 : S3; // only alu0
6031 %}
6033 // Integer ALU0 reg-mem operation
6034 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6035 single_instruction;
6036 dst : S5(write);
6037 mem : S3(read);
6038 D0 : S0; // big decoder only
6039 ALU0 : S4; // ALU0 only
6040 MEM : S3; // any mem
6041 %}
6043 // Integer ALU reg-reg operation
6044 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6045 single_instruction;
6046 cr : S4(write);
6047 src1 : S3(read);
6048 src2 : S3(read);
6049 DECODE : S0; // any decoder
6050 ALU : S3; // any alu
6051 %}
6053 // Integer ALU reg-imm operation
6054 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6055 single_instruction;
6056 cr : S4(write);
6057 src1 : S3(read);
6058 DECODE : S0; // any decoder
6059 ALU : S3; // any alu
6060 %}
6062 // Integer ALU reg-mem operation
6063 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6064 single_instruction;
6065 cr : S4(write);
6066 src1 : S3(read);
6067 src2 : S3(read);
6068 D0 : S0; // big decoder only
6069 ALU : S4; // any alu
6070 MEM : S3;
6071 %}
6073 // Conditional move reg-reg
6074 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6075 instruction_count(4);
6076 y : S4(read);
6077 q : S3(read);
6078 p : S3(read);
6079 DECODE : S0(4); // any decoder
6080 %}
6082 // Conditional move reg-reg
6083 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6084 single_instruction;
6085 dst : S4(write);
6086 src : S3(read);
6087 cr : S3(read);
6088 DECODE : S0; // any decoder
6089 %}
6091 // Conditional move reg-mem
6092 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6093 single_instruction;
6094 dst : S4(write);
6095 src : S3(read);
6096 cr : S3(read);
6097 DECODE : S0; // any decoder
6098 MEM : S3;
6099 %}
6101 // Conditional move reg-reg long
6102 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6103 single_instruction;
6104 dst : S4(write);
6105 src : S3(read);
6106 cr : S3(read);
6107 DECODE : S0(2); // any 2 decoders
6108 %}
6110 // Conditional move double reg-reg
6111 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6112 single_instruction;
6113 dst : S4(write);
6114 src : S3(read);
6115 cr : S3(read);
6116 DECODE : S0; // any decoder
6117 %}
6119 // Float reg-reg operation
6120 pipe_class fpu_reg(regD dst) %{
6121 instruction_count(2);
6122 dst : S3(read);
6123 DECODE : S0(2); // any 2 decoders
6124 FPU : S3;
6125 %}
6127 // Float reg-reg operation
6128 pipe_class fpu_reg_reg(regD dst, regD src) %{
6129 instruction_count(2);
6130 dst : S4(write);
6131 src : S3(read);
6132 DECODE : S0(2); // any 2 decoders
6133 FPU : S3;
6134 %}
6136 // Float reg-reg operation
6137 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6138 instruction_count(3);
6139 dst : S4(write);
6140 src1 : S3(read);
6141 src2 : S3(read);
6142 DECODE : S0(3); // any 3 decoders
6143 FPU : S3(2);
6144 %}
6146 // Float reg-reg operation
6147 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6148 instruction_count(4);
6149 dst : S4(write);
6150 src1 : S3(read);
6151 src2 : S3(read);
6152 src3 : S3(read);
6153 DECODE : S0(4); // any 3 decoders
6154 FPU : S3(2);
6155 %}
6157 // Float reg-reg operation
6158 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6159 instruction_count(4);
6160 dst : S4(write);
6161 src1 : S3(read);
6162 src2 : S3(read);
6163 src3 : S3(read);
6164 DECODE : S1(3); // any 3 decoders
6165 D0 : S0; // Big decoder only
6166 FPU : S3(2);
6167 MEM : S3;
6168 %}
6170 // Float reg-mem operation
6171 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6172 instruction_count(2);
6173 dst : S5(write);
6174 mem : S3(read);
6175 D0 : S0; // big decoder only
6176 DECODE : S1; // any decoder for FPU POP
6177 FPU : S4;
6178 MEM : S3; // any mem
6179 %}
6181 // Float reg-mem operation
6182 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6183 instruction_count(3);
6184 dst : S5(write);
6185 src1 : S3(read);
6186 mem : S3(read);
6187 D0 : S0; // big decoder only
6188 DECODE : S1(2); // any decoder for FPU POP
6189 FPU : S4;
6190 MEM : S3; // any mem
6191 %}
6193 // Float mem-reg operation
6194 pipe_class fpu_mem_reg(memory mem, regD src) %{
6195 instruction_count(2);
6196 src : S5(read);
6197 mem : S3(read);
6198 DECODE : S0; // any decoder for FPU PUSH
6199 D0 : S1; // big decoder only
6200 FPU : S4;
6201 MEM : S3; // any mem
6202 %}
6204 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6205 instruction_count(3);
6206 src1 : S3(read);
6207 src2 : S3(read);
6208 mem : S3(read);
6209 DECODE : S0(2); // any decoder for FPU PUSH
6210 D0 : S1; // big decoder only
6211 FPU : S4;
6212 MEM : S3; // any mem
6213 %}
6215 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6216 instruction_count(3);
6217 src1 : S3(read);
6218 src2 : S3(read);
6219 mem : S4(read);
6220 DECODE : S0; // any decoder for FPU PUSH
6221 D0 : S0(2); // big decoder only
6222 FPU : S4;
6223 MEM : S3(2); // any mem
6224 %}
6226 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6227 instruction_count(2);
6228 src1 : S3(read);
6229 dst : S4(read);
6230 D0 : S0(2); // big decoder only
6231 MEM : S3(2); // any mem
6232 %}
6234 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6235 instruction_count(3);
6236 src1 : S3(read);
6237 src2 : S3(read);
6238 dst : S4(read);
6239 D0 : S0(3); // big decoder only
6240 FPU : S4;
6241 MEM : S3(3); // any mem
6242 %}
6244 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6245 instruction_count(3);
6246 src1 : S4(read);
6247 mem : S4(read);
6248 DECODE : S0; // any decoder for FPU PUSH
6249 D0 : S0(2); // big decoder only
6250 FPU : S4;
6251 MEM : S3(2); // any mem
6252 %}
6254 // Float load constant
6255 pipe_class fpu_reg_con(regD dst) %{
6256 instruction_count(2);
6257 dst : S5(write);
6258 D0 : S0; // big decoder only for the load
6259 DECODE : S1; // any decoder for FPU POP
6260 FPU : S4;
6261 MEM : S3; // any mem
6262 %}
6264 // Float load constant
6265 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6266 instruction_count(3);
6267 dst : S5(write);
6268 src : S3(read);
6269 D0 : S0; // big decoder only for the load
6270 DECODE : S1(2); // any decoder for FPU POP
6271 FPU : S4;
6272 MEM : S3; // any mem
6273 %}
6275 // UnConditional branch
6276 pipe_class pipe_jmp( label labl ) %{
6277 single_instruction;
6278 BR : S3;
6279 %}
6281 // Conditional branch
6282 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6283 single_instruction;
6284 cr : S1(read);
6285 BR : S3;
6286 %}
6288 // Allocation idiom
6289 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6290 instruction_count(1); force_serialization;
6291 fixed_latency(6);
6292 heap_ptr : S3(read);
6293 DECODE : S0(3);
6294 D0 : S2;
6295 MEM : S3;
6296 ALU : S3(2);
6297 dst : S5(write);
6298 BR : S5;
6299 %}
6301 // Generic big/slow expanded idiom
6302 pipe_class pipe_slow( ) %{
6303 instruction_count(10); multiple_bundles; force_serialization;
6304 fixed_latency(100);
6305 D0 : S0(2);
6306 MEM : S3(2);
6307 %}
6309 // The real do-nothing guy
6310 pipe_class empty( ) %{
6311 instruction_count(0);
6312 %}
6314 // Define the class for the Nop node
6315 define %{
6316 MachNop = empty;
6317 %}
6319 %}
6321 //----------INSTRUCTIONS-------------------------------------------------------
6322 //
6323 // match -- States which machine-independent subtree may be replaced
6324 // by this instruction.
6325 // ins_cost -- The estimated cost of this instruction is used by instruction
6326 // selection to identify a minimum cost tree of machine
6327 // instructions that matches a tree of machine-independent
6328 // instructions.
6329 // format -- A string providing the disassembly for this instruction.
6330 // The value of an instruction's operand may be inserted
6331 // by referring to it with a '$' prefix.
6332 // opcode -- Three instruction opcodes may be provided. These are referred
6333 // to within an encode class as $primary, $secondary, and $tertiary
6334 // respectively. The primary opcode is commonly used to
6335 // indicate the type of machine instruction, while secondary
6336 // and tertiary are often used for prefix options or addressing
6337 // modes.
6338 // ins_encode -- A list of encode classes with parameters. The encode class
6339 // name must have been defined in an 'enc_class' specification
6340 // in the encode section of the architecture description.
6342 //----------BSWAP-Instruction--------------------------------------------------
6343 instruct bytes_reverse_int(eRegI dst) %{
6344 match(Set dst (ReverseBytesI dst));
6346 format %{ "BSWAP $dst" %}
6347 opcode(0x0F, 0xC8);
6348 ins_encode( OpcP, OpcSReg(dst) );
6349 ins_pipe( ialu_reg );
6350 %}
6352 instruct bytes_reverse_long(eRegL dst) %{
6353 match(Set dst (ReverseBytesL dst));
6355 format %{ "BSWAP $dst.lo\n\t"
6356 "BSWAP $dst.hi\n\t"
6357 "XCHG $dst.lo $dst.hi" %}
6359 ins_cost(125);
6360 ins_encode( bswap_long_bytes(dst) );
6361 ins_pipe( ialu_reg_reg);
6362 %}
6365 //---------- Population Count Instructions -------------------------------------
6367 instruct popCountI(eRegI dst, eRegI src) %{
6368 predicate(UsePopCountInstruction);
6369 match(Set dst (PopCountI src));
6371 format %{ "POPCNT $dst, $src" %}
6372 ins_encode %{
6373 __ popcntl($dst$$Register, $src$$Register);
6374 %}
6375 ins_pipe(ialu_reg);
6376 %}
6378 instruct popCountI_mem(eRegI dst, memory mem) %{
6379 predicate(UsePopCountInstruction);
6380 match(Set dst (PopCountI (LoadI mem)));
6382 format %{ "POPCNT $dst, $mem" %}
6383 ins_encode %{
6384 __ popcntl($dst$$Register, $mem$$Address);
6385 %}
6386 ins_pipe(ialu_reg);
6387 %}
6389 // Note: Long.bitCount(long) returns an int.
6390 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6391 predicate(UsePopCountInstruction);
6392 match(Set dst (PopCountL src));
6393 effect(KILL cr, TEMP tmp, TEMP dst);
6395 format %{ "POPCNT $dst, $src.lo\n\t"
6396 "POPCNT $tmp, $src.hi\n\t"
6397 "ADD $dst, $tmp" %}
6398 ins_encode %{
6399 __ popcntl($dst$$Register, $src$$Register);
6400 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6401 __ addl($dst$$Register, $tmp$$Register);
6402 %}
6403 ins_pipe(ialu_reg);
6404 %}
6406 // Note: Long.bitCount(long) returns an int.
6407 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6408 predicate(UsePopCountInstruction);
6409 match(Set dst (PopCountL (LoadL mem)));
6410 effect(KILL cr, TEMP tmp, TEMP dst);
6412 format %{ "POPCNT $dst, $mem\n\t"
6413 "POPCNT $tmp, $mem+4\n\t"
6414 "ADD $dst, $tmp" %}
6415 ins_encode %{
6416 //__ popcntl($dst$$Register, $mem$$Address$$first);
6417 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6418 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6419 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6420 __ addl($dst$$Register, $tmp$$Register);
6421 %}
6422 ins_pipe(ialu_reg);
6423 %}
6426 //----------Load/Store/Move Instructions---------------------------------------
6427 //----------Load Instructions--------------------------------------------------
6428 // Load Byte (8bit signed)
6429 instruct loadB(xRegI dst, memory mem) %{
6430 match(Set dst (LoadB mem));
6432 ins_cost(125);
6433 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6435 ins_encode %{
6436 __ movsbl($dst$$Register, $mem$$Address);
6437 %}
6439 ins_pipe(ialu_reg_mem);
6440 %}
6442 // Load Byte (8bit signed) into Long Register
6443 instruct loadB2L(eRegL dst, memory mem) %{
6444 match(Set dst (ConvI2L (LoadB mem)));
6446 ins_cost(375);
6447 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6448 "MOV $dst.hi,$dst.lo\n\t"
6449 "SAR $dst.hi,7" %}
6451 ins_encode %{
6452 __ movsbl($dst$$Register, $mem$$Address);
6453 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6454 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6455 %}
6457 ins_pipe(ialu_reg_mem);
6458 %}
6460 // Load Unsigned Byte (8bit UNsigned)
6461 instruct loadUB(xRegI dst, memory mem) %{
6462 match(Set dst (LoadUB mem));
6464 ins_cost(125);
6465 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6467 ins_encode %{
6468 __ movzbl($dst$$Register, $mem$$Address);
6469 %}
6471 ins_pipe(ialu_reg_mem);
6472 %}
6474 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6475 instruct loadUB2L(eRegL dst, memory mem)
6476 %{
6477 match(Set dst (ConvI2L (LoadUB mem)));
6479 ins_cost(250);
6480 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6481 "XOR $dst.hi,$dst.hi" %}
6483 ins_encode %{
6484 __ movzbl($dst$$Register, $mem$$Address);
6485 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6486 %}
6488 ins_pipe(ialu_reg_mem);
6489 %}
6491 // Load Short (16bit signed)
6492 instruct loadS(eRegI dst, memory mem) %{
6493 match(Set dst (LoadS mem));
6495 ins_cost(125);
6496 format %{ "MOVSX $dst,$mem\t# short" %}
6498 ins_encode %{
6499 __ movswl($dst$$Register, $mem$$Address);
6500 %}
6502 ins_pipe(ialu_reg_mem);
6503 %}
6505 // Load Short (16bit signed) into Long Register
6506 instruct loadS2L(eRegL dst, memory mem) %{
6507 match(Set dst (ConvI2L (LoadS mem)));
6509 ins_cost(375);
6510 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6511 "MOV $dst.hi,$dst.lo\n\t"
6512 "SAR $dst.hi,15" %}
6514 ins_encode %{
6515 __ movswl($dst$$Register, $mem$$Address);
6516 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6517 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6518 %}
6520 ins_pipe(ialu_reg_mem);
6521 %}
6523 // Load Unsigned Short/Char (16bit unsigned)
6524 instruct loadUS(eRegI dst, memory mem) %{
6525 match(Set dst (LoadUS mem));
6527 ins_cost(125);
6528 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6530 ins_encode %{
6531 __ movzwl($dst$$Register, $mem$$Address);
6532 %}
6534 ins_pipe(ialu_reg_mem);
6535 %}
6537 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6538 instruct loadUS2L(eRegL dst, memory mem)
6539 %{
6540 match(Set dst (ConvI2L (LoadUS mem)));
6542 ins_cost(250);
6543 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6544 "XOR $dst.hi,$dst.hi" %}
6546 ins_encode %{
6547 __ movzwl($dst$$Register, $mem$$Address);
6548 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6549 %}
6551 ins_pipe(ialu_reg_mem);
6552 %}
6554 // Load Integer
6555 instruct loadI(eRegI dst, memory mem) %{
6556 match(Set dst (LoadI mem));
6558 ins_cost(125);
6559 format %{ "MOV $dst,$mem\t# int" %}
6561 ins_encode %{
6562 __ movl($dst$$Register, $mem$$Address);
6563 %}
6565 ins_pipe(ialu_reg_mem);
6566 %}
6568 // Load Integer into Long Register
6569 instruct loadI2L(eRegL dst, memory mem) %{
6570 match(Set dst (ConvI2L (LoadI mem)));
6572 ins_cost(375);
6573 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6574 "MOV $dst.hi,$dst.lo\n\t"
6575 "SAR $dst.hi,31" %}
6577 ins_encode %{
6578 __ movl($dst$$Register, $mem$$Address);
6579 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6580 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6581 %}
6583 ins_pipe(ialu_reg_mem);
6584 %}
6586 // Load Unsigned Integer into Long Register
6587 instruct loadUI2L(eRegL dst, memory mem) %{
6588 match(Set dst (LoadUI2L mem));
6590 ins_cost(250);
6591 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6592 "XOR $dst.hi,$dst.hi" %}
6594 ins_encode %{
6595 __ movl($dst$$Register, $mem$$Address);
6596 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6597 %}
6599 ins_pipe(ialu_reg_mem);
6600 %}
6602 // Load Long. Cannot clobber address while loading, so restrict address
6603 // register to ESI
6604 instruct loadL(eRegL dst, load_long_memory mem) %{
6605 predicate(!((LoadLNode*)n)->require_atomic_access());
6606 match(Set dst (LoadL mem));
6608 ins_cost(250);
6609 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6610 "MOV $dst.hi,$mem+4" %}
6612 ins_encode %{
6613 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6614 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6615 __ movl($dst$$Register, Amemlo);
6616 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6617 %}
6619 ins_pipe(ialu_reg_long_mem);
6620 %}
6622 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6623 // then store it down to the stack and reload on the int
6624 // side.
6625 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6626 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6627 match(Set dst (LoadL mem));
6629 ins_cost(200);
6630 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6631 "FISTp $dst" %}
6632 ins_encode(enc_loadL_volatile(mem,dst));
6633 ins_pipe( fpu_reg_mem );
6634 %}
6636 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6637 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6638 match(Set dst (LoadL mem));
6639 effect(TEMP tmp);
6640 ins_cost(180);
6641 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6642 "MOVSD $dst,$tmp" %}
6643 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6644 ins_pipe( pipe_slow );
6645 %}
6647 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6648 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6649 match(Set dst (LoadL mem));
6650 effect(TEMP tmp);
6651 ins_cost(160);
6652 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6653 "MOVD $dst.lo,$tmp\n\t"
6654 "PSRLQ $tmp,32\n\t"
6655 "MOVD $dst.hi,$tmp" %}
6656 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6657 ins_pipe( pipe_slow );
6658 %}
6660 // Load Range
6661 instruct loadRange(eRegI dst, memory mem) %{
6662 match(Set dst (LoadRange mem));
6664 ins_cost(125);
6665 format %{ "MOV $dst,$mem" %}
6666 opcode(0x8B);
6667 ins_encode( OpcP, RegMem(dst,mem));
6668 ins_pipe( ialu_reg_mem );
6669 %}
6672 // Load Pointer
6673 instruct loadP(eRegP dst, memory mem) %{
6674 match(Set dst (LoadP mem));
6676 ins_cost(125);
6677 format %{ "MOV $dst,$mem" %}
6678 opcode(0x8B);
6679 ins_encode( OpcP, RegMem(dst,mem));
6680 ins_pipe( ialu_reg_mem );
6681 %}
6683 // Load Klass Pointer
6684 instruct loadKlass(eRegP dst, memory mem) %{
6685 match(Set dst (LoadKlass mem));
6687 ins_cost(125);
6688 format %{ "MOV $dst,$mem" %}
6689 opcode(0x8B);
6690 ins_encode( OpcP, RegMem(dst,mem));
6691 ins_pipe( ialu_reg_mem );
6692 %}
6694 // Load Double
6695 instruct loadD(regD dst, memory mem) %{
6696 predicate(UseSSE<=1);
6697 match(Set dst (LoadD mem));
6699 ins_cost(150);
6700 format %{ "FLD_D ST,$mem\n\t"
6701 "FSTP $dst" %}
6702 opcode(0xDD); /* DD /0 */
6703 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6704 Pop_Reg_D(dst) );
6705 ins_pipe( fpu_reg_mem );
6706 %}
6708 // Load Double to XMM
6709 instruct loadXD(regXD dst, memory mem) %{
6710 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6711 match(Set dst (LoadD mem));
6712 ins_cost(145);
6713 format %{ "MOVSD $dst,$mem" %}
6714 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6715 ins_pipe( pipe_slow );
6716 %}
6718 instruct loadXD_partial(regXD dst, memory mem) %{
6719 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6720 match(Set dst (LoadD mem));
6721 ins_cost(145);
6722 format %{ "MOVLPD $dst,$mem" %}
6723 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6724 ins_pipe( pipe_slow );
6725 %}
6727 // Load to XMM register (single-precision floating point)
6728 // MOVSS instruction
6729 instruct loadX(regX dst, memory mem) %{
6730 predicate(UseSSE>=1);
6731 match(Set dst (LoadF mem));
6732 ins_cost(145);
6733 format %{ "MOVSS $dst,$mem" %}
6734 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6735 ins_pipe( pipe_slow );
6736 %}
6738 // Load Float
6739 instruct loadF(regF dst, memory mem) %{
6740 predicate(UseSSE==0);
6741 match(Set dst (LoadF mem));
6743 ins_cost(150);
6744 format %{ "FLD_S ST,$mem\n\t"
6745 "FSTP $dst" %}
6746 opcode(0xD9); /* D9 /0 */
6747 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6748 Pop_Reg_F(dst) );
6749 ins_pipe( fpu_reg_mem );
6750 %}
6752 // Load Aligned Packed Byte to XMM register
6753 instruct loadA8B(regXD dst, memory mem) %{
6754 predicate(UseSSE>=1);
6755 match(Set dst (Load8B mem));
6756 ins_cost(125);
6757 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6758 ins_encode( movq_ld(dst, mem));
6759 ins_pipe( pipe_slow );
6760 %}
6762 // Load Aligned Packed Short to XMM register
6763 instruct loadA4S(regXD dst, memory mem) %{
6764 predicate(UseSSE>=1);
6765 match(Set dst (Load4S mem));
6766 ins_cost(125);
6767 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6768 ins_encode( movq_ld(dst, mem));
6769 ins_pipe( pipe_slow );
6770 %}
6772 // Load Aligned Packed Char to XMM register
6773 instruct loadA4C(regXD dst, memory mem) %{
6774 predicate(UseSSE>=1);
6775 match(Set dst (Load4C mem));
6776 ins_cost(125);
6777 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6778 ins_encode( movq_ld(dst, mem));
6779 ins_pipe( pipe_slow );
6780 %}
6782 // Load Aligned Packed Integer to XMM register
6783 instruct load2IU(regXD dst, memory mem) %{
6784 predicate(UseSSE>=1);
6785 match(Set dst (Load2I mem));
6786 ins_cost(125);
6787 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6788 ins_encode( movq_ld(dst, mem));
6789 ins_pipe( pipe_slow );
6790 %}
6792 // Load Aligned Packed Single to XMM
6793 instruct loadA2F(regXD dst, memory mem) %{
6794 predicate(UseSSE>=1);
6795 match(Set dst (Load2F mem));
6796 ins_cost(145);
6797 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6798 ins_encode( movq_ld(dst, mem));
6799 ins_pipe( pipe_slow );
6800 %}
6802 // Load Effective Address
6803 instruct leaP8(eRegP dst, indOffset8 mem) %{
6804 match(Set dst mem);
6806 ins_cost(110);
6807 format %{ "LEA $dst,$mem" %}
6808 opcode(0x8D);
6809 ins_encode( OpcP, RegMem(dst,mem));
6810 ins_pipe( ialu_reg_reg_fat );
6811 %}
6813 instruct leaP32(eRegP dst, indOffset32 mem) %{
6814 match(Set dst mem);
6816 ins_cost(110);
6817 format %{ "LEA $dst,$mem" %}
6818 opcode(0x8D);
6819 ins_encode( OpcP, RegMem(dst,mem));
6820 ins_pipe( ialu_reg_reg_fat );
6821 %}
6823 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6824 match(Set dst mem);
6826 ins_cost(110);
6827 format %{ "LEA $dst,$mem" %}
6828 opcode(0x8D);
6829 ins_encode( OpcP, RegMem(dst,mem));
6830 ins_pipe( ialu_reg_reg_fat );
6831 %}
6833 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6834 match(Set dst mem);
6836 ins_cost(110);
6837 format %{ "LEA $dst,$mem" %}
6838 opcode(0x8D);
6839 ins_encode( OpcP, RegMem(dst,mem));
6840 ins_pipe( ialu_reg_reg_fat );
6841 %}
6843 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6844 match(Set dst mem);
6846 ins_cost(110);
6847 format %{ "LEA $dst,$mem" %}
6848 opcode(0x8D);
6849 ins_encode( OpcP, RegMem(dst,mem));
6850 ins_pipe( ialu_reg_reg_fat );
6851 %}
6853 // Load Constant
6854 instruct loadConI(eRegI dst, immI src) %{
6855 match(Set dst src);
6857 format %{ "MOV $dst,$src" %}
6858 ins_encode( LdImmI(dst, src) );
6859 ins_pipe( ialu_reg_fat );
6860 %}
6862 // Load Constant zero
6863 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6864 match(Set dst src);
6865 effect(KILL cr);
6867 ins_cost(50);
6868 format %{ "XOR $dst,$dst" %}
6869 opcode(0x33); /* + rd */
6870 ins_encode( OpcP, RegReg( dst, dst ) );
6871 ins_pipe( ialu_reg );
6872 %}
6874 instruct loadConP(eRegP dst, immP src) %{
6875 match(Set dst src);
6877 format %{ "MOV $dst,$src" %}
6878 opcode(0xB8); /* + rd */
6879 ins_encode( LdImmP(dst, src) );
6880 ins_pipe( ialu_reg_fat );
6881 %}
6883 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6884 match(Set dst src);
6885 effect(KILL cr);
6886 ins_cost(200);
6887 format %{ "MOV $dst.lo,$src.lo\n\t"
6888 "MOV $dst.hi,$src.hi" %}
6889 opcode(0xB8);
6890 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6891 ins_pipe( ialu_reg_long_fat );
6892 %}
6894 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6895 match(Set dst src);
6896 effect(KILL cr);
6897 ins_cost(150);
6898 format %{ "XOR $dst.lo,$dst.lo\n\t"
6899 "XOR $dst.hi,$dst.hi" %}
6900 opcode(0x33,0x33);
6901 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6902 ins_pipe( ialu_reg_long );
6903 %}
6905 // The instruction usage is guarded by predicate in operand immF().
6906 instruct loadConF(regF dst, immF src) %{
6907 match(Set dst src);
6908 ins_cost(125);
6910 format %{ "FLD_S ST,$src\n\t"
6911 "FSTP $dst" %}
6912 opcode(0xD9, 0x00); /* D9 /0 */
6913 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
6914 ins_pipe( fpu_reg_con );
6915 %}
6917 // The instruction usage is guarded by predicate in operand immXF().
6918 instruct loadConX(regX dst, immXF con) %{
6919 match(Set dst con);
6920 ins_cost(125);
6921 format %{ "MOVSS $dst,[$con]" %}
6922 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
6923 ins_pipe( pipe_slow );
6924 %}
6926 // The instruction usage is guarded by predicate in operand immXF0().
6927 instruct loadConX0(regX dst, immXF0 src) %{
6928 match(Set dst src);
6929 ins_cost(100);
6930 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6931 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6932 ins_pipe( pipe_slow );
6933 %}
6935 // The instruction usage is guarded by predicate in operand immD().
6936 instruct loadConD(regD dst, immD src) %{
6937 match(Set dst src);
6938 ins_cost(125);
6940 format %{ "FLD_D ST,$src\n\t"
6941 "FSTP $dst" %}
6942 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
6943 ins_pipe( fpu_reg_con );
6944 %}
6946 // The instruction usage is guarded by predicate in operand immXD().
6947 instruct loadConXD(regXD dst, immXD con) %{
6948 match(Set dst con);
6949 ins_cost(125);
6950 format %{ "MOVSD $dst,[$con]" %}
6951 ins_encode(load_conXD(dst, con));
6952 ins_pipe( pipe_slow );
6953 %}
6955 // The instruction usage is guarded by predicate in operand immXD0().
6956 instruct loadConXD0(regXD dst, immXD0 src) %{
6957 match(Set dst src);
6958 ins_cost(100);
6959 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6960 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6961 ins_pipe( pipe_slow );
6962 %}
6964 // Load Stack Slot
6965 instruct loadSSI(eRegI dst, stackSlotI src) %{
6966 match(Set dst src);
6967 ins_cost(125);
6969 format %{ "MOV $dst,$src" %}
6970 opcode(0x8B);
6971 ins_encode( OpcP, RegMem(dst,src));
6972 ins_pipe( ialu_reg_mem );
6973 %}
6975 instruct loadSSL(eRegL dst, stackSlotL src) %{
6976 match(Set dst src);
6978 ins_cost(200);
6979 format %{ "MOV $dst,$src.lo\n\t"
6980 "MOV $dst+4,$src.hi" %}
6981 opcode(0x8B, 0x8B);
6982 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6983 ins_pipe( ialu_mem_long_reg );
6984 %}
6986 // Load Stack Slot
6987 instruct loadSSP(eRegP dst, stackSlotP src) %{
6988 match(Set dst src);
6989 ins_cost(125);
6991 format %{ "MOV $dst,$src" %}
6992 opcode(0x8B);
6993 ins_encode( OpcP, RegMem(dst,src));
6994 ins_pipe( ialu_reg_mem );
6995 %}
6997 // Load Stack Slot
6998 instruct loadSSF(regF dst, stackSlotF src) %{
6999 match(Set dst src);
7000 ins_cost(125);
7002 format %{ "FLD_S $src\n\t"
7003 "FSTP $dst" %}
7004 opcode(0xD9); /* D9 /0, FLD m32real */
7005 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7006 Pop_Reg_F(dst) );
7007 ins_pipe( fpu_reg_mem );
7008 %}
7010 // Load Stack Slot
7011 instruct loadSSD(regD dst, stackSlotD src) %{
7012 match(Set dst src);
7013 ins_cost(125);
7015 format %{ "FLD_D $src\n\t"
7016 "FSTP $dst" %}
7017 opcode(0xDD); /* DD /0, FLD m64real */
7018 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7019 Pop_Reg_D(dst) );
7020 ins_pipe( fpu_reg_mem );
7021 %}
7023 // Prefetch instructions.
7024 // Must be safe to execute with invalid address (cannot fault).
7026 instruct prefetchr0( memory mem ) %{
7027 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7028 match(PrefetchRead mem);
7029 ins_cost(0);
7030 size(0);
7031 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7032 ins_encode();
7033 ins_pipe(empty);
7034 %}
7036 instruct prefetchr( memory mem ) %{
7037 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7038 match(PrefetchRead mem);
7039 ins_cost(100);
7041 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7042 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7043 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7044 ins_pipe(ialu_mem);
7045 %}
7047 instruct prefetchrNTA( memory mem ) %{
7048 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7049 match(PrefetchRead mem);
7050 ins_cost(100);
7052 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7053 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7054 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7055 ins_pipe(ialu_mem);
7056 %}
7058 instruct prefetchrT0( memory mem ) %{
7059 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7060 match(PrefetchRead mem);
7061 ins_cost(100);
7063 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7064 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7065 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7066 ins_pipe(ialu_mem);
7067 %}
7069 instruct prefetchrT2( memory mem ) %{
7070 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7071 match(PrefetchRead mem);
7072 ins_cost(100);
7074 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7075 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7076 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7077 ins_pipe(ialu_mem);
7078 %}
7080 instruct prefetchw0( memory mem ) %{
7081 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7082 match(PrefetchWrite mem);
7083 ins_cost(0);
7084 size(0);
7085 format %{ "Prefetch (non-SSE is empty encoding)" %}
7086 ins_encode();
7087 ins_pipe(empty);
7088 %}
7090 instruct prefetchw( memory mem ) %{
7091 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7092 match( PrefetchWrite mem );
7093 ins_cost(100);
7095 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7096 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7097 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7098 ins_pipe(ialu_mem);
7099 %}
7101 instruct prefetchwNTA( memory mem ) %{
7102 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7103 match(PrefetchWrite mem);
7104 ins_cost(100);
7106 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7107 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7108 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7109 ins_pipe(ialu_mem);
7110 %}
7112 instruct prefetchwT0( memory mem ) %{
7113 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7114 match(PrefetchWrite mem);
7115 ins_cost(100);
7117 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7118 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7119 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7120 ins_pipe(ialu_mem);
7121 %}
7123 instruct prefetchwT2( memory mem ) %{
7124 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7125 match(PrefetchWrite mem);
7126 ins_cost(100);
7128 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7129 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7130 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7131 ins_pipe(ialu_mem);
7132 %}
7134 //----------Store Instructions-------------------------------------------------
7136 // Store Byte
7137 instruct storeB(memory mem, xRegI src) %{
7138 match(Set mem (StoreB mem src));
7140 ins_cost(125);
7141 format %{ "MOV8 $mem,$src" %}
7142 opcode(0x88);
7143 ins_encode( OpcP, RegMem( src, mem ) );
7144 ins_pipe( ialu_mem_reg );
7145 %}
7147 // Store Char/Short
7148 instruct storeC(memory mem, eRegI src) %{
7149 match(Set mem (StoreC mem src));
7151 ins_cost(125);
7152 format %{ "MOV16 $mem,$src" %}
7153 opcode(0x89, 0x66);
7154 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7155 ins_pipe( ialu_mem_reg );
7156 %}
7158 // Store Integer
7159 instruct storeI(memory mem, eRegI src) %{
7160 match(Set mem (StoreI mem src));
7162 ins_cost(125);
7163 format %{ "MOV $mem,$src" %}
7164 opcode(0x89);
7165 ins_encode( OpcP, RegMem( src, mem ) );
7166 ins_pipe( ialu_mem_reg );
7167 %}
7169 // Store Long
7170 instruct storeL(long_memory mem, eRegL src) %{
7171 predicate(!((StoreLNode*)n)->require_atomic_access());
7172 match(Set mem (StoreL mem src));
7174 ins_cost(200);
7175 format %{ "MOV $mem,$src.lo\n\t"
7176 "MOV $mem+4,$src.hi" %}
7177 opcode(0x89, 0x89);
7178 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7179 ins_pipe( ialu_mem_long_reg );
7180 %}
7182 // Volatile Store Long. Must be atomic, so move it into
7183 // the FP TOS and then do a 64-bit FIST. Has to probe the
7184 // target address before the store (for null-ptr checks)
7185 // so the memory operand is used twice in the encoding.
7186 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7187 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7188 match(Set mem (StoreL mem src));
7189 effect( KILL cr );
7190 ins_cost(400);
7191 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7192 "FILD $src\n\t"
7193 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7194 opcode(0x3B);
7195 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7196 ins_pipe( fpu_reg_mem );
7197 %}
7199 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7200 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7201 match(Set mem (StoreL mem src));
7202 effect( TEMP tmp, KILL cr );
7203 ins_cost(380);
7204 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7205 "MOVSD $tmp,$src\n\t"
7206 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7207 opcode(0x3B);
7208 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7209 ins_pipe( pipe_slow );
7210 %}
7212 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7213 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7214 match(Set mem (StoreL mem src));
7215 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7216 ins_cost(360);
7217 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7218 "MOVD $tmp,$src.lo\n\t"
7219 "MOVD $tmp2,$src.hi\n\t"
7220 "PUNPCKLDQ $tmp,$tmp2\n\t"
7221 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7222 opcode(0x3B);
7223 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7224 ins_pipe( pipe_slow );
7225 %}
7227 // Store Pointer; for storing unknown oops and raw pointers
7228 instruct storeP(memory mem, anyRegP src) %{
7229 match(Set mem (StoreP mem src));
7231 ins_cost(125);
7232 format %{ "MOV $mem,$src" %}
7233 opcode(0x89);
7234 ins_encode( OpcP, RegMem( src, mem ) );
7235 ins_pipe( ialu_mem_reg );
7236 %}
7238 // Store Integer Immediate
7239 instruct storeImmI(memory mem, immI src) %{
7240 match(Set mem (StoreI mem src));
7242 ins_cost(150);
7243 format %{ "MOV $mem,$src" %}
7244 opcode(0xC7); /* C7 /0 */
7245 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7246 ins_pipe( ialu_mem_imm );
7247 %}
7249 // Store Short/Char Immediate
7250 instruct storeImmI16(memory mem, immI16 src) %{
7251 predicate(UseStoreImmI16);
7252 match(Set mem (StoreC mem src));
7254 ins_cost(150);
7255 format %{ "MOV16 $mem,$src" %}
7256 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7257 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7258 ins_pipe( ialu_mem_imm );
7259 %}
7261 // Store Pointer Immediate; null pointers or constant oops that do not
7262 // need card-mark barriers.
7263 instruct storeImmP(memory mem, immP src) %{
7264 match(Set mem (StoreP mem src));
7266 ins_cost(150);
7267 format %{ "MOV $mem,$src" %}
7268 opcode(0xC7); /* C7 /0 */
7269 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7270 ins_pipe( ialu_mem_imm );
7271 %}
7273 // Store Byte Immediate
7274 instruct storeImmB(memory mem, immI8 src) %{
7275 match(Set mem (StoreB mem src));
7277 ins_cost(150);
7278 format %{ "MOV8 $mem,$src" %}
7279 opcode(0xC6); /* C6 /0 */
7280 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7281 ins_pipe( ialu_mem_imm );
7282 %}
7284 // Store Aligned Packed Byte XMM register to memory
7285 instruct storeA8B(memory mem, regXD src) %{
7286 predicate(UseSSE>=1);
7287 match(Set mem (Store8B mem src));
7288 ins_cost(145);
7289 format %{ "MOVQ $mem,$src\t! packed8B" %}
7290 ins_encode( movq_st(mem, src));
7291 ins_pipe( pipe_slow );
7292 %}
7294 // Store Aligned Packed Char/Short XMM register to memory
7295 instruct storeA4C(memory mem, regXD src) %{
7296 predicate(UseSSE>=1);
7297 match(Set mem (Store4C mem src));
7298 ins_cost(145);
7299 format %{ "MOVQ $mem,$src\t! packed4C" %}
7300 ins_encode( movq_st(mem, src));
7301 ins_pipe( pipe_slow );
7302 %}
7304 // Store Aligned Packed Integer XMM register to memory
7305 instruct storeA2I(memory mem, regXD src) %{
7306 predicate(UseSSE>=1);
7307 match(Set mem (Store2I mem src));
7308 ins_cost(145);
7309 format %{ "MOVQ $mem,$src\t! packed2I" %}
7310 ins_encode( movq_st(mem, src));
7311 ins_pipe( pipe_slow );
7312 %}
7314 // Store CMS card-mark Immediate
7315 instruct storeImmCM(memory mem, immI8 src) %{
7316 match(Set mem (StoreCM mem src));
7318 ins_cost(150);
7319 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7320 opcode(0xC6); /* C6 /0 */
7321 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7322 ins_pipe( ialu_mem_imm );
7323 %}
7325 // Store Double
7326 instruct storeD( memory mem, regDPR1 src) %{
7327 predicate(UseSSE<=1);
7328 match(Set mem (StoreD mem src));
7330 ins_cost(100);
7331 format %{ "FST_D $mem,$src" %}
7332 opcode(0xDD); /* DD /2 */
7333 ins_encode( enc_FP_store(mem,src) );
7334 ins_pipe( fpu_mem_reg );
7335 %}
7337 // Store double does rounding on x86
7338 instruct storeD_rounded( memory mem, regDPR1 src) %{
7339 predicate(UseSSE<=1);
7340 match(Set mem (StoreD mem (RoundDouble src)));
7342 ins_cost(100);
7343 format %{ "FST_D $mem,$src\t# round" %}
7344 opcode(0xDD); /* DD /2 */
7345 ins_encode( enc_FP_store(mem,src) );
7346 ins_pipe( fpu_mem_reg );
7347 %}
7349 // Store XMM register to memory (double-precision floating points)
7350 // MOVSD instruction
7351 instruct storeXD(memory mem, regXD src) %{
7352 predicate(UseSSE>=2);
7353 match(Set mem (StoreD mem src));
7354 ins_cost(95);
7355 format %{ "MOVSD $mem,$src" %}
7356 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7357 ins_pipe( pipe_slow );
7358 %}
7360 // Store XMM register to memory (single-precision floating point)
7361 // MOVSS instruction
7362 instruct storeX(memory mem, regX src) %{
7363 predicate(UseSSE>=1);
7364 match(Set mem (StoreF mem src));
7365 ins_cost(95);
7366 format %{ "MOVSS $mem,$src" %}
7367 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7368 ins_pipe( pipe_slow );
7369 %}
7371 // Store Aligned Packed Single Float XMM register to memory
7372 instruct storeA2F(memory mem, regXD src) %{
7373 predicate(UseSSE>=1);
7374 match(Set mem (Store2F mem src));
7375 ins_cost(145);
7376 format %{ "MOVQ $mem,$src\t! packed2F" %}
7377 ins_encode( movq_st(mem, src));
7378 ins_pipe( pipe_slow );
7379 %}
7381 // Store Float
7382 instruct storeF( memory mem, regFPR1 src) %{
7383 predicate(UseSSE==0);
7384 match(Set mem (StoreF mem src));
7386 ins_cost(100);
7387 format %{ "FST_S $mem,$src" %}
7388 opcode(0xD9); /* D9 /2 */
7389 ins_encode( enc_FP_store(mem,src) );
7390 ins_pipe( fpu_mem_reg );
7391 %}
7393 // Store Float does rounding on x86
7394 instruct storeF_rounded( memory mem, regFPR1 src) %{
7395 predicate(UseSSE==0);
7396 match(Set mem (StoreF mem (RoundFloat src)));
7398 ins_cost(100);
7399 format %{ "FST_S $mem,$src\t# round" %}
7400 opcode(0xD9); /* D9 /2 */
7401 ins_encode( enc_FP_store(mem,src) );
7402 ins_pipe( fpu_mem_reg );
7403 %}
7405 // Store Float does rounding on x86
7406 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7407 predicate(UseSSE<=1);
7408 match(Set mem (StoreF mem (ConvD2F src)));
7410 ins_cost(100);
7411 format %{ "FST_S $mem,$src\t# D-round" %}
7412 opcode(0xD9); /* D9 /2 */
7413 ins_encode( enc_FP_store(mem,src) );
7414 ins_pipe( fpu_mem_reg );
7415 %}
7417 // Store immediate Float value (it is faster than store from FPU register)
7418 // The instruction usage is guarded by predicate in operand immF().
7419 instruct storeF_imm( memory mem, immF src) %{
7420 match(Set mem (StoreF mem src));
7422 ins_cost(50);
7423 format %{ "MOV $mem,$src\t# store float" %}
7424 opcode(0xC7); /* C7 /0 */
7425 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7426 ins_pipe( ialu_mem_imm );
7427 %}
7429 // Store immediate Float value (it is faster than store from XMM register)
7430 // The instruction usage is guarded by predicate in operand immXF().
7431 instruct storeX_imm( memory mem, immXF src) %{
7432 match(Set mem (StoreF mem src));
7434 ins_cost(50);
7435 format %{ "MOV $mem,$src\t# store float" %}
7436 opcode(0xC7); /* C7 /0 */
7437 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7438 ins_pipe( ialu_mem_imm );
7439 %}
7441 // Store Integer to stack slot
7442 instruct storeSSI(stackSlotI dst, eRegI src) %{
7443 match(Set dst src);
7445 ins_cost(100);
7446 format %{ "MOV $dst,$src" %}
7447 opcode(0x89);
7448 ins_encode( OpcPRegSS( dst, src ) );
7449 ins_pipe( ialu_mem_reg );
7450 %}
7452 // Store Integer to stack slot
7453 instruct storeSSP(stackSlotP dst, eRegP src) %{
7454 match(Set dst src);
7456 ins_cost(100);
7457 format %{ "MOV $dst,$src" %}
7458 opcode(0x89);
7459 ins_encode( OpcPRegSS( dst, src ) );
7460 ins_pipe( ialu_mem_reg );
7461 %}
7463 // Store Long to stack slot
7464 instruct storeSSL(stackSlotL dst, eRegL src) %{
7465 match(Set dst src);
7467 ins_cost(200);
7468 format %{ "MOV $dst,$src.lo\n\t"
7469 "MOV $dst+4,$src.hi" %}
7470 opcode(0x89, 0x89);
7471 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7472 ins_pipe( ialu_mem_long_reg );
7473 %}
7475 //----------MemBar Instructions-----------------------------------------------
7476 // Memory barrier flavors
7478 instruct membar_acquire() %{
7479 match(MemBarAcquire);
7480 ins_cost(400);
7482 size(0);
7483 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7484 ins_encode();
7485 ins_pipe(empty);
7486 %}
7488 instruct membar_acquire_lock() %{
7489 match(MemBarAcquire);
7490 predicate(Matcher::prior_fast_lock(n));
7491 ins_cost(0);
7493 size(0);
7494 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7495 ins_encode( );
7496 ins_pipe(empty);
7497 %}
7499 instruct membar_release() %{
7500 match(MemBarRelease);
7501 ins_cost(400);
7503 size(0);
7504 format %{ "MEMBAR-release ! (empty encoding)" %}
7505 ins_encode( );
7506 ins_pipe(empty);
7507 %}
7509 instruct membar_release_lock() %{
7510 match(MemBarRelease);
7511 predicate(Matcher::post_fast_unlock(n));
7512 ins_cost(0);
7514 size(0);
7515 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7516 ins_encode( );
7517 ins_pipe(empty);
7518 %}
7520 instruct membar_volatile(eFlagsReg cr) %{
7521 match(MemBarVolatile);
7522 effect(KILL cr);
7523 ins_cost(400);
7525 format %{
7526 $$template
7527 if (os::is_MP()) {
7528 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7529 } else {
7530 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7531 }
7532 %}
7533 ins_encode %{
7534 __ membar(Assembler::StoreLoad);
7535 %}
7536 ins_pipe(pipe_slow);
7537 %}
7539 instruct unnecessary_membar_volatile() %{
7540 match(MemBarVolatile);
7541 predicate(Matcher::post_store_load_barrier(n));
7542 ins_cost(0);
7544 size(0);
7545 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7546 ins_encode( );
7547 ins_pipe(empty);
7548 %}
7550 //----------Move Instructions--------------------------------------------------
7551 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7552 match(Set dst (CastX2P src));
7553 format %{ "# X2P $dst, $src" %}
7554 ins_encode( /*empty encoding*/ );
7555 ins_cost(0);
7556 ins_pipe(empty);
7557 %}
7559 instruct castP2X(eRegI dst, eRegP src ) %{
7560 match(Set dst (CastP2X src));
7561 ins_cost(50);
7562 format %{ "MOV $dst, $src\t# CastP2X" %}
7563 ins_encode( enc_Copy( dst, src) );
7564 ins_pipe( ialu_reg_reg );
7565 %}
7567 //----------Conditional Move---------------------------------------------------
7568 // Conditional move
7569 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7570 predicate(VM_Version::supports_cmov() );
7571 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7572 ins_cost(200);
7573 format %{ "CMOV$cop $dst,$src" %}
7574 opcode(0x0F,0x40);
7575 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7576 ins_pipe( pipe_cmov_reg );
7577 %}
7579 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7580 predicate(VM_Version::supports_cmov() );
7581 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7582 ins_cost(200);
7583 format %{ "CMOV$cop $dst,$src" %}
7584 opcode(0x0F,0x40);
7585 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7586 ins_pipe( pipe_cmov_reg );
7587 %}
7589 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7590 predicate(VM_Version::supports_cmov() );
7591 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7592 ins_cost(200);
7593 expand %{
7594 cmovI_regU(cop, cr, dst, src);
7595 %}
7596 %}
7598 // Conditional move
7599 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7600 predicate(VM_Version::supports_cmov() );
7601 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7602 ins_cost(250);
7603 format %{ "CMOV$cop $dst,$src" %}
7604 opcode(0x0F,0x40);
7605 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7606 ins_pipe( pipe_cmov_mem );
7607 %}
7609 // Conditional move
7610 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7611 predicate(VM_Version::supports_cmov() );
7612 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7613 ins_cost(250);
7614 format %{ "CMOV$cop $dst,$src" %}
7615 opcode(0x0F,0x40);
7616 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7617 ins_pipe( pipe_cmov_mem );
7618 %}
7620 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7621 predicate(VM_Version::supports_cmov() );
7622 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7623 ins_cost(250);
7624 expand %{
7625 cmovI_memU(cop, cr, dst, src);
7626 %}
7627 %}
7629 // Conditional move
7630 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7631 predicate(VM_Version::supports_cmov() );
7632 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7633 ins_cost(200);
7634 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7635 opcode(0x0F,0x40);
7636 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7637 ins_pipe( pipe_cmov_reg );
7638 %}
7640 // Conditional move (non-P6 version)
7641 // Note: a CMoveP is generated for stubs and native wrappers
7642 // regardless of whether we are on a P6, so we
7643 // emulate a cmov here
7644 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7645 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7646 ins_cost(300);
7647 format %{ "Jn$cop skip\n\t"
7648 "MOV $dst,$src\t# pointer\n"
7649 "skip:" %}
7650 opcode(0x8b);
7651 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7652 ins_pipe( pipe_cmov_reg );
7653 %}
7655 // Conditional move
7656 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7657 predicate(VM_Version::supports_cmov() );
7658 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7659 ins_cost(200);
7660 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7661 opcode(0x0F,0x40);
7662 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7663 ins_pipe( pipe_cmov_reg );
7664 %}
7666 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7667 predicate(VM_Version::supports_cmov() );
7668 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7669 ins_cost(200);
7670 expand %{
7671 cmovP_regU(cop, cr, dst, src);
7672 %}
7673 %}
7675 // DISABLED: Requires the ADLC to emit a bottom_type call that
7676 // correctly meets the two pointer arguments; one is an incoming
7677 // register but the other is a memory operand. ALSO appears to
7678 // be buggy with implicit null checks.
7679 //
7680 //// Conditional move
7681 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7682 // predicate(VM_Version::supports_cmov() );
7683 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7684 // ins_cost(250);
7685 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7686 // opcode(0x0F,0x40);
7687 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7688 // ins_pipe( pipe_cmov_mem );
7689 //%}
7690 //
7691 //// Conditional move
7692 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7693 // predicate(VM_Version::supports_cmov() );
7694 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7695 // ins_cost(250);
7696 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7697 // opcode(0x0F,0x40);
7698 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7699 // ins_pipe( pipe_cmov_mem );
7700 //%}
7702 // Conditional move
7703 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7704 predicate(UseSSE<=1);
7705 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7706 ins_cost(200);
7707 format %{ "FCMOV$cop $dst,$src\t# double" %}
7708 opcode(0xDA);
7709 ins_encode( enc_cmov_d(cop,src) );
7710 ins_pipe( pipe_cmovD_reg );
7711 %}
7713 // Conditional move
7714 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7715 predicate(UseSSE==0);
7716 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7717 ins_cost(200);
7718 format %{ "FCMOV$cop $dst,$src\t# float" %}
7719 opcode(0xDA);
7720 ins_encode( enc_cmov_d(cop,src) );
7721 ins_pipe( pipe_cmovD_reg );
7722 %}
7724 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7725 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7726 predicate(UseSSE<=1);
7727 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7728 ins_cost(200);
7729 format %{ "Jn$cop skip\n\t"
7730 "MOV $dst,$src\t# double\n"
7731 "skip:" %}
7732 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7733 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7734 ins_pipe( pipe_cmovD_reg );
7735 %}
7737 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7738 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7739 predicate(UseSSE==0);
7740 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7741 ins_cost(200);
7742 format %{ "Jn$cop skip\n\t"
7743 "MOV $dst,$src\t# float\n"
7744 "skip:" %}
7745 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7746 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7747 ins_pipe( pipe_cmovD_reg );
7748 %}
7750 // No CMOVE with SSE/SSE2
7751 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7752 predicate (UseSSE>=1);
7753 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7754 ins_cost(200);
7755 format %{ "Jn$cop skip\n\t"
7756 "MOVSS $dst,$src\t# float\n"
7757 "skip:" %}
7758 ins_encode %{
7759 Label skip;
7760 // Invert sense of branch from sense of CMOV
7761 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7762 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7763 __ bind(skip);
7764 %}
7765 ins_pipe( pipe_slow );
7766 %}
7768 // No CMOVE with SSE/SSE2
7769 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7770 predicate (UseSSE>=2);
7771 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7772 ins_cost(200);
7773 format %{ "Jn$cop skip\n\t"
7774 "MOVSD $dst,$src\t# float\n"
7775 "skip:" %}
7776 ins_encode %{
7777 Label skip;
7778 // Invert sense of branch from sense of CMOV
7779 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7780 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7781 __ bind(skip);
7782 %}
7783 ins_pipe( pipe_slow );
7784 %}
7786 // unsigned version
7787 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7788 predicate (UseSSE>=1);
7789 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7790 ins_cost(200);
7791 format %{ "Jn$cop skip\n\t"
7792 "MOVSS $dst,$src\t# float\n"
7793 "skip:" %}
7794 ins_encode %{
7795 Label skip;
7796 // Invert sense of branch from sense of CMOV
7797 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7798 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7799 __ bind(skip);
7800 %}
7801 ins_pipe( pipe_slow );
7802 %}
7804 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
7805 predicate (UseSSE>=1);
7806 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7807 ins_cost(200);
7808 expand %{
7809 fcmovX_regU(cop, cr, dst, src);
7810 %}
7811 %}
7813 // unsigned version
7814 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7815 predicate (UseSSE>=2);
7816 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7817 ins_cost(200);
7818 format %{ "Jn$cop skip\n\t"
7819 "MOVSD $dst,$src\t# float\n"
7820 "skip:" %}
7821 ins_encode %{
7822 Label skip;
7823 // Invert sense of branch from sense of CMOV
7824 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7825 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7826 __ bind(skip);
7827 %}
7828 ins_pipe( pipe_slow );
7829 %}
7831 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
7832 predicate (UseSSE>=2);
7833 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7834 ins_cost(200);
7835 expand %{
7836 fcmovXD_regU(cop, cr, dst, src);
7837 %}
7838 %}
7840 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7841 predicate(VM_Version::supports_cmov() );
7842 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7843 ins_cost(200);
7844 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7845 "CMOV$cop $dst.hi,$src.hi" %}
7846 opcode(0x0F,0x40);
7847 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7848 ins_pipe( pipe_cmov_reg_long );
7849 %}
7851 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7852 predicate(VM_Version::supports_cmov() );
7853 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7854 ins_cost(200);
7855 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7856 "CMOV$cop $dst.hi,$src.hi" %}
7857 opcode(0x0F,0x40);
7858 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7859 ins_pipe( pipe_cmov_reg_long );
7860 %}
7862 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7863 predicate(VM_Version::supports_cmov() );
7864 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7865 ins_cost(200);
7866 expand %{
7867 cmovL_regU(cop, cr, dst, src);
7868 %}
7869 %}
7871 //----------Arithmetic Instructions--------------------------------------------
7872 //----------Addition Instructions----------------------------------------------
7873 // Integer Addition Instructions
7874 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7875 match(Set dst (AddI dst src));
7876 effect(KILL cr);
7878 size(2);
7879 format %{ "ADD $dst,$src" %}
7880 opcode(0x03);
7881 ins_encode( OpcP, RegReg( dst, src) );
7882 ins_pipe( ialu_reg_reg );
7883 %}
7885 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7886 match(Set dst (AddI dst src));
7887 effect(KILL cr);
7889 format %{ "ADD $dst,$src" %}
7890 opcode(0x81, 0x00); /* /0 id */
7891 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7892 ins_pipe( ialu_reg );
7893 %}
7895 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7896 predicate(UseIncDec);
7897 match(Set dst (AddI dst src));
7898 effect(KILL cr);
7900 size(1);
7901 format %{ "INC $dst" %}
7902 opcode(0x40); /* */
7903 ins_encode( Opc_plus( primary, dst ) );
7904 ins_pipe( ialu_reg );
7905 %}
7907 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7908 match(Set dst (AddI src0 src1));
7909 ins_cost(110);
7911 format %{ "LEA $dst,[$src0 + $src1]" %}
7912 opcode(0x8D); /* 0x8D /r */
7913 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7914 ins_pipe( ialu_reg_reg );
7915 %}
7917 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7918 match(Set dst (AddP src0 src1));
7919 ins_cost(110);
7921 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7922 opcode(0x8D); /* 0x8D /r */
7923 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7924 ins_pipe( ialu_reg_reg );
7925 %}
7927 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7928 predicate(UseIncDec);
7929 match(Set dst (AddI dst src));
7930 effect(KILL cr);
7932 size(1);
7933 format %{ "DEC $dst" %}
7934 opcode(0x48); /* */
7935 ins_encode( Opc_plus( primary, dst ) );
7936 ins_pipe( ialu_reg );
7937 %}
7939 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7940 match(Set dst (AddP dst src));
7941 effect(KILL cr);
7943 size(2);
7944 format %{ "ADD $dst,$src" %}
7945 opcode(0x03);
7946 ins_encode( OpcP, RegReg( dst, src) );
7947 ins_pipe( ialu_reg_reg );
7948 %}
7950 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7951 match(Set dst (AddP dst src));
7952 effect(KILL cr);
7954 format %{ "ADD $dst,$src" %}
7955 opcode(0x81,0x00); /* Opcode 81 /0 id */
7956 // ins_encode( RegImm( dst, src) );
7957 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7958 ins_pipe( ialu_reg );
7959 %}
7961 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7962 match(Set dst (AddI dst (LoadI src)));
7963 effect(KILL cr);
7965 ins_cost(125);
7966 format %{ "ADD $dst,$src" %}
7967 opcode(0x03);
7968 ins_encode( OpcP, RegMem( dst, src) );
7969 ins_pipe( ialu_reg_mem );
7970 %}
7972 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7973 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7974 effect(KILL cr);
7976 ins_cost(150);
7977 format %{ "ADD $dst,$src" %}
7978 opcode(0x01); /* Opcode 01 /r */
7979 ins_encode( OpcP, RegMem( src, dst ) );
7980 ins_pipe( ialu_mem_reg );
7981 %}
7983 // Add Memory with Immediate
7984 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7985 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7986 effect(KILL cr);
7988 ins_cost(125);
7989 format %{ "ADD $dst,$src" %}
7990 opcode(0x81); /* Opcode 81 /0 id */
7991 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7992 ins_pipe( ialu_mem_imm );
7993 %}
7995 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7996 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7997 effect(KILL cr);
7999 ins_cost(125);
8000 format %{ "INC $dst" %}
8001 opcode(0xFF); /* Opcode FF /0 */
8002 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8003 ins_pipe( ialu_mem_imm );
8004 %}
8006 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8007 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8008 effect(KILL cr);
8010 ins_cost(125);
8011 format %{ "DEC $dst" %}
8012 opcode(0xFF); /* Opcode FF /1 */
8013 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8014 ins_pipe( ialu_mem_imm );
8015 %}
8018 instruct checkCastPP( eRegP dst ) %{
8019 match(Set dst (CheckCastPP dst));
8021 size(0);
8022 format %{ "#checkcastPP of $dst" %}
8023 ins_encode( /*empty encoding*/ );
8024 ins_pipe( empty );
8025 %}
8027 instruct castPP( eRegP dst ) %{
8028 match(Set dst (CastPP dst));
8029 format %{ "#castPP of $dst" %}
8030 ins_encode( /*empty encoding*/ );
8031 ins_pipe( empty );
8032 %}
8034 instruct castII( eRegI dst ) %{
8035 match(Set dst (CastII dst));
8036 format %{ "#castII of $dst" %}
8037 ins_encode( /*empty encoding*/ );
8038 ins_cost(0);
8039 ins_pipe( empty );
8040 %}
8043 // Load-locked - same as a regular pointer load when used with compare-swap
8044 instruct loadPLocked(eRegP dst, memory mem) %{
8045 match(Set dst (LoadPLocked mem));
8047 ins_cost(125);
8048 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8049 opcode(0x8B);
8050 ins_encode( OpcP, RegMem(dst,mem));
8051 ins_pipe( ialu_reg_mem );
8052 %}
8054 // LoadLong-locked - same as a volatile long load when used with compare-swap
8055 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8056 predicate(UseSSE<=1);
8057 match(Set dst (LoadLLocked mem));
8059 ins_cost(200);
8060 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8061 "FISTp $dst" %}
8062 ins_encode(enc_loadL_volatile(mem,dst));
8063 ins_pipe( fpu_reg_mem );
8064 %}
8066 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8067 predicate(UseSSE>=2);
8068 match(Set dst (LoadLLocked mem));
8069 effect(TEMP tmp);
8070 ins_cost(180);
8071 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8072 "MOVSD $dst,$tmp" %}
8073 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8074 ins_pipe( pipe_slow );
8075 %}
8077 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8078 predicate(UseSSE>=2);
8079 match(Set dst (LoadLLocked mem));
8080 effect(TEMP tmp);
8081 ins_cost(160);
8082 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8083 "MOVD $dst.lo,$tmp\n\t"
8084 "PSRLQ $tmp,32\n\t"
8085 "MOVD $dst.hi,$tmp" %}
8086 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8087 ins_pipe( pipe_slow );
8088 %}
8090 // Conditional-store of the updated heap-top.
8091 // Used during allocation of the shared heap.
8092 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8093 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8094 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8095 // EAX is killed if there is contention, but then it's also unused.
8096 // In the common case of no contention, EAX holds the new oop address.
8097 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8098 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8099 ins_pipe( pipe_cmpxchg );
8100 %}
8102 // Conditional-store of an int value.
8103 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8104 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8105 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8106 effect(KILL oldval);
8107 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8108 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8109 ins_pipe( pipe_cmpxchg );
8110 %}
8112 // Conditional-store of a long value.
8113 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8114 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8115 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8116 effect(KILL oldval);
8117 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8118 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8119 "XCHG EBX,ECX"
8120 %}
8121 ins_encode %{
8122 // Note: we need to swap rbx, and rcx before and after the
8123 // cmpxchg8 instruction because the instruction uses
8124 // rcx as the high order word of the new value to store but
8125 // our register encoding uses rbx.
8126 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8127 if( os::is_MP() )
8128 __ lock();
8129 __ cmpxchg8($mem$$Address);
8130 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8131 %}
8132 ins_pipe( pipe_cmpxchg );
8133 %}
8135 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8137 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8138 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8139 effect(KILL cr, KILL oldval);
8140 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8141 "MOV $res,0\n\t"
8142 "JNE,s fail\n\t"
8143 "MOV $res,1\n"
8144 "fail:" %}
8145 ins_encode( enc_cmpxchg8(mem_ptr),
8146 enc_flags_ne_to_boolean(res) );
8147 ins_pipe( pipe_cmpxchg );
8148 %}
8150 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8151 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8152 effect(KILL cr, KILL oldval);
8153 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8154 "MOV $res,0\n\t"
8155 "JNE,s fail\n\t"
8156 "MOV $res,1\n"
8157 "fail:" %}
8158 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8159 ins_pipe( pipe_cmpxchg );
8160 %}
8162 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8163 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8164 effect(KILL cr, KILL oldval);
8165 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8166 "MOV $res,0\n\t"
8167 "JNE,s fail\n\t"
8168 "MOV $res,1\n"
8169 "fail:" %}
8170 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8171 ins_pipe( pipe_cmpxchg );
8172 %}
8174 //----------Subtraction Instructions-------------------------------------------
8175 // Integer Subtraction Instructions
8176 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8177 match(Set dst (SubI dst src));
8178 effect(KILL cr);
8180 size(2);
8181 format %{ "SUB $dst,$src" %}
8182 opcode(0x2B);
8183 ins_encode( OpcP, RegReg( dst, src) );
8184 ins_pipe( ialu_reg_reg );
8185 %}
8187 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8188 match(Set dst (SubI dst src));
8189 effect(KILL cr);
8191 format %{ "SUB $dst,$src" %}
8192 opcode(0x81,0x05); /* Opcode 81 /5 */
8193 // ins_encode( RegImm( dst, src) );
8194 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8195 ins_pipe( ialu_reg );
8196 %}
8198 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8199 match(Set dst (SubI dst (LoadI src)));
8200 effect(KILL cr);
8202 ins_cost(125);
8203 format %{ "SUB $dst,$src" %}
8204 opcode(0x2B);
8205 ins_encode( OpcP, RegMem( dst, src) );
8206 ins_pipe( ialu_reg_mem );
8207 %}
8209 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8210 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8211 effect(KILL cr);
8213 ins_cost(150);
8214 format %{ "SUB $dst,$src" %}
8215 opcode(0x29); /* Opcode 29 /r */
8216 ins_encode( OpcP, RegMem( src, dst ) );
8217 ins_pipe( ialu_mem_reg );
8218 %}
8220 // Subtract from a pointer
8221 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8222 match(Set dst (AddP dst (SubI zero src)));
8223 effect(KILL cr);
8225 size(2);
8226 format %{ "SUB $dst,$src" %}
8227 opcode(0x2B);
8228 ins_encode( OpcP, RegReg( dst, src) );
8229 ins_pipe( ialu_reg_reg );
8230 %}
8232 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8233 match(Set dst (SubI zero dst));
8234 effect(KILL cr);
8236 size(2);
8237 format %{ "NEG $dst" %}
8238 opcode(0xF7,0x03); // Opcode F7 /3
8239 ins_encode( OpcP, RegOpc( dst ) );
8240 ins_pipe( ialu_reg );
8241 %}
8244 //----------Multiplication/Division Instructions-------------------------------
8245 // Integer Multiplication Instructions
8246 // Multiply Register
8247 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8248 match(Set dst (MulI dst src));
8249 effect(KILL cr);
8251 size(3);
8252 ins_cost(300);
8253 format %{ "IMUL $dst,$src" %}
8254 opcode(0xAF, 0x0F);
8255 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8256 ins_pipe( ialu_reg_reg_alu0 );
8257 %}
8259 // Multiply 32-bit Immediate
8260 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8261 match(Set dst (MulI src imm));
8262 effect(KILL cr);
8264 ins_cost(300);
8265 format %{ "IMUL $dst,$src,$imm" %}
8266 opcode(0x69); /* 69 /r id */
8267 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8268 ins_pipe( ialu_reg_reg_alu0 );
8269 %}
8271 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8272 match(Set dst src);
8273 effect(KILL cr);
8275 // Note that this is artificially increased to make it more expensive than loadConL
8276 ins_cost(250);
8277 format %{ "MOV EAX,$src\t// low word only" %}
8278 opcode(0xB8);
8279 ins_encode( LdImmL_Lo(dst, src) );
8280 ins_pipe( ialu_reg_fat );
8281 %}
8283 // Multiply by 32-bit Immediate, taking the shifted high order results
8284 // (special case for shift by 32)
8285 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8286 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8287 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8288 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8289 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8290 effect(USE src1, KILL cr);
8292 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8293 ins_cost(0*100 + 1*400 - 150);
8294 format %{ "IMUL EDX:EAX,$src1" %}
8295 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8296 ins_pipe( pipe_slow );
8297 %}
8299 // Multiply by 32-bit Immediate, taking the shifted high order results
8300 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8301 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8302 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8303 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8304 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8305 effect(USE src1, KILL cr);
8307 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8308 ins_cost(1*100 + 1*400 - 150);
8309 format %{ "IMUL EDX:EAX,$src1\n\t"
8310 "SAR EDX,$cnt-32" %}
8311 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8312 ins_pipe( pipe_slow );
8313 %}
8315 // Multiply Memory 32-bit Immediate
8316 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8317 match(Set dst (MulI (LoadI src) imm));
8318 effect(KILL cr);
8320 ins_cost(300);
8321 format %{ "IMUL $dst,$src,$imm" %}
8322 opcode(0x69); /* 69 /r id */
8323 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8324 ins_pipe( ialu_reg_mem_alu0 );
8325 %}
8327 // Multiply Memory
8328 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8329 match(Set dst (MulI dst (LoadI src)));
8330 effect(KILL cr);
8332 ins_cost(350);
8333 format %{ "IMUL $dst,$src" %}
8334 opcode(0xAF, 0x0F);
8335 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8336 ins_pipe( ialu_reg_mem_alu0 );
8337 %}
8339 // Multiply Register Int to Long
8340 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8341 // Basic Idea: long = (long)int * (long)int
8342 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8343 effect(DEF dst, USE src, USE src1, KILL flags);
8345 ins_cost(300);
8346 format %{ "IMUL $dst,$src1" %}
8348 ins_encode( long_int_multiply( dst, src1 ) );
8349 ins_pipe( ialu_reg_reg_alu0 );
8350 %}
8352 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8353 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8354 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8355 effect(KILL flags);
8357 ins_cost(300);
8358 format %{ "MUL $dst,$src1" %}
8360 ins_encode( long_uint_multiply(dst, src1) );
8361 ins_pipe( ialu_reg_reg_alu0 );
8362 %}
8364 // Multiply Register Long
8365 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8366 match(Set dst (MulL dst src));
8367 effect(KILL cr, TEMP tmp);
8368 ins_cost(4*100+3*400);
8369 // Basic idea: lo(result) = lo(x_lo * y_lo)
8370 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8371 format %{ "MOV $tmp,$src.lo\n\t"
8372 "IMUL $tmp,EDX\n\t"
8373 "MOV EDX,$src.hi\n\t"
8374 "IMUL EDX,EAX\n\t"
8375 "ADD $tmp,EDX\n\t"
8376 "MUL EDX:EAX,$src.lo\n\t"
8377 "ADD EDX,$tmp" %}
8378 ins_encode( long_multiply( dst, src, tmp ) );
8379 ins_pipe( pipe_slow );
8380 %}
8382 // Multiply Register Long by small constant
8383 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8384 match(Set dst (MulL dst src));
8385 effect(KILL cr, TEMP tmp);
8386 ins_cost(2*100+2*400);
8387 size(12);
8388 // Basic idea: lo(result) = lo(src * EAX)
8389 // hi(result) = hi(src * EAX) + lo(src * EDX)
8390 format %{ "IMUL $tmp,EDX,$src\n\t"
8391 "MOV EDX,$src\n\t"
8392 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8393 "ADD EDX,$tmp" %}
8394 ins_encode( long_multiply_con( dst, src, tmp ) );
8395 ins_pipe( pipe_slow );
8396 %}
8398 // Integer DIV with Register
8399 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8400 match(Set rax (DivI rax div));
8401 effect(KILL rdx, KILL cr);
8402 size(26);
8403 ins_cost(30*100+10*100);
8404 format %{ "CMP EAX,0x80000000\n\t"
8405 "JNE,s normal\n\t"
8406 "XOR EDX,EDX\n\t"
8407 "CMP ECX,-1\n\t"
8408 "JE,s done\n"
8409 "normal: CDQ\n\t"
8410 "IDIV $div\n\t"
8411 "done:" %}
8412 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8413 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8414 ins_pipe( ialu_reg_reg_alu0 );
8415 %}
8417 // Divide Register Long
8418 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8419 match(Set dst (DivL src1 src2));
8420 effect( KILL cr, KILL cx, KILL bx );
8421 ins_cost(10000);
8422 format %{ "PUSH $src1.hi\n\t"
8423 "PUSH $src1.lo\n\t"
8424 "PUSH $src2.hi\n\t"
8425 "PUSH $src2.lo\n\t"
8426 "CALL SharedRuntime::ldiv\n\t"
8427 "ADD ESP,16" %}
8428 ins_encode( long_div(src1,src2) );
8429 ins_pipe( pipe_slow );
8430 %}
8432 // Integer DIVMOD with Register, both quotient and mod results
8433 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8434 match(DivModI rax div);
8435 effect(KILL cr);
8436 size(26);
8437 ins_cost(30*100+10*100);
8438 format %{ "CMP EAX,0x80000000\n\t"
8439 "JNE,s normal\n\t"
8440 "XOR EDX,EDX\n\t"
8441 "CMP ECX,-1\n\t"
8442 "JE,s done\n"
8443 "normal: CDQ\n\t"
8444 "IDIV $div\n\t"
8445 "done:" %}
8446 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8447 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8448 ins_pipe( pipe_slow );
8449 %}
8451 // Integer MOD with Register
8452 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8453 match(Set rdx (ModI rax div));
8454 effect(KILL rax, KILL cr);
8456 size(26);
8457 ins_cost(300);
8458 format %{ "CDQ\n\t"
8459 "IDIV $div" %}
8460 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8461 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8462 ins_pipe( ialu_reg_reg_alu0 );
8463 %}
8465 // Remainder Register Long
8466 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8467 match(Set dst (ModL src1 src2));
8468 effect( KILL cr, KILL cx, KILL bx );
8469 ins_cost(10000);
8470 format %{ "PUSH $src1.hi\n\t"
8471 "PUSH $src1.lo\n\t"
8472 "PUSH $src2.hi\n\t"
8473 "PUSH $src2.lo\n\t"
8474 "CALL SharedRuntime::lrem\n\t"
8475 "ADD ESP,16" %}
8476 ins_encode( long_mod(src1,src2) );
8477 ins_pipe( pipe_slow );
8478 %}
8480 // Integer Shift Instructions
8481 // Shift Left by one
8482 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8483 match(Set dst (LShiftI dst shift));
8484 effect(KILL cr);
8486 size(2);
8487 format %{ "SHL $dst,$shift" %}
8488 opcode(0xD1, 0x4); /* D1 /4 */
8489 ins_encode( OpcP, RegOpc( dst ) );
8490 ins_pipe( ialu_reg );
8491 %}
8493 // Shift Left by 8-bit immediate
8494 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8495 match(Set dst (LShiftI dst shift));
8496 effect(KILL cr);
8498 size(3);
8499 format %{ "SHL $dst,$shift" %}
8500 opcode(0xC1, 0x4); /* C1 /4 ib */
8501 ins_encode( RegOpcImm( dst, shift) );
8502 ins_pipe( ialu_reg );
8503 %}
8505 // Shift Left by variable
8506 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8507 match(Set dst (LShiftI dst shift));
8508 effect(KILL cr);
8510 size(2);
8511 format %{ "SHL $dst,$shift" %}
8512 opcode(0xD3, 0x4); /* D3 /4 */
8513 ins_encode( OpcP, RegOpc( dst ) );
8514 ins_pipe( ialu_reg_reg );
8515 %}
8517 // Arithmetic shift right by one
8518 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8519 match(Set dst (RShiftI dst shift));
8520 effect(KILL cr);
8522 size(2);
8523 format %{ "SAR $dst,$shift" %}
8524 opcode(0xD1, 0x7); /* D1 /7 */
8525 ins_encode( OpcP, RegOpc( dst ) );
8526 ins_pipe( ialu_reg );
8527 %}
8529 // Arithmetic shift right by one
8530 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8531 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8532 effect(KILL cr);
8533 format %{ "SAR $dst,$shift" %}
8534 opcode(0xD1, 0x7); /* D1 /7 */
8535 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8536 ins_pipe( ialu_mem_imm );
8537 %}
8539 // Arithmetic Shift Right by 8-bit immediate
8540 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8541 match(Set dst (RShiftI dst shift));
8542 effect(KILL cr);
8544 size(3);
8545 format %{ "SAR $dst,$shift" %}
8546 opcode(0xC1, 0x7); /* C1 /7 ib */
8547 ins_encode( RegOpcImm( dst, shift ) );
8548 ins_pipe( ialu_mem_imm );
8549 %}
8551 // Arithmetic Shift Right by 8-bit immediate
8552 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8553 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8554 effect(KILL cr);
8556 format %{ "SAR $dst,$shift" %}
8557 opcode(0xC1, 0x7); /* C1 /7 ib */
8558 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8559 ins_pipe( ialu_mem_imm );
8560 %}
8562 // Arithmetic Shift Right by variable
8563 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8564 match(Set dst (RShiftI dst shift));
8565 effect(KILL cr);
8567 size(2);
8568 format %{ "SAR $dst,$shift" %}
8569 opcode(0xD3, 0x7); /* D3 /7 */
8570 ins_encode( OpcP, RegOpc( dst ) );
8571 ins_pipe( ialu_reg_reg );
8572 %}
8574 // Logical shift right by one
8575 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8576 match(Set dst (URShiftI dst shift));
8577 effect(KILL cr);
8579 size(2);
8580 format %{ "SHR $dst,$shift" %}
8581 opcode(0xD1, 0x5); /* D1 /5 */
8582 ins_encode( OpcP, RegOpc( dst ) );
8583 ins_pipe( ialu_reg );
8584 %}
8586 // Logical Shift Right by 8-bit immediate
8587 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8588 match(Set dst (URShiftI dst shift));
8589 effect(KILL cr);
8591 size(3);
8592 format %{ "SHR $dst,$shift" %}
8593 opcode(0xC1, 0x5); /* C1 /5 ib */
8594 ins_encode( RegOpcImm( dst, shift) );
8595 ins_pipe( ialu_reg );
8596 %}
8599 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8600 // This idiom is used by the compiler for the i2b bytecode.
8601 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
8602 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8603 effect(KILL cr);
8605 size(3);
8606 format %{ "MOVSX $dst,$src :8" %}
8607 opcode(0xBE, 0x0F);
8608 ins_encode( OpcS, OpcP, RegReg( dst, src));
8609 ins_pipe( ialu_reg_reg );
8610 %}
8612 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8613 // This idiom is used by the compiler the i2s bytecode.
8614 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
8615 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8616 effect(KILL cr);
8618 size(3);
8619 format %{ "MOVSX $dst,$src :16" %}
8620 opcode(0xBF, 0x0F);
8621 ins_encode( OpcS, OpcP, RegReg( dst, src));
8622 ins_pipe( ialu_reg_reg );
8623 %}
8626 // Logical Shift Right by variable
8627 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8628 match(Set dst (URShiftI dst shift));
8629 effect(KILL cr);
8631 size(2);
8632 format %{ "SHR $dst,$shift" %}
8633 opcode(0xD3, 0x5); /* D3 /5 */
8634 ins_encode( OpcP, RegOpc( dst ) );
8635 ins_pipe( ialu_reg_reg );
8636 %}
8639 //----------Logical Instructions-----------------------------------------------
8640 //----------Integer Logical Instructions---------------------------------------
8641 // And Instructions
8642 // And Register with Register
8643 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8644 match(Set dst (AndI dst src));
8645 effect(KILL cr);
8647 size(2);
8648 format %{ "AND $dst,$src" %}
8649 opcode(0x23);
8650 ins_encode( OpcP, RegReg( dst, src) );
8651 ins_pipe( ialu_reg_reg );
8652 %}
8654 // And Register with Immediate
8655 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8656 match(Set dst (AndI dst src));
8657 effect(KILL cr);
8659 format %{ "AND $dst,$src" %}
8660 opcode(0x81,0x04); /* Opcode 81 /4 */
8661 // ins_encode( RegImm( dst, src) );
8662 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8663 ins_pipe( ialu_reg );
8664 %}
8666 // And Register with Memory
8667 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8668 match(Set dst (AndI dst (LoadI src)));
8669 effect(KILL cr);
8671 ins_cost(125);
8672 format %{ "AND $dst,$src" %}
8673 opcode(0x23);
8674 ins_encode( OpcP, RegMem( dst, src) );
8675 ins_pipe( ialu_reg_mem );
8676 %}
8678 // And Memory with Register
8679 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8680 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8681 effect(KILL cr);
8683 ins_cost(150);
8684 format %{ "AND $dst,$src" %}
8685 opcode(0x21); /* Opcode 21 /r */
8686 ins_encode( OpcP, RegMem( src, dst ) );
8687 ins_pipe( ialu_mem_reg );
8688 %}
8690 // And Memory with Immediate
8691 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8692 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8693 effect(KILL cr);
8695 ins_cost(125);
8696 format %{ "AND $dst,$src" %}
8697 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8698 // ins_encode( MemImm( dst, src) );
8699 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8700 ins_pipe( ialu_mem_imm );
8701 %}
8703 // Or Instructions
8704 // Or Register with Register
8705 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8706 match(Set dst (OrI dst src));
8707 effect(KILL cr);
8709 size(2);
8710 format %{ "OR $dst,$src" %}
8711 opcode(0x0B);
8712 ins_encode( OpcP, RegReg( dst, src) );
8713 ins_pipe( ialu_reg_reg );
8714 %}
8716 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8717 match(Set dst (OrI dst (CastP2X src)));
8718 effect(KILL cr);
8720 size(2);
8721 format %{ "OR $dst,$src" %}
8722 opcode(0x0B);
8723 ins_encode( OpcP, RegReg( dst, src) );
8724 ins_pipe( ialu_reg_reg );
8725 %}
8728 // Or Register with Immediate
8729 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8730 match(Set dst (OrI dst src));
8731 effect(KILL cr);
8733 format %{ "OR $dst,$src" %}
8734 opcode(0x81,0x01); /* Opcode 81 /1 id */
8735 // ins_encode( RegImm( dst, src) );
8736 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8737 ins_pipe( ialu_reg );
8738 %}
8740 // Or Register with Memory
8741 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8742 match(Set dst (OrI dst (LoadI src)));
8743 effect(KILL cr);
8745 ins_cost(125);
8746 format %{ "OR $dst,$src" %}
8747 opcode(0x0B);
8748 ins_encode( OpcP, RegMem( dst, src) );
8749 ins_pipe( ialu_reg_mem );
8750 %}
8752 // Or Memory with Register
8753 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8754 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8755 effect(KILL cr);
8757 ins_cost(150);
8758 format %{ "OR $dst,$src" %}
8759 opcode(0x09); /* Opcode 09 /r */
8760 ins_encode( OpcP, RegMem( src, dst ) );
8761 ins_pipe( ialu_mem_reg );
8762 %}
8764 // Or Memory with Immediate
8765 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8766 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8767 effect(KILL cr);
8769 ins_cost(125);
8770 format %{ "OR $dst,$src" %}
8771 opcode(0x81,0x1); /* Opcode 81 /1 id */
8772 // ins_encode( MemImm( dst, src) );
8773 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8774 ins_pipe( ialu_mem_imm );
8775 %}
8777 // ROL/ROR
8778 // ROL expand
8779 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8780 effect(USE_DEF dst, USE shift, KILL cr);
8782 format %{ "ROL $dst, $shift" %}
8783 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8784 ins_encode( OpcP, RegOpc( dst ));
8785 ins_pipe( ialu_reg );
8786 %}
8788 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8789 effect(USE_DEF dst, USE shift, KILL cr);
8791 format %{ "ROL $dst, $shift" %}
8792 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8793 ins_encode( RegOpcImm(dst, shift) );
8794 ins_pipe(ialu_reg);
8795 %}
8797 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8798 effect(USE_DEF dst, USE shift, KILL cr);
8800 format %{ "ROL $dst, $shift" %}
8801 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8802 ins_encode(OpcP, RegOpc(dst));
8803 ins_pipe( ialu_reg_reg );
8804 %}
8805 // end of ROL expand
8807 // ROL 32bit by one once
8808 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8809 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8811 expand %{
8812 rolI_eReg_imm1(dst, lshift, cr);
8813 %}
8814 %}
8816 // ROL 32bit var by imm8 once
8817 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8818 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8819 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8821 expand %{
8822 rolI_eReg_imm8(dst, lshift, cr);
8823 %}
8824 %}
8826 // ROL 32bit var by var once
8827 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8828 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8830 expand %{
8831 rolI_eReg_CL(dst, shift, cr);
8832 %}
8833 %}
8835 // ROL 32bit var by var once
8836 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8837 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8839 expand %{
8840 rolI_eReg_CL(dst, shift, cr);
8841 %}
8842 %}
8844 // ROR expand
8845 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8846 effect(USE_DEF dst, USE shift, KILL cr);
8848 format %{ "ROR $dst, $shift" %}
8849 opcode(0xD1,0x1); /* Opcode D1 /1 */
8850 ins_encode( OpcP, RegOpc( dst ) );
8851 ins_pipe( ialu_reg );
8852 %}
8854 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8855 effect (USE_DEF dst, USE shift, KILL cr);
8857 format %{ "ROR $dst, $shift" %}
8858 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8859 ins_encode( RegOpcImm(dst, shift) );
8860 ins_pipe( ialu_reg );
8861 %}
8863 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8864 effect(USE_DEF dst, USE shift, KILL cr);
8866 format %{ "ROR $dst, $shift" %}
8867 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8868 ins_encode(OpcP, RegOpc(dst));
8869 ins_pipe( ialu_reg_reg );
8870 %}
8871 // end of ROR expand
8873 // ROR right once
8874 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8875 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8877 expand %{
8878 rorI_eReg_imm1(dst, rshift, cr);
8879 %}
8880 %}
8882 // ROR 32bit by immI8 once
8883 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8884 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8885 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8887 expand %{
8888 rorI_eReg_imm8(dst, rshift, cr);
8889 %}
8890 %}
8892 // ROR 32bit var by var once
8893 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8894 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8896 expand %{
8897 rorI_eReg_CL(dst, shift, cr);
8898 %}
8899 %}
8901 // ROR 32bit var by var once
8902 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8903 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8905 expand %{
8906 rorI_eReg_CL(dst, shift, cr);
8907 %}
8908 %}
8910 // Xor Instructions
8911 // Xor Register with Register
8912 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8913 match(Set dst (XorI dst src));
8914 effect(KILL cr);
8916 size(2);
8917 format %{ "XOR $dst,$src" %}
8918 opcode(0x33);
8919 ins_encode( OpcP, RegReg( dst, src) );
8920 ins_pipe( ialu_reg_reg );
8921 %}
8923 // Xor Register with Immediate -1
8924 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
8925 match(Set dst (XorI dst imm));
8927 size(2);
8928 format %{ "NOT $dst" %}
8929 ins_encode %{
8930 __ notl($dst$$Register);
8931 %}
8932 ins_pipe( ialu_reg );
8933 %}
8935 // Xor Register with Immediate
8936 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8937 match(Set dst (XorI dst src));
8938 effect(KILL cr);
8940 format %{ "XOR $dst,$src" %}
8941 opcode(0x81,0x06); /* Opcode 81 /6 id */
8942 // ins_encode( RegImm( dst, src) );
8943 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8944 ins_pipe( ialu_reg );
8945 %}
8947 // Xor Register with Memory
8948 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8949 match(Set dst (XorI dst (LoadI src)));
8950 effect(KILL cr);
8952 ins_cost(125);
8953 format %{ "XOR $dst,$src" %}
8954 opcode(0x33);
8955 ins_encode( OpcP, RegMem(dst, src) );
8956 ins_pipe( ialu_reg_mem );
8957 %}
8959 // Xor Memory with Register
8960 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8961 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8962 effect(KILL cr);
8964 ins_cost(150);
8965 format %{ "XOR $dst,$src" %}
8966 opcode(0x31); /* Opcode 31 /r */
8967 ins_encode( OpcP, RegMem( src, dst ) );
8968 ins_pipe( ialu_mem_reg );
8969 %}
8971 // Xor Memory with Immediate
8972 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8973 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8974 effect(KILL cr);
8976 ins_cost(125);
8977 format %{ "XOR $dst,$src" %}
8978 opcode(0x81,0x6); /* Opcode 81 /6 id */
8979 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8980 ins_pipe( ialu_mem_imm );
8981 %}
8983 //----------Convert Int to Boolean---------------------------------------------
8985 instruct movI_nocopy(eRegI dst, eRegI src) %{
8986 effect( DEF dst, USE src );
8987 format %{ "MOV $dst,$src" %}
8988 ins_encode( enc_Copy( dst, src) );
8989 ins_pipe( ialu_reg_reg );
8990 %}
8992 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
8993 effect( USE_DEF dst, USE src, KILL cr );
8995 size(4);
8996 format %{ "NEG $dst\n\t"
8997 "ADC $dst,$src" %}
8998 ins_encode( neg_reg(dst),
8999 OpcRegReg(0x13,dst,src) );
9000 ins_pipe( ialu_reg_reg_long );
9001 %}
9003 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9004 match(Set dst (Conv2B src));
9006 expand %{
9007 movI_nocopy(dst,src);
9008 ci2b(dst,src,cr);
9009 %}
9010 %}
9012 instruct movP_nocopy(eRegI dst, eRegP src) %{
9013 effect( DEF dst, USE src );
9014 format %{ "MOV $dst,$src" %}
9015 ins_encode( enc_Copy( dst, src) );
9016 ins_pipe( ialu_reg_reg );
9017 %}
9019 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9020 effect( USE_DEF dst, USE src, KILL cr );
9021 format %{ "NEG $dst\n\t"
9022 "ADC $dst,$src" %}
9023 ins_encode( neg_reg(dst),
9024 OpcRegReg(0x13,dst,src) );
9025 ins_pipe( ialu_reg_reg_long );
9026 %}
9028 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9029 match(Set dst (Conv2B src));
9031 expand %{
9032 movP_nocopy(dst,src);
9033 cp2b(dst,src,cr);
9034 %}
9035 %}
9037 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9038 match(Set dst (CmpLTMask p q));
9039 effect( KILL cr );
9040 ins_cost(400);
9042 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9043 format %{ "XOR $dst,$dst\n\t"
9044 "CMP $p,$q\n\t"
9045 "SETlt $dst\n\t"
9046 "NEG $dst" %}
9047 ins_encode( OpcRegReg(0x33,dst,dst),
9048 OpcRegReg(0x3B,p,q),
9049 setLT_reg(dst), neg_reg(dst) );
9050 ins_pipe( pipe_slow );
9051 %}
9053 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9054 match(Set dst (CmpLTMask dst zero));
9055 effect( DEF dst, KILL cr );
9056 ins_cost(100);
9058 format %{ "SAR $dst,31" %}
9059 opcode(0xC1, 0x7); /* C1 /7 ib */
9060 ins_encode( RegOpcImm( dst, 0x1F ) );
9061 ins_pipe( ialu_reg );
9062 %}
9065 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9066 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9067 effect( KILL tmp, KILL cr );
9068 ins_cost(400);
9069 // annoyingly, $tmp has no edges so you cant ask for it in
9070 // any format or encoding
9071 format %{ "SUB $p,$q\n\t"
9072 "SBB ECX,ECX\n\t"
9073 "AND ECX,$y\n\t"
9074 "ADD $p,ECX" %}
9075 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9076 ins_pipe( pipe_cmplt );
9077 %}
9079 /* If I enable this, I encourage spilling in the inner loop of compress.
9080 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9081 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9082 effect( USE_KILL tmp, KILL cr );
9083 ins_cost(400);
9085 format %{ "SUB $p,$q\n\t"
9086 "SBB ECX,ECX\n\t"
9087 "AND ECX,$y\n\t"
9088 "ADD $p,ECX" %}
9089 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9090 %}
9091 */
9093 //----------Long Instructions------------------------------------------------
9094 // Add Long Register with Register
9095 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9096 match(Set dst (AddL dst src));
9097 effect(KILL cr);
9098 ins_cost(200);
9099 format %{ "ADD $dst.lo,$src.lo\n\t"
9100 "ADC $dst.hi,$src.hi" %}
9101 opcode(0x03, 0x13);
9102 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9103 ins_pipe( ialu_reg_reg_long );
9104 %}
9106 // Add Long Register with Immediate
9107 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9108 match(Set dst (AddL dst src));
9109 effect(KILL cr);
9110 format %{ "ADD $dst.lo,$src.lo\n\t"
9111 "ADC $dst.hi,$src.hi" %}
9112 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9113 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9114 ins_pipe( ialu_reg_long );
9115 %}
9117 // Add Long Register with Memory
9118 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9119 match(Set dst (AddL dst (LoadL mem)));
9120 effect(KILL cr);
9121 ins_cost(125);
9122 format %{ "ADD $dst.lo,$mem\n\t"
9123 "ADC $dst.hi,$mem+4" %}
9124 opcode(0x03, 0x13);
9125 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9126 ins_pipe( ialu_reg_long_mem );
9127 %}
9129 // Subtract Long Register with Register.
9130 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9131 match(Set dst (SubL dst src));
9132 effect(KILL cr);
9133 ins_cost(200);
9134 format %{ "SUB $dst.lo,$src.lo\n\t"
9135 "SBB $dst.hi,$src.hi" %}
9136 opcode(0x2B, 0x1B);
9137 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9138 ins_pipe( ialu_reg_reg_long );
9139 %}
9141 // Subtract Long Register with Immediate
9142 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9143 match(Set dst (SubL dst src));
9144 effect(KILL cr);
9145 format %{ "SUB $dst.lo,$src.lo\n\t"
9146 "SBB $dst.hi,$src.hi" %}
9147 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9148 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9149 ins_pipe( ialu_reg_long );
9150 %}
9152 // Subtract Long Register with Memory
9153 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9154 match(Set dst (SubL dst (LoadL mem)));
9155 effect(KILL cr);
9156 ins_cost(125);
9157 format %{ "SUB $dst.lo,$mem\n\t"
9158 "SBB $dst.hi,$mem+4" %}
9159 opcode(0x2B, 0x1B);
9160 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9161 ins_pipe( ialu_reg_long_mem );
9162 %}
9164 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9165 match(Set dst (SubL zero dst));
9166 effect(KILL cr);
9167 ins_cost(300);
9168 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9169 ins_encode( neg_long(dst) );
9170 ins_pipe( ialu_reg_reg_long );
9171 %}
9173 // And Long Register with Register
9174 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9175 match(Set dst (AndL dst src));
9176 effect(KILL cr);
9177 format %{ "AND $dst.lo,$src.lo\n\t"
9178 "AND $dst.hi,$src.hi" %}
9179 opcode(0x23,0x23);
9180 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9181 ins_pipe( ialu_reg_reg_long );
9182 %}
9184 // And Long Register with Immediate
9185 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9186 match(Set dst (AndL dst src));
9187 effect(KILL cr);
9188 format %{ "AND $dst.lo,$src.lo\n\t"
9189 "AND $dst.hi,$src.hi" %}
9190 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9191 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9192 ins_pipe( ialu_reg_long );
9193 %}
9195 // And Long Register with Memory
9196 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9197 match(Set dst (AndL dst (LoadL mem)));
9198 effect(KILL cr);
9199 ins_cost(125);
9200 format %{ "AND $dst.lo,$mem\n\t"
9201 "AND $dst.hi,$mem+4" %}
9202 opcode(0x23, 0x23);
9203 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9204 ins_pipe( ialu_reg_long_mem );
9205 %}
9207 // Or Long Register with Register
9208 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9209 match(Set dst (OrL dst src));
9210 effect(KILL cr);
9211 format %{ "OR $dst.lo,$src.lo\n\t"
9212 "OR $dst.hi,$src.hi" %}
9213 opcode(0x0B,0x0B);
9214 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9215 ins_pipe( ialu_reg_reg_long );
9216 %}
9218 // Or Long Register with Immediate
9219 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9220 match(Set dst (OrL dst src));
9221 effect(KILL cr);
9222 format %{ "OR $dst.lo,$src.lo\n\t"
9223 "OR $dst.hi,$src.hi" %}
9224 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9225 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9226 ins_pipe( ialu_reg_long );
9227 %}
9229 // Or Long Register with Memory
9230 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9231 match(Set dst (OrL dst (LoadL mem)));
9232 effect(KILL cr);
9233 ins_cost(125);
9234 format %{ "OR $dst.lo,$mem\n\t"
9235 "OR $dst.hi,$mem+4" %}
9236 opcode(0x0B,0x0B);
9237 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9238 ins_pipe( ialu_reg_long_mem );
9239 %}
9241 // Xor Long Register with Register
9242 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9243 match(Set dst (XorL dst src));
9244 effect(KILL cr);
9245 format %{ "XOR $dst.lo,$src.lo\n\t"
9246 "XOR $dst.hi,$src.hi" %}
9247 opcode(0x33,0x33);
9248 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9249 ins_pipe( ialu_reg_reg_long );
9250 %}
9252 // Xor Long Register with Immediate -1
9253 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9254 match(Set dst (XorL dst imm));
9255 format %{ "NOT $dst.lo\n\t"
9256 "NOT $dst.hi" %}
9257 ins_encode %{
9258 __ notl($dst$$Register);
9259 __ notl(HIGH_FROM_LOW($dst$$Register));
9260 %}
9261 ins_pipe( ialu_reg_long );
9262 %}
9264 // Xor Long Register with Immediate
9265 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9266 match(Set dst (XorL dst src));
9267 effect(KILL cr);
9268 format %{ "XOR $dst.lo,$src.lo\n\t"
9269 "XOR $dst.hi,$src.hi" %}
9270 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9271 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9272 ins_pipe( ialu_reg_long );
9273 %}
9275 // Xor Long Register with Memory
9276 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9277 match(Set dst (XorL dst (LoadL mem)));
9278 effect(KILL cr);
9279 ins_cost(125);
9280 format %{ "XOR $dst.lo,$mem\n\t"
9281 "XOR $dst.hi,$mem+4" %}
9282 opcode(0x33,0x33);
9283 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9284 ins_pipe( ialu_reg_long_mem );
9285 %}
9287 // Shift Left Long by 1
9288 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9289 predicate(UseNewLongLShift);
9290 match(Set dst (LShiftL dst cnt));
9291 effect(KILL cr);
9292 ins_cost(100);
9293 format %{ "ADD $dst.lo,$dst.lo\n\t"
9294 "ADC $dst.hi,$dst.hi" %}
9295 ins_encode %{
9296 __ addl($dst$$Register,$dst$$Register);
9297 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9298 %}
9299 ins_pipe( ialu_reg_long );
9300 %}
9302 // Shift Left Long by 2
9303 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9304 predicate(UseNewLongLShift);
9305 match(Set dst (LShiftL dst cnt));
9306 effect(KILL cr);
9307 ins_cost(100);
9308 format %{ "ADD $dst.lo,$dst.lo\n\t"
9309 "ADC $dst.hi,$dst.hi\n\t"
9310 "ADD $dst.lo,$dst.lo\n\t"
9311 "ADC $dst.hi,$dst.hi" %}
9312 ins_encode %{
9313 __ addl($dst$$Register,$dst$$Register);
9314 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9315 __ addl($dst$$Register,$dst$$Register);
9316 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9317 %}
9318 ins_pipe( ialu_reg_long );
9319 %}
9321 // Shift Left Long by 3
9322 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9323 predicate(UseNewLongLShift);
9324 match(Set dst (LShiftL dst cnt));
9325 effect(KILL cr);
9326 ins_cost(100);
9327 format %{ "ADD $dst.lo,$dst.lo\n\t"
9328 "ADC $dst.hi,$dst.hi\n\t"
9329 "ADD $dst.lo,$dst.lo\n\t"
9330 "ADC $dst.hi,$dst.hi\n\t"
9331 "ADD $dst.lo,$dst.lo\n\t"
9332 "ADC $dst.hi,$dst.hi" %}
9333 ins_encode %{
9334 __ addl($dst$$Register,$dst$$Register);
9335 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9336 __ addl($dst$$Register,$dst$$Register);
9337 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9338 __ addl($dst$$Register,$dst$$Register);
9339 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9340 %}
9341 ins_pipe( ialu_reg_long );
9342 %}
9344 // Shift Left Long by 1-31
9345 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9346 match(Set dst (LShiftL dst cnt));
9347 effect(KILL cr);
9348 ins_cost(200);
9349 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9350 "SHL $dst.lo,$cnt" %}
9351 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9352 ins_encode( move_long_small_shift(dst,cnt) );
9353 ins_pipe( ialu_reg_long );
9354 %}
9356 // Shift Left Long by 32-63
9357 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9358 match(Set dst (LShiftL dst cnt));
9359 effect(KILL cr);
9360 ins_cost(300);
9361 format %{ "MOV $dst.hi,$dst.lo\n"
9362 "\tSHL $dst.hi,$cnt-32\n"
9363 "\tXOR $dst.lo,$dst.lo" %}
9364 opcode(0xC1, 0x4); /* C1 /4 ib */
9365 ins_encode( move_long_big_shift_clr(dst,cnt) );
9366 ins_pipe( ialu_reg_long );
9367 %}
9369 // Shift Left Long by variable
9370 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9371 match(Set dst (LShiftL dst shift));
9372 effect(KILL cr);
9373 ins_cost(500+200);
9374 size(17);
9375 format %{ "TEST $shift,32\n\t"
9376 "JEQ,s small\n\t"
9377 "MOV $dst.hi,$dst.lo\n\t"
9378 "XOR $dst.lo,$dst.lo\n"
9379 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9380 "SHL $dst.lo,$shift" %}
9381 ins_encode( shift_left_long( dst, shift ) );
9382 ins_pipe( pipe_slow );
9383 %}
9385 // Shift Right Long by 1-31
9386 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9387 match(Set dst (URShiftL dst cnt));
9388 effect(KILL cr);
9389 ins_cost(200);
9390 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9391 "SHR $dst.hi,$cnt" %}
9392 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9393 ins_encode( move_long_small_shift(dst,cnt) );
9394 ins_pipe( ialu_reg_long );
9395 %}
9397 // Shift Right Long by 32-63
9398 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9399 match(Set dst (URShiftL dst cnt));
9400 effect(KILL cr);
9401 ins_cost(300);
9402 format %{ "MOV $dst.lo,$dst.hi\n"
9403 "\tSHR $dst.lo,$cnt-32\n"
9404 "\tXOR $dst.hi,$dst.hi" %}
9405 opcode(0xC1, 0x5); /* C1 /5 ib */
9406 ins_encode( move_long_big_shift_clr(dst,cnt) );
9407 ins_pipe( ialu_reg_long );
9408 %}
9410 // Shift Right Long by variable
9411 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9412 match(Set dst (URShiftL dst shift));
9413 effect(KILL cr);
9414 ins_cost(600);
9415 size(17);
9416 format %{ "TEST $shift,32\n\t"
9417 "JEQ,s small\n\t"
9418 "MOV $dst.lo,$dst.hi\n\t"
9419 "XOR $dst.hi,$dst.hi\n"
9420 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9421 "SHR $dst.hi,$shift" %}
9422 ins_encode( shift_right_long( dst, shift ) );
9423 ins_pipe( pipe_slow );
9424 %}
9426 // Shift Right Long by 1-31
9427 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9428 match(Set dst (RShiftL dst cnt));
9429 effect(KILL cr);
9430 ins_cost(200);
9431 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9432 "SAR $dst.hi,$cnt" %}
9433 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9434 ins_encode( move_long_small_shift(dst,cnt) );
9435 ins_pipe( ialu_reg_long );
9436 %}
9438 // Shift Right Long by 32-63
9439 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9440 match(Set dst (RShiftL dst cnt));
9441 effect(KILL cr);
9442 ins_cost(300);
9443 format %{ "MOV $dst.lo,$dst.hi\n"
9444 "\tSAR $dst.lo,$cnt-32\n"
9445 "\tSAR $dst.hi,31" %}
9446 opcode(0xC1, 0x7); /* C1 /7 ib */
9447 ins_encode( move_long_big_shift_sign(dst,cnt) );
9448 ins_pipe( ialu_reg_long );
9449 %}
9451 // Shift Right arithmetic Long by variable
9452 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9453 match(Set dst (RShiftL dst shift));
9454 effect(KILL cr);
9455 ins_cost(600);
9456 size(18);
9457 format %{ "TEST $shift,32\n\t"
9458 "JEQ,s small\n\t"
9459 "MOV $dst.lo,$dst.hi\n\t"
9460 "SAR $dst.hi,31\n"
9461 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9462 "SAR $dst.hi,$shift" %}
9463 ins_encode( shift_right_arith_long( dst, shift ) );
9464 ins_pipe( pipe_slow );
9465 %}
9468 //----------Double Instructions------------------------------------------------
9469 // Double Math
9471 // Compare & branch
9473 // P6 version of float compare, sets condition codes in EFLAGS
9474 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9475 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9476 match(Set cr (CmpD src1 src2));
9477 effect(KILL rax);
9478 ins_cost(150);
9479 format %{ "FLD $src1\n\t"
9480 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9481 "JNP exit\n\t"
9482 "MOV ah,1 // saw a NaN, set CF\n\t"
9483 "SAHF\n"
9484 "exit:\tNOP // avoid branch to branch" %}
9485 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9486 ins_encode( Push_Reg_D(src1),
9487 OpcP, RegOpc(src2),
9488 cmpF_P6_fixup );
9489 ins_pipe( pipe_slow );
9490 %}
9492 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9493 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9494 match(Set cr (CmpD src1 src2));
9495 ins_cost(150);
9496 format %{ "FLD $src1\n\t"
9497 "FUCOMIP ST,$src2 // P6 instruction" %}
9498 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9499 ins_encode( Push_Reg_D(src1),
9500 OpcP, RegOpc(src2));
9501 ins_pipe( pipe_slow );
9502 %}
9504 // Compare & branch
9505 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9506 predicate(UseSSE<=1);
9507 match(Set cr (CmpD src1 src2));
9508 effect(KILL rax);
9509 ins_cost(200);
9510 format %{ "FLD $src1\n\t"
9511 "FCOMp $src2\n\t"
9512 "FNSTSW AX\n\t"
9513 "TEST AX,0x400\n\t"
9514 "JZ,s flags\n\t"
9515 "MOV AH,1\t# unordered treat as LT\n"
9516 "flags:\tSAHF" %}
9517 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9518 ins_encode( Push_Reg_D(src1),
9519 OpcP, RegOpc(src2),
9520 fpu_flags);
9521 ins_pipe( pipe_slow );
9522 %}
9524 // Compare vs zero into -1,0,1
9525 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9526 predicate(UseSSE<=1);
9527 match(Set dst (CmpD3 src1 zero));
9528 effect(KILL cr, KILL rax);
9529 ins_cost(280);
9530 format %{ "FTSTD $dst,$src1" %}
9531 opcode(0xE4, 0xD9);
9532 ins_encode( Push_Reg_D(src1),
9533 OpcS, OpcP, PopFPU,
9534 CmpF_Result(dst));
9535 ins_pipe( pipe_slow );
9536 %}
9538 // Compare into -1,0,1
9539 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9540 predicate(UseSSE<=1);
9541 match(Set dst (CmpD3 src1 src2));
9542 effect(KILL cr, KILL rax);
9543 ins_cost(300);
9544 format %{ "FCMPD $dst,$src1,$src2" %}
9545 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9546 ins_encode( Push_Reg_D(src1),
9547 OpcP, RegOpc(src2),
9548 CmpF_Result(dst));
9549 ins_pipe( pipe_slow );
9550 %}
9552 // float compare and set condition codes in EFLAGS by XMM regs
9553 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9554 predicate(UseSSE>=2);
9555 match(Set cr (CmpD dst src));
9556 effect(KILL rax);
9557 ins_cost(125);
9558 format %{ "COMISD $dst,$src\n"
9559 "\tJNP exit\n"
9560 "\tMOV ah,1 // saw a NaN, set CF\n"
9561 "\tSAHF\n"
9562 "exit:\tNOP // avoid branch to branch" %}
9563 opcode(0x66, 0x0F, 0x2F);
9564 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9565 ins_pipe( pipe_slow );
9566 %}
9568 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9569 predicate(UseSSE>=2);
9570 match(Set cr (CmpD dst src));
9571 ins_cost(100);
9572 format %{ "COMISD $dst,$src" %}
9573 opcode(0x66, 0x0F, 0x2F);
9574 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9575 ins_pipe( pipe_slow );
9576 %}
9578 // float compare and set condition codes in EFLAGS by XMM regs
9579 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9580 predicate(UseSSE>=2);
9581 match(Set cr (CmpD dst (LoadD src)));
9582 effect(KILL rax);
9583 ins_cost(145);
9584 format %{ "COMISD $dst,$src\n"
9585 "\tJNP exit\n"
9586 "\tMOV ah,1 // saw a NaN, set CF\n"
9587 "\tSAHF\n"
9588 "exit:\tNOP // avoid branch to branch" %}
9589 opcode(0x66, 0x0F, 0x2F);
9590 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9591 ins_pipe( pipe_slow );
9592 %}
9594 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9595 predicate(UseSSE>=2);
9596 match(Set cr (CmpD dst (LoadD src)));
9597 ins_cost(100);
9598 format %{ "COMISD $dst,$src" %}
9599 opcode(0x66, 0x0F, 0x2F);
9600 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9601 ins_pipe( pipe_slow );
9602 %}
9604 // Compare into -1,0,1 in XMM
9605 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9606 predicate(UseSSE>=2);
9607 match(Set dst (CmpD3 src1 src2));
9608 effect(KILL cr);
9609 ins_cost(255);
9610 format %{ "XOR $dst,$dst\n"
9611 "\tCOMISD $src1,$src2\n"
9612 "\tJP,s nan\n"
9613 "\tJEQ,s exit\n"
9614 "\tJA,s inc\n"
9615 "nan:\tDEC $dst\n"
9616 "\tJMP,s exit\n"
9617 "inc:\tINC $dst\n"
9618 "exit:"
9619 %}
9620 opcode(0x66, 0x0F, 0x2F);
9621 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9622 CmpX_Result(dst));
9623 ins_pipe( pipe_slow );
9624 %}
9626 // Compare into -1,0,1 in XMM and memory
9627 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9628 predicate(UseSSE>=2);
9629 match(Set dst (CmpD3 src1 (LoadD mem)));
9630 effect(KILL cr);
9631 ins_cost(275);
9632 format %{ "COMISD $src1,$mem\n"
9633 "\tMOV $dst,0\t\t# do not blow flags\n"
9634 "\tJP,s nan\n"
9635 "\tJEQ,s exit\n"
9636 "\tJA,s inc\n"
9637 "nan:\tDEC $dst\n"
9638 "\tJMP,s exit\n"
9639 "inc:\tINC $dst\n"
9640 "exit:"
9641 %}
9642 opcode(0x66, 0x0F, 0x2F);
9643 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9644 LdImmI(dst,0x0), CmpX_Result(dst));
9645 ins_pipe( pipe_slow );
9646 %}
9649 instruct subD_reg(regD dst, regD src) %{
9650 predicate (UseSSE <=1);
9651 match(Set dst (SubD dst src));
9653 format %{ "FLD $src\n\t"
9654 "DSUBp $dst,ST" %}
9655 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9656 ins_cost(150);
9657 ins_encode( Push_Reg_D(src),
9658 OpcP, RegOpc(dst) );
9659 ins_pipe( fpu_reg_reg );
9660 %}
9662 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9663 predicate (UseSSE <=1);
9664 match(Set dst (RoundDouble (SubD src1 src2)));
9665 ins_cost(250);
9667 format %{ "FLD $src2\n\t"
9668 "DSUB ST,$src1\n\t"
9669 "FSTP_D $dst\t# D-round" %}
9670 opcode(0xD8, 0x5);
9671 ins_encode( Push_Reg_D(src2),
9672 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9673 ins_pipe( fpu_mem_reg_reg );
9674 %}
9677 instruct subD_reg_mem(regD dst, memory src) %{
9678 predicate (UseSSE <=1);
9679 match(Set dst (SubD dst (LoadD src)));
9680 ins_cost(150);
9682 format %{ "FLD $src\n\t"
9683 "DSUBp $dst,ST" %}
9684 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9685 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9686 OpcP, RegOpc(dst) );
9687 ins_pipe( fpu_reg_mem );
9688 %}
9690 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9691 predicate (UseSSE<=1);
9692 match(Set dst (AbsD src));
9693 ins_cost(100);
9694 format %{ "FABS" %}
9695 opcode(0xE1, 0xD9);
9696 ins_encode( OpcS, OpcP );
9697 ins_pipe( fpu_reg_reg );
9698 %}
9700 instruct absXD_reg( regXD dst ) %{
9701 predicate(UseSSE>=2);
9702 match(Set dst (AbsD dst));
9703 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9704 ins_encode( AbsXD_encoding(dst));
9705 ins_pipe( pipe_slow );
9706 %}
9708 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9709 predicate(UseSSE<=1);
9710 match(Set dst (NegD src));
9711 ins_cost(100);
9712 format %{ "FCHS" %}
9713 opcode(0xE0, 0xD9);
9714 ins_encode( OpcS, OpcP );
9715 ins_pipe( fpu_reg_reg );
9716 %}
9718 instruct negXD_reg( regXD dst ) %{
9719 predicate(UseSSE>=2);
9720 match(Set dst (NegD dst));
9721 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9722 ins_encode %{
9723 __ xorpd($dst$$XMMRegister,
9724 ExternalAddress((address)double_signflip_pool));
9725 %}
9726 ins_pipe( pipe_slow );
9727 %}
9729 instruct addD_reg(regD dst, regD src) %{
9730 predicate(UseSSE<=1);
9731 match(Set dst (AddD dst src));
9732 format %{ "FLD $src\n\t"
9733 "DADD $dst,ST" %}
9734 size(4);
9735 ins_cost(150);
9736 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9737 ins_encode( Push_Reg_D(src),
9738 OpcP, RegOpc(dst) );
9739 ins_pipe( fpu_reg_reg );
9740 %}
9743 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9744 predicate(UseSSE<=1);
9745 match(Set dst (RoundDouble (AddD src1 src2)));
9746 ins_cost(250);
9748 format %{ "FLD $src2\n\t"
9749 "DADD ST,$src1\n\t"
9750 "FSTP_D $dst\t# D-round" %}
9751 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9752 ins_encode( Push_Reg_D(src2),
9753 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9754 ins_pipe( fpu_mem_reg_reg );
9755 %}
9758 instruct addD_reg_mem(regD dst, memory src) %{
9759 predicate(UseSSE<=1);
9760 match(Set dst (AddD dst (LoadD src)));
9761 ins_cost(150);
9763 format %{ "FLD $src\n\t"
9764 "DADDp $dst,ST" %}
9765 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9766 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9767 OpcP, RegOpc(dst) );
9768 ins_pipe( fpu_reg_mem );
9769 %}
9771 // add-to-memory
9772 instruct addD_mem_reg(memory dst, regD src) %{
9773 predicate(UseSSE<=1);
9774 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9775 ins_cost(150);
9777 format %{ "FLD_D $dst\n\t"
9778 "DADD ST,$src\n\t"
9779 "FST_D $dst" %}
9780 opcode(0xDD, 0x0);
9781 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9782 Opcode(0xD8), RegOpc(src),
9783 set_instruction_start,
9784 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9785 ins_pipe( fpu_reg_mem );
9786 %}
9788 instruct addD_reg_imm1(regD dst, immD1 src) %{
9789 predicate(UseSSE<=1);
9790 match(Set dst (AddD dst src));
9791 ins_cost(125);
9792 format %{ "FLD1\n\t"
9793 "DADDp $dst,ST" %}
9794 opcode(0xDE, 0x00);
9795 ins_encode( LdImmD(src),
9796 OpcP, RegOpc(dst) );
9797 ins_pipe( fpu_reg );
9798 %}
9800 instruct addD_reg_imm(regD dst, immD src) %{
9801 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9802 match(Set dst (AddD dst src));
9803 ins_cost(200);
9804 format %{ "FLD_D [$src]\n\t"
9805 "DADDp $dst,ST" %}
9806 opcode(0xDE, 0x00); /* DE /0 */
9807 ins_encode( LdImmD(src),
9808 OpcP, RegOpc(dst));
9809 ins_pipe( fpu_reg_mem );
9810 %}
9812 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9813 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9814 match(Set dst (RoundDouble (AddD src con)));
9815 ins_cost(200);
9816 format %{ "FLD_D [$con]\n\t"
9817 "DADD ST,$src\n\t"
9818 "FSTP_D $dst\t# D-round" %}
9819 opcode(0xD8, 0x00); /* D8 /0 */
9820 ins_encode( LdImmD(con),
9821 OpcP, RegOpc(src), Pop_Mem_D(dst));
9822 ins_pipe( fpu_mem_reg_con );
9823 %}
9825 // Add two double precision floating point values in xmm
9826 instruct addXD_reg(regXD dst, regXD src) %{
9827 predicate(UseSSE>=2);
9828 match(Set dst (AddD dst src));
9829 format %{ "ADDSD $dst,$src" %}
9830 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
9831 ins_pipe( pipe_slow );
9832 %}
9834 instruct addXD_imm(regXD dst, immXD con) %{
9835 predicate(UseSSE>=2);
9836 match(Set dst (AddD dst con));
9837 format %{ "ADDSD $dst,[$con]" %}
9838 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
9839 ins_pipe( pipe_slow );
9840 %}
9842 instruct addXD_mem(regXD dst, memory mem) %{
9843 predicate(UseSSE>=2);
9844 match(Set dst (AddD dst (LoadD mem)));
9845 format %{ "ADDSD $dst,$mem" %}
9846 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
9847 ins_pipe( pipe_slow );
9848 %}
9850 // Sub two double precision floating point values in xmm
9851 instruct subXD_reg(regXD dst, regXD src) %{
9852 predicate(UseSSE>=2);
9853 match(Set dst (SubD dst src));
9854 format %{ "SUBSD $dst,$src" %}
9855 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
9856 ins_pipe( pipe_slow );
9857 %}
9859 instruct subXD_imm(regXD dst, immXD con) %{
9860 predicate(UseSSE>=2);
9861 match(Set dst (SubD dst con));
9862 format %{ "SUBSD $dst,[$con]" %}
9863 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
9864 ins_pipe( pipe_slow );
9865 %}
9867 instruct subXD_mem(regXD dst, memory mem) %{
9868 predicate(UseSSE>=2);
9869 match(Set dst (SubD dst (LoadD mem)));
9870 format %{ "SUBSD $dst,$mem" %}
9871 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
9872 ins_pipe( pipe_slow );
9873 %}
9875 // Mul two double precision floating point values in xmm
9876 instruct mulXD_reg(regXD dst, regXD src) %{
9877 predicate(UseSSE>=2);
9878 match(Set dst (MulD dst src));
9879 format %{ "MULSD $dst,$src" %}
9880 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
9881 ins_pipe( pipe_slow );
9882 %}
9884 instruct mulXD_imm(regXD dst, immXD con) %{
9885 predicate(UseSSE>=2);
9886 match(Set dst (MulD dst con));
9887 format %{ "MULSD $dst,[$con]" %}
9888 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
9889 ins_pipe( pipe_slow );
9890 %}
9892 instruct mulXD_mem(regXD dst, memory mem) %{
9893 predicate(UseSSE>=2);
9894 match(Set dst (MulD dst (LoadD mem)));
9895 format %{ "MULSD $dst,$mem" %}
9896 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
9897 ins_pipe( pipe_slow );
9898 %}
9900 // Div two double precision floating point values in xmm
9901 instruct divXD_reg(regXD dst, regXD src) %{
9902 predicate(UseSSE>=2);
9903 match(Set dst (DivD dst src));
9904 format %{ "DIVSD $dst,$src" %}
9905 opcode(0xF2, 0x0F, 0x5E);
9906 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
9907 ins_pipe( pipe_slow );
9908 %}
9910 instruct divXD_imm(regXD dst, immXD con) %{
9911 predicate(UseSSE>=2);
9912 match(Set dst (DivD dst con));
9913 format %{ "DIVSD $dst,[$con]" %}
9914 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
9915 ins_pipe( pipe_slow );
9916 %}
9918 instruct divXD_mem(regXD dst, memory mem) %{
9919 predicate(UseSSE>=2);
9920 match(Set dst (DivD dst (LoadD mem)));
9921 format %{ "DIVSD $dst,$mem" %}
9922 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
9923 ins_pipe( pipe_slow );
9924 %}
9927 instruct mulD_reg(regD dst, regD src) %{
9928 predicate(UseSSE<=1);
9929 match(Set dst (MulD dst src));
9930 format %{ "FLD $src\n\t"
9931 "DMULp $dst,ST" %}
9932 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9933 ins_cost(150);
9934 ins_encode( Push_Reg_D(src),
9935 OpcP, RegOpc(dst) );
9936 ins_pipe( fpu_reg_reg );
9937 %}
9939 // Strict FP instruction biases argument before multiply then
9940 // biases result to avoid double rounding of subnormals.
9941 //
9942 // scale arg1 by multiplying arg1 by 2^(-15360)
9943 // load arg2
9944 // multiply scaled arg1 by arg2
9945 // rescale product by 2^(15360)
9946 //
9947 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
9948 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9949 match(Set dst (MulD dst src));
9950 ins_cost(1); // Select this instruction for all strict FP double multiplies
9952 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9953 "DMULp $dst,ST\n\t"
9954 "FLD $src\n\t"
9955 "DMULp $dst,ST\n\t"
9956 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9957 "DMULp $dst,ST\n\t" %}
9958 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9959 ins_encode( strictfp_bias1(dst),
9960 Push_Reg_D(src),
9961 OpcP, RegOpc(dst),
9962 strictfp_bias2(dst) );
9963 ins_pipe( fpu_reg_reg );
9964 %}
9966 instruct mulD_reg_imm(regD dst, immD src) %{
9967 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9968 match(Set dst (MulD dst src));
9969 ins_cost(200);
9970 format %{ "FLD_D [$src]\n\t"
9971 "DMULp $dst,ST" %}
9972 opcode(0xDE, 0x1); /* DE /1 */
9973 ins_encode( LdImmD(src),
9974 OpcP, RegOpc(dst) );
9975 ins_pipe( fpu_reg_mem );
9976 %}
9979 instruct mulD_reg_mem(regD dst, memory src) %{
9980 predicate( UseSSE<=1 );
9981 match(Set dst (MulD dst (LoadD src)));
9982 ins_cost(200);
9983 format %{ "FLD_D $src\n\t"
9984 "DMULp $dst,ST" %}
9985 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9986 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9987 OpcP, RegOpc(dst) );
9988 ins_pipe( fpu_reg_mem );
9989 %}
9991 //
9992 // Cisc-alternate to reg-reg multiply
9993 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
9994 predicate( UseSSE<=1 );
9995 match(Set dst (MulD src (LoadD mem)));
9996 ins_cost(250);
9997 format %{ "FLD_D $mem\n\t"
9998 "DMUL ST,$src\n\t"
9999 "FSTP_D $dst" %}
10000 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10001 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10002 OpcReg_F(src),
10003 Pop_Reg_D(dst) );
10004 ins_pipe( fpu_reg_reg_mem );
10005 %}
10008 // MACRO3 -- addD a mulD
10009 // This instruction is a '2-address' instruction in that the result goes
10010 // back to src2. This eliminates a move from the macro; possibly the
10011 // register allocator will have to add it back (and maybe not).
10012 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10013 predicate( UseSSE<=1 );
10014 match(Set src2 (AddD (MulD src0 src1) src2));
10015 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10016 "DMUL ST,$src1\n\t"
10017 "DADDp $src2,ST" %}
10018 ins_cost(250);
10019 opcode(0xDD); /* LoadD DD /0 */
10020 ins_encode( Push_Reg_F(src0),
10021 FMul_ST_reg(src1),
10022 FAddP_reg_ST(src2) );
10023 ins_pipe( fpu_reg_reg_reg );
10024 %}
10027 // MACRO3 -- subD a mulD
10028 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10029 predicate( UseSSE<=1 );
10030 match(Set src2 (SubD (MulD src0 src1) src2));
10031 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10032 "DMUL ST,$src1\n\t"
10033 "DSUBRp $src2,ST" %}
10034 ins_cost(250);
10035 ins_encode( Push_Reg_F(src0),
10036 FMul_ST_reg(src1),
10037 Opcode(0xDE), Opc_plus(0xE0,src2));
10038 ins_pipe( fpu_reg_reg_reg );
10039 %}
10042 instruct divD_reg(regD dst, regD src) %{
10043 predicate( UseSSE<=1 );
10044 match(Set dst (DivD dst src));
10046 format %{ "FLD $src\n\t"
10047 "FDIVp $dst,ST" %}
10048 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10049 ins_cost(150);
10050 ins_encode( Push_Reg_D(src),
10051 OpcP, RegOpc(dst) );
10052 ins_pipe( fpu_reg_reg );
10053 %}
10055 // Strict FP instruction biases argument before division then
10056 // biases result, to avoid double rounding of subnormals.
10057 //
10058 // scale dividend by multiplying dividend by 2^(-15360)
10059 // load divisor
10060 // divide scaled dividend by divisor
10061 // rescale quotient by 2^(15360)
10062 //
10063 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10064 predicate (UseSSE<=1);
10065 match(Set dst (DivD dst src));
10066 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10067 ins_cost(01);
10069 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10070 "DMULp $dst,ST\n\t"
10071 "FLD $src\n\t"
10072 "FDIVp $dst,ST\n\t"
10073 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10074 "DMULp $dst,ST\n\t" %}
10075 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10076 ins_encode( strictfp_bias1(dst),
10077 Push_Reg_D(src),
10078 OpcP, RegOpc(dst),
10079 strictfp_bias2(dst) );
10080 ins_pipe( fpu_reg_reg );
10081 %}
10083 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10084 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10085 match(Set dst (RoundDouble (DivD src1 src2)));
10087 format %{ "FLD $src1\n\t"
10088 "FDIV ST,$src2\n\t"
10089 "FSTP_D $dst\t# D-round" %}
10090 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10091 ins_encode( Push_Reg_D(src1),
10092 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10093 ins_pipe( fpu_mem_reg_reg );
10094 %}
10097 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10098 predicate(UseSSE<=1);
10099 match(Set dst (ModD dst src));
10100 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10102 format %{ "DMOD $dst,$src" %}
10103 ins_cost(250);
10104 ins_encode(Push_Reg_Mod_D(dst, src),
10105 emitModD(),
10106 Push_Result_Mod_D(src),
10107 Pop_Reg_D(dst));
10108 ins_pipe( pipe_slow );
10109 %}
10111 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10112 predicate(UseSSE>=2);
10113 match(Set dst (ModD src0 src1));
10114 effect(KILL rax, KILL cr);
10116 format %{ "SUB ESP,8\t # DMOD\n"
10117 "\tMOVSD [ESP+0],$src1\n"
10118 "\tFLD_D [ESP+0]\n"
10119 "\tMOVSD [ESP+0],$src0\n"
10120 "\tFLD_D [ESP+0]\n"
10121 "loop:\tFPREM\n"
10122 "\tFWAIT\n"
10123 "\tFNSTSW AX\n"
10124 "\tSAHF\n"
10125 "\tJP loop\n"
10126 "\tFSTP_D [ESP+0]\n"
10127 "\tMOVSD $dst,[ESP+0]\n"
10128 "\tADD ESP,8\n"
10129 "\tFSTP ST0\t # Restore FPU Stack"
10130 %}
10131 ins_cost(250);
10132 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10133 ins_pipe( pipe_slow );
10134 %}
10136 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10137 predicate (UseSSE<=1);
10138 match(Set dst (SinD src));
10139 ins_cost(1800);
10140 format %{ "DSIN $dst" %}
10141 opcode(0xD9, 0xFE);
10142 ins_encode( OpcP, OpcS );
10143 ins_pipe( pipe_slow );
10144 %}
10146 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10147 predicate (UseSSE>=2);
10148 match(Set dst (SinD dst));
10149 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10150 ins_cost(1800);
10151 format %{ "DSIN $dst" %}
10152 opcode(0xD9, 0xFE);
10153 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10154 ins_pipe( pipe_slow );
10155 %}
10157 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10158 predicate (UseSSE<=1);
10159 match(Set dst (CosD src));
10160 ins_cost(1800);
10161 format %{ "DCOS $dst" %}
10162 opcode(0xD9, 0xFF);
10163 ins_encode( OpcP, OpcS );
10164 ins_pipe( pipe_slow );
10165 %}
10167 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10168 predicate (UseSSE>=2);
10169 match(Set dst (CosD dst));
10170 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10171 ins_cost(1800);
10172 format %{ "DCOS $dst" %}
10173 opcode(0xD9, 0xFF);
10174 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10175 ins_pipe( pipe_slow );
10176 %}
10178 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10179 predicate (UseSSE<=1);
10180 match(Set dst(TanD src));
10181 format %{ "DTAN $dst" %}
10182 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10183 Opcode(0xDD), Opcode(0xD8)); // fstp st
10184 ins_pipe( pipe_slow );
10185 %}
10187 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10188 predicate (UseSSE>=2);
10189 match(Set dst(TanD dst));
10190 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10191 format %{ "DTAN $dst" %}
10192 ins_encode( Push_SrcXD(dst),
10193 Opcode(0xD9), Opcode(0xF2), // fptan
10194 Opcode(0xDD), Opcode(0xD8), // fstp st
10195 Push_ResultXD(dst) );
10196 ins_pipe( pipe_slow );
10197 %}
10199 instruct atanD_reg(regD dst, regD src) %{
10200 predicate (UseSSE<=1);
10201 match(Set dst(AtanD dst src));
10202 format %{ "DATA $dst,$src" %}
10203 opcode(0xD9, 0xF3);
10204 ins_encode( Push_Reg_D(src),
10205 OpcP, OpcS, RegOpc(dst) );
10206 ins_pipe( pipe_slow );
10207 %}
10209 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10210 predicate (UseSSE>=2);
10211 match(Set dst(AtanD dst src));
10212 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10213 format %{ "DATA $dst,$src" %}
10214 opcode(0xD9, 0xF3);
10215 ins_encode( Push_SrcXD(src),
10216 OpcP, OpcS, Push_ResultXD(dst) );
10217 ins_pipe( pipe_slow );
10218 %}
10220 instruct sqrtD_reg(regD dst, regD src) %{
10221 predicate (UseSSE<=1);
10222 match(Set dst (SqrtD src));
10223 format %{ "DSQRT $dst,$src" %}
10224 opcode(0xFA, 0xD9);
10225 ins_encode( Push_Reg_D(src),
10226 OpcS, OpcP, Pop_Reg_D(dst) );
10227 ins_pipe( pipe_slow );
10228 %}
10230 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10231 predicate (UseSSE<=1);
10232 match(Set Y (PowD X Y)); // Raise X to the Yth power
10233 effect(KILL rax, KILL rbx, KILL rcx);
10234 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10235 "FLD_D $X\n\t"
10236 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10238 "FDUP \t\t\t# Q Q\n\t"
10239 "FRNDINT\t\t\t# int(Q) Q\n\t"
10240 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10241 "FISTP dword [ESP]\n\t"
10242 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10243 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10244 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10245 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10246 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10247 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10248 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10249 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10250 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10251 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10252 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10253 "MOV [ESP+0],0\n\t"
10254 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10256 "ADD ESP,8"
10257 %}
10258 ins_encode( push_stack_temp_qword,
10259 Push_Reg_D(X),
10260 Opcode(0xD9), Opcode(0xF1), // fyl2x
10261 pow_exp_core_encoding,
10262 pop_stack_temp_qword);
10263 ins_pipe( pipe_slow );
10264 %}
10266 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10267 predicate (UseSSE>=2);
10268 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10269 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10270 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10271 "MOVSD [ESP],$src1\n\t"
10272 "FLD FPR1,$src1\n\t"
10273 "MOVSD [ESP],$src0\n\t"
10274 "FLD FPR1,$src0\n\t"
10275 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10277 "FDUP \t\t\t# Q Q\n\t"
10278 "FRNDINT\t\t\t# int(Q) Q\n\t"
10279 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10280 "FISTP dword [ESP]\n\t"
10281 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10282 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10283 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10284 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10285 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10286 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10287 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10288 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10289 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10290 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10291 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10292 "MOV [ESP+0],0\n\t"
10293 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10295 "FST_D [ESP]\n\t"
10296 "MOVSD $dst,[ESP]\n\t"
10297 "ADD ESP,8"
10298 %}
10299 ins_encode( push_stack_temp_qword,
10300 push_xmm_to_fpr1(src1),
10301 push_xmm_to_fpr1(src0),
10302 Opcode(0xD9), Opcode(0xF1), // fyl2x
10303 pow_exp_core_encoding,
10304 Push_ResultXD(dst) );
10305 ins_pipe( pipe_slow );
10306 %}
10309 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10310 predicate (UseSSE<=1);
10311 match(Set dpr1 (ExpD dpr1));
10312 effect(KILL rax, KILL rbx, KILL rcx);
10313 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10314 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10315 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10317 "FDUP \t\t\t# Q Q\n\t"
10318 "FRNDINT\t\t\t# int(Q) Q\n\t"
10319 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10320 "FISTP dword [ESP]\n\t"
10321 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10322 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10323 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10324 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10325 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10326 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10327 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10328 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10329 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10330 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10331 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10332 "MOV [ESP+0],0\n\t"
10333 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10335 "ADD ESP,8"
10336 %}
10337 ins_encode( push_stack_temp_qword,
10338 Opcode(0xD9), Opcode(0xEA), // fldl2e
10339 Opcode(0xDE), Opcode(0xC9), // fmulp
10340 pow_exp_core_encoding,
10341 pop_stack_temp_qword);
10342 ins_pipe( pipe_slow );
10343 %}
10345 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10346 predicate (UseSSE>=2);
10347 match(Set dst (ExpD src));
10348 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10349 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10350 "MOVSD [ESP],$src\n\t"
10351 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10352 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10354 "FDUP \t\t\t# Q Q\n\t"
10355 "FRNDINT\t\t\t# int(Q) Q\n\t"
10356 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10357 "FISTP dword [ESP]\n\t"
10358 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10359 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10360 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10361 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10362 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10363 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10364 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10365 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10366 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10367 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10368 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10369 "MOV [ESP+0],0\n\t"
10370 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10372 "FST_D [ESP]\n\t"
10373 "MOVSD $dst,[ESP]\n\t"
10374 "ADD ESP,8"
10375 %}
10376 ins_encode( Push_SrcXD(src),
10377 Opcode(0xD9), Opcode(0xEA), // fldl2e
10378 Opcode(0xDE), Opcode(0xC9), // fmulp
10379 pow_exp_core_encoding,
10380 Push_ResultXD(dst) );
10381 ins_pipe( pipe_slow );
10382 %}
10386 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10387 predicate (UseSSE<=1);
10388 // The source Double operand on FPU stack
10389 match(Set dst (Log10D src));
10390 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10391 // fxch ; swap ST(0) with ST(1)
10392 // fyl2x ; compute log_10(2) * log_2(x)
10393 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10394 "FXCH \n\t"
10395 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10396 %}
10397 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10398 Opcode(0xD9), Opcode(0xC9), // fxch
10399 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10401 ins_pipe( pipe_slow );
10402 %}
10404 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10405 predicate (UseSSE>=2);
10406 effect(KILL cr);
10407 match(Set dst (Log10D src));
10408 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10409 // fyl2x ; compute log_10(2) * log_2(x)
10410 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10411 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10412 %}
10413 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10414 Push_SrcXD(src),
10415 Opcode(0xD9), Opcode(0xF1), // fyl2x
10416 Push_ResultXD(dst));
10418 ins_pipe( pipe_slow );
10419 %}
10421 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10422 predicate (UseSSE<=1);
10423 // The source Double operand on FPU stack
10424 match(Set dst (LogD src));
10425 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10426 // fxch ; swap ST(0) with ST(1)
10427 // fyl2x ; compute log_e(2) * log_2(x)
10428 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10429 "FXCH \n\t"
10430 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10431 %}
10432 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10433 Opcode(0xD9), Opcode(0xC9), // fxch
10434 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10436 ins_pipe( pipe_slow );
10437 %}
10439 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10440 predicate (UseSSE>=2);
10441 effect(KILL cr);
10442 // The source and result Double operands in XMM registers
10443 match(Set dst (LogD src));
10444 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10445 // fyl2x ; compute log_e(2) * log_2(x)
10446 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10447 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10448 %}
10449 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10450 Push_SrcXD(src),
10451 Opcode(0xD9), Opcode(0xF1), // fyl2x
10452 Push_ResultXD(dst));
10453 ins_pipe( pipe_slow );
10454 %}
10456 //-------------Float Instructions-------------------------------
10457 // Float Math
10459 // Code for float compare:
10460 // fcompp();
10461 // fwait(); fnstsw_ax();
10462 // sahf();
10463 // movl(dst, unordered_result);
10464 // jcc(Assembler::parity, exit);
10465 // movl(dst, less_result);
10466 // jcc(Assembler::below, exit);
10467 // movl(dst, equal_result);
10468 // jcc(Assembler::equal, exit);
10469 // movl(dst, greater_result);
10470 // exit:
10472 // P6 version of float compare, sets condition codes in EFLAGS
10473 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10474 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10475 match(Set cr (CmpF src1 src2));
10476 effect(KILL rax);
10477 ins_cost(150);
10478 format %{ "FLD $src1\n\t"
10479 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10480 "JNP exit\n\t"
10481 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10482 "SAHF\n"
10483 "exit:\tNOP // avoid branch to branch" %}
10484 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10485 ins_encode( Push_Reg_D(src1),
10486 OpcP, RegOpc(src2),
10487 cmpF_P6_fixup );
10488 ins_pipe( pipe_slow );
10489 %}
10491 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10492 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10493 match(Set cr (CmpF src1 src2));
10494 ins_cost(100);
10495 format %{ "FLD $src1\n\t"
10496 "FUCOMIP ST,$src2 // P6 instruction" %}
10497 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10498 ins_encode( Push_Reg_D(src1),
10499 OpcP, RegOpc(src2));
10500 ins_pipe( pipe_slow );
10501 %}
10504 // Compare & branch
10505 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10506 predicate(UseSSE == 0);
10507 match(Set cr (CmpF src1 src2));
10508 effect(KILL rax);
10509 ins_cost(200);
10510 format %{ "FLD $src1\n\t"
10511 "FCOMp $src2\n\t"
10512 "FNSTSW AX\n\t"
10513 "TEST AX,0x400\n\t"
10514 "JZ,s flags\n\t"
10515 "MOV AH,1\t# unordered treat as LT\n"
10516 "flags:\tSAHF" %}
10517 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10518 ins_encode( Push_Reg_D(src1),
10519 OpcP, RegOpc(src2),
10520 fpu_flags);
10521 ins_pipe( pipe_slow );
10522 %}
10524 // Compare vs zero into -1,0,1
10525 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10526 predicate(UseSSE == 0);
10527 match(Set dst (CmpF3 src1 zero));
10528 effect(KILL cr, KILL rax);
10529 ins_cost(280);
10530 format %{ "FTSTF $dst,$src1" %}
10531 opcode(0xE4, 0xD9);
10532 ins_encode( Push_Reg_D(src1),
10533 OpcS, OpcP, PopFPU,
10534 CmpF_Result(dst));
10535 ins_pipe( pipe_slow );
10536 %}
10538 // Compare into -1,0,1
10539 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10540 predicate(UseSSE == 0);
10541 match(Set dst (CmpF3 src1 src2));
10542 effect(KILL cr, KILL rax);
10543 ins_cost(300);
10544 format %{ "FCMPF $dst,$src1,$src2" %}
10545 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10546 ins_encode( Push_Reg_D(src1),
10547 OpcP, RegOpc(src2),
10548 CmpF_Result(dst));
10549 ins_pipe( pipe_slow );
10550 %}
10552 // float compare and set condition codes in EFLAGS by XMM regs
10553 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10554 predicate(UseSSE>=1);
10555 match(Set cr (CmpF dst src));
10556 effect(KILL rax);
10557 ins_cost(145);
10558 format %{ "COMISS $dst,$src\n"
10559 "\tJNP exit\n"
10560 "\tMOV ah,1 // saw a NaN, set CF\n"
10561 "\tSAHF\n"
10562 "exit:\tNOP // avoid branch to branch" %}
10563 opcode(0x0F, 0x2F);
10564 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10565 ins_pipe( pipe_slow );
10566 %}
10568 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10569 predicate(UseSSE>=1);
10570 match(Set cr (CmpF dst src));
10571 ins_cost(100);
10572 format %{ "COMISS $dst,$src" %}
10573 opcode(0x0F, 0x2F);
10574 ins_encode(OpcP, OpcS, RegReg(dst, src));
10575 ins_pipe( pipe_slow );
10576 %}
10578 // float compare and set condition codes in EFLAGS by XMM regs
10579 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10580 predicate(UseSSE>=1);
10581 match(Set cr (CmpF dst (LoadF src)));
10582 effect(KILL rax);
10583 ins_cost(165);
10584 format %{ "COMISS $dst,$src\n"
10585 "\tJNP exit\n"
10586 "\tMOV ah,1 // saw a NaN, set CF\n"
10587 "\tSAHF\n"
10588 "exit:\tNOP // avoid branch to branch" %}
10589 opcode(0x0F, 0x2F);
10590 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10591 ins_pipe( pipe_slow );
10592 %}
10594 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10595 predicate(UseSSE>=1);
10596 match(Set cr (CmpF dst (LoadF src)));
10597 ins_cost(100);
10598 format %{ "COMISS $dst,$src" %}
10599 opcode(0x0F, 0x2F);
10600 ins_encode(OpcP, OpcS, RegMem(dst, src));
10601 ins_pipe( pipe_slow );
10602 %}
10604 // Compare into -1,0,1 in XMM
10605 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10606 predicate(UseSSE>=1);
10607 match(Set dst (CmpF3 src1 src2));
10608 effect(KILL cr);
10609 ins_cost(255);
10610 format %{ "XOR $dst,$dst\n"
10611 "\tCOMISS $src1,$src2\n"
10612 "\tJP,s nan\n"
10613 "\tJEQ,s exit\n"
10614 "\tJA,s inc\n"
10615 "nan:\tDEC $dst\n"
10616 "\tJMP,s exit\n"
10617 "inc:\tINC $dst\n"
10618 "exit:"
10619 %}
10620 opcode(0x0F, 0x2F);
10621 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10622 ins_pipe( pipe_slow );
10623 %}
10625 // Compare into -1,0,1 in XMM and memory
10626 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10627 predicate(UseSSE>=1);
10628 match(Set dst (CmpF3 src1 (LoadF mem)));
10629 effect(KILL cr);
10630 ins_cost(275);
10631 format %{ "COMISS $src1,$mem\n"
10632 "\tMOV $dst,0\t\t# do not blow flags\n"
10633 "\tJP,s nan\n"
10634 "\tJEQ,s exit\n"
10635 "\tJA,s inc\n"
10636 "nan:\tDEC $dst\n"
10637 "\tJMP,s exit\n"
10638 "inc:\tINC $dst\n"
10639 "exit:"
10640 %}
10641 opcode(0x0F, 0x2F);
10642 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10643 ins_pipe( pipe_slow );
10644 %}
10646 // Spill to obtain 24-bit precision
10647 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10648 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10649 match(Set dst (SubF src1 src2));
10651 format %{ "FSUB $dst,$src1 - $src2" %}
10652 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10653 ins_encode( Push_Reg_F(src1),
10654 OpcReg_F(src2),
10655 Pop_Mem_F(dst) );
10656 ins_pipe( fpu_mem_reg_reg );
10657 %}
10658 //
10659 // This instruction does not round to 24-bits
10660 instruct subF_reg(regF dst, regF src) %{
10661 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10662 match(Set dst (SubF dst src));
10664 format %{ "FSUB $dst,$src" %}
10665 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10666 ins_encode( Push_Reg_F(src),
10667 OpcP, RegOpc(dst) );
10668 ins_pipe( fpu_reg_reg );
10669 %}
10671 // Spill to obtain 24-bit precision
10672 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10673 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10674 match(Set dst (AddF src1 src2));
10676 format %{ "FADD $dst,$src1,$src2" %}
10677 opcode(0xD8, 0x0); /* D8 C0+i */
10678 ins_encode( Push_Reg_F(src2),
10679 OpcReg_F(src1),
10680 Pop_Mem_F(dst) );
10681 ins_pipe( fpu_mem_reg_reg );
10682 %}
10683 //
10684 // This instruction does not round to 24-bits
10685 instruct addF_reg(regF dst, regF src) %{
10686 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10687 match(Set dst (AddF dst src));
10689 format %{ "FLD $src\n\t"
10690 "FADDp $dst,ST" %}
10691 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10692 ins_encode( Push_Reg_F(src),
10693 OpcP, RegOpc(dst) );
10694 ins_pipe( fpu_reg_reg );
10695 %}
10697 // Add two single precision floating point values in xmm
10698 instruct addX_reg(regX dst, regX src) %{
10699 predicate(UseSSE>=1);
10700 match(Set dst (AddF dst src));
10701 format %{ "ADDSS $dst,$src" %}
10702 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10703 ins_pipe( pipe_slow );
10704 %}
10706 instruct addX_imm(regX dst, immXF con) %{
10707 predicate(UseSSE>=1);
10708 match(Set dst (AddF dst con));
10709 format %{ "ADDSS $dst,[$con]" %}
10710 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10711 ins_pipe( pipe_slow );
10712 %}
10714 instruct addX_mem(regX dst, memory mem) %{
10715 predicate(UseSSE>=1);
10716 match(Set dst (AddF dst (LoadF mem)));
10717 format %{ "ADDSS $dst,$mem" %}
10718 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10719 ins_pipe( pipe_slow );
10720 %}
10722 // Subtract two single precision floating point values in xmm
10723 instruct subX_reg(regX dst, regX src) %{
10724 predicate(UseSSE>=1);
10725 match(Set dst (SubF dst src));
10726 format %{ "SUBSS $dst,$src" %}
10727 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10728 ins_pipe( pipe_slow );
10729 %}
10731 instruct subX_imm(regX dst, immXF con) %{
10732 predicate(UseSSE>=1);
10733 match(Set dst (SubF dst con));
10734 format %{ "SUBSS $dst,[$con]" %}
10735 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10736 ins_pipe( pipe_slow );
10737 %}
10739 instruct subX_mem(regX dst, memory mem) %{
10740 predicate(UseSSE>=1);
10741 match(Set dst (SubF dst (LoadF mem)));
10742 format %{ "SUBSS $dst,$mem" %}
10743 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10744 ins_pipe( pipe_slow );
10745 %}
10747 // Multiply two single precision floating point values in xmm
10748 instruct mulX_reg(regX dst, regX src) %{
10749 predicate(UseSSE>=1);
10750 match(Set dst (MulF dst src));
10751 format %{ "MULSS $dst,$src" %}
10752 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10753 ins_pipe( pipe_slow );
10754 %}
10756 instruct mulX_imm(regX dst, immXF con) %{
10757 predicate(UseSSE>=1);
10758 match(Set dst (MulF dst con));
10759 format %{ "MULSS $dst,[$con]" %}
10760 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10761 ins_pipe( pipe_slow );
10762 %}
10764 instruct mulX_mem(regX dst, memory mem) %{
10765 predicate(UseSSE>=1);
10766 match(Set dst (MulF dst (LoadF mem)));
10767 format %{ "MULSS $dst,$mem" %}
10768 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10769 ins_pipe( pipe_slow );
10770 %}
10772 // Divide two single precision floating point values in xmm
10773 instruct divX_reg(regX dst, regX src) %{
10774 predicate(UseSSE>=1);
10775 match(Set dst (DivF dst src));
10776 format %{ "DIVSS $dst,$src" %}
10777 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10778 ins_pipe( pipe_slow );
10779 %}
10781 instruct divX_imm(regX dst, immXF con) %{
10782 predicate(UseSSE>=1);
10783 match(Set dst (DivF dst con));
10784 format %{ "DIVSS $dst,[$con]" %}
10785 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
10786 ins_pipe( pipe_slow );
10787 %}
10789 instruct divX_mem(regX dst, memory mem) %{
10790 predicate(UseSSE>=1);
10791 match(Set dst (DivF dst (LoadF mem)));
10792 format %{ "DIVSS $dst,$mem" %}
10793 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10794 ins_pipe( pipe_slow );
10795 %}
10797 // Get the square root of a single precision floating point values in xmm
10798 instruct sqrtX_reg(regX dst, regX src) %{
10799 predicate(UseSSE>=1);
10800 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10801 format %{ "SQRTSS $dst,$src" %}
10802 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10803 ins_pipe( pipe_slow );
10804 %}
10806 instruct sqrtX_mem(regX dst, memory mem) %{
10807 predicate(UseSSE>=1);
10808 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10809 format %{ "SQRTSS $dst,$mem" %}
10810 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10811 ins_pipe( pipe_slow );
10812 %}
10814 // Get the square root of a double precision floating point values in xmm
10815 instruct sqrtXD_reg(regXD dst, regXD src) %{
10816 predicate(UseSSE>=2);
10817 match(Set dst (SqrtD src));
10818 format %{ "SQRTSD $dst,$src" %}
10819 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10820 ins_pipe( pipe_slow );
10821 %}
10823 instruct sqrtXD_mem(regXD dst, memory mem) %{
10824 predicate(UseSSE>=2);
10825 match(Set dst (SqrtD (LoadD mem)));
10826 format %{ "SQRTSD $dst,$mem" %}
10827 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10828 ins_pipe( pipe_slow );
10829 %}
10831 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
10832 predicate(UseSSE==0);
10833 match(Set dst (AbsF src));
10834 ins_cost(100);
10835 format %{ "FABS" %}
10836 opcode(0xE1, 0xD9);
10837 ins_encode( OpcS, OpcP );
10838 ins_pipe( fpu_reg_reg );
10839 %}
10841 instruct absX_reg(regX dst ) %{
10842 predicate(UseSSE>=1);
10843 match(Set dst (AbsF dst));
10844 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
10845 ins_encode( AbsXF_encoding(dst));
10846 ins_pipe( pipe_slow );
10847 %}
10849 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
10850 predicate(UseSSE==0);
10851 match(Set dst (NegF src));
10852 ins_cost(100);
10853 format %{ "FCHS" %}
10854 opcode(0xE0, 0xD9);
10855 ins_encode( OpcS, OpcP );
10856 ins_pipe( fpu_reg_reg );
10857 %}
10859 instruct negX_reg( regX dst ) %{
10860 predicate(UseSSE>=1);
10861 match(Set dst (NegF dst));
10862 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
10863 ins_encode( NegXF_encoding(dst));
10864 ins_pipe( pipe_slow );
10865 %}
10867 // Cisc-alternate to addF_reg
10868 // Spill to obtain 24-bit precision
10869 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10870 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10871 match(Set dst (AddF src1 (LoadF src2)));
10873 format %{ "FLD $src2\n\t"
10874 "FADD ST,$src1\n\t"
10875 "FSTP_S $dst" %}
10876 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10877 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10878 OpcReg_F(src1),
10879 Pop_Mem_F(dst) );
10880 ins_pipe( fpu_mem_reg_mem );
10881 %}
10882 //
10883 // Cisc-alternate to addF_reg
10884 // This instruction does not round to 24-bits
10885 instruct addF_reg_mem(regF dst, memory src) %{
10886 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10887 match(Set dst (AddF dst (LoadF src)));
10889 format %{ "FADD $dst,$src" %}
10890 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10891 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10892 OpcP, RegOpc(dst) );
10893 ins_pipe( fpu_reg_mem );
10894 %}
10896 // // Following two instructions for _222_mpegaudio
10897 // Spill to obtain 24-bit precision
10898 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
10899 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10900 match(Set dst (AddF src1 src2));
10902 format %{ "FADD $dst,$src1,$src2" %}
10903 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10904 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10905 OpcReg_F(src2),
10906 Pop_Mem_F(dst) );
10907 ins_pipe( fpu_mem_reg_mem );
10908 %}
10910 // Cisc-spill variant
10911 // Spill to obtain 24-bit precision
10912 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10913 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10914 match(Set dst (AddF src1 (LoadF src2)));
10916 format %{ "FADD $dst,$src1,$src2 cisc" %}
10917 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10918 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10919 set_instruction_start,
10920 OpcP, RMopc_Mem(secondary,src1),
10921 Pop_Mem_F(dst) );
10922 ins_pipe( fpu_mem_mem_mem );
10923 %}
10925 // Spill to obtain 24-bit precision
10926 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10927 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10928 match(Set dst (AddF src1 src2));
10930 format %{ "FADD $dst,$src1,$src2" %}
10931 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10932 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10933 set_instruction_start,
10934 OpcP, RMopc_Mem(secondary,src1),
10935 Pop_Mem_F(dst) );
10936 ins_pipe( fpu_mem_mem_mem );
10937 %}
10940 // Spill to obtain 24-bit precision
10941 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10942 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10943 match(Set dst (AddF src1 src2));
10944 format %{ "FLD $src1\n\t"
10945 "FADD $src2\n\t"
10946 "FSTP_S $dst" %}
10947 opcode(0xD8, 0x00); /* D8 /0 */
10948 ins_encode( Push_Reg_F(src1),
10949 Opc_MemImm_F(src2),
10950 Pop_Mem_F(dst));
10951 ins_pipe( fpu_mem_reg_con );
10952 %}
10953 //
10954 // This instruction does not round to 24-bits
10955 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
10956 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10957 match(Set dst (AddF src1 src2));
10958 format %{ "FLD $src1\n\t"
10959 "FADD $src2\n\t"
10960 "FSTP_S $dst" %}
10961 opcode(0xD8, 0x00); /* D8 /0 */
10962 ins_encode( Push_Reg_F(src1),
10963 Opc_MemImm_F(src2),
10964 Pop_Reg_F(dst));
10965 ins_pipe( fpu_reg_reg_con );
10966 %}
10968 // Spill to obtain 24-bit precision
10969 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
10970 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10971 match(Set dst (MulF src1 src2));
10973 format %{ "FLD $src1\n\t"
10974 "FMUL $src2\n\t"
10975 "FSTP_S $dst" %}
10976 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10977 ins_encode( Push_Reg_F(src1),
10978 OpcReg_F(src2),
10979 Pop_Mem_F(dst) );
10980 ins_pipe( fpu_mem_reg_reg );
10981 %}
10982 //
10983 // This instruction does not round to 24-bits
10984 instruct mulF_reg(regF dst, regF src1, regF src2) %{
10985 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10986 match(Set dst (MulF src1 src2));
10988 format %{ "FLD $src1\n\t"
10989 "FMUL $src2\n\t"
10990 "FSTP_S $dst" %}
10991 opcode(0xD8, 0x1); /* D8 C8+i */
10992 ins_encode( Push_Reg_F(src2),
10993 OpcReg_F(src1),
10994 Pop_Reg_F(dst) );
10995 ins_pipe( fpu_reg_reg_reg );
10996 %}
10999 // Spill to obtain 24-bit precision
11000 // Cisc-alternate to reg-reg multiply
11001 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11002 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11003 match(Set dst (MulF src1 (LoadF src2)));
11005 format %{ "FLD_S $src2\n\t"
11006 "FMUL $src1\n\t"
11007 "FSTP_S $dst" %}
11008 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11009 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11010 OpcReg_F(src1),
11011 Pop_Mem_F(dst) );
11012 ins_pipe( fpu_mem_reg_mem );
11013 %}
11014 //
11015 // This instruction does not round to 24-bits
11016 // Cisc-alternate to reg-reg multiply
11017 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11018 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11019 match(Set dst (MulF src1 (LoadF src2)));
11021 format %{ "FMUL $dst,$src1,$src2" %}
11022 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11023 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11024 OpcReg_F(src1),
11025 Pop_Reg_F(dst) );
11026 ins_pipe( fpu_reg_reg_mem );
11027 %}
11029 // Spill to obtain 24-bit precision
11030 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11031 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11032 match(Set dst (MulF src1 src2));
11034 format %{ "FMUL $dst,$src1,$src2" %}
11035 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11036 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11037 set_instruction_start,
11038 OpcP, RMopc_Mem(secondary,src1),
11039 Pop_Mem_F(dst) );
11040 ins_pipe( fpu_mem_mem_mem );
11041 %}
11043 // Spill to obtain 24-bit precision
11044 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11045 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11046 match(Set dst (MulF src1 src2));
11048 format %{ "FMULc $dst,$src1,$src2" %}
11049 opcode(0xD8, 0x1); /* D8 /1*/
11050 ins_encode( Push_Reg_F(src1),
11051 Opc_MemImm_F(src2),
11052 Pop_Mem_F(dst));
11053 ins_pipe( fpu_mem_reg_con );
11054 %}
11055 //
11056 // This instruction does not round to 24-bits
11057 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11058 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11059 match(Set dst (MulF src1 src2));
11061 format %{ "FMULc $dst. $src1, $src2" %}
11062 opcode(0xD8, 0x1); /* D8 /1*/
11063 ins_encode( Push_Reg_F(src1),
11064 Opc_MemImm_F(src2),
11065 Pop_Reg_F(dst));
11066 ins_pipe( fpu_reg_reg_con );
11067 %}
11070 //
11071 // MACRO1 -- subsume unshared load into mulF
11072 // This instruction does not round to 24-bits
11073 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11074 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11075 match(Set dst (MulF (LoadF mem1) src));
11077 format %{ "FLD $mem1 ===MACRO1===\n\t"
11078 "FMUL ST,$src\n\t"
11079 "FSTP $dst" %}
11080 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11081 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11082 OpcReg_F(src),
11083 Pop_Reg_F(dst) );
11084 ins_pipe( fpu_reg_reg_mem );
11085 %}
11086 //
11087 // MACRO2 -- addF a mulF which subsumed an unshared load
11088 // This instruction does not round to 24-bits
11089 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11090 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11091 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11092 ins_cost(95);
11094 format %{ "FLD $mem1 ===MACRO2===\n\t"
11095 "FMUL ST,$src1 subsume mulF left load\n\t"
11096 "FADD ST,$src2\n\t"
11097 "FSTP $dst" %}
11098 opcode(0xD9); /* LoadF D9 /0 */
11099 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11100 FMul_ST_reg(src1),
11101 FAdd_ST_reg(src2),
11102 Pop_Reg_F(dst) );
11103 ins_pipe( fpu_reg_mem_reg_reg );
11104 %}
11106 // MACRO3 -- addF a mulF
11107 // This instruction does not round to 24-bits. It is a '2-address'
11108 // instruction in that the result goes back to src2. This eliminates
11109 // a move from the macro; possibly the register allocator will have
11110 // to add it back (and maybe not).
11111 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11112 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11113 match(Set src2 (AddF (MulF src0 src1) src2));
11115 format %{ "FLD $src0 ===MACRO3===\n\t"
11116 "FMUL ST,$src1\n\t"
11117 "FADDP $src2,ST" %}
11118 opcode(0xD9); /* LoadF D9 /0 */
11119 ins_encode( Push_Reg_F(src0),
11120 FMul_ST_reg(src1),
11121 FAddP_reg_ST(src2) );
11122 ins_pipe( fpu_reg_reg_reg );
11123 %}
11125 // MACRO4 -- divF subF
11126 // This instruction does not round to 24-bits
11127 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11128 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11129 match(Set dst (DivF (SubF src2 src1) src3));
11131 format %{ "FLD $src2 ===MACRO4===\n\t"
11132 "FSUB ST,$src1\n\t"
11133 "FDIV ST,$src3\n\t"
11134 "FSTP $dst" %}
11135 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11136 ins_encode( Push_Reg_F(src2),
11137 subF_divF_encode(src1,src3),
11138 Pop_Reg_F(dst) );
11139 ins_pipe( fpu_reg_reg_reg_reg );
11140 %}
11142 // Spill to obtain 24-bit precision
11143 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11144 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11145 match(Set dst (DivF src1 src2));
11147 format %{ "FDIV $dst,$src1,$src2" %}
11148 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11149 ins_encode( Push_Reg_F(src1),
11150 OpcReg_F(src2),
11151 Pop_Mem_F(dst) );
11152 ins_pipe( fpu_mem_reg_reg );
11153 %}
11154 //
11155 // This instruction does not round to 24-bits
11156 instruct divF_reg(regF dst, regF src) %{
11157 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11158 match(Set dst (DivF dst src));
11160 format %{ "FDIV $dst,$src" %}
11161 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11162 ins_encode( Push_Reg_F(src),
11163 OpcP, RegOpc(dst) );
11164 ins_pipe( fpu_reg_reg );
11165 %}
11168 // Spill to obtain 24-bit precision
11169 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11170 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11171 match(Set dst (ModF src1 src2));
11172 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11174 format %{ "FMOD $dst,$src1,$src2" %}
11175 ins_encode( Push_Reg_Mod_D(src1, src2),
11176 emitModD(),
11177 Push_Result_Mod_D(src2),
11178 Pop_Mem_F(dst));
11179 ins_pipe( pipe_slow );
11180 %}
11181 //
11182 // This instruction does not round to 24-bits
11183 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11184 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11185 match(Set dst (ModF dst src));
11186 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11188 format %{ "FMOD $dst,$src" %}
11189 ins_encode(Push_Reg_Mod_D(dst, src),
11190 emitModD(),
11191 Push_Result_Mod_D(src),
11192 Pop_Reg_F(dst));
11193 ins_pipe( pipe_slow );
11194 %}
11196 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11197 predicate(UseSSE>=1);
11198 match(Set dst (ModF src0 src1));
11199 effect(KILL rax, KILL cr);
11200 format %{ "SUB ESP,4\t # FMOD\n"
11201 "\tMOVSS [ESP+0],$src1\n"
11202 "\tFLD_S [ESP+0]\n"
11203 "\tMOVSS [ESP+0],$src0\n"
11204 "\tFLD_S [ESP+0]\n"
11205 "loop:\tFPREM\n"
11206 "\tFWAIT\n"
11207 "\tFNSTSW AX\n"
11208 "\tSAHF\n"
11209 "\tJP loop\n"
11210 "\tFSTP_S [ESP+0]\n"
11211 "\tMOVSS $dst,[ESP+0]\n"
11212 "\tADD ESP,4\n"
11213 "\tFSTP ST0\t # Restore FPU Stack"
11214 %}
11215 ins_cost(250);
11216 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11217 ins_pipe( pipe_slow );
11218 %}
11221 //----------Arithmetic Conversion Instructions---------------------------------
11222 // The conversions operations are all Alpha sorted. Please keep it that way!
11224 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11225 predicate(UseSSE==0);
11226 match(Set dst (RoundFloat src));
11227 ins_cost(125);
11228 format %{ "FST_S $dst,$src\t# F-round" %}
11229 ins_encode( Pop_Mem_Reg_F(dst, src) );
11230 ins_pipe( fpu_mem_reg );
11231 %}
11233 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11234 predicate(UseSSE<=1);
11235 match(Set dst (RoundDouble src));
11236 ins_cost(125);
11237 format %{ "FST_D $dst,$src\t# D-round" %}
11238 ins_encode( Pop_Mem_Reg_D(dst, src) );
11239 ins_pipe( fpu_mem_reg );
11240 %}
11242 // Force rounding to 24-bit precision and 6-bit exponent
11243 instruct convD2F_reg(stackSlotF dst, regD src) %{
11244 predicate(UseSSE==0);
11245 match(Set dst (ConvD2F src));
11246 format %{ "FST_S $dst,$src\t# F-round" %}
11247 expand %{
11248 roundFloat_mem_reg(dst,src);
11249 %}
11250 %}
11252 // Force rounding to 24-bit precision and 6-bit exponent
11253 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11254 predicate(UseSSE==1);
11255 match(Set dst (ConvD2F src));
11256 effect( KILL cr );
11257 format %{ "SUB ESP,4\n\t"
11258 "FST_S [ESP],$src\t# F-round\n\t"
11259 "MOVSS $dst,[ESP]\n\t"
11260 "ADD ESP,4" %}
11261 ins_encode( D2X_encoding(dst, src) );
11262 ins_pipe( pipe_slow );
11263 %}
11265 // Force rounding double precision to single precision
11266 instruct convXD2X_reg(regX dst, regXD src) %{
11267 predicate(UseSSE>=2);
11268 match(Set dst (ConvD2F src));
11269 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11270 opcode(0xF2, 0x0F, 0x5A);
11271 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11272 ins_pipe( pipe_slow );
11273 %}
11275 instruct convF2D_reg_reg(regD dst, regF src) %{
11276 predicate(UseSSE==0);
11277 match(Set dst (ConvF2D src));
11278 format %{ "FST_S $dst,$src\t# D-round" %}
11279 ins_encode( Pop_Reg_Reg_D(dst, src));
11280 ins_pipe( fpu_reg_reg );
11281 %}
11283 instruct convF2D_reg(stackSlotD dst, regF src) %{
11284 predicate(UseSSE==1);
11285 match(Set dst (ConvF2D src));
11286 format %{ "FST_D $dst,$src\t# D-round" %}
11287 expand %{
11288 roundDouble_mem_reg(dst,src);
11289 %}
11290 %}
11292 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11293 predicate(UseSSE==1);
11294 match(Set dst (ConvF2D src));
11295 effect( KILL cr );
11296 format %{ "SUB ESP,4\n\t"
11297 "MOVSS [ESP] $src\n\t"
11298 "FLD_S [ESP]\n\t"
11299 "ADD ESP,4\n\t"
11300 "FSTP $dst\t# D-round" %}
11301 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11302 ins_pipe( pipe_slow );
11303 %}
11305 instruct convX2XD_reg(regXD dst, regX src) %{
11306 predicate(UseSSE>=2);
11307 match(Set dst (ConvF2D src));
11308 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11309 opcode(0xF3, 0x0F, 0x5A);
11310 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11311 ins_pipe( pipe_slow );
11312 %}
11314 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11315 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11316 predicate(UseSSE<=1);
11317 match(Set dst (ConvD2I src));
11318 effect( KILL tmp, KILL cr );
11319 format %{ "FLD $src\t# Convert double to int \n\t"
11320 "FLDCW trunc mode\n\t"
11321 "SUB ESP,4\n\t"
11322 "FISTp [ESP + #0]\n\t"
11323 "FLDCW std/24-bit mode\n\t"
11324 "POP EAX\n\t"
11325 "CMP EAX,0x80000000\n\t"
11326 "JNE,s fast\n\t"
11327 "FLD_D $src\n\t"
11328 "CALL d2i_wrapper\n"
11329 "fast:" %}
11330 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11331 ins_pipe( pipe_slow );
11332 %}
11334 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11335 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11336 predicate(UseSSE>=2);
11337 match(Set dst (ConvD2I src));
11338 effect( KILL tmp, KILL cr );
11339 format %{ "CVTTSD2SI $dst, $src\n\t"
11340 "CMP $dst,0x80000000\n\t"
11341 "JNE,s fast\n\t"
11342 "SUB ESP, 8\n\t"
11343 "MOVSD [ESP], $src\n\t"
11344 "FLD_D [ESP]\n\t"
11345 "ADD ESP, 8\n\t"
11346 "CALL d2i_wrapper\n"
11347 "fast:" %}
11348 opcode(0x1); // double-precision conversion
11349 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11350 ins_pipe( pipe_slow );
11351 %}
11353 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11354 predicate(UseSSE<=1);
11355 match(Set dst (ConvD2L src));
11356 effect( KILL cr );
11357 format %{ "FLD $src\t# Convert double to long\n\t"
11358 "FLDCW trunc mode\n\t"
11359 "SUB ESP,8\n\t"
11360 "FISTp [ESP + #0]\n\t"
11361 "FLDCW std/24-bit mode\n\t"
11362 "POP EAX\n\t"
11363 "POP EDX\n\t"
11364 "CMP EDX,0x80000000\n\t"
11365 "JNE,s fast\n\t"
11366 "TEST EAX,EAX\n\t"
11367 "JNE,s fast\n\t"
11368 "FLD $src\n\t"
11369 "CALL d2l_wrapper\n"
11370 "fast:" %}
11371 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11372 ins_pipe( pipe_slow );
11373 %}
11375 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11376 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11377 predicate (UseSSE>=2);
11378 match(Set dst (ConvD2L src));
11379 effect( KILL cr );
11380 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11381 "MOVSD [ESP],$src\n\t"
11382 "FLD_D [ESP]\n\t"
11383 "FLDCW trunc mode\n\t"
11384 "FISTp [ESP + #0]\n\t"
11385 "FLDCW std/24-bit mode\n\t"
11386 "POP EAX\n\t"
11387 "POP EDX\n\t"
11388 "CMP EDX,0x80000000\n\t"
11389 "JNE,s fast\n\t"
11390 "TEST EAX,EAX\n\t"
11391 "JNE,s fast\n\t"
11392 "SUB ESP,8\n\t"
11393 "MOVSD [ESP],$src\n\t"
11394 "FLD_D [ESP]\n\t"
11395 "CALL d2l_wrapper\n"
11396 "fast:" %}
11397 ins_encode( XD2L_encoding(src) );
11398 ins_pipe( pipe_slow );
11399 %}
11401 // Convert a double to an int. Java semantics require we do complex
11402 // manglations in the corner cases. So we set the rounding mode to
11403 // 'zero', store the darned double down as an int, and reset the
11404 // rounding mode to 'nearest'. The hardware stores a flag value down
11405 // if we would overflow or converted a NAN; we check for this and
11406 // and go the slow path if needed.
11407 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11408 predicate(UseSSE==0);
11409 match(Set dst (ConvF2I src));
11410 effect( KILL tmp, KILL cr );
11411 format %{ "FLD $src\t# Convert float to int \n\t"
11412 "FLDCW trunc mode\n\t"
11413 "SUB ESP,4\n\t"
11414 "FISTp [ESP + #0]\n\t"
11415 "FLDCW std/24-bit mode\n\t"
11416 "POP EAX\n\t"
11417 "CMP EAX,0x80000000\n\t"
11418 "JNE,s fast\n\t"
11419 "FLD $src\n\t"
11420 "CALL d2i_wrapper\n"
11421 "fast:" %}
11422 // D2I_encoding works for F2I
11423 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11424 ins_pipe( pipe_slow );
11425 %}
11427 // Convert a float in xmm to an int reg.
11428 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11429 predicate(UseSSE>=1);
11430 match(Set dst (ConvF2I src));
11431 effect( KILL tmp, KILL cr );
11432 format %{ "CVTTSS2SI $dst, $src\n\t"
11433 "CMP $dst,0x80000000\n\t"
11434 "JNE,s fast\n\t"
11435 "SUB ESP, 4\n\t"
11436 "MOVSS [ESP], $src\n\t"
11437 "FLD [ESP]\n\t"
11438 "ADD ESP, 4\n\t"
11439 "CALL d2i_wrapper\n"
11440 "fast:" %}
11441 opcode(0x0); // single-precision conversion
11442 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11443 ins_pipe( pipe_slow );
11444 %}
11446 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11447 predicate(UseSSE==0);
11448 match(Set dst (ConvF2L src));
11449 effect( KILL cr );
11450 format %{ "FLD $src\t# Convert float to long\n\t"
11451 "FLDCW trunc mode\n\t"
11452 "SUB ESP,8\n\t"
11453 "FISTp [ESP + #0]\n\t"
11454 "FLDCW std/24-bit mode\n\t"
11455 "POP EAX\n\t"
11456 "POP EDX\n\t"
11457 "CMP EDX,0x80000000\n\t"
11458 "JNE,s fast\n\t"
11459 "TEST EAX,EAX\n\t"
11460 "JNE,s fast\n\t"
11461 "FLD $src\n\t"
11462 "CALL d2l_wrapper\n"
11463 "fast:" %}
11464 // D2L_encoding works for F2L
11465 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11466 ins_pipe( pipe_slow );
11467 %}
11469 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11470 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11471 predicate (UseSSE>=1);
11472 match(Set dst (ConvF2L src));
11473 effect( KILL cr );
11474 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11475 "MOVSS [ESP],$src\n\t"
11476 "FLD_S [ESP]\n\t"
11477 "FLDCW trunc mode\n\t"
11478 "FISTp [ESP + #0]\n\t"
11479 "FLDCW std/24-bit mode\n\t"
11480 "POP EAX\n\t"
11481 "POP EDX\n\t"
11482 "CMP EDX,0x80000000\n\t"
11483 "JNE,s fast\n\t"
11484 "TEST EAX,EAX\n\t"
11485 "JNE,s fast\n\t"
11486 "SUB ESP,4\t# Convert float to long\n\t"
11487 "MOVSS [ESP],$src\n\t"
11488 "FLD_S [ESP]\n\t"
11489 "ADD ESP,4\n\t"
11490 "CALL d2l_wrapper\n"
11491 "fast:" %}
11492 ins_encode( X2L_encoding(src) );
11493 ins_pipe( pipe_slow );
11494 %}
11496 instruct convI2D_reg(regD dst, stackSlotI src) %{
11497 predicate( UseSSE<=1 );
11498 match(Set dst (ConvI2D src));
11499 format %{ "FILD $src\n\t"
11500 "FSTP $dst" %}
11501 opcode(0xDB, 0x0); /* DB /0 */
11502 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11503 ins_pipe( fpu_reg_mem );
11504 %}
11506 instruct convI2XD_reg(regXD dst, eRegI src) %{
11507 predicate( UseSSE>=2 && !UseXmmI2D );
11508 match(Set dst (ConvI2D src));
11509 format %{ "CVTSI2SD $dst,$src" %}
11510 opcode(0xF2, 0x0F, 0x2A);
11511 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11512 ins_pipe( pipe_slow );
11513 %}
11515 instruct convI2XD_mem(regXD dst, memory mem) %{
11516 predicate( UseSSE>=2 );
11517 match(Set dst (ConvI2D (LoadI mem)));
11518 format %{ "CVTSI2SD $dst,$mem" %}
11519 opcode(0xF2, 0x0F, 0x2A);
11520 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11521 ins_pipe( pipe_slow );
11522 %}
11524 instruct convXI2XD_reg(regXD dst, eRegI src)
11525 %{
11526 predicate( UseSSE>=2 && UseXmmI2D );
11527 match(Set dst (ConvI2D src));
11529 format %{ "MOVD $dst,$src\n\t"
11530 "CVTDQ2PD $dst,$dst\t# i2d" %}
11531 ins_encode %{
11532 __ movdl($dst$$XMMRegister, $src$$Register);
11533 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11534 %}
11535 ins_pipe(pipe_slow); // XXX
11536 %}
11538 instruct convI2D_mem(regD dst, memory mem) %{
11539 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11540 match(Set dst (ConvI2D (LoadI mem)));
11541 format %{ "FILD $mem\n\t"
11542 "FSTP $dst" %}
11543 opcode(0xDB); /* DB /0 */
11544 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11545 Pop_Reg_D(dst));
11546 ins_pipe( fpu_reg_mem );
11547 %}
11549 // Convert a byte to a float; no rounding step needed.
11550 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11551 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11552 match(Set dst (ConvI2F src));
11553 format %{ "FILD $src\n\t"
11554 "FSTP $dst" %}
11556 opcode(0xDB, 0x0); /* DB /0 */
11557 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11558 ins_pipe( fpu_reg_mem );
11559 %}
11561 // In 24-bit mode, force exponent rounding by storing back out
11562 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11563 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11564 match(Set dst (ConvI2F src));
11565 ins_cost(200);
11566 format %{ "FILD $src\n\t"
11567 "FSTP_S $dst" %}
11568 opcode(0xDB, 0x0); /* DB /0 */
11569 ins_encode( Push_Mem_I(src),
11570 Pop_Mem_F(dst));
11571 ins_pipe( fpu_mem_mem );
11572 %}
11574 // In 24-bit mode, force exponent rounding by storing back out
11575 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11576 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11577 match(Set dst (ConvI2F (LoadI mem)));
11578 ins_cost(200);
11579 format %{ "FILD $mem\n\t"
11580 "FSTP_S $dst" %}
11581 opcode(0xDB); /* DB /0 */
11582 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11583 Pop_Mem_F(dst));
11584 ins_pipe( fpu_mem_mem );
11585 %}
11587 // This instruction does not round to 24-bits
11588 instruct convI2F_reg(regF dst, stackSlotI src) %{
11589 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11590 match(Set dst (ConvI2F src));
11591 format %{ "FILD $src\n\t"
11592 "FSTP $dst" %}
11593 opcode(0xDB, 0x0); /* DB /0 */
11594 ins_encode( Push_Mem_I(src),
11595 Pop_Reg_F(dst));
11596 ins_pipe( fpu_reg_mem );
11597 %}
11599 // This instruction does not round to 24-bits
11600 instruct convI2F_mem(regF dst, memory mem) %{
11601 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11602 match(Set dst (ConvI2F (LoadI mem)));
11603 format %{ "FILD $mem\n\t"
11604 "FSTP $dst" %}
11605 opcode(0xDB); /* DB /0 */
11606 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11607 Pop_Reg_F(dst));
11608 ins_pipe( fpu_reg_mem );
11609 %}
11611 // Convert an int to a float in xmm; no rounding step needed.
11612 instruct convI2X_reg(regX dst, eRegI src) %{
11613 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11614 match(Set dst (ConvI2F src));
11615 format %{ "CVTSI2SS $dst, $src" %}
11617 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11618 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11619 ins_pipe( pipe_slow );
11620 %}
11622 instruct convXI2X_reg(regX dst, eRegI src)
11623 %{
11624 predicate( UseSSE>=2 && UseXmmI2F );
11625 match(Set dst (ConvI2F src));
11627 format %{ "MOVD $dst,$src\n\t"
11628 "CVTDQ2PS $dst,$dst\t# i2f" %}
11629 ins_encode %{
11630 __ movdl($dst$$XMMRegister, $src$$Register);
11631 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11632 %}
11633 ins_pipe(pipe_slow); // XXX
11634 %}
11636 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11637 match(Set dst (ConvI2L src));
11638 effect(KILL cr);
11639 ins_cost(375);
11640 format %{ "MOV $dst.lo,$src\n\t"
11641 "MOV $dst.hi,$src\n\t"
11642 "SAR $dst.hi,31" %}
11643 ins_encode(convert_int_long(dst,src));
11644 ins_pipe( ialu_reg_reg_long );
11645 %}
11647 // Zero-extend convert int to long
11648 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11649 match(Set dst (AndL (ConvI2L src) mask) );
11650 effect( KILL flags );
11651 ins_cost(250);
11652 format %{ "MOV $dst.lo,$src\n\t"
11653 "XOR $dst.hi,$dst.hi" %}
11654 opcode(0x33); // XOR
11655 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11656 ins_pipe( ialu_reg_reg_long );
11657 %}
11659 // Zero-extend long
11660 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11661 match(Set dst (AndL src mask) );
11662 effect( KILL flags );
11663 ins_cost(250);
11664 format %{ "MOV $dst.lo,$src.lo\n\t"
11665 "XOR $dst.hi,$dst.hi\n\t" %}
11666 opcode(0x33); // XOR
11667 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11668 ins_pipe( ialu_reg_reg_long );
11669 %}
11671 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11672 predicate (UseSSE<=1);
11673 match(Set dst (ConvL2D src));
11674 effect( KILL cr );
11675 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11676 "PUSH $src.lo\n\t"
11677 "FILD ST,[ESP + #0]\n\t"
11678 "ADD ESP,8\n\t"
11679 "FSTP_D $dst\t# D-round" %}
11680 opcode(0xDF, 0x5); /* DF /5 */
11681 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11682 ins_pipe( pipe_slow );
11683 %}
11685 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11686 predicate (UseSSE>=2);
11687 match(Set dst (ConvL2D src));
11688 effect( KILL cr );
11689 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11690 "PUSH $src.lo\n\t"
11691 "FILD_D [ESP]\n\t"
11692 "FSTP_D [ESP]\n\t"
11693 "MOVSD $dst,[ESP]\n\t"
11694 "ADD ESP,8" %}
11695 opcode(0xDF, 0x5); /* DF /5 */
11696 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11697 ins_pipe( pipe_slow );
11698 %}
11700 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11701 predicate (UseSSE>=1);
11702 match(Set dst (ConvL2F src));
11703 effect( KILL cr );
11704 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11705 "PUSH $src.lo\n\t"
11706 "FILD_D [ESP]\n\t"
11707 "FSTP_S [ESP]\n\t"
11708 "MOVSS $dst,[ESP]\n\t"
11709 "ADD ESP,8" %}
11710 opcode(0xDF, 0x5); /* DF /5 */
11711 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11712 ins_pipe( pipe_slow );
11713 %}
11715 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11716 match(Set dst (ConvL2F src));
11717 effect( KILL cr );
11718 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11719 "PUSH $src.lo\n\t"
11720 "FILD ST,[ESP + #0]\n\t"
11721 "ADD ESP,8\n\t"
11722 "FSTP_S $dst\t# F-round" %}
11723 opcode(0xDF, 0x5); /* DF /5 */
11724 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11725 ins_pipe( pipe_slow );
11726 %}
11728 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11729 match(Set dst (ConvL2I src));
11730 effect( DEF dst, USE src );
11731 format %{ "MOV $dst,$src.lo" %}
11732 ins_encode(enc_CopyL_Lo(dst,src));
11733 ins_pipe( ialu_reg_reg );
11734 %}
11737 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11738 match(Set dst (MoveF2I src));
11739 effect( DEF dst, USE src );
11740 ins_cost(100);
11741 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11742 opcode(0x8B);
11743 ins_encode( OpcP, RegMem(dst,src));
11744 ins_pipe( ialu_reg_mem );
11745 %}
11747 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11748 predicate(UseSSE==0);
11749 match(Set dst (MoveF2I src));
11750 effect( DEF dst, USE src );
11752 ins_cost(125);
11753 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11754 ins_encode( Pop_Mem_Reg_F(dst, src) );
11755 ins_pipe( fpu_mem_reg );
11756 %}
11758 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11759 predicate(UseSSE>=1);
11760 match(Set dst (MoveF2I src));
11761 effect( DEF dst, USE src );
11763 ins_cost(95);
11764 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11765 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11766 ins_pipe( pipe_slow );
11767 %}
11769 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11770 predicate(UseSSE>=2);
11771 match(Set dst (MoveF2I src));
11772 effect( DEF dst, USE src );
11773 ins_cost(85);
11774 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11775 ins_encode( MovX2I_reg(dst, src));
11776 ins_pipe( pipe_slow );
11777 %}
11779 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11780 match(Set dst (MoveI2F src));
11781 effect( DEF dst, USE src );
11783 ins_cost(100);
11784 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11785 opcode(0x89);
11786 ins_encode( OpcPRegSS( dst, src ) );
11787 ins_pipe( ialu_mem_reg );
11788 %}
11791 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11792 predicate(UseSSE==0);
11793 match(Set dst (MoveI2F src));
11794 effect(DEF dst, USE src);
11796 ins_cost(125);
11797 format %{ "FLD_S $src\n\t"
11798 "FSTP $dst\t# MoveI2F_stack_reg" %}
11799 opcode(0xD9); /* D9 /0, FLD m32real */
11800 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11801 Pop_Reg_F(dst) );
11802 ins_pipe( fpu_reg_mem );
11803 %}
11805 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
11806 predicate(UseSSE>=1);
11807 match(Set dst (MoveI2F src));
11808 effect( DEF dst, USE src );
11810 ins_cost(95);
11811 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11812 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11813 ins_pipe( pipe_slow );
11814 %}
11816 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
11817 predicate(UseSSE>=2);
11818 match(Set dst (MoveI2F src));
11819 effect( DEF dst, USE src );
11821 ins_cost(85);
11822 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11823 ins_encode( MovI2X_reg(dst, src) );
11824 ins_pipe( pipe_slow );
11825 %}
11827 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11828 match(Set dst (MoveD2L src));
11829 effect(DEF dst, USE src);
11831 ins_cost(250);
11832 format %{ "MOV $dst.lo,$src\n\t"
11833 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11834 opcode(0x8B, 0x8B);
11835 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11836 ins_pipe( ialu_mem_long_reg );
11837 %}
11839 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11840 predicate(UseSSE<=1);
11841 match(Set dst (MoveD2L src));
11842 effect(DEF dst, USE src);
11844 ins_cost(125);
11845 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11846 ins_encode( Pop_Mem_Reg_D(dst, src) );
11847 ins_pipe( fpu_mem_reg );
11848 %}
11850 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
11851 predicate(UseSSE>=2);
11852 match(Set dst (MoveD2L src));
11853 effect(DEF dst, USE src);
11854 ins_cost(95);
11856 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11857 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
11858 ins_pipe( pipe_slow );
11859 %}
11861 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
11862 predicate(UseSSE>=2);
11863 match(Set dst (MoveD2L src));
11864 effect(DEF dst, USE src, TEMP tmp);
11865 ins_cost(85);
11866 format %{ "MOVD $dst.lo,$src\n\t"
11867 "PSHUFLW $tmp,$src,0x4E\n\t"
11868 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11869 ins_encode( MovXD2L_reg(dst, src, tmp) );
11870 ins_pipe( pipe_slow );
11871 %}
11873 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11874 match(Set dst (MoveL2D src));
11875 effect(DEF dst, USE src);
11877 ins_cost(200);
11878 format %{ "MOV $dst,$src.lo\n\t"
11879 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11880 opcode(0x89, 0x89);
11881 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11882 ins_pipe( ialu_mem_long_reg );
11883 %}
11886 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11887 predicate(UseSSE<=1);
11888 match(Set dst (MoveL2D src));
11889 effect(DEF dst, USE src);
11890 ins_cost(125);
11892 format %{ "FLD_D $src\n\t"
11893 "FSTP $dst\t# MoveL2D_stack_reg" %}
11894 opcode(0xDD); /* DD /0, FLD m64real */
11895 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11896 Pop_Reg_D(dst) );
11897 ins_pipe( fpu_reg_mem );
11898 %}
11901 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
11902 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11903 match(Set dst (MoveL2D src));
11904 effect(DEF dst, USE src);
11906 ins_cost(95);
11907 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11908 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11909 ins_pipe( pipe_slow );
11910 %}
11912 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
11913 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11914 match(Set dst (MoveL2D src));
11915 effect(DEF dst, USE src);
11917 ins_cost(95);
11918 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11919 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
11920 ins_pipe( pipe_slow );
11921 %}
11923 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
11924 predicate(UseSSE>=2);
11925 match(Set dst (MoveL2D src));
11926 effect(TEMP dst, USE src, TEMP tmp);
11927 ins_cost(85);
11928 format %{ "MOVD $dst,$src.lo\n\t"
11929 "MOVD $tmp,$src.hi\n\t"
11930 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11931 ins_encode( MovL2XD_reg(dst, src, tmp) );
11932 ins_pipe( pipe_slow );
11933 %}
11935 // Replicate scalar to packed byte (1 byte) values in xmm
11936 instruct Repl8B_reg(regXD dst, regXD src) %{
11937 predicate(UseSSE>=2);
11938 match(Set dst (Replicate8B src));
11939 format %{ "MOVDQA $dst,$src\n\t"
11940 "PUNPCKLBW $dst,$dst\n\t"
11941 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11942 ins_encode( pshufd_8x8(dst, src));
11943 ins_pipe( pipe_slow );
11944 %}
11946 // Replicate scalar to packed byte (1 byte) values in xmm
11947 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
11948 predicate(UseSSE>=2);
11949 match(Set dst (Replicate8B src));
11950 format %{ "MOVD $dst,$src\n\t"
11951 "PUNPCKLBW $dst,$dst\n\t"
11952 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11953 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11954 ins_pipe( pipe_slow );
11955 %}
11957 // Replicate scalar zero to packed byte (1 byte) values in xmm
11958 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
11959 predicate(UseSSE>=2);
11960 match(Set dst (Replicate8B zero));
11961 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11962 ins_encode( pxor(dst, dst));
11963 ins_pipe( fpu_reg_reg );
11964 %}
11966 // Replicate scalar to packed shore (2 byte) values in xmm
11967 instruct Repl4S_reg(regXD dst, regXD src) %{
11968 predicate(UseSSE>=2);
11969 match(Set dst (Replicate4S src));
11970 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11971 ins_encode( pshufd_4x16(dst, src));
11972 ins_pipe( fpu_reg_reg );
11973 %}
11975 // Replicate scalar to packed shore (2 byte) values in xmm
11976 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
11977 predicate(UseSSE>=2);
11978 match(Set dst (Replicate4S src));
11979 format %{ "MOVD $dst,$src\n\t"
11980 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11981 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11982 ins_pipe( fpu_reg_reg );
11983 %}
11985 // Replicate scalar zero to packed short (2 byte) values in xmm
11986 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
11987 predicate(UseSSE>=2);
11988 match(Set dst (Replicate4S zero));
11989 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11990 ins_encode( pxor(dst, dst));
11991 ins_pipe( fpu_reg_reg );
11992 %}
11994 // Replicate scalar to packed char (2 byte) values in xmm
11995 instruct Repl4C_reg(regXD dst, regXD src) %{
11996 predicate(UseSSE>=2);
11997 match(Set dst (Replicate4C src));
11998 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11999 ins_encode( pshufd_4x16(dst, src));
12000 ins_pipe( fpu_reg_reg );
12001 %}
12003 // Replicate scalar to packed char (2 byte) values in xmm
12004 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12005 predicate(UseSSE>=2);
12006 match(Set dst (Replicate4C src));
12007 format %{ "MOVD $dst,$src\n\t"
12008 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12009 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12010 ins_pipe( fpu_reg_reg );
12011 %}
12013 // Replicate scalar zero to packed char (2 byte) values in xmm
12014 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12015 predicate(UseSSE>=2);
12016 match(Set dst (Replicate4C zero));
12017 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12018 ins_encode( pxor(dst, dst));
12019 ins_pipe( fpu_reg_reg );
12020 %}
12022 // Replicate scalar to packed integer (4 byte) values in xmm
12023 instruct Repl2I_reg(regXD dst, regXD src) %{
12024 predicate(UseSSE>=2);
12025 match(Set dst (Replicate2I src));
12026 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12027 ins_encode( pshufd(dst, src, 0x00));
12028 ins_pipe( fpu_reg_reg );
12029 %}
12031 // Replicate scalar to packed integer (4 byte) values in xmm
12032 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12033 predicate(UseSSE>=2);
12034 match(Set dst (Replicate2I src));
12035 format %{ "MOVD $dst,$src\n\t"
12036 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12037 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12038 ins_pipe( fpu_reg_reg );
12039 %}
12041 // Replicate scalar zero to packed integer (2 byte) values in xmm
12042 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12043 predicate(UseSSE>=2);
12044 match(Set dst (Replicate2I zero));
12045 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12046 ins_encode( pxor(dst, dst));
12047 ins_pipe( fpu_reg_reg );
12048 %}
12050 // Replicate scalar to packed single precision floating point values in xmm
12051 instruct Repl2F_reg(regXD dst, regXD src) %{
12052 predicate(UseSSE>=2);
12053 match(Set dst (Replicate2F src));
12054 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12055 ins_encode( pshufd(dst, src, 0xe0));
12056 ins_pipe( fpu_reg_reg );
12057 %}
12059 // Replicate scalar to packed single precision floating point values in xmm
12060 instruct Repl2F_regX(regXD dst, regX src) %{
12061 predicate(UseSSE>=2);
12062 match(Set dst (Replicate2F src));
12063 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12064 ins_encode( pshufd(dst, src, 0xe0));
12065 ins_pipe( fpu_reg_reg );
12066 %}
12068 // Replicate scalar to packed single precision floating point values in xmm
12069 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12070 predicate(UseSSE>=2);
12071 match(Set dst (Replicate2F zero));
12072 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12073 ins_encode( pxor(dst, dst));
12074 ins_pipe( fpu_reg_reg );
12075 %}
12079 // =======================================================================
12080 // fast clearing of an array
12082 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12083 match(Set dummy (ClearArray cnt base));
12084 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12085 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12086 "XOR EAX,EAX\n\t"
12087 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12088 opcode(0,0x4);
12089 ins_encode( Opcode(0xD1), RegOpc(ECX),
12090 OpcRegReg(0x33,EAX,EAX),
12091 Opcode(0xF3), Opcode(0xAB) );
12092 ins_pipe( pipe_slow );
12093 %}
12095 instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
12096 match(Set result (StrComp str1 str2));
12097 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
12098 //ins_cost(300);
12100 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
12101 ins_encode( enc_String_Compare() );
12102 ins_pipe( pipe_slow );
12103 %}
12105 // fast array equals
12106 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
12107 match(Set result (AryEq ary1 ary2));
12108 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr);
12109 //ins_cost(300);
12111 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EAX, EBX" %}
12112 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) );
12113 ins_pipe( pipe_slow );
12114 %}
12116 //----------Control Flow Instructions------------------------------------------
12117 // Signed compare Instructions
12118 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12119 match(Set cr (CmpI op1 op2));
12120 effect( DEF cr, USE op1, USE op2 );
12121 format %{ "CMP $op1,$op2" %}
12122 opcode(0x3B); /* Opcode 3B /r */
12123 ins_encode( OpcP, RegReg( op1, op2) );
12124 ins_pipe( ialu_cr_reg_reg );
12125 %}
12127 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12128 match(Set cr (CmpI op1 op2));
12129 effect( DEF cr, USE op1 );
12130 format %{ "CMP $op1,$op2" %}
12131 opcode(0x81,0x07); /* Opcode 81 /7 */
12132 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12133 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12134 ins_pipe( ialu_cr_reg_imm );
12135 %}
12137 // Cisc-spilled version of cmpI_eReg
12138 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12139 match(Set cr (CmpI op1 (LoadI op2)));
12141 format %{ "CMP $op1,$op2" %}
12142 ins_cost(500);
12143 opcode(0x3B); /* Opcode 3B /r */
12144 ins_encode( OpcP, RegMem( op1, op2) );
12145 ins_pipe( ialu_cr_reg_mem );
12146 %}
12148 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12149 match(Set cr (CmpI src zero));
12150 effect( DEF cr, USE src );
12152 format %{ "TEST $src,$src" %}
12153 opcode(0x85);
12154 ins_encode( OpcP, RegReg( src, src ) );
12155 ins_pipe( ialu_cr_reg_imm );
12156 %}
12158 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12159 match(Set cr (CmpI (AndI src con) zero));
12161 format %{ "TEST $src,$con" %}
12162 opcode(0xF7,0x00);
12163 ins_encode( OpcP, RegOpc(src), Con32(con) );
12164 ins_pipe( ialu_cr_reg_imm );
12165 %}
12167 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12168 match(Set cr (CmpI (AndI src mem) zero));
12170 format %{ "TEST $src,$mem" %}
12171 opcode(0x85);
12172 ins_encode( OpcP, RegMem( src, mem ) );
12173 ins_pipe( ialu_cr_reg_mem );
12174 %}
12176 // Unsigned compare Instructions; really, same as signed except they
12177 // produce an eFlagsRegU instead of eFlagsReg.
12178 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12179 match(Set cr (CmpU op1 op2));
12181 format %{ "CMPu $op1,$op2" %}
12182 opcode(0x3B); /* Opcode 3B /r */
12183 ins_encode( OpcP, RegReg( op1, op2) );
12184 ins_pipe( ialu_cr_reg_reg );
12185 %}
12187 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12188 match(Set cr (CmpU op1 op2));
12190 format %{ "CMPu $op1,$op2" %}
12191 opcode(0x81,0x07); /* Opcode 81 /7 */
12192 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12193 ins_pipe( ialu_cr_reg_imm );
12194 %}
12196 // // Cisc-spilled version of cmpU_eReg
12197 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12198 match(Set cr (CmpU op1 (LoadI op2)));
12200 format %{ "CMPu $op1,$op2" %}
12201 ins_cost(500);
12202 opcode(0x3B); /* Opcode 3B /r */
12203 ins_encode( OpcP, RegMem( op1, op2) );
12204 ins_pipe( ialu_cr_reg_mem );
12205 %}
12207 // // Cisc-spilled version of cmpU_eReg
12208 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12209 // match(Set cr (CmpU (LoadI op1) op2));
12210 //
12211 // format %{ "CMPu $op1,$op2" %}
12212 // ins_cost(500);
12213 // opcode(0x39); /* Opcode 39 /r */
12214 // ins_encode( OpcP, RegMem( op1, op2) );
12215 //%}
12217 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12218 match(Set cr (CmpU src zero));
12220 format %{ "TESTu $src,$src" %}
12221 opcode(0x85);
12222 ins_encode( OpcP, RegReg( src, src ) );
12223 ins_pipe( ialu_cr_reg_imm );
12224 %}
12226 // Unsigned pointer compare Instructions
12227 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12228 match(Set cr (CmpP op1 op2));
12230 format %{ "CMPu $op1,$op2" %}
12231 opcode(0x3B); /* Opcode 3B /r */
12232 ins_encode( OpcP, RegReg( op1, op2) );
12233 ins_pipe( ialu_cr_reg_reg );
12234 %}
12236 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12237 match(Set cr (CmpP op1 op2));
12239 format %{ "CMPu $op1,$op2" %}
12240 opcode(0x81,0x07); /* Opcode 81 /7 */
12241 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12242 ins_pipe( ialu_cr_reg_imm );
12243 %}
12245 // // Cisc-spilled version of cmpP_eReg
12246 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12247 match(Set cr (CmpP op1 (LoadP op2)));
12249 format %{ "CMPu $op1,$op2" %}
12250 ins_cost(500);
12251 opcode(0x3B); /* Opcode 3B /r */
12252 ins_encode( OpcP, RegMem( op1, op2) );
12253 ins_pipe( ialu_cr_reg_mem );
12254 %}
12256 // // Cisc-spilled version of cmpP_eReg
12257 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12258 // match(Set cr (CmpP (LoadP op1) op2));
12259 //
12260 // format %{ "CMPu $op1,$op2" %}
12261 // ins_cost(500);
12262 // opcode(0x39); /* Opcode 39 /r */
12263 // ins_encode( OpcP, RegMem( op1, op2) );
12264 //%}
12266 // Compare raw pointer (used in out-of-heap check).
12267 // Only works because non-oop pointers must be raw pointers
12268 // and raw pointers have no anti-dependencies.
12269 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12270 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12271 match(Set cr (CmpP op1 (LoadP op2)));
12273 format %{ "CMPu $op1,$op2" %}
12274 opcode(0x3B); /* Opcode 3B /r */
12275 ins_encode( OpcP, RegMem( op1, op2) );
12276 ins_pipe( ialu_cr_reg_mem );
12277 %}
12279 //
12280 // This will generate a signed flags result. This should be ok
12281 // since any compare to a zero should be eq/neq.
12282 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12283 match(Set cr (CmpP src zero));
12285 format %{ "TEST $src,$src" %}
12286 opcode(0x85);
12287 ins_encode( OpcP, RegReg( src, src ) );
12288 ins_pipe( ialu_cr_reg_imm );
12289 %}
12291 // Cisc-spilled version of testP_reg
12292 // This will generate a signed flags result. This should be ok
12293 // since any compare to a zero should be eq/neq.
12294 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12295 match(Set cr (CmpP (LoadP op) zero));
12297 format %{ "TEST $op,0xFFFFFFFF" %}
12298 ins_cost(500);
12299 opcode(0xF7); /* Opcode F7 /0 */
12300 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12301 ins_pipe( ialu_cr_reg_imm );
12302 %}
12304 // Yanked all unsigned pointer compare operations.
12305 // Pointer compares are done with CmpP which is already unsigned.
12307 //----------Max and Min--------------------------------------------------------
12308 // Min Instructions
12309 ////
12310 // *** Min and Max using the conditional move are slower than the
12311 // *** branch version on a Pentium III.
12312 // // Conditional move for min
12313 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12314 // effect( USE_DEF op2, USE op1, USE cr );
12315 // format %{ "CMOVlt $op2,$op1\t! min" %}
12316 // opcode(0x4C,0x0F);
12317 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12318 // ins_pipe( pipe_cmov_reg );
12319 //%}
12320 //
12321 //// Min Register with Register (P6 version)
12322 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12323 // predicate(VM_Version::supports_cmov() );
12324 // match(Set op2 (MinI op1 op2));
12325 // ins_cost(200);
12326 // expand %{
12327 // eFlagsReg cr;
12328 // compI_eReg(cr,op1,op2);
12329 // cmovI_reg_lt(op2,op1,cr);
12330 // %}
12331 //%}
12333 // Min Register with Register (generic version)
12334 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12335 match(Set dst (MinI dst src));
12336 effect(KILL flags);
12337 ins_cost(300);
12339 format %{ "MIN $dst,$src" %}
12340 opcode(0xCC);
12341 ins_encode( min_enc(dst,src) );
12342 ins_pipe( pipe_slow );
12343 %}
12345 // Max Register with Register
12346 // *** Min and Max using the conditional move are slower than the
12347 // *** branch version on a Pentium III.
12348 // // Conditional move for max
12349 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12350 // effect( USE_DEF op2, USE op1, USE cr );
12351 // format %{ "CMOVgt $op2,$op1\t! max" %}
12352 // opcode(0x4F,0x0F);
12353 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12354 // ins_pipe( pipe_cmov_reg );
12355 //%}
12356 //
12357 // // Max Register with Register (P6 version)
12358 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12359 // predicate(VM_Version::supports_cmov() );
12360 // match(Set op2 (MaxI op1 op2));
12361 // ins_cost(200);
12362 // expand %{
12363 // eFlagsReg cr;
12364 // compI_eReg(cr,op1,op2);
12365 // cmovI_reg_gt(op2,op1,cr);
12366 // %}
12367 //%}
12369 // Max Register with Register (generic version)
12370 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12371 match(Set dst (MaxI dst src));
12372 effect(KILL flags);
12373 ins_cost(300);
12375 format %{ "MAX $dst,$src" %}
12376 opcode(0xCC);
12377 ins_encode( max_enc(dst,src) );
12378 ins_pipe( pipe_slow );
12379 %}
12381 // ============================================================================
12382 // Branch Instructions
12383 // Jump Table
12384 instruct jumpXtnd(eRegI switch_val) %{
12385 match(Jump switch_val);
12386 ins_cost(350);
12388 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12390 ins_encode %{
12391 address table_base = __ address_table_constant(_index2label);
12393 // Jump to Address(table_base + switch_reg)
12394 InternalAddress table(table_base);
12395 Address index(noreg, $switch_val$$Register, Address::times_1);
12396 __ jump(ArrayAddress(table, index));
12397 %}
12398 ins_pc_relative(1);
12399 ins_pipe(pipe_jmp);
12400 %}
12402 // Jump Direct - Label defines a relative address from JMP+1
12403 instruct jmpDir(label labl) %{
12404 match(Goto);
12405 effect(USE labl);
12407 ins_cost(300);
12408 format %{ "JMP $labl" %}
12409 size(5);
12410 opcode(0xE9);
12411 ins_encode( OpcP, Lbl( labl ) );
12412 ins_pipe( pipe_jmp );
12413 ins_pc_relative(1);
12414 %}
12416 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12417 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12418 match(If cop cr);
12419 effect(USE labl);
12421 ins_cost(300);
12422 format %{ "J$cop $labl" %}
12423 size(6);
12424 opcode(0x0F, 0x80);
12425 ins_encode( Jcc( cop, labl) );
12426 ins_pipe( pipe_jcc );
12427 ins_pc_relative(1);
12428 %}
12430 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12431 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12432 match(CountedLoopEnd cop cr);
12433 effect(USE labl);
12435 ins_cost(300);
12436 format %{ "J$cop $labl\t# Loop end" %}
12437 size(6);
12438 opcode(0x0F, 0x80);
12439 ins_encode( Jcc( cop, labl) );
12440 ins_pipe( pipe_jcc );
12441 ins_pc_relative(1);
12442 %}
12444 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12445 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12446 match(CountedLoopEnd cop cmp);
12447 effect(USE labl);
12449 ins_cost(300);
12450 format %{ "J$cop,u $labl\t# Loop end" %}
12451 size(6);
12452 opcode(0x0F, 0x80);
12453 ins_encode( Jcc( cop, labl) );
12454 ins_pipe( pipe_jcc );
12455 ins_pc_relative(1);
12456 %}
12458 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12459 match(CountedLoopEnd cop cmp);
12460 effect(USE labl);
12462 ins_cost(200);
12463 format %{ "J$cop,u $labl\t# Loop end" %}
12464 size(6);
12465 opcode(0x0F, 0x80);
12466 ins_encode( Jcc( cop, labl) );
12467 ins_pipe( pipe_jcc );
12468 ins_pc_relative(1);
12469 %}
12471 // Jump Direct Conditional - using unsigned comparison
12472 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12473 match(If cop cmp);
12474 effect(USE labl);
12476 ins_cost(300);
12477 format %{ "J$cop,u $labl" %}
12478 size(6);
12479 opcode(0x0F, 0x80);
12480 ins_encode(Jcc(cop, labl));
12481 ins_pipe(pipe_jcc);
12482 ins_pc_relative(1);
12483 %}
12485 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12486 match(If cop cmp);
12487 effect(USE labl);
12489 ins_cost(200);
12490 format %{ "J$cop,u $labl" %}
12491 size(6);
12492 opcode(0x0F, 0x80);
12493 ins_encode(Jcc(cop, labl));
12494 ins_pipe(pipe_jcc);
12495 ins_pc_relative(1);
12496 %}
12498 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12499 match(If cop cmp);
12500 effect(USE labl);
12502 ins_cost(200);
12503 format %{ $$template
12504 if ($cop$$cmpcode == Assembler::notEqual) {
12505 $$emit$$"JP,u $labl\n\t"
12506 $$emit$$"J$cop,u $labl"
12507 } else {
12508 $$emit$$"JP,u done\n\t"
12509 $$emit$$"J$cop,u $labl\n\t"
12510 $$emit$$"done:"
12511 }
12512 %}
12513 size(12);
12514 opcode(0x0F, 0x80);
12515 ins_encode %{
12516 Label* l = $labl$$label;
12517 $$$emit8$primary;
12518 emit_cc(cbuf, $secondary, Assembler::parity);
12519 int parity_disp = -1;
12520 bool ok = false;
12521 if ($cop$$cmpcode == Assembler::notEqual) {
12522 // the two jumps 6 bytes apart so the jump distances are too
12523 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12524 } else if ($cop$$cmpcode == Assembler::equal) {
12525 parity_disp = 6;
12526 ok = true;
12527 } else {
12528 ShouldNotReachHere();
12529 }
12530 emit_d32(cbuf, parity_disp);
12531 $$$emit8$primary;
12532 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12533 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12534 emit_d32(cbuf, disp);
12535 %}
12536 ins_pipe(pipe_jcc);
12537 ins_pc_relative(1);
12538 %}
12540 // ============================================================================
12541 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12542 // array for an instance of the superklass. Set a hidden internal cache on a
12543 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12544 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12545 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12546 match(Set result (PartialSubtypeCheck sub super));
12547 effect( KILL rcx, KILL cr );
12549 ins_cost(1100); // slightly larger than the next version
12550 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12551 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12552 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12553 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12554 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12555 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12556 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12557 "miss:\t" %}
12559 opcode(0x1); // Force a XOR of EDI
12560 ins_encode( enc_PartialSubtypeCheck() );
12561 ins_pipe( pipe_slow );
12562 %}
12564 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12565 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12566 effect( KILL rcx, KILL result );
12568 ins_cost(1000);
12569 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12570 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12571 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12572 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12573 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12574 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12575 "miss:\t" %}
12577 opcode(0x0); // No need to XOR EDI
12578 ins_encode( enc_PartialSubtypeCheck() );
12579 ins_pipe( pipe_slow );
12580 %}
12582 // ============================================================================
12583 // Branch Instructions -- short offset versions
12584 //
12585 // These instructions are used to replace jumps of a long offset (the default
12586 // match) with jumps of a shorter offset. These instructions are all tagged
12587 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12588 // match rules in general matching. Instead, the ADLC generates a conversion
12589 // method in the MachNode which can be used to do in-place replacement of the
12590 // long variant with the shorter variant. The compiler will determine if a
12591 // branch can be taken by the is_short_branch_offset() predicate in the machine
12592 // specific code section of the file.
12594 // Jump Direct - Label defines a relative address from JMP+1
12595 instruct jmpDir_short(label labl) %{
12596 match(Goto);
12597 effect(USE labl);
12599 ins_cost(300);
12600 format %{ "JMP,s $labl" %}
12601 size(2);
12602 opcode(0xEB);
12603 ins_encode( OpcP, LblShort( labl ) );
12604 ins_pipe( pipe_jmp );
12605 ins_pc_relative(1);
12606 ins_short_branch(1);
12607 %}
12609 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12610 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12611 match(If cop cr);
12612 effect(USE labl);
12614 ins_cost(300);
12615 format %{ "J$cop,s $labl" %}
12616 size(2);
12617 opcode(0x70);
12618 ins_encode( JccShort( cop, labl) );
12619 ins_pipe( pipe_jcc );
12620 ins_pc_relative(1);
12621 ins_short_branch(1);
12622 %}
12624 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12625 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12626 match(CountedLoopEnd cop cr);
12627 effect(USE labl);
12629 ins_cost(300);
12630 format %{ "J$cop,s $labl\t# Loop end" %}
12631 size(2);
12632 opcode(0x70);
12633 ins_encode( JccShort( cop, labl) );
12634 ins_pipe( pipe_jcc );
12635 ins_pc_relative(1);
12636 ins_short_branch(1);
12637 %}
12639 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12640 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12641 match(CountedLoopEnd cop cmp);
12642 effect(USE labl);
12644 ins_cost(300);
12645 format %{ "J$cop,us $labl\t# Loop end" %}
12646 size(2);
12647 opcode(0x70);
12648 ins_encode( JccShort( cop, labl) );
12649 ins_pipe( pipe_jcc );
12650 ins_pc_relative(1);
12651 ins_short_branch(1);
12652 %}
12654 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12655 match(CountedLoopEnd cop cmp);
12656 effect(USE labl);
12658 ins_cost(300);
12659 format %{ "J$cop,us $labl\t# Loop end" %}
12660 size(2);
12661 opcode(0x70);
12662 ins_encode( JccShort( cop, labl) );
12663 ins_pipe( pipe_jcc );
12664 ins_pc_relative(1);
12665 ins_short_branch(1);
12666 %}
12668 // Jump Direct Conditional - using unsigned comparison
12669 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12670 match(If cop cmp);
12671 effect(USE labl);
12673 ins_cost(300);
12674 format %{ "J$cop,us $labl" %}
12675 size(2);
12676 opcode(0x70);
12677 ins_encode( JccShort( cop, labl) );
12678 ins_pipe( pipe_jcc );
12679 ins_pc_relative(1);
12680 ins_short_branch(1);
12681 %}
12683 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12684 match(If cop cmp);
12685 effect(USE labl);
12687 ins_cost(300);
12688 format %{ "J$cop,us $labl" %}
12689 size(2);
12690 opcode(0x70);
12691 ins_encode( JccShort( cop, labl) );
12692 ins_pipe( pipe_jcc );
12693 ins_pc_relative(1);
12694 ins_short_branch(1);
12695 %}
12697 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12698 match(If cop cmp);
12699 effect(USE labl);
12701 ins_cost(300);
12702 format %{ $$template
12703 if ($cop$$cmpcode == Assembler::notEqual) {
12704 $$emit$$"JP,u,s $labl\n\t"
12705 $$emit$$"J$cop,u,s $labl"
12706 } else {
12707 $$emit$$"JP,u,s done\n\t"
12708 $$emit$$"J$cop,u,s $labl\n\t"
12709 $$emit$$"done:"
12710 }
12711 %}
12712 size(4);
12713 opcode(0x70);
12714 ins_encode %{
12715 Label* l = $labl$$label;
12716 emit_cc(cbuf, $primary, Assembler::parity);
12717 int parity_disp = -1;
12718 if ($cop$$cmpcode == Assembler::notEqual) {
12719 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12720 } else if ($cop$$cmpcode == Assembler::equal) {
12721 parity_disp = 2;
12722 } else {
12723 ShouldNotReachHere();
12724 }
12725 emit_d8(cbuf, parity_disp);
12726 emit_cc(cbuf, $primary, $cop$$cmpcode);
12727 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12728 emit_d8(cbuf, disp);
12729 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12730 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12731 %}
12732 ins_pipe(pipe_jcc);
12733 ins_pc_relative(1);
12734 ins_short_branch(1);
12735 %}
12737 // ============================================================================
12738 // Long Compare
12739 //
12740 // Currently we hold longs in 2 registers. Comparing such values efficiently
12741 // is tricky. The flavor of compare used depends on whether we are testing
12742 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12743 // The GE test is the negated LT test. The LE test can be had by commuting
12744 // the operands (yielding a GE test) and then negating; negate again for the
12745 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12746 // NE test is negated from that.
12748 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12749 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12750 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12751 // are collapsed internally in the ADLC's dfa-gen code. The match for
12752 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12753 // foo match ends up with the wrong leaf. One fix is to not match both
12754 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12755 // both forms beat the trinary form of long-compare and both are very useful
12756 // on Intel which has so few registers.
12758 // Manifest a CmpL result in an integer register. Very painful.
12759 // This is the test to avoid.
12760 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12761 match(Set dst (CmpL3 src1 src2));
12762 effect( KILL flags );
12763 ins_cost(1000);
12764 format %{ "XOR $dst,$dst\n\t"
12765 "CMP $src1.hi,$src2.hi\n\t"
12766 "JLT,s m_one\n\t"
12767 "JGT,s p_one\n\t"
12768 "CMP $src1.lo,$src2.lo\n\t"
12769 "JB,s m_one\n\t"
12770 "JEQ,s done\n"
12771 "p_one:\tINC $dst\n\t"
12772 "JMP,s done\n"
12773 "m_one:\tDEC $dst\n"
12774 "done:" %}
12775 ins_encode %{
12776 Label p_one, m_one, done;
12777 __ xorptr($dst$$Register, $dst$$Register);
12778 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12779 __ jccb(Assembler::less, m_one);
12780 __ jccb(Assembler::greater, p_one);
12781 __ cmpl($src1$$Register, $src2$$Register);
12782 __ jccb(Assembler::below, m_one);
12783 __ jccb(Assembler::equal, done);
12784 __ bind(p_one);
12785 __ incrementl($dst$$Register);
12786 __ jmpb(done);
12787 __ bind(m_one);
12788 __ decrementl($dst$$Register);
12789 __ bind(done);
12790 %}
12791 ins_pipe( pipe_slow );
12792 %}
12794 //======
12795 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12796 // compares. Can be used for LE or GT compares by reversing arguments.
12797 // NOT GOOD FOR EQ/NE tests.
12798 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12799 match( Set flags (CmpL src zero ));
12800 ins_cost(100);
12801 format %{ "TEST $src.hi,$src.hi" %}
12802 opcode(0x85);
12803 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12804 ins_pipe( ialu_cr_reg_reg );
12805 %}
12807 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12808 // compares. Can be used for LE or GT compares by reversing arguments.
12809 // NOT GOOD FOR EQ/NE tests.
12810 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12811 match( Set flags (CmpL src1 src2 ));
12812 effect( TEMP tmp );
12813 ins_cost(300);
12814 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12815 "MOV $tmp,$src1.hi\n\t"
12816 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12817 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12818 ins_pipe( ialu_cr_reg_reg );
12819 %}
12821 // Long compares reg < zero/req OR reg >= zero/req.
12822 // Just a wrapper for a normal branch, plus the predicate test.
12823 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12824 match(If cmp flags);
12825 effect(USE labl);
12826 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12827 expand %{
12828 jmpCon(cmp,flags,labl); // JLT or JGE...
12829 %}
12830 %}
12832 // Compare 2 longs and CMOVE longs.
12833 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12834 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12835 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12836 ins_cost(400);
12837 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12838 "CMOV$cmp $dst.hi,$src.hi" %}
12839 opcode(0x0F,0x40);
12840 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12841 ins_pipe( pipe_cmov_reg_long );
12842 %}
12844 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12845 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12846 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12847 ins_cost(500);
12848 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12849 "CMOV$cmp $dst.hi,$src.hi" %}
12850 opcode(0x0F,0x40);
12851 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12852 ins_pipe( pipe_cmov_reg_long );
12853 %}
12855 // Compare 2 longs and CMOVE ints.
12856 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12857 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12858 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12859 ins_cost(200);
12860 format %{ "CMOV$cmp $dst,$src" %}
12861 opcode(0x0F,0x40);
12862 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12863 ins_pipe( pipe_cmov_reg );
12864 %}
12866 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12867 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12868 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12869 ins_cost(250);
12870 format %{ "CMOV$cmp $dst,$src" %}
12871 opcode(0x0F,0x40);
12872 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12873 ins_pipe( pipe_cmov_mem );
12874 %}
12876 // Compare 2 longs and CMOVE ints.
12877 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12878 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12879 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12880 ins_cost(200);
12881 format %{ "CMOV$cmp $dst,$src" %}
12882 opcode(0x0F,0x40);
12883 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12884 ins_pipe( pipe_cmov_reg );
12885 %}
12887 // Compare 2 longs and CMOVE doubles
12888 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12889 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12890 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12891 ins_cost(200);
12892 expand %{
12893 fcmovD_regS(cmp,flags,dst,src);
12894 %}
12895 %}
12897 // Compare 2 longs and CMOVE doubles
12898 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
12899 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12900 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12901 ins_cost(200);
12902 expand %{
12903 fcmovXD_regS(cmp,flags,dst,src);
12904 %}
12905 %}
12907 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12908 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12909 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12910 ins_cost(200);
12911 expand %{
12912 fcmovF_regS(cmp,flags,dst,src);
12913 %}
12914 %}
12916 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
12917 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12918 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12919 ins_cost(200);
12920 expand %{
12921 fcmovX_regS(cmp,flags,dst,src);
12922 %}
12923 %}
12925 //======
12926 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12927 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12928 match( Set flags (CmpL src zero ));
12929 effect(TEMP tmp);
12930 ins_cost(200);
12931 format %{ "MOV $tmp,$src.lo\n\t"
12932 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12933 ins_encode( long_cmp_flags0( src, tmp ) );
12934 ins_pipe( ialu_reg_reg_long );
12935 %}
12937 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12938 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12939 match( Set flags (CmpL src1 src2 ));
12940 ins_cost(200+300);
12941 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12942 "JNE,s skip\n\t"
12943 "CMP $src1.hi,$src2.hi\n\t"
12944 "skip:\t" %}
12945 ins_encode( long_cmp_flags1( src1, src2 ) );
12946 ins_pipe( ialu_cr_reg_reg );
12947 %}
12949 // Long compare reg == zero/reg OR reg != zero/reg
12950 // Just a wrapper for a normal branch, plus the predicate test.
12951 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12952 match(If cmp flags);
12953 effect(USE labl);
12954 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12955 expand %{
12956 jmpCon(cmp,flags,labl); // JEQ or JNE...
12957 %}
12958 %}
12960 // Compare 2 longs and CMOVE longs.
12961 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12962 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12963 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12964 ins_cost(400);
12965 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12966 "CMOV$cmp $dst.hi,$src.hi" %}
12967 opcode(0x0F,0x40);
12968 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12969 ins_pipe( pipe_cmov_reg_long );
12970 %}
12972 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12973 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12974 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12975 ins_cost(500);
12976 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12977 "CMOV$cmp $dst.hi,$src.hi" %}
12978 opcode(0x0F,0x40);
12979 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12980 ins_pipe( pipe_cmov_reg_long );
12981 %}
12983 // Compare 2 longs and CMOVE ints.
12984 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12985 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12986 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12987 ins_cost(200);
12988 format %{ "CMOV$cmp $dst,$src" %}
12989 opcode(0x0F,0x40);
12990 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12991 ins_pipe( pipe_cmov_reg );
12992 %}
12994 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
12995 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12996 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12997 ins_cost(250);
12998 format %{ "CMOV$cmp $dst,$src" %}
12999 opcode(0x0F,0x40);
13000 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13001 ins_pipe( pipe_cmov_mem );
13002 %}
13004 // Compare 2 longs and CMOVE ints.
13005 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13006 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13007 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13008 ins_cost(200);
13009 format %{ "CMOV$cmp $dst,$src" %}
13010 opcode(0x0F,0x40);
13011 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13012 ins_pipe( pipe_cmov_reg );
13013 %}
13015 // Compare 2 longs and CMOVE doubles
13016 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13017 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13018 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13019 ins_cost(200);
13020 expand %{
13021 fcmovD_regS(cmp,flags,dst,src);
13022 %}
13023 %}
13025 // Compare 2 longs and CMOVE doubles
13026 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13027 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13028 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13029 ins_cost(200);
13030 expand %{
13031 fcmovXD_regS(cmp,flags,dst,src);
13032 %}
13033 %}
13035 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13036 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13037 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13038 ins_cost(200);
13039 expand %{
13040 fcmovF_regS(cmp,flags,dst,src);
13041 %}
13042 %}
13044 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13045 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13046 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13047 ins_cost(200);
13048 expand %{
13049 fcmovX_regS(cmp,flags,dst,src);
13050 %}
13051 %}
13053 //======
13054 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13055 // Same as cmpL_reg_flags_LEGT except must negate src
13056 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13057 match( Set flags (CmpL src zero ));
13058 effect( TEMP tmp );
13059 ins_cost(300);
13060 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13061 "CMP $tmp,$src.lo\n\t"
13062 "SBB $tmp,$src.hi\n\t" %}
13063 ins_encode( long_cmp_flags3(src, tmp) );
13064 ins_pipe( ialu_reg_reg_long );
13065 %}
13067 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13068 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13069 // requires a commuted test to get the same result.
13070 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13071 match( Set flags (CmpL src1 src2 ));
13072 effect( TEMP tmp );
13073 ins_cost(300);
13074 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13075 "MOV $tmp,$src2.hi\n\t"
13076 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13077 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13078 ins_pipe( ialu_cr_reg_reg );
13079 %}
13081 // Long compares reg < zero/req OR reg >= zero/req.
13082 // Just a wrapper for a normal branch, plus the predicate test
13083 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13084 match(If cmp flags);
13085 effect(USE labl);
13086 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13087 ins_cost(300);
13088 expand %{
13089 jmpCon(cmp,flags,labl); // JGT or JLE...
13090 %}
13091 %}
13093 // Compare 2 longs and CMOVE longs.
13094 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13095 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13096 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13097 ins_cost(400);
13098 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13099 "CMOV$cmp $dst.hi,$src.hi" %}
13100 opcode(0x0F,0x40);
13101 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13102 ins_pipe( pipe_cmov_reg_long );
13103 %}
13105 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13106 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13107 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13108 ins_cost(500);
13109 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13110 "CMOV$cmp $dst.hi,$src.hi+4" %}
13111 opcode(0x0F,0x40);
13112 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13113 ins_pipe( pipe_cmov_reg_long );
13114 %}
13116 // Compare 2 longs and CMOVE ints.
13117 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13118 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13119 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13120 ins_cost(200);
13121 format %{ "CMOV$cmp $dst,$src" %}
13122 opcode(0x0F,0x40);
13123 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13124 ins_pipe( pipe_cmov_reg );
13125 %}
13127 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13128 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13129 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13130 ins_cost(250);
13131 format %{ "CMOV$cmp $dst,$src" %}
13132 opcode(0x0F,0x40);
13133 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13134 ins_pipe( pipe_cmov_mem );
13135 %}
13137 // Compare 2 longs and CMOVE ptrs.
13138 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13139 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13140 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13141 ins_cost(200);
13142 format %{ "CMOV$cmp $dst,$src" %}
13143 opcode(0x0F,0x40);
13144 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13145 ins_pipe( pipe_cmov_reg );
13146 %}
13148 // Compare 2 longs and CMOVE doubles
13149 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13150 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13151 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13152 ins_cost(200);
13153 expand %{
13154 fcmovD_regS(cmp,flags,dst,src);
13155 %}
13156 %}
13158 // Compare 2 longs and CMOVE doubles
13159 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13160 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13161 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13162 ins_cost(200);
13163 expand %{
13164 fcmovXD_regS(cmp,flags,dst,src);
13165 %}
13166 %}
13168 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13169 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13170 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13171 ins_cost(200);
13172 expand %{
13173 fcmovF_regS(cmp,flags,dst,src);
13174 %}
13175 %}
13178 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13179 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13180 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13181 ins_cost(200);
13182 expand %{
13183 fcmovX_regS(cmp,flags,dst,src);
13184 %}
13185 %}
13188 // ============================================================================
13189 // Procedure Call/Return Instructions
13190 // Call Java Static Instruction
13191 // Note: If this code changes, the corresponding ret_addr_offset() and
13192 // compute_padding() functions will have to be adjusted.
13193 instruct CallStaticJavaDirect(method meth) %{
13194 match(CallStaticJava);
13195 effect(USE meth);
13197 ins_cost(300);
13198 format %{ "CALL,static " %}
13199 opcode(0xE8); /* E8 cd */
13200 ins_encode( pre_call_FPU,
13201 Java_Static_Call( meth ),
13202 call_epilog,
13203 post_call_FPU );
13204 ins_pipe( pipe_slow );
13205 ins_pc_relative(1);
13206 ins_alignment(4);
13207 %}
13209 // Call Java Dynamic Instruction
13210 // Note: If this code changes, the corresponding ret_addr_offset() and
13211 // compute_padding() functions will have to be adjusted.
13212 instruct CallDynamicJavaDirect(method meth) %{
13213 match(CallDynamicJava);
13214 effect(USE meth);
13216 ins_cost(300);
13217 format %{ "MOV EAX,(oop)-1\n\t"
13218 "CALL,dynamic" %}
13219 opcode(0xE8); /* E8 cd */
13220 ins_encode( pre_call_FPU,
13221 Java_Dynamic_Call( meth ),
13222 call_epilog,
13223 post_call_FPU );
13224 ins_pipe( pipe_slow );
13225 ins_pc_relative(1);
13226 ins_alignment(4);
13227 %}
13229 // Call Runtime Instruction
13230 instruct CallRuntimeDirect(method meth) %{
13231 match(CallRuntime );
13232 effect(USE meth);
13234 ins_cost(300);
13235 format %{ "CALL,runtime " %}
13236 opcode(0xE8); /* E8 cd */
13237 // Use FFREEs to clear entries in float stack
13238 ins_encode( pre_call_FPU,
13239 FFree_Float_Stack_All,
13240 Java_To_Runtime( meth ),
13241 post_call_FPU );
13242 ins_pipe( pipe_slow );
13243 ins_pc_relative(1);
13244 %}
13246 // Call runtime without safepoint
13247 instruct CallLeafDirect(method meth) %{
13248 match(CallLeaf);
13249 effect(USE meth);
13251 ins_cost(300);
13252 format %{ "CALL_LEAF,runtime " %}
13253 opcode(0xE8); /* E8 cd */
13254 ins_encode( pre_call_FPU,
13255 FFree_Float_Stack_All,
13256 Java_To_Runtime( meth ),
13257 Verify_FPU_For_Leaf, post_call_FPU );
13258 ins_pipe( pipe_slow );
13259 ins_pc_relative(1);
13260 %}
13262 instruct CallLeafNoFPDirect(method meth) %{
13263 match(CallLeafNoFP);
13264 effect(USE meth);
13266 ins_cost(300);
13267 format %{ "CALL_LEAF_NOFP,runtime " %}
13268 opcode(0xE8); /* E8 cd */
13269 ins_encode(Java_To_Runtime(meth));
13270 ins_pipe( pipe_slow );
13271 ins_pc_relative(1);
13272 %}
13275 // Return Instruction
13276 // Remove the return address & jump to it.
13277 instruct Ret() %{
13278 match(Return);
13279 format %{ "RET" %}
13280 opcode(0xC3);
13281 ins_encode(OpcP);
13282 ins_pipe( pipe_jmp );
13283 %}
13285 // Tail Call; Jump from runtime stub to Java code.
13286 // Also known as an 'interprocedural jump'.
13287 // Target of jump will eventually return to caller.
13288 // TailJump below removes the return address.
13289 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13290 match(TailCall jump_target method_oop );
13291 ins_cost(300);
13292 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13293 opcode(0xFF, 0x4); /* Opcode FF /4 */
13294 ins_encode( OpcP, RegOpc(jump_target) );
13295 ins_pipe( pipe_jmp );
13296 %}
13299 // Tail Jump; remove the return address; jump to target.
13300 // TailCall above leaves the return address around.
13301 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13302 match( TailJump jump_target ex_oop );
13303 ins_cost(300);
13304 format %{ "POP EDX\t# pop return address into dummy\n\t"
13305 "JMP $jump_target " %}
13306 opcode(0xFF, 0x4); /* Opcode FF /4 */
13307 ins_encode( enc_pop_rdx,
13308 OpcP, RegOpc(jump_target) );
13309 ins_pipe( pipe_jmp );
13310 %}
13312 // Create exception oop: created by stack-crawling runtime code.
13313 // Created exception is now available to this handler, and is setup
13314 // just prior to jumping to this handler. No code emitted.
13315 instruct CreateException( eAXRegP ex_oop )
13316 %{
13317 match(Set ex_oop (CreateEx));
13319 size(0);
13320 // use the following format syntax
13321 format %{ "# exception oop is in EAX; no code emitted" %}
13322 ins_encode();
13323 ins_pipe( empty );
13324 %}
13327 // Rethrow exception:
13328 // The exception oop will come in the first argument position.
13329 // Then JUMP (not call) to the rethrow stub code.
13330 instruct RethrowException()
13331 %{
13332 match(Rethrow);
13334 // use the following format syntax
13335 format %{ "JMP rethrow_stub" %}
13336 ins_encode(enc_rethrow);
13337 ins_pipe( pipe_jmp );
13338 %}
13340 // inlined locking and unlocking
13343 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13344 match( Set cr (FastLock object box) );
13345 effect( TEMP tmp, TEMP scr );
13346 ins_cost(300);
13347 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13348 ins_encode( Fast_Lock(object,box,tmp,scr) );
13349 ins_pipe( pipe_slow );
13350 ins_pc_relative(1);
13351 %}
13353 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13354 match( Set cr (FastUnlock object box) );
13355 effect( TEMP tmp );
13356 ins_cost(300);
13357 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13358 ins_encode( Fast_Unlock(object,box,tmp) );
13359 ins_pipe( pipe_slow );
13360 ins_pc_relative(1);
13361 %}
13365 // ============================================================================
13366 // Safepoint Instruction
13367 instruct safePoint_poll(eFlagsReg cr) %{
13368 match(SafePoint);
13369 effect(KILL cr);
13371 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13372 // On SPARC that might be acceptable as we can generate the address with
13373 // just a sethi, saving an or. By polling at offset 0 we can end up
13374 // putting additional pressure on the index-0 in the D$. Because of
13375 // alignment (just like the situation at hand) the lower indices tend
13376 // to see more traffic. It'd be better to change the polling address
13377 // to offset 0 of the last $line in the polling page.
13379 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13380 ins_cost(125);
13381 size(6) ;
13382 ins_encode( Safepoint_Poll() );
13383 ins_pipe( ialu_reg_mem );
13384 %}
13386 //----------PEEPHOLE RULES-----------------------------------------------------
13387 // These must follow all instruction definitions as they use the names
13388 // defined in the instructions definitions.
13389 //
13390 // peepmatch ( root_instr_name [preceding_instruction]* );
13391 //
13392 // peepconstraint %{
13393 // (instruction_number.operand_name relational_op instruction_number.operand_name
13394 // [, ...] );
13395 // // instruction numbers are zero-based using left to right order in peepmatch
13396 //
13397 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13398 // // provide an instruction_number.operand_name for each operand that appears
13399 // // in the replacement instruction's match rule
13400 //
13401 // ---------VM FLAGS---------------------------------------------------------
13402 //
13403 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13404 //
13405 // Each peephole rule is given an identifying number starting with zero and
13406 // increasing by one in the order seen by the parser. An individual peephole
13407 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13408 // on the command-line.
13409 //
13410 // ---------CURRENT LIMITATIONS----------------------------------------------
13411 //
13412 // Only match adjacent instructions in same basic block
13413 // Only equality constraints
13414 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13415 // Only one replacement instruction
13416 //
13417 // ---------EXAMPLE----------------------------------------------------------
13418 //
13419 // // pertinent parts of existing instructions in architecture description
13420 // instruct movI(eRegI dst, eRegI src) %{
13421 // match(Set dst (CopyI src));
13422 // %}
13423 //
13424 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13425 // match(Set dst (AddI dst src));
13426 // effect(KILL cr);
13427 // %}
13428 //
13429 // // Change (inc mov) to lea
13430 // peephole %{
13431 // // increment preceeded by register-register move
13432 // peepmatch ( incI_eReg movI );
13433 // // require that the destination register of the increment
13434 // // match the destination register of the move
13435 // peepconstraint ( 0.dst == 1.dst );
13436 // // construct a replacement instruction that sets
13437 // // the destination to ( move's source register + one )
13438 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13439 // %}
13440 //
13441 // Implementation no longer uses movX instructions since
13442 // machine-independent system no longer uses CopyX nodes.
13443 //
13444 // peephole %{
13445 // peepmatch ( incI_eReg movI );
13446 // peepconstraint ( 0.dst == 1.dst );
13447 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13448 // %}
13449 //
13450 // peephole %{
13451 // peepmatch ( decI_eReg movI );
13452 // peepconstraint ( 0.dst == 1.dst );
13453 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13454 // %}
13455 //
13456 // peephole %{
13457 // peepmatch ( addI_eReg_imm movI );
13458 // peepconstraint ( 0.dst == 1.dst );
13459 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13460 // %}
13461 //
13462 // peephole %{
13463 // peepmatch ( addP_eReg_imm movP );
13464 // peepconstraint ( 0.dst == 1.dst );
13465 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13466 // %}
13468 // // Change load of spilled value to only a spill
13469 // instruct storeI(memory mem, eRegI src) %{
13470 // match(Set mem (StoreI mem src));
13471 // %}
13472 //
13473 // instruct loadI(eRegI dst, memory mem) %{
13474 // match(Set dst (LoadI mem));
13475 // %}
13476 //
13477 peephole %{
13478 peepmatch ( loadI storeI );
13479 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13480 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13481 %}
13483 //----------SMARTSPILL RULES---------------------------------------------------
13484 // These must follow all instruction definitions as they use the names
13485 // defined in the instructions definitions.