Thu, 19 Mar 2009 09:13:24 -0700
Merge
1 //
2 // Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
25 // X86 Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundary (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
242 #define __ _masm.
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
282 static int sizeof_FFree_Float_Stack_All = -1;
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
295 //
296 // Compute padding required for nodes which need alignment
297 //
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
607 }
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
669 emit_opcode(cbuf, 0x58 | EBP_enc);
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
690 size++; // popl rbp,
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
708 int MachEpilogNode::safepoint_offset() const { return 0; }
710 //=============================================================================
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
886 // Generate spill code!
887 int size = 0;
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1042 assert( size > 0, "missed a case" );
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1063 Unimplemented();
1064 }
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1133 //=============================================================================
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1284 int Matcher::regnum_to_fpu_offset(int regnum) {
1285 return regnum - 32; // The FP registers are in the second chunk
1286 }
1288 bool is_positive_zero_float(jfloat f) {
1289 return jint_cast(f) == jint_cast(0.0F);
1290 }
1292 bool is_positive_one_float(jfloat f) {
1293 return jint_cast(f) == jint_cast(1.0F);
1294 }
1296 bool is_positive_zero_double(jdouble d) {
1297 return jlong_cast(d) == jlong_cast(0.0);
1298 }
1300 bool is_positive_one_double(jdouble d) {
1301 return jlong_cast(d) == jlong_cast(1.0);
1302 }
1304 // This is UltraSparc specific, true just means we have fast l2f conversion
1305 const bool Matcher::convL2FSupported(void) {
1306 return true;
1307 }
1309 // Vector width in bytes
1310 const uint Matcher::vector_width_in_bytes(void) {
1311 return UseSSE >= 2 ? 8 : 0;
1312 }
1314 // Vector ideal reg
1315 const uint Matcher::vector_ideal_reg(void) {
1316 return Op_RegD;
1317 }
1319 // Is this branch offset short enough that a short branch can be used?
1320 //
1321 // NOTE: If the platform does not provide any short branch variants, then
1322 // this method should return false for offset 0.
1323 bool Matcher::is_short_branch_offset(int rule, int offset) {
1324 // the short version of jmpConUCF2 contains multiple branches,
1325 // making the reach slightly less
1326 if (rule == jmpConUCF2_rule)
1327 return (-126 <= offset && offset <= 125);
1328 return (-128 <= offset && offset <= 127);
1329 }
1331 const bool Matcher::isSimpleConstant64(jlong value) {
1332 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1333 return false;
1334 }
1336 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1337 const bool Matcher::init_array_count_is_in_bytes = false;
1339 // Threshold size for cleararray.
1340 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1342 // Should the Matcher clone shifts on addressing modes, expecting them to
1343 // be subsumed into complex addressing expressions or compute them into
1344 // registers? True for Intel but false for most RISCs
1345 const bool Matcher::clone_shift_expressions = true;
1347 // Is it better to copy float constants, or load them directly from memory?
1348 // Intel can load a float constant from a direct address, requiring no
1349 // extra registers. Most RISCs will have to materialize an address into a
1350 // register first, so they would do better to copy the constant from stack.
1351 const bool Matcher::rematerialize_float_constants = true;
1353 // If CPU can load and store mis-aligned doubles directly then no fixup is
1354 // needed. Else we split the double into 2 integer pieces and move it
1355 // piece-by-piece. Only happens when passing doubles into C code as the
1356 // Java calling convention forces doubles to be aligned.
1357 const bool Matcher::misaligned_doubles_ok = true;
1360 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1361 // Get the memory operand from the node
1362 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1363 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1364 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1365 uint opcnt = 1; // First operand
1366 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1367 while( idx >= skipped+num_edges ) {
1368 skipped += num_edges;
1369 opcnt++; // Bump operand count
1370 assert( opcnt < numopnds, "Accessing non-existent operand" );
1371 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1372 }
1374 MachOper *memory = node->_opnds[opcnt];
1375 MachOper *new_memory = NULL;
1376 switch (memory->opcode()) {
1377 case DIRECT:
1378 case INDOFFSET32X:
1379 // No transformation necessary.
1380 return;
1381 case INDIRECT:
1382 new_memory = new (C) indirect_win95_safeOper( );
1383 break;
1384 case INDOFFSET8:
1385 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1386 break;
1387 case INDOFFSET32:
1388 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1389 break;
1390 case INDINDEXOFFSET:
1391 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1392 break;
1393 case INDINDEXSCALE:
1394 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1395 break;
1396 case INDINDEXSCALEOFFSET:
1397 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1398 break;
1399 case LOAD_LONG_INDIRECT:
1400 case LOAD_LONG_INDOFFSET32:
1401 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1402 return;
1403 default:
1404 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1405 return;
1406 }
1407 node->_opnds[opcnt] = new_memory;
1408 }
1410 // Advertise here if the CPU requires explicit rounding operations
1411 // to implement the UseStrictFP mode.
1412 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1414 // Do floats take an entire double register or just half?
1415 const bool Matcher::float_in_double = true;
1416 // Do ints take an entire long register or just half?
1417 const bool Matcher::int_in_long = false;
1419 // Return whether or not this register is ever used as an argument. This
1420 // function is used on startup to build the trampoline stubs in generateOptoStub.
1421 // Registers not mentioned will be killed by the VM call in the trampoline, and
1422 // arguments in those registers not be available to the callee.
1423 bool Matcher::can_be_java_arg( int reg ) {
1424 if( reg == ECX_num || reg == EDX_num ) return true;
1425 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1426 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1427 return false;
1428 }
1430 bool Matcher::is_spillable_arg( int reg ) {
1431 return can_be_java_arg(reg);
1432 }
1434 // Register for DIVI projection of divmodI
1435 RegMask Matcher::divI_proj_mask() {
1436 return EAX_REG_mask;
1437 }
1439 // Register for MODI projection of divmodI
1440 RegMask Matcher::modI_proj_mask() {
1441 return EDX_REG_mask;
1442 }
1444 // Register for DIVL projection of divmodL
1445 RegMask Matcher::divL_proj_mask() {
1446 ShouldNotReachHere();
1447 return RegMask();
1448 }
1450 // Register for MODL projection of divmodL
1451 RegMask Matcher::modL_proj_mask() {
1452 ShouldNotReachHere();
1453 return RegMask();
1454 }
1456 %}
1458 //----------ENCODING BLOCK-----------------------------------------------------
1459 // This block specifies the encoding classes used by the compiler to output
1460 // byte streams. Encoding classes generate functions which are called by
1461 // Machine Instruction Nodes in order to generate the bit encoding of the
1462 // instruction. Operands specify their base encoding interface with the
1463 // interface keyword. There are currently supported four interfaces,
1464 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1465 // operand to generate a function which returns its register number when
1466 // queried. CONST_INTER causes an operand to generate a function which
1467 // returns the value of the constant when queried. MEMORY_INTER causes an
1468 // operand to generate four functions which return the Base Register, the
1469 // Index Register, the Scale Value, and the Offset Value of the operand when
1470 // queried. COND_INTER causes an operand to generate six functions which
1471 // return the encoding code (ie - encoding bits for the instruction)
1472 // associated with each basic boolean condition for a conditional instruction.
1473 // Instructions specify two basic values for encoding. They use the
1474 // ins_encode keyword to specify their encoding class (which must be one of
1475 // the class names specified in the encoding block), and they use the
1476 // opcode keyword to specify, in order, their primary, secondary, and
1477 // tertiary opcode. Only the opcode sections which a particular instruction
1478 // needs for encoding need to be specified.
1479 encode %{
1480 // Build emit functions for each basic byte or larger field in the intel
1481 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1482 // code in the enc_class source block. Emit functions will live in the
1483 // main source block for now. In future, we can generalize this by
1484 // adding a syntax that specifies the sizes of fields in an order,
1485 // so that the adlc can build the emit functions automagically
1487 // Emit primary opcode
1488 enc_class OpcP %{
1489 emit_opcode(cbuf, $primary);
1490 %}
1492 // Emit secondary opcode
1493 enc_class OpcS %{
1494 emit_opcode(cbuf, $secondary);
1495 %}
1497 // Emit opcode directly
1498 enc_class Opcode(immI d8) %{
1499 emit_opcode(cbuf, $d8$$constant);
1500 %}
1502 enc_class SizePrefix %{
1503 emit_opcode(cbuf,0x66);
1504 %}
1506 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1507 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1508 %}
1510 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1511 emit_opcode(cbuf,$opcode$$constant);
1512 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1513 %}
1515 enc_class mov_r32_imm0( eRegI dst ) %{
1516 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1517 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1518 %}
1520 enc_class cdq_enc %{
1521 // Full implementation of Java idiv and irem; checks for
1522 // special case as described in JVM spec., p.243 & p.271.
1523 //
1524 // normal case special case
1525 //
1526 // input : rax,: dividend min_int
1527 // reg: divisor -1
1528 //
1529 // output: rax,: quotient (= rax, idiv reg) min_int
1530 // rdx: remainder (= rax, irem reg) 0
1531 //
1532 // Code sequnce:
1533 //
1534 // 81 F8 00 00 00 80 cmp rax,80000000h
1535 // 0F 85 0B 00 00 00 jne normal_case
1536 // 33 D2 xor rdx,edx
1537 // 83 F9 FF cmp rcx,0FFh
1538 // 0F 84 03 00 00 00 je done
1539 // normal_case:
1540 // 99 cdq
1541 // F7 F9 idiv rax,ecx
1542 // done:
1543 //
1544 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1545 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1546 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1547 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1548 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1549 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1550 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1551 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1552 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1553 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1554 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1555 // normal_case:
1556 emit_opcode(cbuf,0x99); // cdq
1557 // idiv (note: must be emitted by the user of this rule)
1558 // normal:
1559 %}
1561 // Dense encoding for older common ops
1562 enc_class Opc_plus(immI opcode, eRegI reg) %{
1563 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1564 %}
1567 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1568 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1569 // Check for 8-bit immediate, and set sign extend bit in opcode
1570 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1571 emit_opcode(cbuf, $primary | 0x02);
1572 }
1573 else { // If 32-bit immediate
1574 emit_opcode(cbuf, $primary);
1575 }
1576 %}
1578 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1579 // Emit primary opcode and set sign-extend bit
1580 // Check for 8-bit immediate, and set sign extend bit in opcode
1581 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1582 emit_opcode(cbuf, $primary | 0x02); }
1583 else { // If 32-bit immediate
1584 emit_opcode(cbuf, $primary);
1585 }
1586 // Emit r/m byte with secondary opcode, after primary opcode.
1587 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1588 %}
1590 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1591 // Check for 8-bit immediate, and set sign extend bit in opcode
1592 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1593 $$$emit8$imm$$constant;
1594 }
1595 else { // If 32-bit immediate
1596 // Output immediate
1597 $$$emit32$imm$$constant;
1598 }
1599 %}
1601 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1602 // Emit primary opcode and set sign-extend bit
1603 // Check for 8-bit immediate, and set sign extend bit in opcode
1604 int con = (int)$imm$$constant; // Throw away top bits
1605 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1606 // Emit r/m byte with secondary opcode, after primary opcode.
1607 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1608 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1609 else emit_d32(cbuf,con);
1610 %}
1612 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1613 // Emit primary opcode and set sign-extend bit
1614 // Check for 8-bit immediate, and set sign extend bit in opcode
1615 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1616 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1617 // Emit r/m byte with tertiary opcode, after primary opcode.
1618 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1619 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1620 else emit_d32(cbuf,con);
1621 %}
1623 enc_class Lbl (label labl) %{ // JMP, CALL
1624 Label *l = $labl$$label;
1625 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1626 %}
1628 enc_class LblShort (label labl) %{ // JMP, CALL
1629 Label *l = $labl$$label;
1630 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1631 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1632 emit_d8(cbuf, disp);
1633 %}
1635 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1636 emit_cc(cbuf, $secondary, $dst$$reg );
1637 %}
1639 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1640 int destlo = $dst$$reg;
1641 int desthi = HIGH_FROM_LOW(destlo);
1642 // bswap lo
1643 emit_opcode(cbuf, 0x0F);
1644 emit_cc(cbuf, 0xC8, destlo);
1645 // bswap hi
1646 emit_opcode(cbuf, 0x0F);
1647 emit_cc(cbuf, 0xC8, desthi);
1648 // xchg lo and hi
1649 emit_opcode(cbuf, 0x87);
1650 emit_rm(cbuf, 0x3, destlo, desthi);
1651 %}
1653 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1654 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1655 %}
1657 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1658 Label *l = $labl$$label;
1659 $$$emit8$primary;
1660 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1661 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1662 %}
1664 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1665 Label *l = $labl$$label;
1666 emit_cc(cbuf, $primary, $cop$$cmpcode);
1667 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1668 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1669 emit_d8(cbuf, disp);
1670 %}
1672 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1673 $$$emit8$primary;
1674 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1675 %}
1677 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1678 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1679 emit_d8(cbuf, op >> 8 );
1680 emit_d8(cbuf, op & 255);
1681 %}
1683 // emulate a CMOV with a conditional branch around a MOV
1684 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1685 // Invert sense of branch from sense of CMOV
1686 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1687 emit_d8( cbuf, $brOffs$$constant );
1688 %}
1690 enc_class enc_PartialSubtypeCheck( ) %{
1691 Register Redi = as_Register(EDI_enc); // result register
1692 Register Reax = as_Register(EAX_enc); // super class
1693 Register Recx = as_Register(ECX_enc); // killed
1694 Register Resi = as_Register(ESI_enc); // sub class
1695 Label miss;
1697 MacroAssembler _masm(&cbuf);
1698 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1699 NULL, &miss,
1700 /*set_cond_codes:*/ true);
1701 if ($primary) {
1702 __ xorptr(Redi, Redi);
1703 }
1704 __ bind(miss);
1705 %}
1707 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1708 MacroAssembler masm(&cbuf);
1709 int start = masm.offset();
1710 if (UseSSE >= 2) {
1711 if (VerifyFPU) {
1712 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1713 }
1714 } else {
1715 // External c_calling_convention expects the FPU stack to be 'clean'.
1716 // Compiled code leaves it dirty. Do cleanup now.
1717 masm.empty_FPU_stack();
1718 }
1719 if (sizeof_FFree_Float_Stack_All == -1) {
1720 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1721 } else {
1722 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1723 }
1724 %}
1726 enc_class Verify_FPU_For_Leaf %{
1727 if( VerifyFPU ) {
1728 MacroAssembler masm(&cbuf);
1729 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1730 }
1731 %}
1733 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1734 // This is the instruction starting address for relocation info.
1735 cbuf.set_inst_mark();
1736 $$$emit8$primary;
1737 // CALL directly to the runtime
1738 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1739 runtime_call_Relocation::spec(), RELOC_IMM32 );
1741 if (UseSSE >= 2) {
1742 MacroAssembler _masm(&cbuf);
1743 BasicType rt = tf()->return_type();
1745 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1746 // A C runtime call where the return value is unused. In SSE2+
1747 // mode the result needs to be removed from the FPU stack. It's
1748 // likely that this function call could be removed by the
1749 // optimizer if the C function is a pure function.
1750 __ ffree(0);
1751 } else if (rt == T_FLOAT) {
1752 __ lea(rsp, Address(rsp, -4));
1753 __ fstp_s(Address(rsp, 0));
1754 __ movflt(xmm0, Address(rsp, 0));
1755 __ lea(rsp, Address(rsp, 4));
1756 } else if (rt == T_DOUBLE) {
1757 __ lea(rsp, Address(rsp, -8));
1758 __ fstp_d(Address(rsp, 0));
1759 __ movdbl(xmm0, Address(rsp, 0));
1760 __ lea(rsp, Address(rsp, 8));
1761 }
1762 }
1763 %}
1766 enc_class pre_call_FPU %{
1767 // If method sets FPU control word restore it here
1768 if( Compile::current()->in_24_bit_fp_mode() ) {
1769 MacroAssembler masm(&cbuf);
1770 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1771 }
1772 %}
1774 enc_class post_call_FPU %{
1775 // If method sets FPU control word do it here also
1776 if( Compile::current()->in_24_bit_fp_mode() ) {
1777 MacroAssembler masm(&cbuf);
1778 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1779 }
1780 %}
1782 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1783 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1784 // who we intended to call.
1785 cbuf.set_inst_mark();
1786 $$$emit8$primary;
1787 if ( !_method ) {
1788 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1789 runtime_call_Relocation::spec(), RELOC_IMM32 );
1790 } else if(_optimized_virtual) {
1791 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1792 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1793 } else {
1794 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1795 static_call_Relocation::spec(), RELOC_IMM32 );
1796 }
1797 if( _method ) { // Emit stub for static call
1798 emit_java_to_interp(cbuf);
1799 }
1800 %}
1802 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1803 // !!!!!
1804 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1805 // emit_call_dynamic_prologue( cbuf );
1806 cbuf.set_inst_mark();
1807 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1808 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1809 address virtual_call_oop_addr = cbuf.inst_mark();
1810 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1811 // who we intended to call.
1812 cbuf.set_inst_mark();
1813 $$$emit8$primary;
1814 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1815 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1816 %}
1818 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1819 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1820 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1822 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1823 cbuf.set_inst_mark();
1824 $$$emit8$primary;
1825 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1826 emit_d8(cbuf, disp); // Displacement
1828 %}
1830 enc_class Xor_Reg (eRegI dst) %{
1831 emit_opcode(cbuf, 0x33);
1832 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1833 %}
1835 // Following encoding is no longer used, but may be restored if calling
1836 // convention changes significantly.
1837 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1838 //
1839 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1840 // // int ic_reg = Matcher::inline_cache_reg();
1841 // // int ic_encode = Matcher::_regEncode[ic_reg];
1842 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1843 // // int imo_encode = Matcher::_regEncode[imo_reg];
1844 //
1845 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1846 // // // so we load it immediately before the call
1847 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1848 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1849 //
1850 // // xor rbp,ebp
1851 // emit_opcode(cbuf, 0x33);
1852 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1853 //
1854 // // CALL to interpreter.
1855 // cbuf.set_inst_mark();
1856 // $$$emit8$primary;
1857 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1858 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1859 // %}
1861 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1862 $$$emit8$primary;
1863 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1864 $$$emit8$shift$$constant;
1865 %}
1867 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1868 // Load immediate does not have a zero or sign extended version
1869 // for 8-bit immediates
1870 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1871 $$$emit32$src$$constant;
1872 %}
1874 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, $primary + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1881 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 int dst_enc = $dst$$reg;
1885 int src_con = $src$$constant & 0x0FFFFFFFFL;
1886 if (src_con == 0) {
1887 // xor dst, dst
1888 emit_opcode(cbuf, 0x33);
1889 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1890 } else {
1891 emit_opcode(cbuf, $primary + dst_enc);
1892 emit_d32(cbuf, src_con);
1893 }
1894 %}
1896 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1897 // Load immediate does not have a zero or sign extended version
1898 // for 8-bit immediates
1899 int dst_enc = $dst$$reg + 2;
1900 int src_con = ((julong)($src$$constant)) >> 32;
1901 if (src_con == 0) {
1902 // xor dst, dst
1903 emit_opcode(cbuf, 0x33);
1904 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1905 } else {
1906 emit_opcode(cbuf, $primary + dst_enc);
1907 emit_d32(cbuf, src_con);
1908 }
1909 %}
1912 enc_class LdImmD (immD src) %{ // Load Immediate
1913 if( is_positive_zero_double($src$$constant)) {
1914 // FLDZ
1915 emit_opcode(cbuf,0xD9);
1916 emit_opcode(cbuf,0xEE);
1917 } else if( is_positive_one_double($src$$constant)) {
1918 // FLD1
1919 emit_opcode(cbuf,0xD9);
1920 emit_opcode(cbuf,0xE8);
1921 } else {
1922 emit_opcode(cbuf,0xDD);
1923 emit_rm(cbuf, 0x0, 0x0, 0x5);
1924 emit_double_constant(cbuf, $src$$constant);
1925 }
1926 %}
1929 enc_class LdImmF (immF src) %{ // Load Immediate
1930 if( is_positive_zero_float($src$$constant)) {
1931 emit_opcode(cbuf,0xD9);
1932 emit_opcode(cbuf,0xEE);
1933 } else if( is_positive_one_float($src$$constant)) {
1934 emit_opcode(cbuf,0xD9);
1935 emit_opcode(cbuf,0xE8);
1936 } else {
1937 $$$emit8$primary;
1938 // Load immediate does not have a zero or sign extended version
1939 // for 8-bit immediates
1940 // First load to TOS, then move to dst
1941 emit_rm(cbuf, 0x0, 0x0, 0x5);
1942 emit_float_constant(cbuf, $src$$constant);
1943 }
1944 %}
1946 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1947 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1948 emit_float_constant(cbuf, $con$$constant);
1949 %}
1951 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1952 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1953 emit_double_constant(cbuf, $con$$constant);
1954 %}
1956 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1957 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1958 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1959 emit_opcode(cbuf, 0x0F);
1960 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1961 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1962 emit_double_constant(cbuf, $con$$constant);
1963 %}
1965 enc_class Opc_MemImm_F(immF src) %{
1966 cbuf.set_inst_mark();
1967 $$$emit8$primary;
1968 emit_rm(cbuf, 0x0, $secondary, 0x5);
1969 emit_float_constant(cbuf, $src$$constant);
1970 %}
1973 enc_class MovI2X_reg(regX dst, eRegI src) %{
1974 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1975 emit_opcode(cbuf, 0x0F );
1976 emit_opcode(cbuf, 0x6E );
1977 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1978 %}
1980 enc_class MovX2I_reg(eRegI dst, regX src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x7E );
1984 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1985 %}
1987 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1988 { // MOVD $dst,$src.lo
1989 emit_opcode(cbuf,0x66);
1990 emit_opcode(cbuf,0x0F);
1991 emit_opcode(cbuf,0x6E);
1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1993 }
1994 { // MOVD $tmp,$src.hi
1995 emit_opcode(cbuf,0x66);
1996 emit_opcode(cbuf,0x0F);
1997 emit_opcode(cbuf,0x6E);
1998 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
1999 }
2000 { // PUNPCKLDQ $dst,$tmp
2001 emit_opcode(cbuf,0x66);
2002 emit_opcode(cbuf,0x0F);
2003 emit_opcode(cbuf,0x62);
2004 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2005 }
2006 %}
2008 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2009 { // MOVD $dst.lo,$src
2010 emit_opcode(cbuf,0x66);
2011 emit_opcode(cbuf,0x0F);
2012 emit_opcode(cbuf,0x7E);
2013 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2014 }
2015 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2016 emit_opcode(cbuf,0xF2);
2017 emit_opcode(cbuf,0x0F);
2018 emit_opcode(cbuf,0x70);
2019 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2020 emit_d8(cbuf, 0x4E);
2021 }
2022 { // MOVD $dst.hi,$tmp
2023 emit_opcode(cbuf,0x66);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x7E);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2027 }
2028 %}
2031 // Encode a reg-reg copy. If it is useless, then empty encoding.
2032 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2033 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2034 %}
2036 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2037 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2038 %}
2040 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2041 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2042 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2043 %}
2045 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2046 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2047 %}
2049 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2050 $$$emit8$primary;
2051 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2052 %}
2054 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2055 $$$emit8$secondary;
2056 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2057 %}
2059 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2060 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2061 %}
2063 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2064 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2065 %}
2067 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2068 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2069 %}
2071 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2072 // Output immediate
2073 $$$emit32$src$$constant;
2074 %}
2076 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2077 // Output Float immediate bits
2078 jfloat jf = $src$$constant;
2079 int jf_as_bits = jint_cast( jf );
2080 emit_d32(cbuf, jf_as_bits);
2081 %}
2083 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2090 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2091 // Output immediate
2092 $$$emit16$src$$constant;
2093 %}
2095 enc_class Con_d32(immI src) %{
2096 emit_d32(cbuf,$src$$constant);
2097 %}
2099 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2100 // Output immediate memory reference
2101 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2102 emit_d32(cbuf, 0x00);
2103 %}
2105 enc_class lock_prefix( ) %{
2106 if( os::is_MP() )
2107 emit_opcode(cbuf,0xF0); // [Lock]
2108 %}
2110 // Cmp-xchg long value.
2111 // Note: we need to swap rbx, and rcx before and after the
2112 // cmpxchg8 instruction because the instruction uses
2113 // rcx as the high order word of the new value to store but
2114 // our register encoding uses rbx,.
2115 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2117 // XCHG rbx,ecx
2118 emit_opcode(cbuf,0x87);
2119 emit_opcode(cbuf,0xD9);
2120 // [Lock]
2121 if( os::is_MP() )
2122 emit_opcode(cbuf,0xF0);
2123 // CMPXCHG8 [Eptr]
2124 emit_opcode(cbuf,0x0F);
2125 emit_opcode(cbuf,0xC7);
2126 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2127 // XCHG rbx,ecx
2128 emit_opcode(cbuf,0x87);
2129 emit_opcode(cbuf,0xD9);
2130 %}
2132 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2133 // [Lock]
2134 if( os::is_MP() )
2135 emit_opcode(cbuf,0xF0);
2137 // CMPXCHG [Eptr]
2138 emit_opcode(cbuf,0x0F);
2139 emit_opcode(cbuf,0xB1);
2140 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2141 %}
2143 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2144 int res_encoding = $res$$reg;
2146 // MOV res,0
2147 emit_opcode( cbuf, 0xB8 + res_encoding);
2148 emit_d32( cbuf, 0 );
2149 // JNE,s fail
2150 emit_opcode(cbuf,0x75);
2151 emit_d8(cbuf, 5 );
2152 // MOV res,1
2153 emit_opcode( cbuf, 0xB8 + res_encoding);
2154 emit_d32( cbuf, 1 );
2155 // fail:
2156 %}
2158 enc_class set_instruction_start( ) %{
2159 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2160 %}
2162 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2163 int reg_encoding = $ereg$$reg;
2164 int base = $mem$$base;
2165 int index = $mem$$index;
2166 int scale = $mem$$scale;
2167 int displace = $mem$$disp;
2168 bool disp_is_oop = $mem->disp_is_oop();
2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2170 %}
2172 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2173 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2174 int base = $mem$$base;
2175 int index = $mem$$index;
2176 int scale = $mem$$scale;
2177 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2178 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2179 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2180 %}
2182 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2183 int r1, r2;
2184 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2185 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2186 emit_opcode(cbuf,0x0F);
2187 emit_opcode(cbuf,$tertiary);
2188 emit_rm(cbuf, 0x3, r1, r2);
2189 emit_d8(cbuf,$cnt$$constant);
2190 emit_d8(cbuf,$primary);
2191 emit_rm(cbuf, 0x3, $secondary, r1);
2192 emit_d8(cbuf,$cnt$$constant);
2193 %}
2195 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2196 emit_opcode( cbuf, 0x8B ); // Move
2197 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2198 emit_d8(cbuf,$primary);
2199 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2200 emit_d8(cbuf,$cnt$$constant-32);
2201 emit_d8(cbuf,$primary);
2202 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2203 emit_d8(cbuf,31);
2204 %}
2206 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2207 int r1, r2;
2208 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2209 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2211 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2212 emit_rm(cbuf, 0x3, r1, r2);
2213 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2214 emit_opcode(cbuf,$primary);
2215 emit_rm(cbuf, 0x3, $secondary, r1);
2216 emit_d8(cbuf,$cnt$$constant-32);
2217 }
2218 emit_opcode(cbuf,0x33); // XOR r2,r2
2219 emit_rm(cbuf, 0x3, r2, r2);
2220 %}
2222 // Clone of RegMem but accepts an extra parameter to access each
2223 // half of a double in memory; it never needs relocation info.
2224 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2225 emit_opcode(cbuf,$opcode$$constant);
2226 int reg_encoding = $rm_reg$$reg;
2227 int base = $mem$$base;
2228 int index = $mem$$index;
2229 int scale = $mem$$scale;
2230 int displace = $mem$$disp + $disp_for_half$$constant;
2231 bool disp_is_oop = false;
2232 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2233 %}
2235 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2236 //
2237 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2238 // and it never needs relocation information.
2239 // Frequently used to move data between FPU's Stack Top and memory.
2240 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2241 int rm_byte_opcode = $rm_opcode$$constant;
2242 int base = $mem$$base;
2243 int index = $mem$$index;
2244 int scale = $mem$$scale;
2245 int displace = $mem$$disp;
2246 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2247 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2248 %}
2250 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2251 int rm_byte_opcode = $rm_opcode$$constant;
2252 int base = $mem$$base;
2253 int index = $mem$$index;
2254 int scale = $mem$$scale;
2255 int displace = $mem$$disp;
2256 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2257 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2258 %}
2260 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2261 int reg_encoding = $dst$$reg;
2262 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2263 int index = 0x04; // 0x04 indicates no index
2264 int scale = 0x00; // 0x00 indicates no scale
2265 int displace = $src1$$constant; // 0x00 indicates no displacement
2266 bool disp_is_oop = false;
2267 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2268 %}
2270 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2271 // Compare dst,src
2272 emit_opcode(cbuf,0x3B);
2273 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2274 // jmp dst < src around move
2275 emit_opcode(cbuf,0x7C);
2276 emit_d8(cbuf,2);
2277 // move dst,src
2278 emit_opcode(cbuf,0x8B);
2279 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2280 %}
2282 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2283 // Compare dst,src
2284 emit_opcode(cbuf,0x3B);
2285 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2286 // jmp dst > src around move
2287 emit_opcode(cbuf,0x7F);
2288 emit_d8(cbuf,2);
2289 // move dst,src
2290 emit_opcode(cbuf,0x8B);
2291 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2292 %}
2294 enc_class enc_FP_store(memory mem, regD src) %{
2295 // If src is FPR1, we can just FST to store it.
2296 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2297 int reg_encoding = 0x2; // Just store
2298 int base = $mem$$base;
2299 int index = $mem$$index;
2300 int scale = $mem$$scale;
2301 int displace = $mem$$disp;
2302 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2303 if( $src$$reg != FPR1L_enc ) {
2304 reg_encoding = 0x3; // Store & pop
2305 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2306 emit_d8( cbuf, 0xC0-1+$src$$reg );
2307 }
2308 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2309 emit_opcode(cbuf,$primary);
2310 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2311 %}
2313 enc_class neg_reg(eRegI dst) %{
2314 // NEG $dst
2315 emit_opcode(cbuf,0xF7);
2316 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2317 %}
2319 enc_class setLT_reg(eCXRegI dst) %{
2320 // SETLT $dst
2321 emit_opcode(cbuf,0x0F);
2322 emit_opcode(cbuf,0x9C);
2323 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2324 %}
2326 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2327 int tmpReg = $tmp$$reg;
2329 // SUB $p,$q
2330 emit_opcode(cbuf,0x2B);
2331 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2332 // SBB $tmp,$tmp
2333 emit_opcode(cbuf,0x1B);
2334 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2335 // AND $tmp,$y
2336 emit_opcode(cbuf,0x23);
2337 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2338 // ADD $p,$tmp
2339 emit_opcode(cbuf,0x03);
2340 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2341 %}
2343 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2344 int tmpReg = $tmp$$reg;
2346 // SUB $p,$q
2347 emit_opcode(cbuf,0x2B);
2348 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2349 // SBB $tmp,$tmp
2350 emit_opcode(cbuf,0x1B);
2351 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2352 // AND $tmp,$y
2353 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2354 emit_opcode(cbuf,0x23);
2355 int reg_encoding = tmpReg;
2356 int base = $mem$$base;
2357 int index = $mem$$index;
2358 int scale = $mem$$scale;
2359 int displace = $mem$$disp;
2360 bool disp_is_oop = $mem->disp_is_oop();
2361 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2362 // ADD $p,$tmp
2363 emit_opcode(cbuf,0x03);
2364 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2365 %}
2367 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2368 // TEST shift,32
2369 emit_opcode(cbuf,0xF7);
2370 emit_rm(cbuf, 0x3, 0, ECX_enc);
2371 emit_d32(cbuf,0x20);
2372 // JEQ,s small
2373 emit_opcode(cbuf, 0x74);
2374 emit_d8(cbuf, 0x04);
2375 // MOV $dst.hi,$dst.lo
2376 emit_opcode( cbuf, 0x8B );
2377 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2378 // CLR $dst.lo
2379 emit_opcode(cbuf, 0x33);
2380 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2381 // small:
2382 // SHLD $dst.hi,$dst.lo,$shift
2383 emit_opcode(cbuf,0x0F);
2384 emit_opcode(cbuf,0xA5);
2385 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2386 // SHL $dst.lo,$shift"
2387 emit_opcode(cbuf,0xD3);
2388 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2389 %}
2391 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2392 // TEST shift,32
2393 emit_opcode(cbuf,0xF7);
2394 emit_rm(cbuf, 0x3, 0, ECX_enc);
2395 emit_d32(cbuf,0x20);
2396 // JEQ,s small
2397 emit_opcode(cbuf, 0x74);
2398 emit_d8(cbuf, 0x04);
2399 // MOV $dst.lo,$dst.hi
2400 emit_opcode( cbuf, 0x8B );
2401 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2402 // CLR $dst.hi
2403 emit_opcode(cbuf, 0x33);
2404 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2405 // small:
2406 // SHRD $dst.lo,$dst.hi,$shift
2407 emit_opcode(cbuf,0x0F);
2408 emit_opcode(cbuf,0xAD);
2409 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2410 // SHR $dst.hi,$shift"
2411 emit_opcode(cbuf,0xD3);
2412 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2413 %}
2415 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2416 // TEST shift,32
2417 emit_opcode(cbuf,0xF7);
2418 emit_rm(cbuf, 0x3, 0, ECX_enc);
2419 emit_d32(cbuf,0x20);
2420 // JEQ,s small
2421 emit_opcode(cbuf, 0x74);
2422 emit_d8(cbuf, 0x05);
2423 // MOV $dst.lo,$dst.hi
2424 emit_opcode( cbuf, 0x8B );
2425 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2426 // SAR $dst.hi,31
2427 emit_opcode(cbuf, 0xC1);
2428 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2429 emit_d8(cbuf, 0x1F );
2430 // small:
2431 // SHRD $dst.lo,$dst.hi,$shift
2432 emit_opcode(cbuf,0x0F);
2433 emit_opcode(cbuf,0xAD);
2434 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2435 // SAR $dst.hi,$shift"
2436 emit_opcode(cbuf,0xD3);
2437 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2438 %}
2441 // ----------------- Encodings for floating point unit -----------------
2442 // May leave result in FPU-TOS or FPU reg depending on opcodes
2443 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2444 $$$emit8$primary;
2445 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2446 %}
2448 // Pop argument in FPR0 with FSTP ST(0)
2449 enc_class PopFPU() %{
2450 emit_opcode( cbuf, 0xDD );
2451 emit_d8( cbuf, 0xD8 );
2452 %}
2454 // !!!!! equivalent to Pop_Reg_F
2455 enc_class Pop_Reg_D( regD dst ) %{
2456 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2457 emit_d8( cbuf, 0xD8+$dst$$reg );
2458 %}
2460 enc_class Push_Reg_D( regD dst ) %{
2461 emit_opcode( cbuf, 0xD9 );
2462 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2463 %}
2465 enc_class strictfp_bias1( regD dst ) %{
2466 emit_opcode( cbuf, 0xDB ); // FLD m80real
2467 emit_opcode( cbuf, 0x2D );
2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2470 emit_opcode( cbuf, 0xC8+$dst$$reg );
2471 %}
2473 enc_class strictfp_bias2( regD dst ) %{
2474 emit_opcode( cbuf, 0xDB ); // FLD m80real
2475 emit_opcode( cbuf, 0x2D );
2476 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2477 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2478 emit_opcode( cbuf, 0xC8+$dst$$reg );
2479 %}
2481 // Special case for moving an integer register to a stack slot.
2482 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2483 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2484 %}
2486 // Special case for moving a register to a stack slot.
2487 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2488 // Opcode already emitted
2489 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2490 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2491 emit_d32(cbuf, $dst$$disp); // Displacement
2492 %}
2494 // Push the integer in stackSlot 'src' onto FP-stack
2495 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2496 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2497 %}
2499 // Push the float in stackSlot 'src' onto FP-stack
2500 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2501 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2502 %}
2504 // Push the double in stackSlot 'src' onto FP-stack
2505 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2506 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2507 %}
2509 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2510 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2511 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2512 %}
2514 // Same as Pop_Mem_F except for opcode
2515 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2516 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2517 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2518 %}
2520 enc_class Pop_Reg_F( regF dst ) %{
2521 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2522 emit_d8( cbuf, 0xD8+$dst$$reg );
2523 %}
2525 enc_class Push_Reg_F( regF dst ) %{
2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2527 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2528 %}
2530 // Push FPU's float to a stack-slot, and pop FPU-stack
2531 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2532 int pop = 0x02;
2533 if ($src$$reg != FPR1L_enc) {
2534 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2535 emit_d8( cbuf, 0xC0-1+$src$$reg );
2536 pop = 0x03;
2537 }
2538 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2539 %}
2541 // Push FPU's double to a stack-slot, and pop FPU-stack
2542 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2543 int pop = 0x02;
2544 if ($src$$reg != FPR1L_enc) {
2545 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2546 emit_d8( cbuf, 0xC0-1+$src$$reg );
2547 pop = 0x03;
2548 }
2549 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2550 %}
2552 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2553 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2554 int pop = 0xD0 - 1; // -1 since we skip FLD
2555 if ($src$$reg != FPR1L_enc) {
2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2557 emit_d8( cbuf, 0xC0-1+$src$$reg );
2558 pop = 0xD8;
2559 }
2560 emit_opcode( cbuf, 0xDD );
2561 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2562 %}
2565 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2566 MacroAssembler masm(&cbuf);
2567 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2568 masm.fmul( $src2$$reg+0); // value at TOS
2569 masm.fadd( $src$$reg+0); // value at TOS
2570 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2571 %}
2574 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2575 // load dst in FPR0
2576 emit_opcode( cbuf, 0xD9 );
2577 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2578 if ($src$$reg != FPR1L_enc) {
2579 // fincstp
2580 emit_opcode (cbuf, 0xD9);
2581 emit_opcode (cbuf, 0xF7);
2582 // swap src with FPR1:
2583 // FXCH FPR1 with src
2584 emit_opcode(cbuf, 0xD9);
2585 emit_d8(cbuf, 0xC8-1+$src$$reg );
2586 // fdecstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF6);
2589 }
2590 %}
2592 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2593 // Allocate a word
2594 emit_opcode(cbuf,0x83); // SUB ESP,8
2595 emit_opcode(cbuf,0xEC);
2596 emit_d8(cbuf,0x08);
2598 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2599 emit_opcode (cbuf, 0x0F );
2600 emit_opcode (cbuf, 0x11 );
2601 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2603 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2604 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2606 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2607 emit_opcode (cbuf, 0x0F );
2608 emit_opcode (cbuf, 0x11 );
2609 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2611 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2612 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2614 %}
2616 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2617 // Allocate a word
2618 emit_opcode(cbuf,0x83); // SUB ESP,4
2619 emit_opcode(cbuf,0xEC);
2620 emit_d8(cbuf,0x04);
2622 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2623 emit_opcode (cbuf, 0x0F );
2624 emit_opcode (cbuf, 0x11 );
2625 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2627 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2628 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2630 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2631 emit_opcode (cbuf, 0x0F );
2632 emit_opcode (cbuf, 0x11 );
2633 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2635 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2636 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2638 %}
2640 enc_class Push_ResultXD(regXD dst) %{
2641 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2643 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2644 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2645 emit_opcode (cbuf, 0x0F );
2646 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2647 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2649 emit_opcode(cbuf,0x83); // ADD ESP,8
2650 emit_opcode(cbuf,0xC4);
2651 emit_d8(cbuf,0x08);
2652 %}
2654 enc_class Push_ResultX(regX dst, immI d8) %{
2655 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2657 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2658 emit_opcode (cbuf, 0x0F );
2659 emit_opcode (cbuf, 0x10 );
2660 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2662 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2663 emit_opcode(cbuf,0xC4);
2664 emit_d8(cbuf,$d8$$constant);
2665 %}
2667 enc_class Push_SrcXD(regXD src) %{
2668 // Allocate a word
2669 emit_opcode(cbuf,0x83); // SUB ESP,8
2670 emit_opcode(cbuf,0xEC);
2671 emit_d8(cbuf,0x08);
2673 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2674 emit_opcode (cbuf, 0x0F );
2675 emit_opcode (cbuf, 0x11 );
2676 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2678 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2679 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2680 %}
2682 enc_class push_stack_temp_qword() %{
2683 emit_opcode(cbuf,0x83); // SUB ESP,8
2684 emit_opcode(cbuf,0xEC);
2685 emit_d8 (cbuf,0x08);
2686 %}
2688 enc_class pop_stack_temp_qword() %{
2689 emit_opcode(cbuf,0x83); // ADD ESP,8
2690 emit_opcode(cbuf,0xC4);
2691 emit_d8 (cbuf,0x08);
2692 %}
2694 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2695 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2696 emit_opcode (cbuf, 0x0F );
2697 emit_opcode (cbuf, 0x11 );
2698 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2700 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2701 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2702 %}
2704 // Compute X^Y using Intel's fast hardware instructions, if possible.
2705 // Otherwise return a NaN.
2706 enc_class pow_exp_core_encoding %{
2707 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2708 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2710 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2711 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2712 emit_opcode(cbuf,0x1C);
2713 emit_d8(cbuf,0x24);
2714 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2716 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2717 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2718 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2719 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2720 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2721 emit_d32(cbuf,0xFFFFF800);
2722 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2723 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2724 emit_d32(cbuf,1023);
2725 emit_opcode(cbuf,0x8B); // mov rbx,eax
2726 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2727 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2728 emit_rm(cbuf,0x3,0x4,EAX_enc);
2729 emit_d8(cbuf,20);
2730 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2731 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2732 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2733 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2734 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2735 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2736 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2737 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2738 emit_d32(cbuf,0);
2739 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2740 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2741 %}
2743 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2744 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2746 enc_class Push_Result_Mod_D( regD src) %{
2747 if ($src$$reg != FPR1L_enc) {
2748 // fincstp
2749 emit_opcode (cbuf, 0xD9);
2750 emit_opcode (cbuf, 0xF7);
2751 // FXCH FPR1 with src
2752 emit_opcode(cbuf, 0xD9);
2753 emit_d8(cbuf, 0xC8-1+$src$$reg );
2754 // fdecstp
2755 emit_opcode (cbuf, 0xD9);
2756 emit_opcode (cbuf, 0xF6);
2757 }
2758 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2759 // // FSTP FPR$dst$$reg
2760 // emit_opcode( cbuf, 0xDD );
2761 // emit_d8( cbuf, 0xD8+$dst$$reg );
2762 %}
2764 enc_class fnstsw_sahf_skip_parity() %{
2765 // fnstsw ax
2766 emit_opcode( cbuf, 0xDF );
2767 emit_opcode( cbuf, 0xE0 );
2768 // sahf
2769 emit_opcode( cbuf, 0x9E );
2770 // jnp ::skip
2771 emit_opcode( cbuf, 0x7B );
2772 emit_opcode( cbuf, 0x05 );
2773 %}
2775 enc_class emitModD() %{
2776 // fprem must be iterative
2777 // :: loop
2778 // fprem
2779 emit_opcode( cbuf, 0xD9 );
2780 emit_opcode( cbuf, 0xF8 );
2781 // wait
2782 emit_opcode( cbuf, 0x9b );
2783 // fnstsw ax
2784 emit_opcode( cbuf, 0xDF );
2785 emit_opcode( cbuf, 0xE0 );
2786 // sahf
2787 emit_opcode( cbuf, 0x9E );
2788 // jp ::loop
2789 emit_opcode( cbuf, 0x0F );
2790 emit_opcode( cbuf, 0x8A );
2791 emit_opcode( cbuf, 0xF4 );
2792 emit_opcode( cbuf, 0xFF );
2793 emit_opcode( cbuf, 0xFF );
2794 emit_opcode( cbuf, 0xFF );
2795 %}
2797 enc_class fpu_flags() %{
2798 // fnstsw_ax
2799 emit_opcode( cbuf, 0xDF);
2800 emit_opcode( cbuf, 0xE0);
2801 // test ax,0x0400
2802 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2803 emit_opcode( cbuf, 0xA9 );
2804 emit_d16 ( cbuf, 0x0400 );
2805 // // // This sequence works, but stalls for 12-16 cycles on PPro
2806 // // test rax,0x0400
2807 // emit_opcode( cbuf, 0xA9 );
2808 // emit_d32 ( cbuf, 0x00000400 );
2809 //
2810 // jz exit (no unordered comparison)
2811 emit_opcode( cbuf, 0x74 );
2812 emit_d8 ( cbuf, 0x02 );
2813 // mov ah,1 - treat as LT case (set carry flag)
2814 emit_opcode( cbuf, 0xB4 );
2815 emit_d8 ( cbuf, 0x01 );
2816 // sahf
2817 emit_opcode( cbuf, 0x9E);
2818 %}
2820 enc_class cmpF_P6_fixup() %{
2821 // Fixup the integer flags in case comparison involved a NaN
2822 //
2823 // JNP exit (no unordered comparison, P-flag is set by NaN)
2824 emit_opcode( cbuf, 0x7B );
2825 emit_d8 ( cbuf, 0x03 );
2826 // MOV AH,1 - treat as LT case (set carry flag)
2827 emit_opcode( cbuf, 0xB4 );
2828 emit_d8 ( cbuf, 0x01 );
2829 // SAHF
2830 emit_opcode( cbuf, 0x9E);
2831 // NOP // target for branch to avoid branch to branch
2832 emit_opcode( cbuf, 0x90);
2833 %}
2835 // fnstsw_ax();
2836 // sahf();
2837 // movl(dst, nan_result);
2838 // jcc(Assembler::parity, exit);
2839 // movl(dst, less_result);
2840 // jcc(Assembler::below, exit);
2841 // movl(dst, equal_result);
2842 // jcc(Assembler::equal, exit);
2843 // movl(dst, greater_result);
2845 // less_result = 1;
2846 // greater_result = -1;
2847 // equal_result = 0;
2848 // nan_result = -1;
2850 enc_class CmpF_Result(eRegI dst) %{
2851 // fnstsw_ax();
2852 emit_opcode( cbuf, 0xDF);
2853 emit_opcode( cbuf, 0xE0);
2854 // sahf
2855 emit_opcode( cbuf, 0x9E);
2856 // movl(dst, nan_result);
2857 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2858 emit_d32( cbuf, -1 );
2859 // jcc(Assembler::parity, exit);
2860 emit_opcode( cbuf, 0x7A );
2861 emit_d8 ( cbuf, 0x13 );
2862 // movl(dst, less_result);
2863 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2864 emit_d32( cbuf, -1 );
2865 // jcc(Assembler::below, exit);
2866 emit_opcode( cbuf, 0x72 );
2867 emit_d8 ( cbuf, 0x0C );
2868 // movl(dst, equal_result);
2869 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2870 emit_d32( cbuf, 0 );
2871 // jcc(Assembler::equal, exit);
2872 emit_opcode( cbuf, 0x74 );
2873 emit_d8 ( cbuf, 0x05 );
2874 // movl(dst, greater_result);
2875 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2876 emit_d32( cbuf, 1 );
2877 %}
2880 // XMM version of CmpF_Result. Because the XMM compare
2881 // instructions set the EFLAGS directly. It becomes simpler than
2882 // the float version above.
2883 enc_class CmpX_Result(eRegI dst) %{
2884 MacroAssembler _masm(&cbuf);
2885 Label nan, inc, done;
2887 __ jccb(Assembler::parity, nan);
2888 __ jccb(Assembler::equal, done);
2889 __ jccb(Assembler::above, inc);
2890 __ bind(nan);
2891 __ decrement(as_Register($dst$$reg)); // NO L qqq
2892 __ jmpb(done);
2893 __ bind(inc);
2894 __ increment(as_Register($dst$$reg)); // NO L qqq
2895 __ bind(done);
2896 %}
2898 // Compare the longs and set flags
2899 // BROKEN! Do Not use as-is
2900 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2901 // CMP $src1.hi,$src2.hi
2902 emit_opcode( cbuf, 0x3B );
2903 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2904 // JNE,s done
2905 emit_opcode(cbuf,0x75);
2906 emit_d8(cbuf, 2 );
2907 // CMP $src1.lo,$src2.lo
2908 emit_opcode( cbuf, 0x3B );
2909 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2910 // done:
2911 %}
2913 enc_class convert_int_long( regL dst, eRegI src ) %{
2914 // mov $dst.lo,$src
2915 int dst_encoding = $dst$$reg;
2916 int src_encoding = $src$$reg;
2917 encode_Copy( cbuf, dst_encoding , src_encoding );
2918 // mov $dst.hi,$src
2919 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2920 // sar $dst.hi,31
2921 emit_opcode( cbuf, 0xC1 );
2922 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2923 emit_d8(cbuf, 0x1F );
2924 %}
2926 enc_class convert_long_double( eRegL src ) %{
2927 // push $src.hi
2928 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2929 // push $src.lo
2930 emit_opcode(cbuf, 0x50+$src$$reg );
2931 // fild 64-bits at [SP]
2932 emit_opcode(cbuf,0xdf);
2933 emit_d8(cbuf, 0x6C);
2934 emit_d8(cbuf, 0x24);
2935 emit_d8(cbuf, 0x00);
2936 // pop stack
2937 emit_opcode(cbuf, 0x83); // add SP, #8
2938 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2939 emit_d8(cbuf, 0x8);
2940 %}
2942 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2943 // IMUL EDX:EAX,$src1
2944 emit_opcode( cbuf, 0xF7 );
2945 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2946 // SAR EDX,$cnt-32
2947 int shift_count = ((int)$cnt$$constant) - 32;
2948 if (shift_count > 0) {
2949 emit_opcode(cbuf, 0xC1);
2950 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2951 emit_d8(cbuf, shift_count);
2952 }
2953 %}
2955 // this version doesn't have add sp, 8
2956 enc_class convert_long_double2( eRegL src ) %{
2957 // push $src.hi
2958 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2959 // push $src.lo
2960 emit_opcode(cbuf, 0x50+$src$$reg );
2961 // fild 64-bits at [SP]
2962 emit_opcode(cbuf,0xdf);
2963 emit_d8(cbuf, 0x6C);
2964 emit_d8(cbuf, 0x24);
2965 emit_d8(cbuf, 0x00);
2966 %}
2968 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2969 // Basic idea: long = (long)int * (long)int
2970 // IMUL EDX:EAX, src
2971 emit_opcode( cbuf, 0xF7 );
2972 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2973 %}
2975 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2977 // MUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2980 %}
2982 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2983 // Basic idea: lo(result) = lo(x_lo * y_lo)
2984 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2985 // MOV $tmp,$src.lo
2986 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2987 // IMUL $tmp,EDX
2988 emit_opcode( cbuf, 0x0F );
2989 emit_opcode( cbuf, 0xAF );
2990 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2991 // MOV EDX,$src.hi
2992 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2993 // IMUL EDX,EAX
2994 emit_opcode( cbuf, 0x0F );
2995 emit_opcode( cbuf, 0xAF );
2996 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2997 // ADD $tmp,EDX
2998 emit_opcode( cbuf, 0x03 );
2999 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3000 // MUL EDX:EAX,$src.lo
3001 emit_opcode( cbuf, 0xF7 );
3002 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3003 // ADD EDX,ESI
3004 emit_opcode( cbuf, 0x03 );
3005 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3006 %}
3008 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3009 // Basic idea: lo(result) = lo(src * y_lo)
3010 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3011 // IMUL $tmp,EDX,$src
3012 emit_opcode( cbuf, 0x6B );
3013 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3014 emit_d8( cbuf, (int)$src$$constant );
3015 // MOV EDX,$src
3016 emit_opcode(cbuf, 0xB8 + EDX_enc);
3017 emit_d32( cbuf, (int)$src$$constant );
3018 // MUL EDX:EAX,EDX
3019 emit_opcode( cbuf, 0xF7 );
3020 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3021 // ADD EDX,ESI
3022 emit_opcode( cbuf, 0x03 );
3023 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3024 %}
3026 enc_class long_div( eRegL src1, eRegL src2 ) %{
3027 // PUSH src1.hi
3028 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3029 // PUSH src1.lo
3030 emit_opcode(cbuf, 0x50+$src1$$reg );
3031 // PUSH src2.hi
3032 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3033 // PUSH src2.lo
3034 emit_opcode(cbuf, 0x50+$src2$$reg );
3035 // CALL directly to the runtime
3036 cbuf.set_inst_mark();
3037 emit_opcode(cbuf,0xE8); // Call into runtime
3038 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3039 // Restore stack
3040 emit_opcode(cbuf, 0x83); // add SP, #framesize
3041 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3042 emit_d8(cbuf, 4*4);
3043 %}
3045 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3046 // PUSH src1.hi
3047 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3048 // PUSH src1.lo
3049 emit_opcode(cbuf, 0x50+$src1$$reg );
3050 // PUSH src2.hi
3051 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3052 // PUSH src2.lo
3053 emit_opcode(cbuf, 0x50+$src2$$reg );
3054 // CALL directly to the runtime
3055 cbuf.set_inst_mark();
3056 emit_opcode(cbuf,0xE8); // Call into runtime
3057 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3058 // Restore stack
3059 emit_opcode(cbuf, 0x83); // add SP, #framesize
3060 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3061 emit_d8(cbuf, 4*4);
3062 %}
3064 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3065 // MOV $tmp,$src.lo
3066 emit_opcode(cbuf, 0x8B);
3067 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3068 // OR $tmp,$src.hi
3069 emit_opcode(cbuf, 0x0B);
3070 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3071 %}
3073 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3074 // CMP $src1.lo,$src2.lo
3075 emit_opcode( cbuf, 0x3B );
3076 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3077 // JNE,s skip
3078 emit_cc(cbuf, 0x70, 0x5);
3079 emit_d8(cbuf,2);
3080 // CMP $src1.hi,$src2.hi
3081 emit_opcode( cbuf, 0x3B );
3082 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3083 %}
3085 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3086 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3087 emit_opcode( cbuf, 0x3B );
3088 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3089 // MOV $tmp,$src1.hi
3090 emit_opcode( cbuf, 0x8B );
3091 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3092 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3093 emit_opcode( cbuf, 0x1B );
3094 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3095 %}
3097 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3098 // XOR $tmp,$tmp
3099 emit_opcode(cbuf,0x33); // XOR
3100 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3101 // CMP $tmp,$src.lo
3102 emit_opcode( cbuf, 0x3B );
3103 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3104 // SBB $tmp,$src.hi
3105 emit_opcode( cbuf, 0x1B );
3106 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3107 %}
3109 // Sniff, sniff... smells like Gnu Superoptimizer
3110 enc_class neg_long( eRegL dst ) %{
3111 emit_opcode(cbuf,0xF7); // NEG hi
3112 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3113 emit_opcode(cbuf,0xF7); // NEG lo
3114 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3115 emit_opcode(cbuf,0x83); // SBB hi,0
3116 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3117 emit_d8 (cbuf,0 );
3118 %}
3120 enc_class movq_ld(regXD dst, memory mem) %{
3121 MacroAssembler _masm(&cbuf);
3122 __ movq($dst$$XMMRegister, $mem$$Address);
3123 %}
3125 enc_class movq_st(memory mem, regXD src) %{
3126 MacroAssembler _masm(&cbuf);
3127 __ movq($mem$$Address, $src$$XMMRegister);
3128 %}
3130 enc_class pshufd_8x8(regX dst, regX src) %{
3131 MacroAssembler _masm(&cbuf);
3133 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3134 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3135 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3136 %}
3138 enc_class pshufd_4x16(regX dst, regX src) %{
3139 MacroAssembler _masm(&cbuf);
3141 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3142 %}
3144 enc_class pshufd(regXD dst, regXD src, int mode) %{
3145 MacroAssembler _masm(&cbuf);
3147 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3148 %}
3150 enc_class pxor(regXD dst, regXD src) %{
3151 MacroAssembler _masm(&cbuf);
3153 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3154 %}
3156 enc_class mov_i2x(regXD dst, eRegI src) %{
3157 MacroAssembler _masm(&cbuf);
3159 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3160 %}
3163 // Because the transitions from emitted code to the runtime
3164 // monitorenter/exit helper stubs are so slow it's critical that
3165 // we inline both the stack-locking fast-path and the inflated fast path.
3166 //
3167 // See also: cmpFastLock and cmpFastUnlock.
3168 //
3169 // What follows is a specialized inline transliteration of the code
3170 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3171 // another option would be to emit TrySlowEnter and TrySlowExit methods
3172 // at startup-time. These methods would accept arguments as
3173 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3174 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3175 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3176 // In practice, however, the # of lock sites is bounded and is usually small.
3177 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3178 // if the processor uses simple bimodal branch predictors keyed by EIP
3179 // Since the helper routines would be called from multiple synchronization
3180 // sites.
3181 //
3182 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3183 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3184 // to those specialized methods. That'd give us a mostly platform-independent
3185 // implementation that the JITs could optimize and inline at their pleasure.
3186 // Done correctly, the only time we'd need to cross to native could would be
3187 // to park() or unpark() threads. We'd also need a few more unsafe operators
3188 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3189 // (b) explicit barriers or fence operations.
3190 //
3191 // TODO:
3192 //
3193 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3194 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3195 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3196 // the lock operators would typically be faster than reifying Self.
3197 //
3198 // * Ideally I'd define the primitives as:
3199 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3200 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3201 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3202 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3203 // Furthermore the register assignments are overconstrained, possibly resulting in
3204 // sub-optimal code near the synchronization site.
3205 //
3206 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3207 // Alternately, use a better sp-proximity test.
3208 //
3209 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3210 // Either one is sufficient to uniquely identify a thread.
3211 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3212 //
3213 // * Intrinsify notify() and notifyAll() for the common cases where the
3214 // object is locked by the calling thread but the waitlist is empty.
3215 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3216 //
3217 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3218 // But beware of excessive branch density on AMD Opterons.
3219 //
3220 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3221 // or failure of the fast-path. If the fast-path fails then we pass
3222 // control to the slow-path, typically in C. In Fast_Lock and
3223 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3224 // will emit a conditional branch immediately after the node.
3225 // So we have branches to branches and lots of ICC.ZF games.
3226 // Instead, it might be better to have C2 pass a "FailureLabel"
3227 // into Fast_Lock and Fast_Unlock. In the case of success, control
3228 // will drop through the node. ICC.ZF is undefined at exit.
3229 // In the case of failure, the node will branch directly to the
3230 // FailureLabel
3233 // obj: object to lock
3234 // box: on-stack box address (displaced header location) - KILLED
3235 // rax,: tmp -- KILLED
3236 // scr: tmp -- KILLED
3237 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3239 Register objReg = as_Register($obj$$reg);
3240 Register boxReg = as_Register($box$$reg);
3241 Register tmpReg = as_Register($tmp$$reg);
3242 Register scrReg = as_Register($scr$$reg);
3244 // Ensure the register assignents are disjoint
3245 guarantee (objReg != boxReg, "") ;
3246 guarantee (objReg != tmpReg, "") ;
3247 guarantee (objReg != scrReg, "") ;
3248 guarantee (boxReg != tmpReg, "") ;
3249 guarantee (boxReg != scrReg, "") ;
3250 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3252 MacroAssembler masm(&cbuf);
3254 if (_counters != NULL) {
3255 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3256 }
3257 if (EmitSync & 1) {
3258 // set box->dhw = unused_mark (3)
3259 // Force all sync thru slow-path: slow_enter() and slow_exit()
3260 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3261 masm.cmpptr (rsp, (int32_t)0) ;
3262 } else
3263 if (EmitSync & 2) {
3264 Label DONE_LABEL ;
3265 if (UseBiasedLocking) {
3266 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3267 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3268 }
3270 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3271 masm.orptr (tmpReg, 0x1);
3272 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3273 if (os::is_MP()) { masm.lock(); }
3274 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3275 masm.jcc(Assembler::equal, DONE_LABEL);
3276 // Recursive locking
3277 masm.subptr(tmpReg, rsp);
3278 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3279 masm.movptr(Address(boxReg, 0), tmpReg);
3280 masm.bind(DONE_LABEL) ;
3281 } else {
3282 // Possible cases that we'll encounter in fast_lock
3283 // ------------------------------------------------
3284 // * Inflated
3285 // -- unlocked
3286 // -- Locked
3287 // = by self
3288 // = by other
3289 // * biased
3290 // -- by Self
3291 // -- by other
3292 // * neutral
3293 // * stack-locked
3294 // -- by self
3295 // = sp-proximity test hits
3296 // = sp-proximity test generates false-negative
3297 // -- by other
3298 //
3300 Label IsInflated, DONE_LABEL, PopDone ;
3302 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3303 // order to reduce the number of conditional branches in the most common cases.
3304 // Beware -- there's a subtle invariant that fetch of the markword
3305 // at [FETCH], below, will never observe a biased encoding (*101b).
3306 // If this invariant is not held we risk exclusion (safety) failure.
3307 if (UseBiasedLocking && !UseOptoBiasInlining) {
3308 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3309 }
3311 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3312 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3313 masm.jccb (Assembler::notZero, IsInflated) ;
3315 // Attempt stack-locking ...
3316 masm.orptr (tmpReg, 0x1);
3317 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3318 if (os::is_MP()) { masm.lock(); }
3319 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3320 if (_counters != NULL) {
3321 masm.cond_inc32(Assembler::equal,
3322 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3323 }
3324 masm.jccb (Assembler::equal, DONE_LABEL);
3326 // Recursive locking
3327 masm.subptr(tmpReg, rsp);
3328 masm.andptr(tmpReg, 0xFFFFF003 );
3329 masm.movptr(Address(boxReg, 0), tmpReg);
3330 if (_counters != NULL) {
3331 masm.cond_inc32(Assembler::equal,
3332 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3333 }
3334 masm.jmp (DONE_LABEL) ;
3336 masm.bind (IsInflated) ;
3338 // The object is inflated.
3339 //
3340 // TODO-FIXME: eliminate the ugly use of manifest constants:
3341 // Use markOopDesc::monitor_value instead of "2".
3342 // use markOop::unused_mark() instead of "3".
3343 // The tmpReg value is an objectMonitor reference ORed with
3344 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3345 // objectmonitor pointer by masking off the "2" bit or we can just
3346 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3347 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3348 //
3349 // I use the latter as it avoids AGI stalls.
3350 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3351 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3352 //
3353 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3355 // boxReg refers to the on-stack BasicLock in the current frame.
3356 // We'd like to write:
3357 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3358 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3359 // additional latency as we have another ST in the store buffer that must drain.
3361 if (EmitSync & 8192) {
3362 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3363 masm.get_thread (scrReg) ;
3364 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3365 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3366 if (os::is_MP()) { masm.lock(); }
3367 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3368 } else
3369 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3370 masm.movptr(scrReg, boxReg) ;
3371 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3373 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3374 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3375 // prefetchw [eax + Offset(_owner)-2]
3376 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3377 }
3379 if ((EmitSync & 64) == 0) {
3380 // Optimistic form: consider XORL tmpReg,tmpReg
3381 masm.movptr(tmpReg, NULL_WORD) ;
3382 } else {
3383 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3384 // Test-And-CAS instead of CAS
3385 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3386 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3387 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3388 }
3390 // Appears unlocked - try to swing _owner from null to non-null.
3391 // Ideally, I'd manifest "Self" with get_thread and then attempt
3392 // to CAS the register containing Self into m->Owner.
3393 // But we don't have enough registers, so instead we can either try to CAS
3394 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3395 // we later store "Self" into m->Owner. Transiently storing a stack address
3396 // (rsp or the address of the box) into m->owner is harmless.
3397 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3398 if (os::is_MP()) { masm.lock(); }
3399 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3400 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3401 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3402 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3403 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3404 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3406 // If the CAS fails we can either retry or pass control to the slow-path.
3407 // We use the latter tactic.
3408 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3409 // If the CAS was successful ...
3410 // Self has acquired the lock
3411 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3412 // Intentional fall-through into DONE_LABEL ...
3413 } else {
3414 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3415 masm.movptr(boxReg, tmpReg) ;
3417 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3418 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3419 // prefetchw [eax + Offset(_owner)-2]
3420 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3421 }
3423 if ((EmitSync & 64) == 0) {
3424 // Optimistic form
3425 masm.xorptr (tmpReg, tmpReg) ;
3426 } else {
3427 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3428 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3429 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3430 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3431 }
3433 // Appears unlocked - try to swing _owner from null to non-null.
3434 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3435 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3436 masm.get_thread (scrReg) ;
3437 if (os::is_MP()) { masm.lock(); }
3438 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3440 // If the CAS fails we can either retry or pass control to the slow-path.
3441 // We use the latter tactic.
3442 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3443 // If the CAS was successful ...
3444 // Self has acquired the lock
3445 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3446 // Intentional fall-through into DONE_LABEL ...
3447 }
3449 // DONE_LABEL is a hot target - we'd really like to place it at the
3450 // start of cache line by padding with NOPs.
3451 // See the AMD and Intel software optimization manuals for the
3452 // most efficient "long" NOP encodings.
3453 // Unfortunately none of our alignment mechanisms suffice.
3454 masm.bind(DONE_LABEL);
3456 // Avoid branch-to-branch on AMD processors
3457 // This appears to be superstition.
3458 if (EmitSync & 32) masm.nop() ;
3461 // At DONE_LABEL the icc ZFlag is set as follows ...
3462 // Fast_Unlock uses the same protocol.
3463 // ZFlag == 1 -> Success
3464 // ZFlag == 0 -> Failure - force control through the slow-path
3465 }
3466 %}
3468 // obj: object to unlock
3469 // box: box address (displaced header location), killed. Must be EAX.
3470 // rbx,: killed tmp; cannot be obj nor box.
3471 //
3472 // Some commentary on balanced locking:
3473 //
3474 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3475 // Methods that don't have provably balanced locking are forced to run in the
3476 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3477 // The interpreter provides two properties:
3478 // I1: At return-time the interpreter automatically and quietly unlocks any
3479 // objects acquired the current activation (frame). Recall that the
3480 // interpreter maintains an on-stack list of locks currently held by
3481 // a frame.
3482 // I2: If a method attempts to unlock an object that is not held by the
3483 // the frame the interpreter throws IMSX.
3484 //
3485 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3486 // B() doesn't have provably balanced locking so it runs in the interpreter.
3487 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3488 // is still locked by A().
3489 //
3490 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3491 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3492 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3493 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3495 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3497 Register objReg = as_Register($obj$$reg);
3498 Register boxReg = as_Register($box$$reg);
3499 Register tmpReg = as_Register($tmp$$reg);
3501 guarantee (objReg != boxReg, "") ;
3502 guarantee (objReg != tmpReg, "") ;
3503 guarantee (boxReg != tmpReg, "") ;
3504 guarantee (boxReg == as_Register(EAX_enc), "") ;
3505 MacroAssembler masm(&cbuf);
3507 if (EmitSync & 4) {
3508 // Disable - inhibit all inlining. Force control through the slow-path
3509 masm.cmpptr (rsp, 0) ;
3510 } else
3511 if (EmitSync & 8) {
3512 Label DONE_LABEL ;
3513 if (UseBiasedLocking) {
3514 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3515 }
3516 // classic stack-locking code ...
3517 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3518 masm.testptr(tmpReg, tmpReg) ;
3519 masm.jcc (Assembler::zero, DONE_LABEL) ;
3520 if (os::is_MP()) { masm.lock(); }
3521 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3522 masm.bind(DONE_LABEL);
3523 } else {
3524 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3526 // Critically, the biased locking test must have precedence over
3527 // and appear before the (box->dhw == 0) recursive stack-lock test.
3528 if (UseBiasedLocking && !UseOptoBiasInlining) {
3529 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3530 }
3532 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3533 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3534 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3536 masm.testptr(tmpReg, 0x02) ; // Inflated?
3537 masm.jccb (Assembler::zero, Stacked) ;
3539 masm.bind (Inflated) ;
3540 // It's inflated.
3541 // Despite our balanced locking property we still check that m->_owner == Self
3542 // as java routines or native JNI code called by this thread might
3543 // have released the lock.
3544 // Refer to the comments in synchronizer.cpp for how we might encode extra
3545 // state in _succ so we can avoid fetching EntryList|cxq.
3546 //
3547 // I'd like to add more cases in fast_lock() and fast_unlock() --
3548 // such as recursive enter and exit -- but we have to be wary of
3549 // I$ bloat, T$ effects and BP$ effects.
3550 //
3551 // If there's no contention try a 1-0 exit. That is, exit without
3552 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3553 // we detect and recover from the race that the 1-0 exit admits.
3554 //
3555 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3556 // before it STs null into _owner, releasing the lock. Updates
3557 // to data protected by the critical section must be visible before
3558 // we drop the lock (and thus before any other thread could acquire
3559 // the lock and observe the fields protected by the lock).
3560 // IA32's memory-model is SPO, so STs are ordered with respect to
3561 // each other and there's no need for an explicit barrier (fence).
3562 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3564 masm.get_thread (boxReg) ;
3565 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3566 // prefetchw [ebx + Offset(_owner)-2]
3567 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3568 }
3570 // Note that we could employ various encoding schemes to reduce
3571 // the number of loads below (currently 4) to just 2 or 3.
3572 // Refer to the comments in synchronizer.cpp.
3573 // In practice the chain of fetches doesn't seem to impact performance, however.
3574 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3575 // Attempt to reduce branch density - AMD's branch predictor.
3576 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3577 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3578 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3579 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3580 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3581 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3582 masm.jmpb (DONE_LABEL) ;
3583 } else {
3584 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3585 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3586 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3587 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3588 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3589 masm.jccb (Assembler::notZero, CheckSucc) ;
3590 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3591 masm.jmpb (DONE_LABEL) ;
3592 }
3594 // The Following code fragment (EmitSync & 65536) improves the performance of
3595 // contended applications and contended synchronization microbenchmarks.
3596 // Unfortunately the emission of the code - even though not executed - causes regressions
3597 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3598 // with an equal number of never-executed NOPs results in the same regression.
3599 // We leave it off by default.
3601 if ((EmitSync & 65536) != 0) {
3602 Label LSuccess, LGoSlowPath ;
3604 masm.bind (CheckSucc) ;
3606 // Optional pre-test ... it's safe to elide this
3607 if ((EmitSync & 16) == 0) {
3608 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3609 masm.jccb (Assembler::zero, LGoSlowPath) ;
3610 }
3612 // We have a classic Dekker-style idiom:
3613 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3614 // There are a number of ways to implement the barrier:
3615 // (1) lock:andl &m->_owner, 0
3616 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3617 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3618 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3619 // (2) If supported, an explicit MFENCE is appealing.
3620 // In older IA32 processors MFENCE is slower than lock:add or xchg
3621 // particularly if the write-buffer is full as might be the case if
3622 // if stores closely precede the fence or fence-equivalent instruction.
3623 // In more modern implementations MFENCE appears faster, however.
3624 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3625 // The $lines underlying the top-of-stack should be in M-state.
3626 // The locked add instruction is serializing, of course.
3627 // (4) Use xchg, which is serializing
3628 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3629 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3630 // The integer condition codes will tell us if succ was 0.
3631 // Since _succ and _owner should reside in the same $line and
3632 // we just stored into _owner, it's likely that the $line
3633 // remains in M-state for the lock:orl.
3634 //
3635 // We currently use (3), although it's likely that switching to (2)
3636 // is correct for the future.
3638 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3639 if (os::is_MP()) {
3640 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3641 masm.mfence();
3642 } else {
3643 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3644 }
3645 }
3646 // Ratify _succ remains non-null
3647 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3648 masm.jccb (Assembler::notZero, LSuccess) ;
3650 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3651 if (os::is_MP()) { masm.lock(); }
3652 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3653 masm.jccb (Assembler::notEqual, LSuccess) ;
3654 // Since we're low on registers we installed rsp as a placeholding in _owner.
3655 // Now install Self over rsp. This is safe as we're transitioning from
3656 // non-null to non=null
3657 masm.get_thread (boxReg) ;
3658 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3659 // Intentional fall-through into LGoSlowPath ...
3661 masm.bind (LGoSlowPath) ;
3662 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3663 masm.jmpb (DONE_LABEL) ;
3665 masm.bind (LSuccess) ;
3666 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3667 masm.jmpb (DONE_LABEL) ;
3668 }
3670 masm.bind (Stacked) ;
3671 // It's not inflated and it's not recursively stack-locked and it's not biased.
3672 // It must be stack-locked.
3673 // Try to reset the header to displaced header.
3674 // The "box" value on the stack is stable, so we can reload
3675 // and be assured we observe the same value as above.
3676 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3677 if (os::is_MP()) { masm.lock(); }
3678 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3679 // Intention fall-thru into DONE_LABEL
3682 // DONE_LABEL is a hot target - we'd really like to place it at the
3683 // start of cache line by padding with NOPs.
3684 // See the AMD and Intel software optimization manuals for the
3685 // most efficient "long" NOP encodings.
3686 // Unfortunately none of our alignment mechanisms suffice.
3687 if ((EmitSync & 65536) == 0) {
3688 masm.bind (CheckSucc) ;
3689 }
3690 masm.bind(DONE_LABEL);
3692 // Avoid branch to branch on AMD processors
3693 if (EmitSync & 32768) { masm.nop() ; }
3694 }
3695 %}
3697 enc_class enc_String_Compare() %{
3698 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3699 POP_LABEL, DONE_LABEL, CONT_LABEL,
3700 WHILE_HEAD_LABEL;
3701 MacroAssembler masm(&cbuf);
3703 // Get the first character position in both strings
3704 // [8] char array, [12] offset, [16] count
3705 int value_offset = java_lang_String::value_offset_in_bytes();
3706 int offset_offset = java_lang_String::offset_offset_in_bytes();
3707 int count_offset = java_lang_String::count_offset_in_bytes();
3708 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3710 masm.movptr(rax, Address(rsi, value_offset));
3711 masm.movl(rcx, Address(rsi, offset_offset));
3712 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3713 masm.movptr(rbx, Address(rdi, value_offset));
3714 masm.movl(rcx, Address(rdi, offset_offset));
3715 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3717 // Compute the minimum of the string lengths(rsi) and the
3718 // difference of the string lengths (stack)
3721 if (VM_Version::supports_cmov()) {
3722 masm.movl(rdi, Address(rdi, count_offset));
3723 masm.movl(rsi, Address(rsi, count_offset));
3724 masm.movl(rcx, rdi);
3725 masm.subl(rdi, rsi);
3726 masm.push(rdi);
3727 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3728 } else {
3729 masm.movl(rdi, Address(rdi, count_offset));
3730 masm.movl(rcx, Address(rsi, count_offset));
3731 masm.movl(rsi, rdi);
3732 masm.subl(rdi, rcx);
3733 masm.push(rdi);
3734 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL);
3735 masm.movl(rsi, rcx);
3736 // rsi holds min, rcx is unused
3737 }
3739 // Is the minimum length zero?
3740 masm.bind(ECX_GOOD_LABEL);
3741 masm.testl(rsi, rsi);
3742 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3744 // Load first characters
3745 masm.load_unsigned_short(rcx, Address(rbx, 0));
3746 masm.load_unsigned_short(rdi, Address(rax, 0));
3748 // Compare first characters
3749 masm.subl(rcx, rdi);
3750 masm.jcc(Assembler::notZero, POP_LABEL);
3751 masm.decrementl(rsi);
3752 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3754 {
3755 // Check after comparing first character to see if strings are equivalent
3756 Label LSkip2;
3757 // Check if the strings start at same location
3758 masm.cmpptr(rbx,rax);
3759 masm.jcc(Assembler::notEqual, LSkip2);
3761 // Check if the length difference is zero (from stack)
3762 masm.cmpl(Address(rsp, 0), 0x0);
3763 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3765 // Strings might not be equivalent
3766 masm.bind(LSkip2);
3767 }
3769 // Shift rax, and rbx, to the end of the arrays, negate min
3770 masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
3771 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
3772 masm.negl(rsi);
3774 // Compare the rest of the characters
3775 masm.bind(WHILE_HEAD_LABEL);
3776 masm.load_unsigned_short(rcx, Address(rbx, rsi, Address::times_2, 0));
3777 masm.load_unsigned_short(rdi, Address(rax, rsi, Address::times_2, 0));
3778 masm.subl(rcx, rdi);
3779 masm.jcc(Assembler::notZero, POP_LABEL);
3780 masm.incrementl(rsi);
3781 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3783 // Strings are equal up to min length. Return the length difference.
3784 masm.bind(LENGTH_DIFF_LABEL);
3785 masm.pop(rcx);
3786 masm.jmp(DONE_LABEL);
3788 // Discard the stored length difference
3789 masm.bind(POP_LABEL);
3790 masm.addptr(rsp, 4);
3792 // That's it
3793 masm.bind(DONE_LABEL);
3794 %}
3796 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result) %{
3797 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
3798 MacroAssembler masm(&cbuf);
3800 Register ary1Reg = as_Register($ary1$$reg);
3801 Register ary2Reg = as_Register($ary2$$reg);
3802 Register tmp1Reg = as_Register($tmp1$$reg);
3803 Register tmp2Reg = as_Register($tmp2$$reg);
3804 Register resultReg = as_Register($result$$reg);
3806 int length_offset = arrayOopDesc::length_offset_in_bytes();
3807 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3809 // Check the input args
3810 masm.cmpl(ary1Reg, ary2Reg);
3811 masm.jcc(Assembler::equal, TRUE_LABEL);
3812 masm.testl(ary1Reg, ary1Reg);
3813 masm.jcc(Assembler::zero, FALSE_LABEL);
3814 masm.testl(ary2Reg, ary2Reg);
3815 masm.jcc(Assembler::zero, FALSE_LABEL);
3817 // Check the lengths
3818 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
3819 masm.movl(resultReg, Address(ary2Reg, length_offset));
3820 masm.cmpl(tmp2Reg, resultReg);
3821 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3822 masm.testl(resultReg, resultReg);
3823 masm.jcc(Assembler::zero, TRUE_LABEL);
3825 // Get the number of 4 byte vectors to compare
3826 masm.shrl(resultReg, 1);
3828 // Check for odd-length arrays
3829 masm.andl(tmp2Reg, 1);
3830 masm.testl(tmp2Reg, tmp2Reg);
3831 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR);
3833 // Compare 2-byte "tail" at end of arrays
3834 masm.load_unsigned_short(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3835 masm.load_unsigned_short(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3836 masm.cmpl(tmp1Reg, tmp2Reg);
3837 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3838 masm.testl(resultReg, resultReg);
3839 masm.jcc(Assembler::zero, TRUE_LABEL);
3841 // Setup compare loop
3842 masm.bind(COMPARE_LOOP_HDR);
3843 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
3844 masm.leal(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3845 masm.leal(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3846 masm.negl(resultReg);
3848 // 4-byte-wide compare loop
3849 masm.bind(COMPARE_LOOP);
3850 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
3851 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
3852 masm.cmpl(ary1Reg, ary2Reg);
3853 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3854 masm.increment(resultReg);
3855 masm.jcc(Assembler::notZero, COMPARE_LOOP);
3857 masm.bind(TRUE_LABEL);
3858 masm.movl(resultReg, 1); // return true
3859 masm.jmp(DONE_LABEL);
3861 masm.bind(FALSE_LABEL);
3862 masm.xorl(resultReg, resultReg); // return false
3864 // That's it
3865 masm.bind(DONE_LABEL);
3866 %}
3868 enc_class enc_pop_rdx() %{
3869 emit_opcode(cbuf,0x5A);
3870 %}
3872 enc_class enc_rethrow() %{
3873 cbuf.set_inst_mark();
3874 emit_opcode(cbuf, 0xE9); // jmp entry
3875 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3876 runtime_call_Relocation::spec(), RELOC_IMM32 );
3877 %}
3880 // Convert a double to an int. Java semantics require we do complex
3881 // manglelations in the corner cases. So we set the rounding mode to
3882 // 'zero', store the darned double down as an int, and reset the
3883 // rounding mode to 'nearest'. The hardware throws an exception which
3884 // patches up the correct value directly to the stack.
3885 enc_class D2I_encoding( regD src ) %{
3886 // Flip to round-to-zero mode. We attempted to allow invalid-op
3887 // exceptions here, so that a NAN or other corner-case value will
3888 // thrown an exception (but normal values get converted at full speed).
3889 // However, I2C adapters and other float-stack manglers leave pending
3890 // invalid-op exceptions hanging. We would have to clear them before
3891 // enabling them and that is more expensive than just testing for the
3892 // invalid value Intel stores down in the corner cases.
3893 emit_opcode(cbuf,0xD9); // FLDCW trunc
3894 emit_opcode(cbuf,0x2D);
3895 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3896 // Allocate a word
3897 emit_opcode(cbuf,0x83); // SUB ESP,4
3898 emit_opcode(cbuf,0xEC);
3899 emit_d8(cbuf,0x04);
3900 // Encoding assumes a double has been pushed into FPR0.
3901 // Store down the double as an int, popping the FPU stack
3902 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3903 emit_opcode(cbuf,0x1C);
3904 emit_d8(cbuf,0x24);
3905 // Restore the rounding mode; mask the exception
3906 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3907 emit_opcode(cbuf,0x2D);
3908 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3909 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3910 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3912 // Load the converted int; adjust CPU stack
3913 emit_opcode(cbuf,0x58); // POP EAX
3914 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3915 emit_d32 (cbuf,0x80000000); // 0x80000000
3916 emit_opcode(cbuf,0x75); // JNE around_slow_call
3917 emit_d8 (cbuf,0x07); // Size of slow_call
3918 // Push src onto stack slow-path
3919 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3920 emit_d8 (cbuf,0xC0-1+$src$$reg );
3921 // CALL directly to the runtime
3922 cbuf.set_inst_mark();
3923 emit_opcode(cbuf,0xE8); // Call into runtime
3924 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3925 // Carry on here...
3926 %}
3928 enc_class D2L_encoding( regD src ) %{
3929 emit_opcode(cbuf,0xD9); // FLDCW trunc
3930 emit_opcode(cbuf,0x2D);
3931 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3932 // Allocate a word
3933 emit_opcode(cbuf,0x83); // SUB ESP,8
3934 emit_opcode(cbuf,0xEC);
3935 emit_d8(cbuf,0x08);
3936 // Encoding assumes a double has been pushed into FPR0.
3937 // Store down the double as a long, popping the FPU stack
3938 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3939 emit_opcode(cbuf,0x3C);
3940 emit_d8(cbuf,0x24);
3941 // Restore the rounding mode; mask the exception
3942 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3943 emit_opcode(cbuf,0x2D);
3944 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3945 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3946 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3948 // Load the converted int; adjust CPU stack
3949 emit_opcode(cbuf,0x58); // POP EAX
3950 emit_opcode(cbuf,0x5A); // POP EDX
3951 emit_opcode(cbuf,0x81); // CMP EDX,imm
3952 emit_d8 (cbuf,0xFA); // rdx
3953 emit_d32 (cbuf,0x80000000); // 0x80000000
3954 emit_opcode(cbuf,0x75); // JNE around_slow_call
3955 emit_d8 (cbuf,0x07+4); // Size of slow_call
3956 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3957 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3958 emit_opcode(cbuf,0x75); // JNE around_slow_call
3959 emit_d8 (cbuf,0x07); // Size of slow_call
3960 // Push src onto stack slow-path
3961 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3962 emit_d8 (cbuf,0xC0-1+$src$$reg );
3963 // CALL directly to the runtime
3964 cbuf.set_inst_mark();
3965 emit_opcode(cbuf,0xE8); // Call into runtime
3966 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3967 // Carry on here...
3968 %}
3970 enc_class X2L_encoding( regX src ) %{
3971 // Allocate a word
3972 emit_opcode(cbuf,0x83); // SUB ESP,8
3973 emit_opcode(cbuf,0xEC);
3974 emit_d8(cbuf,0x08);
3976 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3977 emit_opcode (cbuf, 0x0F );
3978 emit_opcode (cbuf, 0x11 );
3979 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3981 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3982 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3984 emit_opcode(cbuf,0xD9); // FLDCW trunc
3985 emit_opcode(cbuf,0x2D);
3986 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3988 // Encoding assumes a double has been pushed into FPR0.
3989 // Store down the double as a long, popping the FPU stack
3990 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3991 emit_opcode(cbuf,0x3C);
3992 emit_d8(cbuf,0x24);
3994 // Restore the rounding mode; mask the exception
3995 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3996 emit_opcode(cbuf,0x2D);
3997 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3998 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3999 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4001 // Load the converted int; adjust CPU stack
4002 emit_opcode(cbuf,0x58); // POP EAX
4004 emit_opcode(cbuf,0x5A); // POP EDX
4006 emit_opcode(cbuf,0x81); // CMP EDX,imm
4007 emit_d8 (cbuf,0xFA); // rdx
4008 emit_d32 (cbuf,0x80000000);// 0x80000000
4010 emit_opcode(cbuf,0x75); // JNE around_slow_call
4011 emit_d8 (cbuf,0x13+4); // Size of slow_call
4013 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4014 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4016 emit_opcode(cbuf,0x75); // JNE around_slow_call
4017 emit_d8 (cbuf,0x13); // Size of slow_call
4019 // Allocate a word
4020 emit_opcode(cbuf,0x83); // SUB ESP,4
4021 emit_opcode(cbuf,0xEC);
4022 emit_d8(cbuf,0x04);
4024 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4025 emit_opcode (cbuf, 0x0F );
4026 emit_opcode (cbuf, 0x11 );
4027 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4029 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4030 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4032 emit_opcode(cbuf,0x83); // ADD ESP,4
4033 emit_opcode(cbuf,0xC4);
4034 emit_d8(cbuf,0x04);
4036 // CALL directly to the runtime
4037 cbuf.set_inst_mark();
4038 emit_opcode(cbuf,0xE8); // Call into runtime
4039 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4040 // Carry on here...
4041 %}
4043 enc_class XD2L_encoding( regXD src ) %{
4044 // Allocate a word
4045 emit_opcode(cbuf,0x83); // SUB ESP,8
4046 emit_opcode(cbuf,0xEC);
4047 emit_d8(cbuf,0x08);
4049 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4050 emit_opcode (cbuf, 0x0F );
4051 emit_opcode (cbuf, 0x11 );
4052 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4054 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4055 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4057 emit_opcode(cbuf,0xD9); // FLDCW trunc
4058 emit_opcode(cbuf,0x2D);
4059 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4061 // Encoding assumes a double has been pushed into FPR0.
4062 // Store down the double as a long, popping the FPU stack
4063 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4064 emit_opcode(cbuf,0x3C);
4065 emit_d8(cbuf,0x24);
4067 // Restore the rounding mode; mask the exception
4068 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4069 emit_opcode(cbuf,0x2D);
4070 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4071 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4072 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4074 // Load the converted int; adjust CPU stack
4075 emit_opcode(cbuf,0x58); // POP EAX
4077 emit_opcode(cbuf,0x5A); // POP EDX
4079 emit_opcode(cbuf,0x81); // CMP EDX,imm
4080 emit_d8 (cbuf,0xFA); // rdx
4081 emit_d32 (cbuf,0x80000000); // 0x80000000
4083 emit_opcode(cbuf,0x75); // JNE around_slow_call
4084 emit_d8 (cbuf,0x13+4); // Size of slow_call
4086 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4087 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4089 emit_opcode(cbuf,0x75); // JNE around_slow_call
4090 emit_d8 (cbuf,0x13); // Size of slow_call
4092 // Push src onto stack slow-path
4093 // Allocate a word
4094 emit_opcode(cbuf,0x83); // SUB ESP,8
4095 emit_opcode(cbuf,0xEC);
4096 emit_d8(cbuf,0x08);
4098 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4099 emit_opcode (cbuf, 0x0F );
4100 emit_opcode (cbuf, 0x11 );
4101 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4103 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4104 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4106 emit_opcode(cbuf,0x83); // ADD ESP,8
4107 emit_opcode(cbuf,0xC4);
4108 emit_d8(cbuf,0x08);
4110 // CALL directly to the runtime
4111 cbuf.set_inst_mark();
4112 emit_opcode(cbuf,0xE8); // Call into runtime
4113 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4114 // Carry on here...
4115 %}
4117 enc_class D2X_encoding( regX dst, regD src ) %{
4118 // Allocate a word
4119 emit_opcode(cbuf,0x83); // SUB ESP,4
4120 emit_opcode(cbuf,0xEC);
4121 emit_d8(cbuf,0x04);
4122 int pop = 0x02;
4123 if ($src$$reg != FPR1L_enc) {
4124 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4125 emit_d8( cbuf, 0xC0-1+$src$$reg );
4126 pop = 0x03;
4127 }
4128 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4130 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4131 emit_opcode (cbuf, 0x0F );
4132 emit_opcode (cbuf, 0x10 );
4133 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4135 emit_opcode(cbuf,0x83); // ADD ESP,4
4136 emit_opcode(cbuf,0xC4);
4137 emit_d8(cbuf,0x04);
4138 // Carry on here...
4139 %}
4141 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4142 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4144 // Compare the result to see if we need to go to the slow path
4145 emit_opcode(cbuf,0x81); // CMP dst,imm
4146 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4147 emit_d32 (cbuf,0x80000000); // 0x80000000
4149 emit_opcode(cbuf,0x75); // JNE around_slow_call
4150 emit_d8 (cbuf,0x13); // Size of slow_call
4151 // Store xmm to a temp memory
4152 // location and push it onto stack.
4154 emit_opcode(cbuf,0x83); // SUB ESP,4
4155 emit_opcode(cbuf,0xEC);
4156 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4158 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4159 emit_opcode (cbuf, 0x0F );
4160 emit_opcode (cbuf, 0x11 );
4161 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4163 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4164 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4166 emit_opcode(cbuf,0x83); // ADD ESP,4
4167 emit_opcode(cbuf,0xC4);
4168 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4170 // CALL directly to the runtime
4171 cbuf.set_inst_mark();
4172 emit_opcode(cbuf,0xE8); // Call into runtime
4173 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4175 // Carry on here...
4176 %}
4178 enc_class X2D_encoding( regD dst, regX src ) %{
4179 // Allocate a word
4180 emit_opcode(cbuf,0x83); // SUB ESP,4
4181 emit_opcode(cbuf,0xEC);
4182 emit_d8(cbuf,0x04);
4184 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4185 emit_opcode (cbuf, 0x0F );
4186 emit_opcode (cbuf, 0x11 );
4187 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4189 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4190 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4192 emit_opcode(cbuf,0x83); // ADD ESP,4
4193 emit_opcode(cbuf,0xC4);
4194 emit_d8(cbuf,0x04);
4196 // Carry on here...
4197 %}
4199 enc_class AbsXF_encoding(regX dst) %{
4200 address signmask_address=(address)float_signmask_pool;
4201 // andpd:\tANDPS $dst,[signconst]
4202 emit_opcode(cbuf, 0x0F);
4203 emit_opcode(cbuf, 0x54);
4204 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4205 emit_d32(cbuf, (int)signmask_address);
4206 %}
4208 enc_class AbsXD_encoding(regXD dst) %{
4209 address signmask_address=(address)double_signmask_pool;
4210 // andpd:\tANDPD $dst,[signconst]
4211 emit_opcode(cbuf, 0x66);
4212 emit_opcode(cbuf, 0x0F);
4213 emit_opcode(cbuf, 0x54);
4214 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4215 emit_d32(cbuf, (int)signmask_address);
4216 %}
4218 enc_class NegXF_encoding(regX dst) %{
4219 address signmask_address=(address)float_signflip_pool;
4220 // andpd:\tXORPS $dst,[signconst]
4221 emit_opcode(cbuf, 0x0F);
4222 emit_opcode(cbuf, 0x57);
4223 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4224 emit_d32(cbuf, (int)signmask_address);
4225 %}
4227 enc_class NegXD_encoding(regXD dst) %{
4228 address signmask_address=(address)double_signflip_pool;
4229 // andpd:\tXORPD $dst,[signconst]
4230 emit_opcode(cbuf, 0x66);
4231 emit_opcode(cbuf, 0x0F);
4232 emit_opcode(cbuf, 0x57);
4233 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4234 emit_d32(cbuf, (int)signmask_address);
4235 %}
4237 enc_class FMul_ST_reg( eRegF src1 ) %{
4238 // Operand was loaded from memory into fp ST (stack top)
4239 // FMUL ST,$src /* D8 C8+i */
4240 emit_opcode(cbuf, 0xD8);
4241 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4242 %}
4244 enc_class FAdd_ST_reg( eRegF src2 ) %{
4245 // FADDP ST,src2 /* D8 C0+i */
4246 emit_opcode(cbuf, 0xD8);
4247 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4248 //could use FADDP src2,fpST /* DE C0+i */
4249 %}
4251 enc_class FAddP_reg_ST( eRegF src2 ) %{
4252 // FADDP src2,ST /* DE C0+i */
4253 emit_opcode(cbuf, 0xDE);
4254 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4255 %}
4257 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4258 // Operand has been loaded into fp ST (stack top)
4259 // FSUB ST,$src1
4260 emit_opcode(cbuf, 0xD8);
4261 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4263 // FDIV
4264 emit_opcode(cbuf, 0xD8);
4265 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4266 %}
4268 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4269 // Operand was loaded from memory into fp ST (stack top)
4270 // FADD ST,$src /* D8 C0+i */
4271 emit_opcode(cbuf, 0xD8);
4272 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4274 // FMUL ST,src2 /* D8 C*+i */
4275 emit_opcode(cbuf, 0xD8);
4276 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4277 %}
4280 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4281 // Operand was loaded from memory into fp ST (stack top)
4282 // FADD ST,$src /* D8 C0+i */
4283 emit_opcode(cbuf, 0xD8);
4284 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4286 // FMULP src2,ST /* DE C8+i */
4287 emit_opcode(cbuf, 0xDE);
4288 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4289 %}
4291 enc_class enc_membar_acquire %{
4292 // Doug Lea believes this is not needed with current Sparcs and TSO.
4293 // MacroAssembler masm(&cbuf);
4294 // masm.membar();
4295 %}
4297 enc_class enc_membar_release %{
4298 // Doug Lea believes this is not needed with current Sparcs and TSO.
4299 // MacroAssembler masm(&cbuf);
4300 // masm.membar();
4301 %}
4303 enc_class enc_membar_volatile %{
4304 MacroAssembler masm(&cbuf);
4305 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
4306 Assembler::StoreStore));
4307 %}
4309 // Atomically load the volatile long
4310 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4311 emit_opcode(cbuf,0xDF);
4312 int rm_byte_opcode = 0x05;
4313 int base = $mem$$base;
4314 int index = $mem$$index;
4315 int scale = $mem$$scale;
4316 int displace = $mem$$disp;
4317 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4318 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4319 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4320 %}
4322 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4323 { // Atomic long load
4324 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4325 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4326 emit_opcode(cbuf,0x0F);
4327 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4328 int base = $mem$$base;
4329 int index = $mem$$index;
4330 int scale = $mem$$scale;
4331 int displace = $mem$$disp;
4332 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4333 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4334 }
4335 { // MOVSD $dst,$tmp ! atomic long store
4336 emit_opcode(cbuf,0xF2);
4337 emit_opcode(cbuf,0x0F);
4338 emit_opcode(cbuf,0x11);
4339 int base = $dst$$base;
4340 int index = $dst$$index;
4341 int scale = $dst$$scale;
4342 int displace = $dst$$disp;
4343 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4344 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4345 }
4346 %}
4348 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4349 { // Atomic long load
4350 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4351 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4352 emit_opcode(cbuf,0x0F);
4353 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4354 int base = $mem$$base;
4355 int index = $mem$$index;
4356 int scale = $mem$$scale;
4357 int displace = $mem$$disp;
4358 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4359 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4360 }
4361 { // MOVD $dst.lo,$tmp
4362 emit_opcode(cbuf,0x66);
4363 emit_opcode(cbuf,0x0F);
4364 emit_opcode(cbuf,0x7E);
4365 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4366 }
4367 { // PSRLQ $tmp,32
4368 emit_opcode(cbuf,0x66);
4369 emit_opcode(cbuf,0x0F);
4370 emit_opcode(cbuf,0x73);
4371 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4372 emit_d8(cbuf, 0x20);
4373 }
4374 { // MOVD $dst.hi,$tmp
4375 emit_opcode(cbuf,0x66);
4376 emit_opcode(cbuf,0x0F);
4377 emit_opcode(cbuf,0x7E);
4378 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4379 }
4380 %}
4382 // Volatile Store Long. Must be atomic, so move it into
4383 // the FP TOS and then do a 64-bit FIST. Has to probe the
4384 // target address before the store (for null-ptr checks)
4385 // so the memory operand is used twice in the encoding.
4386 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4387 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4388 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4389 emit_opcode(cbuf,0xDF);
4390 int rm_byte_opcode = 0x07;
4391 int base = $mem$$base;
4392 int index = $mem$$index;
4393 int scale = $mem$$scale;
4394 int displace = $mem$$disp;
4395 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4396 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4397 %}
4399 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4400 { // Atomic long load
4401 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4402 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4403 emit_opcode(cbuf,0x0F);
4404 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4405 int base = $src$$base;
4406 int index = $src$$index;
4407 int scale = $src$$scale;
4408 int displace = $src$$disp;
4409 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4410 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4411 }
4412 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4413 { // MOVSD $mem,$tmp ! atomic long store
4414 emit_opcode(cbuf,0xF2);
4415 emit_opcode(cbuf,0x0F);
4416 emit_opcode(cbuf,0x11);
4417 int base = $mem$$base;
4418 int index = $mem$$index;
4419 int scale = $mem$$scale;
4420 int displace = $mem$$disp;
4421 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4422 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4423 }
4424 %}
4426 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4427 { // MOVD $tmp,$src.lo
4428 emit_opcode(cbuf,0x66);
4429 emit_opcode(cbuf,0x0F);
4430 emit_opcode(cbuf,0x6E);
4431 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4432 }
4433 { // MOVD $tmp2,$src.hi
4434 emit_opcode(cbuf,0x66);
4435 emit_opcode(cbuf,0x0F);
4436 emit_opcode(cbuf,0x6E);
4437 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4438 }
4439 { // PUNPCKLDQ $tmp,$tmp2
4440 emit_opcode(cbuf,0x66);
4441 emit_opcode(cbuf,0x0F);
4442 emit_opcode(cbuf,0x62);
4443 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4444 }
4445 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4446 { // MOVSD $mem,$tmp ! atomic long store
4447 emit_opcode(cbuf,0xF2);
4448 emit_opcode(cbuf,0x0F);
4449 emit_opcode(cbuf,0x11);
4450 int base = $mem$$base;
4451 int index = $mem$$index;
4452 int scale = $mem$$scale;
4453 int displace = $mem$$disp;
4454 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4455 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4456 }
4457 %}
4459 // Safepoint Poll. This polls the safepoint page, and causes an
4460 // exception if it is not readable. Unfortunately, it kills the condition code
4461 // in the process
4462 // We current use TESTL [spp],EDI
4463 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4465 enc_class Safepoint_Poll() %{
4466 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4467 emit_opcode(cbuf,0x85);
4468 emit_rm (cbuf, 0x0, 0x7, 0x5);
4469 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4470 %}
4471 %}
4474 //----------FRAME--------------------------------------------------------------
4475 // Definition of frame structure and management information.
4476 //
4477 // S T A C K L A Y O U T Allocators stack-slot number
4478 // | (to get allocators register number
4479 // G Owned by | | v add OptoReg::stack0())
4480 // r CALLER | |
4481 // o | +--------+ pad to even-align allocators stack-slot
4482 // w V | pad0 | numbers; owned by CALLER
4483 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4484 // h ^ | in | 5
4485 // | | args | 4 Holes in incoming args owned by SELF
4486 // | | | | 3
4487 // | | +--------+
4488 // V | | old out| Empty on Intel, window on Sparc
4489 // | old |preserve| Must be even aligned.
4490 // | SP-+--------+----> Matcher::_old_SP, even aligned
4491 // | | in | 3 area for Intel ret address
4492 // Owned by |preserve| Empty on Sparc.
4493 // SELF +--------+
4494 // | | pad2 | 2 pad to align old SP
4495 // | +--------+ 1
4496 // | | locks | 0
4497 // | +--------+----> OptoReg::stack0(), even aligned
4498 // | | pad1 | 11 pad to align new SP
4499 // | +--------+
4500 // | | | 10
4501 // | | spills | 9 spills
4502 // V | | 8 (pad0 slot for callee)
4503 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4504 // ^ | out | 7
4505 // | | args | 6 Holes in outgoing args owned by CALLEE
4506 // Owned by +--------+
4507 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4508 // | new |preserve| Must be even-aligned.
4509 // | SP-+--------+----> Matcher::_new_SP, even aligned
4510 // | | |
4511 //
4512 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4513 // known from SELF's arguments and the Java calling convention.
4514 // Region 6-7 is determined per call site.
4515 // Note 2: If the calling convention leaves holes in the incoming argument
4516 // area, those holes are owned by SELF. Holes in the outgoing area
4517 // are owned by the CALLEE. Holes should not be nessecary in the
4518 // incoming area, as the Java calling convention is completely under
4519 // the control of the AD file. Doubles can be sorted and packed to
4520 // avoid holes. Holes in the outgoing arguments may be nessecary for
4521 // varargs C calling conventions.
4522 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4523 // even aligned with pad0 as needed.
4524 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4525 // region 6-11 is even aligned; it may be padded out more so that
4526 // the region from SP to FP meets the minimum stack alignment.
4528 frame %{
4529 // What direction does stack grow in (assumed to be same for C & Java)
4530 stack_direction(TOWARDS_LOW);
4532 // These three registers define part of the calling convention
4533 // between compiled code and the interpreter.
4534 inline_cache_reg(EAX); // Inline Cache Register
4535 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4537 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4538 cisc_spilling_operand_name(indOffset32);
4540 // Number of stack slots consumed by locking an object
4541 sync_stack_slots(1);
4543 // Compiled code's Frame Pointer
4544 frame_pointer(ESP);
4545 // Interpreter stores its frame pointer in a register which is
4546 // stored to the stack by I2CAdaptors.
4547 // I2CAdaptors convert from interpreted java to compiled java.
4548 interpreter_frame_pointer(EBP);
4550 // Stack alignment requirement
4551 // Alignment size in bytes (128-bit -> 16 bytes)
4552 stack_alignment(StackAlignmentInBytes);
4554 // Number of stack slots between incoming argument block and the start of
4555 // a new frame. The PROLOG must add this many slots to the stack. The
4556 // EPILOG must remove this many slots. Intel needs one slot for
4557 // return address and one for rbp, (must save rbp)
4558 in_preserve_stack_slots(2+VerifyStackAtCalls);
4560 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4561 // for calls to C. Supports the var-args backing area for register parms.
4562 varargs_C_out_slots_killed(0);
4564 // The after-PROLOG location of the return address. Location of
4565 // return address specifies a type (REG or STACK) and a number
4566 // representing the register number (i.e. - use a register name) or
4567 // stack slot.
4568 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4569 // Otherwise, it is above the locks and verification slot and alignment word
4570 return_addr(STACK - 1 +
4571 round_to(1+VerifyStackAtCalls+
4572 Compile::current()->fixed_slots(),
4573 (StackAlignmentInBytes/wordSize)));
4575 // Body of function which returns an integer array locating
4576 // arguments either in registers or in stack slots. Passed an array
4577 // of ideal registers called "sig" and a "length" count. Stack-slot
4578 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4579 // arguments for a CALLEE. Incoming stack arguments are
4580 // automatically biased by the preserve_stack_slots field above.
4581 calling_convention %{
4582 // No difference between ingoing/outgoing just pass false
4583 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4584 %}
4587 // Body of function which returns an integer array locating
4588 // arguments either in registers or in stack slots. Passed an array
4589 // of ideal registers called "sig" and a "length" count. Stack-slot
4590 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4591 // arguments for a CALLEE. Incoming stack arguments are
4592 // automatically biased by the preserve_stack_slots field above.
4593 c_calling_convention %{
4594 // This is obviously always outgoing
4595 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4596 %}
4598 // Location of C & interpreter return values
4599 c_return_value %{
4600 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4601 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4602 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4604 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4605 // that C functions return float and double results in XMM0.
4606 if( ideal_reg == Op_RegD && UseSSE>=2 )
4607 return OptoRegPair(XMM0b_num,XMM0a_num);
4608 if( ideal_reg == Op_RegF && UseSSE>=2 )
4609 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4611 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4612 %}
4614 // Location of return values
4615 return_value %{
4616 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4617 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4618 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4619 if( ideal_reg == Op_RegD && UseSSE>=2 )
4620 return OptoRegPair(XMM0b_num,XMM0a_num);
4621 if( ideal_reg == Op_RegF && UseSSE>=1 )
4622 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4623 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4624 %}
4626 %}
4628 //----------ATTRIBUTES---------------------------------------------------------
4629 //----------Operand Attributes-------------------------------------------------
4630 op_attrib op_cost(0); // Required cost attribute
4632 //----------Instruction Attributes---------------------------------------------
4633 ins_attrib ins_cost(100); // Required cost attribute
4634 ins_attrib ins_size(8); // Required size attribute (in bits)
4635 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4636 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4637 // non-matching short branch variant of some
4638 // long branch?
4639 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4640 // specifies the alignment that some part of the instruction (not
4641 // necessarily the start) requires. If > 1, a compute_padding()
4642 // function must be provided for the instruction
4644 //----------OPERANDS-----------------------------------------------------------
4645 // Operand definitions must precede instruction definitions for correct parsing
4646 // in the ADLC because operands constitute user defined types which are used in
4647 // instruction definitions.
4649 //----------Simple Operands----------------------------------------------------
4650 // Immediate Operands
4651 // Integer Immediate
4652 operand immI() %{
4653 match(ConI);
4655 op_cost(10);
4656 format %{ %}
4657 interface(CONST_INTER);
4658 %}
4660 // Constant for test vs zero
4661 operand immI0() %{
4662 predicate(n->get_int() == 0);
4663 match(ConI);
4665 op_cost(0);
4666 format %{ %}
4667 interface(CONST_INTER);
4668 %}
4670 // Constant for increment
4671 operand immI1() %{
4672 predicate(n->get_int() == 1);
4673 match(ConI);
4675 op_cost(0);
4676 format %{ %}
4677 interface(CONST_INTER);
4678 %}
4680 // Constant for decrement
4681 operand immI_M1() %{
4682 predicate(n->get_int() == -1);
4683 match(ConI);
4685 op_cost(0);
4686 format %{ %}
4687 interface(CONST_INTER);
4688 %}
4690 // Valid scale values for addressing modes
4691 operand immI2() %{
4692 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4693 match(ConI);
4695 format %{ %}
4696 interface(CONST_INTER);
4697 %}
4699 operand immI8() %{
4700 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4701 match(ConI);
4703 op_cost(5);
4704 format %{ %}
4705 interface(CONST_INTER);
4706 %}
4708 operand immI16() %{
4709 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4710 match(ConI);
4712 op_cost(10);
4713 format %{ %}
4714 interface(CONST_INTER);
4715 %}
4717 // Constant for long shifts
4718 operand immI_32() %{
4719 predicate( n->get_int() == 32 );
4720 match(ConI);
4722 op_cost(0);
4723 format %{ %}
4724 interface(CONST_INTER);
4725 %}
4727 operand immI_1_31() %{
4728 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4729 match(ConI);
4731 op_cost(0);
4732 format %{ %}
4733 interface(CONST_INTER);
4734 %}
4736 operand immI_32_63() %{
4737 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4738 match(ConI);
4739 op_cost(0);
4741 format %{ %}
4742 interface(CONST_INTER);
4743 %}
4745 operand immI_1() %{
4746 predicate( n->get_int() == 1 );
4747 match(ConI);
4749 op_cost(0);
4750 format %{ %}
4751 interface(CONST_INTER);
4752 %}
4754 operand immI_2() %{
4755 predicate( n->get_int() == 2 );
4756 match(ConI);
4758 op_cost(0);
4759 format %{ %}
4760 interface(CONST_INTER);
4761 %}
4763 operand immI_3() %{
4764 predicate( n->get_int() == 3 );
4765 match(ConI);
4767 op_cost(0);
4768 format %{ %}
4769 interface(CONST_INTER);
4770 %}
4772 // Pointer Immediate
4773 operand immP() %{
4774 match(ConP);
4776 op_cost(10);
4777 format %{ %}
4778 interface(CONST_INTER);
4779 %}
4781 // NULL Pointer Immediate
4782 operand immP0() %{
4783 predicate( n->get_ptr() == 0 );
4784 match(ConP);
4785 op_cost(0);
4787 format %{ %}
4788 interface(CONST_INTER);
4789 %}
4791 // Long Immediate
4792 operand immL() %{
4793 match(ConL);
4795 op_cost(20);
4796 format %{ %}
4797 interface(CONST_INTER);
4798 %}
4800 // Long Immediate zero
4801 operand immL0() %{
4802 predicate( n->get_long() == 0L );
4803 match(ConL);
4804 op_cost(0);
4806 format %{ %}
4807 interface(CONST_INTER);
4808 %}
4810 // Long Immediate zero
4811 operand immL_M1() %{
4812 predicate( n->get_long() == -1L );
4813 match(ConL);
4814 op_cost(0);
4816 format %{ %}
4817 interface(CONST_INTER);
4818 %}
4820 // Long immediate from 0 to 127.
4821 // Used for a shorter form of long mul by 10.
4822 operand immL_127() %{
4823 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4824 match(ConL);
4825 op_cost(0);
4827 format %{ %}
4828 interface(CONST_INTER);
4829 %}
4831 // Long Immediate: low 32-bit mask
4832 operand immL_32bits() %{
4833 predicate(n->get_long() == 0xFFFFFFFFL);
4834 match(ConL);
4835 op_cost(0);
4837 format %{ %}
4838 interface(CONST_INTER);
4839 %}
4841 // Long Immediate: low 32-bit mask
4842 operand immL32() %{
4843 predicate(n->get_long() == (int)(n->get_long()));
4844 match(ConL);
4845 op_cost(20);
4847 format %{ %}
4848 interface(CONST_INTER);
4849 %}
4851 //Double Immediate zero
4852 operand immD0() %{
4853 // Do additional (and counter-intuitive) test against NaN to work around VC++
4854 // bug that generates code such that NaNs compare equal to 0.0
4855 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4856 match(ConD);
4858 op_cost(5);
4859 format %{ %}
4860 interface(CONST_INTER);
4861 %}
4863 // Double Immediate
4864 operand immD1() %{
4865 predicate( UseSSE<=1 && n->getd() == 1.0 );
4866 match(ConD);
4868 op_cost(5);
4869 format %{ %}
4870 interface(CONST_INTER);
4871 %}
4873 // Double Immediate
4874 operand immD() %{
4875 predicate(UseSSE<=1);
4876 match(ConD);
4878 op_cost(5);
4879 format %{ %}
4880 interface(CONST_INTER);
4881 %}
4883 operand immXD() %{
4884 predicate(UseSSE>=2);
4885 match(ConD);
4887 op_cost(5);
4888 format %{ %}
4889 interface(CONST_INTER);
4890 %}
4892 // Double Immediate zero
4893 operand immXD0() %{
4894 // Do additional (and counter-intuitive) test against NaN to work around VC++
4895 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4896 // compare equal to -0.0.
4897 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4898 match(ConD);
4900 format %{ %}
4901 interface(CONST_INTER);
4902 %}
4904 // Float Immediate zero
4905 operand immF0() %{
4906 predicate( UseSSE == 0 && n->getf() == 0.0 );
4907 match(ConF);
4909 op_cost(5);
4910 format %{ %}
4911 interface(CONST_INTER);
4912 %}
4914 // Float Immediate
4915 operand immF() %{
4916 predicate( UseSSE == 0 );
4917 match(ConF);
4919 op_cost(5);
4920 format %{ %}
4921 interface(CONST_INTER);
4922 %}
4924 // Float Immediate
4925 operand immXF() %{
4926 predicate(UseSSE >= 1);
4927 match(ConF);
4929 op_cost(5);
4930 format %{ %}
4931 interface(CONST_INTER);
4932 %}
4934 // Float Immediate zero. Zero and not -0.0
4935 operand immXF0() %{
4936 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4937 match(ConF);
4939 op_cost(5);
4940 format %{ %}
4941 interface(CONST_INTER);
4942 %}
4944 // Immediates for special shifts (sign extend)
4946 // Constants for increment
4947 operand immI_16() %{
4948 predicate( n->get_int() == 16 );
4949 match(ConI);
4951 format %{ %}
4952 interface(CONST_INTER);
4953 %}
4955 operand immI_24() %{
4956 predicate( n->get_int() == 24 );
4957 match(ConI);
4959 format %{ %}
4960 interface(CONST_INTER);
4961 %}
4963 // Constant for byte-wide masking
4964 operand immI_255() %{
4965 predicate( n->get_int() == 255 );
4966 match(ConI);
4968 format %{ %}
4969 interface(CONST_INTER);
4970 %}
4972 // Register Operands
4973 // Integer Register
4974 operand eRegI() %{
4975 constraint(ALLOC_IN_RC(e_reg));
4976 match(RegI);
4977 match(xRegI);
4978 match(eAXRegI);
4979 match(eBXRegI);
4980 match(eCXRegI);
4981 match(eDXRegI);
4982 match(eDIRegI);
4983 match(eSIRegI);
4985 format %{ %}
4986 interface(REG_INTER);
4987 %}
4989 // Subset of Integer Register
4990 operand xRegI(eRegI reg) %{
4991 constraint(ALLOC_IN_RC(x_reg));
4992 match(reg);
4993 match(eAXRegI);
4994 match(eBXRegI);
4995 match(eCXRegI);
4996 match(eDXRegI);
4998 format %{ %}
4999 interface(REG_INTER);
5000 %}
5002 // Special Registers
5003 operand eAXRegI(xRegI reg) %{
5004 constraint(ALLOC_IN_RC(eax_reg));
5005 match(reg);
5006 match(eRegI);
5008 format %{ "EAX" %}
5009 interface(REG_INTER);
5010 %}
5012 // Special Registers
5013 operand eBXRegI(xRegI reg) %{
5014 constraint(ALLOC_IN_RC(ebx_reg));
5015 match(reg);
5016 match(eRegI);
5018 format %{ "EBX" %}
5019 interface(REG_INTER);
5020 %}
5022 operand eCXRegI(xRegI reg) %{
5023 constraint(ALLOC_IN_RC(ecx_reg));
5024 match(reg);
5025 match(eRegI);
5027 format %{ "ECX" %}
5028 interface(REG_INTER);
5029 %}
5031 operand eDXRegI(xRegI reg) %{
5032 constraint(ALLOC_IN_RC(edx_reg));
5033 match(reg);
5034 match(eRegI);
5036 format %{ "EDX" %}
5037 interface(REG_INTER);
5038 %}
5040 operand eDIRegI(xRegI reg) %{
5041 constraint(ALLOC_IN_RC(edi_reg));
5042 match(reg);
5043 match(eRegI);
5045 format %{ "EDI" %}
5046 interface(REG_INTER);
5047 %}
5049 operand naxRegI() %{
5050 constraint(ALLOC_IN_RC(nax_reg));
5051 match(RegI);
5052 match(eCXRegI);
5053 match(eDXRegI);
5054 match(eSIRegI);
5055 match(eDIRegI);
5057 format %{ %}
5058 interface(REG_INTER);
5059 %}
5061 operand nadxRegI() %{
5062 constraint(ALLOC_IN_RC(nadx_reg));
5063 match(RegI);
5064 match(eBXRegI);
5065 match(eCXRegI);
5066 match(eSIRegI);
5067 match(eDIRegI);
5069 format %{ %}
5070 interface(REG_INTER);
5071 %}
5073 operand ncxRegI() %{
5074 constraint(ALLOC_IN_RC(ncx_reg));
5075 match(RegI);
5076 match(eAXRegI);
5077 match(eDXRegI);
5078 match(eSIRegI);
5079 match(eDIRegI);
5081 format %{ %}
5082 interface(REG_INTER);
5083 %}
5085 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5086 // //
5087 operand eSIRegI(xRegI reg) %{
5088 constraint(ALLOC_IN_RC(esi_reg));
5089 match(reg);
5090 match(eRegI);
5092 format %{ "ESI" %}
5093 interface(REG_INTER);
5094 %}
5096 // Pointer Register
5097 operand anyRegP() %{
5098 constraint(ALLOC_IN_RC(any_reg));
5099 match(RegP);
5100 match(eAXRegP);
5101 match(eBXRegP);
5102 match(eCXRegP);
5103 match(eDIRegP);
5104 match(eRegP);
5106 format %{ %}
5107 interface(REG_INTER);
5108 %}
5110 operand eRegP() %{
5111 constraint(ALLOC_IN_RC(e_reg));
5112 match(RegP);
5113 match(eAXRegP);
5114 match(eBXRegP);
5115 match(eCXRegP);
5116 match(eDIRegP);
5118 format %{ %}
5119 interface(REG_INTER);
5120 %}
5122 // On windows95, EBP is not safe to use for implicit null tests.
5123 operand eRegP_no_EBP() %{
5124 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5125 match(RegP);
5126 match(eAXRegP);
5127 match(eBXRegP);
5128 match(eCXRegP);
5129 match(eDIRegP);
5131 op_cost(100);
5132 format %{ %}
5133 interface(REG_INTER);
5134 %}
5136 operand naxRegP() %{
5137 constraint(ALLOC_IN_RC(nax_reg));
5138 match(RegP);
5139 match(eBXRegP);
5140 match(eDXRegP);
5141 match(eCXRegP);
5142 match(eSIRegP);
5143 match(eDIRegP);
5145 format %{ %}
5146 interface(REG_INTER);
5147 %}
5149 operand nabxRegP() %{
5150 constraint(ALLOC_IN_RC(nabx_reg));
5151 match(RegP);
5152 match(eCXRegP);
5153 match(eDXRegP);
5154 match(eSIRegP);
5155 match(eDIRegP);
5157 format %{ %}
5158 interface(REG_INTER);
5159 %}
5161 operand pRegP() %{
5162 constraint(ALLOC_IN_RC(p_reg));
5163 match(RegP);
5164 match(eBXRegP);
5165 match(eDXRegP);
5166 match(eSIRegP);
5167 match(eDIRegP);
5169 format %{ %}
5170 interface(REG_INTER);
5171 %}
5173 // Special Registers
5174 // Return a pointer value
5175 operand eAXRegP(eRegP reg) %{
5176 constraint(ALLOC_IN_RC(eax_reg));
5177 match(reg);
5178 format %{ "EAX" %}
5179 interface(REG_INTER);
5180 %}
5182 // Used in AtomicAdd
5183 operand eBXRegP(eRegP reg) %{
5184 constraint(ALLOC_IN_RC(ebx_reg));
5185 match(reg);
5186 format %{ "EBX" %}
5187 interface(REG_INTER);
5188 %}
5190 // Tail-call (interprocedural jump) to interpreter
5191 operand eCXRegP(eRegP reg) %{
5192 constraint(ALLOC_IN_RC(ecx_reg));
5193 match(reg);
5194 format %{ "ECX" %}
5195 interface(REG_INTER);
5196 %}
5198 operand eSIRegP(eRegP reg) %{
5199 constraint(ALLOC_IN_RC(esi_reg));
5200 match(reg);
5201 format %{ "ESI" %}
5202 interface(REG_INTER);
5203 %}
5205 // Used in rep stosw
5206 operand eDIRegP(eRegP reg) %{
5207 constraint(ALLOC_IN_RC(edi_reg));
5208 match(reg);
5209 format %{ "EDI" %}
5210 interface(REG_INTER);
5211 %}
5213 operand eBPRegP() %{
5214 constraint(ALLOC_IN_RC(ebp_reg));
5215 match(RegP);
5216 format %{ "EBP" %}
5217 interface(REG_INTER);
5218 %}
5220 operand eRegL() %{
5221 constraint(ALLOC_IN_RC(long_reg));
5222 match(RegL);
5223 match(eADXRegL);
5225 format %{ %}
5226 interface(REG_INTER);
5227 %}
5229 operand eADXRegL( eRegL reg ) %{
5230 constraint(ALLOC_IN_RC(eadx_reg));
5231 match(reg);
5233 format %{ "EDX:EAX" %}
5234 interface(REG_INTER);
5235 %}
5237 operand eBCXRegL( eRegL reg ) %{
5238 constraint(ALLOC_IN_RC(ebcx_reg));
5239 match(reg);
5241 format %{ "EBX:ECX" %}
5242 interface(REG_INTER);
5243 %}
5245 // Special case for integer high multiply
5246 operand eADXRegL_low_only() %{
5247 constraint(ALLOC_IN_RC(eadx_reg));
5248 match(RegL);
5250 format %{ "EAX" %}
5251 interface(REG_INTER);
5252 %}
5254 // Flags register, used as output of compare instructions
5255 operand eFlagsReg() %{
5256 constraint(ALLOC_IN_RC(int_flags));
5257 match(RegFlags);
5259 format %{ "EFLAGS" %}
5260 interface(REG_INTER);
5261 %}
5263 // Flags register, used as output of FLOATING POINT compare instructions
5264 operand eFlagsRegU() %{
5265 constraint(ALLOC_IN_RC(int_flags));
5266 match(RegFlags);
5268 format %{ "EFLAGS_U" %}
5269 interface(REG_INTER);
5270 %}
5272 operand eFlagsRegUCF() %{
5273 constraint(ALLOC_IN_RC(int_flags));
5274 match(RegFlags);
5275 predicate(false);
5277 format %{ "EFLAGS_U_CF" %}
5278 interface(REG_INTER);
5279 %}
5281 // Condition Code Register used by long compare
5282 operand flagsReg_long_LTGE() %{
5283 constraint(ALLOC_IN_RC(int_flags));
5284 match(RegFlags);
5285 format %{ "FLAGS_LTGE" %}
5286 interface(REG_INTER);
5287 %}
5288 operand flagsReg_long_EQNE() %{
5289 constraint(ALLOC_IN_RC(int_flags));
5290 match(RegFlags);
5291 format %{ "FLAGS_EQNE" %}
5292 interface(REG_INTER);
5293 %}
5294 operand flagsReg_long_LEGT() %{
5295 constraint(ALLOC_IN_RC(int_flags));
5296 match(RegFlags);
5297 format %{ "FLAGS_LEGT" %}
5298 interface(REG_INTER);
5299 %}
5301 // Float register operands
5302 operand regD() %{
5303 predicate( UseSSE < 2 );
5304 constraint(ALLOC_IN_RC(dbl_reg));
5305 match(RegD);
5306 match(regDPR1);
5307 match(regDPR2);
5308 format %{ %}
5309 interface(REG_INTER);
5310 %}
5312 operand regDPR1(regD reg) %{
5313 predicate( UseSSE < 2 );
5314 constraint(ALLOC_IN_RC(dbl_reg0));
5315 match(reg);
5316 format %{ "FPR1" %}
5317 interface(REG_INTER);
5318 %}
5320 operand regDPR2(regD reg) %{
5321 predicate( UseSSE < 2 );
5322 constraint(ALLOC_IN_RC(dbl_reg1));
5323 match(reg);
5324 format %{ "FPR2" %}
5325 interface(REG_INTER);
5326 %}
5328 operand regnotDPR1(regD reg) %{
5329 predicate( UseSSE < 2 );
5330 constraint(ALLOC_IN_RC(dbl_notreg0));
5331 match(reg);
5332 format %{ %}
5333 interface(REG_INTER);
5334 %}
5336 // XMM Double register operands
5337 operand regXD() %{
5338 predicate( UseSSE>=2 );
5339 constraint(ALLOC_IN_RC(xdb_reg));
5340 match(RegD);
5341 match(regXD6);
5342 match(regXD7);
5343 format %{ %}
5344 interface(REG_INTER);
5345 %}
5347 // XMM6 double register operands
5348 operand regXD6(regXD reg) %{
5349 predicate( UseSSE>=2 );
5350 constraint(ALLOC_IN_RC(xdb_reg6));
5351 match(reg);
5352 format %{ "XMM6" %}
5353 interface(REG_INTER);
5354 %}
5356 // XMM7 double register operands
5357 operand regXD7(regXD reg) %{
5358 predicate( UseSSE>=2 );
5359 constraint(ALLOC_IN_RC(xdb_reg7));
5360 match(reg);
5361 format %{ "XMM7" %}
5362 interface(REG_INTER);
5363 %}
5365 // Float register operands
5366 operand regF() %{
5367 predicate( UseSSE < 2 );
5368 constraint(ALLOC_IN_RC(flt_reg));
5369 match(RegF);
5370 match(regFPR1);
5371 format %{ %}
5372 interface(REG_INTER);
5373 %}
5375 // Float register operands
5376 operand regFPR1(regF reg) %{
5377 predicate( UseSSE < 2 );
5378 constraint(ALLOC_IN_RC(flt_reg0));
5379 match(reg);
5380 format %{ "FPR1" %}
5381 interface(REG_INTER);
5382 %}
5384 // XMM register operands
5385 operand regX() %{
5386 predicate( UseSSE>=1 );
5387 constraint(ALLOC_IN_RC(xmm_reg));
5388 match(RegF);
5389 format %{ %}
5390 interface(REG_INTER);
5391 %}
5394 //----------Memory Operands----------------------------------------------------
5395 // Direct Memory Operand
5396 operand direct(immP addr) %{
5397 match(addr);
5399 format %{ "[$addr]" %}
5400 interface(MEMORY_INTER) %{
5401 base(0xFFFFFFFF);
5402 index(0x4);
5403 scale(0x0);
5404 disp($addr);
5405 %}
5406 %}
5408 // Indirect Memory Operand
5409 operand indirect(eRegP reg) %{
5410 constraint(ALLOC_IN_RC(e_reg));
5411 match(reg);
5413 format %{ "[$reg]" %}
5414 interface(MEMORY_INTER) %{
5415 base($reg);
5416 index(0x4);
5417 scale(0x0);
5418 disp(0x0);
5419 %}
5420 %}
5422 // Indirect Memory Plus Short Offset Operand
5423 operand indOffset8(eRegP reg, immI8 off) %{
5424 match(AddP reg off);
5426 format %{ "[$reg + $off]" %}
5427 interface(MEMORY_INTER) %{
5428 base($reg);
5429 index(0x4);
5430 scale(0x0);
5431 disp($off);
5432 %}
5433 %}
5435 // Indirect Memory Plus Long Offset Operand
5436 operand indOffset32(eRegP reg, immI off) %{
5437 match(AddP reg off);
5439 format %{ "[$reg + $off]" %}
5440 interface(MEMORY_INTER) %{
5441 base($reg);
5442 index(0x4);
5443 scale(0x0);
5444 disp($off);
5445 %}
5446 %}
5448 // Indirect Memory Plus Long Offset Operand
5449 operand indOffset32X(eRegI reg, immP off) %{
5450 match(AddP off reg);
5452 format %{ "[$reg + $off]" %}
5453 interface(MEMORY_INTER) %{
5454 base($reg);
5455 index(0x4);
5456 scale(0x0);
5457 disp($off);
5458 %}
5459 %}
5461 // Indirect Memory Plus Index Register Plus Offset Operand
5462 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5463 match(AddP (AddP reg ireg) off);
5465 op_cost(10);
5466 format %{"[$reg + $off + $ireg]" %}
5467 interface(MEMORY_INTER) %{
5468 base($reg);
5469 index($ireg);
5470 scale(0x0);
5471 disp($off);
5472 %}
5473 %}
5475 // Indirect Memory Plus Index Register Plus Offset Operand
5476 operand indIndex(eRegP reg, eRegI ireg) %{
5477 match(AddP reg ireg);
5479 op_cost(10);
5480 format %{"[$reg + $ireg]" %}
5481 interface(MEMORY_INTER) %{
5482 base($reg);
5483 index($ireg);
5484 scale(0x0);
5485 disp(0x0);
5486 %}
5487 %}
5489 // // -------------------------------------------------------------------------
5490 // // 486 architecture doesn't support "scale * index + offset" with out a base
5491 // // -------------------------------------------------------------------------
5492 // // Scaled Memory Operands
5493 // // Indirect Memory Times Scale Plus Offset Operand
5494 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5495 // match(AddP off (LShiftI ireg scale));
5496 //
5497 // op_cost(10);
5498 // format %{"[$off + $ireg << $scale]" %}
5499 // interface(MEMORY_INTER) %{
5500 // base(0x4);
5501 // index($ireg);
5502 // scale($scale);
5503 // disp($off);
5504 // %}
5505 // %}
5507 // Indirect Memory Times Scale Plus Index Register
5508 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5509 match(AddP reg (LShiftI ireg scale));
5511 op_cost(10);
5512 format %{"[$reg + $ireg << $scale]" %}
5513 interface(MEMORY_INTER) %{
5514 base($reg);
5515 index($ireg);
5516 scale($scale);
5517 disp(0x0);
5518 %}
5519 %}
5521 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5522 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5523 match(AddP (AddP reg (LShiftI ireg scale)) off);
5525 op_cost(10);
5526 format %{"[$reg + $off + $ireg << $scale]" %}
5527 interface(MEMORY_INTER) %{
5528 base($reg);
5529 index($ireg);
5530 scale($scale);
5531 disp($off);
5532 %}
5533 %}
5535 //----------Load Long Memory Operands------------------------------------------
5536 // The load-long idiom will use it's address expression again after loading
5537 // the first word of the long. If the load-long destination overlaps with
5538 // registers used in the addressing expression, the 2nd half will be loaded
5539 // from a clobbered address. Fix this by requiring that load-long use
5540 // address registers that do not overlap with the load-long target.
5542 // load-long support
5543 operand load_long_RegP() %{
5544 constraint(ALLOC_IN_RC(esi_reg));
5545 match(RegP);
5546 match(eSIRegP);
5547 op_cost(100);
5548 format %{ %}
5549 interface(REG_INTER);
5550 %}
5552 // Indirect Memory Operand Long
5553 operand load_long_indirect(load_long_RegP reg) %{
5554 constraint(ALLOC_IN_RC(esi_reg));
5555 match(reg);
5557 format %{ "[$reg]" %}
5558 interface(MEMORY_INTER) %{
5559 base($reg);
5560 index(0x4);
5561 scale(0x0);
5562 disp(0x0);
5563 %}
5564 %}
5566 // Indirect Memory Plus Long Offset Operand
5567 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5568 match(AddP reg off);
5570 format %{ "[$reg + $off]" %}
5571 interface(MEMORY_INTER) %{
5572 base($reg);
5573 index(0x4);
5574 scale(0x0);
5575 disp($off);
5576 %}
5577 %}
5579 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5582 //----------Special Memory Operands--------------------------------------------
5583 // Stack Slot Operand - This operand is used for loading and storing temporary
5584 // values on the stack where a match requires a value to
5585 // flow through memory.
5586 operand stackSlotP(sRegP reg) %{
5587 constraint(ALLOC_IN_RC(stack_slots));
5588 // No match rule because this operand is only generated in matching
5589 format %{ "[$reg]" %}
5590 interface(MEMORY_INTER) %{
5591 base(0x4); // ESP
5592 index(0x4); // No Index
5593 scale(0x0); // No Scale
5594 disp($reg); // Stack Offset
5595 %}
5596 %}
5598 operand stackSlotI(sRegI reg) %{
5599 constraint(ALLOC_IN_RC(stack_slots));
5600 // No match rule because this operand is only generated in matching
5601 format %{ "[$reg]" %}
5602 interface(MEMORY_INTER) %{
5603 base(0x4); // ESP
5604 index(0x4); // No Index
5605 scale(0x0); // No Scale
5606 disp($reg); // Stack Offset
5607 %}
5608 %}
5610 operand stackSlotF(sRegF reg) %{
5611 constraint(ALLOC_IN_RC(stack_slots));
5612 // No match rule because this operand is only generated in matching
5613 format %{ "[$reg]" %}
5614 interface(MEMORY_INTER) %{
5615 base(0x4); // ESP
5616 index(0x4); // No Index
5617 scale(0x0); // No Scale
5618 disp($reg); // Stack Offset
5619 %}
5620 %}
5622 operand stackSlotD(sRegD reg) %{
5623 constraint(ALLOC_IN_RC(stack_slots));
5624 // No match rule because this operand is only generated in matching
5625 format %{ "[$reg]" %}
5626 interface(MEMORY_INTER) %{
5627 base(0x4); // ESP
5628 index(0x4); // No Index
5629 scale(0x0); // No Scale
5630 disp($reg); // Stack Offset
5631 %}
5632 %}
5634 operand stackSlotL(sRegL reg) %{
5635 constraint(ALLOC_IN_RC(stack_slots));
5636 // No match rule because this operand is only generated in matching
5637 format %{ "[$reg]" %}
5638 interface(MEMORY_INTER) %{
5639 base(0x4); // ESP
5640 index(0x4); // No Index
5641 scale(0x0); // No Scale
5642 disp($reg); // Stack Offset
5643 %}
5644 %}
5646 //----------Memory Operands - Win95 Implicit Null Variants----------------
5647 // Indirect Memory Operand
5648 operand indirect_win95_safe(eRegP_no_EBP reg)
5649 %{
5650 constraint(ALLOC_IN_RC(e_reg));
5651 match(reg);
5653 op_cost(100);
5654 format %{ "[$reg]" %}
5655 interface(MEMORY_INTER) %{
5656 base($reg);
5657 index(0x4);
5658 scale(0x0);
5659 disp(0x0);
5660 %}
5661 %}
5663 // Indirect Memory Plus Short Offset Operand
5664 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5665 %{
5666 match(AddP reg off);
5668 op_cost(100);
5669 format %{ "[$reg + $off]" %}
5670 interface(MEMORY_INTER) %{
5671 base($reg);
5672 index(0x4);
5673 scale(0x0);
5674 disp($off);
5675 %}
5676 %}
5678 // Indirect Memory Plus Long Offset Operand
5679 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5680 %{
5681 match(AddP reg off);
5683 op_cost(100);
5684 format %{ "[$reg + $off]" %}
5685 interface(MEMORY_INTER) %{
5686 base($reg);
5687 index(0x4);
5688 scale(0x0);
5689 disp($off);
5690 %}
5691 %}
5693 // Indirect Memory Plus Index Register Plus Offset Operand
5694 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5695 %{
5696 match(AddP (AddP reg ireg) off);
5698 op_cost(100);
5699 format %{"[$reg + $off + $ireg]" %}
5700 interface(MEMORY_INTER) %{
5701 base($reg);
5702 index($ireg);
5703 scale(0x0);
5704 disp($off);
5705 %}
5706 %}
5708 // Indirect Memory Times Scale Plus Index Register
5709 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5710 %{
5711 match(AddP reg (LShiftI ireg scale));
5713 op_cost(100);
5714 format %{"[$reg + $ireg << $scale]" %}
5715 interface(MEMORY_INTER) %{
5716 base($reg);
5717 index($ireg);
5718 scale($scale);
5719 disp(0x0);
5720 %}
5721 %}
5723 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5724 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5725 %{
5726 match(AddP (AddP reg (LShiftI ireg scale)) off);
5728 op_cost(100);
5729 format %{"[$reg + $off + $ireg << $scale]" %}
5730 interface(MEMORY_INTER) %{
5731 base($reg);
5732 index($ireg);
5733 scale($scale);
5734 disp($off);
5735 %}
5736 %}
5738 //----------Conditional Branch Operands----------------------------------------
5739 // Comparison Op - This is the operation of the comparison, and is limited to
5740 // the following set of codes:
5741 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5742 //
5743 // Other attributes of the comparison, such as unsignedness, are specified
5744 // by the comparison instruction that sets a condition code flags register.
5745 // That result is represented by a flags operand whose subtype is appropriate
5746 // to the unsignedness (etc.) of the comparison.
5747 //
5748 // Later, the instruction which matches both the Comparison Op (a Bool) and
5749 // the flags (produced by the Cmp) specifies the coding of the comparison op
5750 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5752 // Comparision Code
5753 operand cmpOp() %{
5754 match(Bool);
5756 format %{ "" %}
5757 interface(COND_INTER) %{
5758 equal(0x4, "e");
5759 not_equal(0x5, "ne");
5760 less(0xC, "l");
5761 greater_equal(0xD, "ge");
5762 less_equal(0xE, "le");
5763 greater(0xF, "g");
5764 %}
5765 %}
5767 // Comparison Code, unsigned compare. Used by FP also, with
5768 // C2 (unordered) turned into GT or LT already. The other bits
5769 // C0 and C3 are turned into Carry & Zero flags.
5770 operand cmpOpU() %{
5771 match(Bool);
5773 format %{ "" %}
5774 interface(COND_INTER) %{
5775 equal(0x4, "e");
5776 not_equal(0x5, "ne");
5777 less(0x2, "b");
5778 greater_equal(0x3, "nb");
5779 less_equal(0x6, "be");
5780 greater(0x7, "nbe");
5781 %}
5782 %}
5784 // Floating comparisons that don't require any fixup for the unordered case
5785 operand cmpOpUCF() %{
5786 match(Bool);
5787 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5788 n->as_Bool()->_test._test == BoolTest::ge ||
5789 n->as_Bool()->_test._test == BoolTest::le ||
5790 n->as_Bool()->_test._test == BoolTest::gt);
5791 format %{ "" %}
5792 interface(COND_INTER) %{
5793 equal(0x4, "e");
5794 not_equal(0x5, "ne");
5795 less(0x2, "b");
5796 greater_equal(0x3, "nb");
5797 less_equal(0x6, "be");
5798 greater(0x7, "nbe");
5799 %}
5800 %}
5803 // Floating comparisons that can be fixed up with extra conditional jumps
5804 operand cmpOpUCF2() %{
5805 match(Bool);
5806 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5807 n->as_Bool()->_test._test == BoolTest::eq);
5808 format %{ "" %}
5809 interface(COND_INTER) %{
5810 equal(0x4, "e");
5811 not_equal(0x5, "ne");
5812 less(0x2, "b");
5813 greater_equal(0x3, "nb");
5814 less_equal(0x6, "be");
5815 greater(0x7, "nbe");
5816 %}
5817 %}
5819 // Comparison Code for FP conditional move
5820 operand cmpOp_fcmov() %{
5821 match(Bool);
5823 format %{ "" %}
5824 interface(COND_INTER) %{
5825 equal (0x0C8);
5826 not_equal (0x1C8);
5827 less (0x0C0);
5828 greater_equal(0x1C0);
5829 less_equal (0x0D0);
5830 greater (0x1D0);
5831 %}
5832 %}
5834 // Comparision Code used in long compares
5835 operand cmpOp_commute() %{
5836 match(Bool);
5838 format %{ "" %}
5839 interface(COND_INTER) %{
5840 equal(0x4, "e");
5841 not_equal(0x5, "ne");
5842 less(0xF, "g");
5843 greater_equal(0xE, "le");
5844 less_equal(0xD, "ge");
5845 greater(0xC, "l");
5846 %}
5847 %}
5849 //----------OPERAND CLASSES----------------------------------------------------
5850 // Operand Classes are groups of operands that are used as to simplify
5851 // instruction definitions by not requiring the AD writer to specify separate
5852 // instructions for every form of operand when the instruction accepts
5853 // multiple operand types with the same basic encoding and format. The classic
5854 // case of this is memory operands.
5856 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5857 indIndex, indIndexScale, indIndexScaleOffset);
5859 // Long memory operations are encoded in 2 instructions and a +4 offset.
5860 // This means some kind of offset is always required and you cannot use
5861 // an oop as the offset (done when working on static globals).
5862 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5863 indIndex, indIndexScale, indIndexScaleOffset);
5866 //----------PIPELINE-----------------------------------------------------------
5867 // Rules which define the behavior of the target architectures pipeline.
5868 pipeline %{
5870 //----------ATTRIBUTES---------------------------------------------------------
5871 attributes %{
5872 variable_size_instructions; // Fixed size instructions
5873 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5874 instruction_unit_size = 1; // An instruction is 1 bytes long
5875 instruction_fetch_unit_size = 16; // The processor fetches one line
5876 instruction_fetch_units = 1; // of 16 bytes
5878 // List of nop instructions
5879 nops( MachNop );
5880 %}
5882 //----------RESOURCES----------------------------------------------------------
5883 // Resources are the functional units available to the machine
5885 // Generic P2/P3 pipeline
5886 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5887 // 3 instructions decoded per cycle.
5888 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5889 // 2 ALU op, only ALU0 handles mul/div instructions.
5890 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5891 MS0, MS1, MEM = MS0 | MS1,
5892 BR, FPU,
5893 ALU0, ALU1, ALU = ALU0 | ALU1 );
5895 //----------PIPELINE DESCRIPTION-----------------------------------------------
5896 // Pipeline Description specifies the stages in the machine's pipeline
5898 // Generic P2/P3 pipeline
5899 pipe_desc(S0, S1, S2, S3, S4, S5);
5901 //----------PIPELINE CLASSES---------------------------------------------------
5902 // Pipeline Classes describe the stages in which input and output are
5903 // referenced by the hardware pipeline.
5905 // Naming convention: ialu or fpu
5906 // Then: _reg
5907 // Then: _reg if there is a 2nd register
5908 // Then: _long if it's a pair of instructions implementing a long
5909 // Then: _fat if it requires the big decoder
5910 // Or: _mem if it requires the big decoder and a memory unit.
5912 // Integer ALU reg operation
5913 pipe_class ialu_reg(eRegI dst) %{
5914 single_instruction;
5915 dst : S4(write);
5916 dst : S3(read);
5917 DECODE : S0; // any decoder
5918 ALU : S3; // any alu
5919 %}
5921 // Long ALU reg operation
5922 pipe_class ialu_reg_long(eRegL dst) %{
5923 instruction_count(2);
5924 dst : S4(write);
5925 dst : S3(read);
5926 DECODE : S0(2); // any 2 decoders
5927 ALU : S3(2); // both alus
5928 %}
5930 // Integer ALU reg operation using big decoder
5931 pipe_class ialu_reg_fat(eRegI dst) %{
5932 single_instruction;
5933 dst : S4(write);
5934 dst : S3(read);
5935 D0 : S0; // big decoder only
5936 ALU : S3; // any alu
5937 %}
5939 // Long ALU reg operation using big decoder
5940 pipe_class ialu_reg_long_fat(eRegL dst) %{
5941 instruction_count(2);
5942 dst : S4(write);
5943 dst : S3(read);
5944 D0 : S0(2); // big decoder only; twice
5945 ALU : S3(2); // any 2 alus
5946 %}
5948 // Integer ALU reg-reg operation
5949 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5950 single_instruction;
5951 dst : S4(write);
5952 src : S3(read);
5953 DECODE : S0; // any decoder
5954 ALU : S3; // any alu
5955 %}
5957 // Long ALU reg-reg operation
5958 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5959 instruction_count(2);
5960 dst : S4(write);
5961 src : S3(read);
5962 DECODE : S0(2); // any 2 decoders
5963 ALU : S3(2); // both alus
5964 %}
5966 // Integer ALU reg-reg operation
5967 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5968 single_instruction;
5969 dst : S4(write);
5970 src : S3(read);
5971 D0 : S0; // big decoder only
5972 ALU : S3; // any alu
5973 %}
5975 // Long ALU reg-reg operation
5976 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5977 instruction_count(2);
5978 dst : S4(write);
5979 src : S3(read);
5980 D0 : S0(2); // big decoder only; twice
5981 ALU : S3(2); // both alus
5982 %}
5984 // Integer ALU reg-mem operation
5985 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5986 single_instruction;
5987 dst : S5(write);
5988 mem : S3(read);
5989 D0 : S0; // big decoder only
5990 ALU : S4; // any alu
5991 MEM : S3; // any mem
5992 %}
5994 // Long ALU reg-mem operation
5995 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5996 instruction_count(2);
5997 dst : S5(write);
5998 mem : S3(read);
5999 D0 : S0(2); // big decoder only; twice
6000 ALU : S4(2); // any 2 alus
6001 MEM : S3(2); // both mems
6002 %}
6004 // Integer mem operation (prefetch)
6005 pipe_class ialu_mem(memory mem)
6006 %{
6007 single_instruction;
6008 mem : S3(read);
6009 D0 : S0; // big decoder only
6010 MEM : S3; // any mem
6011 %}
6013 // Integer Store to Memory
6014 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
6015 single_instruction;
6016 mem : S3(read);
6017 src : S5(read);
6018 D0 : S0; // big decoder only
6019 ALU : S4; // any alu
6020 MEM : S3;
6021 %}
6023 // Long Store to Memory
6024 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
6025 instruction_count(2);
6026 mem : S3(read);
6027 src : S5(read);
6028 D0 : S0(2); // big decoder only; twice
6029 ALU : S4(2); // any 2 alus
6030 MEM : S3(2); // Both mems
6031 %}
6033 // Integer Store to Memory
6034 pipe_class ialu_mem_imm(memory mem) %{
6035 single_instruction;
6036 mem : S3(read);
6037 D0 : S0; // big decoder only
6038 ALU : S4; // any alu
6039 MEM : S3;
6040 %}
6042 // Integer ALU0 reg-reg operation
6043 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6044 single_instruction;
6045 dst : S4(write);
6046 src : S3(read);
6047 D0 : S0; // Big decoder only
6048 ALU0 : S3; // only alu0
6049 %}
6051 // Integer ALU0 reg-mem operation
6052 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6053 single_instruction;
6054 dst : S5(write);
6055 mem : S3(read);
6056 D0 : S0; // big decoder only
6057 ALU0 : S4; // ALU0 only
6058 MEM : S3; // any mem
6059 %}
6061 // Integer ALU reg-reg operation
6062 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6063 single_instruction;
6064 cr : S4(write);
6065 src1 : S3(read);
6066 src2 : S3(read);
6067 DECODE : S0; // any decoder
6068 ALU : S3; // any alu
6069 %}
6071 // Integer ALU reg-imm operation
6072 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6073 single_instruction;
6074 cr : S4(write);
6075 src1 : S3(read);
6076 DECODE : S0; // any decoder
6077 ALU : S3; // any alu
6078 %}
6080 // Integer ALU reg-mem operation
6081 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6082 single_instruction;
6083 cr : S4(write);
6084 src1 : S3(read);
6085 src2 : S3(read);
6086 D0 : S0; // big decoder only
6087 ALU : S4; // any alu
6088 MEM : S3;
6089 %}
6091 // Conditional move reg-reg
6092 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6093 instruction_count(4);
6094 y : S4(read);
6095 q : S3(read);
6096 p : S3(read);
6097 DECODE : S0(4); // any decoder
6098 %}
6100 // Conditional move reg-reg
6101 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6102 single_instruction;
6103 dst : S4(write);
6104 src : S3(read);
6105 cr : S3(read);
6106 DECODE : S0; // any decoder
6107 %}
6109 // Conditional move reg-mem
6110 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6111 single_instruction;
6112 dst : S4(write);
6113 src : S3(read);
6114 cr : S3(read);
6115 DECODE : S0; // any decoder
6116 MEM : S3;
6117 %}
6119 // Conditional move reg-reg long
6120 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6121 single_instruction;
6122 dst : S4(write);
6123 src : S3(read);
6124 cr : S3(read);
6125 DECODE : S0(2); // any 2 decoders
6126 %}
6128 // Conditional move double reg-reg
6129 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6130 single_instruction;
6131 dst : S4(write);
6132 src : S3(read);
6133 cr : S3(read);
6134 DECODE : S0; // any decoder
6135 %}
6137 // Float reg-reg operation
6138 pipe_class fpu_reg(regD dst) %{
6139 instruction_count(2);
6140 dst : S3(read);
6141 DECODE : S0(2); // any 2 decoders
6142 FPU : S3;
6143 %}
6145 // Float reg-reg operation
6146 pipe_class fpu_reg_reg(regD dst, regD src) %{
6147 instruction_count(2);
6148 dst : S4(write);
6149 src : S3(read);
6150 DECODE : S0(2); // any 2 decoders
6151 FPU : S3;
6152 %}
6154 // Float reg-reg operation
6155 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6156 instruction_count(3);
6157 dst : S4(write);
6158 src1 : S3(read);
6159 src2 : S3(read);
6160 DECODE : S0(3); // any 3 decoders
6161 FPU : S3(2);
6162 %}
6164 // Float reg-reg operation
6165 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6166 instruction_count(4);
6167 dst : S4(write);
6168 src1 : S3(read);
6169 src2 : S3(read);
6170 src3 : S3(read);
6171 DECODE : S0(4); // any 3 decoders
6172 FPU : S3(2);
6173 %}
6175 // Float reg-reg operation
6176 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6177 instruction_count(4);
6178 dst : S4(write);
6179 src1 : S3(read);
6180 src2 : S3(read);
6181 src3 : S3(read);
6182 DECODE : S1(3); // any 3 decoders
6183 D0 : S0; // Big decoder only
6184 FPU : S3(2);
6185 MEM : S3;
6186 %}
6188 // Float reg-mem operation
6189 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6190 instruction_count(2);
6191 dst : S5(write);
6192 mem : S3(read);
6193 D0 : S0; // big decoder only
6194 DECODE : S1; // any decoder for FPU POP
6195 FPU : S4;
6196 MEM : S3; // any mem
6197 %}
6199 // Float reg-mem operation
6200 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6201 instruction_count(3);
6202 dst : S5(write);
6203 src1 : S3(read);
6204 mem : S3(read);
6205 D0 : S0; // big decoder only
6206 DECODE : S1(2); // any decoder for FPU POP
6207 FPU : S4;
6208 MEM : S3; // any mem
6209 %}
6211 // Float mem-reg operation
6212 pipe_class fpu_mem_reg(memory mem, regD src) %{
6213 instruction_count(2);
6214 src : S5(read);
6215 mem : S3(read);
6216 DECODE : S0; // any decoder for FPU PUSH
6217 D0 : S1; // big decoder only
6218 FPU : S4;
6219 MEM : S3; // any mem
6220 %}
6222 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6223 instruction_count(3);
6224 src1 : S3(read);
6225 src2 : S3(read);
6226 mem : S3(read);
6227 DECODE : S0(2); // any decoder for FPU PUSH
6228 D0 : S1; // big decoder only
6229 FPU : S4;
6230 MEM : S3; // any mem
6231 %}
6233 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6234 instruction_count(3);
6235 src1 : S3(read);
6236 src2 : S3(read);
6237 mem : S4(read);
6238 DECODE : S0; // any decoder for FPU PUSH
6239 D0 : S0(2); // big decoder only
6240 FPU : S4;
6241 MEM : S3(2); // any mem
6242 %}
6244 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6245 instruction_count(2);
6246 src1 : S3(read);
6247 dst : S4(read);
6248 D0 : S0(2); // big decoder only
6249 MEM : S3(2); // any mem
6250 %}
6252 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6253 instruction_count(3);
6254 src1 : S3(read);
6255 src2 : S3(read);
6256 dst : S4(read);
6257 D0 : S0(3); // big decoder only
6258 FPU : S4;
6259 MEM : S3(3); // any mem
6260 %}
6262 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6263 instruction_count(3);
6264 src1 : S4(read);
6265 mem : S4(read);
6266 DECODE : S0; // any decoder for FPU PUSH
6267 D0 : S0(2); // big decoder only
6268 FPU : S4;
6269 MEM : S3(2); // any mem
6270 %}
6272 // Float load constant
6273 pipe_class fpu_reg_con(regD dst) %{
6274 instruction_count(2);
6275 dst : S5(write);
6276 D0 : S0; // big decoder only for the load
6277 DECODE : S1; // any decoder for FPU POP
6278 FPU : S4;
6279 MEM : S3; // any mem
6280 %}
6282 // Float load constant
6283 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6284 instruction_count(3);
6285 dst : S5(write);
6286 src : S3(read);
6287 D0 : S0; // big decoder only for the load
6288 DECODE : S1(2); // any decoder for FPU POP
6289 FPU : S4;
6290 MEM : S3; // any mem
6291 %}
6293 // UnConditional branch
6294 pipe_class pipe_jmp( label labl ) %{
6295 single_instruction;
6296 BR : S3;
6297 %}
6299 // Conditional branch
6300 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6301 single_instruction;
6302 cr : S1(read);
6303 BR : S3;
6304 %}
6306 // Allocation idiom
6307 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6308 instruction_count(1); force_serialization;
6309 fixed_latency(6);
6310 heap_ptr : S3(read);
6311 DECODE : S0(3);
6312 D0 : S2;
6313 MEM : S3;
6314 ALU : S3(2);
6315 dst : S5(write);
6316 BR : S5;
6317 %}
6319 // Generic big/slow expanded idiom
6320 pipe_class pipe_slow( ) %{
6321 instruction_count(10); multiple_bundles; force_serialization;
6322 fixed_latency(100);
6323 D0 : S0(2);
6324 MEM : S3(2);
6325 %}
6327 // The real do-nothing guy
6328 pipe_class empty( ) %{
6329 instruction_count(0);
6330 %}
6332 // Define the class for the Nop node
6333 define %{
6334 MachNop = empty;
6335 %}
6337 %}
6339 //----------INSTRUCTIONS-------------------------------------------------------
6340 //
6341 // match -- States which machine-independent subtree may be replaced
6342 // by this instruction.
6343 // ins_cost -- The estimated cost of this instruction is used by instruction
6344 // selection to identify a minimum cost tree of machine
6345 // instructions that matches a tree of machine-independent
6346 // instructions.
6347 // format -- A string providing the disassembly for this instruction.
6348 // The value of an instruction's operand may be inserted
6349 // by referring to it with a '$' prefix.
6350 // opcode -- Three instruction opcodes may be provided. These are referred
6351 // to within an encode class as $primary, $secondary, and $tertiary
6352 // respectively. The primary opcode is commonly used to
6353 // indicate the type of machine instruction, while secondary
6354 // and tertiary are often used for prefix options or addressing
6355 // modes.
6356 // ins_encode -- A list of encode classes with parameters. The encode class
6357 // name must have been defined in an 'enc_class' specification
6358 // in the encode section of the architecture description.
6360 //----------BSWAP-Instruction--------------------------------------------------
6361 instruct bytes_reverse_int(eRegI dst) %{
6362 match(Set dst (ReverseBytesI dst));
6364 format %{ "BSWAP $dst" %}
6365 opcode(0x0F, 0xC8);
6366 ins_encode( OpcP, OpcSReg(dst) );
6367 ins_pipe( ialu_reg );
6368 %}
6370 instruct bytes_reverse_long(eRegL dst) %{
6371 match(Set dst (ReverseBytesL dst));
6373 format %{ "BSWAP $dst.lo\n\t"
6374 "BSWAP $dst.hi\n\t"
6375 "XCHG $dst.lo $dst.hi" %}
6377 ins_cost(125);
6378 ins_encode( bswap_long_bytes(dst) );
6379 ins_pipe( ialu_reg_reg);
6380 %}
6383 //---------- Population Count Instructions -------------------------------------
6385 instruct popCountI(eRegI dst, eRegI src) %{
6386 predicate(UsePopCountInstruction);
6387 match(Set dst (PopCountI src));
6389 format %{ "POPCNT $dst, $src" %}
6390 ins_encode %{
6391 __ popcntl($dst$$Register, $src$$Register);
6392 %}
6393 ins_pipe(ialu_reg);
6394 %}
6396 instruct popCountI_mem(eRegI dst, memory mem) %{
6397 predicate(UsePopCountInstruction);
6398 match(Set dst (PopCountI (LoadI mem)));
6400 format %{ "POPCNT $dst, $mem" %}
6401 ins_encode %{
6402 __ popcntl($dst$$Register, $mem$$Address);
6403 %}
6404 ins_pipe(ialu_reg);
6405 %}
6407 // Note: Long.bitCount(long) returns an int.
6408 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
6409 predicate(UsePopCountInstruction);
6410 match(Set dst (PopCountL src));
6411 effect(KILL cr, TEMP tmp, TEMP dst);
6413 format %{ "POPCNT $dst, $src.lo\n\t"
6414 "POPCNT $tmp, $src.hi\n\t"
6415 "ADD $dst, $tmp" %}
6416 ins_encode %{
6417 __ popcntl($dst$$Register, $src$$Register);
6418 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
6419 __ addl($dst$$Register, $tmp$$Register);
6420 %}
6421 ins_pipe(ialu_reg);
6422 %}
6424 // Note: Long.bitCount(long) returns an int.
6425 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{
6426 predicate(UsePopCountInstruction);
6427 match(Set dst (PopCountL (LoadL mem)));
6428 effect(KILL cr, TEMP tmp, TEMP dst);
6430 format %{ "POPCNT $dst, $mem\n\t"
6431 "POPCNT $tmp, $mem+4\n\t"
6432 "ADD $dst, $tmp" %}
6433 ins_encode %{
6434 //__ popcntl($dst$$Register, $mem$$Address$$first);
6435 //__ popcntl($tmp$$Register, $mem$$Address$$second);
6436 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
6437 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
6438 __ addl($dst$$Register, $tmp$$Register);
6439 %}
6440 ins_pipe(ialu_reg);
6441 %}
6444 //----------Load/Store/Move Instructions---------------------------------------
6445 //----------Load Instructions--------------------------------------------------
6446 // Load Byte (8bit signed)
6447 instruct loadB(xRegI dst, memory mem) %{
6448 match(Set dst (LoadB mem));
6450 ins_cost(125);
6451 format %{ "MOVSX8 $dst,$mem\t# byte" %}
6453 ins_encode %{
6454 __ movsbl($dst$$Register, $mem$$Address);
6455 %}
6457 ins_pipe(ialu_reg_mem);
6458 %}
6460 // Load Byte (8bit signed) into Long Register
6461 instruct loadB2L(eRegL dst, memory mem) %{
6462 match(Set dst (ConvI2L (LoadB mem)));
6464 ins_cost(375);
6465 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
6466 "MOV $dst.hi,$dst.lo\n\t"
6467 "SAR $dst.hi,7" %}
6469 ins_encode %{
6470 __ movsbl($dst$$Register, $mem$$Address);
6471 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6472 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
6473 %}
6475 ins_pipe(ialu_reg_mem);
6476 %}
6478 // Load Unsigned Byte (8bit UNsigned)
6479 instruct loadUB(xRegI dst, memory mem) %{
6480 match(Set dst (LoadUB mem));
6482 ins_cost(125);
6483 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
6485 ins_encode %{
6486 __ movzbl($dst$$Register, $mem$$Address);
6487 %}
6489 ins_pipe(ialu_reg_mem);
6490 %}
6492 // Load Unsigned Byte (8 bit UNsigned) into Long Register
6493 instruct loadUB2L(eRegL dst, memory mem)
6494 %{
6495 match(Set dst (ConvI2L (LoadUB mem)));
6497 ins_cost(250);
6498 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
6499 "XOR $dst.hi,$dst.hi" %}
6501 ins_encode %{
6502 __ movzbl($dst$$Register, $mem$$Address);
6503 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6504 %}
6506 ins_pipe(ialu_reg_mem);
6507 %}
6509 // Load Short (16bit signed)
6510 instruct loadS(eRegI dst, memory mem) %{
6511 match(Set dst (LoadS mem));
6513 ins_cost(125);
6514 format %{ "MOVSX $dst,$mem\t# short" %}
6516 ins_encode %{
6517 __ movswl($dst$$Register, $mem$$Address);
6518 %}
6520 ins_pipe(ialu_reg_mem);
6521 %}
6523 // Load Short (16bit signed) into Long Register
6524 instruct loadS2L(eRegL dst, memory mem) %{
6525 match(Set dst (ConvI2L (LoadS mem)));
6527 ins_cost(375);
6528 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
6529 "MOV $dst.hi,$dst.lo\n\t"
6530 "SAR $dst.hi,15" %}
6532 ins_encode %{
6533 __ movswl($dst$$Register, $mem$$Address);
6534 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6535 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6536 %}
6538 ins_pipe(ialu_reg_mem);
6539 %}
6541 // Load Unsigned Short/Char (16bit unsigned)
6542 instruct loadUS(eRegI dst, memory mem) %{
6543 match(Set dst (LoadUS mem));
6545 ins_cost(125);
6546 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6548 ins_encode %{
6549 __ movzwl($dst$$Register, $mem$$Address);
6550 %}
6552 ins_pipe(ialu_reg_mem);
6553 %}
6555 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6556 instruct loadUS2L(eRegL dst, memory mem)
6557 %{
6558 match(Set dst (ConvI2L (LoadUS mem)));
6560 ins_cost(250);
6561 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6562 "XOR $dst.hi,$dst.hi" %}
6564 ins_encode %{
6565 __ movzwl($dst$$Register, $mem$$Address);
6566 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6567 %}
6569 ins_pipe(ialu_reg_mem);
6570 %}
6572 // Load Integer
6573 instruct loadI(eRegI dst, memory mem) %{
6574 match(Set dst (LoadI mem));
6576 ins_cost(125);
6577 format %{ "MOV $dst,$mem\t# int" %}
6579 ins_encode %{
6580 __ movl($dst$$Register, $mem$$Address);
6581 %}
6583 ins_pipe(ialu_reg_mem);
6584 %}
6586 // Load Integer into Long Register
6587 instruct loadI2L(eRegL dst, memory mem) %{
6588 match(Set dst (ConvI2L (LoadI mem)));
6590 ins_cost(375);
6591 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6592 "MOV $dst.hi,$dst.lo\n\t"
6593 "SAR $dst.hi,31" %}
6595 ins_encode %{
6596 __ movl($dst$$Register, $mem$$Address);
6597 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6598 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6599 %}
6601 ins_pipe(ialu_reg_mem);
6602 %}
6604 // Load Unsigned Integer into Long Register
6605 instruct loadUI2L(eRegL dst, memory mem) %{
6606 match(Set dst (LoadUI2L mem));
6608 ins_cost(250);
6609 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6610 "XOR $dst.hi,$dst.hi" %}
6612 ins_encode %{
6613 __ movl($dst$$Register, $mem$$Address);
6614 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6615 %}
6617 ins_pipe(ialu_reg_mem);
6618 %}
6620 // Load Long. Cannot clobber address while loading, so restrict address
6621 // register to ESI
6622 instruct loadL(eRegL dst, load_long_memory mem) %{
6623 predicate(!((LoadLNode*)n)->require_atomic_access());
6624 match(Set dst (LoadL mem));
6626 ins_cost(250);
6627 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6628 "MOV $dst.hi,$mem+4" %}
6630 ins_encode %{
6631 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6632 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6633 __ movl($dst$$Register, Amemlo);
6634 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6635 %}
6637 ins_pipe(ialu_reg_long_mem);
6638 %}
6640 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6641 // then store it down to the stack and reload on the int
6642 // side.
6643 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6644 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6645 match(Set dst (LoadL mem));
6647 ins_cost(200);
6648 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6649 "FISTp $dst" %}
6650 ins_encode(enc_loadL_volatile(mem,dst));
6651 ins_pipe( fpu_reg_mem );
6652 %}
6654 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6655 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6656 match(Set dst (LoadL mem));
6657 effect(TEMP tmp);
6658 ins_cost(180);
6659 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6660 "MOVSD $dst,$tmp" %}
6661 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6662 ins_pipe( pipe_slow );
6663 %}
6665 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6666 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6667 match(Set dst (LoadL mem));
6668 effect(TEMP tmp);
6669 ins_cost(160);
6670 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6671 "MOVD $dst.lo,$tmp\n\t"
6672 "PSRLQ $tmp,32\n\t"
6673 "MOVD $dst.hi,$tmp" %}
6674 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6675 ins_pipe( pipe_slow );
6676 %}
6678 // Load Range
6679 instruct loadRange(eRegI dst, memory mem) %{
6680 match(Set dst (LoadRange mem));
6682 ins_cost(125);
6683 format %{ "MOV $dst,$mem" %}
6684 opcode(0x8B);
6685 ins_encode( OpcP, RegMem(dst,mem));
6686 ins_pipe( ialu_reg_mem );
6687 %}
6690 // Load Pointer
6691 instruct loadP(eRegP dst, memory mem) %{
6692 match(Set dst (LoadP mem));
6694 ins_cost(125);
6695 format %{ "MOV $dst,$mem" %}
6696 opcode(0x8B);
6697 ins_encode( OpcP, RegMem(dst,mem));
6698 ins_pipe( ialu_reg_mem );
6699 %}
6701 // Load Klass Pointer
6702 instruct loadKlass(eRegP dst, memory mem) %{
6703 match(Set dst (LoadKlass mem));
6705 ins_cost(125);
6706 format %{ "MOV $dst,$mem" %}
6707 opcode(0x8B);
6708 ins_encode( OpcP, RegMem(dst,mem));
6709 ins_pipe( ialu_reg_mem );
6710 %}
6712 // Load Double
6713 instruct loadD(regD dst, memory mem) %{
6714 predicate(UseSSE<=1);
6715 match(Set dst (LoadD mem));
6717 ins_cost(150);
6718 format %{ "FLD_D ST,$mem\n\t"
6719 "FSTP $dst" %}
6720 opcode(0xDD); /* DD /0 */
6721 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6722 Pop_Reg_D(dst) );
6723 ins_pipe( fpu_reg_mem );
6724 %}
6726 // Load Double to XMM
6727 instruct loadXD(regXD dst, memory mem) %{
6728 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6729 match(Set dst (LoadD mem));
6730 ins_cost(145);
6731 format %{ "MOVSD $dst,$mem" %}
6732 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6733 ins_pipe( pipe_slow );
6734 %}
6736 instruct loadXD_partial(regXD dst, memory mem) %{
6737 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6738 match(Set dst (LoadD mem));
6739 ins_cost(145);
6740 format %{ "MOVLPD $dst,$mem" %}
6741 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6742 ins_pipe( pipe_slow );
6743 %}
6745 // Load to XMM register (single-precision floating point)
6746 // MOVSS instruction
6747 instruct loadX(regX dst, memory mem) %{
6748 predicate(UseSSE>=1);
6749 match(Set dst (LoadF mem));
6750 ins_cost(145);
6751 format %{ "MOVSS $dst,$mem" %}
6752 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6753 ins_pipe( pipe_slow );
6754 %}
6756 // Load Float
6757 instruct loadF(regF dst, memory mem) %{
6758 predicate(UseSSE==0);
6759 match(Set dst (LoadF mem));
6761 ins_cost(150);
6762 format %{ "FLD_S ST,$mem\n\t"
6763 "FSTP $dst" %}
6764 opcode(0xD9); /* D9 /0 */
6765 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6766 Pop_Reg_F(dst) );
6767 ins_pipe( fpu_reg_mem );
6768 %}
6770 // Load Aligned Packed Byte to XMM register
6771 instruct loadA8B(regXD dst, memory mem) %{
6772 predicate(UseSSE>=1);
6773 match(Set dst (Load8B mem));
6774 ins_cost(125);
6775 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6776 ins_encode( movq_ld(dst, mem));
6777 ins_pipe( pipe_slow );
6778 %}
6780 // Load Aligned Packed Short to XMM register
6781 instruct loadA4S(regXD dst, memory mem) %{
6782 predicate(UseSSE>=1);
6783 match(Set dst (Load4S mem));
6784 ins_cost(125);
6785 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6786 ins_encode( movq_ld(dst, mem));
6787 ins_pipe( pipe_slow );
6788 %}
6790 // Load Aligned Packed Char to XMM register
6791 instruct loadA4C(regXD dst, memory mem) %{
6792 predicate(UseSSE>=1);
6793 match(Set dst (Load4C mem));
6794 ins_cost(125);
6795 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6796 ins_encode( movq_ld(dst, mem));
6797 ins_pipe( pipe_slow );
6798 %}
6800 // Load Aligned Packed Integer to XMM register
6801 instruct load2IU(regXD dst, memory mem) %{
6802 predicate(UseSSE>=1);
6803 match(Set dst (Load2I mem));
6804 ins_cost(125);
6805 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6806 ins_encode( movq_ld(dst, mem));
6807 ins_pipe( pipe_slow );
6808 %}
6810 // Load Aligned Packed Single to XMM
6811 instruct loadA2F(regXD dst, memory mem) %{
6812 predicate(UseSSE>=1);
6813 match(Set dst (Load2F mem));
6814 ins_cost(145);
6815 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6816 ins_encode( movq_ld(dst, mem));
6817 ins_pipe( pipe_slow );
6818 %}
6820 // Load Effective Address
6821 instruct leaP8(eRegP dst, indOffset8 mem) %{
6822 match(Set dst mem);
6824 ins_cost(110);
6825 format %{ "LEA $dst,$mem" %}
6826 opcode(0x8D);
6827 ins_encode( OpcP, RegMem(dst,mem));
6828 ins_pipe( ialu_reg_reg_fat );
6829 %}
6831 instruct leaP32(eRegP dst, indOffset32 mem) %{
6832 match(Set dst mem);
6834 ins_cost(110);
6835 format %{ "LEA $dst,$mem" %}
6836 opcode(0x8D);
6837 ins_encode( OpcP, RegMem(dst,mem));
6838 ins_pipe( ialu_reg_reg_fat );
6839 %}
6841 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6842 match(Set dst mem);
6844 ins_cost(110);
6845 format %{ "LEA $dst,$mem" %}
6846 opcode(0x8D);
6847 ins_encode( OpcP, RegMem(dst,mem));
6848 ins_pipe( ialu_reg_reg_fat );
6849 %}
6851 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6852 match(Set dst mem);
6854 ins_cost(110);
6855 format %{ "LEA $dst,$mem" %}
6856 opcode(0x8D);
6857 ins_encode( OpcP, RegMem(dst,mem));
6858 ins_pipe( ialu_reg_reg_fat );
6859 %}
6861 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6862 match(Set dst mem);
6864 ins_cost(110);
6865 format %{ "LEA $dst,$mem" %}
6866 opcode(0x8D);
6867 ins_encode( OpcP, RegMem(dst,mem));
6868 ins_pipe( ialu_reg_reg_fat );
6869 %}
6871 // Load Constant
6872 instruct loadConI(eRegI dst, immI src) %{
6873 match(Set dst src);
6875 format %{ "MOV $dst,$src" %}
6876 ins_encode( LdImmI(dst, src) );
6877 ins_pipe( ialu_reg_fat );
6878 %}
6880 // Load Constant zero
6881 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6882 match(Set dst src);
6883 effect(KILL cr);
6885 ins_cost(50);
6886 format %{ "XOR $dst,$dst" %}
6887 opcode(0x33); /* + rd */
6888 ins_encode( OpcP, RegReg( dst, dst ) );
6889 ins_pipe( ialu_reg );
6890 %}
6892 instruct loadConP(eRegP dst, immP src) %{
6893 match(Set dst src);
6895 format %{ "MOV $dst,$src" %}
6896 opcode(0xB8); /* + rd */
6897 ins_encode( LdImmP(dst, src) );
6898 ins_pipe( ialu_reg_fat );
6899 %}
6901 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6902 match(Set dst src);
6903 effect(KILL cr);
6904 ins_cost(200);
6905 format %{ "MOV $dst.lo,$src.lo\n\t"
6906 "MOV $dst.hi,$src.hi" %}
6907 opcode(0xB8);
6908 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6909 ins_pipe( ialu_reg_long_fat );
6910 %}
6912 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6913 match(Set dst src);
6914 effect(KILL cr);
6915 ins_cost(150);
6916 format %{ "XOR $dst.lo,$dst.lo\n\t"
6917 "XOR $dst.hi,$dst.hi" %}
6918 opcode(0x33,0x33);
6919 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6920 ins_pipe( ialu_reg_long );
6921 %}
6923 // The instruction usage is guarded by predicate in operand immF().
6924 instruct loadConF(regF dst, immF src) %{
6925 match(Set dst src);
6926 ins_cost(125);
6928 format %{ "FLD_S ST,$src\n\t"
6929 "FSTP $dst" %}
6930 opcode(0xD9, 0x00); /* D9 /0 */
6931 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
6932 ins_pipe( fpu_reg_con );
6933 %}
6935 // The instruction usage is guarded by predicate in operand immXF().
6936 instruct loadConX(regX dst, immXF con) %{
6937 match(Set dst con);
6938 ins_cost(125);
6939 format %{ "MOVSS $dst,[$con]" %}
6940 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
6941 ins_pipe( pipe_slow );
6942 %}
6944 // The instruction usage is guarded by predicate in operand immXF0().
6945 instruct loadConX0(regX dst, immXF0 src) %{
6946 match(Set dst src);
6947 ins_cost(100);
6948 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6949 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6950 ins_pipe( pipe_slow );
6951 %}
6953 // The instruction usage is guarded by predicate in operand immD().
6954 instruct loadConD(regD dst, immD src) %{
6955 match(Set dst src);
6956 ins_cost(125);
6958 format %{ "FLD_D ST,$src\n\t"
6959 "FSTP $dst" %}
6960 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
6961 ins_pipe( fpu_reg_con );
6962 %}
6964 // The instruction usage is guarded by predicate in operand immXD().
6965 instruct loadConXD(regXD dst, immXD con) %{
6966 match(Set dst con);
6967 ins_cost(125);
6968 format %{ "MOVSD $dst,[$con]" %}
6969 ins_encode(load_conXD(dst, con));
6970 ins_pipe( pipe_slow );
6971 %}
6973 // The instruction usage is guarded by predicate in operand immXD0().
6974 instruct loadConXD0(regXD dst, immXD0 src) %{
6975 match(Set dst src);
6976 ins_cost(100);
6977 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6978 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6979 ins_pipe( pipe_slow );
6980 %}
6982 // Load Stack Slot
6983 instruct loadSSI(eRegI dst, stackSlotI src) %{
6984 match(Set dst src);
6985 ins_cost(125);
6987 format %{ "MOV $dst,$src" %}
6988 opcode(0x8B);
6989 ins_encode( OpcP, RegMem(dst,src));
6990 ins_pipe( ialu_reg_mem );
6991 %}
6993 instruct loadSSL(eRegL dst, stackSlotL src) %{
6994 match(Set dst src);
6996 ins_cost(200);
6997 format %{ "MOV $dst,$src.lo\n\t"
6998 "MOV $dst+4,$src.hi" %}
6999 opcode(0x8B, 0x8B);
7000 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7001 ins_pipe( ialu_mem_long_reg );
7002 %}
7004 // Load Stack Slot
7005 instruct loadSSP(eRegP dst, stackSlotP src) %{
7006 match(Set dst src);
7007 ins_cost(125);
7009 format %{ "MOV $dst,$src" %}
7010 opcode(0x8B);
7011 ins_encode( OpcP, RegMem(dst,src));
7012 ins_pipe( ialu_reg_mem );
7013 %}
7015 // Load Stack Slot
7016 instruct loadSSF(regF dst, stackSlotF src) %{
7017 match(Set dst src);
7018 ins_cost(125);
7020 format %{ "FLD_S $src\n\t"
7021 "FSTP $dst" %}
7022 opcode(0xD9); /* D9 /0, FLD m32real */
7023 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7024 Pop_Reg_F(dst) );
7025 ins_pipe( fpu_reg_mem );
7026 %}
7028 // Load Stack Slot
7029 instruct loadSSD(regD dst, stackSlotD src) %{
7030 match(Set dst src);
7031 ins_cost(125);
7033 format %{ "FLD_D $src\n\t"
7034 "FSTP $dst" %}
7035 opcode(0xDD); /* DD /0, FLD m64real */
7036 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7037 Pop_Reg_D(dst) );
7038 ins_pipe( fpu_reg_mem );
7039 %}
7041 // Prefetch instructions.
7042 // Must be safe to execute with invalid address (cannot fault).
7044 instruct prefetchr0( memory mem ) %{
7045 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7046 match(PrefetchRead mem);
7047 ins_cost(0);
7048 size(0);
7049 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7050 ins_encode();
7051 ins_pipe(empty);
7052 %}
7054 instruct prefetchr( memory mem ) %{
7055 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7056 match(PrefetchRead mem);
7057 ins_cost(100);
7059 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7060 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7061 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7062 ins_pipe(ialu_mem);
7063 %}
7065 instruct prefetchrNTA( memory mem ) %{
7066 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7067 match(PrefetchRead mem);
7068 ins_cost(100);
7070 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7071 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7072 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7073 ins_pipe(ialu_mem);
7074 %}
7076 instruct prefetchrT0( memory mem ) %{
7077 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7078 match(PrefetchRead mem);
7079 ins_cost(100);
7081 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7082 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7083 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7084 ins_pipe(ialu_mem);
7085 %}
7087 instruct prefetchrT2( memory mem ) %{
7088 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7089 match(PrefetchRead mem);
7090 ins_cost(100);
7092 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7093 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7094 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7095 ins_pipe(ialu_mem);
7096 %}
7098 instruct prefetchw0( memory mem ) %{
7099 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7100 match(PrefetchWrite mem);
7101 ins_cost(0);
7102 size(0);
7103 format %{ "Prefetch (non-SSE is empty encoding)" %}
7104 ins_encode();
7105 ins_pipe(empty);
7106 %}
7108 instruct prefetchw( memory mem ) %{
7109 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7110 match( PrefetchWrite mem );
7111 ins_cost(100);
7113 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7114 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7115 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7116 ins_pipe(ialu_mem);
7117 %}
7119 instruct prefetchwNTA( memory mem ) %{
7120 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7121 match(PrefetchWrite mem);
7122 ins_cost(100);
7124 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7125 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7126 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7127 ins_pipe(ialu_mem);
7128 %}
7130 instruct prefetchwT0( memory mem ) %{
7131 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7132 match(PrefetchWrite mem);
7133 ins_cost(100);
7135 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7136 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7137 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7138 ins_pipe(ialu_mem);
7139 %}
7141 instruct prefetchwT2( memory mem ) %{
7142 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7143 match(PrefetchWrite mem);
7144 ins_cost(100);
7146 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7147 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7148 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7149 ins_pipe(ialu_mem);
7150 %}
7152 //----------Store Instructions-------------------------------------------------
7154 // Store Byte
7155 instruct storeB(memory mem, xRegI src) %{
7156 match(Set mem (StoreB mem src));
7158 ins_cost(125);
7159 format %{ "MOV8 $mem,$src" %}
7160 opcode(0x88);
7161 ins_encode( OpcP, RegMem( src, mem ) );
7162 ins_pipe( ialu_mem_reg );
7163 %}
7165 // Store Char/Short
7166 instruct storeC(memory mem, eRegI src) %{
7167 match(Set mem (StoreC mem src));
7169 ins_cost(125);
7170 format %{ "MOV16 $mem,$src" %}
7171 opcode(0x89, 0x66);
7172 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7173 ins_pipe( ialu_mem_reg );
7174 %}
7176 // Store Integer
7177 instruct storeI(memory mem, eRegI src) %{
7178 match(Set mem (StoreI mem src));
7180 ins_cost(125);
7181 format %{ "MOV $mem,$src" %}
7182 opcode(0x89);
7183 ins_encode( OpcP, RegMem( src, mem ) );
7184 ins_pipe( ialu_mem_reg );
7185 %}
7187 // Store Long
7188 instruct storeL(long_memory mem, eRegL src) %{
7189 predicate(!((StoreLNode*)n)->require_atomic_access());
7190 match(Set mem (StoreL mem src));
7192 ins_cost(200);
7193 format %{ "MOV $mem,$src.lo\n\t"
7194 "MOV $mem+4,$src.hi" %}
7195 opcode(0x89, 0x89);
7196 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7197 ins_pipe( ialu_mem_long_reg );
7198 %}
7200 // Volatile Store Long. Must be atomic, so move it into
7201 // the FP TOS and then do a 64-bit FIST. Has to probe the
7202 // target address before the store (for null-ptr checks)
7203 // so the memory operand is used twice in the encoding.
7204 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7205 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7206 match(Set mem (StoreL mem src));
7207 effect( KILL cr );
7208 ins_cost(400);
7209 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7210 "FILD $src\n\t"
7211 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7212 opcode(0x3B);
7213 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7214 ins_pipe( fpu_reg_mem );
7215 %}
7217 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7218 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7219 match(Set mem (StoreL mem src));
7220 effect( TEMP tmp, KILL cr );
7221 ins_cost(380);
7222 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7223 "MOVSD $tmp,$src\n\t"
7224 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7225 opcode(0x3B);
7226 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7227 ins_pipe( pipe_slow );
7228 %}
7230 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7231 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7232 match(Set mem (StoreL mem src));
7233 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7234 ins_cost(360);
7235 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7236 "MOVD $tmp,$src.lo\n\t"
7237 "MOVD $tmp2,$src.hi\n\t"
7238 "PUNPCKLDQ $tmp,$tmp2\n\t"
7239 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7240 opcode(0x3B);
7241 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7242 ins_pipe( pipe_slow );
7243 %}
7245 // Store Pointer; for storing unknown oops and raw pointers
7246 instruct storeP(memory mem, anyRegP src) %{
7247 match(Set mem (StoreP mem src));
7249 ins_cost(125);
7250 format %{ "MOV $mem,$src" %}
7251 opcode(0x89);
7252 ins_encode( OpcP, RegMem( src, mem ) );
7253 ins_pipe( ialu_mem_reg );
7254 %}
7256 // Store Integer Immediate
7257 instruct storeImmI(memory mem, immI src) %{
7258 match(Set mem (StoreI mem src));
7260 ins_cost(150);
7261 format %{ "MOV $mem,$src" %}
7262 opcode(0xC7); /* C7 /0 */
7263 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7264 ins_pipe( ialu_mem_imm );
7265 %}
7267 // Store Short/Char Immediate
7268 instruct storeImmI16(memory mem, immI16 src) %{
7269 predicate(UseStoreImmI16);
7270 match(Set mem (StoreC mem src));
7272 ins_cost(150);
7273 format %{ "MOV16 $mem,$src" %}
7274 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7275 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7276 ins_pipe( ialu_mem_imm );
7277 %}
7279 // Store Pointer Immediate; null pointers or constant oops that do not
7280 // need card-mark barriers.
7281 instruct storeImmP(memory mem, immP src) %{
7282 match(Set mem (StoreP mem src));
7284 ins_cost(150);
7285 format %{ "MOV $mem,$src" %}
7286 opcode(0xC7); /* C7 /0 */
7287 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7288 ins_pipe( ialu_mem_imm );
7289 %}
7291 // Store Byte Immediate
7292 instruct storeImmB(memory mem, immI8 src) %{
7293 match(Set mem (StoreB mem src));
7295 ins_cost(150);
7296 format %{ "MOV8 $mem,$src" %}
7297 opcode(0xC6); /* C6 /0 */
7298 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7299 ins_pipe( ialu_mem_imm );
7300 %}
7302 // Store Aligned Packed Byte XMM register to memory
7303 instruct storeA8B(memory mem, regXD src) %{
7304 predicate(UseSSE>=1);
7305 match(Set mem (Store8B mem src));
7306 ins_cost(145);
7307 format %{ "MOVQ $mem,$src\t! packed8B" %}
7308 ins_encode( movq_st(mem, src));
7309 ins_pipe( pipe_slow );
7310 %}
7312 // Store Aligned Packed Char/Short XMM register to memory
7313 instruct storeA4C(memory mem, regXD src) %{
7314 predicate(UseSSE>=1);
7315 match(Set mem (Store4C mem src));
7316 ins_cost(145);
7317 format %{ "MOVQ $mem,$src\t! packed4C" %}
7318 ins_encode( movq_st(mem, src));
7319 ins_pipe( pipe_slow );
7320 %}
7322 // Store Aligned Packed Integer XMM register to memory
7323 instruct storeA2I(memory mem, regXD src) %{
7324 predicate(UseSSE>=1);
7325 match(Set mem (Store2I mem src));
7326 ins_cost(145);
7327 format %{ "MOVQ $mem,$src\t! packed2I" %}
7328 ins_encode( movq_st(mem, src));
7329 ins_pipe( pipe_slow );
7330 %}
7332 // Store CMS card-mark Immediate
7333 instruct storeImmCM(memory mem, immI8 src) %{
7334 match(Set mem (StoreCM mem src));
7336 ins_cost(150);
7337 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7338 opcode(0xC6); /* C6 /0 */
7339 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7340 ins_pipe( ialu_mem_imm );
7341 %}
7343 // Store Double
7344 instruct storeD( memory mem, regDPR1 src) %{
7345 predicate(UseSSE<=1);
7346 match(Set mem (StoreD mem src));
7348 ins_cost(100);
7349 format %{ "FST_D $mem,$src" %}
7350 opcode(0xDD); /* DD /2 */
7351 ins_encode( enc_FP_store(mem,src) );
7352 ins_pipe( fpu_mem_reg );
7353 %}
7355 // Store double does rounding on x86
7356 instruct storeD_rounded( memory mem, regDPR1 src) %{
7357 predicate(UseSSE<=1);
7358 match(Set mem (StoreD mem (RoundDouble src)));
7360 ins_cost(100);
7361 format %{ "FST_D $mem,$src\t# round" %}
7362 opcode(0xDD); /* DD /2 */
7363 ins_encode( enc_FP_store(mem,src) );
7364 ins_pipe( fpu_mem_reg );
7365 %}
7367 // Store XMM register to memory (double-precision floating points)
7368 // MOVSD instruction
7369 instruct storeXD(memory mem, regXD src) %{
7370 predicate(UseSSE>=2);
7371 match(Set mem (StoreD mem src));
7372 ins_cost(95);
7373 format %{ "MOVSD $mem,$src" %}
7374 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7375 ins_pipe( pipe_slow );
7376 %}
7378 // Store XMM register to memory (single-precision floating point)
7379 // MOVSS instruction
7380 instruct storeX(memory mem, regX src) %{
7381 predicate(UseSSE>=1);
7382 match(Set mem (StoreF mem src));
7383 ins_cost(95);
7384 format %{ "MOVSS $mem,$src" %}
7385 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7386 ins_pipe( pipe_slow );
7387 %}
7389 // Store Aligned Packed Single Float XMM register to memory
7390 instruct storeA2F(memory mem, regXD src) %{
7391 predicate(UseSSE>=1);
7392 match(Set mem (Store2F mem src));
7393 ins_cost(145);
7394 format %{ "MOVQ $mem,$src\t! packed2F" %}
7395 ins_encode( movq_st(mem, src));
7396 ins_pipe( pipe_slow );
7397 %}
7399 // Store Float
7400 instruct storeF( memory mem, regFPR1 src) %{
7401 predicate(UseSSE==0);
7402 match(Set mem (StoreF mem src));
7404 ins_cost(100);
7405 format %{ "FST_S $mem,$src" %}
7406 opcode(0xD9); /* D9 /2 */
7407 ins_encode( enc_FP_store(mem,src) );
7408 ins_pipe( fpu_mem_reg );
7409 %}
7411 // Store Float does rounding on x86
7412 instruct storeF_rounded( memory mem, regFPR1 src) %{
7413 predicate(UseSSE==0);
7414 match(Set mem (StoreF mem (RoundFloat src)));
7416 ins_cost(100);
7417 format %{ "FST_S $mem,$src\t# round" %}
7418 opcode(0xD9); /* D9 /2 */
7419 ins_encode( enc_FP_store(mem,src) );
7420 ins_pipe( fpu_mem_reg );
7421 %}
7423 // Store Float does rounding on x86
7424 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7425 predicate(UseSSE<=1);
7426 match(Set mem (StoreF mem (ConvD2F src)));
7428 ins_cost(100);
7429 format %{ "FST_S $mem,$src\t# D-round" %}
7430 opcode(0xD9); /* D9 /2 */
7431 ins_encode( enc_FP_store(mem,src) );
7432 ins_pipe( fpu_mem_reg );
7433 %}
7435 // Store immediate Float value (it is faster than store from FPU register)
7436 // The instruction usage is guarded by predicate in operand immF().
7437 instruct storeF_imm( memory mem, immF src) %{
7438 match(Set mem (StoreF mem src));
7440 ins_cost(50);
7441 format %{ "MOV $mem,$src\t# store float" %}
7442 opcode(0xC7); /* C7 /0 */
7443 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7444 ins_pipe( ialu_mem_imm );
7445 %}
7447 // Store immediate Float value (it is faster than store from XMM register)
7448 // The instruction usage is guarded by predicate in operand immXF().
7449 instruct storeX_imm( memory mem, immXF src) %{
7450 match(Set mem (StoreF mem src));
7452 ins_cost(50);
7453 format %{ "MOV $mem,$src\t# store float" %}
7454 opcode(0xC7); /* C7 /0 */
7455 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7456 ins_pipe( ialu_mem_imm );
7457 %}
7459 // Store Integer to stack slot
7460 instruct storeSSI(stackSlotI dst, eRegI src) %{
7461 match(Set dst src);
7463 ins_cost(100);
7464 format %{ "MOV $dst,$src" %}
7465 opcode(0x89);
7466 ins_encode( OpcPRegSS( dst, src ) );
7467 ins_pipe( ialu_mem_reg );
7468 %}
7470 // Store Integer to stack slot
7471 instruct storeSSP(stackSlotP dst, eRegP src) %{
7472 match(Set dst src);
7474 ins_cost(100);
7475 format %{ "MOV $dst,$src" %}
7476 opcode(0x89);
7477 ins_encode( OpcPRegSS( dst, src ) );
7478 ins_pipe( ialu_mem_reg );
7479 %}
7481 // Store Long to stack slot
7482 instruct storeSSL(stackSlotL dst, eRegL src) %{
7483 match(Set dst src);
7485 ins_cost(200);
7486 format %{ "MOV $dst,$src.lo\n\t"
7487 "MOV $dst+4,$src.hi" %}
7488 opcode(0x89, 0x89);
7489 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7490 ins_pipe( ialu_mem_long_reg );
7491 %}
7493 //----------MemBar Instructions-----------------------------------------------
7494 // Memory barrier flavors
7496 instruct membar_acquire() %{
7497 match(MemBarAcquire);
7498 ins_cost(400);
7500 size(0);
7501 format %{ "MEMBAR-acquire" %}
7502 ins_encode( enc_membar_acquire );
7503 ins_pipe(pipe_slow);
7504 %}
7506 instruct membar_acquire_lock() %{
7507 match(MemBarAcquire);
7508 predicate(Matcher::prior_fast_lock(n));
7509 ins_cost(0);
7511 size(0);
7512 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7513 ins_encode( );
7514 ins_pipe(empty);
7515 %}
7517 instruct membar_release() %{
7518 match(MemBarRelease);
7519 ins_cost(400);
7521 size(0);
7522 format %{ "MEMBAR-release" %}
7523 ins_encode( enc_membar_release );
7524 ins_pipe(pipe_slow);
7525 %}
7527 instruct membar_release_lock() %{
7528 match(MemBarRelease);
7529 predicate(Matcher::post_fast_unlock(n));
7530 ins_cost(0);
7532 size(0);
7533 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7534 ins_encode( );
7535 ins_pipe(empty);
7536 %}
7538 instruct membar_volatile() %{
7539 match(MemBarVolatile);
7540 ins_cost(400);
7542 format %{ "MEMBAR-volatile" %}
7543 ins_encode( enc_membar_volatile );
7544 ins_pipe(pipe_slow);
7545 %}
7547 instruct unnecessary_membar_volatile() %{
7548 match(MemBarVolatile);
7549 predicate(Matcher::post_store_load_barrier(n));
7550 ins_cost(0);
7552 size(0);
7553 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7554 ins_encode( );
7555 ins_pipe(empty);
7556 %}
7558 //----------Move Instructions--------------------------------------------------
7559 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7560 match(Set dst (CastX2P src));
7561 format %{ "# X2P $dst, $src" %}
7562 ins_encode( /*empty encoding*/ );
7563 ins_cost(0);
7564 ins_pipe(empty);
7565 %}
7567 instruct castP2X(eRegI dst, eRegP src ) %{
7568 match(Set dst (CastP2X src));
7569 ins_cost(50);
7570 format %{ "MOV $dst, $src\t# CastP2X" %}
7571 ins_encode( enc_Copy( dst, src) );
7572 ins_pipe( ialu_reg_reg );
7573 %}
7575 //----------Conditional Move---------------------------------------------------
7576 // Conditional move
7577 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7578 predicate(VM_Version::supports_cmov() );
7579 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7580 ins_cost(200);
7581 format %{ "CMOV$cop $dst,$src" %}
7582 opcode(0x0F,0x40);
7583 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7584 ins_pipe( pipe_cmov_reg );
7585 %}
7587 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7588 predicate(VM_Version::supports_cmov() );
7589 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7590 ins_cost(200);
7591 format %{ "CMOV$cop $dst,$src" %}
7592 opcode(0x0F,0x40);
7593 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7594 ins_pipe( pipe_cmov_reg );
7595 %}
7597 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7598 predicate(VM_Version::supports_cmov() );
7599 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7600 ins_cost(200);
7601 expand %{
7602 cmovI_regU(cop, cr, dst, src);
7603 %}
7604 %}
7606 // Conditional move
7607 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7608 predicate(VM_Version::supports_cmov() );
7609 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7610 ins_cost(250);
7611 format %{ "CMOV$cop $dst,$src" %}
7612 opcode(0x0F,0x40);
7613 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7614 ins_pipe( pipe_cmov_mem );
7615 %}
7617 // Conditional move
7618 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7619 predicate(VM_Version::supports_cmov() );
7620 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7621 ins_cost(250);
7622 format %{ "CMOV$cop $dst,$src" %}
7623 opcode(0x0F,0x40);
7624 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7625 ins_pipe( pipe_cmov_mem );
7626 %}
7628 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7629 predicate(VM_Version::supports_cmov() );
7630 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7631 ins_cost(250);
7632 expand %{
7633 cmovI_memU(cop, cr, dst, src);
7634 %}
7635 %}
7637 // Conditional move
7638 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7639 predicate(VM_Version::supports_cmov() );
7640 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7641 ins_cost(200);
7642 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7643 opcode(0x0F,0x40);
7644 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7645 ins_pipe( pipe_cmov_reg );
7646 %}
7648 // Conditional move (non-P6 version)
7649 // Note: a CMoveP is generated for stubs and native wrappers
7650 // regardless of whether we are on a P6, so we
7651 // emulate a cmov here
7652 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7653 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7654 ins_cost(300);
7655 format %{ "Jn$cop skip\n\t"
7656 "MOV $dst,$src\t# pointer\n"
7657 "skip:" %}
7658 opcode(0x8b);
7659 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7660 ins_pipe( pipe_cmov_reg );
7661 %}
7663 // Conditional move
7664 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7665 predicate(VM_Version::supports_cmov() );
7666 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7667 ins_cost(200);
7668 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7669 opcode(0x0F,0x40);
7670 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7671 ins_pipe( pipe_cmov_reg );
7672 %}
7674 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7675 predicate(VM_Version::supports_cmov() );
7676 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7677 ins_cost(200);
7678 expand %{
7679 cmovP_regU(cop, cr, dst, src);
7680 %}
7681 %}
7683 // DISABLED: Requires the ADLC to emit a bottom_type call that
7684 // correctly meets the two pointer arguments; one is an incoming
7685 // register but the other is a memory operand. ALSO appears to
7686 // be buggy with implicit null checks.
7687 //
7688 //// Conditional move
7689 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7690 // predicate(VM_Version::supports_cmov() );
7691 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7692 // ins_cost(250);
7693 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7694 // opcode(0x0F,0x40);
7695 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7696 // ins_pipe( pipe_cmov_mem );
7697 //%}
7698 //
7699 //// Conditional move
7700 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7701 // predicate(VM_Version::supports_cmov() );
7702 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7703 // ins_cost(250);
7704 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7705 // opcode(0x0F,0x40);
7706 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7707 // ins_pipe( pipe_cmov_mem );
7708 //%}
7710 // Conditional move
7711 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7712 predicate(UseSSE<=1);
7713 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7714 ins_cost(200);
7715 format %{ "FCMOV$cop $dst,$src\t# double" %}
7716 opcode(0xDA);
7717 ins_encode( enc_cmov_d(cop,src) );
7718 ins_pipe( pipe_cmovD_reg );
7719 %}
7721 // Conditional move
7722 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7723 predicate(UseSSE==0);
7724 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7725 ins_cost(200);
7726 format %{ "FCMOV$cop $dst,$src\t# float" %}
7727 opcode(0xDA);
7728 ins_encode( enc_cmov_d(cop,src) );
7729 ins_pipe( pipe_cmovD_reg );
7730 %}
7732 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7733 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7734 predicate(UseSSE<=1);
7735 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7736 ins_cost(200);
7737 format %{ "Jn$cop skip\n\t"
7738 "MOV $dst,$src\t# double\n"
7739 "skip:" %}
7740 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7741 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7742 ins_pipe( pipe_cmovD_reg );
7743 %}
7745 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7746 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7747 predicate(UseSSE==0);
7748 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7749 ins_cost(200);
7750 format %{ "Jn$cop skip\n\t"
7751 "MOV $dst,$src\t# float\n"
7752 "skip:" %}
7753 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7754 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7755 ins_pipe( pipe_cmovD_reg );
7756 %}
7758 // No CMOVE with SSE/SSE2
7759 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7760 predicate (UseSSE>=1);
7761 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7762 ins_cost(200);
7763 format %{ "Jn$cop skip\n\t"
7764 "MOVSS $dst,$src\t# float\n"
7765 "skip:" %}
7766 ins_encode %{
7767 Label skip;
7768 // Invert sense of branch from sense of CMOV
7769 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7770 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7771 __ bind(skip);
7772 %}
7773 ins_pipe( pipe_slow );
7774 %}
7776 // No CMOVE with SSE/SSE2
7777 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7778 predicate (UseSSE>=2);
7779 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7780 ins_cost(200);
7781 format %{ "Jn$cop skip\n\t"
7782 "MOVSD $dst,$src\t# float\n"
7783 "skip:" %}
7784 ins_encode %{
7785 Label skip;
7786 // Invert sense of branch from sense of CMOV
7787 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7788 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7789 __ bind(skip);
7790 %}
7791 ins_pipe( pipe_slow );
7792 %}
7794 // unsigned version
7795 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7796 predicate (UseSSE>=1);
7797 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7798 ins_cost(200);
7799 format %{ "Jn$cop skip\n\t"
7800 "MOVSS $dst,$src\t# float\n"
7801 "skip:" %}
7802 ins_encode %{
7803 Label skip;
7804 // Invert sense of branch from sense of CMOV
7805 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7806 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7807 __ bind(skip);
7808 %}
7809 ins_pipe( pipe_slow );
7810 %}
7812 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
7813 predicate (UseSSE>=1);
7814 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7815 ins_cost(200);
7816 expand %{
7817 fcmovX_regU(cop, cr, dst, src);
7818 %}
7819 %}
7821 // unsigned version
7822 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7823 predicate (UseSSE>=2);
7824 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7825 ins_cost(200);
7826 format %{ "Jn$cop skip\n\t"
7827 "MOVSD $dst,$src\t# float\n"
7828 "skip:" %}
7829 ins_encode %{
7830 Label skip;
7831 // Invert sense of branch from sense of CMOV
7832 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7833 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7834 __ bind(skip);
7835 %}
7836 ins_pipe( pipe_slow );
7837 %}
7839 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
7840 predicate (UseSSE>=2);
7841 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7842 ins_cost(200);
7843 expand %{
7844 fcmovXD_regU(cop, cr, dst, src);
7845 %}
7846 %}
7848 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7849 predicate(VM_Version::supports_cmov() );
7850 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7851 ins_cost(200);
7852 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7853 "CMOV$cop $dst.hi,$src.hi" %}
7854 opcode(0x0F,0x40);
7855 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7856 ins_pipe( pipe_cmov_reg_long );
7857 %}
7859 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7860 predicate(VM_Version::supports_cmov() );
7861 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7862 ins_cost(200);
7863 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7864 "CMOV$cop $dst.hi,$src.hi" %}
7865 opcode(0x0F,0x40);
7866 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7867 ins_pipe( pipe_cmov_reg_long );
7868 %}
7870 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7871 predicate(VM_Version::supports_cmov() );
7872 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7873 ins_cost(200);
7874 expand %{
7875 cmovL_regU(cop, cr, dst, src);
7876 %}
7877 %}
7879 //----------Arithmetic Instructions--------------------------------------------
7880 //----------Addition Instructions----------------------------------------------
7881 // Integer Addition Instructions
7882 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7883 match(Set dst (AddI dst src));
7884 effect(KILL cr);
7886 size(2);
7887 format %{ "ADD $dst,$src" %}
7888 opcode(0x03);
7889 ins_encode( OpcP, RegReg( dst, src) );
7890 ins_pipe( ialu_reg_reg );
7891 %}
7893 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7894 match(Set dst (AddI dst src));
7895 effect(KILL cr);
7897 format %{ "ADD $dst,$src" %}
7898 opcode(0x81, 0x00); /* /0 id */
7899 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7900 ins_pipe( ialu_reg );
7901 %}
7903 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7904 predicate(UseIncDec);
7905 match(Set dst (AddI dst src));
7906 effect(KILL cr);
7908 size(1);
7909 format %{ "INC $dst" %}
7910 opcode(0x40); /* */
7911 ins_encode( Opc_plus( primary, dst ) );
7912 ins_pipe( ialu_reg );
7913 %}
7915 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7916 match(Set dst (AddI src0 src1));
7917 ins_cost(110);
7919 format %{ "LEA $dst,[$src0 + $src1]" %}
7920 opcode(0x8D); /* 0x8D /r */
7921 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7922 ins_pipe( ialu_reg_reg );
7923 %}
7925 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7926 match(Set dst (AddP src0 src1));
7927 ins_cost(110);
7929 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7930 opcode(0x8D); /* 0x8D /r */
7931 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7932 ins_pipe( ialu_reg_reg );
7933 %}
7935 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7936 predicate(UseIncDec);
7937 match(Set dst (AddI dst src));
7938 effect(KILL cr);
7940 size(1);
7941 format %{ "DEC $dst" %}
7942 opcode(0x48); /* */
7943 ins_encode( Opc_plus( primary, dst ) );
7944 ins_pipe( ialu_reg );
7945 %}
7947 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7948 match(Set dst (AddP dst src));
7949 effect(KILL cr);
7951 size(2);
7952 format %{ "ADD $dst,$src" %}
7953 opcode(0x03);
7954 ins_encode( OpcP, RegReg( dst, src) );
7955 ins_pipe( ialu_reg_reg );
7956 %}
7958 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7959 match(Set dst (AddP dst src));
7960 effect(KILL cr);
7962 format %{ "ADD $dst,$src" %}
7963 opcode(0x81,0x00); /* Opcode 81 /0 id */
7964 // ins_encode( RegImm( dst, src) );
7965 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7966 ins_pipe( ialu_reg );
7967 %}
7969 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7970 match(Set dst (AddI dst (LoadI src)));
7971 effect(KILL cr);
7973 ins_cost(125);
7974 format %{ "ADD $dst,$src" %}
7975 opcode(0x03);
7976 ins_encode( OpcP, RegMem( dst, src) );
7977 ins_pipe( ialu_reg_mem );
7978 %}
7980 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7981 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7982 effect(KILL cr);
7984 ins_cost(150);
7985 format %{ "ADD $dst,$src" %}
7986 opcode(0x01); /* Opcode 01 /r */
7987 ins_encode( OpcP, RegMem( src, dst ) );
7988 ins_pipe( ialu_mem_reg );
7989 %}
7991 // Add Memory with Immediate
7992 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7993 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7994 effect(KILL cr);
7996 ins_cost(125);
7997 format %{ "ADD $dst,$src" %}
7998 opcode(0x81); /* Opcode 81 /0 id */
7999 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8000 ins_pipe( ialu_mem_imm );
8001 %}
8003 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8004 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8005 effect(KILL cr);
8007 ins_cost(125);
8008 format %{ "INC $dst" %}
8009 opcode(0xFF); /* Opcode FF /0 */
8010 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8011 ins_pipe( ialu_mem_imm );
8012 %}
8014 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8015 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8016 effect(KILL cr);
8018 ins_cost(125);
8019 format %{ "DEC $dst" %}
8020 opcode(0xFF); /* Opcode FF /1 */
8021 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8022 ins_pipe( ialu_mem_imm );
8023 %}
8026 instruct checkCastPP( eRegP dst ) %{
8027 match(Set dst (CheckCastPP dst));
8029 size(0);
8030 format %{ "#checkcastPP of $dst" %}
8031 ins_encode( /*empty encoding*/ );
8032 ins_pipe( empty );
8033 %}
8035 instruct castPP( eRegP dst ) %{
8036 match(Set dst (CastPP dst));
8037 format %{ "#castPP of $dst" %}
8038 ins_encode( /*empty encoding*/ );
8039 ins_pipe( empty );
8040 %}
8042 instruct castII( eRegI dst ) %{
8043 match(Set dst (CastII dst));
8044 format %{ "#castII of $dst" %}
8045 ins_encode( /*empty encoding*/ );
8046 ins_cost(0);
8047 ins_pipe( empty );
8048 %}
8051 // Load-locked - same as a regular pointer load when used with compare-swap
8052 instruct loadPLocked(eRegP dst, memory mem) %{
8053 match(Set dst (LoadPLocked mem));
8055 ins_cost(125);
8056 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8057 opcode(0x8B);
8058 ins_encode( OpcP, RegMem(dst,mem));
8059 ins_pipe( ialu_reg_mem );
8060 %}
8062 // LoadLong-locked - same as a volatile long load when used with compare-swap
8063 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8064 predicate(UseSSE<=1);
8065 match(Set dst (LoadLLocked mem));
8067 ins_cost(200);
8068 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8069 "FISTp $dst" %}
8070 ins_encode(enc_loadL_volatile(mem,dst));
8071 ins_pipe( fpu_reg_mem );
8072 %}
8074 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8075 predicate(UseSSE>=2);
8076 match(Set dst (LoadLLocked mem));
8077 effect(TEMP tmp);
8078 ins_cost(180);
8079 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8080 "MOVSD $dst,$tmp" %}
8081 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8082 ins_pipe( pipe_slow );
8083 %}
8085 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8086 predicate(UseSSE>=2);
8087 match(Set dst (LoadLLocked mem));
8088 effect(TEMP tmp);
8089 ins_cost(160);
8090 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8091 "MOVD $dst.lo,$tmp\n\t"
8092 "PSRLQ $tmp,32\n\t"
8093 "MOVD $dst.hi,$tmp" %}
8094 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8095 ins_pipe( pipe_slow );
8096 %}
8098 // Conditional-store of the updated heap-top.
8099 // Used during allocation of the shared heap.
8100 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8101 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8102 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8103 // EAX is killed if there is contention, but then it's also unused.
8104 // In the common case of no contention, EAX holds the new oop address.
8105 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8106 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8107 ins_pipe( pipe_cmpxchg );
8108 %}
8110 // Conditional-store of an int value.
8111 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8112 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8113 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8114 effect(KILL oldval);
8115 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8116 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8117 ins_pipe( pipe_cmpxchg );
8118 %}
8120 // Conditional-store of a long value.
8121 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8122 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8123 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8124 effect(KILL oldval);
8125 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8126 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8127 "XCHG EBX,ECX"
8128 %}
8129 ins_encode %{
8130 // Note: we need to swap rbx, and rcx before and after the
8131 // cmpxchg8 instruction because the instruction uses
8132 // rcx as the high order word of the new value to store but
8133 // our register encoding uses rbx.
8134 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8135 if( os::is_MP() )
8136 __ lock();
8137 __ cmpxchg8($mem$$Address);
8138 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8139 %}
8140 ins_pipe( pipe_cmpxchg );
8141 %}
8143 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8145 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8146 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8147 effect(KILL cr, KILL oldval);
8148 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8149 "MOV $res,0\n\t"
8150 "JNE,s fail\n\t"
8151 "MOV $res,1\n"
8152 "fail:" %}
8153 ins_encode( enc_cmpxchg8(mem_ptr),
8154 enc_flags_ne_to_boolean(res) );
8155 ins_pipe( pipe_cmpxchg );
8156 %}
8158 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8159 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8160 effect(KILL cr, KILL oldval);
8161 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8162 "MOV $res,0\n\t"
8163 "JNE,s fail\n\t"
8164 "MOV $res,1\n"
8165 "fail:" %}
8166 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8167 ins_pipe( pipe_cmpxchg );
8168 %}
8170 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8171 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8172 effect(KILL cr, KILL oldval);
8173 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8174 "MOV $res,0\n\t"
8175 "JNE,s fail\n\t"
8176 "MOV $res,1\n"
8177 "fail:" %}
8178 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8179 ins_pipe( pipe_cmpxchg );
8180 %}
8182 //----------Subtraction Instructions-------------------------------------------
8183 // Integer Subtraction Instructions
8184 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8185 match(Set dst (SubI dst src));
8186 effect(KILL cr);
8188 size(2);
8189 format %{ "SUB $dst,$src" %}
8190 opcode(0x2B);
8191 ins_encode( OpcP, RegReg( dst, src) );
8192 ins_pipe( ialu_reg_reg );
8193 %}
8195 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8196 match(Set dst (SubI dst src));
8197 effect(KILL cr);
8199 format %{ "SUB $dst,$src" %}
8200 opcode(0x81,0x05); /* Opcode 81 /5 */
8201 // ins_encode( RegImm( dst, src) );
8202 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8203 ins_pipe( ialu_reg );
8204 %}
8206 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8207 match(Set dst (SubI dst (LoadI src)));
8208 effect(KILL cr);
8210 ins_cost(125);
8211 format %{ "SUB $dst,$src" %}
8212 opcode(0x2B);
8213 ins_encode( OpcP, RegMem( dst, src) );
8214 ins_pipe( ialu_reg_mem );
8215 %}
8217 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8218 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8219 effect(KILL cr);
8221 ins_cost(150);
8222 format %{ "SUB $dst,$src" %}
8223 opcode(0x29); /* Opcode 29 /r */
8224 ins_encode( OpcP, RegMem( src, dst ) );
8225 ins_pipe( ialu_mem_reg );
8226 %}
8228 // Subtract from a pointer
8229 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8230 match(Set dst (AddP dst (SubI zero src)));
8231 effect(KILL cr);
8233 size(2);
8234 format %{ "SUB $dst,$src" %}
8235 opcode(0x2B);
8236 ins_encode( OpcP, RegReg( dst, src) );
8237 ins_pipe( ialu_reg_reg );
8238 %}
8240 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8241 match(Set dst (SubI zero dst));
8242 effect(KILL cr);
8244 size(2);
8245 format %{ "NEG $dst" %}
8246 opcode(0xF7,0x03); // Opcode F7 /3
8247 ins_encode( OpcP, RegOpc( dst ) );
8248 ins_pipe( ialu_reg );
8249 %}
8252 //----------Multiplication/Division Instructions-------------------------------
8253 // Integer Multiplication Instructions
8254 // Multiply Register
8255 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8256 match(Set dst (MulI dst src));
8257 effect(KILL cr);
8259 size(3);
8260 ins_cost(300);
8261 format %{ "IMUL $dst,$src" %}
8262 opcode(0xAF, 0x0F);
8263 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8264 ins_pipe( ialu_reg_reg_alu0 );
8265 %}
8267 // Multiply 32-bit Immediate
8268 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8269 match(Set dst (MulI src imm));
8270 effect(KILL cr);
8272 ins_cost(300);
8273 format %{ "IMUL $dst,$src,$imm" %}
8274 opcode(0x69); /* 69 /r id */
8275 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8276 ins_pipe( ialu_reg_reg_alu0 );
8277 %}
8279 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8280 match(Set dst src);
8281 effect(KILL cr);
8283 // Note that this is artificially increased to make it more expensive than loadConL
8284 ins_cost(250);
8285 format %{ "MOV EAX,$src\t// low word only" %}
8286 opcode(0xB8);
8287 ins_encode( LdImmL_Lo(dst, src) );
8288 ins_pipe( ialu_reg_fat );
8289 %}
8291 // Multiply by 32-bit Immediate, taking the shifted high order results
8292 // (special case for shift by 32)
8293 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8294 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8295 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8296 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8297 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8298 effect(USE src1, KILL cr);
8300 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8301 ins_cost(0*100 + 1*400 - 150);
8302 format %{ "IMUL EDX:EAX,$src1" %}
8303 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8304 ins_pipe( pipe_slow );
8305 %}
8307 // Multiply by 32-bit Immediate, taking the shifted high order results
8308 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8309 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8310 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8311 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8312 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8313 effect(USE src1, KILL cr);
8315 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8316 ins_cost(1*100 + 1*400 - 150);
8317 format %{ "IMUL EDX:EAX,$src1\n\t"
8318 "SAR EDX,$cnt-32" %}
8319 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8320 ins_pipe( pipe_slow );
8321 %}
8323 // Multiply Memory 32-bit Immediate
8324 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8325 match(Set dst (MulI (LoadI src) imm));
8326 effect(KILL cr);
8328 ins_cost(300);
8329 format %{ "IMUL $dst,$src,$imm" %}
8330 opcode(0x69); /* 69 /r id */
8331 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8332 ins_pipe( ialu_reg_mem_alu0 );
8333 %}
8335 // Multiply Memory
8336 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8337 match(Set dst (MulI dst (LoadI src)));
8338 effect(KILL cr);
8340 ins_cost(350);
8341 format %{ "IMUL $dst,$src" %}
8342 opcode(0xAF, 0x0F);
8343 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8344 ins_pipe( ialu_reg_mem_alu0 );
8345 %}
8347 // Multiply Register Int to Long
8348 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8349 // Basic Idea: long = (long)int * (long)int
8350 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8351 effect(DEF dst, USE src, USE src1, KILL flags);
8353 ins_cost(300);
8354 format %{ "IMUL $dst,$src1" %}
8356 ins_encode( long_int_multiply( dst, src1 ) );
8357 ins_pipe( ialu_reg_reg_alu0 );
8358 %}
8360 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8361 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8362 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8363 effect(KILL flags);
8365 ins_cost(300);
8366 format %{ "MUL $dst,$src1" %}
8368 ins_encode( long_uint_multiply(dst, src1) );
8369 ins_pipe( ialu_reg_reg_alu0 );
8370 %}
8372 // Multiply Register Long
8373 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8374 match(Set dst (MulL dst src));
8375 effect(KILL cr, TEMP tmp);
8376 ins_cost(4*100+3*400);
8377 // Basic idea: lo(result) = lo(x_lo * y_lo)
8378 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8379 format %{ "MOV $tmp,$src.lo\n\t"
8380 "IMUL $tmp,EDX\n\t"
8381 "MOV EDX,$src.hi\n\t"
8382 "IMUL EDX,EAX\n\t"
8383 "ADD $tmp,EDX\n\t"
8384 "MUL EDX:EAX,$src.lo\n\t"
8385 "ADD EDX,$tmp" %}
8386 ins_encode( long_multiply( dst, src, tmp ) );
8387 ins_pipe( pipe_slow );
8388 %}
8390 // Multiply Register Long by small constant
8391 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8392 match(Set dst (MulL dst src));
8393 effect(KILL cr, TEMP tmp);
8394 ins_cost(2*100+2*400);
8395 size(12);
8396 // Basic idea: lo(result) = lo(src * EAX)
8397 // hi(result) = hi(src * EAX) + lo(src * EDX)
8398 format %{ "IMUL $tmp,EDX,$src\n\t"
8399 "MOV EDX,$src\n\t"
8400 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8401 "ADD EDX,$tmp" %}
8402 ins_encode( long_multiply_con( dst, src, tmp ) );
8403 ins_pipe( pipe_slow );
8404 %}
8406 // Integer DIV with Register
8407 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8408 match(Set rax (DivI rax div));
8409 effect(KILL rdx, KILL cr);
8410 size(26);
8411 ins_cost(30*100+10*100);
8412 format %{ "CMP EAX,0x80000000\n\t"
8413 "JNE,s normal\n\t"
8414 "XOR EDX,EDX\n\t"
8415 "CMP ECX,-1\n\t"
8416 "JE,s done\n"
8417 "normal: CDQ\n\t"
8418 "IDIV $div\n\t"
8419 "done:" %}
8420 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8421 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8422 ins_pipe( ialu_reg_reg_alu0 );
8423 %}
8425 // Divide Register Long
8426 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8427 match(Set dst (DivL src1 src2));
8428 effect( KILL cr, KILL cx, KILL bx );
8429 ins_cost(10000);
8430 format %{ "PUSH $src1.hi\n\t"
8431 "PUSH $src1.lo\n\t"
8432 "PUSH $src2.hi\n\t"
8433 "PUSH $src2.lo\n\t"
8434 "CALL SharedRuntime::ldiv\n\t"
8435 "ADD ESP,16" %}
8436 ins_encode( long_div(src1,src2) );
8437 ins_pipe( pipe_slow );
8438 %}
8440 // Integer DIVMOD with Register, both quotient and mod results
8441 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8442 match(DivModI rax div);
8443 effect(KILL cr);
8444 size(26);
8445 ins_cost(30*100+10*100);
8446 format %{ "CMP EAX,0x80000000\n\t"
8447 "JNE,s normal\n\t"
8448 "XOR EDX,EDX\n\t"
8449 "CMP ECX,-1\n\t"
8450 "JE,s done\n"
8451 "normal: CDQ\n\t"
8452 "IDIV $div\n\t"
8453 "done:" %}
8454 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8455 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8456 ins_pipe( pipe_slow );
8457 %}
8459 // Integer MOD with Register
8460 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8461 match(Set rdx (ModI rax div));
8462 effect(KILL rax, KILL cr);
8464 size(26);
8465 ins_cost(300);
8466 format %{ "CDQ\n\t"
8467 "IDIV $div" %}
8468 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8469 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8470 ins_pipe( ialu_reg_reg_alu0 );
8471 %}
8473 // Remainder Register Long
8474 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8475 match(Set dst (ModL src1 src2));
8476 effect( KILL cr, KILL cx, KILL bx );
8477 ins_cost(10000);
8478 format %{ "PUSH $src1.hi\n\t"
8479 "PUSH $src1.lo\n\t"
8480 "PUSH $src2.hi\n\t"
8481 "PUSH $src2.lo\n\t"
8482 "CALL SharedRuntime::lrem\n\t"
8483 "ADD ESP,16" %}
8484 ins_encode( long_mod(src1,src2) );
8485 ins_pipe( pipe_slow );
8486 %}
8488 // Integer Shift Instructions
8489 // Shift Left by one
8490 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8491 match(Set dst (LShiftI dst shift));
8492 effect(KILL cr);
8494 size(2);
8495 format %{ "SHL $dst,$shift" %}
8496 opcode(0xD1, 0x4); /* D1 /4 */
8497 ins_encode( OpcP, RegOpc( dst ) );
8498 ins_pipe( ialu_reg );
8499 %}
8501 // Shift Left by 8-bit immediate
8502 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8503 match(Set dst (LShiftI dst shift));
8504 effect(KILL cr);
8506 size(3);
8507 format %{ "SHL $dst,$shift" %}
8508 opcode(0xC1, 0x4); /* C1 /4 ib */
8509 ins_encode( RegOpcImm( dst, shift) );
8510 ins_pipe( ialu_reg );
8511 %}
8513 // Shift Left by variable
8514 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8515 match(Set dst (LShiftI dst shift));
8516 effect(KILL cr);
8518 size(2);
8519 format %{ "SHL $dst,$shift" %}
8520 opcode(0xD3, 0x4); /* D3 /4 */
8521 ins_encode( OpcP, RegOpc( dst ) );
8522 ins_pipe( ialu_reg_reg );
8523 %}
8525 // Arithmetic shift right by one
8526 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8527 match(Set dst (RShiftI dst shift));
8528 effect(KILL cr);
8530 size(2);
8531 format %{ "SAR $dst,$shift" %}
8532 opcode(0xD1, 0x7); /* D1 /7 */
8533 ins_encode( OpcP, RegOpc( dst ) );
8534 ins_pipe( ialu_reg );
8535 %}
8537 // Arithmetic shift right by one
8538 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8539 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8540 effect(KILL cr);
8541 format %{ "SAR $dst,$shift" %}
8542 opcode(0xD1, 0x7); /* D1 /7 */
8543 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8544 ins_pipe( ialu_mem_imm );
8545 %}
8547 // Arithmetic Shift Right by 8-bit immediate
8548 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8549 match(Set dst (RShiftI dst shift));
8550 effect(KILL cr);
8552 size(3);
8553 format %{ "SAR $dst,$shift" %}
8554 opcode(0xC1, 0x7); /* C1 /7 ib */
8555 ins_encode( RegOpcImm( dst, shift ) );
8556 ins_pipe( ialu_mem_imm );
8557 %}
8559 // Arithmetic Shift Right by 8-bit immediate
8560 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8561 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8562 effect(KILL cr);
8564 format %{ "SAR $dst,$shift" %}
8565 opcode(0xC1, 0x7); /* C1 /7 ib */
8566 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8567 ins_pipe( ialu_mem_imm );
8568 %}
8570 // Arithmetic Shift Right by variable
8571 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8572 match(Set dst (RShiftI dst shift));
8573 effect(KILL cr);
8575 size(2);
8576 format %{ "SAR $dst,$shift" %}
8577 opcode(0xD3, 0x7); /* D3 /7 */
8578 ins_encode( OpcP, RegOpc( dst ) );
8579 ins_pipe( ialu_reg_reg );
8580 %}
8582 // Logical shift right by one
8583 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8584 match(Set dst (URShiftI dst shift));
8585 effect(KILL cr);
8587 size(2);
8588 format %{ "SHR $dst,$shift" %}
8589 opcode(0xD1, 0x5); /* D1 /5 */
8590 ins_encode( OpcP, RegOpc( dst ) );
8591 ins_pipe( ialu_reg );
8592 %}
8594 // Logical Shift Right by 8-bit immediate
8595 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8596 match(Set dst (URShiftI dst shift));
8597 effect(KILL cr);
8599 size(3);
8600 format %{ "SHR $dst,$shift" %}
8601 opcode(0xC1, 0x5); /* C1 /5 ib */
8602 ins_encode( RegOpcImm( dst, shift) );
8603 ins_pipe( ialu_reg );
8604 %}
8607 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8608 // This idiom is used by the compiler for the i2b bytecode.
8609 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
8610 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8611 effect(KILL cr);
8613 size(3);
8614 format %{ "MOVSX $dst,$src :8" %}
8615 opcode(0xBE, 0x0F);
8616 ins_encode( OpcS, OpcP, RegReg( dst, src));
8617 ins_pipe( ialu_reg_reg );
8618 %}
8620 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8621 // This idiom is used by the compiler the i2s bytecode.
8622 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
8623 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8624 effect(KILL cr);
8626 size(3);
8627 format %{ "MOVSX $dst,$src :16" %}
8628 opcode(0xBF, 0x0F);
8629 ins_encode( OpcS, OpcP, RegReg( dst, src));
8630 ins_pipe( ialu_reg_reg );
8631 %}
8634 // Logical Shift Right by variable
8635 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8636 match(Set dst (URShiftI dst shift));
8637 effect(KILL cr);
8639 size(2);
8640 format %{ "SHR $dst,$shift" %}
8641 opcode(0xD3, 0x5); /* D3 /5 */
8642 ins_encode( OpcP, RegOpc( dst ) );
8643 ins_pipe( ialu_reg_reg );
8644 %}
8647 //----------Logical Instructions-----------------------------------------------
8648 //----------Integer Logical Instructions---------------------------------------
8649 // And Instructions
8650 // And Register with Register
8651 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8652 match(Set dst (AndI dst src));
8653 effect(KILL cr);
8655 size(2);
8656 format %{ "AND $dst,$src" %}
8657 opcode(0x23);
8658 ins_encode( OpcP, RegReg( dst, src) );
8659 ins_pipe( ialu_reg_reg );
8660 %}
8662 // And Register with Immediate
8663 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8664 match(Set dst (AndI dst src));
8665 effect(KILL cr);
8667 format %{ "AND $dst,$src" %}
8668 opcode(0x81,0x04); /* Opcode 81 /4 */
8669 // ins_encode( RegImm( dst, src) );
8670 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8671 ins_pipe( ialu_reg );
8672 %}
8674 // And Register with Memory
8675 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8676 match(Set dst (AndI dst (LoadI src)));
8677 effect(KILL cr);
8679 ins_cost(125);
8680 format %{ "AND $dst,$src" %}
8681 opcode(0x23);
8682 ins_encode( OpcP, RegMem( dst, src) );
8683 ins_pipe( ialu_reg_mem );
8684 %}
8686 // And Memory with Register
8687 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8688 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8689 effect(KILL cr);
8691 ins_cost(150);
8692 format %{ "AND $dst,$src" %}
8693 opcode(0x21); /* Opcode 21 /r */
8694 ins_encode( OpcP, RegMem( src, dst ) );
8695 ins_pipe( ialu_mem_reg );
8696 %}
8698 // And Memory with Immediate
8699 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8700 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8701 effect(KILL cr);
8703 ins_cost(125);
8704 format %{ "AND $dst,$src" %}
8705 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8706 // ins_encode( MemImm( dst, src) );
8707 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8708 ins_pipe( ialu_mem_imm );
8709 %}
8711 // Or Instructions
8712 // Or Register with Register
8713 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8714 match(Set dst (OrI dst src));
8715 effect(KILL cr);
8717 size(2);
8718 format %{ "OR $dst,$src" %}
8719 opcode(0x0B);
8720 ins_encode( OpcP, RegReg( dst, src) );
8721 ins_pipe( ialu_reg_reg );
8722 %}
8724 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8725 match(Set dst (OrI dst (CastP2X src)));
8726 effect(KILL cr);
8728 size(2);
8729 format %{ "OR $dst,$src" %}
8730 opcode(0x0B);
8731 ins_encode( OpcP, RegReg( dst, src) );
8732 ins_pipe( ialu_reg_reg );
8733 %}
8736 // Or Register with Immediate
8737 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8738 match(Set dst (OrI dst src));
8739 effect(KILL cr);
8741 format %{ "OR $dst,$src" %}
8742 opcode(0x81,0x01); /* Opcode 81 /1 id */
8743 // ins_encode( RegImm( dst, src) );
8744 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8745 ins_pipe( ialu_reg );
8746 %}
8748 // Or Register with Memory
8749 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8750 match(Set dst (OrI dst (LoadI src)));
8751 effect(KILL cr);
8753 ins_cost(125);
8754 format %{ "OR $dst,$src" %}
8755 opcode(0x0B);
8756 ins_encode( OpcP, RegMem( dst, src) );
8757 ins_pipe( ialu_reg_mem );
8758 %}
8760 // Or Memory with Register
8761 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8762 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8763 effect(KILL cr);
8765 ins_cost(150);
8766 format %{ "OR $dst,$src" %}
8767 opcode(0x09); /* Opcode 09 /r */
8768 ins_encode( OpcP, RegMem( src, dst ) );
8769 ins_pipe( ialu_mem_reg );
8770 %}
8772 // Or Memory with Immediate
8773 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8774 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8775 effect(KILL cr);
8777 ins_cost(125);
8778 format %{ "OR $dst,$src" %}
8779 opcode(0x81,0x1); /* Opcode 81 /1 id */
8780 // ins_encode( MemImm( dst, src) );
8781 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8782 ins_pipe( ialu_mem_imm );
8783 %}
8785 // ROL/ROR
8786 // ROL expand
8787 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8788 effect(USE_DEF dst, USE shift, KILL cr);
8790 format %{ "ROL $dst, $shift" %}
8791 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8792 ins_encode( OpcP, RegOpc( dst ));
8793 ins_pipe( ialu_reg );
8794 %}
8796 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8797 effect(USE_DEF dst, USE shift, KILL cr);
8799 format %{ "ROL $dst, $shift" %}
8800 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8801 ins_encode( RegOpcImm(dst, shift) );
8802 ins_pipe(ialu_reg);
8803 %}
8805 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8806 effect(USE_DEF dst, USE shift, KILL cr);
8808 format %{ "ROL $dst, $shift" %}
8809 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8810 ins_encode(OpcP, RegOpc(dst));
8811 ins_pipe( ialu_reg_reg );
8812 %}
8813 // end of ROL expand
8815 // ROL 32bit by one once
8816 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8817 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8819 expand %{
8820 rolI_eReg_imm1(dst, lshift, cr);
8821 %}
8822 %}
8824 // ROL 32bit var by imm8 once
8825 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8826 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8827 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8829 expand %{
8830 rolI_eReg_imm8(dst, lshift, cr);
8831 %}
8832 %}
8834 // ROL 32bit var by var once
8835 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8836 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8838 expand %{
8839 rolI_eReg_CL(dst, shift, cr);
8840 %}
8841 %}
8843 // ROL 32bit var by var once
8844 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8845 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8847 expand %{
8848 rolI_eReg_CL(dst, shift, cr);
8849 %}
8850 %}
8852 // ROR expand
8853 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8854 effect(USE_DEF dst, USE shift, KILL cr);
8856 format %{ "ROR $dst, $shift" %}
8857 opcode(0xD1,0x1); /* Opcode D1 /1 */
8858 ins_encode( OpcP, RegOpc( dst ) );
8859 ins_pipe( ialu_reg );
8860 %}
8862 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8863 effect (USE_DEF dst, USE shift, KILL cr);
8865 format %{ "ROR $dst, $shift" %}
8866 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8867 ins_encode( RegOpcImm(dst, shift) );
8868 ins_pipe( ialu_reg );
8869 %}
8871 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8872 effect(USE_DEF dst, USE shift, KILL cr);
8874 format %{ "ROR $dst, $shift" %}
8875 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8876 ins_encode(OpcP, RegOpc(dst));
8877 ins_pipe( ialu_reg_reg );
8878 %}
8879 // end of ROR expand
8881 // ROR right once
8882 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8883 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8885 expand %{
8886 rorI_eReg_imm1(dst, rshift, cr);
8887 %}
8888 %}
8890 // ROR 32bit by immI8 once
8891 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8892 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8893 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8895 expand %{
8896 rorI_eReg_imm8(dst, rshift, cr);
8897 %}
8898 %}
8900 // ROR 32bit var by var once
8901 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8902 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8904 expand %{
8905 rorI_eReg_CL(dst, shift, cr);
8906 %}
8907 %}
8909 // ROR 32bit var by var once
8910 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8911 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8913 expand %{
8914 rorI_eReg_CL(dst, shift, cr);
8915 %}
8916 %}
8918 // Xor Instructions
8919 // Xor Register with Register
8920 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8921 match(Set dst (XorI dst src));
8922 effect(KILL cr);
8924 size(2);
8925 format %{ "XOR $dst,$src" %}
8926 opcode(0x33);
8927 ins_encode( OpcP, RegReg( dst, src) );
8928 ins_pipe( ialu_reg_reg );
8929 %}
8931 // Xor Register with Immediate -1
8932 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
8933 match(Set dst (XorI dst imm));
8935 size(2);
8936 format %{ "NOT $dst" %}
8937 ins_encode %{
8938 __ notl($dst$$Register);
8939 %}
8940 ins_pipe( ialu_reg );
8941 %}
8943 // Xor Register with Immediate
8944 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8945 match(Set dst (XorI dst src));
8946 effect(KILL cr);
8948 format %{ "XOR $dst,$src" %}
8949 opcode(0x81,0x06); /* Opcode 81 /6 id */
8950 // ins_encode( RegImm( dst, src) );
8951 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8952 ins_pipe( ialu_reg );
8953 %}
8955 // Xor Register with Memory
8956 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8957 match(Set dst (XorI dst (LoadI src)));
8958 effect(KILL cr);
8960 ins_cost(125);
8961 format %{ "XOR $dst,$src" %}
8962 opcode(0x33);
8963 ins_encode( OpcP, RegMem(dst, src) );
8964 ins_pipe( ialu_reg_mem );
8965 %}
8967 // Xor Memory with Register
8968 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8969 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8970 effect(KILL cr);
8972 ins_cost(150);
8973 format %{ "XOR $dst,$src" %}
8974 opcode(0x31); /* Opcode 31 /r */
8975 ins_encode( OpcP, RegMem( src, dst ) );
8976 ins_pipe( ialu_mem_reg );
8977 %}
8979 // Xor Memory with Immediate
8980 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8981 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8982 effect(KILL cr);
8984 ins_cost(125);
8985 format %{ "XOR $dst,$src" %}
8986 opcode(0x81,0x6); /* Opcode 81 /6 id */
8987 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8988 ins_pipe( ialu_mem_imm );
8989 %}
8991 //----------Convert Int to Boolean---------------------------------------------
8993 instruct movI_nocopy(eRegI dst, eRegI src) %{
8994 effect( DEF dst, USE src );
8995 format %{ "MOV $dst,$src" %}
8996 ins_encode( enc_Copy( dst, src) );
8997 ins_pipe( ialu_reg_reg );
8998 %}
9000 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9001 effect( USE_DEF dst, USE src, KILL cr );
9003 size(4);
9004 format %{ "NEG $dst\n\t"
9005 "ADC $dst,$src" %}
9006 ins_encode( neg_reg(dst),
9007 OpcRegReg(0x13,dst,src) );
9008 ins_pipe( ialu_reg_reg_long );
9009 %}
9011 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9012 match(Set dst (Conv2B src));
9014 expand %{
9015 movI_nocopy(dst,src);
9016 ci2b(dst,src,cr);
9017 %}
9018 %}
9020 instruct movP_nocopy(eRegI dst, eRegP src) %{
9021 effect( DEF dst, USE src );
9022 format %{ "MOV $dst,$src" %}
9023 ins_encode( enc_Copy( dst, src) );
9024 ins_pipe( ialu_reg_reg );
9025 %}
9027 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9028 effect( USE_DEF dst, USE src, KILL cr );
9029 format %{ "NEG $dst\n\t"
9030 "ADC $dst,$src" %}
9031 ins_encode( neg_reg(dst),
9032 OpcRegReg(0x13,dst,src) );
9033 ins_pipe( ialu_reg_reg_long );
9034 %}
9036 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9037 match(Set dst (Conv2B src));
9039 expand %{
9040 movP_nocopy(dst,src);
9041 cp2b(dst,src,cr);
9042 %}
9043 %}
9045 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9046 match(Set dst (CmpLTMask p q));
9047 effect( KILL cr );
9048 ins_cost(400);
9050 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9051 format %{ "XOR $dst,$dst\n\t"
9052 "CMP $p,$q\n\t"
9053 "SETlt $dst\n\t"
9054 "NEG $dst" %}
9055 ins_encode( OpcRegReg(0x33,dst,dst),
9056 OpcRegReg(0x3B,p,q),
9057 setLT_reg(dst), neg_reg(dst) );
9058 ins_pipe( pipe_slow );
9059 %}
9061 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9062 match(Set dst (CmpLTMask dst zero));
9063 effect( DEF dst, KILL cr );
9064 ins_cost(100);
9066 format %{ "SAR $dst,31" %}
9067 opcode(0xC1, 0x7); /* C1 /7 ib */
9068 ins_encode( RegOpcImm( dst, 0x1F ) );
9069 ins_pipe( ialu_reg );
9070 %}
9073 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9074 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9075 effect( KILL tmp, KILL cr );
9076 ins_cost(400);
9077 // annoyingly, $tmp has no edges so you cant ask for it in
9078 // any format or encoding
9079 format %{ "SUB $p,$q\n\t"
9080 "SBB ECX,ECX\n\t"
9081 "AND ECX,$y\n\t"
9082 "ADD $p,ECX" %}
9083 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9084 ins_pipe( pipe_cmplt );
9085 %}
9087 /* If I enable this, I encourage spilling in the inner loop of compress.
9088 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9089 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9090 effect( USE_KILL tmp, KILL cr );
9091 ins_cost(400);
9093 format %{ "SUB $p,$q\n\t"
9094 "SBB ECX,ECX\n\t"
9095 "AND ECX,$y\n\t"
9096 "ADD $p,ECX" %}
9097 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9098 %}
9099 */
9101 //----------Long Instructions------------------------------------------------
9102 // Add Long Register with Register
9103 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9104 match(Set dst (AddL dst src));
9105 effect(KILL cr);
9106 ins_cost(200);
9107 format %{ "ADD $dst.lo,$src.lo\n\t"
9108 "ADC $dst.hi,$src.hi" %}
9109 opcode(0x03, 0x13);
9110 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9111 ins_pipe( ialu_reg_reg_long );
9112 %}
9114 // Add Long Register with Immediate
9115 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9116 match(Set dst (AddL dst src));
9117 effect(KILL cr);
9118 format %{ "ADD $dst.lo,$src.lo\n\t"
9119 "ADC $dst.hi,$src.hi" %}
9120 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9121 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9122 ins_pipe( ialu_reg_long );
9123 %}
9125 // Add Long Register with Memory
9126 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9127 match(Set dst (AddL dst (LoadL mem)));
9128 effect(KILL cr);
9129 ins_cost(125);
9130 format %{ "ADD $dst.lo,$mem\n\t"
9131 "ADC $dst.hi,$mem+4" %}
9132 opcode(0x03, 0x13);
9133 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9134 ins_pipe( ialu_reg_long_mem );
9135 %}
9137 // Subtract Long Register with Register.
9138 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9139 match(Set dst (SubL dst src));
9140 effect(KILL cr);
9141 ins_cost(200);
9142 format %{ "SUB $dst.lo,$src.lo\n\t"
9143 "SBB $dst.hi,$src.hi" %}
9144 opcode(0x2B, 0x1B);
9145 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9146 ins_pipe( ialu_reg_reg_long );
9147 %}
9149 // Subtract Long Register with Immediate
9150 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9151 match(Set dst (SubL dst src));
9152 effect(KILL cr);
9153 format %{ "SUB $dst.lo,$src.lo\n\t"
9154 "SBB $dst.hi,$src.hi" %}
9155 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9156 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9157 ins_pipe( ialu_reg_long );
9158 %}
9160 // Subtract Long Register with Memory
9161 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9162 match(Set dst (SubL dst (LoadL mem)));
9163 effect(KILL cr);
9164 ins_cost(125);
9165 format %{ "SUB $dst.lo,$mem\n\t"
9166 "SBB $dst.hi,$mem+4" %}
9167 opcode(0x2B, 0x1B);
9168 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9169 ins_pipe( ialu_reg_long_mem );
9170 %}
9172 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9173 match(Set dst (SubL zero dst));
9174 effect(KILL cr);
9175 ins_cost(300);
9176 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9177 ins_encode( neg_long(dst) );
9178 ins_pipe( ialu_reg_reg_long );
9179 %}
9181 // And Long Register with Register
9182 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9183 match(Set dst (AndL dst src));
9184 effect(KILL cr);
9185 format %{ "AND $dst.lo,$src.lo\n\t"
9186 "AND $dst.hi,$src.hi" %}
9187 opcode(0x23,0x23);
9188 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9189 ins_pipe( ialu_reg_reg_long );
9190 %}
9192 // And Long Register with Immediate
9193 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9194 match(Set dst (AndL dst src));
9195 effect(KILL cr);
9196 format %{ "AND $dst.lo,$src.lo\n\t"
9197 "AND $dst.hi,$src.hi" %}
9198 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9199 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9200 ins_pipe( ialu_reg_long );
9201 %}
9203 // And Long Register with Memory
9204 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9205 match(Set dst (AndL dst (LoadL mem)));
9206 effect(KILL cr);
9207 ins_cost(125);
9208 format %{ "AND $dst.lo,$mem\n\t"
9209 "AND $dst.hi,$mem+4" %}
9210 opcode(0x23, 0x23);
9211 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9212 ins_pipe( ialu_reg_long_mem );
9213 %}
9215 // Or Long Register with Register
9216 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9217 match(Set dst (OrL dst src));
9218 effect(KILL cr);
9219 format %{ "OR $dst.lo,$src.lo\n\t"
9220 "OR $dst.hi,$src.hi" %}
9221 opcode(0x0B,0x0B);
9222 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9223 ins_pipe( ialu_reg_reg_long );
9224 %}
9226 // Or Long Register with Immediate
9227 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9228 match(Set dst (OrL dst src));
9229 effect(KILL cr);
9230 format %{ "OR $dst.lo,$src.lo\n\t"
9231 "OR $dst.hi,$src.hi" %}
9232 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9233 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9234 ins_pipe( ialu_reg_long );
9235 %}
9237 // Or Long Register with Memory
9238 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9239 match(Set dst (OrL dst (LoadL mem)));
9240 effect(KILL cr);
9241 ins_cost(125);
9242 format %{ "OR $dst.lo,$mem\n\t"
9243 "OR $dst.hi,$mem+4" %}
9244 opcode(0x0B,0x0B);
9245 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9246 ins_pipe( ialu_reg_long_mem );
9247 %}
9249 // Xor Long Register with Register
9250 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9251 match(Set dst (XorL dst src));
9252 effect(KILL cr);
9253 format %{ "XOR $dst.lo,$src.lo\n\t"
9254 "XOR $dst.hi,$src.hi" %}
9255 opcode(0x33,0x33);
9256 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9257 ins_pipe( ialu_reg_reg_long );
9258 %}
9260 // Xor Long Register with Immediate -1
9261 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9262 match(Set dst (XorL dst imm));
9263 format %{ "NOT $dst.lo\n\t"
9264 "NOT $dst.hi" %}
9265 ins_encode %{
9266 __ notl($dst$$Register);
9267 __ notl(HIGH_FROM_LOW($dst$$Register));
9268 %}
9269 ins_pipe( ialu_reg_long );
9270 %}
9272 // Xor Long Register with Immediate
9273 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9274 match(Set dst (XorL dst src));
9275 effect(KILL cr);
9276 format %{ "XOR $dst.lo,$src.lo\n\t"
9277 "XOR $dst.hi,$src.hi" %}
9278 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9279 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9280 ins_pipe( ialu_reg_long );
9281 %}
9283 // Xor Long Register with Memory
9284 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9285 match(Set dst (XorL dst (LoadL mem)));
9286 effect(KILL cr);
9287 ins_cost(125);
9288 format %{ "XOR $dst.lo,$mem\n\t"
9289 "XOR $dst.hi,$mem+4" %}
9290 opcode(0x33,0x33);
9291 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9292 ins_pipe( ialu_reg_long_mem );
9293 %}
9295 // Shift Left Long by 1
9296 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9297 predicate(UseNewLongLShift);
9298 match(Set dst (LShiftL dst cnt));
9299 effect(KILL cr);
9300 ins_cost(100);
9301 format %{ "ADD $dst.lo,$dst.lo\n\t"
9302 "ADC $dst.hi,$dst.hi" %}
9303 ins_encode %{
9304 __ addl($dst$$Register,$dst$$Register);
9305 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9306 %}
9307 ins_pipe( ialu_reg_long );
9308 %}
9310 // Shift Left Long by 2
9311 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9312 predicate(UseNewLongLShift);
9313 match(Set dst (LShiftL dst cnt));
9314 effect(KILL cr);
9315 ins_cost(100);
9316 format %{ "ADD $dst.lo,$dst.lo\n\t"
9317 "ADC $dst.hi,$dst.hi\n\t"
9318 "ADD $dst.lo,$dst.lo\n\t"
9319 "ADC $dst.hi,$dst.hi" %}
9320 ins_encode %{
9321 __ addl($dst$$Register,$dst$$Register);
9322 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9323 __ addl($dst$$Register,$dst$$Register);
9324 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9325 %}
9326 ins_pipe( ialu_reg_long );
9327 %}
9329 // Shift Left Long by 3
9330 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9331 predicate(UseNewLongLShift);
9332 match(Set dst (LShiftL dst cnt));
9333 effect(KILL cr);
9334 ins_cost(100);
9335 format %{ "ADD $dst.lo,$dst.lo\n\t"
9336 "ADC $dst.hi,$dst.hi\n\t"
9337 "ADD $dst.lo,$dst.lo\n\t"
9338 "ADC $dst.hi,$dst.hi\n\t"
9339 "ADD $dst.lo,$dst.lo\n\t"
9340 "ADC $dst.hi,$dst.hi" %}
9341 ins_encode %{
9342 __ addl($dst$$Register,$dst$$Register);
9343 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9344 __ addl($dst$$Register,$dst$$Register);
9345 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9346 __ addl($dst$$Register,$dst$$Register);
9347 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9348 %}
9349 ins_pipe( ialu_reg_long );
9350 %}
9352 // Shift Left Long by 1-31
9353 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9354 match(Set dst (LShiftL dst cnt));
9355 effect(KILL cr);
9356 ins_cost(200);
9357 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9358 "SHL $dst.lo,$cnt" %}
9359 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9360 ins_encode( move_long_small_shift(dst,cnt) );
9361 ins_pipe( ialu_reg_long );
9362 %}
9364 // Shift Left Long by 32-63
9365 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9366 match(Set dst (LShiftL dst cnt));
9367 effect(KILL cr);
9368 ins_cost(300);
9369 format %{ "MOV $dst.hi,$dst.lo\n"
9370 "\tSHL $dst.hi,$cnt-32\n"
9371 "\tXOR $dst.lo,$dst.lo" %}
9372 opcode(0xC1, 0x4); /* C1 /4 ib */
9373 ins_encode( move_long_big_shift_clr(dst,cnt) );
9374 ins_pipe( ialu_reg_long );
9375 %}
9377 // Shift Left Long by variable
9378 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9379 match(Set dst (LShiftL dst shift));
9380 effect(KILL cr);
9381 ins_cost(500+200);
9382 size(17);
9383 format %{ "TEST $shift,32\n\t"
9384 "JEQ,s small\n\t"
9385 "MOV $dst.hi,$dst.lo\n\t"
9386 "XOR $dst.lo,$dst.lo\n"
9387 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9388 "SHL $dst.lo,$shift" %}
9389 ins_encode( shift_left_long( dst, shift ) );
9390 ins_pipe( pipe_slow );
9391 %}
9393 // Shift Right Long by 1-31
9394 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9395 match(Set dst (URShiftL dst cnt));
9396 effect(KILL cr);
9397 ins_cost(200);
9398 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9399 "SHR $dst.hi,$cnt" %}
9400 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9401 ins_encode( move_long_small_shift(dst,cnt) );
9402 ins_pipe( ialu_reg_long );
9403 %}
9405 // Shift Right Long by 32-63
9406 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9407 match(Set dst (URShiftL dst cnt));
9408 effect(KILL cr);
9409 ins_cost(300);
9410 format %{ "MOV $dst.lo,$dst.hi\n"
9411 "\tSHR $dst.lo,$cnt-32\n"
9412 "\tXOR $dst.hi,$dst.hi" %}
9413 opcode(0xC1, 0x5); /* C1 /5 ib */
9414 ins_encode( move_long_big_shift_clr(dst,cnt) );
9415 ins_pipe( ialu_reg_long );
9416 %}
9418 // Shift Right Long by variable
9419 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9420 match(Set dst (URShiftL dst shift));
9421 effect(KILL cr);
9422 ins_cost(600);
9423 size(17);
9424 format %{ "TEST $shift,32\n\t"
9425 "JEQ,s small\n\t"
9426 "MOV $dst.lo,$dst.hi\n\t"
9427 "XOR $dst.hi,$dst.hi\n"
9428 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9429 "SHR $dst.hi,$shift" %}
9430 ins_encode( shift_right_long( dst, shift ) );
9431 ins_pipe( pipe_slow );
9432 %}
9434 // Shift Right Long by 1-31
9435 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9436 match(Set dst (RShiftL dst cnt));
9437 effect(KILL cr);
9438 ins_cost(200);
9439 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9440 "SAR $dst.hi,$cnt" %}
9441 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9442 ins_encode( move_long_small_shift(dst,cnt) );
9443 ins_pipe( ialu_reg_long );
9444 %}
9446 // Shift Right Long by 32-63
9447 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9448 match(Set dst (RShiftL dst cnt));
9449 effect(KILL cr);
9450 ins_cost(300);
9451 format %{ "MOV $dst.lo,$dst.hi\n"
9452 "\tSAR $dst.lo,$cnt-32\n"
9453 "\tSAR $dst.hi,31" %}
9454 opcode(0xC1, 0x7); /* C1 /7 ib */
9455 ins_encode( move_long_big_shift_sign(dst,cnt) );
9456 ins_pipe( ialu_reg_long );
9457 %}
9459 // Shift Right arithmetic Long by variable
9460 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9461 match(Set dst (RShiftL dst shift));
9462 effect(KILL cr);
9463 ins_cost(600);
9464 size(18);
9465 format %{ "TEST $shift,32\n\t"
9466 "JEQ,s small\n\t"
9467 "MOV $dst.lo,$dst.hi\n\t"
9468 "SAR $dst.hi,31\n"
9469 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9470 "SAR $dst.hi,$shift" %}
9471 ins_encode( shift_right_arith_long( dst, shift ) );
9472 ins_pipe( pipe_slow );
9473 %}
9476 //----------Double Instructions------------------------------------------------
9477 // Double Math
9479 // Compare & branch
9481 // P6 version of float compare, sets condition codes in EFLAGS
9482 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9483 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9484 match(Set cr (CmpD src1 src2));
9485 effect(KILL rax);
9486 ins_cost(150);
9487 format %{ "FLD $src1\n\t"
9488 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9489 "JNP exit\n\t"
9490 "MOV ah,1 // saw a NaN, set CF\n\t"
9491 "SAHF\n"
9492 "exit:\tNOP // avoid branch to branch" %}
9493 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9494 ins_encode( Push_Reg_D(src1),
9495 OpcP, RegOpc(src2),
9496 cmpF_P6_fixup );
9497 ins_pipe( pipe_slow );
9498 %}
9500 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9501 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9502 match(Set cr (CmpD src1 src2));
9503 ins_cost(150);
9504 format %{ "FLD $src1\n\t"
9505 "FUCOMIP ST,$src2 // P6 instruction" %}
9506 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9507 ins_encode( Push_Reg_D(src1),
9508 OpcP, RegOpc(src2));
9509 ins_pipe( pipe_slow );
9510 %}
9512 // Compare & branch
9513 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9514 predicate(UseSSE<=1);
9515 match(Set cr (CmpD src1 src2));
9516 effect(KILL rax);
9517 ins_cost(200);
9518 format %{ "FLD $src1\n\t"
9519 "FCOMp $src2\n\t"
9520 "FNSTSW AX\n\t"
9521 "TEST AX,0x400\n\t"
9522 "JZ,s flags\n\t"
9523 "MOV AH,1\t# unordered treat as LT\n"
9524 "flags:\tSAHF" %}
9525 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9526 ins_encode( Push_Reg_D(src1),
9527 OpcP, RegOpc(src2),
9528 fpu_flags);
9529 ins_pipe( pipe_slow );
9530 %}
9532 // Compare vs zero into -1,0,1
9533 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9534 predicate(UseSSE<=1);
9535 match(Set dst (CmpD3 src1 zero));
9536 effect(KILL cr, KILL rax);
9537 ins_cost(280);
9538 format %{ "FTSTD $dst,$src1" %}
9539 opcode(0xE4, 0xD9);
9540 ins_encode( Push_Reg_D(src1),
9541 OpcS, OpcP, PopFPU,
9542 CmpF_Result(dst));
9543 ins_pipe( pipe_slow );
9544 %}
9546 // Compare into -1,0,1
9547 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9548 predicate(UseSSE<=1);
9549 match(Set dst (CmpD3 src1 src2));
9550 effect(KILL cr, KILL rax);
9551 ins_cost(300);
9552 format %{ "FCMPD $dst,$src1,$src2" %}
9553 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9554 ins_encode( Push_Reg_D(src1),
9555 OpcP, RegOpc(src2),
9556 CmpF_Result(dst));
9557 ins_pipe( pipe_slow );
9558 %}
9560 // float compare and set condition codes in EFLAGS by XMM regs
9561 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9562 predicate(UseSSE>=2);
9563 match(Set cr (CmpD dst src));
9564 effect(KILL rax);
9565 ins_cost(125);
9566 format %{ "COMISD $dst,$src\n"
9567 "\tJNP exit\n"
9568 "\tMOV ah,1 // saw a NaN, set CF\n"
9569 "\tSAHF\n"
9570 "exit:\tNOP // avoid branch to branch" %}
9571 opcode(0x66, 0x0F, 0x2F);
9572 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9573 ins_pipe( pipe_slow );
9574 %}
9576 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9577 predicate(UseSSE>=2);
9578 match(Set cr (CmpD dst src));
9579 ins_cost(100);
9580 format %{ "COMISD $dst,$src" %}
9581 opcode(0x66, 0x0F, 0x2F);
9582 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9583 ins_pipe( pipe_slow );
9584 %}
9586 // float compare and set condition codes in EFLAGS by XMM regs
9587 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9588 predicate(UseSSE>=2);
9589 match(Set cr (CmpD dst (LoadD src)));
9590 effect(KILL rax);
9591 ins_cost(145);
9592 format %{ "COMISD $dst,$src\n"
9593 "\tJNP exit\n"
9594 "\tMOV ah,1 // saw a NaN, set CF\n"
9595 "\tSAHF\n"
9596 "exit:\tNOP // avoid branch to branch" %}
9597 opcode(0x66, 0x0F, 0x2F);
9598 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9599 ins_pipe( pipe_slow );
9600 %}
9602 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9603 predicate(UseSSE>=2);
9604 match(Set cr (CmpD dst (LoadD src)));
9605 ins_cost(100);
9606 format %{ "COMISD $dst,$src" %}
9607 opcode(0x66, 0x0F, 0x2F);
9608 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9609 ins_pipe( pipe_slow );
9610 %}
9612 // Compare into -1,0,1 in XMM
9613 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9614 predicate(UseSSE>=2);
9615 match(Set dst (CmpD3 src1 src2));
9616 effect(KILL cr);
9617 ins_cost(255);
9618 format %{ "XOR $dst,$dst\n"
9619 "\tCOMISD $src1,$src2\n"
9620 "\tJP,s nan\n"
9621 "\tJEQ,s exit\n"
9622 "\tJA,s inc\n"
9623 "nan:\tDEC $dst\n"
9624 "\tJMP,s exit\n"
9625 "inc:\tINC $dst\n"
9626 "exit:"
9627 %}
9628 opcode(0x66, 0x0F, 0x2F);
9629 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9630 CmpX_Result(dst));
9631 ins_pipe( pipe_slow );
9632 %}
9634 // Compare into -1,0,1 in XMM and memory
9635 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9636 predicate(UseSSE>=2);
9637 match(Set dst (CmpD3 src1 (LoadD mem)));
9638 effect(KILL cr);
9639 ins_cost(275);
9640 format %{ "COMISD $src1,$mem\n"
9641 "\tMOV $dst,0\t\t# do not blow flags\n"
9642 "\tJP,s nan\n"
9643 "\tJEQ,s exit\n"
9644 "\tJA,s inc\n"
9645 "nan:\tDEC $dst\n"
9646 "\tJMP,s exit\n"
9647 "inc:\tINC $dst\n"
9648 "exit:"
9649 %}
9650 opcode(0x66, 0x0F, 0x2F);
9651 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9652 LdImmI(dst,0x0), CmpX_Result(dst));
9653 ins_pipe( pipe_slow );
9654 %}
9657 instruct subD_reg(regD dst, regD src) %{
9658 predicate (UseSSE <=1);
9659 match(Set dst (SubD dst src));
9661 format %{ "FLD $src\n\t"
9662 "DSUBp $dst,ST" %}
9663 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9664 ins_cost(150);
9665 ins_encode( Push_Reg_D(src),
9666 OpcP, RegOpc(dst) );
9667 ins_pipe( fpu_reg_reg );
9668 %}
9670 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9671 predicate (UseSSE <=1);
9672 match(Set dst (RoundDouble (SubD src1 src2)));
9673 ins_cost(250);
9675 format %{ "FLD $src2\n\t"
9676 "DSUB ST,$src1\n\t"
9677 "FSTP_D $dst\t# D-round" %}
9678 opcode(0xD8, 0x5);
9679 ins_encode( Push_Reg_D(src2),
9680 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9681 ins_pipe( fpu_mem_reg_reg );
9682 %}
9685 instruct subD_reg_mem(regD dst, memory src) %{
9686 predicate (UseSSE <=1);
9687 match(Set dst (SubD dst (LoadD src)));
9688 ins_cost(150);
9690 format %{ "FLD $src\n\t"
9691 "DSUBp $dst,ST" %}
9692 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9693 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9694 OpcP, RegOpc(dst) );
9695 ins_pipe( fpu_reg_mem );
9696 %}
9698 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9699 predicate (UseSSE<=1);
9700 match(Set dst (AbsD src));
9701 ins_cost(100);
9702 format %{ "FABS" %}
9703 opcode(0xE1, 0xD9);
9704 ins_encode( OpcS, OpcP );
9705 ins_pipe( fpu_reg_reg );
9706 %}
9708 instruct absXD_reg( regXD dst ) %{
9709 predicate(UseSSE>=2);
9710 match(Set dst (AbsD dst));
9711 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9712 ins_encode( AbsXD_encoding(dst));
9713 ins_pipe( pipe_slow );
9714 %}
9716 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9717 predicate(UseSSE<=1);
9718 match(Set dst (NegD src));
9719 ins_cost(100);
9720 format %{ "FCHS" %}
9721 opcode(0xE0, 0xD9);
9722 ins_encode( OpcS, OpcP );
9723 ins_pipe( fpu_reg_reg );
9724 %}
9726 instruct negXD_reg( regXD dst ) %{
9727 predicate(UseSSE>=2);
9728 match(Set dst (NegD dst));
9729 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9730 ins_encode %{
9731 __ xorpd($dst$$XMMRegister,
9732 ExternalAddress((address)double_signflip_pool));
9733 %}
9734 ins_pipe( pipe_slow );
9735 %}
9737 instruct addD_reg(regD dst, regD src) %{
9738 predicate(UseSSE<=1);
9739 match(Set dst (AddD dst src));
9740 format %{ "FLD $src\n\t"
9741 "DADD $dst,ST" %}
9742 size(4);
9743 ins_cost(150);
9744 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9745 ins_encode( Push_Reg_D(src),
9746 OpcP, RegOpc(dst) );
9747 ins_pipe( fpu_reg_reg );
9748 %}
9751 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9752 predicate(UseSSE<=1);
9753 match(Set dst (RoundDouble (AddD src1 src2)));
9754 ins_cost(250);
9756 format %{ "FLD $src2\n\t"
9757 "DADD ST,$src1\n\t"
9758 "FSTP_D $dst\t# D-round" %}
9759 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9760 ins_encode( Push_Reg_D(src2),
9761 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9762 ins_pipe( fpu_mem_reg_reg );
9763 %}
9766 instruct addD_reg_mem(regD dst, memory src) %{
9767 predicate(UseSSE<=1);
9768 match(Set dst (AddD dst (LoadD src)));
9769 ins_cost(150);
9771 format %{ "FLD $src\n\t"
9772 "DADDp $dst,ST" %}
9773 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9774 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9775 OpcP, RegOpc(dst) );
9776 ins_pipe( fpu_reg_mem );
9777 %}
9779 // add-to-memory
9780 instruct addD_mem_reg(memory dst, regD src) %{
9781 predicate(UseSSE<=1);
9782 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9783 ins_cost(150);
9785 format %{ "FLD_D $dst\n\t"
9786 "DADD ST,$src\n\t"
9787 "FST_D $dst" %}
9788 opcode(0xDD, 0x0);
9789 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9790 Opcode(0xD8), RegOpc(src),
9791 set_instruction_start,
9792 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9793 ins_pipe( fpu_reg_mem );
9794 %}
9796 instruct addD_reg_imm1(regD dst, immD1 src) %{
9797 predicate(UseSSE<=1);
9798 match(Set dst (AddD dst src));
9799 ins_cost(125);
9800 format %{ "FLD1\n\t"
9801 "DADDp $dst,ST" %}
9802 opcode(0xDE, 0x00);
9803 ins_encode( LdImmD(src),
9804 OpcP, RegOpc(dst) );
9805 ins_pipe( fpu_reg );
9806 %}
9808 instruct addD_reg_imm(regD dst, immD src) %{
9809 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9810 match(Set dst (AddD dst src));
9811 ins_cost(200);
9812 format %{ "FLD_D [$src]\n\t"
9813 "DADDp $dst,ST" %}
9814 opcode(0xDE, 0x00); /* DE /0 */
9815 ins_encode( LdImmD(src),
9816 OpcP, RegOpc(dst));
9817 ins_pipe( fpu_reg_mem );
9818 %}
9820 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9821 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9822 match(Set dst (RoundDouble (AddD src con)));
9823 ins_cost(200);
9824 format %{ "FLD_D [$con]\n\t"
9825 "DADD ST,$src\n\t"
9826 "FSTP_D $dst\t# D-round" %}
9827 opcode(0xD8, 0x00); /* D8 /0 */
9828 ins_encode( LdImmD(con),
9829 OpcP, RegOpc(src), Pop_Mem_D(dst));
9830 ins_pipe( fpu_mem_reg_con );
9831 %}
9833 // Add two double precision floating point values in xmm
9834 instruct addXD_reg(regXD dst, regXD src) %{
9835 predicate(UseSSE>=2);
9836 match(Set dst (AddD dst src));
9837 format %{ "ADDSD $dst,$src" %}
9838 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
9839 ins_pipe( pipe_slow );
9840 %}
9842 instruct addXD_imm(regXD dst, immXD con) %{
9843 predicate(UseSSE>=2);
9844 match(Set dst (AddD dst con));
9845 format %{ "ADDSD $dst,[$con]" %}
9846 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
9847 ins_pipe( pipe_slow );
9848 %}
9850 instruct addXD_mem(regXD dst, memory mem) %{
9851 predicate(UseSSE>=2);
9852 match(Set dst (AddD dst (LoadD mem)));
9853 format %{ "ADDSD $dst,$mem" %}
9854 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
9855 ins_pipe( pipe_slow );
9856 %}
9858 // Sub two double precision floating point values in xmm
9859 instruct subXD_reg(regXD dst, regXD src) %{
9860 predicate(UseSSE>=2);
9861 match(Set dst (SubD dst src));
9862 format %{ "SUBSD $dst,$src" %}
9863 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
9864 ins_pipe( pipe_slow );
9865 %}
9867 instruct subXD_imm(regXD dst, immXD con) %{
9868 predicate(UseSSE>=2);
9869 match(Set dst (SubD dst con));
9870 format %{ "SUBSD $dst,[$con]" %}
9871 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
9872 ins_pipe( pipe_slow );
9873 %}
9875 instruct subXD_mem(regXD dst, memory mem) %{
9876 predicate(UseSSE>=2);
9877 match(Set dst (SubD dst (LoadD mem)));
9878 format %{ "SUBSD $dst,$mem" %}
9879 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
9880 ins_pipe( pipe_slow );
9881 %}
9883 // Mul two double precision floating point values in xmm
9884 instruct mulXD_reg(regXD dst, regXD src) %{
9885 predicate(UseSSE>=2);
9886 match(Set dst (MulD dst src));
9887 format %{ "MULSD $dst,$src" %}
9888 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
9889 ins_pipe( pipe_slow );
9890 %}
9892 instruct mulXD_imm(regXD dst, immXD con) %{
9893 predicate(UseSSE>=2);
9894 match(Set dst (MulD dst con));
9895 format %{ "MULSD $dst,[$con]" %}
9896 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
9897 ins_pipe( pipe_slow );
9898 %}
9900 instruct mulXD_mem(regXD dst, memory mem) %{
9901 predicate(UseSSE>=2);
9902 match(Set dst (MulD dst (LoadD mem)));
9903 format %{ "MULSD $dst,$mem" %}
9904 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
9905 ins_pipe( pipe_slow );
9906 %}
9908 // Div two double precision floating point values in xmm
9909 instruct divXD_reg(regXD dst, regXD src) %{
9910 predicate(UseSSE>=2);
9911 match(Set dst (DivD dst src));
9912 format %{ "DIVSD $dst,$src" %}
9913 opcode(0xF2, 0x0F, 0x5E);
9914 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
9915 ins_pipe( pipe_slow );
9916 %}
9918 instruct divXD_imm(regXD dst, immXD con) %{
9919 predicate(UseSSE>=2);
9920 match(Set dst (DivD dst con));
9921 format %{ "DIVSD $dst,[$con]" %}
9922 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
9923 ins_pipe( pipe_slow );
9924 %}
9926 instruct divXD_mem(regXD dst, memory mem) %{
9927 predicate(UseSSE>=2);
9928 match(Set dst (DivD dst (LoadD mem)));
9929 format %{ "DIVSD $dst,$mem" %}
9930 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
9931 ins_pipe( pipe_slow );
9932 %}
9935 instruct mulD_reg(regD dst, regD src) %{
9936 predicate(UseSSE<=1);
9937 match(Set dst (MulD dst src));
9938 format %{ "FLD $src\n\t"
9939 "DMULp $dst,ST" %}
9940 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9941 ins_cost(150);
9942 ins_encode( Push_Reg_D(src),
9943 OpcP, RegOpc(dst) );
9944 ins_pipe( fpu_reg_reg );
9945 %}
9947 // Strict FP instruction biases argument before multiply then
9948 // biases result to avoid double rounding of subnormals.
9949 //
9950 // scale arg1 by multiplying arg1 by 2^(-15360)
9951 // load arg2
9952 // multiply scaled arg1 by arg2
9953 // rescale product by 2^(15360)
9954 //
9955 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
9956 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9957 match(Set dst (MulD dst src));
9958 ins_cost(1); // Select this instruction for all strict FP double multiplies
9960 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9961 "DMULp $dst,ST\n\t"
9962 "FLD $src\n\t"
9963 "DMULp $dst,ST\n\t"
9964 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9965 "DMULp $dst,ST\n\t" %}
9966 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9967 ins_encode( strictfp_bias1(dst),
9968 Push_Reg_D(src),
9969 OpcP, RegOpc(dst),
9970 strictfp_bias2(dst) );
9971 ins_pipe( fpu_reg_reg );
9972 %}
9974 instruct mulD_reg_imm(regD dst, immD src) %{
9975 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9976 match(Set dst (MulD dst src));
9977 ins_cost(200);
9978 format %{ "FLD_D [$src]\n\t"
9979 "DMULp $dst,ST" %}
9980 opcode(0xDE, 0x1); /* DE /1 */
9981 ins_encode( LdImmD(src),
9982 OpcP, RegOpc(dst) );
9983 ins_pipe( fpu_reg_mem );
9984 %}
9987 instruct mulD_reg_mem(regD dst, memory src) %{
9988 predicate( UseSSE<=1 );
9989 match(Set dst (MulD dst (LoadD src)));
9990 ins_cost(200);
9991 format %{ "FLD_D $src\n\t"
9992 "DMULp $dst,ST" %}
9993 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9994 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9995 OpcP, RegOpc(dst) );
9996 ins_pipe( fpu_reg_mem );
9997 %}
9999 //
10000 // Cisc-alternate to reg-reg multiply
10001 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10002 predicate( UseSSE<=1 );
10003 match(Set dst (MulD src (LoadD mem)));
10004 ins_cost(250);
10005 format %{ "FLD_D $mem\n\t"
10006 "DMUL ST,$src\n\t"
10007 "FSTP_D $dst" %}
10008 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10009 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10010 OpcReg_F(src),
10011 Pop_Reg_D(dst) );
10012 ins_pipe( fpu_reg_reg_mem );
10013 %}
10016 // MACRO3 -- addD a mulD
10017 // This instruction is a '2-address' instruction in that the result goes
10018 // back to src2. This eliminates a move from the macro; possibly the
10019 // register allocator will have to add it back (and maybe not).
10020 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10021 predicate( UseSSE<=1 );
10022 match(Set src2 (AddD (MulD src0 src1) src2));
10023 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10024 "DMUL ST,$src1\n\t"
10025 "DADDp $src2,ST" %}
10026 ins_cost(250);
10027 opcode(0xDD); /* LoadD DD /0 */
10028 ins_encode( Push_Reg_F(src0),
10029 FMul_ST_reg(src1),
10030 FAddP_reg_ST(src2) );
10031 ins_pipe( fpu_reg_reg_reg );
10032 %}
10035 // MACRO3 -- subD a mulD
10036 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10037 predicate( UseSSE<=1 );
10038 match(Set src2 (SubD (MulD src0 src1) src2));
10039 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10040 "DMUL ST,$src1\n\t"
10041 "DSUBRp $src2,ST" %}
10042 ins_cost(250);
10043 ins_encode( Push_Reg_F(src0),
10044 FMul_ST_reg(src1),
10045 Opcode(0xDE), Opc_plus(0xE0,src2));
10046 ins_pipe( fpu_reg_reg_reg );
10047 %}
10050 instruct divD_reg(regD dst, regD src) %{
10051 predicate( UseSSE<=1 );
10052 match(Set dst (DivD dst src));
10054 format %{ "FLD $src\n\t"
10055 "FDIVp $dst,ST" %}
10056 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10057 ins_cost(150);
10058 ins_encode( Push_Reg_D(src),
10059 OpcP, RegOpc(dst) );
10060 ins_pipe( fpu_reg_reg );
10061 %}
10063 // Strict FP instruction biases argument before division then
10064 // biases result, to avoid double rounding of subnormals.
10065 //
10066 // scale dividend by multiplying dividend by 2^(-15360)
10067 // load divisor
10068 // divide scaled dividend by divisor
10069 // rescale quotient by 2^(15360)
10070 //
10071 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10072 predicate (UseSSE<=1);
10073 match(Set dst (DivD dst src));
10074 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10075 ins_cost(01);
10077 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10078 "DMULp $dst,ST\n\t"
10079 "FLD $src\n\t"
10080 "FDIVp $dst,ST\n\t"
10081 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10082 "DMULp $dst,ST\n\t" %}
10083 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10084 ins_encode( strictfp_bias1(dst),
10085 Push_Reg_D(src),
10086 OpcP, RegOpc(dst),
10087 strictfp_bias2(dst) );
10088 ins_pipe( fpu_reg_reg );
10089 %}
10091 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10092 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10093 match(Set dst (RoundDouble (DivD src1 src2)));
10095 format %{ "FLD $src1\n\t"
10096 "FDIV ST,$src2\n\t"
10097 "FSTP_D $dst\t# D-round" %}
10098 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10099 ins_encode( Push_Reg_D(src1),
10100 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10101 ins_pipe( fpu_mem_reg_reg );
10102 %}
10105 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10106 predicate(UseSSE<=1);
10107 match(Set dst (ModD dst src));
10108 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10110 format %{ "DMOD $dst,$src" %}
10111 ins_cost(250);
10112 ins_encode(Push_Reg_Mod_D(dst, src),
10113 emitModD(),
10114 Push_Result_Mod_D(src),
10115 Pop_Reg_D(dst));
10116 ins_pipe( pipe_slow );
10117 %}
10119 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10120 predicate(UseSSE>=2);
10121 match(Set dst (ModD src0 src1));
10122 effect(KILL rax, KILL cr);
10124 format %{ "SUB ESP,8\t # DMOD\n"
10125 "\tMOVSD [ESP+0],$src1\n"
10126 "\tFLD_D [ESP+0]\n"
10127 "\tMOVSD [ESP+0],$src0\n"
10128 "\tFLD_D [ESP+0]\n"
10129 "loop:\tFPREM\n"
10130 "\tFWAIT\n"
10131 "\tFNSTSW AX\n"
10132 "\tSAHF\n"
10133 "\tJP loop\n"
10134 "\tFSTP_D [ESP+0]\n"
10135 "\tMOVSD $dst,[ESP+0]\n"
10136 "\tADD ESP,8\n"
10137 "\tFSTP ST0\t # Restore FPU Stack"
10138 %}
10139 ins_cost(250);
10140 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10141 ins_pipe( pipe_slow );
10142 %}
10144 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10145 predicate (UseSSE<=1);
10146 match(Set dst (SinD src));
10147 ins_cost(1800);
10148 format %{ "DSIN $dst" %}
10149 opcode(0xD9, 0xFE);
10150 ins_encode( OpcP, OpcS );
10151 ins_pipe( pipe_slow );
10152 %}
10154 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10155 predicate (UseSSE>=2);
10156 match(Set dst (SinD dst));
10157 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10158 ins_cost(1800);
10159 format %{ "DSIN $dst" %}
10160 opcode(0xD9, 0xFE);
10161 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10162 ins_pipe( pipe_slow );
10163 %}
10165 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10166 predicate (UseSSE<=1);
10167 match(Set dst (CosD src));
10168 ins_cost(1800);
10169 format %{ "DCOS $dst" %}
10170 opcode(0xD9, 0xFF);
10171 ins_encode( OpcP, OpcS );
10172 ins_pipe( pipe_slow );
10173 %}
10175 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10176 predicate (UseSSE>=2);
10177 match(Set dst (CosD dst));
10178 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10179 ins_cost(1800);
10180 format %{ "DCOS $dst" %}
10181 opcode(0xD9, 0xFF);
10182 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10183 ins_pipe( pipe_slow );
10184 %}
10186 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10187 predicate (UseSSE<=1);
10188 match(Set dst(TanD src));
10189 format %{ "DTAN $dst" %}
10190 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10191 Opcode(0xDD), Opcode(0xD8)); // fstp st
10192 ins_pipe( pipe_slow );
10193 %}
10195 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10196 predicate (UseSSE>=2);
10197 match(Set dst(TanD dst));
10198 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10199 format %{ "DTAN $dst" %}
10200 ins_encode( Push_SrcXD(dst),
10201 Opcode(0xD9), Opcode(0xF2), // fptan
10202 Opcode(0xDD), Opcode(0xD8), // fstp st
10203 Push_ResultXD(dst) );
10204 ins_pipe( pipe_slow );
10205 %}
10207 instruct atanD_reg(regD dst, regD src) %{
10208 predicate (UseSSE<=1);
10209 match(Set dst(AtanD dst src));
10210 format %{ "DATA $dst,$src" %}
10211 opcode(0xD9, 0xF3);
10212 ins_encode( Push_Reg_D(src),
10213 OpcP, OpcS, RegOpc(dst) );
10214 ins_pipe( pipe_slow );
10215 %}
10217 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10218 predicate (UseSSE>=2);
10219 match(Set dst(AtanD dst src));
10220 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10221 format %{ "DATA $dst,$src" %}
10222 opcode(0xD9, 0xF3);
10223 ins_encode( Push_SrcXD(src),
10224 OpcP, OpcS, Push_ResultXD(dst) );
10225 ins_pipe( pipe_slow );
10226 %}
10228 instruct sqrtD_reg(regD dst, regD src) %{
10229 predicate (UseSSE<=1);
10230 match(Set dst (SqrtD src));
10231 format %{ "DSQRT $dst,$src" %}
10232 opcode(0xFA, 0xD9);
10233 ins_encode( Push_Reg_D(src),
10234 OpcS, OpcP, Pop_Reg_D(dst) );
10235 ins_pipe( pipe_slow );
10236 %}
10238 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10239 predicate (UseSSE<=1);
10240 match(Set Y (PowD X Y)); // Raise X to the Yth power
10241 effect(KILL rax, KILL rbx, KILL rcx);
10242 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10243 "FLD_D $X\n\t"
10244 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10246 "FDUP \t\t\t# Q Q\n\t"
10247 "FRNDINT\t\t\t# int(Q) Q\n\t"
10248 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10249 "FISTP dword [ESP]\n\t"
10250 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10251 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10252 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10253 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10254 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10255 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10256 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10257 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10258 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10259 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10260 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10261 "MOV [ESP+0],0\n\t"
10262 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10264 "ADD ESP,8"
10265 %}
10266 ins_encode( push_stack_temp_qword,
10267 Push_Reg_D(X),
10268 Opcode(0xD9), Opcode(0xF1), // fyl2x
10269 pow_exp_core_encoding,
10270 pop_stack_temp_qword);
10271 ins_pipe( pipe_slow );
10272 %}
10274 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10275 predicate (UseSSE>=2);
10276 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10277 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10278 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10279 "MOVSD [ESP],$src1\n\t"
10280 "FLD FPR1,$src1\n\t"
10281 "MOVSD [ESP],$src0\n\t"
10282 "FLD FPR1,$src0\n\t"
10283 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10285 "FDUP \t\t\t# Q Q\n\t"
10286 "FRNDINT\t\t\t# int(Q) Q\n\t"
10287 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10288 "FISTP dword [ESP]\n\t"
10289 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10290 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10291 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10292 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10293 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10294 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10295 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10296 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10297 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10298 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10299 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10300 "MOV [ESP+0],0\n\t"
10301 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10303 "FST_D [ESP]\n\t"
10304 "MOVSD $dst,[ESP]\n\t"
10305 "ADD ESP,8"
10306 %}
10307 ins_encode( push_stack_temp_qword,
10308 push_xmm_to_fpr1(src1),
10309 push_xmm_to_fpr1(src0),
10310 Opcode(0xD9), Opcode(0xF1), // fyl2x
10311 pow_exp_core_encoding,
10312 Push_ResultXD(dst) );
10313 ins_pipe( pipe_slow );
10314 %}
10317 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10318 predicate (UseSSE<=1);
10319 match(Set dpr1 (ExpD dpr1));
10320 effect(KILL rax, KILL rbx, KILL rcx);
10321 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10322 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10323 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10325 "FDUP \t\t\t# Q Q\n\t"
10326 "FRNDINT\t\t\t# int(Q) Q\n\t"
10327 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10328 "FISTP dword [ESP]\n\t"
10329 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10330 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10331 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10332 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10333 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10334 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10335 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10336 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10337 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10338 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10339 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10340 "MOV [ESP+0],0\n\t"
10341 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10343 "ADD ESP,8"
10344 %}
10345 ins_encode( push_stack_temp_qword,
10346 Opcode(0xD9), Opcode(0xEA), // fldl2e
10347 Opcode(0xDE), Opcode(0xC9), // fmulp
10348 pow_exp_core_encoding,
10349 pop_stack_temp_qword);
10350 ins_pipe( pipe_slow );
10351 %}
10353 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10354 predicate (UseSSE>=2);
10355 match(Set dst (ExpD src));
10356 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10357 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10358 "MOVSD [ESP],$src\n\t"
10359 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10360 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10362 "FDUP \t\t\t# Q Q\n\t"
10363 "FRNDINT\t\t\t# int(Q) Q\n\t"
10364 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10365 "FISTP dword [ESP]\n\t"
10366 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10367 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10368 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10369 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10370 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10371 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10372 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10373 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10374 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10375 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10376 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10377 "MOV [ESP+0],0\n\t"
10378 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10380 "FST_D [ESP]\n\t"
10381 "MOVSD $dst,[ESP]\n\t"
10382 "ADD ESP,8"
10383 %}
10384 ins_encode( Push_SrcXD(src),
10385 Opcode(0xD9), Opcode(0xEA), // fldl2e
10386 Opcode(0xDE), Opcode(0xC9), // fmulp
10387 pow_exp_core_encoding,
10388 Push_ResultXD(dst) );
10389 ins_pipe( pipe_slow );
10390 %}
10394 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10395 predicate (UseSSE<=1);
10396 // The source Double operand on FPU stack
10397 match(Set dst (Log10D src));
10398 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10399 // fxch ; swap ST(0) with ST(1)
10400 // fyl2x ; compute log_10(2) * log_2(x)
10401 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10402 "FXCH \n\t"
10403 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10404 %}
10405 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10406 Opcode(0xD9), Opcode(0xC9), // fxch
10407 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10409 ins_pipe( pipe_slow );
10410 %}
10412 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10413 predicate (UseSSE>=2);
10414 effect(KILL cr);
10415 match(Set dst (Log10D src));
10416 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10417 // fyl2x ; compute log_10(2) * log_2(x)
10418 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10419 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10420 %}
10421 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10422 Push_SrcXD(src),
10423 Opcode(0xD9), Opcode(0xF1), // fyl2x
10424 Push_ResultXD(dst));
10426 ins_pipe( pipe_slow );
10427 %}
10429 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10430 predicate (UseSSE<=1);
10431 // The source Double operand on FPU stack
10432 match(Set dst (LogD src));
10433 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10434 // fxch ; swap ST(0) with ST(1)
10435 // fyl2x ; compute log_e(2) * log_2(x)
10436 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10437 "FXCH \n\t"
10438 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10439 %}
10440 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10441 Opcode(0xD9), Opcode(0xC9), // fxch
10442 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10444 ins_pipe( pipe_slow );
10445 %}
10447 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10448 predicate (UseSSE>=2);
10449 effect(KILL cr);
10450 // The source and result Double operands in XMM registers
10451 match(Set dst (LogD src));
10452 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10453 // fyl2x ; compute log_e(2) * log_2(x)
10454 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10455 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10456 %}
10457 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10458 Push_SrcXD(src),
10459 Opcode(0xD9), Opcode(0xF1), // fyl2x
10460 Push_ResultXD(dst));
10461 ins_pipe( pipe_slow );
10462 %}
10464 //-------------Float Instructions-------------------------------
10465 // Float Math
10467 // Code for float compare:
10468 // fcompp();
10469 // fwait(); fnstsw_ax();
10470 // sahf();
10471 // movl(dst, unordered_result);
10472 // jcc(Assembler::parity, exit);
10473 // movl(dst, less_result);
10474 // jcc(Assembler::below, exit);
10475 // movl(dst, equal_result);
10476 // jcc(Assembler::equal, exit);
10477 // movl(dst, greater_result);
10478 // exit:
10480 // P6 version of float compare, sets condition codes in EFLAGS
10481 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10482 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10483 match(Set cr (CmpF src1 src2));
10484 effect(KILL rax);
10485 ins_cost(150);
10486 format %{ "FLD $src1\n\t"
10487 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10488 "JNP exit\n\t"
10489 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10490 "SAHF\n"
10491 "exit:\tNOP // avoid branch to branch" %}
10492 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10493 ins_encode( Push_Reg_D(src1),
10494 OpcP, RegOpc(src2),
10495 cmpF_P6_fixup );
10496 ins_pipe( pipe_slow );
10497 %}
10499 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10500 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10501 match(Set cr (CmpF src1 src2));
10502 ins_cost(100);
10503 format %{ "FLD $src1\n\t"
10504 "FUCOMIP ST,$src2 // P6 instruction" %}
10505 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10506 ins_encode( Push_Reg_D(src1),
10507 OpcP, RegOpc(src2));
10508 ins_pipe( pipe_slow );
10509 %}
10512 // Compare & branch
10513 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10514 predicate(UseSSE == 0);
10515 match(Set cr (CmpF src1 src2));
10516 effect(KILL rax);
10517 ins_cost(200);
10518 format %{ "FLD $src1\n\t"
10519 "FCOMp $src2\n\t"
10520 "FNSTSW AX\n\t"
10521 "TEST AX,0x400\n\t"
10522 "JZ,s flags\n\t"
10523 "MOV AH,1\t# unordered treat as LT\n"
10524 "flags:\tSAHF" %}
10525 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10526 ins_encode( Push_Reg_D(src1),
10527 OpcP, RegOpc(src2),
10528 fpu_flags);
10529 ins_pipe( pipe_slow );
10530 %}
10532 // Compare vs zero into -1,0,1
10533 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10534 predicate(UseSSE == 0);
10535 match(Set dst (CmpF3 src1 zero));
10536 effect(KILL cr, KILL rax);
10537 ins_cost(280);
10538 format %{ "FTSTF $dst,$src1" %}
10539 opcode(0xE4, 0xD9);
10540 ins_encode( Push_Reg_D(src1),
10541 OpcS, OpcP, PopFPU,
10542 CmpF_Result(dst));
10543 ins_pipe( pipe_slow );
10544 %}
10546 // Compare into -1,0,1
10547 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10548 predicate(UseSSE == 0);
10549 match(Set dst (CmpF3 src1 src2));
10550 effect(KILL cr, KILL rax);
10551 ins_cost(300);
10552 format %{ "FCMPF $dst,$src1,$src2" %}
10553 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10554 ins_encode( Push_Reg_D(src1),
10555 OpcP, RegOpc(src2),
10556 CmpF_Result(dst));
10557 ins_pipe( pipe_slow );
10558 %}
10560 // float compare and set condition codes in EFLAGS by XMM regs
10561 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10562 predicate(UseSSE>=1);
10563 match(Set cr (CmpF dst src));
10564 effect(KILL rax);
10565 ins_cost(145);
10566 format %{ "COMISS $dst,$src\n"
10567 "\tJNP exit\n"
10568 "\tMOV ah,1 // saw a NaN, set CF\n"
10569 "\tSAHF\n"
10570 "exit:\tNOP // avoid branch to branch" %}
10571 opcode(0x0F, 0x2F);
10572 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10573 ins_pipe( pipe_slow );
10574 %}
10576 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10577 predicate(UseSSE>=1);
10578 match(Set cr (CmpF dst src));
10579 ins_cost(100);
10580 format %{ "COMISS $dst,$src" %}
10581 opcode(0x0F, 0x2F);
10582 ins_encode(OpcP, OpcS, RegReg(dst, src));
10583 ins_pipe( pipe_slow );
10584 %}
10586 // float compare and set condition codes in EFLAGS by XMM regs
10587 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10588 predicate(UseSSE>=1);
10589 match(Set cr (CmpF dst (LoadF src)));
10590 effect(KILL rax);
10591 ins_cost(165);
10592 format %{ "COMISS $dst,$src\n"
10593 "\tJNP exit\n"
10594 "\tMOV ah,1 // saw a NaN, set CF\n"
10595 "\tSAHF\n"
10596 "exit:\tNOP // avoid branch to branch" %}
10597 opcode(0x0F, 0x2F);
10598 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10599 ins_pipe( pipe_slow );
10600 %}
10602 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10603 predicate(UseSSE>=1);
10604 match(Set cr (CmpF dst (LoadF src)));
10605 ins_cost(100);
10606 format %{ "COMISS $dst,$src" %}
10607 opcode(0x0F, 0x2F);
10608 ins_encode(OpcP, OpcS, RegMem(dst, src));
10609 ins_pipe( pipe_slow );
10610 %}
10612 // Compare into -1,0,1 in XMM
10613 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10614 predicate(UseSSE>=1);
10615 match(Set dst (CmpF3 src1 src2));
10616 effect(KILL cr);
10617 ins_cost(255);
10618 format %{ "XOR $dst,$dst\n"
10619 "\tCOMISS $src1,$src2\n"
10620 "\tJP,s nan\n"
10621 "\tJEQ,s exit\n"
10622 "\tJA,s inc\n"
10623 "nan:\tDEC $dst\n"
10624 "\tJMP,s exit\n"
10625 "inc:\tINC $dst\n"
10626 "exit:"
10627 %}
10628 opcode(0x0F, 0x2F);
10629 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10630 ins_pipe( pipe_slow );
10631 %}
10633 // Compare into -1,0,1 in XMM and memory
10634 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10635 predicate(UseSSE>=1);
10636 match(Set dst (CmpF3 src1 (LoadF mem)));
10637 effect(KILL cr);
10638 ins_cost(275);
10639 format %{ "COMISS $src1,$mem\n"
10640 "\tMOV $dst,0\t\t# do not blow flags\n"
10641 "\tJP,s nan\n"
10642 "\tJEQ,s exit\n"
10643 "\tJA,s inc\n"
10644 "nan:\tDEC $dst\n"
10645 "\tJMP,s exit\n"
10646 "inc:\tINC $dst\n"
10647 "exit:"
10648 %}
10649 opcode(0x0F, 0x2F);
10650 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10651 ins_pipe( pipe_slow );
10652 %}
10654 // Spill to obtain 24-bit precision
10655 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10656 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10657 match(Set dst (SubF src1 src2));
10659 format %{ "FSUB $dst,$src1 - $src2" %}
10660 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10661 ins_encode( Push_Reg_F(src1),
10662 OpcReg_F(src2),
10663 Pop_Mem_F(dst) );
10664 ins_pipe( fpu_mem_reg_reg );
10665 %}
10666 //
10667 // This instruction does not round to 24-bits
10668 instruct subF_reg(regF dst, regF src) %{
10669 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10670 match(Set dst (SubF dst src));
10672 format %{ "FSUB $dst,$src" %}
10673 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10674 ins_encode( Push_Reg_F(src),
10675 OpcP, RegOpc(dst) );
10676 ins_pipe( fpu_reg_reg );
10677 %}
10679 // Spill to obtain 24-bit precision
10680 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10681 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10682 match(Set dst (AddF src1 src2));
10684 format %{ "FADD $dst,$src1,$src2" %}
10685 opcode(0xD8, 0x0); /* D8 C0+i */
10686 ins_encode( Push_Reg_F(src2),
10687 OpcReg_F(src1),
10688 Pop_Mem_F(dst) );
10689 ins_pipe( fpu_mem_reg_reg );
10690 %}
10691 //
10692 // This instruction does not round to 24-bits
10693 instruct addF_reg(regF dst, regF src) %{
10694 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10695 match(Set dst (AddF dst src));
10697 format %{ "FLD $src\n\t"
10698 "FADDp $dst,ST" %}
10699 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10700 ins_encode( Push_Reg_F(src),
10701 OpcP, RegOpc(dst) );
10702 ins_pipe( fpu_reg_reg );
10703 %}
10705 // Add two single precision floating point values in xmm
10706 instruct addX_reg(regX dst, regX src) %{
10707 predicate(UseSSE>=1);
10708 match(Set dst (AddF dst src));
10709 format %{ "ADDSS $dst,$src" %}
10710 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10711 ins_pipe( pipe_slow );
10712 %}
10714 instruct addX_imm(regX dst, immXF con) %{
10715 predicate(UseSSE>=1);
10716 match(Set dst (AddF dst con));
10717 format %{ "ADDSS $dst,[$con]" %}
10718 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10719 ins_pipe( pipe_slow );
10720 %}
10722 instruct addX_mem(regX dst, memory mem) %{
10723 predicate(UseSSE>=1);
10724 match(Set dst (AddF dst (LoadF mem)));
10725 format %{ "ADDSS $dst,$mem" %}
10726 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10727 ins_pipe( pipe_slow );
10728 %}
10730 // Subtract two single precision floating point values in xmm
10731 instruct subX_reg(regX dst, regX src) %{
10732 predicate(UseSSE>=1);
10733 match(Set dst (SubF dst src));
10734 format %{ "SUBSS $dst,$src" %}
10735 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10736 ins_pipe( pipe_slow );
10737 %}
10739 instruct subX_imm(regX dst, immXF con) %{
10740 predicate(UseSSE>=1);
10741 match(Set dst (SubF dst con));
10742 format %{ "SUBSS $dst,[$con]" %}
10743 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10744 ins_pipe( pipe_slow );
10745 %}
10747 instruct subX_mem(regX dst, memory mem) %{
10748 predicate(UseSSE>=1);
10749 match(Set dst (SubF dst (LoadF mem)));
10750 format %{ "SUBSS $dst,$mem" %}
10751 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10752 ins_pipe( pipe_slow );
10753 %}
10755 // Multiply two single precision floating point values in xmm
10756 instruct mulX_reg(regX dst, regX src) %{
10757 predicate(UseSSE>=1);
10758 match(Set dst (MulF dst src));
10759 format %{ "MULSS $dst,$src" %}
10760 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10761 ins_pipe( pipe_slow );
10762 %}
10764 instruct mulX_imm(regX dst, immXF con) %{
10765 predicate(UseSSE>=1);
10766 match(Set dst (MulF dst con));
10767 format %{ "MULSS $dst,[$con]" %}
10768 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10769 ins_pipe( pipe_slow );
10770 %}
10772 instruct mulX_mem(regX dst, memory mem) %{
10773 predicate(UseSSE>=1);
10774 match(Set dst (MulF dst (LoadF mem)));
10775 format %{ "MULSS $dst,$mem" %}
10776 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10777 ins_pipe( pipe_slow );
10778 %}
10780 // Divide two single precision floating point values in xmm
10781 instruct divX_reg(regX dst, regX src) %{
10782 predicate(UseSSE>=1);
10783 match(Set dst (DivF dst src));
10784 format %{ "DIVSS $dst,$src" %}
10785 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10786 ins_pipe( pipe_slow );
10787 %}
10789 instruct divX_imm(regX dst, immXF con) %{
10790 predicate(UseSSE>=1);
10791 match(Set dst (DivF dst con));
10792 format %{ "DIVSS $dst,[$con]" %}
10793 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
10794 ins_pipe( pipe_slow );
10795 %}
10797 instruct divX_mem(regX dst, memory mem) %{
10798 predicate(UseSSE>=1);
10799 match(Set dst (DivF dst (LoadF mem)));
10800 format %{ "DIVSS $dst,$mem" %}
10801 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10802 ins_pipe( pipe_slow );
10803 %}
10805 // Get the square root of a single precision floating point values in xmm
10806 instruct sqrtX_reg(regX dst, regX src) %{
10807 predicate(UseSSE>=1);
10808 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10809 format %{ "SQRTSS $dst,$src" %}
10810 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10811 ins_pipe( pipe_slow );
10812 %}
10814 instruct sqrtX_mem(regX dst, memory mem) %{
10815 predicate(UseSSE>=1);
10816 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10817 format %{ "SQRTSS $dst,$mem" %}
10818 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10819 ins_pipe( pipe_slow );
10820 %}
10822 // Get the square root of a double precision floating point values in xmm
10823 instruct sqrtXD_reg(regXD dst, regXD src) %{
10824 predicate(UseSSE>=2);
10825 match(Set dst (SqrtD src));
10826 format %{ "SQRTSD $dst,$src" %}
10827 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10828 ins_pipe( pipe_slow );
10829 %}
10831 instruct sqrtXD_mem(regXD dst, memory mem) %{
10832 predicate(UseSSE>=2);
10833 match(Set dst (SqrtD (LoadD mem)));
10834 format %{ "SQRTSD $dst,$mem" %}
10835 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10836 ins_pipe( pipe_slow );
10837 %}
10839 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
10840 predicate(UseSSE==0);
10841 match(Set dst (AbsF src));
10842 ins_cost(100);
10843 format %{ "FABS" %}
10844 opcode(0xE1, 0xD9);
10845 ins_encode( OpcS, OpcP );
10846 ins_pipe( fpu_reg_reg );
10847 %}
10849 instruct absX_reg(regX dst ) %{
10850 predicate(UseSSE>=1);
10851 match(Set dst (AbsF dst));
10852 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
10853 ins_encode( AbsXF_encoding(dst));
10854 ins_pipe( pipe_slow );
10855 %}
10857 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
10858 predicate(UseSSE==0);
10859 match(Set dst (NegF src));
10860 ins_cost(100);
10861 format %{ "FCHS" %}
10862 opcode(0xE0, 0xD9);
10863 ins_encode( OpcS, OpcP );
10864 ins_pipe( fpu_reg_reg );
10865 %}
10867 instruct negX_reg( regX dst ) %{
10868 predicate(UseSSE>=1);
10869 match(Set dst (NegF dst));
10870 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
10871 ins_encode( NegXF_encoding(dst));
10872 ins_pipe( pipe_slow );
10873 %}
10875 // Cisc-alternate to addF_reg
10876 // Spill to obtain 24-bit precision
10877 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10878 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10879 match(Set dst (AddF src1 (LoadF src2)));
10881 format %{ "FLD $src2\n\t"
10882 "FADD ST,$src1\n\t"
10883 "FSTP_S $dst" %}
10884 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10885 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10886 OpcReg_F(src1),
10887 Pop_Mem_F(dst) );
10888 ins_pipe( fpu_mem_reg_mem );
10889 %}
10890 //
10891 // Cisc-alternate to addF_reg
10892 // This instruction does not round to 24-bits
10893 instruct addF_reg_mem(regF dst, memory src) %{
10894 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10895 match(Set dst (AddF dst (LoadF src)));
10897 format %{ "FADD $dst,$src" %}
10898 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10899 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10900 OpcP, RegOpc(dst) );
10901 ins_pipe( fpu_reg_mem );
10902 %}
10904 // // Following two instructions for _222_mpegaudio
10905 // Spill to obtain 24-bit precision
10906 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
10907 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10908 match(Set dst (AddF src1 src2));
10910 format %{ "FADD $dst,$src1,$src2" %}
10911 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10912 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10913 OpcReg_F(src2),
10914 Pop_Mem_F(dst) );
10915 ins_pipe( fpu_mem_reg_mem );
10916 %}
10918 // Cisc-spill variant
10919 // Spill to obtain 24-bit precision
10920 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10921 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10922 match(Set dst (AddF src1 (LoadF src2)));
10924 format %{ "FADD $dst,$src1,$src2 cisc" %}
10925 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10926 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10927 set_instruction_start,
10928 OpcP, RMopc_Mem(secondary,src1),
10929 Pop_Mem_F(dst) );
10930 ins_pipe( fpu_mem_mem_mem );
10931 %}
10933 // Spill to obtain 24-bit precision
10934 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10935 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10936 match(Set dst (AddF src1 src2));
10938 format %{ "FADD $dst,$src1,$src2" %}
10939 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10940 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10941 set_instruction_start,
10942 OpcP, RMopc_Mem(secondary,src1),
10943 Pop_Mem_F(dst) );
10944 ins_pipe( fpu_mem_mem_mem );
10945 %}
10948 // Spill to obtain 24-bit precision
10949 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10950 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10951 match(Set dst (AddF src1 src2));
10952 format %{ "FLD $src1\n\t"
10953 "FADD $src2\n\t"
10954 "FSTP_S $dst" %}
10955 opcode(0xD8, 0x00); /* D8 /0 */
10956 ins_encode( Push_Reg_F(src1),
10957 Opc_MemImm_F(src2),
10958 Pop_Mem_F(dst));
10959 ins_pipe( fpu_mem_reg_con );
10960 %}
10961 //
10962 // This instruction does not round to 24-bits
10963 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
10964 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10965 match(Set dst (AddF src1 src2));
10966 format %{ "FLD $src1\n\t"
10967 "FADD $src2\n\t"
10968 "FSTP_S $dst" %}
10969 opcode(0xD8, 0x00); /* D8 /0 */
10970 ins_encode( Push_Reg_F(src1),
10971 Opc_MemImm_F(src2),
10972 Pop_Reg_F(dst));
10973 ins_pipe( fpu_reg_reg_con );
10974 %}
10976 // Spill to obtain 24-bit precision
10977 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
10978 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10979 match(Set dst (MulF src1 src2));
10981 format %{ "FLD $src1\n\t"
10982 "FMUL $src2\n\t"
10983 "FSTP_S $dst" %}
10984 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10985 ins_encode( Push_Reg_F(src1),
10986 OpcReg_F(src2),
10987 Pop_Mem_F(dst) );
10988 ins_pipe( fpu_mem_reg_reg );
10989 %}
10990 //
10991 // This instruction does not round to 24-bits
10992 instruct mulF_reg(regF dst, regF src1, regF src2) %{
10993 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10994 match(Set dst (MulF src1 src2));
10996 format %{ "FLD $src1\n\t"
10997 "FMUL $src2\n\t"
10998 "FSTP_S $dst" %}
10999 opcode(0xD8, 0x1); /* D8 C8+i */
11000 ins_encode( Push_Reg_F(src2),
11001 OpcReg_F(src1),
11002 Pop_Reg_F(dst) );
11003 ins_pipe( fpu_reg_reg_reg );
11004 %}
11007 // Spill to obtain 24-bit precision
11008 // Cisc-alternate to reg-reg multiply
11009 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11010 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11011 match(Set dst (MulF src1 (LoadF src2)));
11013 format %{ "FLD_S $src2\n\t"
11014 "FMUL $src1\n\t"
11015 "FSTP_S $dst" %}
11016 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11017 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11018 OpcReg_F(src1),
11019 Pop_Mem_F(dst) );
11020 ins_pipe( fpu_mem_reg_mem );
11021 %}
11022 //
11023 // This instruction does not round to 24-bits
11024 // Cisc-alternate to reg-reg multiply
11025 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11026 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11027 match(Set dst (MulF src1 (LoadF src2)));
11029 format %{ "FMUL $dst,$src1,$src2" %}
11030 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11031 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11032 OpcReg_F(src1),
11033 Pop_Reg_F(dst) );
11034 ins_pipe( fpu_reg_reg_mem );
11035 %}
11037 // Spill to obtain 24-bit precision
11038 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11039 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11040 match(Set dst (MulF src1 src2));
11042 format %{ "FMUL $dst,$src1,$src2" %}
11043 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11044 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11045 set_instruction_start,
11046 OpcP, RMopc_Mem(secondary,src1),
11047 Pop_Mem_F(dst) );
11048 ins_pipe( fpu_mem_mem_mem );
11049 %}
11051 // Spill to obtain 24-bit precision
11052 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11053 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11054 match(Set dst (MulF src1 src2));
11056 format %{ "FMULc $dst,$src1,$src2" %}
11057 opcode(0xD8, 0x1); /* D8 /1*/
11058 ins_encode( Push_Reg_F(src1),
11059 Opc_MemImm_F(src2),
11060 Pop_Mem_F(dst));
11061 ins_pipe( fpu_mem_reg_con );
11062 %}
11063 //
11064 // This instruction does not round to 24-bits
11065 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11066 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11067 match(Set dst (MulF src1 src2));
11069 format %{ "FMULc $dst. $src1, $src2" %}
11070 opcode(0xD8, 0x1); /* D8 /1*/
11071 ins_encode( Push_Reg_F(src1),
11072 Opc_MemImm_F(src2),
11073 Pop_Reg_F(dst));
11074 ins_pipe( fpu_reg_reg_con );
11075 %}
11078 //
11079 // MACRO1 -- subsume unshared load into mulF
11080 // This instruction does not round to 24-bits
11081 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11082 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11083 match(Set dst (MulF (LoadF mem1) src));
11085 format %{ "FLD $mem1 ===MACRO1===\n\t"
11086 "FMUL ST,$src\n\t"
11087 "FSTP $dst" %}
11088 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11089 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11090 OpcReg_F(src),
11091 Pop_Reg_F(dst) );
11092 ins_pipe( fpu_reg_reg_mem );
11093 %}
11094 //
11095 // MACRO2 -- addF a mulF which subsumed an unshared load
11096 // This instruction does not round to 24-bits
11097 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11098 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11099 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11100 ins_cost(95);
11102 format %{ "FLD $mem1 ===MACRO2===\n\t"
11103 "FMUL ST,$src1 subsume mulF left load\n\t"
11104 "FADD ST,$src2\n\t"
11105 "FSTP $dst" %}
11106 opcode(0xD9); /* LoadF D9 /0 */
11107 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11108 FMul_ST_reg(src1),
11109 FAdd_ST_reg(src2),
11110 Pop_Reg_F(dst) );
11111 ins_pipe( fpu_reg_mem_reg_reg );
11112 %}
11114 // MACRO3 -- addF a mulF
11115 // This instruction does not round to 24-bits. It is a '2-address'
11116 // instruction in that the result goes back to src2. This eliminates
11117 // a move from the macro; possibly the register allocator will have
11118 // to add it back (and maybe not).
11119 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11120 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11121 match(Set src2 (AddF (MulF src0 src1) src2));
11123 format %{ "FLD $src0 ===MACRO3===\n\t"
11124 "FMUL ST,$src1\n\t"
11125 "FADDP $src2,ST" %}
11126 opcode(0xD9); /* LoadF D9 /0 */
11127 ins_encode( Push_Reg_F(src0),
11128 FMul_ST_reg(src1),
11129 FAddP_reg_ST(src2) );
11130 ins_pipe( fpu_reg_reg_reg );
11131 %}
11133 // MACRO4 -- divF subF
11134 // This instruction does not round to 24-bits
11135 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11136 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11137 match(Set dst (DivF (SubF src2 src1) src3));
11139 format %{ "FLD $src2 ===MACRO4===\n\t"
11140 "FSUB ST,$src1\n\t"
11141 "FDIV ST,$src3\n\t"
11142 "FSTP $dst" %}
11143 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11144 ins_encode( Push_Reg_F(src2),
11145 subF_divF_encode(src1,src3),
11146 Pop_Reg_F(dst) );
11147 ins_pipe( fpu_reg_reg_reg_reg );
11148 %}
11150 // Spill to obtain 24-bit precision
11151 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11152 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11153 match(Set dst (DivF src1 src2));
11155 format %{ "FDIV $dst,$src1,$src2" %}
11156 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11157 ins_encode( Push_Reg_F(src1),
11158 OpcReg_F(src2),
11159 Pop_Mem_F(dst) );
11160 ins_pipe( fpu_mem_reg_reg );
11161 %}
11162 //
11163 // This instruction does not round to 24-bits
11164 instruct divF_reg(regF dst, regF src) %{
11165 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11166 match(Set dst (DivF dst src));
11168 format %{ "FDIV $dst,$src" %}
11169 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11170 ins_encode( Push_Reg_F(src),
11171 OpcP, RegOpc(dst) );
11172 ins_pipe( fpu_reg_reg );
11173 %}
11176 // Spill to obtain 24-bit precision
11177 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11178 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11179 match(Set dst (ModF src1 src2));
11180 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11182 format %{ "FMOD $dst,$src1,$src2" %}
11183 ins_encode( Push_Reg_Mod_D(src1, src2),
11184 emitModD(),
11185 Push_Result_Mod_D(src2),
11186 Pop_Mem_F(dst));
11187 ins_pipe( pipe_slow );
11188 %}
11189 //
11190 // This instruction does not round to 24-bits
11191 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11192 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11193 match(Set dst (ModF dst src));
11194 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11196 format %{ "FMOD $dst,$src" %}
11197 ins_encode(Push_Reg_Mod_D(dst, src),
11198 emitModD(),
11199 Push_Result_Mod_D(src),
11200 Pop_Reg_F(dst));
11201 ins_pipe( pipe_slow );
11202 %}
11204 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11205 predicate(UseSSE>=1);
11206 match(Set dst (ModF src0 src1));
11207 effect(KILL rax, KILL cr);
11208 format %{ "SUB ESP,4\t # FMOD\n"
11209 "\tMOVSS [ESP+0],$src1\n"
11210 "\tFLD_S [ESP+0]\n"
11211 "\tMOVSS [ESP+0],$src0\n"
11212 "\tFLD_S [ESP+0]\n"
11213 "loop:\tFPREM\n"
11214 "\tFWAIT\n"
11215 "\tFNSTSW AX\n"
11216 "\tSAHF\n"
11217 "\tJP loop\n"
11218 "\tFSTP_S [ESP+0]\n"
11219 "\tMOVSS $dst,[ESP+0]\n"
11220 "\tADD ESP,4\n"
11221 "\tFSTP ST0\t # Restore FPU Stack"
11222 %}
11223 ins_cost(250);
11224 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11225 ins_pipe( pipe_slow );
11226 %}
11229 //----------Arithmetic Conversion Instructions---------------------------------
11230 // The conversions operations are all Alpha sorted. Please keep it that way!
11232 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11233 predicate(UseSSE==0);
11234 match(Set dst (RoundFloat src));
11235 ins_cost(125);
11236 format %{ "FST_S $dst,$src\t# F-round" %}
11237 ins_encode( Pop_Mem_Reg_F(dst, src) );
11238 ins_pipe( fpu_mem_reg );
11239 %}
11241 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11242 predicate(UseSSE<=1);
11243 match(Set dst (RoundDouble src));
11244 ins_cost(125);
11245 format %{ "FST_D $dst,$src\t# D-round" %}
11246 ins_encode( Pop_Mem_Reg_D(dst, src) );
11247 ins_pipe( fpu_mem_reg );
11248 %}
11250 // Force rounding to 24-bit precision and 6-bit exponent
11251 instruct convD2F_reg(stackSlotF dst, regD src) %{
11252 predicate(UseSSE==0);
11253 match(Set dst (ConvD2F src));
11254 format %{ "FST_S $dst,$src\t# F-round" %}
11255 expand %{
11256 roundFloat_mem_reg(dst,src);
11257 %}
11258 %}
11260 // Force rounding to 24-bit precision and 6-bit exponent
11261 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11262 predicate(UseSSE==1);
11263 match(Set dst (ConvD2F src));
11264 effect( KILL cr );
11265 format %{ "SUB ESP,4\n\t"
11266 "FST_S [ESP],$src\t# F-round\n\t"
11267 "MOVSS $dst,[ESP]\n\t"
11268 "ADD ESP,4" %}
11269 ins_encode( D2X_encoding(dst, src) );
11270 ins_pipe( pipe_slow );
11271 %}
11273 // Force rounding double precision to single precision
11274 instruct convXD2X_reg(regX dst, regXD src) %{
11275 predicate(UseSSE>=2);
11276 match(Set dst (ConvD2F src));
11277 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11278 opcode(0xF2, 0x0F, 0x5A);
11279 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11280 ins_pipe( pipe_slow );
11281 %}
11283 instruct convF2D_reg_reg(regD dst, regF src) %{
11284 predicate(UseSSE==0);
11285 match(Set dst (ConvF2D src));
11286 format %{ "FST_S $dst,$src\t# D-round" %}
11287 ins_encode( Pop_Reg_Reg_D(dst, src));
11288 ins_pipe( fpu_reg_reg );
11289 %}
11291 instruct convF2D_reg(stackSlotD dst, regF src) %{
11292 predicate(UseSSE==1);
11293 match(Set dst (ConvF2D src));
11294 format %{ "FST_D $dst,$src\t# D-round" %}
11295 expand %{
11296 roundDouble_mem_reg(dst,src);
11297 %}
11298 %}
11300 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11301 predicate(UseSSE==1);
11302 match(Set dst (ConvF2D src));
11303 effect( KILL cr );
11304 format %{ "SUB ESP,4\n\t"
11305 "MOVSS [ESP] $src\n\t"
11306 "FLD_S [ESP]\n\t"
11307 "ADD ESP,4\n\t"
11308 "FSTP $dst\t# D-round" %}
11309 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11310 ins_pipe( pipe_slow );
11311 %}
11313 instruct convX2XD_reg(regXD dst, regX src) %{
11314 predicate(UseSSE>=2);
11315 match(Set dst (ConvF2D src));
11316 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11317 opcode(0xF3, 0x0F, 0x5A);
11318 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11319 ins_pipe( pipe_slow );
11320 %}
11322 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11323 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11324 predicate(UseSSE<=1);
11325 match(Set dst (ConvD2I src));
11326 effect( KILL tmp, KILL cr );
11327 format %{ "FLD $src\t# Convert double to int \n\t"
11328 "FLDCW trunc mode\n\t"
11329 "SUB ESP,4\n\t"
11330 "FISTp [ESP + #0]\n\t"
11331 "FLDCW std/24-bit mode\n\t"
11332 "POP EAX\n\t"
11333 "CMP EAX,0x80000000\n\t"
11334 "JNE,s fast\n\t"
11335 "FLD_D $src\n\t"
11336 "CALL d2i_wrapper\n"
11337 "fast:" %}
11338 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11339 ins_pipe( pipe_slow );
11340 %}
11342 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11343 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11344 predicate(UseSSE>=2);
11345 match(Set dst (ConvD2I src));
11346 effect( KILL tmp, KILL cr );
11347 format %{ "CVTTSD2SI $dst, $src\n\t"
11348 "CMP $dst,0x80000000\n\t"
11349 "JNE,s fast\n\t"
11350 "SUB ESP, 8\n\t"
11351 "MOVSD [ESP], $src\n\t"
11352 "FLD_D [ESP]\n\t"
11353 "ADD ESP, 8\n\t"
11354 "CALL d2i_wrapper\n"
11355 "fast:" %}
11356 opcode(0x1); // double-precision conversion
11357 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11358 ins_pipe( pipe_slow );
11359 %}
11361 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11362 predicate(UseSSE<=1);
11363 match(Set dst (ConvD2L src));
11364 effect( KILL cr );
11365 format %{ "FLD $src\t# Convert double to long\n\t"
11366 "FLDCW trunc mode\n\t"
11367 "SUB ESP,8\n\t"
11368 "FISTp [ESP + #0]\n\t"
11369 "FLDCW std/24-bit mode\n\t"
11370 "POP EAX\n\t"
11371 "POP EDX\n\t"
11372 "CMP EDX,0x80000000\n\t"
11373 "JNE,s fast\n\t"
11374 "TEST EAX,EAX\n\t"
11375 "JNE,s fast\n\t"
11376 "FLD $src\n\t"
11377 "CALL d2l_wrapper\n"
11378 "fast:" %}
11379 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11380 ins_pipe( pipe_slow );
11381 %}
11383 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11384 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11385 predicate (UseSSE>=2);
11386 match(Set dst (ConvD2L src));
11387 effect( KILL cr );
11388 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11389 "MOVSD [ESP],$src\n\t"
11390 "FLD_D [ESP]\n\t"
11391 "FLDCW trunc mode\n\t"
11392 "FISTp [ESP + #0]\n\t"
11393 "FLDCW std/24-bit mode\n\t"
11394 "POP EAX\n\t"
11395 "POP EDX\n\t"
11396 "CMP EDX,0x80000000\n\t"
11397 "JNE,s fast\n\t"
11398 "TEST EAX,EAX\n\t"
11399 "JNE,s fast\n\t"
11400 "SUB ESP,8\n\t"
11401 "MOVSD [ESP],$src\n\t"
11402 "FLD_D [ESP]\n\t"
11403 "CALL d2l_wrapper\n"
11404 "fast:" %}
11405 ins_encode( XD2L_encoding(src) );
11406 ins_pipe( pipe_slow );
11407 %}
11409 // Convert a double to an int. Java semantics require we do complex
11410 // manglations in the corner cases. So we set the rounding mode to
11411 // 'zero', store the darned double down as an int, and reset the
11412 // rounding mode to 'nearest'. The hardware stores a flag value down
11413 // if we would overflow or converted a NAN; we check for this and
11414 // and go the slow path if needed.
11415 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11416 predicate(UseSSE==0);
11417 match(Set dst (ConvF2I src));
11418 effect( KILL tmp, KILL cr );
11419 format %{ "FLD $src\t# Convert float to int \n\t"
11420 "FLDCW trunc mode\n\t"
11421 "SUB ESP,4\n\t"
11422 "FISTp [ESP + #0]\n\t"
11423 "FLDCW std/24-bit mode\n\t"
11424 "POP EAX\n\t"
11425 "CMP EAX,0x80000000\n\t"
11426 "JNE,s fast\n\t"
11427 "FLD $src\n\t"
11428 "CALL d2i_wrapper\n"
11429 "fast:" %}
11430 // D2I_encoding works for F2I
11431 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11432 ins_pipe( pipe_slow );
11433 %}
11435 // Convert a float in xmm to an int reg.
11436 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11437 predicate(UseSSE>=1);
11438 match(Set dst (ConvF2I src));
11439 effect( KILL tmp, KILL cr );
11440 format %{ "CVTTSS2SI $dst, $src\n\t"
11441 "CMP $dst,0x80000000\n\t"
11442 "JNE,s fast\n\t"
11443 "SUB ESP, 4\n\t"
11444 "MOVSS [ESP], $src\n\t"
11445 "FLD [ESP]\n\t"
11446 "ADD ESP, 4\n\t"
11447 "CALL d2i_wrapper\n"
11448 "fast:" %}
11449 opcode(0x0); // single-precision conversion
11450 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11451 ins_pipe( pipe_slow );
11452 %}
11454 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11455 predicate(UseSSE==0);
11456 match(Set dst (ConvF2L src));
11457 effect( KILL cr );
11458 format %{ "FLD $src\t# Convert float to long\n\t"
11459 "FLDCW trunc mode\n\t"
11460 "SUB ESP,8\n\t"
11461 "FISTp [ESP + #0]\n\t"
11462 "FLDCW std/24-bit mode\n\t"
11463 "POP EAX\n\t"
11464 "POP EDX\n\t"
11465 "CMP EDX,0x80000000\n\t"
11466 "JNE,s fast\n\t"
11467 "TEST EAX,EAX\n\t"
11468 "JNE,s fast\n\t"
11469 "FLD $src\n\t"
11470 "CALL d2l_wrapper\n"
11471 "fast:" %}
11472 // D2L_encoding works for F2L
11473 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11474 ins_pipe( pipe_slow );
11475 %}
11477 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11478 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11479 predicate (UseSSE>=1);
11480 match(Set dst (ConvF2L src));
11481 effect( KILL cr );
11482 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11483 "MOVSS [ESP],$src\n\t"
11484 "FLD_S [ESP]\n\t"
11485 "FLDCW trunc mode\n\t"
11486 "FISTp [ESP + #0]\n\t"
11487 "FLDCW std/24-bit mode\n\t"
11488 "POP EAX\n\t"
11489 "POP EDX\n\t"
11490 "CMP EDX,0x80000000\n\t"
11491 "JNE,s fast\n\t"
11492 "TEST EAX,EAX\n\t"
11493 "JNE,s fast\n\t"
11494 "SUB ESP,4\t# Convert float to long\n\t"
11495 "MOVSS [ESP],$src\n\t"
11496 "FLD_S [ESP]\n\t"
11497 "ADD ESP,4\n\t"
11498 "CALL d2l_wrapper\n"
11499 "fast:" %}
11500 ins_encode( X2L_encoding(src) );
11501 ins_pipe( pipe_slow );
11502 %}
11504 instruct convI2D_reg(regD dst, stackSlotI src) %{
11505 predicate( UseSSE<=1 );
11506 match(Set dst (ConvI2D src));
11507 format %{ "FILD $src\n\t"
11508 "FSTP $dst" %}
11509 opcode(0xDB, 0x0); /* DB /0 */
11510 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11511 ins_pipe( fpu_reg_mem );
11512 %}
11514 instruct convI2XD_reg(regXD dst, eRegI src) %{
11515 predicate( UseSSE>=2 && !UseXmmI2D );
11516 match(Set dst (ConvI2D src));
11517 format %{ "CVTSI2SD $dst,$src" %}
11518 opcode(0xF2, 0x0F, 0x2A);
11519 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11520 ins_pipe( pipe_slow );
11521 %}
11523 instruct convI2XD_mem(regXD dst, memory mem) %{
11524 predicate( UseSSE>=2 );
11525 match(Set dst (ConvI2D (LoadI mem)));
11526 format %{ "CVTSI2SD $dst,$mem" %}
11527 opcode(0xF2, 0x0F, 0x2A);
11528 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11529 ins_pipe( pipe_slow );
11530 %}
11532 instruct convXI2XD_reg(regXD dst, eRegI src)
11533 %{
11534 predicate( UseSSE>=2 && UseXmmI2D );
11535 match(Set dst (ConvI2D src));
11537 format %{ "MOVD $dst,$src\n\t"
11538 "CVTDQ2PD $dst,$dst\t# i2d" %}
11539 ins_encode %{
11540 __ movdl($dst$$XMMRegister, $src$$Register);
11541 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11542 %}
11543 ins_pipe(pipe_slow); // XXX
11544 %}
11546 instruct convI2D_mem(regD dst, memory mem) %{
11547 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11548 match(Set dst (ConvI2D (LoadI mem)));
11549 format %{ "FILD $mem\n\t"
11550 "FSTP $dst" %}
11551 opcode(0xDB); /* DB /0 */
11552 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11553 Pop_Reg_D(dst));
11554 ins_pipe( fpu_reg_mem );
11555 %}
11557 // Convert a byte to a float; no rounding step needed.
11558 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11559 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11560 match(Set dst (ConvI2F src));
11561 format %{ "FILD $src\n\t"
11562 "FSTP $dst" %}
11564 opcode(0xDB, 0x0); /* DB /0 */
11565 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11566 ins_pipe( fpu_reg_mem );
11567 %}
11569 // In 24-bit mode, force exponent rounding by storing back out
11570 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11571 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11572 match(Set dst (ConvI2F src));
11573 ins_cost(200);
11574 format %{ "FILD $src\n\t"
11575 "FSTP_S $dst" %}
11576 opcode(0xDB, 0x0); /* DB /0 */
11577 ins_encode( Push_Mem_I(src),
11578 Pop_Mem_F(dst));
11579 ins_pipe( fpu_mem_mem );
11580 %}
11582 // In 24-bit mode, force exponent rounding by storing back out
11583 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11584 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11585 match(Set dst (ConvI2F (LoadI mem)));
11586 ins_cost(200);
11587 format %{ "FILD $mem\n\t"
11588 "FSTP_S $dst" %}
11589 opcode(0xDB); /* DB /0 */
11590 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11591 Pop_Mem_F(dst));
11592 ins_pipe( fpu_mem_mem );
11593 %}
11595 // This instruction does not round to 24-bits
11596 instruct convI2F_reg(regF dst, stackSlotI src) %{
11597 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11598 match(Set dst (ConvI2F src));
11599 format %{ "FILD $src\n\t"
11600 "FSTP $dst" %}
11601 opcode(0xDB, 0x0); /* DB /0 */
11602 ins_encode( Push_Mem_I(src),
11603 Pop_Reg_F(dst));
11604 ins_pipe( fpu_reg_mem );
11605 %}
11607 // This instruction does not round to 24-bits
11608 instruct convI2F_mem(regF dst, memory mem) %{
11609 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11610 match(Set dst (ConvI2F (LoadI mem)));
11611 format %{ "FILD $mem\n\t"
11612 "FSTP $dst" %}
11613 opcode(0xDB); /* DB /0 */
11614 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11615 Pop_Reg_F(dst));
11616 ins_pipe( fpu_reg_mem );
11617 %}
11619 // Convert an int to a float in xmm; no rounding step needed.
11620 instruct convI2X_reg(regX dst, eRegI src) %{
11621 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11622 match(Set dst (ConvI2F src));
11623 format %{ "CVTSI2SS $dst, $src" %}
11625 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11626 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11627 ins_pipe( pipe_slow );
11628 %}
11630 instruct convXI2X_reg(regX dst, eRegI src)
11631 %{
11632 predicate( UseSSE>=2 && UseXmmI2F );
11633 match(Set dst (ConvI2F src));
11635 format %{ "MOVD $dst,$src\n\t"
11636 "CVTDQ2PS $dst,$dst\t# i2f" %}
11637 ins_encode %{
11638 __ movdl($dst$$XMMRegister, $src$$Register);
11639 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11640 %}
11641 ins_pipe(pipe_slow); // XXX
11642 %}
11644 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11645 match(Set dst (ConvI2L src));
11646 effect(KILL cr);
11647 ins_cost(375);
11648 format %{ "MOV $dst.lo,$src\n\t"
11649 "MOV $dst.hi,$src\n\t"
11650 "SAR $dst.hi,31" %}
11651 ins_encode(convert_int_long(dst,src));
11652 ins_pipe( ialu_reg_reg_long );
11653 %}
11655 // Zero-extend convert int to long
11656 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11657 match(Set dst (AndL (ConvI2L src) mask) );
11658 effect( KILL flags );
11659 ins_cost(250);
11660 format %{ "MOV $dst.lo,$src\n\t"
11661 "XOR $dst.hi,$dst.hi" %}
11662 opcode(0x33); // XOR
11663 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11664 ins_pipe( ialu_reg_reg_long );
11665 %}
11667 // Zero-extend long
11668 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11669 match(Set dst (AndL src mask) );
11670 effect( KILL flags );
11671 ins_cost(250);
11672 format %{ "MOV $dst.lo,$src.lo\n\t"
11673 "XOR $dst.hi,$dst.hi\n\t" %}
11674 opcode(0x33); // XOR
11675 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11676 ins_pipe( ialu_reg_reg_long );
11677 %}
11679 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11680 predicate (UseSSE<=1);
11681 match(Set dst (ConvL2D src));
11682 effect( KILL cr );
11683 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11684 "PUSH $src.lo\n\t"
11685 "FILD ST,[ESP + #0]\n\t"
11686 "ADD ESP,8\n\t"
11687 "FSTP_D $dst\t# D-round" %}
11688 opcode(0xDF, 0x5); /* DF /5 */
11689 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11690 ins_pipe( pipe_slow );
11691 %}
11693 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11694 predicate (UseSSE>=2);
11695 match(Set dst (ConvL2D src));
11696 effect( KILL cr );
11697 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11698 "PUSH $src.lo\n\t"
11699 "FILD_D [ESP]\n\t"
11700 "FSTP_D [ESP]\n\t"
11701 "MOVSD $dst,[ESP]\n\t"
11702 "ADD ESP,8" %}
11703 opcode(0xDF, 0x5); /* DF /5 */
11704 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11705 ins_pipe( pipe_slow );
11706 %}
11708 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11709 predicate (UseSSE>=1);
11710 match(Set dst (ConvL2F src));
11711 effect( KILL cr );
11712 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11713 "PUSH $src.lo\n\t"
11714 "FILD_D [ESP]\n\t"
11715 "FSTP_S [ESP]\n\t"
11716 "MOVSS $dst,[ESP]\n\t"
11717 "ADD ESP,8" %}
11718 opcode(0xDF, 0x5); /* DF /5 */
11719 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11720 ins_pipe( pipe_slow );
11721 %}
11723 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11724 match(Set dst (ConvL2F src));
11725 effect( KILL cr );
11726 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11727 "PUSH $src.lo\n\t"
11728 "FILD ST,[ESP + #0]\n\t"
11729 "ADD ESP,8\n\t"
11730 "FSTP_S $dst\t# F-round" %}
11731 opcode(0xDF, 0x5); /* DF /5 */
11732 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11733 ins_pipe( pipe_slow );
11734 %}
11736 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11737 match(Set dst (ConvL2I src));
11738 effect( DEF dst, USE src );
11739 format %{ "MOV $dst,$src.lo" %}
11740 ins_encode(enc_CopyL_Lo(dst,src));
11741 ins_pipe( ialu_reg_reg );
11742 %}
11745 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11746 match(Set dst (MoveF2I src));
11747 effect( DEF dst, USE src );
11748 ins_cost(100);
11749 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11750 opcode(0x8B);
11751 ins_encode( OpcP, RegMem(dst,src));
11752 ins_pipe( ialu_reg_mem );
11753 %}
11755 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11756 predicate(UseSSE==0);
11757 match(Set dst (MoveF2I src));
11758 effect( DEF dst, USE src );
11760 ins_cost(125);
11761 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11762 ins_encode( Pop_Mem_Reg_F(dst, src) );
11763 ins_pipe( fpu_mem_reg );
11764 %}
11766 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11767 predicate(UseSSE>=1);
11768 match(Set dst (MoveF2I src));
11769 effect( DEF dst, USE src );
11771 ins_cost(95);
11772 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11773 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11774 ins_pipe( pipe_slow );
11775 %}
11777 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11778 predicate(UseSSE>=2);
11779 match(Set dst (MoveF2I src));
11780 effect( DEF dst, USE src );
11781 ins_cost(85);
11782 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11783 ins_encode( MovX2I_reg(dst, src));
11784 ins_pipe( pipe_slow );
11785 %}
11787 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11788 match(Set dst (MoveI2F src));
11789 effect( DEF dst, USE src );
11791 ins_cost(100);
11792 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11793 opcode(0x89);
11794 ins_encode( OpcPRegSS( dst, src ) );
11795 ins_pipe( ialu_mem_reg );
11796 %}
11799 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11800 predicate(UseSSE==0);
11801 match(Set dst (MoveI2F src));
11802 effect(DEF dst, USE src);
11804 ins_cost(125);
11805 format %{ "FLD_S $src\n\t"
11806 "FSTP $dst\t# MoveI2F_stack_reg" %}
11807 opcode(0xD9); /* D9 /0, FLD m32real */
11808 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11809 Pop_Reg_F(dst) );
11810 ins_pipe( fpu_reg_mem );
11811 %}
11813 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
11814 predicate(UseSSE>=1);
11815 match(Set dst (MoveI2F src));
11816 effect( DEF dst, USE src );
11818 ins_cost(95);
11819 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11820 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11821 ins_pipe( pipe_slow );
11822 %}
11824 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
11825 predicate(UseSSE>=2);
11826 match(Set dst (MoveI2F src));
11827 effect( DEF dst, USE src );
11829 ins_cost(85);
11830 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11831 ins_encode( MovI2X_reg(dst, src) );
11832 ins_pipe( pipe_slow );
11833 %}
11835 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11836 match(Set dst (MoveD2L src));
11837 effect(DEF dst, USE src);
11839 ins_cost(250);
11840 format %{ "MOV $dst.lo,$src\n\t"
11841 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11842 opcode(0x8B, 0x8B);
11843 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11844 ins_pipe( ialu_mem_long_reg );
11845 %}
11847 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11848 predicate(UseSSE<=1);
11849 match(Set dst (MoveD2L src));
11850 effect(DEF dst, USE src);
11852 ins_cost(125);
11853 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11854 ins_encode( Pop_Mem_Reg_D(dst, src) );
11855 ins_pipe( fpu_mem_reg );
11856 %}
11858 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
11859 predicate(UseSSE>=2);
11860 match(Set dst (MoveD2L src));
11861 effect(DEF dst, USE src);
11862 ins_cost(95);
11864 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11865 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
11866 ins_pipe( pipe_slow );
11867 %}
11869 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
11870 predicate(UseSSE>=2);
11871 match(Set dst (MoveD2L src));
11872 effect(DEF dst, USE src, TEMP tmp);
11873 ins_cost(85);
11874 format %{ "MOVD $dst.lo,$src\n\t"
11875 "PSHUFLW $tmp,$src,0x4E\n\t"
11876 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11877 ins_encode( MovXD2L_reg(dst, src, tmp) );
11878 ins_pipe( pipe_slow );
11879 %}
11881 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11882 match(Set dst (MoveL2D src));
11883 effect(DEF dst, USE src);
11885 ins_cost(200);
11886 format %{ "MOV $dst,$src.lo\n\t"
11887 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11888 opcode(0x89, 0x89);
11889 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11890 ins_pipe( ialu_mem_long_reg );
11891 %}
11894 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11895 predicate(UseSSE<=1);
11896 match(Set dst (MoveL2D src));
11897 effect(DEF dst, USE src);
11898 ins_cost(125);
11900 format %{ "FLD_D $src\n\t"
11901 "FSTP $dst\t# MoveL2D_stack_reg" %}
11902 opcode(0xDD); /* DD /0, FLD m64real */
11903 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11904 Pop_Reg_D(dst) );
11905 ins_pipe( fpu_reg_mem );
11906 %}
11909 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
11910 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11911 match(Set dst (MoveL2D src));
11912 effect(DEF dst, USE src);
11914 ins_cost(95);
11915 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11916 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11917 ins_pipe( pipe_slow );
11918 %}
11920 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
11921 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11922 match(Set dst (MoveL2D src));
11923 effect(DEF dst, USE src);
11925 ins_cost(95);
11926 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11927 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
11928 ins_pipe( pipe_slow );
11929 %}
11931 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
11932 predicate(UseSSE>=2);
11933 match(Set dst (MoveL2D src));
11934 effect(TEMP dst, USE src, TEMP tmp);
11935 ins_cost(85);
11936 format %{ "MOVD $dst,$src.lo\n\t"
11937 "MOVD $tmp,$src.hi\n\t"
11938 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11939 ins_encode( MovL2XD_reg(dst, src, tmp) );
11940 ins_pipe( pipe_slow );
11941 %}
11943 // Replicate scalar to packed byte (1 byte) values in xmm
11944 instruct Repl8B_reg(regXD dst, regXD src) %{
11945 predicate(UseSSE>=2);
11946 match(Set dst (Replicate8B src));
11947 format %{ "MOVDQA $dst,$src\n\t"
11948 "PUNPCKLBW $dst,$dst\n\t"
11949 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11950 ins_encode( pshufd_8x8(dst, src));
11951 ins_pipe( pipe_slow );
11952 %}
11954 // Replicate scalar to packed byte (1 byte) values in xmm
11955 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
11956 predicate(UseSSE>=2);
11957 match(Set dst (Replicate8B src));
11958 format %{ "MOVD $dst,$src\n\t"
11959 "PUNPCKLBW $dst,$dst\n\t"
11960 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11961 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11962 ins_pipe( pipe_slow );
11963 %}
11965 // Replicate scalar zero to packed byte (1 byte) values in xmm
11966 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
11967 predicate(UseSSE>=2);
11968 match(Set dst (Replicate8B zero));
11969 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11970 ins_encode( pxor(dst, dst));
11971 ins_pipe( fpu_reg_reg );
11972 %}
11974 // Replicate scalar to packed shore (2 byte) values in xmm
11975 instruct Repl4S_reg(regXD dst, regXD src) %{
11976 predicate(UseSSE>=2);
11977 match(Set dst (Replicate4S src));
11978 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11979 ins_encode( pshufd_4x16(dst, src));
11980 ins_pipe( fpu_reg_reg );
11981 %}
11983 // Replicate scalar to packed shore (2 byte) values in xmm
11984 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
11985 predicate(UseSSE>=2);
11986 match(Set dst (Replicate4S src));
11987 format %{ "MOVD $dst,$src\n\t"
11988 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11989 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11990 ins_pipe( fpu_reg_reg );
11991 %}
11993 // Replicate scalar zero to packed short (2 byte) values in xmm
11994 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
11995 predicate(UseSSE>=2);
11996 match(Set dst (Replicate4S zero));
11997 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11998 ins_encode( pxor(dst, dst));
11999 ins_pipe( fpu_reg_reg );
12000 %}
12002 // Replicate scalar to packed char (2 byte) values in xmm
12003 instruct Repl4C_reg(regXD dst, regXD src) %{
12004 predicate(UseSSE>=2);
12005 match(Set dst (Replicate4C src));
12006 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12007 ins_encode( pshufd_4x16(dst, src));
12008 ins_pipe( fpu_reg_reg );
12009 %}
12011 // Replicate scalar to packed char (2 byte) values in xmm
12012 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12013 predicate(UseSSE>=2);
12014 match(Set dst (Replicate4C src));
12015 format %{ "MOVD $dst,$src\n\t"
12016 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12017 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12018 ins_pipe( fpu_reg_reg );
12019 %}
12021 // Replicate scalar zero to packed char (2 byte) values in xmm
12022 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12023 predicate(UseSSE>=2);
12024 match(Set dst (Replicate4C zero));
12025 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12026 ins_encode( pxor(dst, dst));
12027 ins_pipe( fpu_reg_reg );
12028 %}
12030 // Replicate scalar to packed integer (4 byte) values in xmm
12031 instruct Repl2I_reg(regXD dst, regXD src) %{
12032 predicate(UseSSE>=2);
12033 match(Set dst (Replicate2I src));
12034 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12035 ins_encode( pshufd(dst, src, 0x00));
12036 ins_pipe( fpu_reg_reg );
12037 %}
12039 // Replicate scalar to packed integer (4 byte) values in xmm
12040 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12041 predicate(UseSSE>=2);
12042 match(Set dst (Replicate2I src));
12043 format %{ "MOVD $dst,$src\n\t"
12044 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12045 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12046 ins_pipe( fpu_reg_reg );
12047 %}
12049 // Replicate scalar zero to packed integer (2 byte) values in xmm
12050 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12051 predicate(UseSSE>=2);
12052 match(Set dst (Replicate2I zero));
12053 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12054 ins_encode( pxor(dst, dst));
12055 ins_pipe( fpu_reg_reg );
12056 %}
12058 // Replicate scalar to packed single precision floating point values in xmm
12059 instruct Repl2F_reg(regXD dst, regXD src) %{
12060 predicate(UseSSE>=2);
12061 match(Set dst (Replicate2F src));
12062 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12063 ins_encode( pshufd(dst, src, 0xe0));
12064 ins_pipe( fpu_reg_reg );
12065 %}
12067 // Replicate scalar to packed single precision floating point values in xmm
12068 instruct Repl2F_regX(regXD dst, regX src) %{
12069 predicate(UseSSE>=2);
12070 match(Set dst (Replicate2F src));
12071 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12072 ins_encode( pshufd(dst, src, 0xe0));
12073 ins_pipe( fpu_reg_reg );
12074 %}
12076 // Replicate scalar to packed single precision floating point values in xmm
12077 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12078 predicate(UseSSE>=2);
12079 match(Set dst (Replicate2F zero));
12080 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12081 ins_encode( pxor(dst, dst));
12082 ins_pipe( fpu_reg_reg );
12083 %}
12087 // =======================================================================
12088 // fast clearing of an array
12090 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12091 match(Set dummy (ClearArray cnt base));
12092 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12093 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12094 "XOR EAX,EAX\n\t"
12095 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12096 opcode(0,0x4);
12097 ins_encode( Opcode(0xD1), RegOpc(ECX),
12098 OpcRegReg(0x33,EAX,EAX),
12099 Opcode(0xF3), Opcode(0xAB) );
12100 ins_pipe( pipe_slow );
12101 %}
12103 instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
12104 match(Set result (StrComp str1 str2));
12105 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
12106 //ins_cost(300);
12108 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
12109 ins_encode( enc_String_Compare() );
12110 ins_pipe( pipe_slow );
12111 %}
12113 // fast array equals
12114 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
12115 match(Set result (AryEq ary1 ary2));
12116 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr);
12117 //ins_cost(300);
12119 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EAX, EBX" %}
12120 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) );
12121 ins_pipe( pipe_slow );
12122 %}
12124 //----------Control Flow Instructions------------------------------------------
12125 // Signed compare Instructions
12126 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12127 match(Set cr (CmpI op1 op2));
12128 effect( DEF cr, USE op1, USE op2 );
12129 format %{ "CMP $op1,$op2" %}
12130 opcode(0x3B); /* Opcode 3B /r */
12131 ins_encode( OpcP, RegReg( op1, op2) );
12132 ins_pipe( ialu_cr_reg_reg );
12133 %}
12135 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12136 match(Set cr (CmpI op1 op2));
12137 effect( DEF cr, USE op1 );
12138 format %{ "CMP $op1,$op2" %}
12139 opcode(0x81,0x07); /* Opcode 81 /7 */
12140 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12141 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12142 ins_pipe( ialu_cr_reg_imm );
12143 %}
12145 // Cisc-spilled version of cmpI_eReg
12146 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12147 match(Set cr (CmpI op1 (LoadI op2)));
12149 format %{ "CMP $op1,$op2" %}
12150 ins_cost(500);
12151 opcode(0x3B); /* Opcode 3B /r */
12152 ins_encode( OpcP, RegMem( op1, op2) );
12153 ins_pipe( ialu_cr_reg_mem );
12154 %}
12156 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12157 match(Set cr (CmpI src zero));
12158 effect( DEF cr, USE src );
12160 format %{ "TEST $src,$src" %}
12161 opcode(0x85);
12162 ins_encode( OpcP, RegReg( src, src ) );
12163 ins_pipe( ialu_cr_reg_imm );
12164 %}
12166 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12167 match(Set cr (CmpI (AndI src con) zero));
12169 format %{ "TEST $src,$con" %}
12170 opcode(0xF7,0x00);
12171 ins_encode( OpcP, RegOpc(src), Con32(con) );
12172 ins_pipe( ialu_cr_reg_imm );
12173 %}
12175 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12176 match(Set cr (CmpI (AndI src mem) zero));
12178 format %{ "TEST $src,$mem" %}
12179 opcode(0x85);
12180 ins_encode( OpcP, RegMem( src, mem ) );
12181 ins_pipe( ialu_cr_reg_mem );
12182 %}
12184 // Unsigned compare Instructions; really, same as signed except they
12185 // produce an eFlagsRegU instead of eFlagsReg.
12186 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12187 match(Set cr (CmpU op1 op2));
12189 format %{ "CMPu $op1,$op2" %}
12190 opcode(0x3B); /* Opcode 3B /r */
12191 ins_encode( OpcP, RegReg( op1, op2) );
12192 ins_pipe( ialu_cr_reg_reg );
12193 %}
12195 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12196 match(Set cr (CmpU op1 op2));
12198 format %{ "CMPu $op1,$op2" %}
12199 opcode(0x81,0x07); /* Opcode 81 /7 */
12200 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12201 ins_pipe( ialu_cr_reg_imm );
12202 %}
12204 // // Cisc-spilled version of cmpU_eReg
12205 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12206 match(Set cr (CmpU op1 (LoadI op2)));
12208 format %{ "CMPu $op1,$op2" %}
12209 ins_cost(500);
12210 opcode(0x3B); /* Opcode 3B /r */
12211 ins_encode( OpcP, RegMem( op1, op2) );
12212 ins_pipe( ialu_cr_reg_mem );
12213 %}
12215 // // Cisc-spilled version of cmpU_eReg
12216 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12217 // match(Set cr (CmpU (LoadI op1) op2));
12218 //
12219 // format %{ "CMPu $op1,$op2" %}
12220 // ins_cost(500);
12221 // opcode(0x39); /* Opcode 39 /r */
12222 // ins_encode( OpcP, RegMem( op1, op2) );
12223 //%}
12225 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12226 match(Set cr (CmpU src zero));
12228 format %{ "TESTu $src,$src" %}
12229 opcode(0x85);
12230 ins_encode( OpcP, RegReg( src, src ) );
12231 ins_pipe( ialu_cr_reg_imm );
12232 %}
12234 // Unsigned pointer compare Instructions
12235 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12236 match(Set cr (CmpP op1 op2));
12238 format %{ "CMPu $op1,$op2" %}
12239 opcode(0x3B); /* Opcode 3B /r */
12240 ins_encode( OpcP, RegReg( op1, op2) );
12241 ins_pipe( ialu_cr_reg_reg );
12242 %}
12244 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12245 match(Set cr (CmpP op1 op2));
12247 format %{ "CMPu $op1,$op2" %}
12248 opcode(0x81,0x07); /* Opcode 81 /7 */
12249 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12250 ins_pipe( ialu_cr_reg_imm );
12251 %}
12253 // // Cisc-spilled version of cmpP_eReg
12254 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12255 match(Set cr (CmpP op1 (LoadP op2)));
12257 format %{ "CMPu $op1,$op2" %}
12258 ins_cost(500);
12259 opcode(0x3B); /* Opcode 3B /r */
12260 ins_encode( OpcP, RegMem( op1, op2) );
12261 ins_pipe( ialu_cr_reg_mem );
12262 %}
12264 // // Cisc-spilled version of cmpP_eReg
12265 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12266 // match(Set cr (CmpP (LoadP op1) op2));
12267 //
12268 // format %{ "CMPu $op1,$op2" %}
12269 // ins_cost(500);
12270 // opcode(0x39); /* Opcode 39 /r */
12271 // ins_encode( OpcP, RegMem( op1, op2) );
12272 //%}
12274 // Compare raw pointer (used in out-of-heap check).
12275 // Only works because non-oop pointers must be raw pointers
12276 // and raw pointers have no anti-dependencies.
12277 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12278 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12279 match(Set cr (CmpP op1 (LoadP op2)));
12281 format %{ "CMPu $op1,$op2" %}
12282 opcode(0x3B); /* Opcode 3B /r */
12283 ins_encode( OpcP, RegMem( op1, op2) );
12284 ins_pipe( ialu_cr_reg_mem );
12285 %}
12287 //
12288 // This will generate a signed flags result. This should be ok
12289 // since any compare to a zero should be eq/neq.
12290 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12291 match(Set cr (CmpP src zero));
12293 format %{ "TEST $src,$src" %}
12294 opcode(0x85);
12295 ins_encode( OpcP, RegReg( src, src ) );
12296 ins_pipe( ialu_cr_reg_imm );
12297 %}
12299 // Cisc-spilled version of testP_reg
12300 // This will generate a signed flags result. This should be ok
12301 // since any compare to a zero should be eq/neq.
12302 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12303 match(Set cr (CmpP (LoadP op) zero));
12305 format %{ "TEST $op,0xFFFFFFFF" %}
12306 ins_cost(500);
12307 opcode(0xF7); /* Opcode F7 /0 */
12308 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12309 ins_pipe( ialu_cr_reg_imm );
12310 %}
12312 // Yanked all unsigned pointer compare operations.
12313 // Pointer compares are done with CmpP which is already unsigned.
12315 //----------Max and Min--------------------------------------------------------
12316 // Min Instructions
12317 ////
12318 // *** Min and Max using the conditional move are slower than the
12319 // *** branch version on a Pentium III.
12320 // // Conditional move for min
12321 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12322 // effect( USE_DEF op2, USE op1, USE cr );
12323 // format %{ "CMOVlt $op2,$op1\t! min" %}
12324 // opcode(0x4C,0x0F);
12325 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12326 // ins_pipe( pipe_cmov_reg );
12327 //%}
12328 //
12329 //// Min Register with Register (P6 version)
12330 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12331 // predicate(VM_Version::supports_cmov() );
12332 // match(Set op2 (MinI op1 op2));
12333 // ins_cost(200);
12334 // expand %{
12335 // eFlagsReg cr;
12336 // compI_eReg(cr,op1,op2);
12337 // cmovI_reg_lt(op2,op1,cr);
12338 // %}
12339 //%}
12341 // Min Register with Register (generic version)
12342 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12343 match(Set dst (MinI dst src));
12344 effect(KILL flags);
12345 ins_cost(300);
12347 format %{ "MIN $dst,$src" %}
12348 opcode(0xCC);
12349 ins_encode( min_enc(dst,src) );
12350 ins_pipe( pipe_slow );
12351 %}
12353 // Max Register with Register
12354 // *** Min and Max using the conditional move are slower than the
12355 // *** branch version on a Pentium III.
12356 // // Conditional move for max
12357 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12358 // effect( USE_DEF op2, USE op1, USE cr );
12359 // format %{ "CMOVgt $op2,$op1\t! max" %}
12360 // opcode(0x4F,0x0F);
12361 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12362 // ins_pipe( pipe_cmov_reg );
12363 //%}
12364 //
12365 // // Max Register with Register (P6 version)
12366 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12367 // predicate(VM_Version::supports_cmov() );
12368 // match(Set op2 (MaxI op1 op2));
12369 // ins_cost(200);
12370 // expand %{
12371 // eFlagsReg cr;
12372 // compI_eReg(cr,op1,op2);
12373 // cmovI_reg_gt(op2,op1,cr);
12374 // %}
12375 //%}
12377 // Max Register with Register (generic version)
12378 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12379 match(Set dst (MaxI dst src));
12380 effect(KILL flags);
12381 ins_cost(300);
12383 format %{ "MAX $dst,$src" %}
12384 opcode(0xCC);
12385 ins_encode( max_enc(dst,src) );
12386 ins_pipe( pipe_slow );
12387 %}
12389 // ============================================================================
12390 // Branch Instructions
12391 // Jump Table
12392 instruct jumpXtnd(eRegI switch_val) %{
12393 match(Jump switch_val);
12394 ins_cost(350);
12396 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12398 ins_encode %{
12399 address table_base = __ address_table_constant(_index2label);
12401 // Jump to Address(table_base + switch_reg)
12402 InternalAddress table(table_base);
12403 Address index(noreg, $switch_val$$Register, Address::times_1);
12404 __ jump(ArrayAddress(table, index));
12405 %}
12406 ins_pc_relative(1);
12407 ins_pipe(pipe_jmp);
12408 %}
12410 // Jump Direct - Label defines a relative address from JMP+1
12411 instruct jmpDir(label labl) %{
12412 match(Goto);
12413 effect(USE labl);
12415 ins_cost(300);
12416 format %{ "JMP $labl" %}
12417 size(5);
12418 opcode(0xE9);
12419 ins_encode( OpcP, Lbl( labl ) );
12420 ins_pipe( pipe_jmp );
12421 ins_pc_relative(1);
12422 %}
12424 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12425 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12426 match(If cop cr);
12427 effect(USE labl);
12429 ins_cost(300);
12430 format %{ "J$cop $labl" %}
12431 size(6);
12432 opcode(0x0F, 0x80);
12433 ins_encode( Jcc( cop, labl) );
12434 ins_pipe( pipe_jcc );
12435 ins_pc_relative(1);
12436 %}
12438 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12439 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12440 match(CountedLoopEnd cop cr);
12441 effect(USE labl);
12443 ins_cost(300);
12444 format %{ "J$cop $labl\t# Loop end" %}
12445 size(6);
12446 opcode(0x0F, 0x80);
12447 ins_encode( Jcc( cop, labl) );
12448 ins_pipe( pipe_jcc );
12449 ins_pc_relative(1);
12450 %}
12452 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12453 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12454 match(CountedLoopEnd cop cmp);
12455 effect(USE labl);
12457 ins_cost(300);
12458 format %{ "J$cop,u $labl\t# Loop end" %}
12459 size(6);
12460 opcode(0x0F, 0x80);
12461 ins_encode( Jcc( cop, labl) );
12462 ins_pipe( pipe_jcc );
12463 ins_pc_relative(1);
12464 %}
12466 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12467 match(CountedLoopEnd cop cmp);
12468 effect(USE labl);
12470 ins_cost(200);
12471 format %{ "J$cop,u $labl\t# Loop end" %}
12472 size(6);
12473 opcode(0x0F, 0x80);
12474 ins_encode( Jcc( cop, labl) );
12475 ins_pipe( pipe_jcc );
12476 ins_pc_relative(1);
12477 %}
12479 // Jump Direct Conditional - using unsigned comparison
12480 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12481 match(If cop cmp);
12482 effect(USE labl);
12484 ins_cost(300);
12485 format %{ "J$cop,u $labl" %}
12486 size(6);
12487 opcode(0x0F, 0x80);
12488 ins_encode(Jcc(cop, labl));
12489 ins_pipe(pipe_jcc);
12490 ins_pc_relative(1);
12491 %}
12493 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12494 match(If cop cmp);
12495 effect(USE labl);
12497 ins_cost(200);
12498 format %{ "J$cop,u $labl" %}
12499 size(6);
12500 opcode(0x0F, 0x80);
12501 ins_encode(Jcc(cop, labl));
12502 ins_pipe(pipe_jcc);
12503 ins_pc_relative(1);
12504 %}
12506 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12507 match(If cop cmp);
12508 effect(USE labl);
12510 ins_cost(200);
12511 format %{ $$template
12512 if ($cop$$cmpcode == Assembler::notEqual) {
12513 $$emit$$"JP,u $labl\n\t"
12514 $$emit$$"J$cop,u $labl"
12515 } else {
12516 $$emit$$"JP,u done\n\t"
12517 $$emit$$"J$cop,u $labl\n\t"
12518 $$emit$$"done:"
12519 }
12520 %}
12521 size(12);
12522 opcode(0x0F, 0x80);
12523 ins_encode %{
12524 Label* l = $labl$$label;
12525 $$$emit8$primary;
12526 emit_cc(cbuf, $secondary, Assembler::parity);
12527 int parity_disp = -1;
12528 bool ok = false;
12529 if ($cop$$cmpcode == Assembler::notEqual) {
12530 // the two jumps 6 bytes apart so the jump distances are too
12531 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12532 } else if ($cop$$cmpcode == Assembler::equal) {
12533 parity_disp = 6;
12534 ok = true;
12535 } else {
12536 ShouldNotReachHere();
12537 }
12538 emit_d32(cbuf, parity_disp);
12539 $$$emit8$primary;
12540 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12541 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12542 emit_d32(cbuf, disp);
12543 %}
12544 ins_pipe(pipe_jcc);
12545 ins_pc_relative(1);
12546 %}
12548 // ============================================================================
12549 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12550 // array for an instance of the superklass. Set a hidden internal cache on a
12551 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12552 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12553 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12554 match(Set result (PartialSubtypeCheck sub super));
12555 effect( KILL rcx, KILL cr );
12557 ins_cost(1100); // slightly larger than the next version
12558 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12559 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12560 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12561 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12562 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12563 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12564 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12565 "miss:\t" %}
12567 opcode(0x1); // Force a XOR of EDI
12568 ins_encode( enc_PartialSubtypeCheck() );
12569 ins_pipe( pipe_slow );
12570 %}
12572 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12573 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12574 effect( KILL rcx, KILL result );
12576 ins_cost(1000);
12577 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12578 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12579 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12580 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12581 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12582 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12583 "miss:\t" %}
12585 opcode(0x0); // No need to XOR EDI
12586 ins_encode( enc_PartialSubtypeCheck() );
12587 ins_pipe( pipe_slow );
12588 %}
12590 // ============================================================================
12591 // Branch Instructions -- short offset versions
12592 //
12593 // These instructions are used to replace jumps of a long offset (the default
12594 // match) with jumps of a shorter offset. These instructions are all tagged
12595 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12596 // match rules in general matching. Instead, the ADLC generates a conversion
12597 // method in the MachNode which can be used to do in-place replacement of the
12598 // long variant with the shorter variant. The compiler will determine if a
12599 // branch can be taken by the is_short_branch_offset() predicate in the machine
12600 // specific code section of the file.
12602 // Jump Direct - Label defines a relative address from JMP+1
12603 instruct jmpDir_short(label labl) %{
12604 match(Goto);
12605 effect(USE labl);
12607 ins_cost(300);
12608 format %{ "JMP,s $labl" %}
12609 size(2);
12610 opcode(0xEB);
12611 ins_encode( OpcP, LblShort( labl ) );
12612 ins_pipe( pipe_jmp );
12613 ins_pc_relative(1);
12614 ins_short_branch(1);
12615 %}
12617 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12618 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12619 match(If cop cr);
12620 effect(USE labl);
12622 ins_cost(300);
12623 format %{ "J$cop,s $labl" %}
12624 size(2);
12625 opcode(0x70);
12626 ins_encode( JccShort( cop, labl) );
12627 ins_pipe( pipe_jcc );
12628 ins_pc_relative(1);
12629 ins_short_branch(1);
12630 %}
12632 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12633 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12634 match(CountedLoopEnd cop cr);
12635 effect(USE labl);
12637 ins_cost(300);
12638 format %{ "J$cop,s $labl\t# Loop end" %}
12639 size(2);
12640 opcode(0x70);
12641 ins_encode( JccShort( cop, labl) );
12642 ins_pipe( pipe_jcc );
12643 ins_pc_relative(1);
12644 ins_short_branch(1);
12645 %}
12647 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12648 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12649 match(CountedLoopEnd cop cmp);
12650 effect(USE labl);
12652 ins_cost(300);
12653 format %{ "J$cop,us $labl\t# Loop end" %}
12654 size(2);
12655 opcode(0x70);
12656 ins_encode( JccShort( cop, labl) );
12657 ins_pipe( pipe_jcc );
12658 ins_pc_relative(1);
12659 ins_short_branch(1);
12660 %}
12662 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12663 match(CountedLoopEnd cop cmp);
12664 effect(USE labl);
12666 ins_cost(300);
12667 format %{ "J$cop,us $labl\t# Loop end" %}
12668 size(2);
12669 opcode(0x70);
12670 ins_encode( JccShort( cop, labl) );
12671 ins_pipe( pipe_jcc );
12672 ins_pc_relative(1);
12673 ins_short_branch(1);
12674 %}
12676 // Jump Direct Conditional - using unsigned comparison
12677 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12678 match(If cop cmp);
12679 effect(USE labl);
12681 ins_cost(300);
12682 format %{ "J$cop,us $labl" %}
12683 size(2);
12684 opcode(0x70);
12685 ins_encode( JccShort( cop, labl) );
12686 ins_pipe( pipe_jcc );
12687 ins_pc_relative(1);
12688 ins_short_branch(1);
12689 %}
12691 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12692 match(If cop cmp);
12693 effect(USE labl);
12695 ins_cost(300);
12696 format %{ "J$cop,us $labl" %}
12697 size(2);
12698 opcode(0x70);
12699 ins_encode( JccShort( cop, labl) );
12700 ins_pipe( pipe_jcc );
12701 ins_pc_relative(1);
12702 ins_short_branch(1);
12703 %}
12705 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12706 match(If cop cmp);
12707 effect(USE labl);
12709 ins_cost(300);
12710 format %{ $$template
12711 if ($cop$$cmpcode == Assembler::notEqual) {
12712 $$emit$$"JP,u,s $labl\n\t"
12713 $$emit$$"J$cop,u,s $labl"
12714 } else {
12715 $$emit$$"JP,u,s done\n\t"
12716 $$emit$$"J$cop,u,s $labl\n\t"
12717 $$emit$$"done:"
12718 }
12719 %}
12720 size(4);
12721 opcode(0x70);
12722 ins_encode %{
12723 Label* l = $labl$$label;
12724 emit_cc(cbuf, $primary, Assembler::parity);
12725 int parity_disp = -1;
12726 if ($cop$$cmpcode == Assembler::notEqual) {
12727 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12728 } else if ($cop$$cmpcode == Assembler::equal) {
12729 parity_disp = 2;
12730 } else {
12731 ShouldNotReachHere();
12732 }
12733 emit_d8(cbuf, parity_disp);
12734 emit_cc(cbuf, $primary, $cop$$cmpcode);
12735 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12736 emit_d8(cbuf, disp);
12737 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12738 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12739 %}
12740 ins_pipe(pipe_jcc);
12741 ins_pc_relative(1);
12742 ins_short_branch(1);
12743 %}
12745 // ============================================================================
12746 // Long Compare
12747 //
12748 // Currently we hold longs in 2 registers. Comparing such values efficiently
12749 // is tricky. The flavor of compare used depends on whether we are testing
12750 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12751 // The GE test is the negated LT test. The LE test can be had by commuting
12752 // the operands (yielding a GE test) and then negating; negate again for the
12753 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12754 // NE test is negated from that.
12756 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12757 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12758 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12759 // are collapsed internally in the ADLC's dfa-gen code. The match for
12760 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12761 // foo match ends up with the wrong leaf. One fix is to not match both
12762 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12763 // both forms beat the trinary form of long-compare and both are very useful
12764 // on Intel which has so few registers.
12766 // Manifest a CmpL result in an integer register. Very painful.
12767 // This is the test to avoid.
12768 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12769 match(Set dst (CmpL3 src1 src2));
12770 effect( KILL flags );
12771 ins_cost(1000);
12772 format %{ "XOR $dst,$dst\n\t"
12773 "CMP $src1.hi,$src2.hi\n\t"
12774 "JLT,s m_one\n\t"
12775 "JGT,s p_one\n\t"
12776 "CMP $src1.lo,$src2.lo\n\t"
12777 "JB,s m_one\n\t"
12778 "JEQ,s done\n"
12779 "p_one:\tINC $dst\n\t"
12780 "JMP,s done\n"
12781 "m_one:\tDEC $dst\n"
12782 "done:" %}
12783 ins_encode %{
12784 Label p_one, m_one, done;
12785 __ xorptr($dst$$Register, $dst$$Register);
12786 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12787 __ jccb(Assembler::less, m_one);
12788 __ jccb(Assembler::greater, p_one);
12789 __ cmpl($src1$$Register, $src2$$Register);
12790 __ jccb(Assembler::below, m_one);
12791 __ jccb(Assembler::equal, done);
12792 __ bind(p_one);
12793 __ incrementl($dst$$Register);
12794 __ jmpb(done);
12795 __ bind(m_one);
12796 __ decrementl($dst$$Register);
12797 __ bind(done);
12798 %}
12799 ins_pipe( pipe_slow );
12800 %}
12802 //======
12803 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12804 // compares. Can be used for LE or GT compares by reversing arguments.
12805 // NOT GOOD FOR EQ/NE tests.
12806 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12807 match( Set flags (CmpL src zero ));
12808 ins_cost(100);
12809 format %{ "TEST $src.hi,$src.hi" %}
12810 opcode(0x85);
12811 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12812 ins_pipe( ialu_cr_reg_reg );
12813 %}
12815 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12816 // compares. Can be used for LE or GT compares by reversing arguments.
12817 // NOT GOOD FOR EQ/NE tests.
12818 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12819 match( Set flags (CmpL src1 src2 ));
12820 effect( TEMP tmp );
12821 ins_cost(300);
12822 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12823 "MOV $tmp,$src1.hi\n\t"
12824 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12825 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12826 ins_pipe( ialu_cr_reg_reg );
12827 %}
12829 // Long compares reg < zero/req OR reg >= zero/req.
12830 // Just a wrapper for a normal branch, plus the predicate test.
12831 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12832 match(If cmp flags);
12833 effect(USE labl);
12834 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12835 expand %{
12836 jmpCon(cmp,flags,labl); // JLT or JGE...
12837 %}
12838 %}
12840 // Compare 2 longs and CMOVE longs.
12841 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12842 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12843 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12844 ins_cost(400);
12845 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12846 "CMOV$cmp $dst.hi,$src.hi" %}
12847 opcode(0x0F,0x40);
12848 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12849 ins_pipe( pipe_cmov_reg_long );
12850 %}
12852 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12853 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12854 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12855 ins_cost(500);
12856 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12857 "CMOV$cmp $dst.hi,$src.hi" %}
12858 opcode(0x0F,0x40);
12859 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12860 ins_pipe( pipe_cmov_reg_long );
12861 %}
12863 // Compare 2 longs and CMOVE ints.
12864 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12865 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12866 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12867 ins_cost(200);
12868 format %{ "CMOV$cmp $dst,$src" %}
12869 opcode(0x0F,0x40);
12870 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12871 ins_pipe( pipe_cmov_reg );
12872 %}
12874 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12875 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12876 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12877 ins_cost(250);
12878 format %{ "CMOV$cmp $dst,$src" %}
12879 opcode(0x0F,0x40);
12880 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12881 ins_pipe( pipe_cmov_mem );
12882 %}
12884 // Compare 2 longs and CMOVE ints.
12885 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12886 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12887 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12888 ins_cost(200);
12889 format %{ "CMOV$cmp $dst,$src" %}
12890 opcode(0x0F,0x40);
12891 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12892 ins_pipe( pipe_cmov_reg );
12893 %}
12895 // Compare 2 longs and CMOVE doubles
12896 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12897 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12898 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12899 ins_cost(200);
12900 expand %{
12901 fcmovD_regS(cmp,flags,dst,src);
12902 %}
12903 %}
12905 // Compare 2 longs and CMOVE doubles
12906 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
12907 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12908 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12909 ins_cost(200);
12910 expand %{
12911 fcmovXD_regS(cmp,flags,dst,src);
12912 %}
12913 %}
12915 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12916 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12917 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12918 ins_cost(200);
12919 expand %{
12920 fcmovF_regS(cmp,flags,dst,src);
12921 %}
12922 %}
12924 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
12925 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12926 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12927 ins_cost(200);
12928 expand %{
12929 fcmovX_regS(cmp,flags,dst,src);
12930 %}
12931 %}
12933 //======
12934 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12935 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12936 match( Set flags (CmpL src zero ));
12937 effect(TEMP tmp);
12938 ins_cost(200);
12939 format %{ "MOV $tmp,$src.lo\n\t"
12940 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12941 ins_encode( long_cmp_flags0( src, tmp ) );
12942 ins_pipe( ialu_reg_reg_long );
12943 %}
12945 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12946 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12947 match( Set flags (CmpL src1 src2 ));
12948 ins_cost(200+300);
12949 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12950 "JNE,s skip\n\t"
12951 "CMP $src1.hi,$src2.hi\n\t"
12952 "skip:\t" %}
12953 ins_encode( long_cmp_flags1( src1, src2 ) );
12954 ins_pipe( ialu_cr_reg_reg );
12955 %}
12957 // Long compare reg == zero/reg OR reg != zero/reg
12958 // Just a wrapper for a normal branch, plus the predicate test.
12959 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12960 match(If cmp flags);
12961 effect(USE labl);
12962 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12963 expand %{
12964 jmpCon(cmp,flags,labl); // JEQ or JNE...
12965 %}
12966 %}
12968 // Compare 2 longs and CMOVE longs.
12969 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12970 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12971 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12972 ins_cost(400);
12973 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12974 "CMOV$cmp $dst.hi,$src.hi" %}
12975 opcode(0x0F,0x40);
12976 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12977 ins_pipe( pipe_cmov_reg_long );
12978 %}
12980 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12981 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12982 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12983 ins_cost(500);
12984 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12985 "CMOV$cmp $dst.hi,$src.hi" %}
12986 opcode(0x0F,0x40);
12987 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12988 ins_pipe( pipe_cmov_reg_long );
12989 %}
12991 // Compare 2 longs and CMOVE ints.
12992 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12993 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12994 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12995 ins_cost(200);
12996 format %{ "CMOV$cmp $dst,$src" %}
12997 opcode(0x0F,0x40);
12998 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12999 ins_pipe( pipe_cmov_reg );
13000 %}
13002 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13003 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13004 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13005 ins_cost(250);
13006 format %{ "CMOV$cmp $dst,$src" %}
13007 opcode(0x0F,0x40);
13008 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13009 ins_pipe( pipe_cmov_mem );
13010 %}
13012 // Compare 2 longs and CMOVE ints.
13013 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13014 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13015 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13016 ins_cost(200);
13017 format %{ "CMOV$cmp $dst,$src" %}
13018 opcode(0x0F,0x40);
13019 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13020 ins_pipe( pipe_cmov_reg );
13021 %}
13023 // Compare 2 longs and CMOVE doubles
13024 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13025 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13026 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13027 ins_cost(200);
13028 expand %{
13029 fcmovD_regS(cmp,flags,dst,src);
13030 %}
13031 %}
13033 // Compare 2 longs and CMOVE doubles
13034 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13035 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13036 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13037 ins_cost(200);
13038 expand %{
13039 fcmovXD_regS(cmp,flags,dst,src);
13040 %}
13041 %}
13043 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13044 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13045 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13046 ins_cost(200);
13047 expand %{
13048 fcmovF_regS(cmp,flags,dst,src);
13049 %}
13050 %}
13052 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13053 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13054 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13055 ins_cost(200);
13056 expand %{
13057 fcmovX_regS(cmp,flags,dst,src);
13058 %}
13059 %}
13061 //======
13062 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13063 // Same as cmpL_reg_flags_LEGT except must negate src
13064 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13065 match( Set flags (CmpL src zero ));
13066 effect( TEMP tmp );
13067 ins_cost(300);
13068 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13069 "CMP $tmp,$src.lo\n\t"
13070 "SBB $tmp,$src.hi\n\t" %}
13071 ins_encode( long_cmp_flags3(src, tmp) );
13072 ins_pipe( ialu_reg_reg_long );
13073 %}
13075 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13076 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13077 // requires a commuted test to get the same result.
13078 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13079 match( Set flags (CmpL src1 src2 ));
13080 effect( TEMP tmp );
13081 ins_cost(300);
13082 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13083 "MOV $tmp,$src2.hi\n\t"
13084 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13085 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13086 ins_pipe( ialu_cr_reg_reg );
13087 %}
13089 // Long compares reg < zero/req OR reg >= zero/req.
13090 // Just a wrapper for a normal branch, plus the predicate test
13091 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13092 match(If cmp flags);
13093 effect(USE labl);
13094 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13095 ins_cost(300);
13096 expand %{
13097 jmpCon(cmp,flags,labl); // JGT or JLE...
13098 %}
13099 %}
13101 // Compare 2 longs and CMOVE longs.
13102 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13103 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13104 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13105 ins_cost(400);
13106 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13107 "CMOV$cmp $dst.hi,$src.hi" %}
13108 opcode(0x0F,0x40);
13109 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13110 ins_pipe( pipe_cmov_reg_long );
13111 %}
13113 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13114 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13115 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13116 ins_cost(500);
13117 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13118 "CMOV$cmp $dst.hi,$src.hi+4" %}
13119 opcode(0x0F,0x40);
13120 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13121 ins_pipe( pipe_cmov_reg_long );
13122 %}
13124 // Compare 2 longs and CMOVE ints.
13125 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13126 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13127 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13128 ins_cost(200);
13129 format %{ "CMOV$cmp $dst,$src" %}
13130 opcode(0x0F,0x40);
13131 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13132 ins_pipe( pipe_cmov_reg );
13133 %}
13135 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13136 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13137 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13138 ins_cost(250);
13139 format %{ "CMOV$cmp $dst,$src" %}
13140 opcode(0x0F,0x40);
13141 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13142 ins_pipe( pipe_cmov_mem );
13143 %}
13145 // Compare 2 longs and CMOVE ptrs.
13146 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13147 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13148 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13149 ins_cost(200);
13150 format %{ "CMOV$cmp $dst,$src" %}
13151 opcode(0x0F,0x40);
13152 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13153 ins_pipe( pipe_cmov_reg );
13154 %}
13156 // Compare 2 longs and CMOVE doubles
13157 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13158 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13159 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13160 ins_cost(200);
13161 expand %{
13162 fcmovD_regS(cmp,flags,dst,src);
13163 %}
13164 %}
13166 // Compare 2 longs and CMOVE doubles
13167 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13168 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13169 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13170 ins_cost(200);
13171 expand %{
13172 fcmovXD_regS(cmp,flags,dst,src);
13173 %}
13174 %}
13176 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13177 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13178 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13179 ins_cost(200);
13180 expand %{
13181 fcmovF_regS(cmp,flags,dst,src);
13182 %}
13183 %}
13186 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13187 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13188 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13189 ins_cost(200);
13190 expand %{
13191 fcmovX_regS(cmp,flags,dst,src);
13192 %}
13193 %}
13196 // ============================================================================
13197 // Procedure Call/Return Instructions
13198 // Call Java Static Instruction
13199 // Note: If this code changes, the corresponding ret_addr_offset() and
13200 // compute_padding() functions will have to be adjusted.
13201 instruct CallStaticJavaDirect(method meth) %{
13202 match(CallStaticJava);
13203 effect(USE meth);
13205 ins_cost(300);
13206 format %{ "CALL,static " %}
13207 opcode(0xE8); /* E8 cd */
13208 ins_encode( pre_call_FPU,
13209 Java_Static_Call( meth ),
13210 call_epilog,
13211 post_call_FPU );
13212 ins_pipe( pipe_slow );
13213 ins_pc_relative(1);
13214 ins_alignment(4);
13215 %}
13217 // Call Java Dynamic Instruction
13218 // Note: If this code changes, the corresponding ret_addr_offset() and
13219 // compute_padding() functions will have to be adjusted.
13220 instruct CallDynamicJavaDirect(method meth) %{
13221 match(CallDynamicJava);
13222 effect(USE meth);
13224 ins_cost(300);
13225 format %{ "MOV EAX,(oop)-1\n\t"
13226 "CALL,dynamic" %}
13227 opcode(0xE8); /* E8 cd */
13228 ins_encode( pre_call_FPU,
13229 Java_Dynamic_Call( meth ),
13230 call_epilog,
13231 post_call_FPU );
13232 ins_pipe( pipe_slow );
13233 ins_pc_relative(1);
13234 ins_alignment(4);
13235 %}
13237 // Call Runtime Instruction
13238 instruct CallRuntimeDirect(method meth) %{
13239 match(CallRuntime );
13240 effect(USE meth);
13242 ins_cost(300);
13243 format %{ "CALL,runtime " %}
13244 opcode(0xE8); /* E8 cd */
13245 // Use FFREEs to clear entries in float stack
13246 ins_encode( pre_call_FPU,
13247 FFree_Float_Stack_All,
13248 Java_To_Runtime( meth ),
13249 post_call_FPU );
13250 ins_pipe( pipe_slow );
13251 ins_pc_relative(1);
13252 %}
13254 // Call runtime without safepoint
13255 instruct CallLeafDirect(method meth) %{
13256 match(CallLeaf);
13257 effect(USE meth);
13259 ins_cost(300);
13260 format %{ "CALL_LEAF,runtime " %}
13261 opcode(0xE8); /* E8 cd */
13262 ins_encode( pre_call_FPU,
13263 FFree_Float_Stack_All,
13264 Java_To_Runtime( meth ),
13265 Verify_FPU_For_Leaf, post_call_FPU );
13266 ins_pipe( pipe_slow );
13267 ins_pc_relative(1);
13268 %}
13270 instruct CallLeafNoFPDirect(method meth) %{
13271 match(CallLeafNoFP);
13272 effect(USE meth);
13274 ins_cost(300);
13275 format %{ "CALL_LEAF_NOFP,runtime " %}
13276 opcode(0xE8); /* E8 cd */
13277 ins_encode(Java_To_Runtime(meth));
13278 ins_pipe( pipe_slow );
13279 ins_pc_relative(1);
13280 %}
13283 // Return Instruction
13284 // Remove the return address & jump to it.
13285 instruct Ret() %{
13286 match(Return);
13287 format %{ "RET" %}
13288 opcode(0xC3);
13289 ins_encode(OpcP);
13290 ins_pipe( pipe_jmp );
13291 %}
13293 // Tail Call; Jump from runtime stub to Java code.
13294 // Also known as an 'interprocedural jump'.
13295 // Target of jump will eventually return to caller.
13296 // TailJump below removes the return address.
13297 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13298 match(TailCall jump_target method_oop );
13299 ins_cost(300);
13300 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13301 opcode(0xFF, 0x4); /* Opcode FF /4 */
13302 ins_encode( OpcP, RegOpc(jump_target) );
13303 ins_pipe( pipe_jmp );
13304 %}
13307 // Tail Jump; remove the return address; jump to target.
13308 // TailCall above leaves the return address around.
13309 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13310 match( TailJump jump_target ex_oop );
13311 ins_cost(300);
13312 format %{ "POP EDX\t# pop return address into dummy\n\t"
13313 "JMP $jump_target " %}
13314 opcode(0xFF, 0x4); /* Opcode FF /4 */
13315 ins_encode( enc_pop_rdx,
13316 OpcP, RegOpc(jump_target) );
13317 ins_pipe( pipe_jmp );
13318 %}
13320 // Create exception oop: created by stack-crawling runtime code.
13321 // Created exception is now available to this handler, and is setup
13322 // just prior to jumping to this handler. No code emitted.
13323 instruct CreateException( eAXRegP ex_oop )
13324 %{
13325 match(Set ex_oop (CreateEx));
13327 size(0);
13328 // use the following format syntax
13329 format %{ "# exception oop is in EAX; no code emitted" %}
13330 ins_encode();
13331 ins_pipe( empty );
13332 %}
13335 // Rethrow exception:
13336 // The exception oop will come in the first argument position.
13337 // Then JUMP (not call) to the rethrow stub code.
13338 instruct RethrowException()
13339 %{
13340 match(Rethrow);
13342 // use the following format syntax
13343 format %{ "JMP rethrow_stub" %}
13344 ins_encode(enc_rethrow);
13345 ins_pipe( pipe_jmp );
13346 %}
13348 // inlined locking and unlocking
13351 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13352 match( Set cr (FastLock object box) );
13353 effect( TEMP tmp, TEMP scr );
13354 ins_cost(300);
13355 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13356 ins_encode( Fast_Lock(object,box,tmp,scr) );
13357 ins_pipe( pipe_slow );
13358 ins_pc_relative(1);
13359 %}
13361 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13362 match( Set cr (FastUnlock object box) );
13363 effect( TEMP tmp );
13364 ins_cost(300);
13365 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13366 ins_encode( Fast_Unlock(object,box,tmp) );
13367 ins_pipe( pipe_slow );
13368 ins_pc_relative(1);
13369 %}
13373 // ============================================================================
13374 // Safepoint Instruction
13375 instruct safePoint_poll(eFlagsReg cr) %{
13376 match(SafePoint);
13377 effect(KILL cr);
13379 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13380 // On SPARC that might be acceptable as we can generate the address with
13381 // just a sethi, saving an or. By polling at offset 0 we can end up
13382 // putting additional pressure on the index-0 in the D$. Because of
13383 // alignment (just like the situation at hand) the lower indices tend
13384 // to see more traffic. It'd be better to change the polling address
13385 // to offset 0 of the last $line in the polling page.
13387 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13388 ins_cost(125);
13389 size(6) ;
13390 ins_encode( Safepoint_Poll() );
13391 ins_pipe( ialu_reg_mem );
13392 %}
13394 //----------PEEPHOLE RULES-----------------------------------------------------
13395 // These must follow all instruction definitions as they use the names
13396 // defined in the instructions definitions.
13397 //
13398 // peepmatch ( root_instr_name [preceding_instruction]* );
13399 //
13400 // peepconstraint %{
13401 // (instruction_number.operand_name relational_op instruction_number.operand_name
13402 // [, ...] );
13403 // // instruction numbers are zero-based using left to right order in peepmatch
13404 //
13405 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13406 // // provide an instruction_number.operand_name for each operand that appears
13407 // // in the replacement instruction's match rule
13408 //
13409 // ---------VM FLAGS---------------------------------------------------------
13410 //
13411 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13412 //
13413 // Each peephole rule is given an identifying number starting with zero and
13414 // increasing by one in the order seen by the parser. An individual peephole
13415 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13416 // on the command-line.
13417 //
13418 // ---------CURRENT LIMITATIONS----------------------------------------------
13419 //
13420 // Only match adjacent instructions in same basic block
13421 // Only equality constraints
13422 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13423 // Only one replacement instruction
13424 //
13425 // ---------EXAMPLE----------------------------------------------------------
13426 //
13427 // // pertinent parts of existing instructions in architecture description
13428 // instruct movI(eRegI dst, eRegI src) %{
13429 // match(Set dst (CopyI src));
13430 // %}
13431 //
13432 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13433 // match(Set dst (AddI dst src));
13434 // effect(KILL cr);
13435 // %}
13436 //
13437 // // Change (inc mov) to lea
13438 // peephole %{
13439 // // increment preceeded by register-register move
13440 // peepmatch ( incI_eReg movI );
13441 // // require that the destination register of the increment
13442 // // match the destination register of the move
13443 // peepconstraint ( 0.dst == 1.dst );
13444 // // construct a replacement instruction that sets
13445 // // the destination to ( move's source register + one )
13446 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13447 // %}
13448 //
13449 // Implementation no longer uses movX instructions since
13450 // machine-independent system no longer uses CopyX nodes.
13451 //
13452 // peephole %{
13453 // peepmatch ( incI_eReg movI );
13454 // peepconstraint ( 0.dst == 1.dst );
13455 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13456 // %}
13457 //
13458 // peephole %{
13459 // peepmatch ( decI_eReg movI );
13460 // peepconstraint ( 0.dst == 1.dst );
13461 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13462 // %}
13463 //
13464 // peephole %{
13465 // peepmatch ( addI_eReg_imm movI );
13466 // peepconstraint ( 0.dst == 1.dst );
13467 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13468 // %}
13469 //
13470 // peephole %{
13471 // peepmatch ( addP_eReg_imm movP );
13472 // peepconstraint ( 0.dst == 1.dst );
13473 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13474 // %}
13476 // // Change load of spilled value to only a spill
13477 // instruct storeI(memory mem, eRegI src) %{
13478 // match(Set mem (StoreI mem src));
13479 // %}
13480 //
13481 // instruct loadI(eRegI dst, memory mem) %{
13482 // match(Set dst (LoadI mem));
13483 // %}
13484 //
13485 peephole %{
13486 peepmatch ( loadI storeI );
13487 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13488 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13489 %}
13491 //----------SMARTSPILL RULES---------------------------------------------------
13492 // These must follow all instruction definitions as they use the names
13493 // defined in the instructions definitions.