src/cpu/x86/vm/icache_x86.hpp

Fri, 16 Aug 2019 16:50:17 +0200

author
eosterlund
date
Fri, 16 Aug 2019 16:50:17 +0200
changeset 9834
bb1da64b0492
parent 2984
6ae7a1561b53
child 6876
710a3c8b516e
permissions
-rw-r--r--

8229345: Memory leak due to vtable stubs not being shared on SPARC
Reviewed-by: mdoerr, dholmes, kvn

     1 /*
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     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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     5  * This code is free software; you can redistribute it and/or modify it
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     9  * This code is distributed in the hope that it will be useful, but WITHOUT
    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    12  * version 2 for more details (a copy is included in the LICENSE file that
    13  * accompanied this code).
    14  *
    15  * You should have received a copy of the GNU General Public License version
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    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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    25 #ifndef CPU_X86_VM_ICACHE_X86_HPP
    26 #define CPU_X86_VM_ICACHE_X86_HPP
    28 // Interface for updating the instruction cache.  Whenever the VM modifies
    29 // code, part of the processor instruction cache potentially has to be flushed.
    31 // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
    32 // after the next jump, and the VM never modifies instructions directly ahead
    33 // of the instruction fetch path.
    35 // [phh] It's not clear that the above comment is correct, because on an MP
    36 // system where the dcaches are not snooped, only the thread doing the invalidate
    37 // will see the update.  Even in the snooped case, a memory fence would be
    38 // necessary if stores weren't ordered.  Fortunately, they are on all known
    39 // x86 implementations.
    41 class ICache : public AbstractICache {
    42  public:
    43 #ifdef AMD64
    44   enum {
    45     stub_size      = 64, // Size of the icache flush stub in bytes
    46     line_size      = 64, // Icache line size in bytes
    47     log2_line_size = 6   // log2(line_size)
    48   };
    50   // Use default implementation
    51 #else
    52   enum {
    53     stub_size      = 16,                 // Size of the icache flush stub in bytes
    54     line_size      = BytesPerWord,      // conservative
    55     log2_line_size = LogBytesPerWord    // log2(line_size)
    56   };
    57 #endif // AMD64
    58 };
    60 #endif // CPU_X86_VM_ICACHE_X86_HPP

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