Tue, 22 Jan 2013 15:34:16 -0800
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
Summary: Use SSE4.2 and AVX2 instructions for encodeArray intrinsic.
Reviewed-by: roland
1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #ifndef SERIALGC
40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
42 #include "gc_implementation/g1/heapRegion.hpp"
43 #endif
45 #ifdef PRODUCT
46 #define BLOCK_COMMENT(str) /* nothing */
47 #define STOP(error) stop(error)
48 #else
49 #define BLOCK_COMMENT(str) block_comment(str)
50 #define STOP(error) block_comment(error); stop(error)
51 #endif
53 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
54 // Implementation of AddressLiteral
56 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
57 _is_lval = false;
58 _target = target;
59 switch (rtype) {
60 case relocInfo::oop_type:
61 case relocInfo::metadata_type:
62 // Oops are a special case. Normally they would be their own section
63 // but in cases like icBuffer they are literals in the code stream that
64 // we don't have a section for. We use none so that we get a literal address
65 // which is always patchable.
66 break;
67 case relocInfo::external_word_type:
68 _rspec = external_word_Relocation::spec(target);
69 break;
70 case relocInfo::internal_word_type:
71 _rspec = internal_word_Relocation::spec(target);
72 break;
73 case relocInfo::opt_virtual_call_type:
74 _rspec = opt_virtual_call_Relocation::spec();
75 break;
76 case relocInfo::static_call_type:
77 _rspec = static_call_Relocation::spec();
78 break;
79 case relocInfo::runtime_call_type:
80 _rspec = runtime_call_Relocation::spec();
81 break;
82 case relocInfo::poll_type:
83 case relocInfo::poll_return_type:
84 _rspec = Relocation::spec_simple(rtype);
85 break;
86 case relocInfo::none:
87 break;
88 default:
89 ShouldNotReachHere();
90 break;
91 }
92 }
94 // Implementation of Address
96 #ifdef _LP64
98 Address Address::make_array(ArrayAddress adr) {
99 // Not implementable on 64bit machines
100 // Should have been handled higher up the call chain.
101 ShouldNotReachHere();
102 return Address();
103 }
105 // exceedingly dangerous constructor
106 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
107 _base = noreg;
108 _index = noreg;
109 _scale = no_scale;
110 _disp = disp;
111 switch (rtype) {
112 case relocInfo::external_word_type:
113 _rspec = external_word_Relocation::spec(loc);
114 break;
115 case relocInfo::internal_word_type:
116 _rspec = internal_word_Relocation::spec(loc);
117 break;
118 case relocInfo::runtime_call_type:
119 // HMM
120 _rspec = runtime_call_Relocation::spec();
121 break;
122 case relocInfo::poll_type:
123 case relocInfo::poll_return_type:
124 _rspec = Relocation::spec_simple(rtype);
125 break;
126 case relocInfo::none:
127 break;
128 default:
129 ShouldNotReachHere();
130 }
131 }
132 #else // LP64
134 Address Address::make_array(ArrayAddress adr) {
135 AddressLiteral base = adr.base();
136 Address index = adr.index();
137 assert(index._disp == 0, "must not have disp"); // maybe it can?
138 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
139 array._rspec = base._rspec;
140 return array;
141 }
143 // exceedingly dangerous constructor
144 Address::Address(address loc, RelocationHolder spec) {
145 _base = noreg;
146 _index = noreg;
147 _scale = no_scale;
148 _disp = (intptr_t) loc;
149 _rspec = spec;
150 }
152 #endif // _LP64
156 // Convert the raw encoding form into the form expected by the constructor for
157 // Address. An index of 4 (rsp) corresponds to having no index, so convert
158 // that to noreg for the Address constructor.
159 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
160 RelocationHolder rspec;
161 if (disp_reloc != relocInfo::none) {
162 rspec = Relocation::spec_simple(disp_reloc);
163 }
164 bool valid_index = index != rsp->encoding();
165 if (valid_index) {
166 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
167 madr._rspec = rspec;
168 return madr;
169 } else {
170 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
171 madr._rspec = rspec;
172 return madr;
173 }
174 }
176 // Implementation of Assembler
178 int AbstractAssembler::code_fill_byte() {
179 return (u_char)'\xF4'; // hlt
180 }
182 // make this go away someday
183 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
184 if (rtype == relocInfo::none)
185 emit_int32(data);
186 else emit_data(data, Relocation::spec_simple(rtype), format);
187 }
189 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
190 assert(imm_operand == 0, "default format must be immediate in this file");
191 assert(inst_mark() != NULL, "must be inside InstructionMark");
192 if (rspec.type() != relocInfo::none) {
193 #ifdef ASSERT
194 check_relocation(rspec, format);
195 #endif
196 // Do not use AbstractAssembler::relocate, which is not intended for
197 // embedded words. Instead, relocate to the enclosing instruction.
199 // hack. call32 is too wide for mask so use disp32
200 if (format == call32_operand)
201 code_section()->relocate(inst_mark(), rspec, disp32_operand);
202 else
203 code_section()->relocate(inst_mark(), rspec, format);
204 }
205 emit_int32(data);
206 }
208 static int encode(Register r) {
209 int enc = r->encoding();
210 if (enc >= 8) {
211 enc -= 8;
212 }
213 return enc;
214 }
216 static int encode(XMMRegister r) {
217 int enc = r->encoding();
218 if (enc >= 8) {
219 enc -= 8;
220 }
221 return enc;
222 }
224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
225 assert(dst->has_byte_register(), "must have byte register");
226 assert(isByte(op1) && isByte(op2), "wrong opcode");
227 assert(isByte(imm8), "not a byte");
228 assert((op1 & 0x01) == 0, "should be 8bit operation");
229 emit_int8(op1);
230 emit_int8(op2 | encode(dst));
231 emit_int8(imm8);
232 }
235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
236 assert(isByte(op1) && isByte(op2), "wrong opcode");
237 assert((op1 & 0x01) == 1, "should be 32bit operation");
238 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
239 if (is8bit(imm32)) {
240 emit_int8(op1 | 0x02); // set sign bit
241 emit_int8(op2 | encode(dst));
242 emit_int8(imm32 & 0xFF);
243 } else {
244 emit_int8(op1);
245 emit_int8(op2 | encode(dst));
246 emit_int32(imm32);
247 }
248 }
250 // Force generation of a 4 byte immediate value even if it fits into 8bit
251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
252 assert(isByte(op1) && isByte(op2), "wrong opcode");
253 assert((op1 & 0x01) == 1, "should be 32bit operation");
254 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
255 emit_int8(op1);
256 emit_int8(op2 | encode(dst));
257 emit_int32(imm32);
258 }
260 // immediate-to-memory forms
261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
262 assert((op1 & 0x01) == 1, "should be 32bit operation");
263 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
264 if (is8bit(imm32)) {
265 emit_int8(op1 | 0x02); // set sign bit
266 emit_operand(rm, adr, 1);
267 emit_int8(imm32 & 0xFF);
268 } else {
269 emit_int8(op1);
270 emit_operand(rm, adr, 4);
271 emit_int32(imm32);
272 }
273 }
276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
277 assert(isByte(op1) && isByte(op2), "wrong opcode");
278 emit_int8(op1);
279 emit_int8(op2 | encode(dst) << 3 | encode(src));
280 }
283 void Assembler::emit_operand(Register reg, Register base, Register index,
284 Address::ScaleFactor scale, int disp,
285 RelocationHolder const& rspec,
286 int rip_relative_correction) {
287 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
289 // Encode the registers as needed in the fields they are used in
291 int regenc = encode(reg) << 3;
292 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
293 int baseenc = base->is_valid() ? encode(base) : 0;
295 if (base->is_valid()) {
296 if (index->is_valid()) {
297 assert(scale != Address::no_scale, "inconsistent address");
298 // [base + index*scale + disp]
299 if (disp == 0 && rtype == relocInfo::none &&
300 base != rbp LP64_ONLY(&& base != r13)) {
301 // [base + index*scale]
302 // [00 reg 100][ss index base]
303 assert(index != rsp, "illegal addressing mode");
304 emit_int8(0x04 | regenc);
305 emit_int8(scale << 6 | indexenc | baseenc);
306 } else if (is8bit(disp) && rtype == relocInfo::none) {
307 // [base + index*scale + imm8]
308 // [01 reg 100][ss index base] imm8
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x44 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_int8(disp & 0xFF);
313 } else {
314 // [base + index*scale + disp32]
315 // [10 reg 100][ss index base] disp32
316 assert(index != rsp, "illegal addressing mode");
317 emit_int8(0x84 | regenc);
318 emit_int8(scale << 6 | indexenc | baseenc);
319 emit_data(disp, rspec, disp32_operand);
320 }
321 } else if (base == rsp LP64_ONLY(|| base == r12)) {
322 // [rsp + disp]
323 if (disp == 0 && rtype == relocInfo::none) {
324 // [rsp]
325 // [00 reg 100][00 100 100]
326 emit_int8(0x04 | regenc);
327 emit_int8(0x24);
328 } else if (is8bit(disp) && rtype == relocInfo::none) {
329 // [rsp + imm8]
330 // [01 reg 100][00 100 100] disp8
331 emit_int8(0x44 | regenc);
332 emit_int8(0x24);
333 emit_int8(disp & 0xFF);
334 } else {
335 // [rsp + imm32]
336 // [10 reg 100][00 100 100] disp32
337 emit_int8(0x84 | regenc);
338 emit_int8(0x24);
339 emit_data(disp, rspec, disp32_operand);
340 }
341 } else {
342 // [base + disp]
343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
344 if (disp == 0 && rtype == relocInfo::none &&
345 base != rbp LP64_ONLY(&& base != r13)) {
346 // [base]
347 // [00 reg base]
348 emit_int8(0x00 | regenc | baseenc);
349 } else if (is8bit(disp) && rtype == relocInfo::none) {
350 // [base + disp8]
351 // [01 reg base] disp8
352 emit_int8(0x40 | regenc | baseenc);
353 emit_int8(disp & 0xFF);
354 } else {
355 // [base + disp32]
356 // [10 reg base] disp32
357 emit_int8(0x80 | regenc | baseenc);
358 emit_data(disp, rspec, disp32_operand);
359 }
360 }
361 } else {
362 if (index->is_valid()) {
363 assert(scale != Address::no_scale, "inconsistent address");
364 // [index*scale + disp]
365 // [00 reg 100][ss index 101] disp32
366 assert(index != rsp, "illegal addressing mode");
367 emit_int8(0x04 | regenc);
368 emit_int8(scale << 6 | indexenc | 0x05);
369 emit_data(disp, rspec, disp32_operand);
370 } else if (rtype != relocInfo::none ) {
371 // [disp] (64bit) RIP-RELATIVE (32bit) abs
372 // [00 000 101] disp32
374 emit_int8(0x05 | regenc);
375 // Note that the RIP-rel. correction applies to the generated
376 // disp field, but _not_ to the target address in the rspec.
378 // disp was created by converting the target address minus the pc
379 // at the start of the instruction. That needs more correction here.
380 // intptr_t disp = target - next_ip;
381 assert(inst_mark() != NULL, "must be inside InstructionMark");
382 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
383 int64_t adjusted = disp;
384 // Do rip-rel adjustment for 64bit
385 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
386 assert(is_simm32(adjusted),
387 "must be 32bit offset (RIP relative address)");
388 emit_data((int32_t) adjusted, rspec, disp32_operand);
390 } else {
391 // 32bit never did this, did everything as the rip-rel/disp code above
392 // [disp] ABSOLUTE
393 // [00 reg 100][00 100 101] disp32
394 emit_int8(0x04 | regenc);
395 emit_int8(0x25);
396 emit_data(disp, rspec, disp32_operand);
397 }
398 }
399 }
401 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
402 Address::ScaleFactor scale, int disp,
403 RelocationHolder const& rspec) {
404 emit_operand((Register)reg, base, index, scale, disp, rspec);
405 }
407 // Secret local extension to Assembler::WhichOperand:
408 #define end_pc_operand (_WhichOperand_limit)
410 address Assembler::locate_operand(address inst, WhichOperand which) {
411 // Decode the given instruction, and return the address of
412 // an embedded 32-bit operand word.
414 // If "which" is disp32_operand, selects the displacement portion
415 // of an effective address specifier.
416 // If "which" is imm64_operand, selects the trailing immediate constant.
417 // If "which" is call32_operand, selects the displacement of a call or jump.
418 // Caller is responsible for ensuring that there is such an operand,
419 // and that it is 32/64 bits wide.
421 // If "which" is end_pc_operand, find the end of the instruction.
423 address ip = inst;
424 bool is_64bit = false;
426 debug_only(bool has_disp32 = false);
427 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
429 again_after_prefix:
430 switch (0xFF & *ip++) {
432 // These convenience macros generate groups of "case" labels for the switch.
433 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
434 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
435 case (x)+4: case (x)+5: case (x)+6: case (x)+7
436 #define REP16(x) REP8((x)+0): \
437 case REP8((x)+8)
439 case CS_segment:
440 case SS_segment:
441 case DS_segment:
442 case ES_segment:
443 case FS_segment:
444 case GS_segment:
445 // Seems dubious
446 LP64_ONLY(assert(false, "shouldn't have that prefix"));
447 assert(ip == inst+1, "only one prefix allowed");
448 goto again_after_prefix;
450 case 0x67:
451 case REX:
452 case REX_B:
453 case REX_X:
454 case REX_XB:
455 case REX_R:
456 case REX_RB:
457 case REX_RX:
458 case REX_RXB:
459 NOT_LP64(assert(false, "64bit prefixes"));
460 goto again_after_prefix;
462 case REX_W:
463 case REX_WB:
464 case REX_WX:
465 case REX_WXB:
466 case REX_WR:
467 case REX_WRB:
468 case REX_WRX:
469 case REX_WRXB:
470 NOT_LP64(assert(false, "64bit prefixes"));
471 is_64bit = true;
472 goto again_after_prefix;
474 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
475 case 0x88: // movb a, r
476 case 0x89: // movl a, r
477 case 0x8A: // movb r, a
478 case 0x8B: // movl r, a
479 case 0x8F: // popl a
480 debug_only(has_disp32 = true);
481 break;
483 case 0x68: // pushq #32
484 if (which == end_pc_operand) {
485 return ip + 4;
486 }
487 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
488 return ip; // not produced by emit_operand
490 case 0x66: // movw ... (size prefix)
491 again_after_size_prefix2:
492 switch (0xFF & *ip++) {
493 case REX:
494 case REX_B:
495 case REX_X:
496 case REX_XB:
497 case REX_R:
498 case REX_RB:
499 case REX_RX:
500 case REX_RXB:
501 case REX_W:
502 case REX_WB:
503 case REX_WX:
504 case REX_WXB:
505 case REX_WR:
506 case REX_WRB:
507 case REX_WRX:
508 case REX_WRXB:
509 NOT_LP64(assert(false, "64bit prefix found"));
510 goto again_after_size_prefix2;
511 case 0x8B: // movw r, a
512 case 0x89: // movw a, r
513 debug_only(has_disp32 = true);
514 break;
515 case 0xC7: // movw a, #16
516 debug_only(has_disp32 = true);
517 tail_size = 2; // the imm16
518 break;
519 case 0x0F: // several SSE/SSE2 variants
520 ip--; // reparse the 0x0F
521 goto again_after_prefix;
522 default:
523 ShouldNotReachHere();
524 }
525 break;
527 case REP8(0xB8): // movl/q r, #32/#64(oop?)
528 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
529 // these asserts are somewhat nonsensical
530 #ifndef _LP64
531 assert(which == imm_operand || which == disp32_operand,
532 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
533 #else
534 assert((which == call32_operand || which == imm_operand) && is_64bit ||
535 which == narrow_oop_operand && !is_64bit,
536 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
537 #endif // _LP64
538 return ip;
540 case 0x69: // imul r, a, #32
541 case 0xC7: // movl a, #32(oop?)
542 tail_size = 4;
543 debug_only(has_disp32 = true); // has both kinds of operands!
544 break;
546 case 0x0F: // movx..., etc.
547 switch (0xFF & *ip++) {
548 case 0x3A: // pcmpestri
549 tail_size = 1;
550 case 0x38: // ptest, pmovzxbw
551 ip++; // skip opcode
552 debug_only(has_disp32 = true); // has both kinds of operands!
553 break;
555 case 0x70: // pshufd r, r/a, #8
556 debug_only(has_disp32 = true); // has both kinds of operands!
557 case 0x73: // psrldq r, #8
558 tail_size = 1;
559 break;
561 case 0x12: // movlps
562 case 0x28: // movaps
563 case 0x2E: // ucomiss
564 case 0x2F: // comiss
565 case 0x54: // andps
566 case 0x55: // andnps
567 case 0x56: // orps
568 case 0x57: // xorps
569 case 0x6E: // movd
570 case 0x7E: // movd
571 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
572 debug_only(has_disp32 = true);
573 break;
575 case 0xAD: // shrd r, a, %cl
576 case 0xAF: // imul r, a
577 case 0xBE: // movsbl r, a (movsxb)
578 case 0xBF: // movswl r, a (movsxw)
579 case 0xB6: // movzbl r, a (movzxb)
580 case 0xB7: // movzwl r, a (movzxw)
581 case REP16(0x40): // cmovl cc, r, a
582 case 0xB0: // cmpxchgb
583 case 0xB1: // cmpxchg
584 case 0xC1: // xaddl
585 case 0xC7: // cmpxchg8
586 case REP16(0x90): // setcc a
587 debug_only(has_disp32 = true);
588 // fall out of the switch to decode the address
589 break;
591 case 0xC4: // pinsrw r, a, #8
592 debug_only(has_disp32 = true);
593 case 0xC5: // pextrw r, r, #8
594 tail_size = 1; // the imm8
595 break;
597 case 0xAC: // shrd r, a, #8
598 debug_only(has_disp32 = true);
599 tail_size = 1; // the imm8
600 break;
602 case REP16(0x80): // jcc rdisp32
603 if (which == end_pc_operand) return ip + 4;
604 assert(which == call32_operand, "jcc has no disp32 or imm");
605 return ip;
606 default:
607 ShouldNotReachHere();
608 }
609 break;
611 case 0x81: // addl a, #32; addl r, #32
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 // on 32bit in the case of cmpl, the imm might be an oop
614 tail_size = 4;
615 debug_only(has_disp32 = true); // has both kinds of operands!
616 break;
618 case 0x83: // addl a, #8; addl r, #8
619 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
620 debug_only(has_disp32 = true); // has both kinds of operands!
621 tail_size = 1;
622 break;
624 case 0x9B:
625 switch (0xFF & *ip++) {
626 case 0xD9: // fnstcw a
627 debug_only(has_disp32 = true);
628 break;
629 default:
630 ShouldNotReachHere();
631 }
632 break;
634 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
635 case REP4(0x10): // adc...
636 case REP4(0x20): // and...
637 case REP4(0x30): // xor...
638 case REP4(0x08): // or...
639 case REP4(0x18): // sbb...
640 case REP4(0x28): // sub...
641 case 0xF7: // mull a
642 case 0x8D: // lea r, a
643 case 0x87: // xchg r, a
644 case REP4(0x38): // cmp...
645 case 0x85: // test r, a
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 break;
649 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
650 case 0xC6: // movb a, #8
651 case 0x80: // cmpb a, #8
652 case 0x6B: // imul r, a, #8
653 debug_only(has_disp32 = true); // has both kinds of operands!
654 tail_size = 1; // the imm8
655 break;
657 case 0xC4: // VEX_3bytes
658 case 0xC5: // VEX_2bytes
659 assert((UseAVX > 0), "shouldn't have VEX prefix");
660 assert(ip == inst+1, "no prefixes allowed");
661 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
662 // but they have prefix 0x0F and processed when 0x0F processed above.
663 //
664 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
665 // instructions (these instructions are not supported in 64-bit mode).
666 // To distinguish them bits [7:6] are set in the VEX second byte since
667 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
668 // those VEX bits REX and vvvv bits are inverted.
669 //
670 // Fortunately C2 doesn't generate these instructions so we don't need
671 // to check for them in product version.
673 // Check second byte
674 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
676 // First byte
677 if ((0xFF & *inst) == VEX_3bytes) {
678 ip++; // third byte
679 is_64bit = ((VEX_W & *ip) == VEX_W);
680 }
681 ip++; // opcode
682 // To find the end of instruction (which == end_pc_operand).
683 switch (0xFF & *ip) {
684 case 0x61: // pcmpestri r, r/a, #8
685 case 0x70: // pshufd r, r/a, #8
686 case 0x73: // psrldq r, #8
687 tail_size = 1; // the imm8
688 break;
689 default:
690 break;
691 }
692 ip++; // skip opcode
693 debug_only(has_disp32 = true); // has both kinds of operands!
694 break;
696 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
697 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
698 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
699 case 0xDD: // fld_d a; fst_d a; fstp_d a
700 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
701 case 0xDF: // fild_d a; fistp_d a
702 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
703 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
704 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
705 debug_only(has_disp32 = true);
706 break;
708 case 0xE8: // call rdisp32
709 case 0xE9: // jmp rdisp32
710 if (which == end_pc_operand) return ip + 4;
711 assert(which == call32_operand, "call has no disp32 or imm");
712 return ip;
714 case 0xF0: // Lock
715 assert(os::is_MP(), "only on MP");
716 goto again_after_prefix;
718 case 0xF3: // For SSE
719 case 0xF2: // For SSE2
720 switch (0xFF & *ip++) {
721 case REX:
722 case REX_B:
723 case REX_X:
724 case REX_XB:
725 case REX_R:
726 case REX_RB:
727 case REX_RX:
728 case REX_RXB:
729 case REX_W:
730 case REX_WB:
731 case REX_WX:
732 case REX_WXB:
733 case REX_WR:
734 case REX_WRB:
735 case REX_WRX:
736 case REX_WRXB:
737 NOT_LP64(assert(false, "found 64bit prefix"));
738 ip++;
739 default:
740 ip++;
741 }
742 debug_only(has_disp32 = true); // has both kinds of operands!
743 break;
745 default:
746 ShouldNotReachHere();
748 #undef REP8
749 #undef REP16
750 }
752 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
753 #ifdef _LP64
754 assert(which != imm_operand, "instruction is not a movq reg, imm64");
755 #else
756 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
757 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
758 #endif // LP64
759 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
761 // parse the output of emit_operand
762 int op2 = 0xFF & *ip++;
763 int base = op2 & 0x07;
764 int op3 = -1;
765 const int b100 = 4;
766 const int b101 = 5;
767 if (base == b100 && (op2 >> 6) != 3) {
768 op3 = 0xFF & *ip++;
769 base = op3 & 0x07; // refetch the base
770 }
771 // now ip points at the disp (if any)
773 switch (op2 >> 6) {
774 case 0:
775 // [00 reg 100][ss index base]
776 // [00 reg 100][00 100 esp]
777 // [00 reg base]
778 // [00 reg 100][ss index 101][disp32]
779 // [00 reg 101] [disp32]
781 if (base == b101) {
782 if (which == disp32_operand)
783 return ip; // caller wants the disp32
784 ip += 4; // skip the disp32
785 }
786 break;
788 case 1:
789 // [01 reg 100][ss index base][disp8]
790 // [01 reg 100][00 100 esp][disp8]
791 // [01 reg base] [disp8]
792 ip += 1; // skip the disp8
793 break;
795 case 2:
796 // [10 reg 100][ss index base][disp32]
797 // [10 reg 100][00 100 esp][disp32]
798 // [10 reg base] [disp32]
799 if (which == disp32_operand)
800 return ip; // caller wants the disp32
801 ip += 4; // skip the disp32
802 break;
804 case 3:
805 // [11 reg base] (not a memory addressing mode)
806 break;
807 }
809 if (which == end_pc_operand) {
810 return ip + tail_size;
811 }
813 #ifdef _LP64
814 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
815 #else
816 assert(which == imm_operand, "instruction has only an imm field");
817 #endif // LP64
818 return ip;
819 }
821 address Assembler::locate_next_instruction(address inst) {
822 // Secretly share code with locate_operand:
823 return locate_operand(inst, end_pc_operand);
824 }
827 #ifdef ASSERT
828 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
829 address inst = inst_mark();
830 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
831 address opnd;
833 Relocation* r = rspec.reloc();
834 if (r->type() == relocInfo::none) {
835 return;
836 } else if (r->is_call() || format == call32_operand) {
837 // assert(format == imm32_operand, "cannot specify a nonzero format");
838 opnd = locate_operand(inst, call32_operand);
839 } else if (r->is_data()) {
840 assert(format == imm_operand || format == disp32_operand
841 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
842 opnd = locate_operand(inst, (WhichOperand)format);
843 } else {
844 assert(format == imm_operand, "cannot specify a format");
845 return;
846 }
847 assert(opnd == pc(), "must put operand where relocs can find it");
848 }
849 #endif // ASSERT
851 void Assembler::emit_operand32(Register reg, Address adr) {
852 assert(reg->encoding() < 8, "no extended registers");
853 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
854 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
855 adr._rspec);
856 }
858 void Assembler::emit_operand(Register reg, Address adr,
859 int rip_relative_correction) {
860 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
861 adr._rspec,
862 rip_relative_correction);
863 }
865 void Assembler::emit_operand(XMMRegister reg, Address adr) {
866 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
867 adr._rspec);
868 }
870 // MMX operations
871 void Assembler::emit_operand(MMXRegister reg, Address adr) {
872 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
873 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
874 }
876 // work around gcc (3.2.1-7a) bug
877 void Assembler::emit_operand(Address adr, MMXRegister reg) {
878 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
879 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
880 }
883 void Assembler::emit_farith(int b1, int b2, int i) {
884 assert(isByte(b1) && isByte(b2), "wrong opcode");
885 assert(0 <= i && i < 8, "illegal stack offset");
886 emit_int8(b1);
887 emit_int8(b2 + i);
888 }
891 // Now the Assembler instructions (identical for 32/64 bits)
893 void Assembler::adcl(Address dst, int32_t imm32) {
894 InstructionMark im(this);
895 prefix(dst);
896 emit_arith_operand(0x81, rdx, dst, imm32);
897 }
899 void Assembler::adcl(Address dst, Register src) {
900 InstructionMark im(this);
901 prefix(dst, src);
902 emit_int8(0x11);
903 emit_operand(src, dst);
904 }
906 void Assembler::adcl(Register dst, int32_t imm32) {
907 prefix(dst);
908 emit_arith(0x81, 0xD0, dst, imm32);
909 }
911 void Assembler::adcl(Register dst, Address src) {
912 InstructionMark im(this);
913 prefix(src, dst);
914 emit_int8(0x13);
915 emit_operand(dst, src);
916 }
918 void Assembler::adcl(Register dst, Register src) {
919 (void) prefix_and_encode(dst->encoding(), src->encoding());
920 emit_arith(0x13, 0xC0, dst, src);
921 }
923 void Assembler::addl(Address dst, int32_t imm32) {
924 InstructionMark im(this);
925 prefix(dst);
926 emit_arith_operand(0x81, rax, dst, imm32);
927 }
929 void Assembler::addl(Address dst, Register src) {
930 InstructionMark im(this);
931 prefix(dst, src);
932 emit_int8(0x01);
933 emit_operand(src, dst);
934 }
936 void Assembler::addl(Register dst, int32_t imm32) {
937 prefix(dst);
938 emit_arith(0x81, 0xC0, dst, imm32);
939 }
941 void Assembler::addl(Register dst, Address src) {
942 InstructionMark im(this);
943 prefix(src, dst);
944 emit_int8(0x03);
945 emit_operand(dst, src);
946 }
948 void Assembler::addl(Register dst, Register src) {
949 (void) prefix_and_encode(dst->encoding(), src->encoding());
950 emit_arith(0x03, 0xC0, dst, src);
951 }
953 void Assembler::addr_nop_4() {
954 assert(UseAddressNop, "no CPU support");
955 // 4 bytes: NOP DWORD PTR [EAX+0]
956 emit_int8(0x0F);
957 emit_int8(0x1F);
958 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
959 emit_int8(0); // 8-bits offset (1 byte)
960 }
962 void Assembler::addr_nop_5() {
963 assert(UseAddressNop, "no CPU support");
964 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
965 emit_int8(0x0F);
966 emit_int8(0x1F);
967 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
968 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
969 emit_int8(0); // 8-bits offset (1 byte)
970 }
972 void Assembler::addr_nop_7() {
973 assert(UseAddressNop, "no CPU support");
974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
975 emit_int8(0x0F);
976 emit_int8(0x1F);
977 emit_int8((unsigned char)0x80);
978 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
979 emit_int32(0); // 32-bits offset (4 bytes)
980 }
982 void Assembler::addr_nop_8() {
983 assert(UseAddressNop, "no CPU support");
984 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
985 emit_int8(0x0F);
986 emit_int8(0x1F);
987 emit_int8((unsigned char)0x84);
988 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
989 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
990 emit_int32(0); // 32-bits offset (4 bytes)
991 }
993 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
995 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
996 }
998 void Assembler::addsd(XMMRegister dst, Address src) {
999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1000 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1001 }
1003 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1005 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1006 }
1008 void Assembler::addss(XMMRegister dst, Address src) {
1009 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1010 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1011 }
1013 void Assembler::aesdec(XMMRegister dst, Address src) {
1014 assert(VM_Version::supports_aes(), "");
1015 InstructionMark im(this);
1016 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_operand(dst, src);
1019 }
1021 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1022 assert(VM_Version::supports_aes(), "");
1023 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1024 emit_int8((unsigned char)0xDE);
1025 emit_int8(0xC0 | encode);
1026 }
1028 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1029 assert(VM_Version::supports_aes(), "");
1030 InstructionMark im(this);
1031 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_operand(dst, src);
1034 }
1036 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1037 assert(VM_Version::supports_aes(), "");
1038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1039 emit_int8((unsigned char)0xDF);
1040 emit_int8((unsigned char)(0xC0 | encode));
1041 }
1043 void Assembler::aesenc(XMMRegister dst, Address src) {
1044 assert(VM_Version::supports_aes(), "");
1045 InstructionMark im(this);
1046 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_operand(dst, src);
1049 }
1051 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1052 assert(VM_Version::supports_aes(), "");
1053 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1054 emit_int8((unsigned char)0xDC);
1055 emit_int8(0xC0 | encode);
1056 }
1058 void Assembler::aesenclast(XMMRegister dst, Address src) {
1059 assert(VM_Version::supports_aes(), "");
1060 InstructionMark im(this);
1061 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_operand(dst, src);
1064 }
1066 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1067 assert(VM_Version::supports_aes(), "");
1068 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1069 emit_int8((unsigned char)0xDD);
1070 emit_int8((unsigned char)(0xC0 | encode));
1071 }
1074 void Assembler::andl(Address dst, int32_t imm32) {
1075 InstructionMark im(this);
1076 prefix(dst);
1077 emit_int8((unsigned char)0x81);
1078 emit_operand(rsp, dst, 4);
1079 emit_int32(imm32);
1080 }
1082 void Assembler::andl(Register dst, int32_t imm32) {
1083 prefix(dst);
1084 emit_arith(0x81, 0xE0, dst, imm32);
1085 }
1087 void Assembler::andl(Register dst, Address src) {
1088 InstructionMark im(this);
1089 prefix(src, dst);
1090 emit_int8(0x23);
1091 emit_operand(dst, src);
1092 }
1094 void Assembler::andl(Register dst, Register src) {
1095 (void) prefix_and_encode(dst->encoding(), src->encoding());
1096 emit_arith(0x23, 0xC0, dst, src);
1097 }
1099 void Assembler::bsfl(Register dst, Register src) {
1100 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1101 emit_int8(0x0F);
1102 emit_int8((unsigned char)0xBC);
1103 emit_int8((unsigned char)(0xC0 | encode));
1104 }
1106 void Assembler::bsrl(Register dst, Register src) {
1107 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBD);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1114 void Assembler::bswapl(Register reg) { // bswap
1115 int encode = prefix_and_encode(reg->encoding());
1116 emit_int8(0x0F);
1117 emit_int8((unsigned char)(0xC8 | encode));
1118 }
1120 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1121 // suspect disp32 is always good
1122 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1124 if (L.is_bound()) {
1125 const int long_size = 5;
1126 int offs = (int)( target(L) - pc() );
1127 assert(offs <= 0, "assembler error");
1128 InstructionMark im(this);
1129 // 1110 1000 #32-bit disp
1130 emit_int8((unsigned char)0xE8);
1131 emit_data(offs - long_size, rtype, operand);
1132 } else {
1133 InstructionMark im(this);
1134 // 1110 1000 #32-bit disp
1135 L.add_patch_at(code(), locator());
1137 emit_int8((unsigned char)0xE8);
1138 emit_data(int(0), rtype, operand);
1139 }
1140 }
1142 void Assembler::call(Register dst) {
1143 int encode = prefix_and_encode(dst->encoding());
1144 emit_int8((unsigned char)0xFF);
1145 emit_int8((unsigned char)(0xD0 | encode));
1146 }
1149 void Assembler::call(Address adr) {
1150 InstructionMark im(this);
1151 prefix(adr);
1152 emit_int8((unsigned char)0xFF);
1153 emit_operand(rdx, adr);
1154 }
1156 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1157 assert(entry != NULL, "call most probably wrong");
1158 InstructionMark im(this);
1159 emit_int8((unsigned char)0xE8);
1160 intptr_t disp = entry - (pc() + sizeof(int32_t));
1161 assert(is_simm32(disp), "must be 32bit offset (call2)");
1162 // Technically, should use call32_operand, but this format is
1163 // implied by the fact that we're emitting a call instruction.
1165 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1166 emit_data((int) disp, rspec, operand);
1167 }
1169 void Assembler::cdql() {
1170 emit_int8((unsigned char)0x99);
1171 }
1173 void Assembler::cld() {
1174 emit_int8((unsigned char)0xFC);
1175 }
1177 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1178 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1179 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1180 emit_int8(0x0F);
1181 emit_int8(0x40 | cc);
1182 emit_int8((unsigned char)(0xC0 | encode));
1183 }
1186 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1187 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1188 prefix(src, dst);
1189 emit_int8(0x0F);
1190 emit_int8(0x40 | cc);
1191 emit_operand(dst, src);
1192 }
1194 void Assembler::cmpb(Address dst, int imm8) {
1195 InstructionMark im(this);
1196 prefix(dst);
1197 emit_int8((unsigned char)0x80);
1198 emit_operand(rdi, dst, 1);
1199 emit_int8(imm8);
1200 }
1202 void Assembler::cmpl(Address dst, int32_t imm32) {
1203 InstructionMark im(this);
1204 prefix(dst);
1205 emit_int8((unsigned char)0x81);
1206 emit_operand(rdi, dst, 4);
1207 emit_int32(imm32);
1208 }
1210 void Assembler::cmpl(Register dst, int32_t imm32) {
1211 prefix(dst);
1212 emit_arith(0x81, 0xF8, dst, imm32);
1213 }
1215 void Assembler::cmpl(Register dst, Register src) {
1216 (void) prefix_and_encode(dst->encoding(), src->encoding());
1217 emit_arith(0x3B, 0xC0, dst, src);
1218 }
1221 void Assembler::cmpl(Register dst, Address src) {
1222 InstructionMark im(this);
1223 prefix(src, dst);
1224 emit_int8((unsigned char)0x3B);
1225 emit_operand(dst, src);
1226 }
1228 void Assembler::cmpw(Address dst, int imm16) {
1229 InstructionMark im(this);
1230 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1231 emit_int8(0x66);
1232 emit_int8((unsigned char)0x81);
1233 emit_operand(rdi, dst, 2);
1234 emit_int16(imm16);
1235 }
1237 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1238 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1239 // The ZF is set if the compared values were equal, and cleared otherwise.
1240 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1241 InstructionMark im(this);
1242 prefix(adr, reg);
1243 emit_int8(0x0F);
1244 emit_int8((unsigned char)0xB1);
1245 emit_operand(reg, adr);
1246 }
1248 void Assembler::comisd(XMMRegister dst, Address src) {
1249 // NOTE: dbx seems to decode this as comiss even though the
1250 // 0x66 is there. Strangly ucomisd comes out correct
1251 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1252 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1253 }
1255 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1257 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1258 }
1260 void Assembler::comiss(XMMRegister dst, Address src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1263 }
1265 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1266 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1267 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1268 }
1270 void Assembler::cpuid() {
1271 emit_int8(0x0F);
1272 emit_int8((unsigned char)0xA2);
1273 }
1275 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1277 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1278 }
1280 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1281 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1282 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1283 }
1285 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1287 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1288 }
1290 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1292 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1293 }
1295 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1298 emit_int8(0x2A);
1299 emit_int8((unsigned char)(0xC0 | encode));
1300 }
1302 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1303 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1304 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1305 }
1307 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1308 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1309 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1310 emit_int8(0x2A);
1311 emit_int8((unsigned char)(0xC0 | encode));
1312 }
1314 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1315 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1316 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1317 }
1319 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1321 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1322 }
1324 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1326 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1327 }
1330 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1331 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1332 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1333 emit_int8(0x2C);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1337 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1338 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1339 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1340 emit_int8(0x2C);
1341 emit_int8((unsigned char)(0xC0 | encode));
1342 }
1344 void Assembler::decl(Address dst) {
1345 // Don't use it directly. Use MacroAssembler::decrement() instead.
1346 InstructionMark im(this);
1347 prefix(dst);
1348 emit_int8((unsigned char)0xFF);
1349 emit_operand(rcx, dst);
1350 }
1352 void Assembler::divsd(XMMRegister dst, Address src) {
1353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1354 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1355 }
1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1358 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1359 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1360 }
1362 void Assembler::divss(XMMRegister dst, Address src) {
1363 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1364 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1365 }
1367 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1368 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1369 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1370 }
1372 void Assembler::emms() {
1373 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1374 emit_int8(0x0F);
1375 emit_int8(0x77);
1376 }
1378 void Assembler::hlt() {
1379 emit_int8((unsigned char)0xF4);
1380 }
1382 void Assembler::idivl(Register src) {
1383 int encode = prefix_and_encode(src->encoding());
1384 emit_int8((unsigned char)0xF7);
1385 emit_int8((unsigned char)(0xF8 | encode));
1386 }
1388 void Assembler::divl(Register src) { // Unsigned
1389 int encode = prefix_and_encode(src->encoding());
1390 emit_int8((unsigned char)0xF7);
1391 emit_int8((unsigned char)(0xF0 | encode));
1392 }
1394 void Assembler::imull(Register dst, Register src) {
1395 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1396 emit_int8(0x0F);
1397 emit_int8((unsigned char)0xAF);
1398 emit_int8((unsigned char)(0xC0 | encode));
1399 }
1402 void Assembler::imull(Register dst, Register src, int value) {
1403 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1404 if (is8bit(value)) {
1405 emit_int8(0x6B);
1406 emit_int8((unsigned char)(0xC0 | encode));
1407 emit_int8(value & 0xFF);
1408 } else {
1409 emit_int8(0x69);
1410 emit_int8((unsigned char)(0xC0 | encode));
1411 emit_int32(value);
1412 }
1413 }
1415 void Assembler::incl(Address dst) {
1416 // Don't use it directly. Use MacroAssembler::increment() instead.
1417 InstructionMark im(this);
1418 prefix(dst);
1419 emit_int8((unsigned char)0xFF);
1420 emit_operand(rax, dst);
1421 }
1423 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1424 InstructionMark im(this);
1425 assert((0 <= cc) && (cc < 16), "illegal cc");
1426 if (L.is_bound()) {
1427 address dst = target(L);
1428 assert(dst != NULL, "jcc most probably wrong");
1430 const int short_size = 2;
1431 const int long_size = 6;
1432 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1433 if (maybe_short && is8bit(offs - short_size)) {
1434 // 0111 tttn #8-bit disp
1435 emit_int8(0x70 | cc);
1436 emit_int8((offs - short_size) & 0xFF);
1437 } else {
1438 // 0000 1111 1000 tttn #32-bit disp
1439 assert(is_simm32(offs - long_size),
1440 "must be 32bit offset (call4)");
1441 emit_int8(0x0F);
1442 emit_int8((unsigned char)(0x80 | cc));
1443 emit_int32(offs - long_size);
1444 }
1445 } else {
1446 // Note: could eliminate cond. jumps to this jump if condition
1447 // is the same however, seems to be rather unlikely case.
1448 // Note: use jccb() if label to be bound is very close to get
1449 // an 8-bit displacement
1450 L.add_patch_at(code(), locator());
1451 emit_int8(0x0F);
1452 emit_int8((unsigned char)(0x80 | cc));
1453 emit_int32(0);
1454 }
1455 }
1457 void Assembler::jccb(Condition cc, Label& L) {
1458 if (L.is_bound()) {
1459 const int short_size = 2;
1460 address entry = target(L);
1461 #ifdef ASSERT
1462 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1463 intptr_t delta = short_branch_delta();
1464 if (delta != 0) {
1465 dist += (dist < 0 ? (-delta) :delta);
1466 }
1467 assert(is8bit(dist), "Dispacement too large for a short jmp");
1468 #endif
1469 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1470 // 0111 tttn #8-bit disp
1471 emit_int8(0x70 | cc);
1472 emit_int8((offs - short_size) & 0xFF);
1473 } else {
1474 InstructionMark im(this);
1475 L.add_patch_at(code(), locator());
1476 emit_int8(0x70 | cc);
1477 emit_int8(0);
1478 }
1479 }
1481 void Assembler::jmp(Address adr) {
1482 InstructionMark im(this);
1483 prefix(adr);
1484 emit_int8((unsigned char)0xFF);
1485 emit_operand(rsp, adr);
1486 }
1488 void Assembler::jmp(Label& L, bool maybe_short) {
1489 if (L.is_bound()) {
1490 address entry = target(L);
1491 assert(entry != NULL, "jmp most probably wrong");
1492 InstructionMark im(this);
1493 const int short_size = 2;
1494 const int long_size = 5;
1495 intptr_t offs = entry - pc();
1496 if (maybe_short && is8bit(offs - short_size)) {
1497 emit_int8((unsigned char)0xEB);
1498 emit_int8((offs - short_size) & 0xFF);
1499 } else {
1500 emit_int8((unsigned char)0xE9);
1501 emit_int32(offs - long_size);
1502 }
1503 } else {
1504 // By default, forward jumps are always 32-bit displacements, since
1505 // we can't yet know where the label will be bound. If you're sure that
1506 // the forward jump will not run beyond 256 bytes, use jmpb to
1507 // force an 8-bit displacement.
1508 InstructionMark im(this);
1509 L.add_patch_at(code(), locator());
1510 emit_int8((unsigned char)0xE9);
1511 emit_int32(0);
1512 }
1513 }
1515 void Assembler::jmp(Register entry) {
1516 int encode = prefix_and_encode(entry->encoding());
1517 emit_int8((unsigned char)0xFF);
1518 emit_int8((unsigned char)(0xE0 | encode));
1519 }
1521 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1522 InstructionMark im(this);
1523 emit_int8((unsigned char)0xE9);
1524 assert(dest != NULL, "must have a target");
1525 intptr_t disp = dest - (pc() + sizeof(int32_t));
1526 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1527 emit_data(disp, rspec.reloc(), call32_operand);
1528 }
1530 void Assembler::jmpb(Label& L) {
1531 if (L.is_bound()) {
1532 const int short_size = 2;
1533 address entry = target(L);
1534 assert(entry != NULL, "jmp most probably wrong");
1535 #ifdef ASSERT
1536 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1537 intptr_t delta = short_branch_delta();
1538 if (delta != 0) {
1539 dist += (dist < 0 ? (-delta) :delta);
1540 }
1541 assert(is8bit(dist), "Dispacement too large for a short jmp");
1542 #endif
1543 intptr_t offs = entry - pc();
1544 emit_int8((unsigned char)0xEB);
1545 emit_int8((offs - short_size) & 0xFF);
1546 } else {
1547 InstructionMark im(this);
1548 L.add_patch_at(code(), locator());
1549 emit_int8((unsigned char)0xEB);
1550 emit_int8(0);
1551 }
1552 }
1554 void Assembler::ldmxcsr( Address src) {
1555 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1556 InstructionMark im(this);
1557 prefix(src);
1558 emit_int8(0x0F);
1559 emit_int8((unsigned char)0xAE);
1560 emit_operand(as_Register(2), src);
1561 }
1563 void Assembler::leal(Register dst, Address src) {
1564 InstructionMark im(this);
1565 #ifdef _LP64
1566 emit_int8(0x67); // addr32
1567 prefix(src, dst);
1568 #endif // LP64
1569 emit_int8((unsigned char)0x8D);
1570 emit_operand(dst, src);
1571 }
1573 void Assembler::lfence() {
1574 emit_int8(0x0F);
1575 emit_int8((unsigned char)0xAE);
1576 emit_int8((unsigned char)0xE8);
1577 }
1579 void Assembler::lock() {
1580 emit_int8((unsigned char)0xF0);
1581 }
1583 void Assembler::lzcntl(Register dst, Register src) {
1584 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1585 emit_int8((unsigned char)0xF3);
1586 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1587 emit_int8(0x0F);
1588 emit_int8((unsigned char)0xBD);
1589 emit_int8((unsigned char)(0xC0 | encode));
1590 }
1592 // Emit mfence instruction
1593 void Assembler::mfence() {
1594 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1595 emit_int8(0x0F);
1596 emit_int8((unsigned char)0xAE);
1597 emit_int8((unsigned char)0xF0);
1598 }
1600 void Assembler::mov(Register dst, Register src) {
1601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1602 }
1604 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1607 }
1609 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1610 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1611 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1612 }
1614 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1615 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1616 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1617 emit_int8(0x16);
1618 emit_int8((unsigned char)(0xC0 | encode));
1619 }
1621 void Assembler::movb(Register dst, Address src) {
1622 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1623 InstructionMark im(this);
1624 prefix(src, dst, true);
1625 emit_int8((unsigned char)0x8A);
1626 emit_operand(dst, src);
1627 }
1630 void Assembler::movb(Address dst, int imm8) {
1631 InstructionMark im(this);
1632 prefix(dst);
1633 emit_int8((unsigned char)0xC6);
1634 emit_operand(rax, dst, 1);
1635 emit_int8(imm8);
1636 }
1639 void Assembler::movb(Address dst, Register src) {
1640 assert(src->has_byte_register(), "must have byte register");
1641 InstructionMark im(this);
1642 prefix(dst, src, true);
1643 emit_int8((unsigned char)0x88);
1644 emit_operand(src, dst);
1645 }
1647 void Assembler::movdl(XMMRegister dst, Register src) {
1648 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1649 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1650 emit_int8(0x6E);
1651 emit_int8((unsigned char)(0xC0 | encode));
1652 }
1654 void Assembler::movdl(Register dst, XMMRegister src) {
1655 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1656 // swap src/dst to get correct prefix
1657 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1658 emit_int8(0x7E);
1659 emit_int8((unsigned char)(0xC0 | encode));
1660 }
1662 void Assembler::movdl(XMMRegister dst, Address src) {
1663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1664 InstructionMark im(this);
1665 simd_prefix(dst, src, VEX_SIMD_66);
1666 emit_int8(0x6E);
1667 emit_operand(dst, src);
1668 }
1670 void Assembler::movdl(Address dst, XMMRegister src) {
1671 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1672 InstructionMark im(this);
1673 simd_prefix(dst, src, VEX_SIMD_66);
1674 emit_int8(0x7E);
1675 emit_operand(src, dst);
1676 }
1678 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1679 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1680 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1681 }
1683 void Assembler::movdqu(XMMRegister dst, Address src) {
1684 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1685 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1686 }
1688 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1689 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1690 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1691 }
1693 void Assembler::movdqu(Address dst, XMMRegister src) {
1694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1695 InstructionMark im(this);
1696 simd_prefix(dst, src, VEX_SIMD_F3);
1697 emit_int8(0x7F);
1698 emit_operand(src, dst);
1699 }
1701 // Move Unaligned 256bit Vector
1702 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1703 assert(UseAVX, "");
1704 bool vector256 = true;
1705 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1706 emit_int8(0x6F);
1707 emit_int8((unsigned char)(0xC0 | encode));
1708 }
1710 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1711 assert(UseAVX, "");
1712 InstructionMark im(this);
1713 bool vector256 = true;
1714 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1715 emit_int8(0x6F);
1716 emit_operand(dst, src);
1717 }
1719 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1720 assert(UseAVX, "");
1721 InstructionMark im(this);
1722 bool vector256 = true;
1723 // swap src<->dst for encoding
1724 assert(src != xnoreg, "sanity");
1725 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1726 emit_int8(0x7F);
1727 emit_operand(src, dst);
1728 }
1730 // Uses zero extension on 64bit
1732 void Assembler::movl(Register dst, int32_t imm32) {
1733 int encode = prefix_and_encode(dst->encoding());
1734 emit_int8((unsigned char)(0xB8 | encode));
1735 emit_int32(imm32);
1736 }
1738 void Assembler::movl(Register dst, Register src) {
1739 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1740 emit_int8((unsigned char)0x8B);
1741 emit_int8((unsigned char)(0xC0 | encode));
1742 }
1744 void Assembler::movl(Register dst, Address src) {
1745 InstructionMark im(this);
1746 prefix(src, dst);
1747 emit_int8((unsigned char)0x8B);
1748 emit_operand(dst, src);
1749 }
1751 void Assembler::movl(Address dst, int32_t imm32) {
1752 InstructionMark im(this);
1753 prefix(dst);
1754 emit_int8((unsigned char)0xC7);
1755 emit_operand(rax, dst, 4);
1756 emit_int32(imm32);
1757 }
1759 void Assembler::movl(Address dst, Register src) {
1760 InstructionMark im(this);
1761 prefix(dst, src);
1762 emit_int8((unsigned char)0x89);
1763 emit_operand(src, dst);
1764 }
1766 // New cpus require to use movsd and movss to avoid partial register stall
1767 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1768 // The selection is done in MacroAssembler::movdbl() and movflt().
1769 void Assembler::movlpd(XMMRegister dst, Address src) {
1770 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1771 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1772 }
1774 void Assembler::movq( MMXRegister dst, Address src ) {
1775 assert( VM_Version::supports_mmx(), "" );
1776 emit_int8(0x0F);
1777 emit_int8(0x6F);
1778 emit_operand(dst, src);
1779 }
1781 void Assembler::movq( Address dst, MMXRegister src ) {
1782 assert( VM_Version::supports_mmx(), "" );
1783 emit_int8(0x0F);
1784 emit_int8(0x7F);
1785 // workaround gcc (3.2.1-7a) bug
1786 // In that version of gcc with only an emit_operand(MMX, Address)
1787 // gcc will tail jump and try and reverse the parameters completely
1788 // obliterating dst in the process. By having a version available
1789 // that doesn't need to swap the args at the tail jump the bug is
1790 // avoided.
1791 emit_operand(dst, src);
1792 }
1794 void Assembler::movq(XMMRegister dst, Address src) {
1795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1796 InstructionMark im(this);
1797 simd_prefix(dst, src, VEX_SIMD_F3);
1798 emit_int8(0x7E);
1799 emit_operand(dst, src);
1800 }
1802 void Assembler::movq(Address dst, XMMRegister src) {
1803 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1804 InstructionMark im(this);
1805 simd_prefix(dst, src, VEX_SIMD_66);
1806 emit_int8((unsigned char)0xD6);
1807 emit_operand(src, dst);
1808 }
1810 void Assembler::movsbl(Register dst, Address src) { // movsxb
1811 InstructionMark im(this);
1812 prefix(src, dst);
1813 emit_int8(0x0F);
1814 emit_int8((unsigned char)0xBE);
1815 emit_operand(dst, src);
1816 }
1818 void Assembler::movsbl(Register dst, Register src) { // movsxb
1819 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1820 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1821 emit_int8(0x0F);
1822 emit_int8((unsigned char)0xBE);
1823 emit_int8((unsigned char)(0xC0 | encode));
1824 }
1826 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1828 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1829 }
1831 void Assembler::movsd(XMMRegister dst, Address src) {
1832 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1833 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1834 }
1836 void Assembler::movsd(Address dst, XMMRegister src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 InstructionMark im(this);
1839 simd_prefix(dst, src, VEX_SIMD_F2);
1840 emit_int8(0x11);
1841 emit_operand(src, dst);
1842 }
1844 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1845 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1846 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1847 }
1849 void Assembler::movss(XMMRegister dst, Address src) {
1850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1851 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1852 }
1854 void Assembler::movss(Address dst, XMMRegister src) {
1855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1856 InstructionMark im(this);
1857 simd_prefix(dst, src, VEX_SIMD_F3);
1858 emit_int8(0x11);
1859 emit_operand(src, dst);
1860 }
1862 void Assembler::movswl(Register dst, Address src) { // movsxw
1863 InstructionMark im(this);
1864 prefix(src, dst);
1865 emit_int8(0x0F);
1866 emit_int8((unsigned char)0xBF);
1867 emit_operand(dst, src);
1868 }
1870 void Assembler::movswl(Register dst, Register src) { // movsxw
1871 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1872 emit_int8(0x0F);
1873 emit_int8((unsigned char)0xBF);
1874 emit_int8((unsigned char)(0xC0 | encode));
1875 }
1877 void Assembler::movw(Address dst, int imm16) {
1878 InstructionMark im(this);
1880 emit_int8(0x66); // switch to 16-bit mode
1881 prefix(dst);
1882 emit_int8((unsigned char)0xC7);
1883 emit_operand(rax, dst, 2);
1884 emit_int16(imm16);
1885 }
1887 void Assembler::movw(Register dst, Address src) {
1888 InstructionMark im(this);
1889 emit_int8(0x66);
1890 prefix(src, dst);
1891 emit_int8((unsigned char)0x8B);
1892 emit_operand(dst, src);
1893 }
1895 void Assembler::movw(Address dst, Register src) {
1896 InstructionMark im(this);
1897 emit_int8(0x66);
1898 prefix(dst, src);
1899 emit_int8((unsigned char)0x89);
1900 emit_operand(src, dst);
1901 }
1903 void Assembler::movzbl(Register dst, Address src) { // movzxb
1904 InstructionMark im(this);
1905 prefix(src, dst);
1906 emit_int8(0x0F);
1907 emit_int8((unsigned char)0xB6);
1908 emit_operand(dst, src);
1909 }
1911 void Assembler::movzbl(Register dst, Register src) { // movzxb
1912 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1913 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1914 emit_int8(0x0F);
1915 emit_int8((unsigned char)0xB6);
1916 emit_int8(0xC0 | encode);
1917 }
1919 void Assembler::movzwl(Register dst, Address src) { // movzxw
1920 InstructionMark im(this);
1921 prefix(src, dst);
1922 emit_int8(0x0F);
1923 emit_int8((unsigned char)0xB7);
1924 emit_operand(dst, src);
1925 }
1927 void Assembler::movzwl(Register dst, Register src) { // movzxw
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1929 emit_int8(0x0F);
1930 emit_int8((unsigned char)0xB7);
1931 emit_int8(0xC0 | encode);
1932 }
1934 void Assembler::mull(Address src) {
1935 InstructionMark im(this);
1936 prefix(src);
1937 emit_int8((unsigned char)0xF7);
1938 emit_operand(rsp, src);
1939 }
1941 void Assembler::mull(Register src) {
1942 int encode = prefix_and_encode(src->encoding());
1943 emit_int8((unsigned char)0xF7);
1944 emit_int8((unsigned char)(0xE0 | encode));
1945 }
1947 void Assembler::mulsd(XMMRegister dst, Address src) {
1948 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1949 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1950 }
1952 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1953 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1954 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1955 }
1957 void Assembler::mulss(XMMRegister dst, Address src) {
1958 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1959 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1960 }
1962 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1963 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1964 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1965 }
1967 void Assembler::negl(Register dst) {
1968 int encode = prefix_and_encode(dst->encoding());
1969 emit_int8((unsigned char)0xF7);
1970 emit_int8((unsigned char)(0xD8 | encode));
1971 }
1973 void Assembler::nop(int i) {
1974 #ifdef ASSERT
1975 assert(i > 0, " ");
1976 // The fancy nops aren't currently recognized by debuggers making it a
1977 // pain to disassemble code while debugging. If asserts are on clearly
1978 // speed is not an issue so simply use the single byte traditional nop
1979 // to do alignment.
1981 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
1982 return;
1984 #endif // ASSERT
1986 if (UseAddressNop && VM_Version::is_intel()) {
1987 //
1988 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1989 // 1: 0x90
1990 // 2: 0x66 0x90
1991 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1992 // 4: 0x0F 0x1F 0x40 0x00
1993 // 5: 0x0F 0x1F 0x44 0x00 0x00
1994 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1995 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1996 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1997 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1998 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1999 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2001 // The rest coding is Intel specific - don't use consecutive address nops
2003 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2004 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2005 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2006 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2008 while(i >= 15) {
2009 // For Intel don't generate consecutive addess nops (mix with regular nops)
2010 i -= 15;
2011 emit_int8(0x66); // size prefix
2012 emit_int8(0x66); // size prefix
2013 emit_int8(0x66); // size prefix
2014 addr_nop_8();
2015 emit_int8(0x66); // size prefix
2016 emit_int8(0x66); // size prefix
2017 emit_int8(0x66); // size prefix
2018 emit_int8((unsigned char)0x90);
2019 // nop
2020 }
2021 switch (i) {
2022 case 14:
2023 emit_int8(0x66); // size prefix
2024 case 13:
2025 emit_int8(0x66); // size prefix
2026 case 12:
2027 addr_nop_8();
2028 emit_int8(0x66); // size prefix
2029 emit_int8(0x66); // size prefix
2030 emit_int8(0x66); // size prefix
2031 emit_int8((unsigned char)0x90);
2032 // nop
2033 break;
2034 case 11:
2035 emit_int8(0x66); // size prefix
2036 case 10:
2037 emit_int8(0x66); // size prefix
2038 case 9:
2039 emit_int8(0x66); // size prefix
2040 case 8:
2041 addr_nop_8();
2042 break;
2043 case 7:
2044 addr_nop_7();
2045 break;
2046 case 6:
2047 emit_int8(0x66); // size prefix
2048 case 5:
2049 addr_nop_5();
2050 break;
2051 case 4:
2052 addr_nop_4();
2053 break;
2054 case 3:
2055 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2056 emit_int8(0x66); // size prefix
2057 case 2:
2058 emit_int8(0x66); // size prefix
2059 case 1:
2060 emit_int8((unsigned char)0x90);
2061 // nop
2062 break;
2063 default:
2064 assert(i == 0, " ");
2065 }
2066 return;
2067 }
2068 if (UseAddressNop && VM_Version::is_amd()) {
2069 //
2070 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2071 // 1: 0x90
2072 // 2: 0x66 0x90
2073 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2074 // 4: 0x0F 0x1F 0x40 0x00
2075 // 5: 0x0F 0x1F 0x44 0x00 0x00
2076 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2077 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2078 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2079 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2080 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2081 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2083 // The rest coding is AMD specific - use consecutive address nops
2085 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2086 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2087 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2088 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2089 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2090 // Size prefixes (0x66) are added for larger sizes
2092 while(i >= 22) {
2093 i -= 11;
2094 emit_int8(0x66); // size prefix
2095 emit_int8(0x66); // size prefix
2096 emit_int8(0x66); // size prefix
2097 addr_nop_8();
2098 }
2099 // Generate first nop for size between 21-12
2100 switch (i) {
2101 case 21:
2102 i -= 1;
2103 emit_int8(0x66); // size prefix
2104 case 20:
2105 case 19:
2106 i -= 1;
2107 emit_int8(0x66); // size prefix
2108 case 18:
2109 case 17:
2110 i -= 1;
2111 emit_int8(0x66); // size prefix
2112 case 16:
2113 case 15:
2114 i -= 8;
2115 addr_nop_8();
2116 break;
2117 case 14:
2118 case 13:
2119 i -= 7;
2120 addr_nop_7();
2121 break;
2122 case 12:
2123 i -= 6;
2124 emit_int8(0x66); // size prefix
2125 addr_nop_5();
2126 break;
2127 default:
2128 assert(i < 12, " ");
2129 }
2131 // Generate second nop for size between 11-1
2132 switch (i) {
2133 case 11:
2134 emit_int8(0x66); // size prefix
2135 case 10:
2136 emit_int8(0x66); // size prefix
2137 case 9:
2138 emit_int8(0x66); // size prefix
2139 case 8:
2140 addr_nop_8();
2141 break;
2142 case 7:
2143 addr_nop_7();
2144 break;
2145 case 6:
2146 emit_int8(0x66); // size prefix
2147 case 5:
2148 addr_nop_5();
2149 break;
2150 case 4:
2151 addr_nop_4();
2152 break;
2153 case 3:
2154 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2155 emit_int8(0x66); // size prefix
2156 case 2:
2157 emit_int8(0x66); // size prefix
2158 case 1:
2159 emit_int8((unsigned char)0x90);
2160 // nop
2161 break;
2162 default:
2163 assert(i == 0, " ");
2164 }
2165 return;
2166 }
2168 // Using nops with size prefixes "0x66 0x90".
2169 // From AMD Optimization Guide:
2170 // 1: 0x90
2171 // 2: 0x66 0x90
2172 // 3: 0x66 0x66 0x90
2173 // 4: 0x66 0x66 0x66 0x90
2174 // 5: 0x66 0x66 0x90 0x66 0x90
2175 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2176 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2177 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2178 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2179 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2180 //
2181 while(i > 12) {
2182 i -= 4;
2183 emit_int8(0x66); // size prefix
2184 emit_int8(0x66);
2185 emit_int8(0x66);
2186 emit_int8((unsigned char)0x90);
2187 // nop
2188 }
2189 // 1 - 12 nops
2190 if(i > 8) {
2191 if(i > 9) {
2192 i -= 1;
2193 emit_int8(0x66);
2194 }
2195 i -= 3;
2196 emit_int8(0x66);
2197 emit_int8(0x66);
2198 emit_int8((unsigned char)0x90);
2199 }
2200 // 1 - 8 nops
2201 if(i > 4) {
2202 if(i > 6) {
2203 i -= 1;
2204 emit_int8(0x66);
2205 }
2206 i -= 3;
2207 emit_int8(0x66);
2208 emit_int8(0x66);
2209 emit_int8((unsigned char)0x90);
2210 }
2211 switch (i) {
2212 case 4:
2213 emit_int8(0x66);
2214 case 3:
2215 emit_int8(0x66);
2216 case 2:
2217 emit_int8(0x66);
2218 case 1:
2219 emit_int8((unsigned char)0x90);
2220 break;
2221 default:
2222 assert(i == 0, " ");
2223 }
2224 }
2226 void Assembler::notl(Register dst) {
2227 int encode = prefix_and_encode(dst->encoding());
2228 emit_int8((unsigned char)0xF7);
2229 emit_int8((unsigned char)(0xD0 | encode));
2230 }
2232 void Assembler::orl(Address dst, int32_t imm32) {
2233 InstructionMark im(this);
2234 prefix(dst);
2235 emit_arith_operand(0x81, rcx, dst, imm32);
2236 }
2238 void Assembler::orl(Register dst, int32_t imm32) {
2239 prefix(dst);
2240 emit_arith(0x81, 0xC8, dst, imm32);
2241 }
2243 void Assembler::orl(Register dst, Address src) {
2244 InstructionMark im(this);
2245 prefix(src, dst);
2246 emit_int8(0x0B);
2247 emit_operand(dst, src);
2248 }
2250 void Assembler::orl(Register dst, Register src) {
2251 (void) prefix_and_encode(dst->encoding(), src->encoding());
2252 emit_arith(0x0B, 0xC0, dst, src);
2253 }
2255 void Assembler::packuswb(XMMRegister dst, Address src) {
2256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2257 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2258 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2259 }
2261 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2263 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2264 }
2266 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2267 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2268 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2269 }
2271 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2272 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2273 emit_int8(0x00);
2274 emit_int8(0xC0 | encode);
2275 emit_int8(imm8);
2276 }
2278 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2279 assert(VM_Version::supports_sse4_2(), "");
2280 InstructionMark im(this);
2281 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2282 emit_int8(0x61);
2283 emit_operand(dst, src);
2284 emit_int8(imm8);
2285 }
2287 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2288 assert(VM_Version::supports_sse4_2(), "");
2289 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2290 emit_int8(0x61);
2291 emit_int8((unsigned char)(0xC0 | encode));
2292 emit_int8(imm8);
2293 }
2295 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2296 assert(VM_Version::supports_sse4_1(), "");
2297 InstructionMark im(this);
2298 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2299 emit_int8(0x30);
2300 emit_operand(dst, src);
2301 }
2303 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2304 assert(VM_Version::supports_sse4_1(), "");
2305 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2306 emit_int8(0x30);
2307 emit_int8((unsigned char)(0xC0 | encode));
2308 }
2310 // generic
2311 void Assembler::pop(Register dst) {
2312 int encode = prefix_and_encode(dst->encoding());
2313 emit_int8(0x58 | encode);
2314 }
2316 void Assembler::popcntl(Register dst, Address src) {
2317 assert(VM_Version::supports_popcnt(), "must support");
2318 InstructionMark im(this);
2319 emit_int8((unsigned char)0xF3);
2320 prefix(src, dst);
2321 emit_int8(0x0F);
2322 emit_int8((unsigned char)0xB8);
2323 emit_operand(dst, src);
2324 }
2326 void Assembler::popcntl(Register dst, Register src) {
2327 assert(VM_Version::supports_popcnt(), "must support");
2328 emit_int8((unsigned char)0xF3);
2329 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2330 emit_int8(0x0F);
2331 emit_int8((unsigned char)0xB8);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2335 void Assembler::popf() {
2336 emit_int8((unsigned char)0x9D);
2337 }
2339 #ifndef _LP64 // no 32bit push/pop on amd64
2340 void Assembler::popl(Address dst) {
2341 // NOTE: this will adjust stack by 8byte on 64bits
2342 InstructionMark im(this);
2343 prefix(dst);
2344 emit_int8((unsigned char)0x8F);
2345 emit_operand(rax, dst);
2346 }
2347 #endif
2349 void Assembler::prefetch_prefix(Address src) {
2350 prefix(src);
2351 emit_int8(0x0F);
2352 }
2354 void Assembler::prefetchnta(Address src) {
2355 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2356 InstructionMark im(this);
2357 prefetch_prefix(src);
2358 emit_int8(0x18);
2359 emit_operand(rax, src); // 0, src
2360 }
2362 void Assembler::prefetchr(Address src) {
2363 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2364 InstructionMark im(this);
2365 prefetch_prefix(src);
2366 emit_int8(0x0D);
2367 emit_operand(rax, src); // 0, src
2368 }
2370 void Assembler::prefetcht0(Address src) {
2371 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2372 InstructionMark im(this);
2373 prefetch_prefix(src);
2374 emit_int8(0x18);
2375 emit_operand(rcx, src); // 1, src
2376 }
2378 void Assembler::prefetcht1(Address src) {
2379 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2380 InstructionMark im(this);
2381 prefetch_prefix(src);
2382 emit_int8(0x18);
2383 emit_operand(rdx, src); // 2, src
2384 }
2386 void Assembler::prefetcht2(Address src) {
2387 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2388 InstructionMark im(this);
2389 prefetch_prefix(src);
2390 emit_int8(0x18);
2391 emit_operand(rbx, src); // 3, src
2392 }
2394 void Assembler::prefetchw(Address src) {
2395 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2396 InstructionMark im(this);
2397 prefetch_prefix(src);
2398 emit_int8(0x0D);
2399 emit_operand(rcx, src); // 1, src
2400 }
2402 void Assembler::prefix(Prefix p) {
2403 emit_int8(p);
2404 }
2406 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2407 assert(VM_Version::supports_ssse3(), "");
2408 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2409 emit_int8(0x00);
2410 emit_int8((unsigned char)(0xC0 | encode));
2411 }
2413 void Assembler::pshufb(XMMRegister dst, Address src) {
2414 assert(VM_Version::supports_ssse3(), "");
2415 InstructionMark im(this);
2416 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2417 emit_int8(0x00);
2418 emit_operand(dst, src);
2419 }
2421 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2422 assert(isByte(mode), "invalid value");
2423 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2424 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2425 emit_int8(mode & 0xFF);
2427 }
2429 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2430 assert(isByte(mode), "invalid value");
2431 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2432 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2433 InstructionMark im(this);
2434 simd_prefix(dst, src, VEX_SIMD_66);
2435 emit_int8(0x70);
2436 emit_operand(dst, src);
2437 emit_int8(mode & 0xFF);
2438 }
2440 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2441 assert(isByte(mode), "invalid value");
2442 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2443 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2444 emit_int8(mode & 0xFF);
2445 }
2447 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2448 assert(isByte(mode), "invalid value");
2449 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2450 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2451 InstructionMark im(this);
2452 simd_prefix(dst, src, VEX_SIMD_F2);
2453 emit_int8(0x70);
2454 emit_operand(dst, src);
2455 emit_int8(mode & 0xFF);
2456 }
2458 void Assembler::psrldq(XMMRegister dst, int shift) {
2459 // Shift 128 bit value in xmm register by number of bytes.
2460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2461 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2462 emit_int8(0x73);
2463 emit_int8((unsigned char)(0xC0 | encode));
2464 emit_int8(shift);
2465 }
2467 void Assembler::ptest(XMMRegister dst, Address src) {
2468 assert(VM_Version::supports_sse4_1(), "");
2469 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2470 InstructionMark im(this);
2471 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2472 emit_int8(0x17);
2473 emit_operand(dst, src);
2474 }
2476 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2477 assert(VM_Version::supports_sse4_1(), "");
2478 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2479 emit_int8(0x17);
2480 emit_int8((unsigned char)(0xC0 | encode));
2481 }
2483 void Assembler::vptest(XMMRegister dst, Address src) {
2484 assert(VM_Version::supports_avx(), "");
2485 InstructionMark im(this);
2486 bool vector256 = true;
2487 assert(dst != xnoreg, "sanity");
2488 int dst_enc = dst->encoding();
2489 // swap src<->dst for encoding
2490 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2491 emit_int8(0x17);
2492 emit_operand(dst, src);
2493 }
2495 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2496 assert(VM_Version::supports_avx(), "");
2497 bool vector256 = true;
2498 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2499 emit_int8(0x17);
2500 emit_int8((unsigned char)(0xC0 | encode));
2501 }
2503 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2504 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2505 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2506 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2507 }
2509 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2510 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2511 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2512 }
2514 void Assembler::punpckldq(XMMRegister dst, Address src) {
2515 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2516 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2517 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2518 }
2520 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2521 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2522 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2523 }
2525 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2526 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2527 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2528 }
2530 void Assembler::push(int32_t imm32) {
2531 // in 64bits we push 64bits onto the stack but only
2532 // take a 32bit immediate
2533 emit_int8(0x68);
2534 emit_int32(imm32);
2535 }
2537 void Assembler::push(Register src) {
2538 int encode = prefix_and_encode(src->encoding());
2540 emit_int8(0x50 | encode);
2541 }
2543 void Assembler::pushf() {
2544 emit_int8((unsigned char)0x9C);
2545 }
2547 #ifndef _LP64 // no 32bit push/pop on amd64
2548 void Assembler::pushl(Address src) {
2549 // Note this will push 64bit on 64bit
2550 InstructionMark im(this);
2551 prefix(src);
2552 emit_int8((unsigned char)0xFF);
2553 emit_operand(rsi, src);
2554 }
2555 #endif
2557 void Assembler::rcll(Register dst, int imm8) {
2558 assert(isShiftCount(imm8), "illegal shift count");
2559 int encode = prefix_and_encode(dst->encoding());
2560 if (imm8 == 1) {
2561 emit_int8((unsigned char)0xD1);
2562 emit_int8((unsigned char)(0xD0 | encode));
2563 } else {
2564 emit_int8((unsigned char)0xC1);
2565 emit_int8((unsigned char)0xD0 | encode);
2566 emit_int8(imm8);
2567 }
2568 }
2570 // copies data from [esi] to [edi] using rcx pointer sized words
2571 // generic
2572 void Assembler::rep_mov() {
2573 emit_int8((unsigned char)0xF3);
2574 // MOVSQ
2575 LP64_ONLY(prefix(REX_W));
2576 emit_int8((unsigned char)0xA5);
2577 }
2579 // sets rcx bytes with rax, value at [edi]
2580 void Assembler::rep_stosb() {
2581 emit_int8((unsigned char)0xF3); // REP
2582 LP64_ONLY(prefix(REX_W));
2583 emit_int8((unsigned char)0xAA); // STOSB
2584 }
2586 // sets rcx pointer sized words with rax, value at [edi]
2587 // generic
2588 void Assembler::rep_stos() {
2589 emit_int8((unsigned char)0xF3); // REP
2590 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2591 emit_int8((unsigned char)0xAB);
2592 }
2594 // scans rcx pointer sized words at [edi] for occurance of rax,
2595 // generic
2596 void Assembler::repne_scan() { // repne_scan
2597 emit_int8((unsigned char)0xF2);
2598 // SCASQ
2599 LP64_ONLY(prefix(REX_W));
2600 emit_int8((unsigned char)0xAF);
2601 }
2603 #ifdef _LP64
2604 // scans rcx 4 byte words at [edi] for occurance of rax,
2605 // generic
2606 void Assembler::repne_scanl() { // repne_scan
2607 emit_int8((unsigned char)0xF2);
2608 // SCASL
2609 emit_int8((unsigned char)0xAF);
2610 }
2611 #endif
2613 void Assembler::ret(int imm16) {
2614 if (imm16 == 0) {
2615 emit_int8((unsigned char)0xC3);
2616 } else {
2617 emit_int8((unsigned char)0xC2);
2618 emit_int16(imm16);
2619 }
2620 }
2622 void Assembler::sahf() {
2623 #ifdef _LP64
2624 // Not supported in 64bit mode
2625 ShouldNotReachHere();
2626 #endif
2627 emit_int8((unsigned char)0x9E);
2628 }
2630 void Assembler::sarl(Register dst, int imm8) {
2631 int encode = prefix_and_encode(dst->encoding());
2632 assert(isShiftCount(imm8), "illegal shift count");
2633 if (imm8 == 1) {
2634 emit_int8((unsigned char)0xD1);
2635 emit_int8((unsigned char)(0xF8 | encode));
2636 } else {
2637 emit_int8((unsigned char)0xC1);
2638 emit_int8((unsigned char)(0xF8 | encode));
2639 emit_int8(imm8);
2640 }
2641 }
2643 void Assembler::sarl(Register dst) {
2644 int encode = prefix_and_encode(dst->encoding());
2645 emit_int8((unsigned char)0xD3);
2646 emit_int8((unsigned char)(0xF8 | encode));
2647 }
2649 void Assembler::sbbl(Address dst, int32_t imm32) {
2650 InstructionMark im(this);
2651 prefix(dst);
2652 emit_arith_operand(0x81, rbx, dst, imm32);
2653 }
2655 void Assembler::sbbl(Register dst, int32_t imm32) {
2656 prefix(dst);
2657 emit_arith(0x81, 0xD8, dst, imm32);
2658 }
2661 void Assembler::sbbl(Register dst, Address src) {
2662 InstructionMark im(this);
2663 prefix(src, dst);
2664 emit_int8(0x1B);
2665 emit_operand(dst, src);
2666 }
2668 void Assembler::sbbl(Register dst, Register src) {
2669 (void) prefix_and_encode(dst->encoding(), src->encoding());
2670 emit_arith(0x1B, 0xC0, dst, src);
2671 }
2673 void Assembler::setb(Condition cc, Register dst) {
2674 assert(0 <= cc && cc < 16, "illegal cc");
2675 int encode = prefix_and_encode(dst->encoding(), true);
2676 emit_int8(0x0F);
2677 emit_int8((unsigned char)0x90 | cc);
2678 emit_int8((unsigned char)(0xC0 | encode));
2679 }
2681 void Assembler::shll(Register dst, int imm8) {
2682 assert(isShiftCount(imm8), "illegal shift count");
2683 int encode = prefix_and_encode(dst->encoding());
2684 if (imm8 == 1 ) {
2685 emit_int8((unsigned char)0xD1);
2686 emit_int8((unsigned char)(0xE0 | encode));
2687 } else {
2688 emit_int8((unsigned char)0xC1);
2689 emit_int8((unsigned char)(0xE0 | encode));
2690 emit_int8(imm8);
2691 }
2692 }
2694 void Assembler::shll(Register dst) {
2695 int encode = prefix_and_encode(dst->encoding());
2696 emit_int8((unsigned char)0xD3);
2697 emit_int8((unsigned char)(0xE0 | encode));
2698 }
2700 void Assembler::shrl(Register dst, int imm8) {
2701 assert(isShiftCount(imm8), "illegal shift count");
2702 int encode = prefix_and_encode(dst->encoding());
2703 emit_int8((unsigned char)0xC1);
2704 emit_int8((unsigned char)(0xE8 | encode));
2705 emit_int8(imm8);
2706 }
2708 void Assembler::shrl(Register dst) {
2709 int encode = prefix_and_encode(dst->encoding());
2710 emit_int8((unsigned char)0xD3);
2711 emit_int8((unsigned char)(0xE8 | encode));
2712 }
2714 // copies a single word from [esi] to [edi]
2715 void Assembler::smovl() {
2716 emit_int8((unsigned char)0xA5);
2717 }
2719 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2721 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2722 }
2724 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2726 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2727 }
2729 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2730 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2731 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2732 }
2734 void Assembler::std() {
2735 emit_int8((unsigned char)0xFD);
2736 }
2738 void Assembler::sqrtss(XMMRegister dst, Address src) {
2739 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2740 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2741 }
2743 void Assembler::stmxcsr( Address dst) {
2744 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2745 InstructionMark im(this);
2746 prefix(dst);
2747 emit_int8(0x0F);
2748 emit_int8((unsigned char)0xAE);
2749 emit_operand(as_Register(3), dst);
2750 }
2752 void Assembler::subl(Address dst, int32_t imm32) {
2753 InstructionMark im(this);
2754 prefix(dst);
2755 emit_arith_operand(0x81, rbp, dst, imm32);
2756 }
2758 void Assembler::subl(Address dst, Register src) {
2759 InstructionMark im(this);
2760 prefix(dst, src);
2761 emit_int8(0x29);
2762 emit_operand(src, dst);
2763 }
2765 void Assembler::subl(Register dst, int32_t imm32) {
2766 prefix(dst);
2767 emit_arith(0x81, 0xE8, dst, imm32);
2768 }
2770 // Force generation of a 4 byte immediate value even if it fits into 8bit
2771 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2772 prefix(dst);
2773 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2774 }
2776 void Assembler::subl(Register dst, Address src) {
2777 InstructionMark im(this);
2778 prefix(src, dst);
2779 emit_int8(0x2B);
2780 emit_operand(dst, src);
2781 }
2783 void Assembler::subl(Register dst, Register src) {
2784 (void) prefix_and_encode(dst->encoding(), src->encoding());
2785 emit_arith(0x2B, 0xC0, dst, src);
2786 }
2788 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2789 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2790 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2791 }
2793 void Assembler::subsd(XMMRegister dst, Address src) {
2794 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2795 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2796 }
2798 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2799 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2800 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2801 }
2803 void Assembler::subss(XMMRegister dst, Address src) {
2804 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2805 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2806 }
2808 void Assembler::testb(Register dst, int imm8) {
2809 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2810 (void) prefix_and_encode(dst->encoding(), true);
2811 emit_arith_b(0xF6, 0xC0, dst, imm8);
2812 }
2814 void Assembler::testl(Register dst, int32_t imm32) {
2815 // not using emit_arith because test
2816 // doesn't support sign-extension of
2817 // 8bit operands
2818 int encode = dst->encoding();
2819 if (encode == 0) {
2820 emit_int8((unsigned char)0xA9);
2821 } else {
2822 encode = prefix_and_encode(encode);
2823 emit_int8((unsigned char)0xF7);
2824 emit_int8((unsigned char)(0xC0 | encode));
2825 }
2826 emit_int32(imm32);
2827 }
2829 void Assembler::testl(Register dst, Register src) {
2830 (void) prefix_and_encode(dst->encoding(), src->encoding());
2831 emit_arith(0x85, 0xC0, dst, src);
2832 }
2834 void Assembler::testl(Register dst, Address src) {
2835 InstructionMark im(this);
2836 prefix(src, dst);
2837 emit_int8((unsigned char)0x85);
2838 emit_operand(dst, src);
2839 }
2841 void Assembler::ucomisd(XMMRegister dst, Address src) {
2842 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2843 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2844 }
2846 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2847 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2848 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2849 }
2851 void Assembler::ucomiss(XMMRegister dst, Address src) {
2852 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2853 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2854 }
2856 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2857 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2858 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2859 }
2862 void Assembler::xaddl(Address dst, Register src) {
2863 InstructionMark im(this);
2864 prefix(dst, src);
2865 emit_int8(0x0F);
2866 emit_int8((unsigned char)0xC1);
2867 emit_operand(src, dst);
2868 }
2870 void Assembler::xchgl(Register dst, Address src) { // xchg
2871 InstructionMark im(this);
2872 prefix(src, dst);
2873 emit_int8((unsigned char)0x87);
2874 emit_operand(dst, src);
2875 }
2877 void Assembler::xchgl(Register dst, Register src) {
2878 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2879 emit_int8((unsigned char)0x87);
2880 emit_int8((unsigned char)(0xC0 | encode));
2881 }
2883 void Assembler::xgetbv() {
2884 emit_int8(0x0F);
2885 emit_int8(0x01);
2886 emit_int8((unsigned char)0xD0);
2887 }
2889 void Assembler::xorl(Register dst, int32_t imm32) {
2890 prefix(dst);
2891 emit_arith(0x81, 0xF0, dst, imm32);
2892 }
2894 void Assembler::xorl(Register dst, Address src) {
2895 InstructionMark im(this);
2896 prefix(src, dst);
2897 emit_int8(0x33);
2898 emit_operand(dst, src);
2899 }
2901 void Assembler::xorl(Register dst, Register src) {
2902 (void) prefix_and_encode(dst->encoding(), src->encoding());
2903 emit_arith(0x33, 0xC0, dst, src);
2904 }
2907 // AVX 3-operands scalar float-point arithmetic instructions
2909 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
2910 assert(VM_Version::supports_avx(), "");
2911 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2912 }
2914 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2915 assert(VM_Version::supports_avx(), "");
2916 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2917 }
2919 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
2920 assert(VM_Version::supports_avx(), "");
2921 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2922 }
2924 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2925 assert(VM_Version::supports_avx(), "");
2926 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2927 }
2929 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
2930 assert(VM_Version::supports_avx(), "");
2931 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2932 }
2934 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2935 assert(VM_Version::supports_avx(), "");
2936 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2937 }
2939 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
2940 assert(VM_Version::supports_avx(), "");
2941 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2942 }
2944 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2945 assert(VM_Version::supports_avx(), "");
2946 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2947 }
2949 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
2950 assert(VM_Version::supports_avx(), "");
2951 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2952 }
2954 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2955 assert(VM_Version::supports_avx(), "");
2956 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2957 }
2959 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
2960 assert(VM_Version::supports_avx(), "");
2961 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2962 }
2964 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2965 assert(VM_Version::supports_avx(), "");
2966 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2967 }
2969 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
2970 assert(VM_Version::supports_avx(), "");
2971 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2972 }
2974 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2975 assert(VM_Version::supports_avx(), "");
2976 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2977 }
2979 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
2980 assert(VM_Version::supports_avx(), "");
2981 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2982 }
2984 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2985 assert(VM_Version::supports_avx(), "");
2986 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2987 }
2989 //====================VECTOR ARITHMETIC=====================================
2991 // Float-point vector arithmetic
2993 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
2994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2995 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
2996 }
2998 void Assembler::addps(XMMRegister dst, XMMRegister src) {
2999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3000 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3001 }
3003 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3004 assert(VM_Version::supports_avx(), "");
3005 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3006 }
3008 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3009 assert(VM_Version::supports_avx(), "");
3010 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3011 }
3013 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3014 assert(VM_Version::supports_avx(), "");
3015 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3016 }
3018 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3019 assert(VM_Version::supports_avx(), "");
3020 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3021 }
3023 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3024 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3025 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3026 }
3028 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3029 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3030 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3031 }
3033 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3034 assert(VM_Version::supports_avx(), "");
3035 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3036 }
3038 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3039 assert(VM_Version::supports_avx(), "");
3040 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3041 }
3043 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3044 assert(VM_Version::supports_avx(), "");
3045 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3046 }
3048 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3049 assert(VM_Version::supports_avx(), "");
3050 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3051 }
3053 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3054 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3055 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3056 }
3058 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3059 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3060 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3061 }
3063 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3064 assert(VM_Version::supports_avx(), "");
3065 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3066 }
3068 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3069 assert(VM_Version::supports_avx(), "");
3070 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3071 }
3073 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3074 assert(VM_Version::supports_avx(), "");
3075 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3076 }
3078 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3079 assert(VM_Version::supports_avx(), "");
3080 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3081 }
3083 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3085 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3086 }
3088 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3089 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3090 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3091 }
3093 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3094 assert(VM_Version::supports_avx(), "");
3095 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3096 }
3098 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3099 assert(VM_Version::supports_avx(), "");
3100 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3101 }
3103 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3104 assert(VM_Version::supports_avx(), "");
3105 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3106 }
3108 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3109 assert(VM_Version::supports_avx(), "");
3110 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3111 }
3113 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3114 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3115 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3116 }
3118 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3119 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3120 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3121 }
3123 void Assembler::andps(XMMRegister dst, Address src) {
3124 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3125 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3126 }
3128 void Assembler::andpd(XMMRegister dst, Address src) {
3129 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3130 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3131 }
3133 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3134 assert(VM_Version::supports_avx(), "");
3135 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3136 }
3138 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3139 assert(VM_Version::supports_avx(), "");
3140 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3141 }
3143 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3144 assert(VM_Version::supports_avx(), "");
3145 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3146 }
3148 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3149 assert(VM_Version::supports_avx(), "");
3150 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3151 }
3153 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3154 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3155 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3156 }
3158 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3159 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3160 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3161 }
3163 void Assembler::xorpd(XMMRegister dst, Address src) {
3164 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3165 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3166 }
3168 void Assembler::xorps(XMMRegister dst, Address src) {
3169 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3170 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3171 }
3173 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3174 assert(VM_Version::supports_avx(), "");
3175 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3176 }
3178 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3179 assert(VM_Version::supports_avx(), "");
3180 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3181 }
3183 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3184 assert(VM_Version::supports_avx(), "");
3185 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3186 }
3188 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3189 assert(VM_Version::supports_avx(), "");
3190 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3191 }
3194 // Integer vector arithmetic
3195 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3196 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3197 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3198 }
3200 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3201 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3202 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3203 }
3205 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3206 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3207 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3208 }
3210 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3211 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3212 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3213 }
3215 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3216 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3217 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3218 }
3220 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3221 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3222 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3223 }
3225 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3226 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3227 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3228 }
3230 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3231 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3232 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3233 }
3235 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3236 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3237 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3238 }
3240 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3241 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3242 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3243 }
3245 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3246 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3247 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3248 }
3250 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3251 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3252 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3253 }
3255 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3257 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3258 }
3260 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3262 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3263 }
3265 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3266 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3267 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3268 }
3270 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3272 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3273 }
3275 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3276 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3277 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3278 }
3280 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3281 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3282 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3283 }
3285 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3286 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3287 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3288 }
3290 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3291 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3292 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3293 }
3295 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3296 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3297 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3298 }
3300 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3301 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3302 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3303 }
3305 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3306 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3307 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3308 }
3310 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3311 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3312 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3313 }
3315 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3316 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3317 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3318 }
3320 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3321 assert(VM_Version::supports_sse4_1(), "");
3322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3323 emit_int8(0x40);
3324 emit_int8((unsigned char)(0xC0 | encode));
3325 }
3327 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3328 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3329 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3330 }
3332 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3333 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3334 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3335 emit_int8(0x40);
3336 emit_int8((unsigned char)(0xC0 | encode));
3337 }
3339 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3340 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3341 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3342 }
3344 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3345 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3346 InstructionMark im(this);
3347 int dst_enc = dst->encoding();
3348 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3349 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3350 emit_int8(0x40);
3351 emit_operand(dst, src);
3352 }
3354 // Shift packed integers left by specified number of bits.
3355 void Assembler::psllw(XMMRegister dst, int shift) {
3356 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3357 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3358 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3359 emit_int8(0x71);
3360 emit_int8((unsigned char)(0xC0 | encode));
3361 emit_int8(shift & 0xFF);
3362 }
3364 void Assembler::pslld(XMMRegister dst, int shift) {
3365 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3366 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3367 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3368 emit_int8(0x72);
3369 emit_int8((unsigned char)(0xC0 | encode));
3370 emit_int8(shift & 0xFF);
3371 }
3373 void Assembler::psllq(XMMRegister dst, int shift) {
3374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3375 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3376 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3377 emit_int8(0x73);
3378 emit_int8((unsigned char)(0xC0 | encode));
3379 emit_int8(shift & 0xFF);
3380 }
3382 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3384 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3385 }
3387 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3389 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3390 }
3392 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3393 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3394 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3395 }
3397 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3398 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3399 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3400 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3401 emit_int8(shift & 0xFF);
3402 }
3404 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3405 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3406 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3407 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3408 emit_int8(shift & 0xFF);
3409 }
3411 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3412 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3413 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3414 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3415 emit_int8(shift & 0xFF);
3416 }
3418 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3419 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3420 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3421 }
3423 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3424 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3425 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3426 }
3428 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3429 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3430 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3431 }
3433 // Shift packed integers logically right by specified number of bits.
3434 void Assembler::psrlw(XMMRegister dst, int shift) {
3435 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3436 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3437 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3438 emit_int8(0x71);
3439 emit_int8((unsigned char)(0xC0 | encode));
3440 emit_int8(shift & 0xFF);
3441 }
3443 void Assembler::psrld(XMMRegister dst, int shift) {
3444 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3445 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3446 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3447 emit_int8(0x72);
3448 emit_int8((unsigned char)(0xC0 | encode));
3449 emit_int8(shift & 0xFF);
3450 }
3452 void Assembler::psrlq(XMMRegister dst, int shift) {
3453 // Do not confuse it with psrldq SSE2 instruction which
3454 // shifts 128 bit value in xmm register by number of bytes.
3455 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3456 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3457 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3458 emit_int8(0x73);
3459 emit_int8((unsigned char)(0xC0 | encode));
3460 emit_int8(shift & 0xFF);
3461 }
3463 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3464 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3465 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3466 }
3468 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3469 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3470 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3471 }
3473 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3475 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3476 }
3478 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3479 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3480 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3481 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3482 emit_int8(shift & 0xFF);
3483 }
3485 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3486 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3487 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3488 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3489 emit_int8(shift & 0xFF);
3490 }
3492 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3493 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3494 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3495 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3496 emit_int8(shift & 0xFF);
3497 }
3499 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3500 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3501 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3502 }
3504 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3505 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3506 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3507 }
3509 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3510 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3511 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3512 }
3514 // Shift packed integers arithmetically right by specified number of bits.
3515 void Assembler::psraw(XMMRegister dst, int shift) {
3516 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3517 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3518 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3519 emit_int8(0x71);
3520 emit_int8((unsigned char)(0xC0 | encode));
3521 emit_int8(shift & 0xFF);
3522 }
3524 void Assembler::psrad(XMMRegister dst, int shift) {
3525 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3526 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3527 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3528 emit_int8(0x72);
3529 emit_int8((unsigned char)(0xC0 | encode));
3530 emit_int8(shift & 0xFF);
3531 }
3533 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3534 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3535 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3536 }
3538 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3539 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3540 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3541 }
3543 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3544 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3545 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3546 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3547 emit_int8(shift & 0xFF);
3548 }
3550 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3551 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3552 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3553 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3554 emit_int8(shift & 0xFF);
3555 }
3557 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3558 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3559 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3560 }
3562 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3563 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3564 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3565 }
3568 // AND packed integers
3569 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3571 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3572 }
3574 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3575 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3576 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3577 }
3579 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3580 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3581 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3582 }
3584 void Assembler::por(XMMRegister dst, XMMRegister src) {
3585 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3586 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3587 }
3589 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3590 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3591 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3592 }
3594 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3595 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3596 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3597 }
3599 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3601 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3602 }
3604 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3605 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3606 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3607 }
3609 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3610 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3611 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3612 }
3615 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3616 assert(VM_Version::supports_avx(), "");
3617 bool vector256 = true;
3618 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3619 emit_int8(0x18);
3620 emit_int8((unsigned char)(0xC0 | encode));
3621 // 0x00 - insert into lower 128 bits
3622 // 0x01 - insert into upper 128 bits
3623 emit_int8(0x01);
3624 }
3626 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3627 assert(VM_Version::supports_avx(), "");
3628 InstructionMark im(this);
3629 bool vector256 = true;
3630 assert(dst != xnoreg, "sanity");
3631 int dst_enc = dst->encoding();
3632 // swap src<->dst for encoding
3633 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3634 emit_int8(0x18);
3635 emit_operand(dst, src);
3636 // 0x01 - insert into upper 128 bits
3637 emit_int8(0x01);
3638 }
3640 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3641 assert(VM_Version::supports_avx(), "");
3642 InstructionMark im(this);
3643 bool vector256 = true;
3644 assert(src != xnoreg, "sanity");
3645 int src_enc = src->encoding();
3646 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3647 emit_int8(0x19);
3648 emit_operand(src, dst);
3649 // 0x01 - extract from upper 128 bits
3650 emit_int8(0x01);
3651 }
3653 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3654 assert(VM_Version::supports_avx2(), "");
3655 bool vector256 = true;
3656 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3657 emit_int8(0x38);
3658 emit_int8((unsigned char)(0xC0 | encode));
3659 // 0x00 - insert into lower 128 bits
3660 // 0x01 - insert into upper 128 bits
3661 emit_int8(0x01);
3662 }
3664 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3665 assert(VM_Version::supports_avx2(), "");
3666 InstructionMark im(this);
3667 bool vector256 = true;
3668 assert(dst != xnoreg, "sanity");
3669 int dst_enc = dst->encoding();
3670 // swap src<->dst for encoding
3671 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3672 emit_int8(0x38);
3673 emit_operand(dst, src);
3674 // 0x01 - insert into upper 128 bits
3675 emit_int8(0x01);
3676 }
3678 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3679 assert(VM_Version::supports_avx2(), "");
3680 InstructionMark im(this);
3681 bool vector256 = true;
3682 assert(src != xnoreg, "sanity");
3683 int src_enc = src->encoding();
3684 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3685 emit_int8(0x39);
3686 emit_operand(src, dst);
3687 // 0x01 - extract from upper 128 bits
3688 emit_int8(0x01);
3689 }
3691 // duplicate 4-bytes integer data from src into 8 locations in dest
3692 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3693 assert(VM_Version::supports_avx2(), "");
3694 bool vector256 = true;
3695 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3696 emit_int8(0x58);
3697 emit_int8((unsigned char)(0xC0 | encode));
3698 }
3700 void Assembler::vzeroupper() {
3701 assert(VM_Version::supports_avx(), "");
3702 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3703 emit_int8(0x77);
3704 }
3707 #ifndef _LP64
3708 // 32bit only pieces of the assembler
3710 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3711 // NO PREFIX AS NEVER 64BIT
3712 InstructionMark im(this);
3713 emit_int8((unsigned char)0x81);
3714 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3715 emit_data(imm32, rspec, 0);
3716 }
3718 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3719 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3720 InstructionMark im(this);
3721 emit_int8((unsigned char)0x81);
3722 emit_operand(rdi, src1);
3723 emit_data(imm32, rspec, 0);
3724 }
3726 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3727 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3728 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3729 void Assembler::cmpxchg8(Address adr) {
3730 InstructionMark im(this);
3731 emit_int8(0x0F);
3732 emit_int8((unsigned char)0xC7);
3733 emit_operand(rcx, adr);
3734 }
3736 void Assembler::decl(Register dst) {
3737 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3738 emit_int8(0x48 | dst->encoding());
3739 }
3741 #endif // _LP64
3743 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3745 void Assembler::fabs() {
3746 emit_int8((unsigned char)0xD9);
3747 emit_int8((unsigned char)0xE1);
3748 }
3750 void Assembler::fadd(int i) {
3751 emit_farith(0xD8, 0xC0, i);
3752 }
3754 void Assembler::fadd_d(Address src) {
3755 InstructionMark im(this);
3756 emit_int8((unsigned char)0xDC);
3757 emit_operand32(rax, src);
3758 }
3760 void Assembler::fadd_s(Address src) {
3761 InstructionMark im(this);
3762 emit_int8((unsigned char)0xD8);
3763 emit_operand32(rax, src);
3764 }
3766 void Assembler::fadda(int i) {
3767 emit_farith(0xDC, 0xC0, i);
3768 }
3770 void Assembler::faddp(int i) {
3771 emit_farith(0xDE, 0xC0, i);
3772 }
3774 void Assembler::fchs() {
3775 emit_int8((unsigned char)0xD9);
3776 emit_int8((unsigned char)0xE0);
3777 }
3779 void Assembler::fcom(int i) {
3780 emit_farith(0xD8, 0xD0, i);
3781 }
3783 void Assembler::fcomp(int i) {
3784 emit_farith(0xD8, 0xD8, i);
3785 }
3787 void Assembler::fcomp_d(Address src) {
3788 InstructionMark im(this);
3789 emit_int8((unsigned char)0xDC);
3790 emit_operand32(rbx, src);
3791 }
3793 void Assembler::fcomp_s(Address src) {
3794 InstructionMark im(this);
3795 emit_int8((unsigned char)0xD8);
3796 emit_operand32(rbx, src);
3797 }
3799 void Assembler::fcompp() {
3800 emit_int8((unsigned char)0xDE);
3801 emit_int8((unsigned char)0xD9);
3802 }
3804 void Assembler::fcos() {
3805 emit_int8((unsigned char)0xD9);
3806 emit_int8((unsigned char)0xFF);
3807 }
3809 void Assembler::fdecstp() {
3810 emit_int8((unsigned char)0xD9);
3811 emit_int8((unsigned char)0xF6);
3812 }
3814 void Assembler::fdiv(int i) {
3815 emit_farith(0xD8, 0xF0, i);
3816 }
3818 void Assembler::fdiv_d(Address src) {
3819 InstructionMark im(this);
3820 emit_int8((unsigned char)0xDC);
3821 emit_operand32(rsi, src);
3822 }
3824 void Assembler::fdiv_s(Address src) {
3825 InstructionMark im(this);
3826 emit_int8((unsigned char)0xD8);
3827 emit_operand32(rsi, src);
3828 }
3830 void Assembler::fdiva(int i) {
3831 emit_farith(0xDC, 0xF8, i);
3832 }
3834 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3835 // is erroneous for some of the floating-point instructions below.
3837 void Assembler::fdivp(int i) {
3838 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3839 }
3841 void Assembler::fdivr(int i) {
3842 emit_farith(0xD8, 0xF8, i);
3843 }
3845 void Assembler::fdivr_d(Address src) {
3846 InstructionMark im(this);
3847 emit_int8((unsigned char)0xDC);
3848 emit_operand32(rdi, src);
3849 }
3851 void Assembler::fdivr_s(Address src) {
3852 InstructionMark im(this);
3853 emit_int8((unsigned char)0xD8);
3854 emit_operand32(rdi, src);
3855 }
3857 void Assembler::fdivra(int i) {
3858 emit_farith(0xDC, 0xF0, i);
3859 }
3861 void Assembler::fdivrp(int i) {
3862 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3863 }
3865 void Assembler::ffree(int i) {
3866 emit_farith(0xDD, 0xC0, i);
3867 }
3869 void Assembler::fild_d(Address adr) {
3870 InstructionMark im(this);
3871 emit_int8((unsigned char)0xDF);
3872 emit_operand32(rbp, adr);
3873 }
3875 void Assembler::fild_s(Address adr) {
3876 InstructionMark im(this);
3877 emit_int8((unsigned char)0xDB);
3878 emit_operand32(rax, adr);
3879 }
3881 void Assembler::fincstp() {
3882 emit_int8((unsigned char)0xD9);
3883 emit_int8((unsigned char)0xF7);
3884 }
3886 void Assembler::finit() {
3887 emit_int8((unsigned char)0x9B);
3888 emit_int8((unsigned char)0xDB);
3889 emit_int8((unsigned char)0xE3);
3890 }
3892 void Assembler::fist_s(Address adr) {
3893 InstructionMark im(this);
3894 emit_int8((unsigned char)0xDB);
3895 emit_operand32(rdx, adr);
3896 }
3898 void Assembler::fistp_d(Address adr) {
3899 InstructionMark im(this);
3900 emit_int8((unsigned char)0xDF);
3901 emit_operand32(rdi, adr);
3902 }
3904 void Assembler::fistp_s(Address adr) {
3905 InstructionMark im(this);
3906 emit_int8((unsigned char)0xDB);
3907 emit_operand32(rbx, adr);
3908 }
3910 void Assembler::fld1() {
3911 emit_int8((unsigned char)0xD9);
3912 emit_int8((unsigned char)0xE8);
3913 }
3915 void Assembler::fld_d(Address adr) {
3916 InstructionMark im(this);
3917 emit_int8((unsigned char)0xDD);
3918 emit_operand32(rax, adr);
3919 }
3921 void Assembler::fld_s(Address adr) {
3922 InstructionMark im(this);
3923 emit_int8((unsigned char)0xD9);
3924 emit_operand32(rax, adr);
3925 }
3928 void Assembler::fld_s(int index) {
3929 emit_farith(0xD9, 0xC0, index);
3930 }
3932 void Assembler::fld_x(Address adr) {
3933 InstructionMark im(this);
3934 emit_int8((unsigned char)0xDB);
3935 emit_operand32(rbp, adr);
3936 }
3938 void Assembler::fldcw(Address src) {
3939 InstructionMark im(this);
3940 emit_int8((unsigned char)0xD9);
3941 emit_operand32(rbp, src);
3942 }
3944 void Assembler::fldenv(Address src) {
3945 InstructionMark im(this);
3946 emit_int8((unsigned char)0xD9);
3947 emit_operand32(rsp, src);
3948 }
3950 void Assembler::fldlg2() {
3951 emit_int8((unsigned char)0xD9);
3952 emit_int8((unsigned char)0xEC);
3953 }
3955 void Assembler::fldln2() {
3956 emit_int8((unsigned char)0xD9);
3957 emit_int8((unsigned char)0xED);
3958 }
3960 void Assembler::fldz() {
3961 emit_int8((unsigned char)0xD9);
3962 emit_int8((unsigned char)0xEE);
3963 }
3965 void Assembler::flog() {
3966 fldln2();
3967 fxch();
3968 fyl2x();
3969 }
3971 void Assembler::flog10() {
3972 fldlg2();
3973 fxch();
3974 fyl2x();
3975 }
3977 void Assembler::fmul(int i) {
3978 emit_farith(0xD8, 0xC8, i);
3979 }
3981 void Assembler::fmul_d(Address src) {
3982 InstructionMark im(this);
3983 emit_int8((unsigned char)0xDC);
3984 emit_operand32(rcx, src);
3985 }
3987 void Assembler::fmul_s(Address src) {
3988 InstructionMark im(this);
3989 emit_int8((unsigned char)0xD8);
3990 emit_operand32(rcx, src);
3991 }
3993 void Assembler::fmula(int i) {
3994 emit_farith(0xDC, 0xC8, i);
3995 }
3997 void Assembler::fmulp(int i) {
3998 emit_farith(0xDE, 0xC8, i);
3999 }
4001 void Assembler::fnsave(Address dst) {
4002 InstructionMark im(this);
4003 emit_int8((unsigned char)0xDD);
4004 emit_operand32(rsi, dst);
4005 }
4007 void Assembler::fnstcw(Address src) {
4008 InstructionMark im(this);
4009 emit_int8((unsigned char)0x9B);
4010 emit_int8((unsigned char)0xD9);
4011 emit_operand32(rdi, src);
4012 }
4014 void Assembler::fnstsw_ax() {
4015 emit_int8((unsigned char)0xDF);
4016 emit_int8((unsigned char)0xE0);
4017 }
4019 void Assembler::fprem() {
4020 emit_int8((unsigned char)0xD9);
4021 emit_int8((unsigned char)0xF8);
4022 }
4024 void Assembler::fprem1() {
4025 emit_int8((unsigned char)0xD9);
4026 emit_int8((unsigned char)0xF5);
4027 }
4029 void Assembler::frstor(Address src) {
4030 InstructionMark im(this);
4031 emit_int8((unsigned char)0xDD);
4032 emit_operand32(rsp, src);
4033 }
4035 void Assembler::fsin() {
4036 emit_int8((unsigned char)0xD9);
4037 emit_int8((unsigned char)0xFE);
4038 }
4040 void Assembler::fsqrt() {
4041 emit_int8((unsigned char)0xD9);
4042 emit_int8((unsigned char)0xFA);
4043 }
4045 void Assembler::fst_d(Address adr) {
4046 InstructionMark im(this);
4047 emit_int8((unsigned char)0xDD);
4048 emit_operand32(rdx, adr);
4049 }
4051 void Assembler::fst_s(Address adr) {
4052 InstructionMark im(this);
4053 emit_int8((unsigned char)0xD9);
4054 emit_operand32(rdx, adr);
4055 }
4057 void Assembler::fstp_d(Address adr) {
4058 InstructionMark im(this);
4059 emit_int8((unsigned char)0xDD);
4060 emit_operand32(rbx, adr);
4061 }
4063 void Assembler::fstp_d(int index) {
4064 emit_farith(0xDD, 0xD8, index);
4065 }
4067 void Assembler::fstp_s(Address adr) {
4068 InstructionMark im(this);
4069 emit_int8((unsigned char)0xD9);
4070 emit_operand32(rbx, adr);
4071 }
4073 void Assembler::fstp_x(Address adr) {
4074 InstructionMark im(this);
4075 emit_int8((unsigned char)0xDB);
4076 emit_operand32(rdi, adr);
4077 }
4079 void Assembler::fsub(int i) {
4080 emit_farith(0xD8, 0xE0, i);
4081 }
4083 void Assembler::fsub_d(Address src) {
4084 InstructionMark im(this);
4085 emit_int8((unsigned char)0xDC);
4086 emit_operand32(rsp, src);
4087 }
4089 void Assembler::fsub_s(Address src) {
4090 InstructionMark im(this);
4091 emit_int8((unsigned char)0xD8);
4092 emit_operand32(rsp, src);
4093 }
4095 void Assembler::fsuba(int i) {
4096 emit_farith(0xDC, 0xE8, i);
4097 }
4099 void Assembler::fsubp(int i) {
4100 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4101 }
4103 void Assembler::fsubr(int i) {
4104 emit_farith(0xD8, 0xE8, i);
4105 }
4107 void Assembler::fsubr_d(Address src) {
4108 InstructionMark im(this);
4109 emit_int8((unsigned char)0xDC);
4110 emit_operand32(rbp, src);
4111 }
4113 void Assembler::fsubr_s(Address src) {
4114 InstructionMark im(this);
4115 emit_int8((unsigned char)0xD8);
4116 emit_operand32(rbp, src);
4117 }
4119 void Assembler::fsubra(int i) {
4120 emit_farith(0xDC, 0xE0, i);
4121 }
4123 void Assembler::fsubrp(int i) {
4124 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4125 }
4127 void Assembler::ftan() {
4128 emit_int8((unsigned char)0xD9);
4129 emit_int8((unsigned char)0xF2);
4130 emit_int8((unsigned char)0xDD);
4131 emit_int8((unsigned char)0xD8);
4132 }
4134 void Assembler::ftst() {
4135 emit_int8((unsigned char)0xD9);
4136 emit_int8((unsigned char)0xE4);
4137 }
4139 void Assembler::fucomi(int i) {
4140 // make sure the instruction is supported (introduced for P6, together with cmov)
4141 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4142 emit_farith(0xDB, 0xE8, i);
4143 }
4145 void Assembler::fucomip(int i) {
4146 // make sure the instruction is supported (introduced for P6, together with cmov)
4147 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4148 emit_farith(0xDF, 0xE8, i);
4149 }
4151 void Assembler::fwait() {
4152 emit_int8((unsigned char)0x9B);
4153 }
4155 void Assembler::fxch(int i) {
4156 emit_farith(0xD9, 0xC8, i);
4157 }
4159 void Assembler::fyl2x() {
4160 emit_int8((unsigned char)0xD9);
4161 emit_int8((unsigned char)0xF1);
4162 }
4164 void Assembler::frndint() {
4165 emit_int8((unsigned char)0xD9);
4166 emit_int8((unsigned char)0xFC);
4167 }
4169 void Assembler::f2xm1() {
4170 emit_int8((unsigned char)0xD9);
4171 emit_int8((unsigned char)0xF0);
4172 }
4174 void Assembler::fldl2e() {
4175 emit_int8((unsigned char)0xD9);
4176 emit_int8((unsigned char)0xEA);
4177 }
4179 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4180 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4181 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4182 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4184 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4185 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4186 if (pre > 0) {
4187 emit_int8(simd_pre[pre]);
4188 }
4189 if (rex_w) {
4190 prefixq(adr, xreg);
4191 } else {
4192 prefix(adr, xreg);
4193 }
4194 if (opc > 0) {
4195 emit_int8(0x0F);
4196 int opc2 = simd_opc[opc];
4197 if (opc2 > 0) {
4198 emit_int8(opc2);
4199 }
4200 }
4201 }
4203 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4204 if (pre > 0) {
4205 emit_int8(simd_pre[pre]);
4206 }
4207 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4208 prefix_and_encode(dst_enc, src_enc);
4209 if (opc > 0) {
4210 emit_int8(0x0F);
4211 int opc2 = simd_opc[opc];
4212 if (opc2 > 0) {
4213 emit_int8(opc2);
4214 }
4215 }
4216 return encode;
4217 }
4220 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4221 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4222 prefix(VEX_3bytes);
4224 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4225 byte1 = (~byte1) & 0xE0;
4226 byte1 |= opc;
4227 emit_int8(byte1);
4229 int byte2 = ((~nds_enc) & 0xf) << 3;
4230 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4231 emit_int8(byte2);
4232 } else {
4233 prefix(VEX_2bytes);
4235 int byte1 = vex_r ? VEX_R : 0;
4236 byte1 = (~byte1) & 0x80;
4237 byte1 |= ((~nds_enc) & 0xf) << 3;
4238 byte1 |= (vector256 ? 4 : 0) | pre;
4239 emit_int8(byte1);
4240 }
4241 }
4243 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4244 bool vex_r = (xreg_enc >= 8);
4245 bool vex_b = adr.base_needs_rex();
4246 bool vex_x = adr.index_needs_rex();
4247 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4248 }
4250 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4251 bool vex_r = (dst_enc >= 8);
4252 bool vex_b = (src_enc >= 8);
4253 bool vex_x = false;
4254 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4255 return (((dst_enc & 7) << 3) | (src_enc & 7));
4256 }
4259 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4260 if (UseAVX > 0) {
4261 int xreg_enc = xreg->encoding();
4262 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4263 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4264 } else {
4265 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4266 rex_prefix(adr, xreg, pre, opc, rex_w);
4267 }
4268 }
4270 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4271 int dst_enc = dst->encoding();
4272 int src_enc = src->encoding();
4273 if (UseAVX > 0) {
4274 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4275 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4276 } else {
4277 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4278 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4279 }
4280 }
4282 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4283 InstructionMark im(this);
4284 simd_prefix(dst, dst, src, pre);
4285 emit_int8(opcode);
4286 emit_operand(dst, src);
4287 }
4289 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4290 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4291 emit_int8(opcode);
4292 emit_int8((unsigned char)(0xC0 | encode));
4293 }
4295 // Versions with no second source register (non-destructive source).
4296 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4297 InstructionMark im(this);
4298 simd_prefix(dst, xnoreg, src, pre);
4299 emit_int8(opcode);
4300 emit_operand(dst, src);
4301 }
4303 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4304 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4305 emit_int8(opcode);
4306 emit_int8((unsigned char)(0xC0 | encode));
4307 }
4309 // 3-operands AVX instructions
4310 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4311 Address src, VexSimdPrefix pre, bool vector256) {
4312 InstructionMark im(this);
4313 vex_prefix(dst, nds, src, pre, vector256);
4314 emit_int8(opcode);
4315 emit_operand(dst, src);
4316 }
4318 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4319 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4320 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4321 emit_int8(opcode);
4322 emit_int8((unsigned char)(0xC0 | encode));
4323 }
4325 #ifndef _LP64
4327 void Assembler::incl(Register dst) {
4328 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4329 emit_int8(0x40 | dst->encoding());
4330 }
4332 void Assembler::lea(Register dst, Address src) {
4333 leal(dst, src);
4334 }
4336 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4337 InstructionMark im(this);
4338 emit_int8((unsigned char)0xC7);
4339 emit_operand(rax, dst);
4340 emit_data((int)imm32, rspec, 0);
4341 }
4343 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4344 InstructionMark im(this);
4345 int encode = prefix_and_encode(dst->encoding());
4346 emit_int8((unsigned char)(0xB8 | encode));
4347 emit_data((int)imm32, rspec, 0);
4348 }
4350 void Assembler::popa() { // 32bit
4351 emit_int8(0x61);
4352 }
4354 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4355 InstructionMark im(this);
4356 emit_int8(0x68);
4357 emit_data(imm32, rspec, 0);
4358 }
4360 void Assembler::pusha() { // 32bit
4361 emit_int8(0x60);
4362 }
4364 void Assembler::set_byte_if_not_zero(Register dst) {
4365 emit_int8(0x0F);
4366 emit_int8((unsigned char)0x95);
4367 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4368 }
4370 void Assembler::shldl(Register dst, Register src) {
4371 emit_int8(0x0F);
4372 emit_int8((unsigned char)0xA5);
4373 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4374 }
4376 void Assembler::shrdl(Register dst, Register src) {
4377 emit_int8(0x0F);
4378 emit_int8((unsigned char)0xAD);
4379 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4380 }
4382 #else // LP64
4384 void Assembler::set_byte_if_not_zero(Register dst) {
4385 int enc = prefix_and_encode(dst->encoding(), true);
4386 emit_int8(0x0F);
4387 emit_int8((unsigned char)0x95);
4388 emit_int8((unsigned char)(0xE0 | enc));
4389 }
4391 // 64bit only pieces of the assembler
4392 // This should only be used by 64bit instructions that can use rip-relative
4393 // it cannot be used by instructions that want an immediate value.
4395 bool Assembler::reachable(AddressLiteral adr) {
4396 int64_t disp;
4397 // None will force a 64bit literal to the code stream. Likely a placeholder
4398 // for something that will be patched later and we need to certain it will
4399 // always be reachable.
4400 if (adr.reloc() == relocInfo::none) {
4401 return false;
4402 }
4403 if (adr.reloc() == relocInfo::internal_word_type) {
4404 // This should be rip relative and easily reachable.
4405 return true;
4406 }
4407 if (adr.reloc() == relocInfo::virtual_call_type ||
4408 adr.reloc() == relocInfo::opt_virtual_call_type ||
4409 adr.reloc() == relocInfo::static_call_type ||
4410 adr.reloc() == relocInfo::static_stub_type ) {
4411 // This should be rip relative within the code cache and easily
4412 // reachable until we get huge code caches. (At which point
4413 // ic code is going to have issues).
4414 return true;
4415 }
4416 if (adr.reloc() != relocInfo::external_word_type &&
4417 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4418 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4419 adr.reloc() != relocInfo::runtime_call_type ) {
4420 return false;
4421 }
4423 // Stress the correction code
4424 if (ForceUnreachable) {
4425 // Must be runtimecall reloc, see if it is in the codecache
4426 // Flipping stuff in the codecache to be unreachable causes issues
4427 // with things like inline caches where the additional instructions
4428 // are not handled.
4429 if (CodeCache::find_blob(adr._target) == NULL) {
4430 return false;
4431 }
4432 }
4433 // For external_word_type/runtime_call_type if it is reachable from where we
4434 // are now (possibly a temp buffer) and where we might end up
4435 // anywhere in the codeCache then we are always reachable.
4436 // This would have to change if we ever save/restore shared code
4437 // to be more pessimistic.
4438 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4439 if (!is_simm32(disp)) return false;
4440 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4441 if (!is_simm32(disp)) return false;
4443 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4445 // Because rip relative is a disp + address_of_next_instruction and we
4446 // don't know the value of address_of_next_instruction we apply a fudge factor
4447 // to make sure we will be ok no matter the size of the instruction we get placed into.
4448 // We don't have to fudge the checks above here because they are already worst case.
4450 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4451 // + 4 because better safe than sorry.
4452 const int fudge = 12 + 4;
4453 if (disp < 0) {
4454 disp -= fudge;
4455 } else {
4456 disp += fudge;
4457 }
4458 return is_simm32(disp);
4459 }
4461 // Check if the polling page is not reachable from the code cache using rip-relative
4462 // addressing.
4463 bool Assembler::is_polling_page_far() {
4464 intptr_t addr = (intptr_t)os::get_polling_page();
4465 return ForceUnreachable ||
4466 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4467 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4468 }
4470 void Assembler::emit_data64(jlong data,
4471 relocInfo::relocType rtype,
4472 int format) {
4473 if (rtype == relocInfo::none) {
4474 emit_int64(data);
4475 } else {
4476 emit_data64(data, Relocation::spec_simple(rtype), format);
4477 }
4478 }
4480 void Assembler::emit_data64(jlong data,
4481 RelocationHolder const& rspec,
4482 int format) {
4483 assert(imm_operand == 0, "default format must be immediate in this file");
4484 assert(imm_operand == format, "must be immediate");
4485 assert(inst_mark() != NULL, "must be inside InstructionMark");
4486 // Do not use AbstractAssembler::relocate, which is not intended for
4487 // embedded words. Instead, relocate to the enclosing instruction.
4488 code_section()->relocate(inst_mark(), rspec, format);
4489 #ifdef ASSERT
4490 check_relocation(rspec, format);
4491 #endif
4492 emit_int64(data);
4493 }
4495 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4496 if (reg_enc >= 8) {
4497 prefix(REX_B);
4498 reg_enc -= 8;
4499 } else if (byteinst && reg_enc >= 4) {
4500 prefix(REX);
4501 }
4502 return reg_enc;
4503 }
4505 int Assembler::prefixq_and_encode(int reg_enc) {
4506 if (reg_enc < 8) {
4507 prefix(REX_W);
4508 } else {
4509 prefix(REX_WB);
4510 reg_enc -= 8;
4511 }
4512 return reg_enc;
4513 }
4515 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4516 if (dst_enc < 8) {
4517 if (src_enc >= 8) {
4518 prefix(REX_B);
4519 src_enc -= 8;
4520 } else if (byteinst && src_enc >= 4) {
4521 prefix(REX);
4522 }
4523 } else {
4524 if (src_enc < 8) {
4525 prefix(REX_R);
4526 } else {
4527 prefix(REX_RB);
4528 src_enc -= 8;
4529 }
4530 dst_enc -= 8;
4531 }
4532 return dst_enc << 3 | src_enc;
4533 }
4535 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4536 if (dst_enc < 8) {
4537 if (src_enc < 8) {
4538 prefix(REX_W);
4539 } else {
4540 prefix(REX_WB);
4541 src_enc -= 8;
4542 }
4543 } else {
4544 if (src_enc < 8) {
4545 prefix(REX_WR);
4546 } else {
4547 prefix(REX_WRB);
4548 src_enc -= 8;
4549 }
4550 dst_enc -= 8;
4551 }
4552 return dst_enc << 3 | src_enc;
4553 }
4555 void Assembler::prefix(Register reg) {
4556 if (reg->encoding() >= 8) {
4557 prefix(REX_B);
4558 }
4559 }
4561 void Assembler::prefix(Address adr) {
4562 if (adr.base_needs_rex()) {
4563 if (adr.index_needs_rex()) {
4564 prefix(REX_XB);
4565 } else {
4566 prefix(REX_B);
4567 }
4568 } else {
4569 if (adr.index_needs_rex()) {
4570 prefix(REX_X);
4571 }
4572 }
4573 }
4575 void Assembler::prefixq(Address adr) {
4576 if (adr.base_needs_rex()) {
4577 if (adr.index_needs_rex()) {
4578 prefix(REX_WXB);
4579 } else {
4580 prefix(REX_WB);
4581 }
4582 } else {
4583 if (adr.index_needs_rex()) {
4584 prefix(REX_WX);
4585 } else {
4586 prefix(REX_W);
4587 }
4588 }
4589 }
4592 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4593 if (reg->encoding() < 8) {
4594 if (adr.base_needs_rex()) {
4595 if (adr.index_needs_rex()) {
4596 prefix(REX_XB);
4597 } else {
4598 prefix(REX_B);
4599 }
4600 } else {
4601 if (adr.index_needs_rex()) {
4602 prefix(REX_X);
4603 } else if (byteinst && reg->encoding() >= 4 ) {
4604 prefix(REX);
4605 }
4606 }
4607 } else {
4608 if (adr.base_needs_rex()) {
4609 if (adr.index_needs_rex()) {
4610 prefix(REX_RXB);
4611 } else {
4612 prefix(REX_RB);
4613 }
4614 } else {
4615 if (adr.index_needs_rex()) {
4616 prefix(REX_RX);
4617 } else {
4618 prefix(REX_R);
4619 }
4620 }
4621 }
4622 }
4624 void Assembler::prefixq(Address adr, Register src) {
4625 if (src->encoding() < 8) {
4626 if (adr.base_needs_rex()) {
4627 if (adr.index_needs_rex()) {
4628 prefix(REX_WXB);
4629 } else {
4630 prefix(REX_WB);
4631 }
4632 } else {
4633 if (adr.index_needs_rex()) {
4634 prefix(REX_WX);
4635 } else {
4636 prefix(REX_W);
4637 }
4638 }
4639 } else {
4640 if (adr.base_needs_rex()) {
4641 if (adr.index_needs_rex()) {
4642 prefix(REX_WRXB);
4643 } else {
4644 prefix(REX_WRB);
4645 }
4646 } else {
4647 if (adr.index_needs_rex()) {
4648 prefix(REX_WRX);
4649 } else {
4650 prefix(REX_WR);
4651 }
4652 }
4653 }
4654 }
4656 void Assembler::prefix(Address adr, XMMRegister reg) {
4657 if (reg->encoding() < 8) {
4658 if (adr.base_needs_rex()) {
4659 if (adr.index_needs_rex()) {
4660 prefix(REX_XB);
4661 } else {
4662 prefix(REX_B);
4663 }
4664 } else {
4665 if (adr.index_needs_rex()) {
4666 prefix(REX_X);
4667 }
4668 }
4669 } else {
4670 if (adr.base_needs_rex()) {
4671 if (adr.index_needs_rex()) {
4672 prefix(REX_RXB);
4673 } else {
4674 prefix(REX_RB);
4675 }
4676 } else {
4677 if (adr.index_needs_rex()) {
4678 prefix(REX_RX);
4679 } else {
4680 prefix(REX_R);
4681 }
4682 }
4683 }
4684 }
4686 void Assembler::prefixq(Address adr, XMMRegister src) {
4687 if (src->encoding() < 8) {
4688 if (adr.base_needs_rex()) {
4689 if (adr.index_needs_rex()) {
4690 prefix(REX_WXB);
4691 } else {
4692 prefix(REX_WB);
4693 }
4694 } else {
4695 if (adr.index_needs_rex()) {
4696 prefix(REX_WX);
4697 } else {
4698 prefix(REX_W);
4699 }
4700 }
4701 } else {
4702 if (adr.base_needs_rex()) {
4703 if (adr.index_needs_rex()) {
4704 prefix(REX_WRXB);
4705 } else {
4706 prefix(REX_WRB);
4707 }
4708 } else {
4709 if (adr.index_needs_rex()) {
4710 prefix(REX_WRX);
4711 } else {
4712 prefix(REX_WR);
4713 }
4714 }
4715 }
4716 }
4718 void Assembler::adcq(Register dst, int32_t imm32) {
4719 (void) prefixq_and_encode(dst->encoding());
4720 emit_arith(0x81, 0xD0, dst, imm32);
4721 }
4723 void Assembler::adcq(Register dst, Address src) {
4724 InstructionMark im(this);
4725 prefixq(src, dst);
4726 emit_int8(0x13);
4727 emit_operand(dst, src);
4728 }
4730 void Assembler::adcq(Register dst, Register src) {
4731 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4732 emit_arith(0x13, 0xC0, dst, src);
4733 }
4735 void Assembler::addq(Address dst, int32_t imm32) {
4736 InstructionMark im(this);
4737 prefixq(dst);
4738 emit_arith_operand(0x81, rax, dst,imm32);
4739 }
4741 void Assembler::addq(Address dst, Register src) {
4742 InstructionMark im(this);
4743 prefixq(dst, src);
4744 emit_int8(0x01);
4745 emit_operand(src, dst);
4746 }
4748 void Assembler::addq(Register dst, int32_t imm32) {
4749 (void) prefixq_and_encode(dst->encoding());
4750 emit_arith(0x81, 0xC0, dst, imm32);
4751 }
4753 void Assembler::addq(Register dst, Address src) {
4754 InstructionMark im(this);
4755 prefixq(src, dst);
4756 emit_int8(0x03);
4757 emit_operand(dst, src);
4758 }
4760 void Assembler::addq(Register dst, Register src) {
4761 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4762 emit_arith(0x03, 0xC0, dst, src);
4763 }
4765 void Assembler::andq(Address dst, int32_t imm32) {
4766 InstructionMark im(this);
4767 prefixq(dst);
4768 emit_int8((unsigned char)0x81);
4769 emit_operand(rsp, dst, 4);
4770 emit_int32(imm32);
4771 }
4773 void Assembler::andq(Register dst, int32_t imm32) {
4774 (void) prefixq_and_encode(dst->encoding());
4775 emit_arith(0x81, 0xE0, dst, imm32);
4776 }
4778 void Assembler::andq(Register dst, Address src) {
4779 InstructionMark im(this);
4780 prefixq(src, dst);
4781 emit_int8(0x23);
4782 emit_operand(dst, src);
4783 }
4785 void Assembler::andq(Register dst, Register src) {
4786 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4787 emit_arith(0x23, 0xC0, dst, src);
4788 }
4790 void Assembler::bsfq(Register dst, Register src) {
4791 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4792 emit_int8(0x0F);
4793 emit_int8((unsigned char)0xBC);
4794 emit_int8((unsigned char)(0xC0 | encode));
4795 }
4797 void Assembler::bsrq(Register dst, Register src) {
4798 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4799 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4800 emit_int8(0x0F);
4801 emit_int8((unsigned char)0xBD);
4802 emit_int8((unsigned char)(0xC0 | encode));
4803 }
4805 void Assembler::bswapq(Register reg) {
4806 int encode = prefixq_and_encode(reg->encoding());
4807 emit_int8(0x0F);
4808 emit_int8((unsigned char)(0xC8 | encode));
4809 }
4811 void Assembler::cdqq() {
4812 prefix(REX_W);
4813 emit_int8((unsigned char)0x99);
4814 }
4816 void Assembler::clflush(Address adr) {
4817 prefix(adr);
4818 emit_int8(0x0F);
4819 emit_int8((unsigned char)0xAE);
4820 emit_operand(rdi, adr);
4821 }
4823 void Assembler::cmovq(Condition cc, Register dst, Register src) {
4824 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4825 emit_int8(0x0F);
4826 emit_int8(0x40 | cc);
4827 emit_int8((unsigned char)(0xC0 | encode));
4828 }
4830 void Assembler::cmovq(Condition cc, Register dst, Address src) {
4831 InstructionMark im(this);
4832 prefixq(src, dst);
4833 emit_int8(0x0F);
4834 emit_int8(0x40 | cc);
4835 emit_operand(dst, src);
4836 }
4838 void Assembler::cmpq(Address dst, int32_t imm32) {
4839 InstructionMark im(this);
4840 prefixq(dst);
4841 emit_int8((unsigned char)0x81);
4842 emit_operand(rdi, dst, 4);
4843 emit_int32(imm32);
4844 }
4846 void Assembler::cmpq(Register dst, int32_t imm32) {
4847 (void) prefixq_and_encode(dst->encoding());
4848 emit_arith(0x81, 0xF8, dst, imm32);
4849 }
4851 void Assembler::cmpq(Address dst, Register src) {
4852 InstructionMark im(this);
4853 prefixq(dst, src);
4854 emit_int8(0x3B);
4855 emit_operand(src, dst);
4856 }
4858 void Assembler::cmpq(Register dst, Register src) {
4859 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4860 emit_arith(0x3B, 0xC0, dst, src);
4861 }
4863 void Assembler::cmpq(Register dst, Address src) {
4864 InstructionMark im(this);
4865 prefixq(src, dst);
4866 emit_int8(0x3B);
4867 emit_operand(dst, src);
4868 }
4870 void Assembler::cmpxchgq(Register reg, Address adr) {
4871 InstructionMark im(this);
4872 prefixq(adr, reg);
4873 emit_int8(0x0F);
4874 emit_int8((unsigned char)0xB1);
4875 emit_operand(reg, adr);
4876 }
4878 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
4879 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4880 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
4881 emit_int8(0x2A);
4882 emit_int8((unsigned char)(0xC0 | encode));
4883 }
4885 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
4886 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4887 InstructionMark im(this);
4888 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
4889 emit_int8(0x2A);
4890 emit_operand(dst, src);
4891 }
4893 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
4894 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4895 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
4896 emit_int8(0x2A);
4897 emit_int8((unsigned char)(0xC0 | encode));
4898 }
4900 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
4901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4902 InstructionMark im(this);
4903 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
4904 emit_int8(0x2A);
4905 emit_operand(dst, src);
4906 }
4908 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
4909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4910 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
4911 emit_int8(0x2C);
4912 emit_int8((unsigned char)(0xC0 | encode));
4913 }
4915 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
4916 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4917 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
4918 emit_int8(0x2C);
4919 emit_int8((unsigned char)(0xC0 | encode));
4920 }
4922 void Assembler::decl(Register dst) {
4923 // Don't use it directly. Use MacroAssembler::decrementl() instead.
4924 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
4925 int encode = prefix_and_encode(dst->encoding());
4926 emit_int8((unsigned char)0xFF);
4927 emit_int8((unsigned char)(0xC8 | encode));
4928 }
4930 void Assembler::decq(Register dst) {
4931 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4932 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4933 int encode = prefixq_and_encode(dst->encoding());
4934 emit_int8((unsigned char)0xFF);
4935 emit_int8(0xC8 | encode);
4936 }
4938 void Assembler::decq(Address dst) {
4939 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4940 InstructionMark im(this);
4941 prefixq(dst);
4942 emit_int8((unsigned char)0xFF);
4943 emit_operand(rcx, dst);
4944 }
4946 void Assembler::fxrstor(Address src) {
4947 prefixq(src);
4948 emit_int8(0x0F);
4949 emit_int8((unsigned char)0xAE);
4950 emit_operand(as_Register(1), src);
4951 }
4953 void Assembler::fxsave(Address dst) {
4954 prefixq(dst);
4955 emit_int8(0x0F);
4956 emit_int8((unsigned char)0xAE);
4957 emit_operand(as_Register(0), dst);
4958 }
4960 void Assembler::idivq(Register src) {
4961 int encode = prefixq_and_encode(src->encoding());
4962 emit_int8((unsigned char)0xF7);
4963 emit_int8((unsigned char)(0xF8 | encode));
4964 }
4966 void Assembler::imulq(Register dst, Register src) {
4967 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4968 emit_int8(0x0F);
4969 emit_int8((unsigned char)0xAF);
4970 emit_int8((unsigned char)(0xC0 | encode));
4971 }
4973 void Assembler::imulq(Register dst, Register src, int value) {
4974 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4975 if (is8bit(value)) {
4976 emit_int8(0x6B);
4977 emit_int8((unsigned char)(0xC0 | encode));
4978 emit_int8(value & 0xFF);
4979 } else {
4980 emit_int8(0x69);
4981 emit_int8((unsigned char)(0xC0 | encode));
4982 emit_int32(value);
4983 }
4984 }
4986 void Assembler::incl(Register dst) {
4987 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4988 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4989 int encode = prefix_and_encode(dst->encoding());
4990 emit_int8((unsigned char)0xFF);
4991 emit_int8((unsigned char)(0xC0 | encode));
4992 }
4994 void Assembler::incq(Register dst) {
4995 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4996 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4997 int encode = prefixq_and_encode(dst->encoding());
4998 emit_int8((unsigned char)0xFF);
4999 emit_int8((unsigned char)(0xC0 | encode));
5000 }
5002 void Assembler::incq(Address dst) {
5003 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5004 InstructionMark im(this);
5005 prefixq(dst);
5006 emit_int8((unsigned char)0xFF);
5007 emit_operand(rax, dst);
5008 }
5010 void Assembler::lea(Register dst, Address src) {
5011 leaq(dst, src);
5012 }
5014 void Assembler::leaq(Register dst, Address src) {
5015 InstructionMark im(this);
5016 prefixq(src, dst);
5017 emit_int8((unsigned char)0x8D);
5018 emit_operand(dst, src);
5019 }
5021 void Assembler::mov64(Register dst, int64_t imm64) {
5022 InstructionMark im(this);
5023 int encode = prefixq_and_encode(dst->encoding());
5024 emit_int8((unsigned char)(0xB8 | encode));
5025 emit_int64(imm64);
5026 }
5028 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5029 InstructionMark im(this);
5030 int encode = prefixq_and_encode(dst->encoding());
5031 emit_int8(0xB8 | encode);
5032 emit_data64(imm64, rspec);
5033 }
5035 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5036 InstructionMark im(this);
5037 int encode = prefix_and_encode(dst->encoding());
5038 emit_int8((unsigned char)(0xB8 | encode));
5039 emit_data((int)imm32, rspec, narrow_oop_operand);
5040 }
5042 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5043 InstructionMark im(this);
5044 prefix(dst);
5045 emit_int8((unsigned char)0xC7);
5046 emit_operand(rax, dst, 4);
5047 emit_data((int)imm32, rspec, narrow_oop_operand);
5048 }
5050 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5051 InstructionMark im(this);
5052 int encode = prefix_and_encode(src1->encoding());
5053 emit_int8((unsigned char)0x81);
5054 emit_int8((unsigned char)(0xF8 | encode));
5055 emit_data((int)imm32, rspec, narrow_oop_operand);
5056 }
5058 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5059 InstructionMark im(this);
5060 prefix(src1);
5061 emit_int8((unsigned char)0x81);
5062 emit_operand(rax, src1, 4);
5063 emit_data((int)imm32, rspec, narrow_oop_operand);
5064 }
5066 void Assembler::lzcntq(Register dst, Register src) {
5067 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5068 emit_int8((unsigned char)0xF3);
5069 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5070 emit_int8(0x0F);
5071 emit_int8((unsigned char)0xBD);
5072 emit_int8((unsigned char)(0xC0 | encode));
5073 }
5075 void Assembler::movdq(XMMRegister dst, Register src) {
5076 // table D-1 says MMX/SSE2
5077 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5078 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5079 emit_int8(0x6E);
5080 emit_int8((unsigned char)(0xC0 | encode));
5081 }
5083 void Assembler::movdq(Register dst, XMMRegister src) {
5084 // table D-1 says MMX/SSE2
5085 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5086 // swap src/dst to get correct prefix
5087 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5088 emit_int8(0x7E);
5089 emit_int8((unsigned char)(0xC0 | encode));
5090 }
5092 void Assembler::movq(Register dst, Register src) {
5093 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5094 emit_int8((unsigned char)0x8B);
5095 emit_int8((unsigned char)(0xC0 | encode));
5096 }
5098 void Assembler::movq(Register dst, Address src) {
5099 InstructionMark im(this);
5100 prefixq(src, dst);
5101 emit_int8((unsigned char)0x8B);
5102 emit_operand(dst, src);
5103 }
5105 void Assembler::movq(Address dst, Register src) {
5106 InstructionMark im(this);
5107 prefixq(dst, src);
5108 emit_int8((unsigned char)0x89);
5109 emit_operand(src, dst);
5110 }
5112 void Assembler::movsbq(Register dst, Address src) {
5113 InstructionMark im(this);
5114 prefixq(src, dst);
5115 emit_int8(0x0F);
5116 emit_int8((unsigned char)0xBE);
5117 emit_operand(dst, src);
5118 }
5120 void Assembler::movsbq(Register dst, Register src) {
5121 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5122 emit_int8(0x0F);
5123 emit_int8((unsigned char)0xBE);
5124 emit_int8((unsigned char)(0xC0 | encode));
5125 }
5127 void Assembler::movslq(Register dst, int32_t imm32) {
5128 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5129 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5130 // as a result we shouldn't use until tested at runtime...
5131 ShouldNotReachHere();
5132 InstructionMark im(this);
5133 int encode = prefixq_and_encode(dst->encoding());
5134 emit_int8((unsigned char)(0xC7 | encode));
5135 emit_int32(imm32);
5136 }
5138 void Assembler::movslq(Address dst, int32_t imm32) {
5139 assert(is_simm32(imm32), "lost bits");
5140 InstructionMark im(this);
5141 prefixq(dst);
5142 emit_int8((unsigned char)0xC7);
5143 emit_operand(rax, dst, 4);
5144 emit_int32(imm32);
5145 }
5147 void Assembler::movslq(Register dst, Address src) {
5148 InstructionMark im(this);
5149 prefixq(src, dst);
5150 emit_int8(0x63);
5151 emit_operand(dst, src);
5152 }
5154 void Assembler::movslq(Register dst, Register src) {
5155 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5156 emit_int8(0x63);
5157 emit_int8((unsigned char)(0xC0 | encode));
5158 }
5160 void Assembler::movswq(Register dst, Address src) {
5161 InstructionMark im(this);
5162 prefixq(src, dst);
5163 emit_int8(0x0F);
5164 emit_int8((unsigned char)0xBF);
5165 emit_operand(dst, src);
5166 }
5168 void Assembler::movswq(Register dst, Register src) {
5169 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5170 emit_int8((unsigned char)0x0F);
5171 emit_int8((unsigned char)0xBF);
5172 emit_int8((unsigned char)(0xC0 | encode));
5173 }
5175 void Assembler::movzbq(Register dst, Address src) {
5176 InstructionMark im(this);
5177 prefixq(src, dst);
5178 emit_int8((unsigned char)0x0F);
5179 emit_int8((unsigned char)0xB6);
5180 emit_operand(dst, src);
5181 }
5183 void Assembler::movzbq(Register dst, Register src) {
5184 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5185 emit_int8(0x0F);
5186 emit_int8((unsigned char)0xB6);
5187 emit_int8(0xC0 | encode);
5188 }
5190 void Assembler::movzwq(Register dst, Address src) {
5191 InstructionMark im(this);
5192 prefixq(src, dst);
5193 emit_int8((unsigned char)0x0F);
5194 emit_int8((unsigned char)0xB7);
5195 emit_operand(dst, src);
5196 }
5198 void Assembler::movzwq(Register dst, Register src) {
5199 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5200 emit_int8((unsigned char)0x0F);
5201 emit_int8((unsigned char)0xB7);
5202 emit_int8((unsigned char)(0xC0 | encode));
5203 }
5205 void Assembler::negq(Register dst) {
5206 int encode = prefixq_and_encode(dst->encoding());
5207 emit_int8((unsigned char)0xF7);
5208 emit_int8((unsigned char)(0xD8 | encode));
5209 }
5211 void Assembler::notq(Register dst) {
5212 int encode = prefixq_and_encode(dst->encoding());
5213 emit_int8((unsigned char)0xF7);
5214 emit_int8((unsigned char)(0xD0 | encode));
5215 }
5217 void Assembler::orq(Address dst, int32_t imm32) {
5218 InstructionMark im(this);
5219 prefixq(dst);
5220 emit_int8((unsigned char)0x81);
5221 emit_operand(rcx, dst, 4);
5222 emit_int32(imm32);
5223 }
5225 void Assembler::orq(Register dst, int32_t imm32) {
5226 (void) prefixq_and_encode(dst->encoding());
5227 emit_arith(0x81, 0xC8, dst, imm32);
5228 }
5230 void Assembler::orq(Register dst, Address src) {
5231 InstructionMark im(this);
5232 prefixq(src, dst);
5233 emit_int8(0x0B);
5234 emit_operand(dst, src);
5235 }
5237 void Assembler::orq(Register dst, Register src) {
5238 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5239 emit_arith(0x0B, 0xC0, dst, src);
5240 }
5242 void Assembler::popa() { // 64bit
5243 movq(r15, Address(rsp, 0));
5244 movq(r14, Address(rsp, wordSize));
5245 movq(r13, Address(rsp, 2 * wordSize));
5246 movq(r12, Address(rsp, 3 * wordSize));
5247 movq(r11, Address(rsp, 4 * wordSize));
5248 movq(r10, Address(rsp, 5 * wordSize));
5249 movq(r9, Address(rsp, 6 * wordSize));
5250 movq(r8, Address(rsp, 7 * wordSize));
5251 movq(rdi, Address(rsp, 8 * wordSize));
5252 movq(rsi, Address(rsp, 9 * wordSize));
5253 movq(rbp, Address(rsp, 10 * wordSize));
5254 // skip rsp
5255 movq(rbx, Address(rsp, 12 * wordSize));
5256 movq(rdx, Address(rsp, 13 * wordSize));
5257 movq(rcx, Address(rsp, 14 * wordSize));
5258 movq(rax, Address(rsp, 15 * wordSize));
5260 addq(rsp, 16 * wordSize);
5261 }
5263 void Assembler::popcntq(Register dst, Address src) {
5264 assert(VM_Version::supports_popcnt(), "must support");
5265 InstructionMark im(this);
5266 emit_int8((unsigned char)0xF3);
5267 prefixq(src, dst);
5268 emit_int8((unsigned char)0x0F);
5269 emit_int8((unsigned char)0xB8);
5270 emit_operand(dst, src);
5271 }
5273 void Assembler::popcntq(Register dst, Register src) {
5274 assert(VM_Version::supports_popcnt(), "must support");
5275 emit_int8((unsigned char)0xF3);
5276 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5277 emit_int8((unsigned char)0x0F);
5278 emit_int8((unsigned char)0xB8);
5279 emit_int8((unsigned char)(0xC0 | encode));
5280 }
5282 void Assembler::popq(Address dst) {
5283 InstructionMark im(this);
5284 prefixq(dst);
5285 emit_int8((unsigned char)0x8F);
5286 emit_operand(rax, dst);
5287 }
5289 void Assembler::pusha() { // 64bit
5290 // we have to store original rsp. ABI says that 128 bytes
5291 // below rsp are local scratch.
5292 movq(Address(rsp, -5 * wordSize), rsp);
5294 subq(rsp, 16 * wordSize);
5296 movq(Address(rsp, 15 * wordSize), rax);
5297 movq(Address(rsp, 14 * wordSize), rcx);
5298 movq(Address(rsp, 13 * wordSize), rdx);
5299 movq(Address(rsp, 12 * wordSize), rbx);
5300 // skip rsp
5301 movq(Address(rsp, 10 * wordSize), rbp);
5302 movq(Address(rsp, 9 * wordSize), rsi);
5303 movq(Address(rsp, 8 * wordSize), rdi);
5304 movq(Address(rsp, 7 * wordSize), r8);
5305 movq(Address(rsp, 6 * wordSize), r9);
5306 movq(Address(rsp, 5 * wordSize), r10);
5307 movq(Address(rsp, 4 * wordSize), r11);
5308 movq(Address(rsp, 3 * wordSize), r12);
5309 movq(Address(rsp, 2 * wordSize), r13);
5310 movq(Address(rsp, wordSize), r14);
5311 movq(Address(rsp, 0), r15);
5312 }
5314 void Assembler::pushq(Address src) {
5315 InstructionMark im(this);
5316 prefixq(src);
5317 emit_int8((unsigned char)0xFF);
5318 emit_operand(rsi, src);
5319 }
5321 void Assembler::rclq(Register dst, int imm8) {
5322 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5323 int encode = prefixq_and_encode(dst->encoding());
5324 if (imm8 == 1) {
5325 emit_int8((unsigned char)0xD1);
5326 emit_int8((unsigned char)(0xD0 | encode));
5327 } else {
5328 emit_int8((unsigned char)0xC1);
5329 emit_int8((unsigned char)(0xD0 | encode));
5330 emit_int8(imm8);
5331 }
5332 }
5333 void Assembler::sarq(Register dst, int imm8) {
5334 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5335 int encode = prefixq_and_encode(dst->encoding());
5336 if (imm8 == 1) {
5337 emit_int8((unsigned char)0xD1);
5338 emit_int8((unsigned char)(0xF8 | encode));
5339 } else {
5340 emit_int8((unsigned char)0xC1);
5341 emit_int8((unsigned char)(0xF8 | encode));
5342 emit_int8(imm8);
5343 }
5344 }
5346 void Assembler::sarq(Register dst) {
5347 int encode = prefixq_and_encode(dst->encoding());
5348 emit_int8((unsigned char)0xD3);
5349 emit_int8((unsigned char)(0xF8 | encode));
5350 }
5352 void Assembler::sbbq(Address dst, int32_t imm32) {
5353 InstructionMark im(this);
5354 prefixq(dst);
5355 emit_arith_operand(0x81, rbx, dst, imm32);
5356 }
5358 void Assembler::sbbq(Register dst, int32_t imm32) {
5359 (void) prefixq_and_encode(dst->encoding());
5360 emit_arith(0x81, 0xD8, dst, imm32);
5361 }
5363 void Assembler::sbbq(Register dst, Address src) {
5364 InstructionMark im(this);
5365 prefixq(src, dst);
5366 emit_int8(0x1B);
5367 emit_operand(dst, src);
5368 }
5370 void Assembler::sbbq(Register dst, Register src) {
5371 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5372 emit_arith(0x1B, 0xC0, dst, src);
5373 }
5375 void Assembler::shlq(Register dst, int imm8) {
5376 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5377 int encode = prefixq_and_encode(dst->encoding());
5378 if (imm8 == 1) {
5379 emit_int8((unsigned char)0xD1);
5380 emit_int8((unsigned char)(0xE0 | encode));
5381 } else {
5382 emit_int8((unsigned char)0xC1);
5383 emit_int8((unsigned char)(0xE0 | encode));
5384 emit_int8(imm8);
5385 }
5386 }
5388 void Assembler::shlq(Register dst) {
5389 int encode = prefixq_and_encode(dst->encoding());
5390 emit_int8((unsigned char)0xD3);
5391 emit_int8((unsigned char)(0xE0 | encode));
5392 }
5394 void Assembler::shrq(Register dst, int imm8) {
5395 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5396 int encode = prefixq_and_encode(dst->encoding());
5397 emit_int8((unsigned char)0xC1);
5398 emit_int8((unsigned char)(0xE8 | encode));
5399 emit_int8(imm8);
5400 }
5402 void Assembler::shrq(Register dst) {
5403 int encode = prefixq_and_encode(dst->encoding());
5404 emit_int8((unsigned char)0xD3);
5405 emit_int8(0xE8 | encode);
5406 }
5408 void Assembler::subq(Address dst, int32_t imm32) {
5409 InstructionMark im(this);
5410 prefixq(dst);
5411 emit_arith_operand(0x81, rbp, dst, imm32);
5412 }
5414 void Assembler::subq(Address dst, Register src) {
5415 InstructionMark im(this);
5416 prefixq(dst, src);
5417 emit_int8(0x29);
5418 emit_operand(src, dst);
5419 }
5421 void Assembler::subq(Register dst, int32_t imm32) {
5422 (void) prefixq_and_encode(dst->encoding());
5423 emit_arith(0x81, 0xE8, dst, imm32);
5424 }
5426 // Force generation of a 4 byte immediate value even if it fits into 8bit
5427 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5428 (void) prefixq_and_encode(dst->encoding());
5429 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5430 }
5432 void Assembler::subq(Register dst, Address src) {
5433 InstructionMark im(this);
5434 prefixq(src, dst);
5435 emit_int8(0x2B);
5436 emit_operand(dst, src);
5437 }
5439 void Assembler::subq(Register dst, Register src) {
5440 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5441 emit_arith(0x2B, 0xC0, dst, src);
5442 }
5444 void Assembler::testq(Register dst, int32_t imm32) {
5445 // not using emit_arith because test
5446 // doesn't support sign-extension of
5447 // 8bit operands
5448 int encode = dst->encoding();
5449 if (encode == 0) {
5450 prefix(REX_W);
5451 emit_int8((unsigned char)0xA9);
5452 } else {
5453 encode = prefixq_and_encode(encode);
5454 emit_int8((unsigned char)0xF7);
5455 emit_int8((unsigned char)(0xC0 | encode));
5456 }
5457 emit_int32(imm32);
5458 }
5460 void Assembler::testq(Register dst, Register src) {
5461 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5462 emit_arith(0x85, 0xC0, dst, src);
5463 }
5465 void Assembler::xaddq(Address dst, Register src) {
5466 InstructionMark im(this);
5467 prefixq(dst, src);
5468 emit_int8(0x0F);
5469 emit_int8((unsigned char)0xC1);
5470 emit_operand(src, dst);
5471 }
5473 void Assembler::xchgq(Register dst, Address src) {
5474 InstructionMark im(this);
5475 prefixq(src, dst);
5476 emit_int8((unsigned char)0x87);
5477 emit_operand(dst, src);
5478 }
5480 void Assembler::xchgq(Register dst, Register src) {
5481 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5482 emit_int8((unsigned char)0x87);
5483 emit_int8((unsigned char)(0xc0 | encode));
5484 }
5486 void Assembler::xorq(Register dst, Register src) {
5487 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5488 emit_arith(0x33, 0xC0, dst, src);
5489 }
5491 void Assembler::xorq(Register dst, Address src) {
5492 InstructionMark im(this);
5493 prefixq(src, dst);
5494 emit_int8(0x33);
5495 emit_operand(dst, src);
5496 }
5498 #endif // !LP64