1.1 --- a/src/cpu/x86/vm/assembler_x86.cpp Tue Jan 22 11:31:25 2013 -0800 1.2 +++ b/src/cpu/x86/vm/assembler_x86.cpp Tue Jan 22 15:34:16 2013 -0800 1.3 @@ -2263,6 +2263,18 @@ 1.4 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); 1.5 } 1.6 1.7 +void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { 1.8 + assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 1.9 + emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256); 1.10 +} 1.11 + 1.12 +void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) { 1.13 + int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256); 1.14 + emit_int8(0x00); 1.15 + emit_int8(0xC0 | encode); 1.16 + emit_int8(imm8); 1.17 +} 1.18 + 1.19 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 1.20 assert(VM_Version::supports_sse4_2(), ""); 1.21 InstructionMark im(this); 1.22 @@ -2475,7 +2487,7 @@ 1.23 assert(dst != xnoreg, "sanity"); 1.24 int dst_enc = dst->encoding(); 1.25 // swap src<->dst for encoding 1.26 - vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); 1.27 + vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); 1.28 emit_int8(0x17); 1.29 emit_operand(dst, src); 1.30 }