Thu, 19 Mar 2015 19:53:34 +0100
8074869: C2 code generator can replace -0.0f with +0.0f on Linux
Summary: Instead of 'fpclass', use cast float->int and double->long to check if value is +0.0f and +0.0d, respectively.
Reviewed-by: kvn, simonis, dlong
1 //
2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2014 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 //
27 // PPC64 Architecture Description File
28 //
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
79 // PPC64 has 32 64-bit integer registers.
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
233 // Condition Codes Flag Registers
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
248 // Special registers of PPC64
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
267 // It's worth about 1% on SPEC geomean to get this right.
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
335 // scratch register
336 F0, F0_H,
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
398 //-------Architecture Description Register Classes-----------------------
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
560 reg_class r19_bits64_reg(R19_H, R19);
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
861 %}
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
907 source %{
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
977 return false;
978 }
980 #define __ _masm.
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
985 // ****************************************************************************
987 // REQUIRED FUNCTIONALITY
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
993 // PPC port: Removed use of lazy constant construct.
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1025 //=============================================================================
1027 // condition code conversions
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1041 //=============================================================================
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1080 //=============================================================================
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1088 //=============================================================================
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1110 //=============================================================================
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1122 //=============================================================================
1124 %} // interrupt source
1126 source_hpp %{ // Header information of the source block.
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1134 class CallStubImpl {
1136 public:
1138 // Emit call stub, compiled java to interpreter.
1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1141 // Size of call trampoline stub.
1142 // This doesn't need to be accurate to the byte, but it
1143 // must be larger than or equal to the real size of the stub.
1144 static uint size_call_trampoline() {
1145 return trampoline_stub_size;
1146 }
1148 // number of relocations needed by a call trampoline stub
1149 static uint reloc_call_trampoline() {
1150 return 5;
1151 }
1153 };
1155 %} // end source_hpp
1157 source %{
1159 // Emit a trampoline stub for a call to a target which is too far away.
1160 //
1161 // code sequences:
1162 //
1163 // call-site:
1164 // branch-and-link to <destination> or <trampoline stub>
1165 //
1166 // Related trampoline stub for this call-site in the stub section:
1167 // load the call target from the constant pool
1168 // branch via CTR (LR/link still points to the call-site above)
1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1171 // Start the stub.
1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1173 if (stub == NULL) {
1174 Compile::current()->env()->record_out_of_memory_failure();
1175 return;
1176 }
1178 // For java_to_interp stubs we use R11_scratch1 as scratch register
1179 // and in call trampoline stubs we use R12_scratch2. This way we
1180 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1181 Register reg_scratch = R12_scratch2;
1183 // Create a trampoline stub relocation which relates this trampoline stub
1184 // with the call instruction at insts_call_instruction_offset in the
1185 // instructions code-section.
1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1187 const int stub_start_offset = __ offset();
1189 // Now, create the trampoline stub's code:
1190 // - load the TOC
1191 // - load the call target from the constant pool
1192 // - call
1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1195 __ mtctr(reg_scratch);
1196 __ bctr();
1198 const address stub_start_addr = __ addr_at(stub_start_offset);
1200 // FIXME: Assert that the trampoline stub can be identified and patched.
1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1204 "encoded offset into the constant pool must match");
1205 // Trampoline_stub_size should be good.
1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1209 // End the stub.
1210 __ end_a_stub();
1211 }
1213 //=============================================================================
1215 // Emit an inline branch-and-link call and a related trampoline stub.
1216 //
1217 // code sequences:
1218 //
1219 // call-site:
1220 // branch-and-link to <destination> or <trampoline stub>
1221 //
1222 // Related trampoline stub for this call-site in the stub section:
1223 // load the call target from the constant pool
1224 // branch via CTR (LR/link still points to the call-site above)
1225 //
1227 typedef struct {
1228 int insts_call_instruction_offset;
1229 int ret_addr_offset;
1230 } EmitCallOffsets;
1232 // Emit a branch-and-link instruction that branches to a trampoline.
1233 // - Remember the offset of the branch-and-link instruction.
1234 // - Add a relocation at the branch-and-link instruction.
1235 // - Emit a branch-and-link.
1236 // - Remember the return pc offset.
1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1238 EmitCallOffsets offsets = { -1, -1 };
1239 const int start_offset = __ offset();
1240 offsets.insts_call_instruction_offset = __ offset();
1242 // No entry point given, use the current pc.
1243 if (entry_point == NULL) entry_point = __ pc();
1245 if (!Compile::current()->in_scratch_emit_size()) {
1246 // Put the entry point as a constant into the constant pool.
1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1250 // Emit the trampoline stub which will be related to the branch-and-link below.
1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1252 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full.
1253 __ relocate(rtype);
1254 }
1256 // Note: At this point we do not have the address of the trampoline
1257 // stub, and the entry point might be too far away for bl, so __ pc()
1258 // serves as dummy and the bl will be patched later.
1259 __ bl((address) __ pc());
1261 offsets.ret_addr_offset = __ offset() - start_offset;
1263 return offsets;
1264 }
1266 //=============================================================================
1268 // Factory for creating loadConL* nodes for large/small constant pool.
1270 static inline jlong replicate_immF(float con) {
1271 // Replicate float con 2 times and pack into vector.
1272 int val = *((int*)&con);
1273 jlong lval = val;
1274 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1275 return lval;
1276 }
1278 //=============================================================================
1280 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1281 int Compile::ConstantTable::calculate_table_base_offset() const {
1282 return 0; // absolute addressing, no offset
1283 }
1285 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1286 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1287 Compile *C = ra_->C;
1289 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1290 MachNode *m1 = new (C) loadToc_hiNode();
1291 MachNode *m2 = new (C) loadToc_loNode();
1293 m1->add_req(NULL);
1294 m2->add_req(NULL, m1);
1295 m1->_opnds[0] = op_dst;
1296 m2->_opnds[0] = op_dst;
1297 m2->_opnds[1] = op_dst;
1298 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1299 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1300 nodes->push(m1);
1301 nodes->push(m2);
1302 }
1304 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1305 // Is postalloc expanded.
1306 ShouldNotReachHere();
1307 }
1309 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1310 return 0;
1311 }
1313 #ifndef PRODUCT
1314 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1315 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1316 }
1317 #endif
1319 //=============================================================================
1321 #ifndef PRODUCT
1322 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1323 Compile* C = ra_->C;
1324 const long framesize = C->frame_slots() << LogBytesPerInt;
1326 st->print("PROLOG\n\t");
1327 if (C->need_stack_bang(framesize)) {
1328 st->print("stack_overflow_check\n\t");
1329 }
1331 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1332 st->print("save return pc\n\t");
1333 st->print("push frame %ld\n\t", -framesize);
1334 }
1335 }
1336 #endif
1338 // Macro used instead of the common __ to emulate the pipes of PPC.
1339 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1340 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1341 // still no scheduling of this code is possible, the micro scheduler is aware of the
1342 // code and can update its internal data. The following mechanism is used to achieve this:
1343 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1344 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1345 #if 0 // TODO: PPC port
1346 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1347 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1348 _masm.
1349 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1350 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1351 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1352 C->hb_scheduling()->_pdScheduling->advance_offset
1353 #else
1354 #define ___(op) if (UsePower6SchedulerPPC64) \
1355 Unimplemented(); \
1356 _masm.
1357 #define ___stop if (UsePower6SchedulerPPC64) \
1358 Unimplemented()
1359 #define ___advance if (UsePower6SchedulerPPC64) \
1360 Unimplemented()
1361 #endif
1363 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1364 Compile* C = ra_->C;
1365 MacroAssembler _masm(&cbuf);
1367 const long framesize = C->frame_size_in_bytes();
1368 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1370 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1372 const Register return_pc = R20; // Must match return_addr() in frame section.
1373 const Register callers_sp = R21;
1374 const Register push_frame_temp = R22;
1375 const Register toc_temp = R23;
1376 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1378 if (method_is_frameless) {
1379 // Add nop at beginning of all frameless methods to prevent any
1380 // oop instructions from getting overwritten by make_not_entrant
1381 // (patching attempt would fail).
1382 ___(nop) nop();
1383 } else {
1384 // Get return pc.
1385 ___(mflr) mflr(return_pc);
1386 }
1388 // Calls to C2R adapters often do not accept exceptional returns.
1389 // We require that their callers must bang for them. But be
1390 // careful, because some VM calls (such as call site linkage) can
1391 // use several kilobytes of stack. But the stack safety zone should
1392 // account for that. See bugs 4446381, 4468289, 4497237.
1394 int bangsize = C->bang_size_in_bytes();
1395 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1396 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1397 // Unfortunately we cannot use the function provided in
1398 // assembler.cpp as we have to emulate the pipes. So I had to
1399 // insert the code of generate_stack_overflow_check(), see
1400 // assembler.cpp for some illuminative comments.
1401 const int page_size = os::vm_page_size();
1402 int bang_end = StackShadowPages * page_size;
1404 // This is how far the previous frame's stack banging extended.
1405 const int bang_end_safe = bang_end;
1407 if (bangsize > page_size) {
1408 bang_end += bangsize;
1409 }
1411 int bang_offset = bang_end_safe;
1413 while (bang_offset <= bang_end) {
1414 // Need at least one stack bang at end of shadow zone.
1416 // Again I had to copy code, this time from assembler_ppc.cpp,
1417 // bang_stack_with_offset - see there for comments.
1419 // Stack grows down, caller passes positive offset.
1420 assert(bang_offset > 0, "must bang with positive offset");
1422 long stdoffset = -bang_offset;
1424 if (Assembler::is_simm(stdoffset, 16)) {
1425 // Signed 16 bit offset, a simple std is ok.
1426 if (UseLoadInstructionsForStackBangingPPC64) {
1427 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1428 } else {
1429 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1430 }
1431 } else if (Assembler::is_simm(stdoffset, 31)) {
1432 // Use largeoffset calculations for addis & ld/std.
1433 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1434 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1436 Register tmp = R11;
1437 ___(addis) addis(tmp, R1_SP, hi);
1438 if (UseLoadInstructionsForStackBangingPPC64) {
1439 ___(ld) ld(R0, lo, tmp);
1440 } else {
1441 ___(std) std(R0, lo, tmp);
1442 }
1443 } else {
1444 ShouldNotReachHere();
1445 }
1447 bang_offset += page_size;
1448 }
1449 // R11 trashed
1450 } // C->need_stack_bang(framesize) && UseStackBanging
1452 unsigned int bytes = (unsigned int)framesize;
1453 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1454 ciMethod *currMethod = C->method();
1456 // Optimized version for most common case.
1457 if (UsePower6SchedulerPPC64 &&
1458 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1459 !(false /* ConstantsALot TODO: PPC port*/)) {
1460 ___(or) mr(callers_sp, R1_SP);
1461 ___(std) std(return_pc, _abi(lr), R1_SP);
1462 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1463 return;
1464 }
1466 if (!method_is_frameless) {
1467 // Get callers sp.
1468 ___(or) mr(callers_sp, R1_SP);
1470 // Push method's frame, modifies SP.
1471 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1472 // The ABI is already accounted for in 'framesize' via the
1473 // 'out_preserve' area.
1474 Register tmp = push_frame_temp;
1475 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1476 if (Assembler::is_simm(-offset, 16)) {
1477 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1478 } else {
1479 long x = -offset;
1480 // Had to insert load_const(tmp, -offset).
1481 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1482 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1483 ___(rldicr) sldi(tmp, tmp, 32);
1484 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1485 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1487 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1488 }
1489 }
1490 #if 0 // TODO: PPC port
1491 // For testing large constant pools, emit a lot of constants to constant pool.
1492 // "Randomize" const_size.
1493 if (ConstantsALot) {
1494 const int num_consts = const_size();
1495 for (int i = 0; i < num_consts; i++) {
1496 __ long_constant(0xB0B5B00BBABE);
1497 }
1498 }
1499 #endif
1500 if (!method_is_frameless) {
1501 // Save return pc.
1502 ___(std) std(return_pc, _abi(lr), callers_sp);
1503 }
1504 }
1505 #undef ___
1506 #undef ___stop
1507 #undef ___advance
1509 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1510 // Variable size. determine dynamically.
1511 return MachNode::size(ra_);
1512 }
1514 int MachPrologNode::reloc() const {
1515 // Return number of relocatable values contained in this instruction.
1516 return 1; // 1 reloc entry for load_const(toc).
1517 }
1519 //=============================================================================
1521 #ifndef PRODUCT
1522 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1523 Compile* C = ra_->C;
1525 st->print("EPILOG\n\t");
1526 st->print("restore return pc\n\t");
1527 st->print("pop frame\n\t");
1529 if (do_polling() && C->is_method_compilation()) {
1530 st->print("touch polling page\n\t");
1531 }
1532 }
1533 #endif
1535 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1536 Compile* C = ra_->C;
1537 MacroAssembler _masm(&cbuf);
1539 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1540 assert(framesize >= 0, "negative frame-size?");
1542 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1543 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1544 const Register return_pc = R11;
1545 const Register polling_page = R12;
1547 if (!method_is_frameless) {
1548 // Restore return pc relative to callers' sp.
1549 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1550 }
1552 if (method_needs_polling) {
1553 if (LoadPollAddressFromThread) {
1554 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1555 Unimplemented();
1556 } else {
1557 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1558 }
1559 }
1561 if (!method_is_frameless) {
1562 // Move return pc to LR.
1563 __ mtlr(return_pc);
1564 // Pop frame (fixed frame-size).
1565 __ addi(R1_SP, R1_SP, (int)framesize);
1566 }
1568 if (method_needs_polling) {
1569 // We need to mark the code position where the load from the safepoint
1570 // polling page was emitted as relocInfo::poll_return_type here.
1571 __ relocate(relocInfo::poll_return_type);
1572 __ load_from_polling_page(polling_page);
1573 }
1574 }
1576 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1577 // Variable size. Determine dynamically.
1578 return MachNode::size(ra_);
1579 }
1581 int MachEpilogNode::reloc() const {
1582 // Return number of relocatable values contained in this instruction.
1583 return 1; // 1 for load_from_polling_page.
1584 }
1586 const Pipeline * MachEpilogNode::pipeline() const {
1587 return MachNode::pipeline_class();
1588 }
1590 // This method seems to be obsolete. It is declared in machnode.hpp
1591 // and defined in all *.ad files, but it is never called. Should we
1592 // get rid of it?
1593 int MachEpilogNode::safepoint_offset() const {
1594 assert(do_polling(), "no return for this epilog node");
1595 return 0;
1596 }
1598 #if 0 // TODO: PPC port
1599 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1600 MacroAssembler _masm(&cbuf);
1601 if (LoadPollAddressFromThread) {
1602 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1603 } else {
1604 _masm.nop();
1605 }
1606 }
1608 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1609 if (LoadPollAddressFromThread) {
1610 return 4;
1611 } else {
1612 return 4;
1613 }
1614 }
1616 #ifndef PRODUCT
1617 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1618 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1619 }
1620 #endif
1622 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1623 return RSCRATCH1_BITS64_REG_mask();
1624 }
1625 #endif // PPC port
1627 // =============================================================================
1629 // Figure out which register class each belongs in: rc_int, rc_float or
1630 // rc_stack.
1631 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1633 static enum RC rc_class(OptoReg::Name reg) {
1634 // Return the register class for the given register. The given register
1635 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1636 // enumeration in adGlobals_ppc64.hpp.
1638 if (reg == OptoReg::Bad) return rc_bad;
1640 // We have 64 integer register halves, starting at index 0.
1641 if (reg < 64) return rc_int;
1643 // We have 64 floating-point register halves, starting at index 64.
1644 if (reg < 64+64) return rc_float;
1646 // Between float regs & stack are the flags regs.
1647 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1649 return rc_stack;
1650 }
1652 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1653 bool do_print, Compile* C, outputStream *st) {
1655 assert(opcode == Assembler::LD_OPCODE ||
1656 opcode == Assembler::STD_OPCODE ||
1657 opcode == Assembler::LWZ_OPCODE ||
1658 opcode == Assembler::STW_OPCODE ||
1659 opcode == Assembler::LFD_OPCODE ||
1660 opcode == Assembler::STFD_OPCODE ||
1661 opcode == Assembler::LFS_OPCODE ||
1662 opcode == Assembler::STFS_OPCODE,
1663 "opcode not supported");
1665 if (cbuf) {
1666 int d =
1667 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1668 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1669 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1670 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1671 }
1672 #ifndef PRODUCT
1673 else if (do_print) {
1674 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1675 op_str,
1676 Matcher::regName[reg],
1677 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1678 }
1679 #endif
1680 return 4; // size
1681 }
1683 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1684 Compile* C = ra_->C;
1686 // Get registers to move.
1687 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1688 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1689 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1690 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1692 enum RC src_hi_rc = rc_class(src_hi);
1693 enum RC src_lo_rc = rc_class(src_lo);
1694 enum RC dst_hi_rc = rc_class(dst_hi);
1695 enum RC dst_lo_rc = rc_class(dst_lo);
1697 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1698 if (src_hi != OptoReg::Bad)
1699 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1700 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1701 "expected aligned-adjacent pairs");
1702 // Generate spill code!
1703 int size = 0;
1705 if (src_lo == dst_lo && src_hi == dst_hi)
1706 return size; // Self copy, no move.
1708 // --------------------------------------
1709 // Memory->Memory Spill. Use R0 to hold the value.
1710 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1711 int src_offset = ra_->reg2offset(src_lo);
1712 int dst_offset = ra_->reg2offset(dst_lo);
1713 if (src_hi != OptoReg::Bad) {
1714 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1715 "expected same type of move for high parts");
1716 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1717 if (!cbuf && !do_size) st->print("\n\t");
1718 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1719 } else {
1720 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1721 if (!cbuf && !do_size) st->print("\n\t");
1722 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1723 }
1724 return size;
1725 }
1727 // --------------------------------------
1728 // Check for float->int copy; requires a trip through memory.
1729 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1730 Unimplemented();
1731 }
1733 // --------------------------------------
1734 // Check for integer reg-reg copy.
1735 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1736 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1737 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1738 size = (Rsrc != Rdst) ? 4 : 0;
1740 if (cbuf) {
1741 MacroAssembler _masm(cbuf);
1742 if (size) {
1743 __ mr(Rdst, Rsrc);
1744 }
1745 }
1746 #ifndef PRODUCT
1747 else if (!do_size) {
1748 if (size) {
1749 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1750 } else {
1751 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1752 }
1753 }
1754 #endif
1755 return size;
1756 }
1758 // Check for integer store.
1759 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1760 int dst_offset = ra_->reg2offset(dst_lo);
1761 if (src_hi != OptoReg::Bad) {
1762 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1763 "expected same type of move for high parts");
1764 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1765 } else {
1766 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1767 }
1768 return size;
1769 }
1771 // Check for integer load.
1772 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1773 int src_offset = ra_->reg2offset(src_lo);
1774 if (src_hi != OptoReg::Bad) {
1775 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1776 "expected same type of move for high parts");
1777 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1778 } else {
1779 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1780 }
1781 return size;
1782 }
1784 // Check for float reg-reg copy.
1785 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1786 if (cbuf) {
1787 MacroAssembler _masm(cbuf);
1788 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1789 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1790 __ fmr(Rdst, Rsrc);
1791 }
1792 #ifndef PRODUCT
1793 else if (!do_size) {
1794 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1795 }
1796 #endif
1797 return 4;
1798 }
1800 // Check for float store.
1801 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1802 int dst_offset = ra_->reg2offset(dst_lo);
1803 if (src_hi != OptoReg::Bad) {
1804 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1805 "expected same type of move for high parts");
1806 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1807 } else {
1808 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1809 }
1810 return size;
1811 }
1813 // Check for float load.
1814 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1815 int src_offset = ra_->reg2offset(src_lo);
1816 if (src_hi != OptoReg::Bad) {
1817 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1818 "expected same type of move for high parts");
1819 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1820 } else {
1821 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1822 }
1823 return size;
1824 }
1826 // --------------------------------------------------------------------
1827 // Check for hi bits still needing moving. Only happens for misaligned
1828 // arguments to native calls.
1829 if (src_hi == dst_hi)
1830 return size; // Self copy; no move.
1832 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1833 ShouldNotReachHere(); // Unimplemented
1834 return 0;
1835 }
1837 #ifndef PRODUCT
1838 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1839 if (!ra_)
1840 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1841 else
1842 implementation(NULL, ra_, false, st);
1843 }
1844 #endif
1846 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1847 implementation(&cbuf, ra_, false, NULL);
1848 }
1850 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1851 return implementation(NULL, ra_, true, NULL);
1852 }
1854 #if 0 // TODO: PPC port
1855 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1856 #ifndef PRODUCT
1857 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1858 #endif
1859 assert(ra_->node_regs_max_index() != 0, "");
1861 // Get registers to move.
1862 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1863 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1864 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1865 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1867 enum RC src_lo_rc = rc_class(src_lo);
1868 enum RC dst_lo_rc = rc_class(dst_lo);
1870 if (src_lo == dst_lo && src_hi == dst_hi)
1871 return ppc64Opcode_none; // Self copy, no move.
1873 // --------------------------------------
1874 // Memory->Memory Spill. Use R0 to hold the value.
1875 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1876 return ppc64Opcode_compound;
1877 }
1879 // --------------------------------------
1880 // Check for float->int copy; requires a trip through memory.
1881 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1882 Unimplemented();
1883 }
1885 // --------------------------------------
1886 // Check for integer reg-reg copy.
1887 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1888 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1889 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1890 if (Rsrc == Rdst) {
1891 return ppc64Opcode_none;
1892 } else {
1893 return ppc64Opcode_or;
1894 }
1895 }
1897 // Check for integer store.
1898 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1899 if (src_hi != OptoReg::Bad) {
1900 return ppc64Opcode_std;
1901 } else {
1902 return ppc64Opcode_stw;
1903 }
1904 }
1906 // Check for integer load.
1907 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1908 if (src_hi != OptoReg::Bad) {
1909 return ppc64Opcode_ld;
1910 } else {
1911 return ppc64Opcode_lwz;
1912 }
1913 }
1915 // Check for float reg-reg copy.
1916 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1917 return ppc64Opcode_fmr;
1918 }
1920 // Check for float store.
1921 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1922 if (src_hi != OptoReg::Bad) {
1923 return ppc64Opcode_stfd;
1924 } else {
1925 return ppc64Opcode_stfs;
1926 }
1927 }
1929 // Check for float load.
1930 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1931 if (src_hi != OptoReg::Bad) {
1932 return ppc64Opcode_lfd;
1933 } else {
1934 return ppc64Opcode_lfs;
1935 }
1936 }
1938 // --------------------------------------------------------------------
1939 // Check for hi bits still needing moving. Only happens for misaligned
1940 // arguments to native calls.
1941 if (src_hi == dst_hi) {
1942 return ppc64Opcode_none; // Self copy; no move.
1943 }
1945 ShouldNotReachHere();
1946 return ppc64Opcode_undefined;
1947 }
1948 #endif // PPC port
1950 #ifndef PRODUCT
1951 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1952 st->print("NOP \t// %d nops to pad for loops.", _count);
1953 }
1954 #endif
1956 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1957 MacroAssembler _masm(&cbuf);
1958 // _count contains the number of nops needed for padding.
1959 for (int i = 0; i < _count; i++) {
1960 __ nop();
1961 }
1962 }
1964 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1965 return _count * 4;
1966 }
1968 #ifndef PRODUCT
1969 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1970 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1971 char reg_str[128];
1972 ra_->dump_register(this, reg_str);
1973 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1974 }
1975 #endif
1977 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1978 MacroAssembler _masm(&cbuf);
1980 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1981 int reg = ra_->get_encode(this);
1983 if (Assembler::is_simm(offset, 16)) {
1984 __ addi(as_Register(reg), R1, offset);
1985 } else {
1986 ShouldNotReachHere();
1987 }
1988 }
1990 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1991 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1992 return 4;
1993 }
1995 #ifndef PRODUCT
1996 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1997 st->print_cr("---- MachUEPNode ----");
1998 st->print_cr("...");
1999 }
2000 #endif
2002 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2003 // This is the unverified entry point.
2004 MacroAssembler _masm(&cbuf);
2006 // Inline_cache contains a klass.
2007 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2008 Register receiver_klass = R12_scratch2; // tmp
2010 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2011 assert(R11_scratch1 == R11, "need prologue scratch register");
2013 // Check for NULL argument if we don't have implicit null checks.
2014 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2015 if (TrapBasedNullChecks) {
2016 __ trap_null_check(R3_ARG1);
2017 } else {
2018 Label valid;
2019 __ cmpdi(CCR0, R3_ARG1, 0);
2020 __ bne_predict_taken(CCR0, valid);
2021 // We have a null argument, branch to ic_miss_stub.
2022 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2023 relocInfo::runtime_call_type);
2024 __ bind(valid);
2025 }
2026 }
2027 // Assume argument is not NULL, load klass from receiver.
2028 __ load_klass(receiver_klass, R3_ARG1);
2030 if (TrapBasedICMissChecks) {
2031 __ trap_ic_miss_check(receiver_klass, ic_klass);
2032 } else {
2033 Label valid;
2034 __ cmpd(CCR0, receiver_klass, ic_klass);
2035 __ beq_predict_taken(CCR0, valid);
2036 // We have an unexpected klass, branch to ic_miss_stub.
2037 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2038 relocInfo::runtime_call_type);
2039 __ bind(valid);
2040 }
2042 // Argument is valid and klass is as expected, continue.
2043 }
2045 #if 0 // TODO: PPC port
2046 // Optimize UEP code on z (save a load_const() call in main path).
2047 int MachUEPNode::ep_offset() {
2048 return 0;
2049 }
2050 #endif
2052 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2053 // Variable size. Determine dynamically.
2054 return MachNode::size(ra_);
2055 }
2057 //=============================================================================
2059 %} // interrupt source
2061 source_hpp %{ // Header information of the source block.
2063 class HandlerImpl {
2065 public:
2067 static int emit_exception_handler(CodeBuffer &cbuf);
2068 static int emit_deopt_handler(CodeBuffer& cbuf);
2070 static uint size_exception_handler() {
2071 // The exception_handler is a b64_patchable.
2072 return MacroAssembler::b64_patchable_size;
2073 }
2075 static uint size_deopt_handler() {
2076 // The deopt_handler is a bl64_patchable.
2077 return MacroAssembler::bl64_patchable_size;
2078 }
2080 };
2082 %} // end source_hpp
2084 source %{
2086 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2087 MacroAssembler _masm(&cbuf);
2089 address base = __ start_a_stub(size_exception_handler());
2090 if (base == NULL) return 0; // CodeBuffer::expand failed
2092 int offset = __ offset();
2093 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2094 relocInfo::runtime_call_type);
2095 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2096 __ end_a_stub();
2098 return offset;
2099 }
2101 // The deopt_handler is like the exception handler, but it calls to
2102 // the deoptimization blob instead of jumping to the exception blob.
2103 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2104 MacroAssembler _masm(&cbuf);
2106 address base = __ start_a_stub(size_deopt_handler());
2107 if (base == NULL) return 0; // CodeBuffer::expand failed
2109 int offset = __ offset();
2110 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2111 relocInfo::runtime_call_type);
2112 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2113 __ end_a_stub();
2115 return offset;
2116 }
2118 //=============================================================================
2120 // Use a frame slots bias for frameless methods if accessing the stack.
2121 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2122 if (as_Register(reg_enc) == R1_SP) {
2123 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2124 }
2125 return 0;
2126 }
2128 const bool Matcher::match_rule_supported(int opcode) {
2129 if (!has_match_rule(opcode))
2130 return false;
2132 switch (opcode) {
2133 case Op_SqrtD:
2134 return VM_Version::has_fsqrt();
2135 case Op_CountLeadingZerosI:
2136 case Op_CountLeadingZerosL:
2137 case Op_CountTrailingZerosI:
2138 case Op_CountTrailingZerosL:
2139 if (!UseCountLeadingZerosInstructionsPPC64)
2140 return false;
2141 break;
2143 case Op_PopCountI:
2144 case Op_PopCountL:
2145 return (UsePopCountInstruction && VM_Version::has_popcntw());
2147 case Op_StrComp:
2148 return SpecialStringCompareTo;
2149 case Op_StrEquals:
2150 return SpecialStringEquals;
2151 case Op_StrIndexOf:
2152 return SpecialStringIndexOf;
2153 }
2155 return true; // Per default match rules are supported.
2156 }
2158 int Matcher::regnum_to_fpu_offset(int regnum) {
2159 // No user for this method?
2160 Unimplemented();
2161 return 999;
2162 }
2164 const bool Matcher::convL2FSupported(void) {
2165 // fcfids can do the conversion (>= Power7).
2166 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2167 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2168 }
2170 // Vector width in bytes.
2171 const int Matcher::vector_width_in_bytes(BasicType bt) {
2172 assert(MaxVectorSize == 8, "");
2173 return 8;
2174 }
2176 // Vector ideal reg.
2177 const int Matcher::vector_ideal_reg(int size) {
2178 assert(MaxVectorSize == 8 && size == 8, "");
2179 return Op_RegL;
2180 }
2182 const int Matcher::vector_shift_count_ideal_reg(int size) {
2183 fatal("vector shift is not supported");
2184 return Node::NotAMachineReg;
2185 }
2187 // Limits on vector size (number of elements) loaded into vector.
2188 const int Matcher::max_vector_size(const BasicType bt) {
2189 assert(is_java_primitive(bt), "only primitive type vectors");
2190 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2191 }
2193 const int Matcher::min_vector_size(const BasicType bt) {
2194 return max_vector_size(bt); // Same as max.
2195 }
2197 // PPC doesn't support misaligned vectors store/load.
2198 const bool Matcher::misaligned_vectors_ok() {
2199 return false;
2200 }
2202 // PPC AES support not yet implemented
2203 const bool Matcher::pass_original_key_for_aes() {
2204 return false;
2205 }
2207 // RETURNS: whether this branch offset is short enough that a short
2208 // branch can be used.
2209 //
2210 // If the platform does not provide any short branch variants, then
2211 // this method should return `false' for offset 0.
2212 //
2213 // `Compile::Fill_buffer' will decide on basis of this information
2214 // whether to do the pass `Compile::Shorten_branches' at all.
2215 //
2216 // And `Compile::Shorten_branches' will decide on basis of this
2217 // information whether to replace particular branch sites by short
2218 // ones.
2219 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2220 // Is the offset within the range of a ppc64 pc relative branch?
2221 bool b;
2223 const int safety_zone = 3 * BytesPerInstWord;
2224 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2225 29 - 16 + 1 + 2);
2226 return b;
2227 }
2229 const bool Matcher::isSimpleConstant64(jlong value) {
2230 // Probably always true, even if a temp register is required.
2231 return true;
2232 }
2233 /* TODO: PPC port
2234 // Make a new machine dependent decode node (with its operands).
2235 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2236 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2237 "This method is only implemented for unscaled cOops mode so far");
2238 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2239 decode->set_opnd_array(0, new (C) iRegPdstOper());
2240 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2241 return decode;
2242 }
2243 */
2244 // Threshold size for cleararray.
2245 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2247 // false => size gets scaled to BytesPerLong, ok.
2248 const bool Matcher::init_array_count_is_in_bytes = false;
2250 // Use conditional move (CMOVL) on Power7.
2251 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2253 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2254 // fsel doesn't accept a condition register as input, so this would be slightly different.
2255 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2257 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2258 const bool Matcher::require_postalloc_expand = true;
2260 // Should the Matcher clone shifts on addressing modes, expecting them to
2261 // be subsumed into complex addressing expressions or compute them into
2262 // registers? True for Intel but false for most RISCs.
2263 const bool Matcher::clone_shift_expressions = false;
2265 // Do we need to mask the count passed to shift instructions or does
2266 // the cpu only look at the lower 5/6 bits anyway?
2267 // Off, as masks are generated in expand rules where required.
2268 // Constant shift counts are handled in Ideal phase.
2269 const bool Matcher::need_masked_shift_count = false;
2271 // This affects two different things:
2272 // - how Decode nodes are matched
2273 // - how ImplicitNullCheck opportunities are recognized
2274 // If true, the matcher will try to remove all Decodes and match them
2275 // (as operands) into nodes. NullChecks are not prepared to deal with
2276 // Decodes by final_graph_reshaping().
2277 // If false, final_graph_reshaping() forces the decode behind the Cmp
2278 // for a NullCheck. The matcher matches the Decode node into a register.
2279 // Implicit_null_check optimization moves the Decode along with the
2280 // memory operation back up before the NullCheck.
2281 bool Matcher::narrow_oop_use_complex_address() {
2282 // TODO: PPC port if (MatchDecodeNodes) return true;
2283 return false;
2284 }
2286 bool Matcher::narrow_klass_use_complex_address() {
2287 NOT_LP64(ShouldNotCallThis());
2288 assert(UseCompressedClassPointers, "only for compressed klass code");
2289 // TODO: PPC port if (MatchDecodeNodes) return true;
2290 return false;
2291 }
2293 // Is it better to copy float constants, or load them directly from memory?
2294 // Intel can load a float constant from a direct address, requiring no
2295 // extra registers. Most RISCs will have to materialize an address into a
2296 // register first, so they would do better to copy the constant from stack.
2297 const bool Matcher::rematerialize_float_constants = false;
2299 // If CPU can load and store mis-aligned doubles directly then no fixup is
2300 // needed. Else we split the double into 2 integer pieces and move it
2301 // piece-by-piece. Only happens when passing doubles into C code as the
2302 // Java calling convention forces doubles to be aligned.
2303 const bool Matcher::misaligned_doubles_ok = true;
2305 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2306 Unimplemented();
2307 }
2309 // Advertise here if the CPU requires explicit rounding operations
2310 // to implement the UseStrictFP mode.
2311 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2313 // Do floats take an entire double register or just half?
2314 //
2315 // A float occupies a ppc64 double register. For the allocator, a
2316 // ppc64 double register appears as a pair of float registers.
2317 bool Matcher::float_in_double() { return true; }
2319 // Do ints take an entire long register or just half?
2320 // The relevant question is how the int is callee-saved:
2321 // the whole long is written but de-opt'ing will have to extract
2322 // the relevant 32 bits.
2323 const bool Matcher::int_in_long = true;
2325 // Constants for c2c and c calling conventions.
2327 const MachRegisterNumbers iarg_reg[8] = {
2328 R3_num, R4_num, R5_num, R6_num,
2329 R7_num, R8_num, R9_num, R10_num
2330 };
2332 const MachRegisterNumbers farg_reg[13] = {
2333 F1_num, F2_num, F3_num, F4_num,
2334 F5_num, F6_num, F7_num, F8_num,
2335 F9_num, F10_num, F11_num, F12_num,
2336 F13_num
2337 };
2339 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2341 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2343 // Return whether or not this register is ever used as an argument. This
2344 // function is used on startup to build the trampoline stubs in generateOptoStub.
2345 // Registers not mentioned will be killed by the VM call in the trampoline, and
2346 // arguments in those registers not be available to the callee.
2347 bool Matcher::can_be_java_arg(int reg) {
2348 // We return true for all registers contained in iarg_reg[] and
2349 // farg_reg[] and their virtual halves.
2350 // We must include the virtual halves in order to get STDs and LDs
2351 // instead of STWs and LWs in the trampoline stubs.
2353 if ( reg == R3_num || reg == R3_H_num
2354 || reg == R4_num || reg == R4_H_num
2355 || reg == R5_num || reg == R5_H_num
2356 || reg == R6_num || reg == R6_H_num
2357 || reg == R7_num || reg == R7_H_num
2358 || reg == R8_num || reg == R8_H_num
2359 || reg == R9_num || reg == R9_H_num
2360 || reg == R10_num || reg == R10_H_num)
2361 return true;
2363 if ( reg == F1_num || reg == F1_H_num
2364 || reg == F2_num || reg == F2_H_num
2365 || reg == F3_num || reg == F3_H_num
2366 || reg == F4_num || reg == F4_H_num
2367 || reg == F5_num || reg == F5_H_num
2368 || reg == F6_num || reg == F6_H_num
2369 || reg == F7_num || reg == F7_H_num
2370 || reg == F8_num || reg == F8_H_num
2371 || reg == F9_num || reg == F9_H_num
2372 || reg == F10_num || reg == F10_H_num
2373 || reg == F11_num || reg == F11_H_num
2374 || reg == F12_num || reg == F12_H_num
2375 || reg == F13_num || reg == F13_H_num)
2376 return true;
2378 return false;
2379 }
2381 bool Matcher::is_spillable_arg(int reg) {
2382 return can_be_java_arg(reg);
2383 }
2385 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2386 return false;
2387 }
2389 // Register for DIVI projection of divmodI.
2390 RegMask Matcher::divI_proj_mask() {
2391 ShouldNotReachHere();
2392 return RegMask();
2393 }
2395 // Register for MODI projection of divmodI.
2396 RegMask Matcher::modI_proj_mask() {
2397 ShouldNotReachHere();
2398 return RegMask();
2399 }
2401 // Register for DIVL projection of divmodL.
2402 RegMask Matcher::divL_proj_mask() {
2403 ShouldNotReachHere();
2404 return RegMask();
2405 }
2407 // Register for MODL projection of divmodL.
2408 RegMask Matcher::modL_proj_mask() {
2409 ShouldNotReachHere();
2410 return RegMask();
2411 }
2413 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2414 return RegMask();
2415 }
2417 %}
2419 //----------ENCODING BLOCK-----------------------------------------------------
2420 // This block specifies the encoding classes used by the compiler to output
2421 // byte streams. Encoding classes are parameterized macros used by
2422 // Machine Instruction Nodes in order to generate the bit encoding of the
2423 // instruction. Operands specify their base encoding interface with the
2424 // interface keyword. There are currently supported four interfaces,
2425 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2426 // operand to generate a function which returns its register number when
2427 // queried. CONST_INTER causes an operand to generate a function which
2428 // returns the value of the constant when queried. MEMORY_INTER causes an
2429 // operand to generate four functions which return the Base Register, the
2430 // Index Register, the Scale Value, and the Offset Value of the operand when
2431 // queried. COND_INTER causes an operand to generate six functions which
2432 // return the encoding code (ie - encoding bits for the instruction)
2433 // associated with each basic boolean condition for a conditional instruction.
2434 //
2435 // Instructions specify two basic values for encoding. Again, a function
2436 // is available to check if the constant displacement is an oop. They use the
2437 // ins_encode keyword to specify their encoding classes (which must be
2438 // a sequence of enc_class names, and their parameters, specified in
2439 // the encoding block), and they use the
2440 // opcode keyword to specify, in order, their primary, secondary, and
2441 // tertiary opcode. Only the opcode sections which a particular instruction
2442 // needs for encoding need to be specified.
2443 encode %{
2444 enc_class enc_unimplemented %{
2445 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2446 MacroAssembler _masm(&cbuf);
2447 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2448 %}
2450 enc_class enc_untested %{
2451 #ifdef ASSERT
2452 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2453 MacroAssembler _masm(&cbuf);
2454 __ untested("Untested mach node encoding in AD file.");
2455 #else
2456 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2457 #endif
2458 %}
2460 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2461 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2462 MacroAssembler _masm(&cbuf);
2463 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2464 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2465 %}
2467 // Load acquire.
2468 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2469 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2470 MacroAssembler _masm(&cbuf);
2471 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2472 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2473 __ twi_0($dst$$Register);
2474 __ isync();
2475 %}
2477 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2478 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2480 MacroAssembler _masm(&cbuf);
2481 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2482 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2483 %}
2485 // Load acquire.
2486 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2487 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2489 MacroAssembler _masm(&cbuf);
2490 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2491 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2492 __ twi_0($dst$$Register);
2493 __ isync();
2494 %}
2496 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2497 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2499 MacroAssembler _masm(&cbuf);
2500 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2501 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2502 %}
2504 // Load acquire.
2505 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2506 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2508 MacroAssembler _masm(&cbuf);
2509 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2510 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2511 __ twi_0($dst$$Register);
2512 __ isync();
2513 %}
2515 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2516 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2517 MacroAssembler _masm(&cbuf);
2518 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2519 // Operand 'ds' requires 4-alignment.
2520 assert((Idisp & 0x3) == 0, "unaligned offset");
2521 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2522 %}
2524 // Load acquire.
2525 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2526 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2527 MacroAssembler _masm(&cbuf);
2528 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2529 // Operand 'ds' requires 4-alignment.
2530 assert((Idisp & 0x3) == 0, "unaligned offset");
2531 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2532 __ twi_0($dst$$Register);
2533 __ isync();
2534 %}
2536 enc_class enc_lfd(RegF dst, memory mem) %{
2537 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2538 MacroAssembler _masm(&cbuf);
2539 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2540 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2541 %}
2543 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2544 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2546 MacroAssembler _masm(&cbuf);
2547 int toc_offset = 0;
2549 if (!ra_->C->in_scratch_emit_size()) {
2550 address const_toc_addr;
2551 // Create a non-oop constant, no relocation needed.
2552 // If it is an IC, it has a virtual_call_Relocation.
2553 const_toc_addr = __ long_constant((jlong)$src$$constant);
2555 // Get the constant's TOC offset.
2556 toc_offset = __ offset_to_method_toc(const_toc_addr);
2558 // Keep the current instruction offset in mind.
2559 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2560 }
2562 __ ld($dst$$Register, toc_offset, $toc$$Register);
2563 %}
2565 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2566 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2568 MacroAssembler _masm(&cbuf);
2570 if (!ra_->C->in_scratch_emit_size()) {
2571 address const_toc_addr;
2572 // Create a non-oop constant, no relocation needed.
2573 // If it is an IC, it has a virtual_call_Relocation.
2574 const_toc_addr = __ long_constant((jlong)$src$$constant);
2576 // Get the constant's TOC offset.
2577 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2578 // Store the toc offset of the constant.
2579 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2581 // Also keep the current instruction offset in mind.
2582 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2583 }
2585 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2586 %}
2588 %} // encode
2590 source %{
2592 typedef struct {
2593 loadConL_hiNode *_large_hi;
2594 loadConL_loNode *_large_lo;
2595 loadConLNode *_small;
2596 MachNode *_last;
2597 } loadConLNodesTuple;
2599 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2600 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2601 loadConLNodesTuple nodes;
2603 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2604 if (large_constant_pool) {
2605 // Create new nodes.
2606 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2607 loadConL_loNode *m2 = new (C) loadConL_loNode();
2609 // inputs for new nodes
2610 m1->add_req(NULL, toc);
2611 m2->add_req(NULL, m1);
2613 // operands for new nodes
2614 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2615 m1->_opnds[1] = immSrc; // src
2616 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2617 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2618 m2->_opnds[1] = immSrc; // src
2619 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2621 // Initialize ins_attrib TOC fields.
2622 m1->_const_toc_offset = -1;
2623 m2->_const_toc_offset_hi_node = m1;
2625 // Initialize ins_attrib instruction offset.
2626 m1->_cbuf_insts_offset = -1;
2628 // register allocation for new nodes
2629 ra_->set_pair(m1->_idx, reg_second, reg_first);
2630 ra_->set_pair(m2->_idx, reg_second, reg_first);
2632 // Create result.
2633 nodes._large_hi = m1;
2634 nodes._large_lo = m2;
2635 nodes._small = NULL;
2636 nodes._last = nodes._large_lo;
2637 assert(m2->bottom_type()->isa_long(), "must be long");
2638 } else {
2639 loadConLNode *m2 = new (C) loadConLNode();
2641 // inputs for new nodes
2642 m2->add_req(NULL, toc);
2644 // operands for new nodes
2645 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2646 m2->_opnds[1] = immSrc; // src
2647 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2649 // Initialize ins_attrib instruction offset.
2650 m2->_cbuf_insts_offset = -1;
2652 // register allocation for new nodes
2653 ra_->set_pair(m2->_idx, reg_second, reg_first);
2655 // Create result.
2656 nodes._large_hi = NULL;
2657 nodes._large_lo = NULL;
2658 nodes._small = m2;
2659 nodes._last = nodes._small;
2660 assert(m2->bottom_type()->isa_long(), "must be long");
2661 }
2663 return nodes;
2664 }
2666 %} // source
2668 encode %{
2669 // Postalloc expand emitter for loading a long constant from the method's TOC.
2670 // Enc_class needed as consttanttablebase is not supported by postalloc
2671 // expand.
2672 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2673 // Create new nodes.
2674 loadConLNodesTuple loadConLNodes =
2675 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2676 ra_->get_reg_second(this), ra_->get_reg_first(this));
2678 // Push new nodes.
2679 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2680 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2682 // some asserts
2683 assert(nodes->length() >= 1, "must have created at least 1 node");
2684 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2685 %}
2687 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2688 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2690 MacroAssembler _masm(&cbuf);
2691 int toc_offset = 0;
2693 if (!ra_->C->in_scratch_emit_size()) {
2694 intptr_t val = $src$$constant;
2695 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2696 address const_toc_addr;
2697 if (constant_reloc == relocInfo::oop_type) {
2698 // Create an oop constant and a corresponding relocation.
2699 AddressLiteral a = __ allocate_oop_address((jobject)val);
2700 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2701 __ relocate(a.rspec());
2702 } else if (constant_reloc == relocInfo::metadata_type) {
2703 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2704 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2705 __ relocate(a.rspec());
2706 } else {
2707 // Create a non-oop constant, no relocation needed.
2708 const_toc_addr = __ long_constant((jlong)$src$$constant);
2709 }
2711 // Get the constant's TOC offset.
2712 toc_offset = __ offset_to_method_toc(const_toc_addr);
2713 }
2715 __ ld($dst$$Register, toc_offset, $toc$$Register);
2716 %}
2718 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2719 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2721 MacroAssembler _masm(&cbuf);
2722 if (!ra_->C->in_scratch_emit_size()) {
2723 intptr_t val = $src$$constant;
2724 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2725 address const_toc_addr;
2726 if (constant_reloc == relocInfo::oop_type) {
2727 // Create an oop constant and a corresponding relocation.
2728 AddressLiteral a = __ allocate_oop_address((jobject)val);
2729 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2730 __ relocate(a.rspec());
2731 } else if (constant_reloc == relocInfo::metadata_type) {
2732 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2733 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2734 __ relocate(a.rspec());
2735 } else { // non-oop pointers, e.g. card mark base, heap top
2736 // Create a non-oop constant, no relocation needed.
2737 const_toc_addr = __ long_constant((jlong)$src$$constant);
2738 }
2740 // Get the constant's TOC offset.
2741 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2742 // Store the toc offset of the constant.
2743 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2744 }
2746 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2747 %}
2749 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2750 // Enc_class needed as consttanttablebase is not supported by postalloc
2751 // expand.
2752 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2753 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2754 if (large_constant_pool) {
2755 // Create new nodes.
2756 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2757 loadConP_loNode *m2 = new (C) loadConP_loNode();
2759 // inputs for new nodes
2760 m1->add_req(NULL, n_toc);
2761 m2->add_req(NULL, m1);
2763 // operands for new nodes
2764 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2765 m1->_opnds[1] = op_src; // src
2766 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2767 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2768 m2->_opnds[1] = op_src; // src
2769 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2771 // Initialize ins_attrib TOC fields.
2772 m1->_const_toc_offset = -1;
2773 m2->_const_toc_offset_hi_node = m1;
2775 // Register allocation for new nodes.
2776 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2777 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2779 nodes->push(m1);
2780 nodes->push(m2);
2781 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2782 } else {
2783 loadConPNode *m2 = new (C) loadConPNode();
2785 // inputs for new nodes
2786 m2->add_req(NULL, n_toc);
2788 // operands for new nodes
2789 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2790 m2->_opnds[1] = op_src; // src
2791 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2793 // Register allocation for new nodes.
2794 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2796 nodes->push(m2);
2797 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2798 }
2799 %}
2801 // Enc_class needed as consttanttablebase is not supported by postalloc
2802 // expand.
2803 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2804 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2806 MachNode *m2;
2807 if (large_constant_pool) {
2808 m2 = new (C) loadConFCompNode();
2809 } else {
2810 m2 = new (C) loadConFNode();
2811 }
2812 // inputs for new nodes
2813 m2->add_req(NULL, n_toc);
2815 // operands for new nodes
2816 m2->_opnds[0] = op_dst;
2817 m2->_opnds[1] = op_src;
2818 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2820 // register allocation for new nodes
2821 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2822 nodes->push(m2);
2823 %}
2825 // Enc_class needed as consttanttablebase is not supported by postalloc
2826 // expand.
2827 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2828 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2830 MachNode *m2;
2831 if (large_constant_pool) {
2832 m2 = new (C) loadConDCompNode();
2833 } else {
2834 m2 = new (C) loadConDNode();
2835 }
2836 // inputs for new nodes
2837 m2->add_req(NULL, n_toc);
2839 // operands for new nodes
2840 m2->_opnds[0] = op_dst;
2841 m2->_opnds[1] = op_src;
2842 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2844 // register allocation for new nodes
2845 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2846 nodes->push(m2);
2847 %}
2849 enc_class enc_stw(iRegIsrc src, memory mem) %{
2850 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2851 MacroAssembler _masm(&cbuf);
2852 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2853 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2854 %}
2856 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2857 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2858 MacroAssembler _masm(&cbuf);
2859 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2860 // Operand 'ds' requires 4-alignment.
2861 assert((Idisp & 0x3) == 0, "unaligned offset");
2862 __ std($src$$Register, Idisp, $mem$$base$$Register);
2863 %}
2865 enc_class enc_stfs(RegF src, memory mem) %{
2866 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2867 MacroAssembler _masm(&cbuf);
2868 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2869 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2870 %}
2872 enc_class enc_stfd(RegF src, memory mem) %{
2873 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2874 MacroAssembler _masm(&cbuf);
2875 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2876 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2877 %}
2879 // Use release_store for card-marking to ensure that previous
2880 // oop-stores are visible before the card-mark change.
2881 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2882 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2883 // FIXME: Implement this as a cmove and use a fixed condition code
2884 // register which is written on every transition to compiled code,
2885 // e.g. in call-stub and when returning from runtime stubs.
2886 //
2887 // Proposed code sequence for the cmove implementation:
2888 //
2889 // Label skip_release;
2890 // __ beq(CCRfixed, skip_release);
2891 // __ release();
2892 // __ bind(skip_release);
2893 // __ stb(card mark);
2895 MacroAssembler _masm(&cbuf);
2896 Label skip_storestore;
2898 #if 0 // TODO: PPC port
2899 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2900 // StoreStore barrier conditionally.
2901 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2902 __ cmpwi(CCR0, R0, 0);
2903 __ beq_predict_taken(CCR0, skip_storestore);
2904 #endif
2905 __ li(R0, 0);
2906 __ membar(Assembler::StoreStore);
2907 #if 0 // TODO: PPC port
2908 __ bind(skip_storestore);
2909 #endif
2911 // Do the store.
2912 if ($mem$$index == 0) {
2913 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2914 } else {
2915 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2916 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2917 }
2918 %}
2920 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2922 if (VM_Version::has_isel()) {
2923 // use isel instruction with Power 7
2924 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2925 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2926 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2927 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2929 n_compare->add_req(n_region, n_src);
2930 n_compare->_opnds[0] = op_crx;
2931 n_compare->_opnds[1] = op_src;
2932 n_compare->_opnds[2] = new (C) immL16Oper(0);
2934 n_sub_base->add_req(n_region, n_src);
2935 n_sub_base->_opnds[0] = op_dst;
2936 n_sub_base->_opnds[1] = op_src;
2937 n_sub_base->_bottom_type = _bottom_type;
2939 n_shift->add_req(n_region, n_sub_base);
2940 n_shift->_opnds[0] = op_dst;
2941 n_shift->_opnds[1] = op_dst;
2942 n_shift->_bottom_type = _bottom_type;
2944 n_cond_set->add_req(n_region, n_compare, n_shift);
2945 n_cond_set->_opnds[0] = op_dst;
2946 n_cond_set->_opnds[1] = op_crx;
2947 n_cond_set->_opnds[2] = op_dst;
2948 n_cond_set->_bottom_type = _bottom_type;
2950 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2951 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2952 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2953 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2955 nodes->push(n_compare);
2956 nodes->push(n_sub_base);
2957 nodes->push(n_shift);
2958 nodes->push(n_cond_set);
2960 } else {
2961 // before Power 7
2962 moveRegNode *n_move = new (C) moveRegNode();
2963 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2964 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2965 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2967 n_move->add_req(n_region, n_src);
2968 n_move->_opnds[0] = op_dst;
2969 n_move->_opnds[1] = op_src;
2970 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2972 n_compare->add_req(n_region, n_src);
2973 n_compare->add_prec(n_move);
2975 n_compare->_opnds[0] = op_crx;
2976 n_compare->_opnds[1] = op_src;
2977 n_compare->_opnds[2] = new (C) immL16Oper(0);
2979 n_sub_base->add_req(n_region, n_compare, n_src);
2980 n_sub_base->_opnds[0] = op_dst;
2981 n_sub_base->_opnds[1] = op_crx;
2982 n_sub_base->_opnds[2] = op_src;
2983 n_sub_base->_bottom_type = _bottom_type;
2985 n_shift->add_req(n_region, n_sub_base);
2986 n_shift->_opnds[0] = op_dst;
2987 n_shift->_opnds[1] = op_dst;
2988 n_shift->_bottom_type = _bottom_type;
2990 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2991 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2992 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2993 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2995 nodes->push(n_move);
2996 nodes->push(n_compare);
2997 nodes->push(n_sub_base);
2998 nodes->push(n_shift);
2999 }
3001 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3002 %}
3004 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3006 encodeP_subNode *n1 = new (C) encodeP_subNode();
3007 n1->add_req(n_region, n_src);
3008 n1->_opnds[0] = op_dst;
3009 n1->_opnds[1] = op_src;
3010 n1->_bottom_type = _bottom_type;
3012 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
3013 n2->add_req(n_region, n1);
3014 n2->_opnds[0] = op_dst;
3015 n2->_opnds[1] = op_dst;
3016 n2->_bottom_type = _bottom_type;
3017 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3018 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3020 nodes->push(n1);
3021 nodes->push(n2);
3022 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3023 %}
3025 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3026 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
3027 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
3029 n_compare->add_req(n_region, n_src);
3030 n_compare->_opnds[0] = op_crx;
3031 n_compare->_opnds[1] = op_src;
3032 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
3034 n_shift->add_req(n_region, n_src);
3035 n_shift->_opnds[0] = op_dst;
3036 n_shift->_opnds[1] = op_src;
3037 n_shift->_bottom_type = _bottom_type;
3039 if (VM_Version::has_isel()) {
3040 // use isel instruction with Power 7
3042 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
3043 n_add_base->add_req(n_region, n_shift);
3044 n_add_base->_opnds[0] = op_dst;
3045 n_add_base->_opnds[1] = op_dst;
3046 n_add_base->_bottom_type = _bottom_type;
3048 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3049 n_cond_set->add_req(n_region, n_compare, n_add_base);
3050 n_cond_set->_opnds[0] = op_dst;
3051 n_cond_set->_opnds[1] = op_crx;
3052 n_cond_set->_opnds[2] = op_dst;
3053 n_cond_set->_bottom_type = _bottom_type;
3055 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3056 ra_->set_oop(n_cond_set, true);
3058 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3059 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3060 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3061 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3063 nodes->push(n_compare);
3064 nodes->push(n_shift);
3065 nodes->push(n_add_base);
3066 nodes->push(n_cond_set);
3068 } else {
3069 // before Power 7
3070 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3072 n_add_base->add_req(n_region, n_compare, n_shift);
3073 n_add_base->_opnds[0] = op_dst;
3074 n_add_base->_opnds[1] = op_crx;
3075 n_add_base->_opnds[2] = op_dst;
3076 n_add_base->_bottom_type = _bottom_type;
3078 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3079 ra_->set_oop(n_add_base, true);
3081 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3082 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3083 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3085 nodes->push(n_compare);
3086 nodes->push(n_shift);
3087 nodes->push(n_add_base);
3088 }
3089 %}
3091 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3092 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3093 n1->add_req(n_region, n_src);
3094 n1->_opnds[0] = op_dst;
3095 n1->_opnds[1] = op_src;
3096 n1->_bottom_type = _bottom_type;
3098 decodeN_addNode *n2 = new (C) decodeN_addNode();
3099 n2->add_req(n_region, n1);
3100 n2->_opnds[0] = op_dst;
3101 n2->_opnds[1] = op_dst;
3102 n2->_bottom_type = _bottom_type;
3103 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3104 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3106 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3107 ra_->set_oop(n2, true);
3109 nodes->push(n1);
3110 nodes->push(n2);
3111 %}
3113 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3114 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3116 MacroAssembler _masm(&cbuf);
3117 int cc = $cmp$$cmpcode;
3118 int flags_reg = $crx$$reg;
3119 Label done;
3120 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3121 // Branch if not (cmp crx).
3122 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3123 __ mr($dst$$Register, $src$$Register);
3124 // TODO PPC port __ endgroup_if_needed(_size == 12);
3125 __ bind(done);
3126 %}
3128 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3129 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3131 MacroAssembler _masm(&cbuf);
3132 Label done;
3133 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3134 // Branch if not (cmp crx).
3135 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3136 __ li($dst$$Register, $src$$constant);
3137 // TODO PPC port __ endgroup_if_needed(_size == 12);
3138 __ bind(done);
3139 %}
3141 // New atomics.
3142 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3143 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3145 MacroAssembler _masm(&cbuf);
3146 Register Rtmp = R0;
3147 Register Rres = $res$$Register;
3148 Register Rsrc = $src$$Register;
3149 Register Rptr = $mem_ptr$$Register;
3150 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3151 Register Rold = RegCollision ? Rtmp : Rres;
3153 Label Lretry;
3154 __ bind(Lretry);
3155 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3156 __ add(Rtmp, Rsrc, Rold);
3157 __ stwcx_(Rtmp, Rptr);
3158 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3159 __ bne_predict_not_taken(CCR0, Lretry);
3160 } else {
3161 __ bne( CCR0, Lretry);
3162 }
3163 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3164 __ fence();
3165 %}
3167 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3168 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3170 MacroAssembler _masm(&cbuf);
3171 Register Rtmp = R0;
3172 Register Rres = $res$$Register;
3173 Register Rsrc = $src$$Register;
3174 Register Rptr = $mem_ptr$$Register;
3175 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3176 Register Rold = RegCollision ? Rtmp : Rres;
3178 Label Lretry;
3179 __ bind(Lretry);
3180 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3181 __ add(Rtmp, Rsrc, Rold);
3182 __ stdcx_(Rtmp, Rptr);
3183 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3184 __ bne_predict_not_taken(CCR0, Lretry);
3185 } else {
3186 __ bne( CCR0, Lretry);
3187 }
3188 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3189 __ fence();
3190 %}
3192 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3193 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3195 MacroAssembler _masm(&cbuf);
3196 Register Rtmp = R0;
3197 Register Rres = $res$$Register;
3198 Register Rsrc = $src$$Register;
3199 Register Rptr = $mem_ptr$$Register;
3200 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3201 Register Rold = RegCollision ? Rtmp : Rres;
3203 Label Lretry;
3204 __ bind(Lretry);
3205 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3206 __ stwcx_(Rsrc, Rptr);
3207 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3208 __ bne_predict_not_taken(CCR0, Lretry);
3209 } else {
3210 __ bne( CCR0, Lretry);
3211 }
3212 if (RegCollision) __ mr(Rres, Rtmp);
3213 __ fence();
3214 %}
3216 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3217 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3219 MacroAssembler _masm(&cbuf);
3220 Register Rtmp = R0;
3221 Register Rres = $res$$Register;
3222 Register Rsrc = $src$$Register;
3223 Register Rptr = $mem_ptr$$Register;
3224 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3225 Register Rold = RegCollision ? Rtmp : Rres;
3227 Label Lretry;
3228 __ bind(Lretry);
3229 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3230 __ stdcx_(Rsrc, Rptr);
3231 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3232 __ bne_predict_not_taken(CCR0, Lretry);
3233 } else {
3234 __ bne( CCR0, Lretry);
3235 }
3236 if (RegCollision) __ mr(Rres, Rtmp);
3237 __ fence();
3238 %}
3240 // This enc_class is needed so that scheduler gets proper
3241 // input mapping for latency computation.
3242 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3243 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3244 MacroAssembler _masm(&cbuf);
3245 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3246 %}
3248 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3249 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3251 MacroAssembler _masm(&cbuf);
3253 Label done;
3254 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3255 __ li($dst$$Register, $zero$$constant);
3256 __ beq($crx$$CondRegister, done);
3257 __ li($dst$$Register, $notzero$$constant);
3258 __ bind(done);
3259 %}
3261 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3262 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3264 MacroAssembler _masm(&cbuf);
3266 Label done;
3267 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3268 __ li($dst$$Register, $zero$$constant);
3269 __ beq($crx$$CondRegister, done);
3270 __ li($dst$$Register, $notzero$$constant);
3271 __ bind(done);
3272 %}
3274 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3275 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3277 MacroAssembler _masm(&cbuf);
3278 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3279 Label done;
3280 __ bso($crx$$CondRegister, done);
3281 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3282 // TODO PPC port __ endgroup_if_needed(_size == 12);
3283 __ bind(done);
3284 %}
3286 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3287 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3289 MacroAssembler _masm(&cbuf);
3290 Label d; // dummy
3291 __ bind(d);
3292 Label* p = ($lbl$$label);
3293 // `p' is `NULL' when this encoding class is used only to
3294 // determine the size of the encoded instruction.
3295 Label& l = (NULL == p)? d : *(p);
3296 int cc = $cmp$$cmpcode;
3297 int flags_reg = $crx$$reg;
3298 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3299 int bhint = Assembler::bhintNoHint;
3301 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3302 if (_prob <= PROB_NEVER) {
3303 bhint = Assembler::bhintIsNotTaken;
3304 } else if (_prob >= PROB_ALWAYS) {
3305 bhint = Assembler::bhintIsTaken;
3306 }
3307 }
3309 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3310 cc_to_biint(cc, flags_reg),
3311 l);
3312 %}
3314 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3315 // The scheduler doesn't know about branch shortening, so we set the opcode
3316 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3317 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3319 MacroAssembler _masm(&cbuf);
3320 Label d; // dummy
3321 __ bind(d);
3322 Label* p = ($lbl$$label);
3323 // `p' is `NULL' when this encoding class is used only to
3324 // determine the size of the encoded instruction.
3325 Label& l = (NULL == p)? d : *(p);
3326 int cc = $cmp$$cmpcode;
3327 int flags_reg = $crx$$reg;
3328 int bhint = Assembler::bhintNoHint;
3330 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3331 if (_prob <= PROB_NEVER) {
3332 bhint = Assembler::bhintIsNotTaken;
3333 } else if (_prob >= PROB_ALWAYS) {
3334 bhint = Assembler::bhintIsTaken;
3335 }
3336 }
3338 // Tell the conditional far branch to optimize itself when being relocated.
3339 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3340 cc_to_biint(cc, flags_reg),
3341 l,
3342 MacroAssembler::bc_far_optimize_on_relocate);
3343 %}
3345 // Branch used with Power6 scheduling (can be shortened without changing the node).
3346 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3347 // The scheduler doesn't know about branch shortening, so we set the opcode
3348 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3349 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3351 MacroAssembler _masm(&cbuf);
3352 Label d; // dummy
3353 __ bind(d);
3354 Label* p = ($lbl$$label);
3355 // `p' is `NULL' when this encoding class is used only to
3356 // determine the size of the encoded instruction.
3357 Label& l = (NULL == p)? d : *(p);
3358 int cc = $cmp$$cmpcode;
3359 int flags_reg = $crx$$reg;
3360 int bhint = Assembler::bhintNoHint;
3362 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3363 if (_prob <= PROB_NEVER) {
3364 bhint = Assembler::bhintIsNotTaken;
3365 } else if (_prob >= PROB_ALWAYS) {
3366 bhint = Assembler::bhintIsTaken;
3367 }
3368 }
3370 #if 0 // TODO: PPC port
3371 if (_size == 8) {
3372 // Tell the conditional far branch to optimize itself when being relocated.
3373 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3374 cc_to_biint(cc, flags_reg),
3375 l,
3376 MacroAssembler::bc_far_optimize_on_relocate);
3377 } else {
3378 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3379 cc_to_biint(cc, flags_reg),
3380 l);
3381 }
3382 #endif
3383 Unimplemented();
3384 %}
3386 // Postalloc expand emitter for loading a replicatef float constant from
3387 // the method's TOC.
3388 // Enc_class needed as consttanttablebase is not supported by postalloc
3389 // expand.
3390 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3391 // Create new nodes.
3393 // Make an operand with the bit pattern to load as float.
3394 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3396 loadConLNodesTuple loadConLNodes =
3397 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3398 ra_->get_reg_second(this), ra_->get_reg_first(this));
3400 // Push new nodes.
3401 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3402 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3404 assert(nodes->length() >= 1, "must have created at least 1 node");
3405 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3406 %}
3408 // This enc_class is needed so that scheduler gets proper
3409 // input mapping for latency computation.
3410 enc_class enc_poll(immI dst, iRegLdst poll) %{
3411 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3412 // Fake operand dst needed for PPC scheduler.
3413 assert($dst$$constant == 0x0, "dst must be 0x0");
3415 MacroAssembler _masm(&cbuf);
3416 // Mark the code position where the load from the safepoint
3417 // polling page was emitted as relocInfo::poll_type.
3418 __ relocate(relocInfo::poll_type);
3419 __ load_from_polling_page($poll$$Register);
3420 %}
3422 // A Java static call or a runtime call.
3423 //
3424 // Branch-and-link relative to a trampoline.
3425 // The trampoline loads the target address and does a long branch to there.
3426 // In case we call java, the trampoline branches to a interpreter_stub
3427 // which loads the inline cache and the real call target from the constant pool.
3428 //
3429 // This basically looks like this:
3430 //
3431 // >>>> consts -+ -+
3432 // | |- offset1
3433 // [call target1] | <-+
3434 // [IC cache] |- offset2
3435 // [call target2] <--+
3436 //
3437 // <<<< consts
3438 // >>>> insts
3439 //
3440 // bl offset16 -+ -+ ??? // How many bits available?
3441 // | |
3442 // <<<< insts | |
3443 // >>>> stubs | |
3444 // | |- trampoline_stub_Reloc
3445 // trampoline stub: | <-+
3446 // r2 = toc |
3447 // r2 = [r2 + offset1] | // Load call target1 from const section
3448 // mtctr r2 |
3449 // bctr |- static_stub_Reloc
3450 // comp_to_interp_stub: <---+
3451 // r1 = toc
3452 // ICreg = [r1 + IC_offset] // Load IC from const section
3453 // r1 = [r1 + offset2] // Load call target2 from const section
3454 // mtctr r1
3455 // bctr
3456 //
3457 // <<<< stubs
3458 //
3459 // The call instruction in the code either
3460 // - Branches directly to a compiled method if the offset is encodable in instruction.
3461 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3462 // - Branches to the compiled_to_interp stub if the target is interpreted.
3463 //
3464 // Further there are three relocations from the loads to the constants in
3465 // the constant section.
3466 //
3467 // Usage of r1 and r2 in the stubs allows to distinguish them.
3468 enc_class enc_java_static_call(method meth) %{
3469 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3471 MacroAssembler _masm(&cbuf);
3472 address entry_point = (address)$meth$$method;
3474 if (!_method) {
3475 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3476 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3477 } else {
3478 // Remember the offset not the address.
3479 const int start_offset = __ offset();
3480 // The trampoline stub.
3481 if (!Compile::current()->in_scratch_emit_size()) {
3482 // No entry point given, use the current pc.
3483 // Make sure branch fits into
3484 if (entry_point == 0) entry_point = __ pc();
3486 // Put the entry point as a constant into the constant pool.
3487 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3488 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3490 // Emit the trampoline stub which will be related to the branch-and-link below.
3491 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3492 if (Compile::current()->env()->failing()) { return; } // Code cache may be full.
3493 __ relocate(_optimized_virtual ?
3494 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3495 }
3497 // The real call.
3498 // Note: At this point we do not have the address of the trampoline
3499 // stub, and the entry point might be too far away for bl, so __ pc()
3500 // serves as dummy and the bl will be patched later.
3501 cbuf.set_insts_mark();
3502 __ bl(__ pc()); // Emits a relocation.
3504 // The stub for call to interpreter.
3505 CompiledStaticCall::emit_to_interp_stub(cbuf);
3506 }
3507 %}
3509 // Emit a method handle call.
3510 //
3511 // Method handle calls from compiled to compiled are going thru a
3512 // c2i -> i2c adapter, extending the frame for their arguments. The
3513 // caller however, returns directly to the compiled callee, that has
3514 // to cope with the extended frame. We restore the original frame by
3515 // loading the callers sp and adding the calculated framesize.
3516 enc_class enc_java_handle_call(method meth) %{
3517 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3519 MacroAssembler _masm(&cbuf);
3520 address entry_point = (address)$meth$$method;
3522 // Remember the offset not the address.
3523 const int start_offset = __ offset();
3524 // The trampoline stub.
3525 if (!ra_->C->in_scratch_emit_size()) {
3526 // No entry point given, use the current pc.
3527 // Make sure branch fits into
3528 if (entry_point == 0) entry_point = __ pc();
3530 // Put the entry point as a constant into the constant pool.
3531 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3532 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3534 // Emit the trampoline stub which will be related to the branch-and-link below.
3535 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3536 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3537 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3538 __ relocate(relocInfo::opt_virtual_call_type);
3539 }
3541 // The real call.
3542 // Note: At this point we do not have the address of the trampoline
3543 // stub, and the entry point might be too far away for bl, so __ pc()
3544 // serves as dummy and the bl will be patched later.
3545 cbuf.set_insts_mark();
3546 __ bl(__ pc()); // Emits a relocation.
3548 assert(_method, "execute next statement conditionally");
3549 // The stub for call to interpreter.
3550 CompiledStaticCall::emit_to_interp_stub(cbuf);
3552 // Restore original sp.
3553 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3554 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3555 unsigned int bytes = (unsigned int)framesize;
3556 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3557 if (Assembler::is_simm(-offset, 16)) {
3558 __ addi(R1_SP, R11_scratch1, -offset);
3559 } else {
3560 __ load_const_optimized(R12_scratch2, -offset);
3561 __ add(R1_SP, R11_scratch1, R12_scratch2);
3562 }
3563 #ifdef ASSERT
3564 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3565 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3566 __ asm_assert_eq("backlink changed", 0x8000);
3567 #endif
3568 // If fails should store backlink before unextending.
3570 if (ra_->C->env()->failing()) {
3571 return;
3572 }
3573 %}
3575 // Second node of expanded dynamic call - the call.
3576 enc_class enc_java_dynamic_call_sched(method meth) %{
3577 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3579 MacroAssembler _masm(&cbuf);
3581 if (!ra_->C->in_scratch_emit_size()) {
3582 // Create a call trampoline stub for the given method.
3583 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3584 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3585 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3586 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3587 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3589 // Build relocation at call site with ic position as data.
3590 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3591 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3592 "must have one, but can't have both");
3593 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3594 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3595 "must contain instruction offset");
3596 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3597 ? _load_ic_hi_node->_cbuf_insts_offset
3598 : _load_ic_node->_cbuf_insts_offset;
3599 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3600 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3601 "should be load from TOC");
3603 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3604 }
3606 // At this point I do not have the address of the trampoline stub,
3607 // and the entry point might be too far away for bl. Pc() serves
3608 // as dummy and bl will be patched later.
3609 __ bl((address) __ pc());
3610 %}
3612 // postalloc expand emitter for virtual calls.
3613 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3615 // Create the nodes for loading the IC from the TOC.
3616 loadConLNodesTuple loadConLNodes_IC =
3617 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3618 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3620 // Create the call node.
3621 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3622 call->_method_handle_invoke = _method_handle_invoke;
3623 call->_vtable_index = _vtable_index;
3624 call->_method = _method;
3625 call->_bci = _bci;
3626 call->_optimized_virtual = _optimized_virtual;
3627 call->_tf = _tf;
3628 call->_entry_point = _entry_point;
3629 call->_cnt = _cnt;
3630 call->_argsize = _argsize;
3631 call->_oop_map = _oop_map;
3632 call->_jvms = _jvms;
3633 call->_jvmadj = _jvmadj;
3634 call->_in_rms = _in_rms;
3635 call->_nesting = _nesting;
3637 // New call needs all inputs of old call.
3638 // Req...
3639 for (uint i = 0; i < req(); ++i) {
3640 // The expanded node does not need toc any more.
3641 // Add the inline cache constant here instead. This expresses the
3642 // register of the inline cache must be live at the call.
3643 // Else we would have to adapt JVMState by -1.
3644 if (i == mach_constant_base_node_input()) {
3645 call->add_req(loadConLNodes_IC._last);
3646 } else {
3647 call->add_req(in(i));
3648 }
3649 }
3650 // ...as well as prec
3651 for (uint i = req(); i < len(); ++i) {
3652 call->add_prec(in(i));
3653 }
3655 // Remember nodes loading the inline cache into r19.
3656 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3657 call->_load_ic_node = loadConLNodes_IC._small;
3659 // Operands for new nodes.
3660 call->_opnds[0] = _opnds[0];
3661 call->_opnds[1] = _opnds[1];
3663 // Only the inline cache is associated with a register.
3664 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3666 // Push new nodes.
3667 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3668 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3669 nodes->push(call);
3670 %}
3672 // Compound version of call dynamic
3673 // Toc is only passed so that it can be used in ins_encode statement.
3674 // In the code we have to use $constanttablebase.
3675 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3676 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3677 MacroAssembler _masm(&cbuf);
3678 int start_offset = __ offset();
3680 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3681 #if 0
3682 int vtable_index = this->_vtable_index;
3683 if (_vtable_index < 0) {
3684 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3685 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3686 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3688 // Virtual call relocation will point to ic load.
3689 address virtual_call_meta_addr = __ pc();
3690 // Load a clear inline cache.
3691 AddressLiteral empty_ic((address) Universe::non_oop_word());
3692 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3693 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3694 // to determine who we intended to call.
3695 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3696 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3697 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3698 "Fix constant in ret_addr_offset()");
3699 } else {
3700 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3701 // Go thru the vtable. Get receiver klass. Receiver already
3702 // checked for non-null. If we'll go thru a C2I adapter, the
3703 // interpreter expects method in R19_method.
3705 __ load_klass(R11_scratch1, R3);
3707 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3708 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3709 __ li(R19_method, v_off);
3710 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3711 // NOTE: for vtable dispatches, the vtable entry will never be
3712 // null. However it may very well end up in handle_wrong_method
3713 // if the method is abstract for the particular class.
3714 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3715 // Call target. Either compiled code or C2I adapter.
3716 __ mtctr(R11_scratch1);
3717 __ bctrl();
3718 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3719 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3720 }
3721 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3722 "Fix constant in ret_addr_offset()");
3723 }
3724 #endif
3725 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3726 %}
3728 // a runtime call
3729 enc_class enc_java_to_runtime_call (method meth) %{
3730 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3732 MacroAssembler _masm(&cbuf);
3733 const address start_pc = __ pc();
3735 #if defined(ABI_ELFv2)
3736 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3737 __ call_c(entry, relocInfo::runtime_call_type);
3738 #else
3739 // The function we're going to call.
3740 FunctionDescriptor fdtemp;
3741 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3743 Register Rtoc = R12_scratch2;
3744 // Calculate the method's TOC.
3745 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3746 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3747 // pool entries; call_c_using_toc will optimize the call.
3748 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3749 #endif
3751 // Check the ret_addr_offset.
3752 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3753 "Fix constant in ret_addr_offset()");
3754 %}
3756 // Move to ctr for leaf call.
3757 // This enc_class is needed so that scheduler gets proper
3758 // input mapping for latency computation.
3759 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3760 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3761 MacroAssembler _masm(&cbuf);
3762 __ mtctr($src$$Register);
3763 %}
3765 // Postalloc expand emitter for runtime leaf calls.
3766 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3767 loadConLNodesTuple loadConLNodes_Entry;
3768 #if defined(ABI_ELFv2)
3769 jlong entry_address = (jlong) this->entry_point();
3770 assert(entry_address, "need address here");
3771 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3772 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3773 #else
3774 // Get the struct that describes the function we are about to call.
3775 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3776 assert(fd, "need fd here");
3777 jlong entry_address = (jlong) fd->entry();
3778 // new nodes
3779 loadConLNodesTuple loadConLNodes_Env;
3780 loadConLNodesTuple loadConLNodes_Toc;
3782 // Create nodes and operands for loading the entry point.
3783 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3784 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3787 // Create nodes and operands for loading the env pointer.
3788 if (fd->env() != NULL) {
3789 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3790 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3791 } else {
3792 loadConLNodes_Env._large_hi = NULL;
3793 loadConLNodes_Env._large_lo = NULL;
3794 loadConLNodes_Env._small = NULL;
3795 loadConLNodes_Env._last = new (C) loadConL16Node();
3796 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3797 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3798 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3799 }
3801 // Create nodes and operands for loading the Toc point.
3802 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3803 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3804 #endif // ABI_ELFv2
3805 // mtctr node
3806 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode();
3808 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3809 mtctr->add_req(0, loadConLNodes_Entry._last);
3811 mtctr->_opnds[0] = new (C) iRegLdstOper();
3812 mtctr->_opnds[1] = new (C) iRegLdstOper();
3814 // call node
3815 MachCallLeafNode *call = new (C) CallLeafDirectNode();
3817 call->_opnds[0] = _opnds[0];
3818 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later.
3820 // Make the new call node look like the old one.
3821 call->_name = _name;
3822 call->_tf = _tf;
3823 call->_entry_point = _entry_point;
3824 call->_cnt = _cnt;
3825 call->_argsize = _argsize;
3826 call->_oop_map = _oop_map;
3827 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3828 call->_jvms = NULL;
3829 call->_jvmadj = _jvmadj;
3830 call->_in_rms = _in_rms;
3831 call->_nesting = _nesting;
3834 // New call needs all inputs of old call.
3835 // Req...
3836 for (uint i = 0; i < req(); ++i) {
3837 if (i != mach_constant_base_node_input()) {
3838 call->add_req(in(i));
3839 }
3840 }
3842 // These must be reqired edges, as the registers are live up to
3843 // the call. Else the constants are handled as kills.
3844 call->add_req(mtctr);
3845 #if !defined(ABI_ELFv2)
3846 call->add_req(loadConLNodes_Env._last);
3847 call->add_req(loadConLNodes_Toc._last);
3848 #endif
3850 // ...as well as prec
3851 for (uint i = req(); i < len(); ++i) {
3852 call->add_prec(in(i));
3853 }
3855 // registers
3856 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3858 // Insert the new nodes.
3859 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3860 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3861 #if !defined(ABI_ELFv2)
3862 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3863 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3864 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3865 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3866 #endif
3867 nodes->push(mtctr);
3868 nodes->push(call);
3869 %}
3870 %}
3872 //----------FRAME--------------------------------------------------------------
3873 // Definition of frame structure and management information.
3875 frame %{
3876 // What direction does stack grow in (assumed to be same for native & Java).
3877 stack_direction(TOWARDS_LOW);
3879 // These two registers define part of the calling convention between
3880 // compiled code and the interpreter.
3882 // Inline Cache Register or method for I2C.
3883 inline_cache_reg(R19); // R19_method
3885 // Method Oop Register when calling interpreter.
3886 interpreter_method_oop_reg(R19); // R19_method
3888 // Optional: name the operand used by cisc-spilling to access
3889 // [stack_pointer + offset].
3890 cisc_spilling_operand_name(indOffset);
3892 // Number of stack slots consumed by a Monitor enter.
3893 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3895 // Compiled code's Frame Pointer.
3896 frame_pointer(R1); // R1_SP
3898 // Interpreter stores its frame pointer in a register which is
3899 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3900 // interpreted java to compiled java.
3901 //
3902 // R14_state holds pointer to caller's cInterpreter.
3903 interpreter_frame_pointer(R14); // R14_state
3905 stack_alignment(frame::alignment_in_bytes);
3907 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3909 // Number of outgoing stack slots killed above the
3910 // out_preserve_stack_slots for calls to C. Supports the var-args
3911 // backing area for register parms.
3912 //
3913 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3915 // The after-PROLOG location of the return address. Location of
3916 // return address specifies a type (REG or STACK) and a number
3917 // representing the register number (i.e. - use a register name) or
3918 // stack slot.
3919 //
3920 // A: Link register is stored in stack slot ...
3921 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3922 // J: Therefore, we make sure that the link register is also in R11_scratch1
3923 // at the end of the prolog.
3924 // B: We use R20, now.
3925 //return_addr(REG R20);
3927 // G: After reading the comments made by all the luminaries on their
3928 // failure to tell the compiler where the return address really is,
3929 // I hardly dare to try myself. However, I'm convinced it's in slot
3930 // 4 what apparently works and saves us some spills.
3931 return_addr(STACK 4);
3933 // This is the body of the function
3934 //
3935 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3936 // uint length, // length of array
3937 // bool is_outgoing)
3938 //
3939 // The `sig' array is to be updated. sig[j] represents the location
3940 // of the j-th argument, either a register or a stack slot.
3942 // Comment taken from i486.ad:
3943 // Body of function which returns an integer array locating
3944 // arguments either in registers or in stack slots. Passed an array
3945 // of ideal registers called "sig" and a "length" count. Stack-slot
3946 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3947 // arguments for a CALLEE. Incoming stack arguments are
3948 // automatically biased by the preserve_stack_slots field above.
3949 calling_convention %{
3950 // No difference between ingoing/outgoing. Just pass false.
3951 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3952 %}
3954 // Comment taken from i486.ad:
3955 // Body of function which returns an integer array locating
3956 // arguments either in registers or in stack slots. Passed an array
3957 // of ideal registers called "sig" and a "length" count. Stack-slot
3958 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3959 // arguments for a CALLEE. Incoming stack arguments are
3960 // automatically biased by the preserve_stack_slots field above.
3961 c_calling_convention %{
3962 // This is obviously always outgoing.
3963 // C argument in register AND stack slot.
3964 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3965 %}
3967 // Location of native (C/C++) and interpreter return values. This
3968 // is specified to be the same as Java. In the 32-bit VM, long
3969 // values are actually returned from native calls in O0:O1 and
3970 // returned to the interpreter in I0:I1. The copying to and from
3971 // the register pairs is done by the appropriate call and epilog
3972 // opcodes. This simplifies the register allocator.
3973 c_return_value %{
3974 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3975 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3976 "only return normal values");
3977 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3978 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3979 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3980 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3981 %}
3983 // Location of compiled Java return values. Same as C
3984 return_value %{
3985 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3986 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3987 "only return normal values");
3988 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3989 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3990 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3991 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3992 %}
3993 %}
3996 //----------ATTRIBUTES---------------------------------------------------------
3998 //----------Operand Attributes-------------------------------------------------
3999 op_attrib op_cost(1); // Required cost attribute.
4001 //----------Instruction Attributes---------------------------------------------
4003 // Cost attribute. required.
4004 ins_attrib ins_cost(DEFAULT_COST);
4006 // Is this instruction a non-matching short branch variant of some
4007 // long branch? Not required.
4008 ins_attrib ins_short_branch(0);
4010 ins_attrib ins_is_TrapBasedCheckNode(true);
4012 // Number of constants.
4013 // This instruction uses the given number of constants
4014 // (optional attribute).
4015 // This is needed to determine in time whether the constant pool will
4016 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4017 // is determined. It's also used to compute the constant pool size
4018 // in Output().
4019 ins_attrib ins_num_consts(0);
4021 // Required alignment attribute (must be a power of 2) specifies the
4022 // alignment that some part of the instruction (not necessarily the
4023 // start) requires. If > 1, a compute_padding() function must be
4024 // provided for the instruction.
4025 ins_attrib ins_alignment(1);
4027 // Enforce/prohibit rematerializations.
4028 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4029 // then rematerialization of that instruction is prohibited and the
4030 // instruction's value will be spilled if necessary.
4031 // Causes that MachNode::rematerialize() returns false.
4032 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4033 // then rematerialization should be enforced and a copy of the instruction
4034 // should be inserted if possible; rematerialization is not guaranteed.
4035 // Note: this may result in rematerializations in front of every use.
4036 // Causes that MachNode::rematerialize() can return true.
4037 // (optional attribute)
4038 ins_attrib ins_cannot_rematerialize(false);
4039 ins_attrib ins_should_rematerialize(false);
4041 // Instruction has variable size depending on alignment.
4042 ins_attrib ins_variable_size_depending_on_alignment(false);
4044 // Instruction is a nop.
4045 ins_attrib ins_is_nop(false);
4047 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4048 ins_attrib ins_use_mach_if_fast_lock_node(false);
4050 // Field for the toc offset of a constant.
4051 //
4052 // This is needed if the toc offset is not encodable as an immediate in
4053 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4054 // added to the toc, and from this a load with immediate is performed.
4055 // With postalloc expand, we get two nodes that require the same offset
4056 // but which don't know about each other. The offset is only known
4057 // when the constant is added to the constant pool during emitting.
4058 // It is generated in the 'hi'-node adding the upper bits, and saved
4059 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4060 // the offset from there when it gets encoded.
4061 ins_attrib ins_field_const_toc_offset(0);
4062 ins_attrib ins_field_const_toc_offset_hi_node(0);
4064 // A field that can hold the instructions offset in the code buffer.
4065 // Set in the nodes emitter.
4066 ins_attrib ins_field_cbuf_insts_offset(-1);
4068 // Fields for referencing a call's load-IC-node.
4069 // If the toc offset can not be encoded as an immediate in a load, we
4070 // use two nodes.
4071 ins_attrib ins_field_load_ic_hi_node(0);
4072 ins_attrib ins_field_load_ic_node(0);
4074 //----------OPERANDS-----------------------------------------------------------
4075 // Operand definitions must precede instruction definitions for correct
4076 // parsing in the ADLC because operands constitute user defined types
4077 // which are used in instruction definitions.
4078 //
4079 // Formats are generated automatically for constants and base registers.
4081 //----------Simple Operands----------------------------------------------------
4082 // Immediate Operands
4084 // Integer Immediate: 32-bit
4085 operand immI() %{
4086 match(ConI);
4087 op_cost(40);
4088 format %{ %}
4089 interface(CONST_INTER);
4090 %}
4092 operand immI8() %{
4093 predicate(Assembler::is_simm(n->get_int(), 8));
4094 op_cost(0);
4095 match(ConI);
4096 format %{ %}
4097 interface(CONST_INTER);
4098 %}
4100 // Integer Immediate: 16-bit
4101 operand immI16() %{
4102 predicate(Assembler::is_simm(n->get_int(), 16));
4103 op_cost(0);
4104 match(ConI);
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4109 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4110 operand immIhi16() %{
4111 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4112 match(ConI);
4113 op_cost(0);
4114 format %{ %}
4115 interface(CONST_INTER);
4116 %}
4118 operand immInegpow2() %{
4119 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4120 match(ConI);
4121 op_cost(0);
4122 format %{ %}
4123 interface(CONST_INTER);
4124 %}
4126 operand immIpow2minus1() %{
4127 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4128 match(ConI);
4129 op_cost(0);
4130 format %{ %}
4131 interface(CONST_INTER);
4132 %}
4134 operand immIpowerOf2() %{
4135 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4136 match(ConI);
4137 op_cost(0);
4138 format %{ %}
4139 interface(CONST_INTER);
4140 %}
4142 // Unsigned Integer Immediate: the values 0-31
4143 operand uimmI5() %{
4144 predicate(Assembler::is_uimm(n->get_int(), 5));
4145 match(ConI);
4146 op_cost(0);
4147 format %{ %}
4148 interface(CONST_INTER);
4149 %}
4151 // Unsigned Integer Immediate: 6-bit
4152 operand uimmI6() %{
4153 predicate(Assembler::is_uimm(n->get_int(), 6));
4154 match(ConI);
4155 op_cost(0);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4160 // Unsigned Integer Immediate: 6-bit int, greater than 32
4161 operand uimmI6_ge32() %{
4162 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4163 match(ConI);
4164 op_cost(0);
4165 format %{ %}
4166 interface(CONST_INTER);
4167 %}
4169 // Unsigned Integer Immediate: 15-bit
4170 operand uimmI15() %{
4171 predicate(Assembler::is_uimm(n->get_int(), 15));
4172 match(ConI);
4173 op_cost(0);
4174 format %{ %}
4175 interface(CONST_INTER);
4176 %}
4178 // Unsigned Integer Immediate: 16-bit
4179 operand uimmI16() %{
4180 predicate(Assembler::is_uimm(n->get_int(), 16));
4181 match(ConI);
4182 op_cost(0);
4183 format %{ %}
4184 interface(CONST_INTER);
4185 %}
4187 // constant 'int 0'.
4188 operand immI_0() %{
4189 predicate(n->get_int() == 0);
4190 match(ConI);
4191 op_cost(0);
4192 format %{ %}
4193 interface(CONST_INTER);
4194 %}
4196 // constant 'int 1'.
4197 operand immI_1() %{
4198 predicate(n->get_int() == 1);
4199 match(ConI);
4200 op_cost(0);
4201 format %{ %}
4202 interface(CONST_INTER);
4203 %}
4205 // constant 'int -1'.
4206 operand immI_minus1() %{
4207 predicate(n->get_int() == -1);
4208 match(ConI);
4209 op_cost(0);
4210 format %{ %}
4211 interface(CONST_INTER);
4212 %}
4214 // int value 16.
4215 operand immI_16() %{
4216 predicate(n->get_int() == 16);
4217 match(ConI);
4218 op_cost(0);
4219 format %{ %}
4220 interface(CONST_INTER);
4221 %}
4223 // int value 24.
4224 operand immI_24() %{
4225 predicate(n->get_int() == 24);
4226 match(ConI);
4227 op_cost(0);
4228 format %{ %}
4229 interface(CONST_INTER);
4230 %}
4232 // Compressed oops constants
4233 // Pointer Immediate
4234 operand immN() %{
4235 match(ConN);
4237 op_cost(10);
4238 format %{ %}
4239 interface(CONST_INTER);
4240 %}
4242 // NULL Pointer Immediate
4243 operand immN_0() %{
4244 predicate(n->get_narrowcon() == 0);
4245 match(ConN);
4247 op_cost(0);
4248 format %{ %}
4249 interface(CONST_INTER);
4250 %}
4252 // Compressed klass constants
4253 operand immNKlass() %{
4254 match(ConNKlass);
4256 op_cost(0);
4257 format %{ %}
4258 interface(CONST_INTER);
4259 %}
4261 // This operand can be used to avoid matching of an instruct
4262 // with chain rule.
4263 operand immNKlass_NM() %{
4264 match(ConNKlass);
4265 predicate(false);
4266 op_cost(0);
4267 format %{ %}
4268 interface(CONST_INTER);
4269 %}
4271 // Pointer Immediate: 64-bit
4272 operand immP() %{
4273 match(ConP);
4274 op_cost(0);
4275 format %{ %}
4276 interface(CONST_INTER);
4277 %}
4279 // Operand to avoid match of loadConP.
4280 // This operand can be used to avoid matching of an instruct
4281 // with chain rule.
4282 operand immP_NM() %{
4283 match(ConP);
4284 predicate(false);
4285 op_cost(0);
4286 format %{ %}
4287 interface(CONST_INTER);
4288 %}
4290 // costant 'pointer 0'.
4291 operand immP_0() %{
4292 predicate(n->get_ptr() == 0);
4293 match(ConP);
4294 op_cost(0);
4295 format %{ %}
4296 interface(CONST_INTER);
4297 %}
4299 // pointer 0x0 or 0x1
4300 operand immP_0or1() %{
4301 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4302 match(ConP);
4303 op_cost(0);
4304 format %{ %}
4305 interface(CONST_INTER);
4306 %}
4308 operand immL() %{
4309 match(ConL);
4310 op_cost(40);
4311 format %{ %}
4312 interface(CONST_INTER);
4313 %}
4315 // Long Immediate: 16-bit
4316 operand immL16() %{
4317 predicate(Assembler::is_simm(n->get_long(), 16));
4318 match(ConL);
4319 op_cost(0);
4320 format %{ %}
4321 interface(CONST_INTER);
4322 %}
4324 // Long Immediate: 16-bit, 4-aligned
4325 operand immL16Alg4() %{
4326 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4327 match(ConL);
4328 op_cost(0);
4329 format %{ %}
4330 interface(CONST_INTER);
4331 %}
4333 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4334 operand immL32hi16() %{
4335 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4336 match(ConL);
4337 op_cost(0);
4338 format %{ %}
4339 interface(CONST_INTER);
4340 %}
4342 // Long Immediate: 32-bit
4343 operand immL32() %{
4344 predicate(Assembler::is_simm(n->get_long(), 32));
4345 match(ConL);
4346 op_cost(0);
4347 format %{ %}
4348 interface(CONST_INTER);
4349 %}
4351 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4352 operand immLhighest16() %{
4353 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4354 match(ConL);
4355 op_cost(0);
4356 format %{ %}
4357 interface(CONST_INTER);
4358 %}
4360 operand immLnegpow2() %{
4361 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4362 match(ConL);
4363 op_cost(0);
4364 format %{ %}
4365 interface(CONST_INTER);
4366 %}
4368 operand immLpow2minus1() %{
4369 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4370 (n->get_long() != (jlong)0xffffffffffffffffL));
4371 match(ConL);
4372 op_cost(0);
4373 format %{ %}
4374 interface(CONST_INTER);
4375 %}
4377 // constant 'long 0'.
4378 operand immL_0() %{
4379 predicate(n->get_long() == 0L);
4380 match(ConL);
4381 op_cost(0);
4382 format %{ %}
4383 interface(CONST_INTER);
4384 %}
4386 // constat ' long -1'.
4387 operand immL_minus1() %{
4388 predicate(n->get_long() == -1L);
4389 match(ConL);
4390 op_cost(0);
4391 format %{ %}
4392 interface(CONST_INTER);
4393 %}
4395 // Long Immediate: low 32-bit mask
4396 operand immL_32bits() %{
4397 predicate(n->get_long() == 0xFFFFFFFFL);
4398 match(ConL);
4399 op_cost(0);
4400 format %{ %}
4401 interface(CONST_INTER);
4402 %}
4404 // Unsigned Long Immediate: 16-bit
4405 operand uimmL16() %{
4406 predicate(Assembler::is_uimm(n->get_long(), 16));
4407 match(ConL);
4408 op_cost(0);
4409 format %{ %}
4410 interface(CONST_INTER);
4411 %}
4413 // Float Immediate
4414 operand immF() %{
4415 match(ConF);
4416 op_cost(40);
4417 format %{ %}
4418 interface(CONST_INTER);
4419 %}
4421 // Float Immediate: +0.0f.
4422 operand immF_0() %{
4423 predicate(jint_cast(n->getf()) == 0);
4424 match(ConF);
4426 op_cost(0);
4427 format %{ %}
4428 interface(CONST_INTER);
4429 %}
4431 // Double Immediate
4432 operand immD() %{
4433 match(ConD);
4434 op_cost(40);
4435 format %{ %}
4436 interface(CONST_INTER);
4437 %}
4439 // Integer Register Operands
4440 // Integer Destination Register
4441 // See definition of reg_class bits32_reg_rw.
4442 operand iRegIdst() %{
4443 constraint(ALLOC_IN_RC(bits32_reg_rw));
4444 match(RegI);
4445 match(rscratch1RegI);
4446 match(rscratch2RegI);
4447 match(rarg1RegI);
4448 match(rarg2RegI);
4449 match(rarg3RegI);
4450 match(rarg4RegI);
4451 format %{ %}
4452 interface(REG_INTER);
4453 %}
4455 // Integer Source Register
4456 // See definition of reg_class bits32_reg_ro.
4457 operand iRegIsrc() %{
4458 constraint(ALLOC_IN_RC(bits32_reg_ro));
4459 match(RegI);
4460 match(rscratch1RegI);
4461 match(rscratch2RegI);
4462 match(rarg1RegI);
4463 match(rarg2RegI);
4464 match(rarg3RegI);
4465 match(rarg4RegI);
4466 format %{ %}
4467 interface(REG_INTER);
4468 %}
4470 operand rscratch1RegI() %{
4471 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4472 match(iRegIdst);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4477 operand rscratch2RegI() %{
4478 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4479 match(iRegIdst);
4480 format %{ %}
4481 interface(REG_INTER);
4482 %}
4484 operand rarg1RegI() %{
4485 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4486 match(iRegIdst);
4487 format %{ %}
4488 interface(REG_INTER);
4489 %}
4491 operand rarg2RegI() %{
4492 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4493 match(iRegIdst);
4494 format %{ %}
4495 interface(REG_INTER);
4496 %}
4498 operand rarg3RegI() %{
4499 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4500 match(iRegIdst);
4501 format %{ %}
4502 interface(REG_INTER);
4503 %}
4505 operand rarg4RegI() %{
4506 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4507 match(iRegIdst);
4508 format %{ %}
4509 interface(REG_INTER);
4510 %}
4512 operand rarg1RegL() %{
4513 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4514 match(iRegLdst);
4515 format %{ %}
4516 interface(REG_INTER);
4517 %}
4519 operand rarg2RegL() %{
4520 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4521 match(iRegLdst);
4522 format %{ %}
4523 interface(REG_INTER);
4524 %}
4526 operand rarg3RegL() %{
4527 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4528 match(iRegLdst);
4529 format %{ %}
4530 interface(REG_INTER);
4531 %}
4533 operand rarg4RegL() %{
4534 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4535 match(iRegLdst);
4536 format %{ %}
4537 interface(REG_INTER);
4538 %}
4540 // Pointer Destination Register
4541 // See definition of reg_class bits64_reg_rw.
4542 operand iRegPdst() %{
4543 constraint(ALLOC_IN_RC(bits64_reg_rw));
4544 match(RegP);
4545 match(rscratch1RegP);
4546 match(rscratch2RegP);
4547 match(rarg1RegP);
4548 match(rarg2RegP);
4549 match(rarg3RegP);
4550 match(rarg4RegP);
4551 format %{ %}
4552 interface(REG_INTER);
4553 %}
4555 // Pointer Destination Register
4556 // Operand not using r11 and r12 (killed in epilog).
4557 operand iRegPdstNoScratch() %{
4558 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4559 match(RegP);
4560 match(rarg1RegP);
4561 match(rarg2RegP);
4562 match(rarg3RegP);
4563 match(rarg4RegP);
4564 format %{ %}
4565 interface(REG_INTER);
4566 %}
4568 // Pointer Source Register
4569 // See definition of reg_class bits64_reg_ro.
4570 operand iRegPsrc() %{
4571 constraint(ALLOC_IN_RC(bits64_reg_ro));
4572 match(RegP);
4573 match(iRegPdst);
4574 match(rscratch1RegP);
4575 match(rscratch2RegP);
4576 match(rarg1RegP);
4577 match(rarg2RegP);
4578 match(rarg3RegP);
4579 match(rarg4RegP);
4580 match(threadRegP);
4581 format %{ %}
4582 interface(REG_INTER);
4583 %}
4585 // Thread operand.
4586 operand threadRegP() %{
4587 constraint(ALLOC_IN_RC(thread_bits64_reg));
4588 match(iRegPdst);
4589 format %{ "R16" %}
4590 interface(REG_INTER);
4591 %}
4593 operand rscratch1RegP() %{
4594 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4595 match(iRegPdst);
4596 format %{ "R11" %}
4597 interface(REG_INTER);
4598 %}
4600 operand rscratch2RegP() %{
4601 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4602 match(iRegPdst);
4603 format %{ %}
4604 interface(REG_INTER);
4605 %}
4607 operand rarg1RegP() %{
4608 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4609 match(iRegPdst);
4610 format %{ %}
4611 interface(REG_INTER);
4612 %}
4614 operand rarg2RegP() %{
4615 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4616 match(iRegPdst);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4621 operand rarg3RegP() %{
4622 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4623 match(iRegPdst);
4624 format %{ %}
4625 interface(REG_INTER);
4626 %}
4628 operand rarg4RegP() %{
4629 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4630 match(iRegPdst);
4631 format %{ %}
4632 interface(REG_INTER);
4633 %}
4635 operand iRegNsrc() %{
4636 constraint(ALLOC_IN_RC(bits32_reg_ro));
4637 match(RegN);
4638 match(iRegNdst);
4640 format %{ %}
4641 interface(REG_INTER);
4642 %}
4644 operand iRegNdst() %{
4645 constraint(ALLOC_IN_RC(bits32_reg_rw));
4646 match(RegN);
4648 format %{ %}
4649 interface(REG_INTER);
4650 %}
4652 // Long Destination Register
4653 // See definition of reg_class bits64_reg_rw.
4654 operand iRegLdst() %{
4655 constraint(ALLOC_IN_RC(bits64_reg_rw));
4656 match(RegL);
4657 match(rscratch1RegL);
4658 match(rscratch2RegL);
4659 format %{ %}
4660 interface(REG_INTER);
4661 %}
4663 // Long Source Register
4664 // See definition of reg_class bits64_reg_ro.
4665 operand iRegLsrc() %{
4666 constraint(ALLOC_IN_RC(bits64_reg_ro));
4667 match(RegL);
4668 match(iRegLdst);
4669 match(rscratch1RegL);
4670 match(rscratch2RegL);
4671 format %{ %}
4672 interface(REG_INTER);
4673 %}
4675 // Special operand for ConvL2I.
4676 operand iRegL2Isrc(iRegLsrc reg) %{
4677 constraint(ALLOC_IN_RC(bits64_reg_ro));
4678 match(ConvL2I reg);
4679 format %{ "ConvL2I($reg)" %}
4680 interface(REG_INTER)
4681 %}
4683 operand rscratch1RegL() %{
4684 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4685 match(RegL);
4686 format %{ %}
4687 interface(REG_INTER);
4688 %}
4690 operand rscratch2RegL() %{
4691 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4692 match(RegL);
4693 format %{ %}
4694 interface(REG_INTER);
4695 %}
4697 // Condition Code Flag Registers
4698 operand flagsReg() %{
4699 constraint(ALLOC_IN_RC(int_flags));
4700 match(RegFlags);
4701 format %{ %}
4702 interface(REG_INTER);
4703 %}
4705 // Condition Code Flag Register CR0
4706 operand flagsRegCR0() %{
4707 constraint(ALLOC_IN_RC(int_flags_CR0));
4708 match(RegFlags);
4709 format %{ "CR0" %}
4710 interface(REG_INTER);
4711 %}
4713 operand flagsRegCR1() %{
4714 constraint(ALLOC_IN_RC(int_flags_CR1));
4715 match(RegFlags);
4716 format %{ "CR1" %}
4717 interface(REG_INTER);
4718 %}
4720 operand flagsRegCR6() %{
4721 constraint(ALLOC_IN_RC(int_flags_CR6));
4722 match(RegFlags);
4723 format %{ "CR6" %}
4724 interface(REG_INTER);
4725 %}
4727 operand regCTR() %{
4728 constraint(ALLOC_IN_RC(ctr_reg));
4729 // RegFlags should work. Introducing a RegSpecial type would cause a
4730 // lot of changes.
4731 match(RegFlags);
4732 format %{"SR_CTR" %}
4733 interface(REG_INTER);
4734 %}
4736 operand regD() %{
4737 constraint(ALLOC_IN_RC(dbl_reg));
4738 match(RegD);
4739 format %{ %}
4740 interface(REG_INTER);
4741 %}
4743 operand regF() %{
4744 constraint(ALLOC_IN_RC(flt_reg));
4745 match(RegF);
4746 format %{ %}
4747 interface(REG_INTER);
4748 %}
4750 // Special Registers
4752 // Method Register
4753 operand inline_cache_regP(iRegPdst reg) %{
4754 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4755 match(reg);
4756 format %{ %}
4757 interface(REG_INTER);
4758 %}
4760 operand compiler_method_oop_regP(iRegPdst reg) %{
4761 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4762 match(reg);
4763 format %{ %}
4764 interface(REG_INTER);
4765 %}
4767 operand interpreter_method_oop_regP(iRegPdst reg) %{
4768 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4769 match(reg);
4770 format %{ %}
4771 interface(REG_INTER);
4772 %}
4774 // Operands to remove register moves in unscaled mode.
4775 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4776 operand iRegP2N(iRegPsrc reg) %{
4777 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4778 constraint(ALLOC_IN_RC(bits64_reg_ro));
4779 match(EncodeP reg);
4780 format %{ "$reg" %}
4781 interface(REG_INTER)
4782 %}
4784 operand iRegN2P(iRegNsrc reg) %{
4785 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4786 constraint(ALLOC_IN_RC(bits32_reg_ro));
4787 match(DecodeN reg);
4788 match(DecodeNKlass reg);
4789 format %{ "$reg" %}
4790 interface(REG_INTER)
4791 %}
4793 //----------Complex Operands---------------------------------------------------
4794 // Indirect Memory Reference
4795 operand indirect(iRegPsrc reg) %{
4796 constraint(ALLOC_IN_RC(bits64_reg_ro));
4797 match(reg);
4798 op_cost(100);
4799 format %{ "[$reg]" %}
4800 interface(MEMORY_INTER) %{
4801 base($reg);
4802 index(0x0);
4803 scale(0x0);
4804 disp(0x0);
4805 %}
4806 %}
4808 // Indirect with Offset
4809 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4810 constraint(ALLOC_IN_RC(bits64_reg_ro));
4811 match(AddP reg offset);
4812 op_cost(100);
4813 format %{ "[$reg + $offset]" %}
4814 interface(MEMORY_INTER) %{
4815 base($reg);
4816 index(0x0);
4817 scale(0x0);
4818 disp($offset);
4819 %}
4820 %}
4822 // Indirect with 4-aligned Offset
4823 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4824 constraint(ALLOC_IN_RC(bits64_reg_ro));
4825 match(AddP reg offset);
4826 op_cost(100);
4827 format %{ "[$reg + $offset]" %}
4828 interface(MEMORY_INTER) %{
4829 base($reg);
4830 index(0x0);
4831 scale(0x0);
4832 disp($offset);
4833 %}
4834 %}
4836 //----------Complex Operands for Compressed OOPs-------------------------------
4837 // Compressed OOPs with narrow_oop_shift == 0.
4839 // Indirect Memory Reference, compressed OOP
4840 operand indirectNarrow(iRegNsrc reg) %{
4841 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4842 constraint(ALLOC_IN_RC(bits64_reg_ro));
4843 match(DecodeN reg);
4844 match(DecodeNKlass reg);
4845 op_cost(100);
4846 format %{ "[$reg]" %}
4847 interface(MEMORY_INTER) %{
4848 base($reg);
4849 index(0x0);
4850 scale(0x0);
4851 disp(0x0);
4852 %}
4853 %}
4855 // Indirect with Offset, compressed OOP
4856 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4857 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4858 constraint(ALLOC_IN_RC(bits64_reg_ro));
4859 match(AddP (DecodeN reg) offset);
4860 match(AddP (DecodeNKlass reg) offset);
4861 op_cost(100);
4862 format %{ "[$reg + $offset]" %}
4863 interface(MEMORY_INTER) %{
4864 base($reg);
4865 index(0x0);
4866 scale(0x0);
4867 disp($offset);
4868 %}
4869 %}
4871 // Indirect with 4-aligned Offset, compressed OOP
4872 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4873 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4874 constraint(ALLOC_IN_RC(bits64_reg_ro));
4875 match(AddP (DecodeN reg) offset);
4876 match(AddP (DecodeNKlass reg) offset);
4877 op_cost(100);
4878 format %{ "[$reg + $offset]" %}
4879 interface(MEMORY_INTER) %{
4880 base($reg);
4881 index(0x0);
4882 scale(0x0);
4883 disp($offset);
4884 %}
4885 %}
4887 //----------Special Memory Operands--------------------------------------------
4888 // Stack Slot Operand
4889 //
4890 // This operand is used for loading and storing temporary values on
4891 // the stack where a match requires a value to flow through memory.
4892 operand stackSlotI(sRegI reg) %{
4893 constraint(ALLOC_IN_RC(stack_slots));
4894 op_cost(100);
4895 //match(RegI);
4896 format %{ "[sp+$reg]" %}
4897 interface(MEMORY_INTER) %{
4898 base(0x1); // R1_SP
4899 index(0x0);
4900 scale(0x0);
4901 disp($reg); // Stack Offset
4902 %}
4903 %}
4905 operand stackSlotL(sRegL reg) %{
4906 constraint(ALLOC_IN_RC(stack_slots));
4907 op_cost(100);
4908 //match(RegL);
4909 format %{ "[sp+$reg]" %}
4910 interface(MEMORY_INTER) %{
4911 base(0x1); // R1_SP
4912 index(0x0);
4913 scale(0x0);
4914 disp($reg); // Stack Offset
4915 %}
4916 %}
4918 operand stackSlotP(sRegP reg) %{
4919 constraint(ALLOC_IN_RC(stack_slots));
4920 op_cost(100);
4921 //match(RegP);
4922 format %{ "[sp+$reg]" %}
4923 interface(MEMORY_INTER) %{
4924 base(0x1); // R1_SP
4925 index(0x0);
4926 scale(0x0);
4927 disp($reg); // Stack Offset
4928 %}
4929 %}
4931 operand stackSlotF(sRegF reg) %{
4932 constraint(ALLOC_IN_RC(stack_slots));
4933 op_cost(100);
4934 //match(RegF);
4935 format %{ "[sp+$reg]" %}
4936 interface(MEMORY_INTER) %{
4937 base(0x1); // R1_SP
4938 index(0x0);
4939 scale(0x0);
4940 disp($reg); // Stack Offset
4941 %}
4942 %}
4944 operand stackSlotD(sRegD reg) %{
4945 constraint(ALLOC_IN_RC(stack_slots));
4946 op_cost(100);
4947 //match(RegD);
4948 format %{ "[sp+$reg]" %}
4949 interface(MEMORY_INTER) %{
4950 base(0x1); // R1_SP
4951 index(0x0);
4952 scale(0x0);
4953 disp($reg); // Stack Offset
4954 %}
4955 %}
4957 // Operands for expressing Control Flow
4958 // NOTE: Label is a predefined operand which should not be redefined in
4959 // the AD file. It is generically handled within the ADLC.
4961 //----------Conditional Branch Operands----------------------------------------
4962 // Comparison Op
4963 //
4964 // This is the operation of the comparison, and is limited to the
4965 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4966 // (!=).
4967 //
4968 // Other attributes of the comparison, such as unsignedness, are specified
4969 // by the comparison instruction that sets a condition code flags register.
4970 // That result is represented by a flags operand whose subtype is appropriate
4971 // to the unsignedness (etc.) of the comparison.
4972 //
4973 // Later, the instruction which matches both the Comparison Op (a Bool) and
4974 // the flags (produced by the Cmp) specifies the coding of the comparison op
4975 // by matching a specific subtype of Bool operand below.
4977 // When used for floating point comparisons: unordered same as less.
4978 operand cmpOp() %{
4979 match(Bool);
4980 format %{ "" %}
4981 interface(COND_INTER) %{
4982 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4983 // BO & BI
4984 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4985 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4986 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4987 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4988 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4989 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4990 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4991 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4992 %}
4993 %}
4995 //----------OPERAND CLASSES----------------------------------------------------
4996 // Operand Classes are groups of operands that are used to simplify
4997 // instruction definitions by not requiring the AD writer to specify
4998 // seperate instructions for every form of operand when the
4999 // instruction accepts multiple operand types with the same basic
5000 // encoding and format. The classic case of this is memory operands.
5001 // Indirect is not included since its use is limited to Compare & Swap.
5003 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
5004 // Memory operand where offsets are 4-aligned. Required for ld, std.
5005 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
5006 opclass indirectMemory(indirect, indirectNarrow);
5008 // Special opclass for I and ConvL2I.
5009 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5011 // Operand classes to match encode and decode. iRegN_P2N is only used
5012 // for storeN. I have never seen an encode node elsewhere.
5013 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5014 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5016 //----------PIPELINE-----------------------------------------------------------
5018 pipeline %{
5020 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5021 // J. Res. & Dev., No. 1, Jan. 2002.
5023 //----------ATTRIBUTES---------------------------------------------------------
5024 attributes %{
5026 // Power4 instructions are of fixed length.
5027 fixed_size_instructions;
5029 // TODO: if `bundle' means number of instructions fetched
5030 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5031 // max instructions issued per cycle, this is 5.
5032 max_instructions_per_bundle = 8;
5034 // A Power4 instruction is 4 bytes long.
5035 instruction_unit_size = 4;
5037 // The Power4 processor fetches 64 bytes...
5038 instruction_fetch_unit_size = 64;
5040 // ...in one line
5041 instruction_fetch_units = 1
5043 // Unused, list one so that array generated by adlc is not empty.
5044 // Aix compiler chokes if _nop_count = 0.
5045 nops(fxNop);
5046 %}
5048 //----------RESOURCES----------------------------------------------------------
5049 // Resources are the functional units available to the machine
5050 resources(
5051 PPC_BR, // branch unit
5052 PPC_CR, // condition unit
5053 PPC_FX1, // integer arithmetic unit 1
5054 PPC_FX2, // integer arithmetic unit 2
5055 PPC_LDST1, // load/store unit 1
5056 PPC_LDST2, // load/store unit 2
5057 PPC_FP1, // float arithmetic unit 1
5058 PPC_FP2, // float arithmetic unit 2
5059 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5060 PPC_FX = PPC_FX1 | PPC_FX2,
5061 PPC_FP = PPC_FP1 | PPC_FP2
5062 );
5064 //----------PIPELINE DESCRIPTION-----------------------------------------------
5065 // Pipeline Description specifies the stages in the machine's pipeline
5066 pipe_desc(
5067 // Power4 longest pipeline path
5068 PPC_IF, // instruction fetch
5069 PPC_IC,
5070 //PPC_BP, // branch prediction
5071 PPC_D0, // decode
5072 PPC_D1, // decode
5073 PPC_D2, // decode
5074 PPC_D3, // decode
5075 PPC_Xfer1,
5076 PPC_GD, // group definition
5077 PPC_MP, // map
5078 PPC_ISS, // issue
5079 PPC_RF, // resource fetch
5080 PPC_EX1, // execute (all units)
5081 PPC_EX2, // execute (FP, LDST)
5082 PPC_EX3, // execute (FP, LDST)
5083 PPC_EX4, // execute (FP)
5084 PPC_EX5, // execute (FP)
5085 PPC_EX6, // execute (FP)
5086 PPC_WB, // write back
5087 PPC_Xfer2,
5088 PPC_CP
5089 );
5091 //----------PIPELINE CLASSES---------------------------------------------------
5092 // Pipeline Classes describe the stages in which input and output are
5093 // referenced by the hardware pipeline.
5095 // Simple pipeline classes.
5097 // Default pipeline class.
5098 pipe_class pipe_class_default() %{
5099 single_instruction;
5100 fixed_latency(2);
5101 %}
5103 // Pipeline class for empty instructions.
5104 pipe_class pipe_class_empty() %{
5105 single_instruction;
5106 fixed_latency(0);
5107 %}
5109 // Pipeline class for compares.
5110 pipe_class pipe_class_compare() %{
5111 single_instruction;
5112 fixed_latency(16);
5113 %}
5115 // Pipeline class for traps.
5116 pipe_class pipe_class_trap() %{
5117 single_instruction;
5118 fixed_latency(100);
5119 %}
5121 // Pipeline class for memory operations.
5122 pipe_class pipe_class_memory() %{
5123 single_instruction;
5124 fixed_latency(16);
5125 %}
5127 // Pipeline class for call.
5128 pipe_class pipe_class_call() %{
5129 single_instruction;
5130 fixed_latency(100);
5131 %}
5133 // Define the class for the Nop node.
5134 define %{
5135 MachNop = pipe_class_default;
5136 %}
5138 %}
5140 //----------INSTRUCTIONS-------------------------------------------------------
5142 // Naming of instructions:
5143 // opA_operB / opA_operB_operC:
5144 // Operation 'op' with one or two source operands 'oper'. Result
5145 // type is A, source operand types are B and C.
5146 // Iff A == B == C, B and C are left out.
5147 //
5148 // The instructions are ordered according to the following scheme:
5149 // - loads
5150 // - load constants
5151 // - prefetch
5152 // - store
5153 // - encode/decode
5154 // - membar
5155 // - conditional moves
5156 // - compare & swap
5157 // - arithmetic and logic operations
5158 // * int: Add, Sub, Mul, Div, Mod
5159 // * int: lShift, arShift, urShift, rot
5160 // * float: Add, Sub, Mul, Div
5161 // * and, or, xor ...
5162 // - register moves: float <-> int, reg <-> stack, repl
5163 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5164 // - conv (low level type cast requiring bit changes (sign extend etc)
5165 // - compares, range & zero checks.
5166 // - branches
5167 // - complex operations, intrinsics, min, max, replicate
5168 // - lock
5169 // - Calls
5170 //
5171 // If there are similar instructions with different types they are sorted:
5172 // int before float
5173 // small before big
5174 // signed before unsigned
5175 // e.g., loadS before loadUS before loadI before loadF.
5178 //----------Load/Store Instructions--------------------------------------------
5180 //----------Load Instructions--------------------------------------------------
5182 // Converts byte to int.
5183 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5184 // reuses the 'amount' operand, but adlc expects that operand specification
5185 // and operands in match rule are equivalent.
5186 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5187 effect(DEF dst, USE src);
5188 format %{ "EXTSB $dst, $src \t// byte->int" %}
5189 size(4);
5190 ins_encode %{
5191 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5192 __ extsb($dst$$Register, $src$$Register);
5193 %}
5194 ins_pipe(pipe_class_default);
5195 %}
5197 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5198 // match-rule, false predicate
5199 match(Set dst (LoadB mem));
5200 predicate(false);
5202 format %{ "LBZ $dst, $mem" %}
5203 size(4);
5204 ins_encode( enc_lbz(dst, mem) );
5205 ins_pipe(pipe_class_memory);
5206 %}
5208 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5209 // match-rule, false predicate
5210 match(Set dst (LoadB mem));
5211 predicate(false);
5213 format %{ "LBZ $dst, $mem\n\t"
5214 "TWI $dst\n\t"
5215 "ISYNC" %}
5216 size(12);
5217 ins_encode( enc_lbz_ac(dst, mem) );
5218 ins_pipe(pipe_class_memory);
5219 %}
5221 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5222 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5223 match(Set dst (LoadB mem));
5224 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5225 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5226 expand %{
5227 iRegIdst tmp;
5228 loadUB_indirect(tmp, mem);
5229 convB2I_reg_2(dst, tmp);
5230 %}
5231 %}
5233 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5234 match(Set dst (LoadB mem));
5235 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5236 expand %{
5237 iRegIdst tmp;
5238 loadUB_indirect_ac(tmp, mem);
5239 convB2I_reg_2(dst, tmp);
5240 %}
5241 %}
5243 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5244 // match-rule, false predicate
5245 match(Set dst (LoadB mem));
5246 predicate(false);
5248 format %{ "LBZ $dst, $mem" %}
5249 size(4);
5250 ins_encode( enc_lbz(dst, mem) );
5251 ins_pipe(pipe_class_memory);
5252 %}
5254 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5255 // match-rule, false predicate
5256 match(Set dst (LoadB mem));
5257 predicate(false);
5259 format %{ "LBZ $dst, $mem\n\t"
5260 "TWI $dst\n\t"
5261 "ISYNC" %}
5262 size(12);
5263 ins_encode( enc_lbz_ac(dst, mem) );
5264 ins_pipe(pipe_class_memory);
5265 %}
5267 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5268 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5269 match(Set dst (LoadB mem));
5270 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5271 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5273 expand %{
5274 iRegIdst tmp;
5275 loadUB_indOffset16(tmp, mem);
5276 convB2I_reg_2(dst, tmp);
5277 %}
5278 %}
5280 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5281 match(Set dst (LoadB mem));
5282 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5284 expand %{
5285 iRegIdst tmp;
5286 loadUB_indOffset16_ac(tmp, mem);
5287 convB2I_reg_2(dst, tmp);
5288 %}
5289 %}
5291 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5292 instruct loadUB(iRegIdst dst, memory mem) %{
5293 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5294 match(Set dst (LoadUB mem));
5295 ins_cost(MEMORY_REF_COST);
5297 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5298 size(4);
5299 ins_encode( enc_lbz(dst, mem) );
5300 ins_pipe(pipe_class_memory);
5301 %}
5303 // Load Unsigned Byte (8bit UNsigned) acquire.
5304 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5305 match(Set dst (LoadUB mem));
5306 ins_cost(3*MEMORY_REF_COST);
5308 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5309 "TWI $dst\n\t"
5310 "ISYNC" %}
5311 size(12);
5312 ins_encode( enc_lbz_ac(dst, mem) );
5313 ins_pipe(pipe_class_memory);
5314 %}
5316 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5317 instruct loadUB2L(iRegLdst dst, memory mem) %{
5318 match(Set dst (ConvI2L (LoadUB mem)));
5319 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5320 ins_cost(MEMORY_REF_COST);
5322 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5323 size(4);
5324 ins_encode( enc_lbz(dst, mem) );
5325 ins_pipe(pipe_class_memory);
5326 %}
5328 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5329 match(Set dst (ConvI2L (LoadUB mem)));
5330 ins_cost(3*MEMORY_REF_COST);
5332 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5333 "TWI $dst\n\t"
5334 "ISYNC" %}
5335 size(12);
5336 ins_encode( enc_lbz_ac(dst, mem) );
5337 ins_pipe(pipe_class_memory);
5338 %}
5340 // Load Short (16bit signed)
5341 instruct loadS(iRegIdst dst, memory mem) %{
5342 match(Set dst (LoadS mem));
5343 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5344 ins_cost(MEMORY_REF_COST);
5346 format %{ "LHA $dst, $mem" %}
5347 size(4);
5348 ins_encode %{
5349 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5350 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5351 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5352 %}
5353 ins_pipe(pipe_class_memory);
5354 %}
5356 // Load Short (16bit signed) acquire.
5357 instruct loadS_ac(iRegIdst dst, memory mem) %{
5358 match(Set dst (LoadS mem));
5359 ins_cost(3*MEMORY_REF_COST);
5361 format %{ "LHA $dst, $mem\t acquire\n\t"
5362 "TWI $dst\n\t"
5363 "ISYNC" %}
5364 size(12);
5365 ins_encode %{
5366 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5367 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5368 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5369 __ twi_0($dst$$Register);
5370 __ isync();
5371 %}
5372 ins_pipe(pipe_class_memory);
5373 %}
5375 // Load Char (16bit unsigned)
5376 instruct loadUS(iRegIdst dst, memory mem) %{
5377 match(Set dst (LoadUS mem));
5378 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5379 ins_cost(MEMORY_REF_COST);
5381 format %{ "LHZ $dst, $mem" %}
5382 size(4);
5383 ins_encode( enc_lhz(dst, mem) );
5384 ins_pipe(pipe_class_memory);
5385 %}
5387 // Load Char (16bit unsigned) acquire.
5388 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5389 match(Set dst (LoadUS mem));
5390 ins_cost(3*MEMORY_REF_COST);
5392 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5393 "TWI $dst\n\t"
5394 "ISYNC" %}
5395 size(12);
5396 ins_encode( enc_lhz_ac(dst, mem) );
5397 ins_pipe(pipe_class_memory);
5398 %}
5400 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5401 instruct loadUS2L(iRegLdst dst, memory mem) %{
5402 match(Set dst (ConvI2L (LoadUS mem)));
5403 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5404 ins_cost(MEMORY_REF_COST);
5406 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5407 size(4);
5408 ins_encode( enc_lhz(dst, mem) );
5409 ins_pipe(pipe_class_memory);
5410 %}
5412 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5413 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5414 match(Set dst (ConvI2L (LoadUS mem)));
5415 ins_cost(3*MEMORY_REF_COST);
5417 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5418 "TWI $dst\n\t"
5419 "ISYNC" %}
5420 size(12);
5421 ins_encode( enc_lhz_ac(dst, mem) );
5422 ins_pipe(pipe_class_memory);
5423 %}
5425 // Load Integer.
5426 instruct loadI(iRegIdst dst, memory mem) %{
5427 match(Set dst (LoadI mem));
5428 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5429 ins_cost(MEMORY_REF_COST);
5431 format %{ "LWZ $dst, $mem" %}
5432 size(4);
5433 ins_encode( enc_lwz(dst, mem) );
5434 ins_pipe(pipe_class_memory);
5435 %}
5437 // Load Integer acquire.
5438 instruct loadI_ac(iRegIdst dst, memory mem) %{
5439 match(Set dst (LoadI mem));
5440 ins_cost(3*MEMORY_REF_COST);
5442 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5443 "TWI $dst\n\t"
5444 "ISYNC" %}
5445 size(12);
5446 ins_encode( enc_lwz_ac(dst, mem) );
5447 ins_pipe(pipe_class_memory);
5448 %}
5450 // Match loading integer and casting it to unsigned int in
5451 // long register.
5452 // LoadI + ConvI2L + AndL 0xffffffff.
5453 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5454 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5455 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5456 ins_cost(MEMORY_REF_COST);
5458 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5459 size(4);
5460 ins_encode( enc_lwz(dst, mem) );
5461 ins_pipe(pipe_class_memory);
5462 %}
5464 // Match loading integer and casting it to long.
5465 instruct loadI2L(iRegLdst dst, memory mem) %{
5466 match(Set dst (ConvI2L (LoadI mem)));
5467 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5468 ins_cost(MEMORY_REF_COST);
5470 format %{ "LWA $dst, $mem \t// loadI2L" %}
5471 size(4);
5472 ins_encode %{
5473 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5474 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5475 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5476 %}
5477 ins_pipe(pipe_class_memory);
5478 %}
5480 // Match loading integer and casting it to long - acquire.
5481 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5482 match(Set dst (ConvI2L (LoadI mem)));
5483 ins_cost(3*MEMORY_REF_COST);
5485 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5486 "TWI $dst\n\t"
5487 "ISYNC" %}
5488 size(12);
5489 ins_encode %{
5490 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5491 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5492 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5493 __ twi_0($dst$$Register);
5494 __ isync();
5495 %}
5496 ins_pipe(pipe_class_memory);
5497 %}
5499 // Load Long - aligned
5500 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5501 match(Set dst (LoadL mem));
5502 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5503 ins_cost(MEMORY_REF_COST);
5505 format %{ "LD $dst, $mem \t// long" %}
5506 size(4);
5507 ins_encode( enc_ld(dst, mem) );
5508 ins_pipe(pipe_class_memory);
5509 %}
5511 // Load Long - aligned acquire.
5512 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5513 match(Set dst (LoadL mem));
5514 ins_cost(3*MEMORY_REF_COST);
5516 format %{ "LD $dst, $mem \t// long acquire\n\t"
5517 "TWI $dst\n\t"
5518 "ISYNC" %}
5519 size(12);
5520 ins_encode( enc_ld_ac(dst, mem) );
5521 ins_pipe(pipe_class_memory);
5522 %}
5524 // Load Long - UNaligned
5525 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5526 match(Set dst (LoadL_unaligned mem));
5527 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5528 ins_cost(MEMORY_REF_COST);
5530 format %{ "LD $dst, $mem \t// unaligned long" %}
5531 size(4);
5532 ins_encode( enc_ld(dst, mem) );
5533 ins_pipe(pipe_class_memory);
5534 %}
5536 // Load nodes for superwords
5538 // Load Aligned Packed Byte
5539 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5540 predicate(n->as_LoadVector()->memory_size() == 8);
5541 match(Set dst (LoadVector mem));
5542 ins_cost(MEMORY_REF_COST);
5544 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5545 size(4);
5546 ins_encode( enc_ld(dst, mem) );
5547 ins_pipe(pipe_class_memory);
5548 %}
5550 // Load Range, range = array length (=jint)
5551 instruct loadRange(iRegIdst dst, memory mem) %{
5552 match(Set dst (LoadRange mem));
5553 ins_cost(MEMORY_REF_COST);
5555 format %{ "LWZ $dst, $mem \t// range" %}
5556 size(4);
5557 ins_encode( enc_lwz(dst, mem) );
5558 ins_pipe(pipe_class_memory);
5559 %}
5561 // Load Compressed Pointer
5562 instruct loadN(iRegNdst dst, memory mem) %{
5563 match(Set dst (LoadN mem));
5564 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5565 ins_cost(MEMORY_REF_COST);
5567 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5568 size(4);
5569 ins_encode( enc_lwz(dst, mem) );
5570 ins_pipe(pipe_class_memory);
5571 %}
5573 // Load Compressed Pointer acquire.
5574 instruct loadN_ac(iRegNdst dst, memory mem) %{
5575 match(Set dst (LoadN mem));
5576 ins_cost(3*MEMORY_REF_COST);
5578 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5579 "TWI $dst\n\t"
5580 "ISYNC" %}
5581 size(12);
5582 ins_encode( enc_lwz_ac(dst, mem) );
5583 ins_pipe(pipe_class_memory);
5584 %}
5586 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5587 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5588 match(Set dst (DecodeN (LoadN mem)));
5589 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5590 ins_cost(MEMORY_REF_COST);
5592 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5593 size(4);
5594 ins_encode( enc_lwz(dst, mem) );
5595 ins_pipe(pipe_class_memory);
5596 %}
5598 // Load Pointer
5599 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5600 match(Set dst (LoadP mem));
5601 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5602 ins_cost(MEMORY_REF_COST);
5604 format %{ "LD $dst, $mem \t// ptr" %}
5605 size(4);
5606 ins_encode( enc_ld(dst, mem) );
5607 ins_pipe(pipe_class_memory);
5608 %}
5610 // Load Pointer acquire.
5611 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5612 match(Set dst (LoadP mem));
5613 ins_cost(3*MEMORY_REF_COST);
5615 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5616 "TWI $dst\n\t"
5617 "ISYNC" %}
5618 size(12);
5619 ins_encode( enc_ld_ac(dst, mem) );
5620 ins_pipe(pipe_class_memory);
5621 %}
5623 // LoadP + CastP2L
5624 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5625 match(Set dst (CastP2X (LoadP mem)));
5626 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5627 ins_cost(MEMORY_REF_COST);
5629 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5630 size(4);
5631 ins_encode( enc_ld(dst, mem) );
5632 ins_pipe(pipe_class_memory);
5633 %}
5635 // Load compressed klass pointer.
5636 instruct loadNKlass(iRegNdst dst, memory mem) %{
5637 match(Set dst (LoadNKlass mem));
5638 ins_cost(MEMORY_REF_COST);
5640 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5641 size(4);
5642 ins_encode( enc_lwz(dst, mem) );
5643 ins_pipe(pipe_class_memory);
5644 %}
5646 // Load Klass Pointer
5647 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5648 match(Set dst (LoadKlass mem));
5649 ins_cost(MEMORY_REF_COST);
5651 format %{ "LD $dst, $mem \t// klass ptr" %}
5652 size(4);
5653 ins_encode( enc_ld(dst, mem) );
5654 ins_pipe(pipe_class_memory);
5655 %}
5657 // Load Float
5658 instruct loadF(regF dst, memory mem) %{
5659 match(Set dst (LoadF mem));
5660 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5661 ins_cost(MEMORY_REF_COST);
5663 format %{ "LFS $dst, $mem" %}
5664 size(4);
5665 ins_encode %{
5666 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5667 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5668 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5669 %}
5670 ins_pipe(pipe_class_memory);
5671 %}
5673 // Load Float acquire.
5674 instruct loadF_ac(regF dst, memory mem) %{
5675 match(Set dst (LoadF mem));
5676 ins_cost(3*MEMORY_REF_COST);
5678 format %{ "LFS $dst, $mem \t// acquire\n\t"
5679 "FCMPU cr0, $dst, $dst\n\t"
5680 "BNE cr0, next\n"
5681 "next:\n\t"
5682 "ISYNC" %}
5683 size(16);
5684 ins_encode %{
5685 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5686 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5687 Label next;
5688 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5689 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5690 __ bne(CCR0, next);
5691 __ bind(next);
5692 __ isync();
5693 %}
5694 ins_pipe(pipe_class_memory);
5695 %}
5697 // Load Double - aligned
5698 instruct loadD(regD dst, memory mem) %{
5699 match(Set dst (LoadD mem));
5700 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5701 ins_cost(MEMORY_REF_COST);
5703 format %{ "LFD $dst, $mem" %}
5704 size(4);
5705 ins_encode( enc_lfd(dst, mem) );
5706 ins_pipe(pipe_class_memory);
5707 %}
5709 // Load Double - aligned acquire.
5710 instruct loadD_ac(regD dst, memory mem) %{
5711 match(Set dst (LoadD mem));
5712 ins_cost(3*MEMORY_REF_COST);
5714 format %{ "LFD $dst, $mem \t// acquire\n\t"
5715 "FCMPU cr0, $dst, $dst\n\t"
5716 "BNE cr0, next\n"
5717 "next:\n\t"
5718 "ISYNC" %}
5719 size(16);
5720 ins_encode %{
5721 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5722 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5723 Label next;
5724 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5725 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5726 __ bne(CCR0, next);
5727 __ bind(next);
5728 __ isync();
5729 %}
5730 ins_pipe(pipe_class_memory);
5731 %}
5733 // Load Double - UNaligned
5734 instruct loadD_unaligned(regD dst, memory mem) %{
5735 match(Set dst (LoadD_unaligned mem));
5736 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5737 ins_cost(MEMORY_REF_COST);
5739 format %{ "LFD $dst, $mem" %}
5740 size(4);
5741 ins_encode( enc_lfd(dst, mem) );
5742 ins_pipe(pipe_class_memory);
5743 %}
5745 //----------Constants--------------------------------------------------------
5747 // Load MachConstantTableBase: add hi offset to global toc.
5748 // TODO: Handle hidden register r29 in bundler!
5749 instruct loadToc_hi(iRegLdst dst) %{
5750 effect(DEF dst);
5751 ins_cost(DEFAULT_COST);
5753 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5754 size(4);
5755 ins_encode %{
5756 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5757 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5758 %}
5759 ins_pipe(pipe_class_default);
5760 %}
5762 // Load MachConstantTableBase: add lo offset to global toc.
5763 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5764 effect(DEF dst, USE src);
5765 ins_cost(DEFAULT_COST);
5767 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5768 size(4);
5769 ins_encode %{
5770 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5771 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5772 %}
5773 ins_pipe(pipe_class_default);
5774 %}
5776 // Load 16-bit integer constant 0xssss????
5777 instruct loadConI16(iRegIdst dst, immI16 src) %{
5778 match(Set dst src);
5780 format %{ "LI $dst, $src" %}
5781 size(4);
5782 ins_encode %{
5783 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5784 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5785 %}
5786 ins_pipe(pipe_class_default);
5787 %}
5789 // Load integer constant 0x????0000
5790 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5791 match(Set dst src);
5792 ins_cost(DEFAULT_COST);
5794 format %{ "LIS $dst, $src.hi" %}
5795 size(4);
5796 ins_encode %{
5797 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5798 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5799 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5800 %}
5801 ins_pipe(pipe_class_default);
5802 %}
5804 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5805 // and sign extended), this adds the low 16 bits.
5806 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5807 // no match-rule, false predicate
5808 effect(DEF dst, USE src1, USE src2);
5809 predicate(false);
5811 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5812 size(4);
5813 ins_encode %{
5814 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5815 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5816 %}
5817 ins_pipe(pipe_class_default);
5818 %}
5820 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5821 match(Set dst src);
5822 ins_cost(DEFAULT_COST*2);
5824 expand %{
5825 // Would like to use $src$$constant.
5826 immI16 srcLo %{ _opnds[1]->constant() %}
5827 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5828 immIhi16 srcHi %{ _opnds[1]->constant() %}
5829 iRegIdst tmpI;
5830 loadConIhi16(tmpI, srcHi);
5831 loadConI32_lo16(dst, tmpI, srcLo);
5832 %}
5833 %}
5835 // No constant pool entries required.
5836 instruct loadConL16(iRegLdst dst, immL16 src) %{
5837 match(Set dst src);
5839 format %{ "LI $dst, $src \t// long" %}
5840 size(4);
5841 ins_encode %{
5842 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5843 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5844 %}
5845 ins_pipe(pipe_class_default);
5846 %}
5848 // Load long constant 0xssssssss????0000
5849 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5850 match(Set dst src);
5851 ins_cost(DEFAULT_COST);
5853 format %{ "LIS $dst, $src.hi \t// long" %}
5854 size(4);
5855 ins_encode %{
5856 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5857 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5858 %}
5859 ins_pipe(pipe_class_default);
5860 %}
5862 // To load a 32 bit constant: merge lower 16 bits into already loaded
5863 // high 16 bits.
5864 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5865 // no match-rule, false predicate
5866 effect(DEF dst, USE src1, USE src2);
5867 predicate(false);
5869 format %{ "ORI $dst, $src1, $src2.lo" %}
5870 size(4);
5871 ins_encode %{
5872 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5873 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5874 %}
5875 ins_pipe(pipe_class_default);
5876 %}
5878 // Load 32-bit long constant
5879 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5880 match(Set dst src);
5881 ins_cost(DEFAULT_COST*2);
5883 expand %{
5884 // Would like to use $src$$constant.
5885 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5886 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5887 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5888 iRegLdst tmpL;
5889 loadConL32hi16(tmpL, srcHi);
5890 loadConL32_lo16(dst, tmpL, srcLo);
5891 %}
5892 %}
5894 // Load long constant 0x????000000000000.
5895 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5896 match(Set dst src);
5897 ins_cost(DEFAULT_COST);
5899 expand %{
5900 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5901 immI shift32 %{ 32 %}
5902 iRegLdst tmpL;
5903 loadConL32hi16(tmpL, srcHi);
5904 lshiftL_regL_immI(dst, tmpL, shift32);
5905 %}
5906 %}
5908 // Expand node for constant pool load: small offset.
5909 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5910 effect(DEF dst, USE src, USE toc);
5911 ins_cost(MEMORY_REF_COST);
5913 ins_num_consts(1);
5914 // Needed so that CallDynamicJavaDirect can compute the address of this
5915 // instruction for relocation.
5916 ins_field_cbuf_insts_offset(int);
5918 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5919 size(4);
5920 ins_encode( enc_load_long_constL(dst, src, toc) );
5921 ins_pipe(pipe_class_memory);
5922 %}
5924 // Expand node for constant pool load: large offset.
5925 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5926 effect(DEF dst, USE src, USE toc);
5927 predicate(false);
5929 ins_num_consts(1);
5930 ins_field_const_toc_offset(int);
5931 // Needed so that CallDynamicJavaDirect can compute the address of this
5932 // instruction for relocation.
5933 ins_field_cbuf_insts_offset(int);
5935 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5936 size(4);
5937 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5938 ins_pipe(pipe_class_default);
5939 %}
5941 // Expand node for constant pool load: large offset.
5942 // No constant pool entries required.
5943 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5944 effect(DEF dst, USE src, USE base);
5945 predicate(false);
5947 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5949 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5950 size(4);
5951 ins_encode %{
5952 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5953 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5954 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5955 %}
5956 ins_pipe(pipe_class_memory);
5957 %}
5959 // Load long constant from constant table. Expand in case of
5960 // offset > 16 bit is needed.
5961 // Adlc adds toc node MachConstantTableBase.
5962 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5963 match(Set dst src);
5964 ins_cost(MEMORY_REF_COST);
5966 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5967 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5968 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5969 %}
5971 // Load NULL as compressed oop.
5972 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5973 match(Set dst src);
5974 ins_cost(DEFAULT_COST);
5976 format %{ "LI $dst, $src \t// compressed ptr" %}
5977 size(4);
5978 ins_encode %{
5979 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5980 __ li($dst$$Register, 0);
5981 %}
5982 ins_pipe(pipe_class_default);
5983 %}
5985 // Load hi part of compressed oop constant.
5986 instruct loadConN_hi(iRegNdst dst, immN src) %{
5987 effect(DEF dst, USE src);
5988 ins_cost(DEFAULT_COST);
5990 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5991 size(4);
5992 ins_encode %{
5993 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5994 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5995 %}
5996 ins_pipe(pipe_class_default);
5997 %}
5999 // Add lo part of compressed oop constant to already loaded hi part.
6000 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6001 effect(DEF dst, USE src1, USE src2);
6002 ins_cost(DEFAULT_COST);
6004 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6005 size(4);
6006 ins_encode %{
6007 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6008 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6009 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6010 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6011 __ relocate(rspec, 1);
6012 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6013 %}
6014 ins_pipe(pipe_class_default);
6015 %}
6017 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6018 // leaving the upper 32 bits with sign-extension bits.
6019 // This clears these bits: dst = src & 0xFFFFFFFF.
6020 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6021 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6022 effect(DEF dst, USE src);
6023 predicate(false);
6025 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6026 size(4);
6027 ins_encode %{
6028 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6029 __ clrldi($dst$$Register, $src$$Register, 0x20);
6030 %}
6031 ins_pipe(pipe_class_default);
6032 %}
6034 // Loading ConN must be postalloc expanded so that edges between
6035 // the nodes are safe. They may not interfere with a safepoint.
6036 // GL TODO: This needs three instructions: better put this into the constant pool.
6037 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6038 match(Set dst src);
6039 ins_cost(DEFAULT_COST*2);
6041 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6042 postalloc_expand %{
6043 MachNode *m1 = new (C) loadConN_hiNode();
6044 MachNode *m2 = new (C) loadConN_loNode();
6045 MachNode *m3 = new (C) clearMs32bNode();
6046 m1->add_req(NULL);
6047 m2->add_req(NULL, m1);
6048 m3->add_req(NULL, m2);
6049 m1->_opnds[0] = op_dst;
6050 m1->_opnds[1] = op_src;
6051 m2->_opnds[0] = op_dst;
6052 m2->_opnds[1] = op_dst;
6053 m2->_opnds[2] = op_src;
6054 m3->_opnds[0] = op_dst;
6055 m3->_opnds[1] = op_dst;
6056 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6057 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6058 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6059 nodes->push(m1);
6060 nodes->push(m2);
6061 nodes->push(m3);
6062 %}
6063 %}
6065 // We have seen a safepoint between the hi and lo parts, and this node was handled
6066 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6067 // not a narrow oop.
6068 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6069 match(Set dst src);
6070 effect(DEF dst, USE src);
6071 ins_cost(DEFAULT_COST);
6073 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6074 size(4);
6075 ins_encode %{
6076 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6077 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6078 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6079 %}
6080 ins_pipe(pipe_class_default);
6081 %}
6083 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6084 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6085 match(Set dst src1);
6086 effect(TEMP src2);
6087 ins_cost(DEFAULT_COST);
6089 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6090 size(4);
6091 ins_encode %{
6092 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6093 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6094 %}
6095 ins_pipe(pipe_class_default);
6096 %}
6098 // This needs a match rule so that build_oop_map knows this is
6099 // not a narrow oop.
6100 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6101 match(Set dst src1);
6102 effect(TEMP src2);
6103 ins_cost(DEFAULT_COST);
6105 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6106 size(4);
6107 ins_encode %{
6108 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6109 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6110 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6111 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6112 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6114 __ relocate(rspec, 1);
6115 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6116 %}
6117 ins_pipe(pipe_class_default);
6118 %}
6120 // Loading ConNKlass must be postalloc expanded so that edges between
6121 // the nodes are safe. They may not interfere with a safepoint.
6122 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6123 match(Set dst src);
6124 ins_cost(DEFAULT_COST*2);
6126 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6127 postalloc_expand %{
6128 // Load high bits into register. Sign extended.
6129 MachNode *m1 = new (C) loadConNKlass_hiNode();
6130 m1->add_req(NULL);
6131 m1->_opnds[0] = op_dst;
6132 m1->_opnds[1] = op_src;
6133 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6134 nodes->push(m1);
6136 MachNode *m2 = m1;
6137 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6138 // Value might be 1-extended. Mask out these bits.
6139 m2 = new (C) loadConNKlass_maskNode();
6140 m2->add_req(NULL, m1);
6141 m2->_opnds[0] = op_dst;
6142 m2->_opnds[1] = op_src;
6143 m2->_opnds[2] = op_dst;
6144 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6145 nodes->push(m2);
6146 }
6148 MachNode *m3 = new (C) loadConNKlass_loNode();
6149 m3->add_req(NULL, m2);
6150 m3->_opnds[0] = op_dst;
6151 m3->_opnds[1] = op_src;
6152 m3->_opnds[2] = op_dst;
6153 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6154 nodes->push(m3);
6155 %}
6156 %}
6158 // 0x1 is used in object initialization (initial object header).
6159 // No constant pool entries required.
6160 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6161 match(Set dst src);
6163 format %{ "LI $dst, $src \t// ptr" %}
6164 size(4);
6165 ins_encode %{
6166 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6167 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6168 %}
6169 ins_pipe(pipe_class_default);
6170 %}
6172 // Expand node for constant pool load: small offset.
6173 // The match rule is needed to generate the correct bottom_type(),
6174 // however this node should never match. The use of predicate is not
6175 // possible since ADLC forbids predicates for chain rules. The higher
6176 // costs do not prevent matching in this case. For that reason the
6177 // operand immP_NM with predicate(false) is used.
6178 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6179 match(Set dst src);
6180 effect(TEMP toc);
6182 ins_num_consts(1);
6184 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6185 size(4);
6186 ins_encode( enc_load_long_constP(dst, src, toc) );
6187 ins_pipe(pipe_class_memory);
6188 %}
6190 // Expand node for constant pool load: large offset.
6191 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6192 effect(DEF dst, USE src, USE toc);
6193 predicate(false);
6195 ins_num_consts(1);
6196 ins_field_const_toc_offset(int);
6198 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6199 size(4);
6200 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6201 ins_pipe(pipe_class_default);
6202 %}
6204 // Expand node for constant pool load: large offset.
6205 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6206 match(Set dst src);
6207 effect(TEMP base);
6209 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6211 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6212 size(4);
6213 ins_encode %{
6214 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6215 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6216 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6217 %}
6218 ins_pipe(pipe_class_memory);
6219 %}
6221 // Load pointer constant from constant table. Expand in case an
6222 // offset > 16 bit is needed.
6223 // Adlc adds toc node MachConstantTableBase.
6224 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6225 match(Set dst src);
6226 ins_cost(MEMORY_REF_COST);
6228 // This rule does not use "expand" because then
6229 // the result type is not known to be an Oop. An ADLC
6230 // enhancement will be needed to make that work - not worth it!
6232 // If this instruction rematerializes, it prolongs the live range
6233 // of the toc node, causing illegal graphs.
6234 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6235 ins_cannot_rematerialize(true);
6237 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6238 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6239 %}
6241 // Expand node for constant pool load: small offset.
6242 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6243 effect(DEF dst, USE src, USE toc);
6244 ins_cost(MEMORY_REF_COST);
6246 ins_num_consts(1);
6248 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6249 size(4);
6250 ins_encode %{
6251 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6252 address float_address = __ float_constant($src$$constant);
6253 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6254 %}
6255 ins_pipe(pipe_class_memory);
6256 %}
6258 // Expand node for constant pool load: large offset.
6259 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6260 effect(DEF dst, USE src, USE toc);
6261 ins_cost(MEMORY_REF_COST);
6263 ins_num_consts(1);
6265 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6266 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6267 "ADDIS $toc, $toc, -offset_hi"%}
6268 size(12);
6269 ins_encode %{
6270 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6271 FloatRegister Rdst = $dst$$FloatRegister;
6272 Register Rtoc = $toc$$Register;
6273 address float_address = __ float_constant($src$$constant);
6274 int offset = __ offset_to_method_toc(float_address);
6275 int hi = (offset + (1<<15))>>16;
6276 int lo = offset - hi * (1<<16);
6278 __ addis(Rtoc, Rtoc, hi);
6279 __ lfs(Rdst, lo, Rtoc);
6280 __ addis(Rtoc, Rtoc, -hi);
6281 %}
6282 ins_pipe(pipe_class_memory);
6283 %}
6285 // Adlc adds toc node MachConstantTableBase.
6286 instruct loadConF_Ex(regF dst, immF src) %{
6287 match(Set dst src);
6288 ins_cost(MEMORY_REF_COST);
6290 // See loadConP.
6291 ins_cannot_rematerialize(true);
6293 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6294 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6295 %}
6297 // Expand node for constant pool load: small offset.
6298 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6299 effect(DEF dst, USE src, USE toc);
6300 ins_cost(MEMORY_REF_COST);
6302 ins_num_consts(1);
6304 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6305 size(4);
6306 ins_encode %{
6307 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6308 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6309 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6310 %}
6311 ins_pipe(pipe_class_memory);
6312 %}
6314 // Expand node for constant pool load: large offset.
6315 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6316 effect(DEF dst, USE src, USE toc);
6317 ins_cost(MEMORY_REF_COST);
6319 ins_num_consts(1);
6321 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6322 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6323 "ADDIS $toc, $toc, -offset_hi" %}
6324 size(12);
6325 ins_encode %{
6326 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6327 FloatRegister Rdst = $dst$$FloatRegister;
6328 Register Rtoc = $toc$$Register;
6329 address float_address = __ double_constant($src$$constant);
6330 int offset = __ offset_to_method_toc(float_address);
6331 int hi = (offset + (1<<15))>>16;
6332 int lo = offset - hi * (1<<16);
6334 __ addis(Rtoc, Rtoc, hi);
6335 __ lfd(Rdst, lo, Rtoc);
6336 __ addis(Rtoc, Rtoc, -hi);
6337 %}
6338 ins_pipe(pipe_class_memory);
6339 %}
6341 // Adlc adds toc node MachConstantTableBase.
6342 instruct loadConD_Ex(regD dst, immD src) %{
6343 match(Set dst src);
6344 ins_cost(MEMORY_REF_COST);
6346 // See loadConP.
6347 ins_cannot_rematerialize(true);
6349 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6350 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6351 %}
6353 // Prefetch instructions.
6354 // Must be safe to execute with invalid address (cannot fault).
6356 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6357 match(PrefetchRead (AddP mem src));
6358 ins_cost(MEMORY_REF_COST);
6360 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6361 size(4);
6362 ins_encode %{
6363 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6364 __ dcbt($src$$Register, $mem$$base$$Register);
6365 %}
6366 ins_pipe(pipe_class_memory);
6367 %}
6369 instruct prefetchr_no_offset(indirectMemory mem) %{
6370 match(PrefetchRead mem);
6371 ins_cost(MEMORY_REF_COST);
6373 format %{ "PREFETCH $mem" %}
6374 size(4);
6375 ins_encode %{
6376 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6377 __ dcbt($mem$$base$$Register);
6378 %}
6379 ins_pipe(pipe_class_memory);
6380 %}
6382 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6383 match(PrefetchWrite (AddP mem src));
6384 ins_cost(MEMORY_REF_COST);
6386 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6387 size(4);
6388 ins_encode %{
6389 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6390 __ dcbtst($src$$Register, $mem$$base$$Register);
6391 %}
6392 ins_pipe(pipe_class_memory);
6393 %}
6395 instruct prefetchw_no_offset(indirectMemory mem) %{
6396 match(PrefetchWrite mem);
6397 ins_cost(MEMORY_REF_COST);
6399 format %{ "PREFETCH $mem" %}
6400 size(4);
6401 ins_encode %{
6402 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6403 __ dcbtst($mem$$base$$Register);
6404 %}
6405 ins_pipe(pipe_class_memory);
6406 %}
6408 // Special prefetch versions which use the dcbz instruction.
6409 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6410 match(PrefetchAllocation (AddP mem src));
6411 predicate(AllocatePrefetchStyle == 3);
6412 ins_cost(MEMORY_REF_COST);
6414 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6415 size(4);
6416 ins_encode %{
6417 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6418 __ dcbz($src$$Register, $mem$$base$$Register);
6419 %}
6420 ins_pipe(pipe_class_memory);
6421 %}
6423 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6424 match(PrefetchAllocation mem);
6425 predicate(AllocatePrefetchStyle == 3);
6426 ins_cost(MEMORY_REF_COST);
6428 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6429 size(4);
6430 ins_encode %{
6431 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6432 __ dcbz($mem$$base$$Register);
6433 %}
6434 ins_pipe(pipe_class_memory);
6435 %}
6437 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6438 match(PrefetchAllocation (AddP mem src));
6439 predicate(AllocatePrefetchStyle != 3);
6440 ins_cost(MEMORY_REF_COST);
6442 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6443 size(4);
6444 ins_encode %{
6445 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6446 __ dcbtst($src$$Register, $mem$$base$$Register);
6447 %}
6448 ins_pipe(pipe_class_memory);
6449 %}
6451 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6452 match(PrefetchAllocation mem);
6453 predicate(AllocatePrefetchStyle != 3);
6454 ins_cost(MEMORY_REF_COST);
6456 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6457 size(4);
6458 ins_encode %{
6459 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6460 __ dcbtst($mem$$base$$Register);
6461 %}
6462 ins_pipe(pipe_class_memory);
6463 %}
6465 //----------Store Instructions-------------------------------------------------
6467 // Store Byte
6468 instruct storeB(memory mem, iRegIsrc src) %{
6469 match(Set mem (StoreB mem src));
6470 ins_cost(MEMORY_REF_COST);
6472 format %{ "STB $src, $mem \t// byte" %}
6473 size(4);
6474 ins_encode %{
6475 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6476 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6477 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6478 %}
6479 ins_pipe(pipe_class_memory);
6480 %}
6482 // Store Char/Short
6483 instruct storeC(memory mem, iRegIsrc src) %{
6484 match(Set mem (StoreC mem src));
6485 ins_cost(MEMORY_REF_COST);
6487 format %{ "STH $src, $mem \t// short" %}
6488 size(4);
6489 ins_encode %{
6490 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6491 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6492 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6493 %}
6494 ins_pipe(pipe_class_memory);
6495 %}
6497 // Store Integer
6498 instruct storeI(memory mem, iRegIsrc src) %{
6499 match(Set mem (StoreI mem src));
6500 ins_cost(MEMORY_REF_COST);
6502 format %{ "STW $src, $mem" %}
6503 size(4);
6504 ins_encode( enc_stw(src, mem) );
6505 ins_pipe(pipe_class_memory);
6506 %}
6508 // ConvL2I + StoreI.
6509 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6510 match(Set mem (StoreI mem (ConvL2I src)));
6511 ins_cost(MEMORY_REF_COST);
6513 format %{ "STW l2i($src), $mem" %}
6514 size(4);
6515 ins_encode( enc_stw(src, mem) );
6516 ins_pipe(pipe_class_memory);
6517 %}
6519 // Store Long
6520 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6521 match(Set mem (StoreL mem src));
6522 ins_cost(MEMORY_REF_COST);
6524 format %{ "STD $src, $mem \t// long" %}
6525 size(4);
6526 ins_encode( enc_std(src, mem) );
6527 ins_pipe(pipe_class_memory);
6528 %}
6530 // Store super word nodes.
6532 // Store Aligned Packed Byte long register to memory
6533 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6534 predicate(n->as_StoreVector()->memory_size() == 8);
6535 match(Set mem (StoreVector mem src));
6536 ins_cost(MEMORY_REF_COST);
6538 format %{ "STD $mem, $src \t// packed8B" %}
6539 size(4);
6540 ins_encode( enc_std(src, mem) );
6541 ins_pipe(pipe_class_memory);
6542 %}
6544 // Store Compressed Oop
6545 instruct storeN(memory dst, iRegN_P2N src) %{
6546 match(Set dst (StoreN dst src));
6547 ins_cost(MEMORY_REF_COST);
6549 format %{ "STW $src, $dst \t// compressed oop" %}
6550 size(4);
6551 ins_encode( enc_stw(src, dst) );
6552 ins_pipe(pipe_class_memory);
6553 %}
6555 // Store Compressed KLass
6556 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6557 match(Set dst (StoreNKlass dst src));
6558 ins_cost(MEMORY_REF_COST);
6560 format %{ "STW $src, $dst \t// compressed klass" %}
6561 size(4);
6562 ins_encode( enc_stw(src, dst) );
6563 ins_pipe(pipe_class_memory);
6564 %}
6566 // Store Pointer
6567 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6568 match(Set dst (StoreP dst src));
6569 ins_cost(MEMORY_REF_COST);
6571 format %{ "STD $src, $dst \t// ptr" %}
6572 size(4);
6573 ins_encode( enc_std(src, dst) );
6574 ins_pipe(pipe_class_memory);
6575 %}
6577 // Store Float
6578 instruct storeF(memory mem, regF src) %{
6579 match(Set mem (StoreF mem src));
6580 ins_cost(MEMORY_REF_COST);
6582 format %{ "STFS $src, $mem" %}
6583 size(4);
6584 ins_encode( enc_stfs(src, mem) );
6585 ins_pipe(pipe_class_memory);
6586 %}
6588 // Store Double
6589 instruct storeD(memory mem, regD src) %{
6590 match(Set mem (StoreD mem src));
6591 ins_cost(MEMORY_REF_COST);
6593 format %{ "STFD $src, $mem" %}
6594 size(4);
6595 ins_encode( enc_stfd(src, mem) );
6596 ins_pipe(pipe_class_memory);
6597 %}
6599 //----------Store Instructions With Zeros--------------------------------------
6601 // Card-mark for CMS garbage collection.
6602 // This cardmark does an optimization so that it must not always
6603 // do a releasing store. For this, it gets the address of
6604 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6605 // (Using releaseFieldAddr in the match rule is a hack.)
6606 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6607 match(Set mem (StoreCM mem releaseFieldAddr));
6608 predicate(false);
6609 ins_cost(MEMORY_REF_COST);
6611 // See loadConP.
6612 ins_cannot_rematerialize(true);
6614 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6615 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6616 ins_pipe(pipe_class_memory);
6617 %}
6619 // Card-mark for CMS garbage collection.
6620 // This cardmark does an optimization so that it must not always
6621 // do a releasing store. For this, it needs the constant address of
6622 // CMSCollectorCardTableModRefBSExt::_requires_release.
6623 // This constant address is split off here by expand so we can use
6624 // adlc / matcher functionality to load it from the constant section.
6625 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6626 match(Set mem (StoreCM mem zero));
6627 predicate(UseConcMarkSweepGC);
6629 expand %{
6630 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6631 iRegLdst releaseFieldAddress;
6632 loadConL_Ex(releaseFieldAddress, baseImm);
6633 storeCM_CMS(mem, releaseFieldAddress);
6634 %}
6635 %}
6637 instruct storeCM_G1(memory mem, immI_0 zero) %{
6638 match(Set mem (StoreCM mem zero));
6639 predicate(UseG1GC);
6640 ins_cost(MEMORY_REF_COST);
6642 ins_cannot_rematerialize(true);
6644 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6645 size(8);
6646 ins_encode %{
6647 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6648 __ li(R0, 0);
6649 //__ release(); // G1: oops are allowed to get visible after dirty marking
6650 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6651 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6652 %}
6653 ins_pipe(pipe_class_memory);
6654 %}
6656 // Convert oop pointer into compressed form.
6658 // Nodes for postalloc expand.
6660 // Shift node for expand.
6661 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6662 // The match rule is needed to make it a 'MachTypeNode'!
6663 match(Set dst (EncodeP src));
6664 predicate(false);
6666 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6667 size(4);
6668 ins_encode %{
6669 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6670 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6671 %}
6672 ins_pipe(pipe_class_default);
6673 %}
6675 // Add node for expand.
6676 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6677 // The match rule is needed to make it a 'MachTypeNode'!
6678 match(Set dst (EncodeP src));
6679 predicate(false);
6681 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6682 size(4);
6683 ins_encode %{
6684 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6685 __ subf($dst$$Register, R30, $src$$Register);
6686 %}
6687 ins_pipe(pipe_class_default);
6688 %}
6690 // Conditional sub base.
6691 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6692 // The match rule is needed to make it a 'MachTypeNode'!
6693 match(Set dst (EncodeP (Binary crx src1)));
6694 predicate(false);
6696 ins_variable_size_depending_on_alignment(true);
6698 format %{ "BEQ $crx, done\n\t"
6699 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6700 "done:" %}
6701 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6702 ins_encode %{
6703 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6704 Label done;
6705 __ beq($crx$$CondRegister, done);
6706 __ subf($dst$$Register, R30, $src1$$Register);
6707 // TODO PPC port __ endgroup_if_needed(_size == 12);
6708 __ bind(done);
6709 %}
6710 ins_pipe(pipe_class_default);
6711 %}
6713 // Power 7 can use isel instruction
6714 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6715 // The match rule is needed to make it a 'MachTypeNode'!
6716 match(Set dst (EncodeP (Binary crx src1)));
6717 predicate(false);
6719 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6720 size(4);
6721 ins_encode %{
6722 // This is a Power7 instruction for which no machine description exists.
6723 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6724 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6725 %}
6726 ins_pipe(pipe_class_default);
6727 %}
6729 // base != 0
6730 // 32G aligned narrow oop base.
6731 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6732 match(Set dst (EncodeP src));
6733 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6735 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6736 size(4);
6737 ins_encode %{
6738 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6739 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6740 %}
6741 ins_pipe(pipe_class_default);
6742 %}
6744 // shift != 0, base != 0
6745 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6746 match(Set dst (EncodeP src));
6747 effect(TEMP crx);
6748 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6749 Universe::narrow_oop_shift() != 0 &&
6750 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6752 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6753 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6754 %}
6756 // shift != 0, base != 0
6757 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6758 match(Set dst (EncodeP src));
6759 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6760 Universe::narrow_oop_shift() != 0 &&
6761 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6763 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6764 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6765 %}
6767 // shift != 0, base == 0
6768 // TODO: This is the same as encodeP_shift. Merge!
6769 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6770 match(Set dst (EncodeP src));
6771 predicate(Universe::narrow_oop_shift() != 0 &&
6772 Universe::narrow_oop_base() ==0);
6774 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6775 size(4);
6776 ins_encode %{
6777 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6778 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6779 %}
6780 ins_pipe(pipe_class_default);
6781 %}
6783 // Compressed OOPs with narrow_oop_shift == 0.
6784 // shift == 0, base == 0
6785 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6786 match(Set dst (EncodeP src));
6787 predicate(Universe::narrow_oop_shift() == 0);
6789 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6790 // variable size, 0 or 4.
6791 ins_encode %{
6792 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6793 __ mr_if_needed($dst$$Register, $src$$Register);
6794 %}
6795 ins_pipe(pipe_class_default);
6796 %}
6798 // Decode nodes.
6800 // Shift node for expand.
6801 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6802 // The match rule is needed to make it a 'MachTypeNode'!
6803 match(Set dst (DecodeN src));
6804 predicate(false);
6806 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6807 size(4);
6808 ins_encode %{
6809 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6810 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6811 %}
6812 ins_pipe(pipe_class_default);
6813 %}
6815 // Add node for expand.
6816 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6817 // The match rule is needed to make it a 'MachTypeNode'!
6818 match(Set dst (DecodeN src));
6819 predicate(false);
6821 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6822 size(4);
6823 ins_encode %{
6824 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6825 __ add($dst$$Register, $src$$Register, R30);
6826 %}
6827 ins_pipe(pipe_class_default);
6828 %}
6830 // conditianal add base for expand
6831 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6832 // The match rule is needed to make it a 'MachTypeNode'!
6833 // NOTICE that the rule is nonsense - we just have to make sure that:
6834 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6835 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6836 match(Set dst (DecodeN (Binary crx src1)));
6837 predicate(false);
6839 ins_variable_size_depending_on_alignment(true);
6841 format %{ "BEQ $crx, done\n\t"
6842 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6843 "done:" %}
6844 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6845 ins_encode %{
6846 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6847 Label done;
6848 __ beq($crx$$CondRegister, done);
6849 __ add($dst$$Register, $src1$$Register, R30);
6850 // TODO PPC port __ endgroup_if_needed(_size == 12);
6851 __ bind(done);
6852 %}
6853 ins_pipe(pipe_class_default);
6854 %}
6856 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6857 // The match rule is needed to make it a 'MachTypeNode'!
6858 // NOTICE that the rule is nonsense - we just have to make sure that:
6859 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6860 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6861 match(Set dst (DecodeN (Binary crx src1)));
6862 predicate(false);
6864 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6865 size(4);
6866 ins_encode %{
6867 // This is a Power7 instruction for which no machine description exists.
6868 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6869 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6870 %}
6871 ins_pipe(pipe_class_default);
6872 %}
6874 // shift != 0, base != 0
6875 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6876 match(Set dst (DecodeN src));
6877 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6878 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6879 Universe::narrow_oop_shift() != 0 &&
6880 Universe::narrow_oop_base() != 0);
6881 effect(TEMP crx);
6883 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6884 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6885 %}
6887 // shift != 0, base == 0
6888 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6889 match(Set dst (DecodeN src));
6890 predicate(Universe::narrow_oop_shift() != 0 &&
6891 Universe::narrow_oop_base() == 0);
6893 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6894 size(4);
6895 ins_encode %{
6896 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6897 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6898 %}
6899 ins_pipe(pipe_class_default);
6900 %}
6902 // src != 0, shift != 0, base != 0
6903 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6904 match(Set dst (DecodeN src));
6905 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6906 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6907 Universe::narrow_oop_shift() != 0 &&
6908 Universe::narrow_oop_base() != 0);
6910 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6911 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6912 %}
6914 // Compressed OOPs with narrow_oop_shift == 0.
6915 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6916 match(Set dst (DecodeN src));
6917 predicate(Universe::narrow_oop_shift() == 0);
6918 ins_cost(DEFAULT_COST);
6920 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6921 // variable size, 0 or 4.
6922 ins_encode %{
6923 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6924 __ mr_if_needed($dst$$Register, $src$$Register);
6925 %}
6926 ins_pipe(pipe_class_default);
6927 %}
6929 // Convert compressed oop into int for vectors alignment masking.
6930 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6931 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6932 predicate(Universe::narrow_oop_shift() == 0);
6933 ins_cost(DEFAULT_COST);
6935 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6936 // variable size, 0 or 4.
6937 ins_encode %{
6938 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6939 __ mr_if_needed($dst$$Register, $src$$Register);
6940 %}
6941 ins_pipe(pipe_class_default);
6942 %}
6944 // Convert klass pointer into compressed form.
6946 // Nodes for postalloc expand.
6948 // Shift node for expand.
6949 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6950 // The match rule is needed to make it a 'MachTypeNode'!
6951 match(Set dst (EncodePKlass src));
6952 predicate(false);
6954 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6955 size(4);
6956 ins_encode %{
6957 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6958 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6959 %}
6960 ins_pipe(pipe_class_default);
6961 %}
6963 // Add node for expand.
6964 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6965 // The match rule is needed to make it a 'MachTypeNode'!
6966 match(Set dst (EncodePKlass (Binary base src)));
6967 predicate(false);
6969 format %{ "SUB $dst, $base, $src \t// encode" %}
6970 size(4);
6971 ins_encode %{
6972 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6973 __ subf($dst$$Register, $base$$Register, $src$$Register);
6974 %}
6975 ins_pipe(pipe_class_default);
6976 %}
6978 // base != 0
6979 // 32G aligned narrow oop base.
6980 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6981 match(Set dst (EncodePKlass src));
6982 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6984 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6985 size(4);
6986 ins_encode %{
6987 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6988 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
6989 %}
6990 ins_pipe(pipe_class_default);
6991 %}
6993 // shift != 0, base != 0
6994 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6995 match(Set dst (EncodePKlass (Binary base src)));
6996 predicate(false);
6998 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6999 postalloc_expand %{
7000 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
7001 n1->add_req(n_region, n_base, n_src);
7002 n1->_opnds[0] = op_dst;
7003 n1->_opnds[1] = op_base;
7004 n1->_opnds[2] = op_src;
7005 n1->_bottom_type = _bottom_type;
7007 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
7008 n2->add_req(n_region, n1);
7009 n2->_opnds[0] = op_dst;
7010 n2->_opnds[1] = op_dst;
7011 n2->_bottom_type = _bottom_type;
7012 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7013 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7015 nodes->push(n1);
7016 nodes->push(n2);
7017 %}
7018 %}
7020 // shift != 0, base != 0
7021 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7022 match(Set dst (EncodePKlass src));
7023 //predicate(Universe::narrow_klass_shift() != 0 &&
7024 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7026 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7027 ins_cost(DEFAULT_COST*2); // Don't count constant.
7028 expand %{
7029 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7030 iRegLdst base;
7031 loadConL_Ex(base, baseImm);
7032 encodePKlass_not_null_Ex(dst, base, src);
7033 %}
7034 %}
7036 // Decode nodes.
7038 // Shift node for expand.
7039 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7040 // The match rule is needed to make it a 'MachTypeNode'!
7041 match(Set dst (DecodeNKlass src));
7042 predicate(false);
7044 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7045 size(4);
7046 ins_encode %{
7047 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7048 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7049 %}
7050 ins_pipe(pipe_class_default);
7051 %}
7053 // Add node for expand.
7055 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7056 // The match rule is needed to make it a 'MachTypeNode'!
7057 match(Set dst (DecodeNKlass (Binary base src)));
7058 predicate(false);
7060 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7061 size(4);
7062 ins_encode %{
7063 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7064 __ add($dst$$Register, $base$$Register, $src$$Register);
7065 %}
7066 ins_pipe(pipe_class_default);
7067 %}
7069 // src != 0, shift != 0, base != 0
7070 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7071 match(Set dst (DecodeNKlass (Binary base src)));
7072 //effect(kill src); // We need a register for the immediate result after shifting.
7073 predicate(false);
7075 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7076 postalloc_expand %{
7077 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7078 n1->add_req(n_region, n_base, n_src);
7079 n1->_opnds[0] = op_dst;
7080 n1->_opnds[1] = op_base;
7081 n1->_opnds[2] = op_src;
7082 n1->_bottom_type = _bottom_type;
7084 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7085 n2->add_req(n_region, n1);
7086 n2->_opnds[0] = op_dst;
7087 n2->_opnds[1] = op_dst;
7088 n2->_bottom_type = _bottom_type;
7090 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7091 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7093 nodes->push(n1);
7094 nodes->push(n2);
7095 %}
7096 %}
7098 // src != 0, shift != 0, base != 0
7099 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7100 match(Set dst (DecodeNKlass src));
7101 // predicate(Universe::narrow_klass_shift() != 0 &&
7102 // Universe::narrow_klass_base() != 0);
7104 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7106 ins_cost(DEFAULT_COST*2); // Don't count constant.
7107 expand %{
7108 // We add first, then we shift. Like this, we can get along with one register less.
7109 // But we have to load the base pre-shifted.
7110 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7111 iRegLdst base;
7112 loadConL_Ex(base, baseImm);
7113 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7114 %}
7115 %}
7117 //----------MemBar Instructions-----------------------------------------------
7118 // Memory barrier flavors
7120 instruct membar_acquire() %{
7121 match(LoadFence);
7122 ins_cost(4*MEMORY_REF_COST);
7124 format %{ "MEMBAR-acquire" %}
7125 size(4);
7126 ins_encode %{
7127 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7128 __ acquire();
7129 %}
7130 ins_pipe(pipe_class_default);
7131 %}
7133 instruct unnecessary_membar_acquire() %{
7134 match(MemBarAcquire);
7135 ins_cost(0);
7137 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7138 size(0);
7139 ins_encode( /*empty*/ );
7140 ins_pipe(pipe_class_default);
7141 %}
7143 instruct membar_acquire_lock() %{
7144 match(MemBarAcquireLock);
7145 ins_cost(0);
7147 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7148 size(0);
7149 ins_encode( /*empty*/ );
7150 ins_pipe(pipe_class_default);
7151 %}
7153 instruct membar_release() %{
7154 match(MemBarRelease);
7155 match(StoreFence);
7156 ins_cost(4*MEMORY_REF_COST);
7158 format %{ "MEMBAR-release" %}
7159 size(4);
7160 ins_encode %{
7161 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7162 __ release();
7163 %}
7164 ins_pipe(pipe_class_default);
7165 %}
7167 instruct membar_storestore() %{
7168 match(MemBarStoreStore);
7169 ins_cost(4*MEMORY_REF_COST);
7171 format %{ "MEMBAR-store-store" %}
7172 size(4);
7173 ins_encode %{
7174 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7175 __ membar(Assembler::StoreStore);
7176 %}
7177 ins_pipe(pipe_class_default);
7178 %}
7180 instruct membar_release_lock() %{
7181 match(MemBarReleaseLock);
7182 ins_cost(0);
7184 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7185 size(0);
7186 ins_encode( /*empty*/ );
7187 ins_pipe(pipe_class_default);
7188 %}
7190 instruct membar_volatile() %{
7191 match(MemBarVolatile);
7192 ins_cost(4*MEMORY_REF_COST);
7194 format %{ "MEMBAR-volatile" %}
7195 size(4);
7196 ins_encode %{
7197 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7198 __ fence();
7199 %}
7200 ins_pipe(pipe_class_default);
7201 %}
7203 // This optimization is wrong on PPC. The following pattern is not supported:
7204 // MemBarVolatile
7205 // ^ ^
7206 // | |
7207 // CtrlProj MemProj
7208 // ^ ^
7209 // | |
7210 // | Load
7211 // |
7212 // MemBarVolatile
7213 //
7214 // The first MemBarVolatile could get optimized out! According to
7215 // Vladimir, this pattern can not occur on Oracle platforms.
7216 // However, it does occur on PPC64 (because of membars in
7217 // inline_unsafe_load_store).
7218 //
7219 // Add this node again if we found a good solution for inline_unsafe_load_store().
7220 // Don't forget to look at the implementation of post_store_load_barrier again,
7221 // we did other fixes in that method.
7222 //instruct unnecessary_membar_volatile() %{
7223 // match(MemBarVolatile);
7224 // predicate(Matcher::post_store_load_barrier(n));
7225 // ins_cost(0);
7226 //
7227 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7228 // size(0);
7229 // ins_encode( /*empty*/ );
7230 // ins_pipe(pipe_class_default);
7231 //%}
7233 instruct membar_CPUOrder() %{
7234 match(MemBarCPUOrder);
7235 ins_cost(0);
7237 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7238 size(0);
7239 ins_encode( /*empty*/ );
7240 ins_pipe(pipe_class_default);
7241 %}
7243 //----------Conditional Move---------------------------------------------------
7245 // Cmove using isel.
7246 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7247 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7248 predicate(VM_Version::has_isel());
7249 ins_cost(DEFAULT_COST);
7251 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7252 size(4);
7253 ins_encode %{
7254 // This is a Power7 instruction for which no machine description
7255 // exists. Anyways, the scheduler should be off on Power7.
7256 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7257 int cc = $cmp$$cmpcode;
7258 __ isel($dst$$Register, $crx$$CondRegister,
7259 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7260 %}
7261 ins_pipe(pipe_class_default);
7262 %}
7264 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7265 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7266 predicate(!VM_Version::has_isel());
7267 ins_cost(DEFAULT_COST+BRANCH_COST);
7269 ins_variable_size_depending_on_alignment(true);
7271 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7272 // Worst case is branch + move + stop, no stop without scheduler
7273 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7274 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7275 ins_pipe(pipe_class_default);
7276 %}
7278 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7279 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7280 ins_cost(DEFAULT_COST+BRANCH_COST);
7282 ins_variable_size_depending_on_alignment(true);
7284 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7285 // Worst case is branch + move + stop, no stop without scheduler
7286 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7287 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7288 ins_pipe(pipe_class_default);
7289 %}
7291 // Cmove using isel.
7292 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7293 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7294 predicate(VM_Version::has_isel());
7295 ins_cost(DEFAULT_COST);
7297 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7298 size(4);
7299 ins_encode %{
7300 // This is a Power7 instruction for which no machine description
7301 // exists. Anyways, the scheduler should be off on Power7.
7302 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7303 int cc = $cmp$$cmpcode;
7304 __ isel($dst$$Register, $crx$$CondRegister,
7305 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7306 %}
7307 ins_pipe(pipe_class_default);
7308 %}
7310 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7311 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7312 predicate(!VM_Version::has_isel());
7313 ins_cost(DEFAULT_COST+BRANCH_COST);
7315 ins_variable_size_depending_on_alignment(true);
7317 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7318 // Worst case is branch + move + stop, no stop without scheduler.
7319 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7320 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7321 ins_pipe(pipe_class_default);
7322 %}
7324 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7325 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7326 ins_cost(DEFAULT_COST+BRANCH_COST);
7328 ins_variable_size_depending_on_alignment(true);
7330 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7331 // Worst case is branch + move + stop, no stop without scheduler.
7332 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7333 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7334 ins_pipe(pipe_class_default);
7335 %}
7337 // Cmove using isel.
7338 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7339 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7340 predicate(VM_Version::has_isel());
7341 ins_cost(DEFAULT_COST);
7343 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7344 size(4);
7345 ins_encode %{
7346 // This is a Power7 instruction for which no machine description
7347 // exists. Anyways, the scheduler should be off on Power7.
7348 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7349 int cc = $cmp$$cmpcode;
7350 __ isel($dst$$Register, $crx$$CondRegister,
7351 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7352 %}
7353 ins_pipe(pipe_class_default);
7354 %}
7356 // Conditional move for RegN. Only cmov(reg, reg).
7357 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7358 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7359 predicate(!VM_Version::has_isel());
7360 ins_cost(DEFAULT_COST+BRANCH_COST);
7362 ins_variable_size_depending_on_alignment(true);
7364 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7365 // Worst case is branch + move + stop, no stop without scheduler.
7366 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7367 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7368 ins_pipe(pipe_class_default);
7369 %}
7371 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7372 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7373 ins_cost(DEFAULT_COST+BRANCH_COST);
7375 ins_variable_size_depending_on_alignment(true);
7377 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7378 // Worst case is branch + move + stop, no stop without scheduler.
7379 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7380 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7381 ins_pipe(pipe_class_default);
7382 %}
7384 // Cmove using isel.
7385 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7386 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7387 predicate(VM_Version::has_isel());
7388 ins_cost(DEFAULT_COST);
7390 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7391 size(4);
7392 ins_encode %{
7393 // This is a Power7 instruction for which no machine description
7394 // exists. Anyways, the scheduler should be off on Power7.
7395 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7396 int cc = $cmp$$cmpcode;
7397 __ isel($dst$$Register, $crx$$CondRegister,
7398 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7399 %}
7400 ins_pipe(pipe_class_default);
7401 %}
7403 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7404 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7405 predicate(!VM_Version::has_isel());
7406 ins_cost(DEFAULT_COST+BRANCH_COST);
7408 ins_variable_size_depending_on_alignment(true);
7410 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7411 // Worst case is branch + move + stop, no stop without scheduler.
7412 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7413 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7414 ins_pipe(pipe_class_default);
7415 %}
7417 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7418 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7419 ins_cost(DEFAULT_COST+BRANCH_COST);
7421 ins_variable_size_depending_on_alignment(true);
7423 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7424 // Worst case is branch + move + stop, no stop without scheduler.
7425 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7426 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7427 ins_pipe(pipe_class_default);
7428 %}
7430 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7431 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7432 ins_cost(DEFAULT_COST+BRANCH_COST);
7434 ins_variable_size_depending_on_alignment(true);
7436 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7437 // Worst case is branch + move + stop, no stop without scheduler.
7438 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7439 ins_encode %{
7440 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7441 Label done;
7442 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7443 // Branch if not (cmp crx).
7444 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7445 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7446 // TODO PPC port __ endgroup_if_needed(_size == 12);
7447 __ bind(done);
7448 %}
7449 ins_pipe(pipe_class_default);
7450 %}
7452 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7453 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7454 ins_cost(DEFAULT_COST+BRANCH_COST);
7456 ins_variable_size_depending_on_alignment(true);
7458 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7459 // Worst case is branch + move + stop, no stop without scheduler.
7460 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7461 ins_encode %{
7462 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7463 Label done;
7464 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7465 // Branch if not (cmp crx).
7466 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7467 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7468 // TODO PPC port __ endgroup_if_needed(_size == 12);
7469 __ bind(done);
7470 %}
7471 ins_pipe(pipe_class_default);
7472 %}
7474 //----------Conditional_store--------------------------------------------------
7475 // Conditional-store of the updated heap-top.
7476 // Used during allocation of the shared heap.
7477 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7479 // As compareAndSwapL, but return flag register instead of boolean value in
7480 // int register.
7481 // Used by sun/misc/AtomicLongCSImpl.java.
7482 // Mem_ptr must be a memory operand, else this node does not get
7483 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7484 // can be rematerialized which leads to errors.
7485 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7486 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7487 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7488 ins_encode %{
7489 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7490 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7491 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7492 noreg, NULL, true);
7493 %}
7494 ins_pipe(pipe_class_default);
7495 %}
7497 // As compareAndSwapP, but return flag register instead of boolean value in
7498 // int register.
7499 // This instruction is matched if UseTLAB is off.
7500 // Mem_ptr must be a memory operand, else this node does not get
7501 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7502 // can be rematerialized which leads to errors.
7503 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7504 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7505 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7506 ins_encode %{
7507 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7508 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7509 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7510 noreg, NULL, true);
7511 %}
7512 ins_pipe(pipe_class_default);
7513 %}
7515 // Implement LoadPLocked. Must be ordered against changes of the memory location
7516 // by storePConditional.
7517 // Don't know whether this is ever used.
7518 instruct loadPLocked(iRegPdst dst, memory mem) %{
7519 match(Set dst (LoadPLocked mem));
7520 ins_cost(MEMORY_REF_COST);
7522 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7523 "TWI $dst\n\t"
7524 "ISYNC" %}
7525 size(12);
7526 ins_encode( enc_ld_ac(dst, mem) );
7527 ins_pipe(pipe_class_memory);
7528 %}
7530 //----------Compare-And-Swap---------------------------------------------------
7532 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7533 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7534 // matched.
7536 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7537 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7538 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7539 // Variable size: instruction count smaller if regs are disjoint.
7540 ins_encode %{
7541 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7542 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7543 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7544 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7545 $res$$Register, true);
7546 %}
7547 ins_pipe(pipe_class_default);
7548 %}
7550 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7551 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7552 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7553 // Variable size: instruction count smaller if regs are disjoint.
7554 ins_encode %{
7555 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7556 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7557 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7558 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7559 $res$$Register, true);
7560 %}
7561 ins_pipe(pipe_class_default);
7562 %}
7564 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7565 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7566 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7567 // Variable size: instruction count smaller if regs are disjoint.
7568 ins_encode %{
7569 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7570 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7571 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7572 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7573 $res$$Register, NULL, true);
7574 %}
7575 ins_pipe(pipe_class_default);
7576 %}
7578 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7579 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7580 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7581 // Variable size: instruction count smaller if regs are disjoint.
7582 ins_encode %{
7583 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7584 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7585 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7586 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7587 $res$$Register, NULL, true);
7588 %}
7589 ins_pipe(pipe_class_default);
7590 %}
7592 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7593 match(Set res (GetAndAddI mem_ptr src));
7594 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7595 // Variable size: instruction count smaller if regs are disjoint.
7596 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7597 ins_pipe(pipe_class_default);
7598 %}
7600 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7601 match(Set res (GetAndAddL mem_ptr src));
7602 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7603 // Variable size: instruction count smaller if regs are disjoint.
7604 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7605 ins_pipe(pipe_class_default);
7606 %}
7608 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7609 match(Set res (GetAndSetI mem_ptr src));
7610 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7611 // Variable size: instruction count smaller if regs are disjoint.
7612 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7613 ins_pipe(pipe_class_default);
7614 %}
7616 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7617 match(Set res (GetAndSetL mem_ptr src));
7618 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7619 // Variable size: instruction count smaller if regs are disjoint.
7620 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7621 ins_pipe(pipe_class_default);
7622 %}
7624 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7625 match(Set res (GetAndSetP mem_ptr src));
7626 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7627 // Variable size: instruction count smaller if regs are disjoint.
7628 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7629 ins_pipe(pipe_class_default);
7630 %}
7632 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7633 match(Set res (GetAndSetN mem_ptr src));
7634 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7635 // Variable size: instruction count smaller if regs are disjoint.
7636 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7637 ins_pipe(pipe_class_default);
7638 %}
7640 //----------Arithmetic Instructions--------------------------------------------
7641 // Addition Instructions
7643 // Register Addition
7644 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7645 match(Set dst (AddI src1 src2));
7646 format %{ "ADD $dst, $src1, $src2" %}
7647 size(4);
7648 ins_encode %{
7649 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7650 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7651 %}
7652 ins_pipe(pipe_class_default);
7653 %}
7655 // Expand does not work with above instruct. (??)
7656 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7657 // no match-rule
7658 effect(DEF dst, USE src1, USE src2);
7659 format %{ "ADD $dst, $src1, $src2" %}
7660 size(4);
7661 ins_encode %{
7662 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7663 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7664 %}
7665 ins_pipe(pipe_class_default);
7666 %}
7668 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7669 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7670 ins_cost(DEFAULT_COST*3);
7672 expand %{
7673 // FIXME: we should do this in the ideal world.
7674 iRegIdst tmp1;
7675 iRegIdst tmp2;
7676 addI_reg_reg(tmp1, src1, src2);
7677 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7678 addI_reg_reg(dst, tmp1, tmp2);
7679 %}
7680 %}
7682 // Immediate Addition
7683 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7684 match(Set dst (AddI src1 src2));
7685 format %{ "ADDI $dst, $src1, $src2" %}
7686 size(4);
7687 ins_encode %{
7688 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7689 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7690 %}
7691 ins_pipe(pipe_class_default);
7692 %}
7694 // Immediate Addition with 16-bit shifted operand
7695 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7696 match(Set dst (AddI src1 src2));
7697 format %{ "ADDIS $dst, $src1, $src2" %}
7698 size(4);
7699 ins_encode %{
7700 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7701 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7702 %}
7703 ins_pipe(pipe_class_default);
7704 %}
7706 // Long Addition
7707 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7708 match(Set dst (AddL src1 src2));
7709 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7710 size(4);
7711 ins_encode %{
7712 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7713 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7714 %}
7715 ins_pipe(pipe_class_default);
7716 %}
7718 // Expand does not work with above instruct. (??)
7719 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7720 // no match-rule
7721 effect(DEF dst, USE src1, USE src2);
7722 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7723 size(4);
7724 ins_encode %{
7725 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7726 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7727 %}
7728 ins_pipe(pipe_class_default);
7729 %}
7731 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7732 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7733 ins_cost(DEFAULT_COST*3);
7735 expand %{
7736 // FIXME: we should do this in the ideal world.
7737 iRegLdst tmp1;
7738 iRegLdst tmp2;
7739 addL_reg_reg(tmp1, src1, src2);
7740 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7741 addL_reg_reg(dst, tmp1, tmp2);
7742 %}
7743 %}
7745 // AddL + ConvL2I.
7746 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7747 match(Set dst (ConvL2I (AddL src1 src2)));
7749 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7750 size(4);
7751 ins_encode %{
7752 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7753 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7754 %}
7755 ins_pipe(pipe_class_default);
7756 %}
7758 // No constant pool entries required.
7759 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7760 match(Set dst (AddL src1 src2));
7762 format %{ "ADDI $dst, $src1, $src2" %}
7763 size(4);
7764 ins_encode %{
7765 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7766 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7767 %}
7768 ins_pipe(pipe_class_default);
7769 %}
7771 // Long Immediate Addition with 16-bit shifted operand.
7772 // No constant pool entries required.
7773 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7774 match(Set dst (AddL src1 src2));
7776 format %{ "ADDIS $dst, $src1, $src2" %}
7777 size(4);
7778 ins_encode %{
7779 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7780 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7781 %}
7782 ins_pipe(pipe_class_default);
7783 %}
7785 // Pointer Register Addition
7786 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7787 match(Set dst (AddP src1 src2));
7788 format %{ "ADD $dst, $src1, $src2" %}
7789 size(4);
7790 ins_encode %{
7791 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7792 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7793 %}
7794 ins_pipe(pipe_class_default);
7795 %}
7797 // Pointer Immediate Addition
7798 // No constant pool entries required.
7799 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7800 match(Set dst (AddP src1 src2));
7802 format %{ "ADDI $dst, $src1, $src2" %}
7803 size(4);
7804 ins_encode %{
7805 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7806 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7807 %}
7808 ins_pipe(pipe_class_default);
7809 %}
7811 // Pointer Immediate Addition with 16-bit shifted operand.
7812 // No constant pool entries required.
7813 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7814 match(Set dst (AddP src1 src2));
7816 format %{ "ADDIS $dst, $src1, $src2" %}
7817 size(4);
7818 ins_encode %{
7819 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7820 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7821 %}
7822 ins_pipe(pipe_class_default);
7823 %}
7825 //---------------------
7826 // Subtraction Instructions
7828 // Register Subtraction
7829 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7830 match(Set dst (SubI src1 src2));
7831 format %{ "SUBF $dst, $src2, $src1" %}
7832 size(4);
7833 ins_encode %{
7834 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7835 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7836 %}
7837 ins_pipe(pipe_class_default);
7838 %}
7840 // Immediate Subtraction
7841 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7842 // so this rule seems to be unused.
7843 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7844 match(Set dst (SubI src1 src2));
7845 format %{ "SUBI $dst, $src1, $src2" %}
7846 size(4);
7847 ins_encode %{
7848 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7849 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7850 %}
7851 ins_pipe(pipe_class_default);
7852 %}
7854 // SubI from constant (using subfic).
7855 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7856 match(Set dst (SubI src1 src2));
7857 format %{ "SUBI $dst, $src1, $src2" %}
7859 size(4);
7860 ins_encode %{
7861 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7862 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7863 %}
7864 ins_pipe(pipe_class_default);
7865 %}
7867 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7868 // positive integers and 0xF...F for negative ones.
7869 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7870 // no match-rule, false predicate
7871 effect(DEF dst, USE src);
7872 predicate(false);
7874 format %{ "SRAWI $dst, $src, #31" %}
7875 size(4);
7876 ins_encode %{
7877 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7878 __ srawi($dst$$Register, $src$$Register, 0x1f);
7879 %}
7880 ins_pipe(pipe_class_default);
7881 %}
7883 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7884 match(Set dst (AbsI src));
7885 ins_cost(DEFAULT_COST*3);
7887 expand %{
7888 iRegIdst tmp1;
7889 iRegIdst tmp2;
7890 signmask32I_regI(tmp1, src);
7891 xorI_reg_reg(tmp2, tmp1, src);
7892 subI_reg_reg(dst, tmp2, tmp1);
7893 %}
7894 %}
7896 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7897 match(Set dst (SubI zero src2));
7898 format %{ "NEG $dst, $src2" %}
7899 size(4);
7900 ins_encode %{
7901 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7902 __ neg($dst$$Register, $src2$$Register);
7903 %}
7904 ins_pipe(pipe_class_default);
7905 %}
7907 // Long subtraction
7908 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7909 match(Set dst (SubL src1 src2));
7910 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7911 size(4);
7912 ins_encode %{
7913 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7914 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7915 %}
7916 ins_pipe(pipe_class_default);
7917 %}
7919 // SubL + convL2I.
7920 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7921 match(Set dst (ConvL2I (SubL src1 src2)));
7923 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7924 size(4);
7925 ins_encode %{
7926 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7927 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7928 %}
7929 ins_pipe(pipe_class_default);
7930 %}
7932 // Immediate Subtraction
7933 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7934 // so this rule seems to be unused.
7935 // No constant pool entries required.
7936 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7937 match(Set dst (SubL src1 src2));
7939 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7940 size(4);
7941 ins_encode %{
7942 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7943 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7944 %}
7945 ins_pipe(pipe_class_default);
7946 %}
7948 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7949 // positive longs and 0xF...F for negative ones.
7950 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7951 // no match-rule, false predicate
7952 effect(DEF dst, USE src);
7953 predicate(false);
7955 format %{ "SRADI $dst, $src, #63" %}
7956 size(4);
7957 ins_encode %{
7958 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7959 __ sradi($dst$$Register, $src$$Register, 0x3f);
7960 %}
7961 ins_pipe(pipe_class_default);
7962 %}
7964 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7965 // positive longs and 0xF...F for negative ones.
7966 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7967 // no match-rule, false predicate
7968 effect(DEF dst, USE src);
7969 predicate(false);
7971 format %{ "SRADI $dst, $src, #63" %}
7972 size(4);
7973 ins_encode %{
7974 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7975 __ sradi($dst$$Register, $src$$Register, 0x3f);
7976 %}
7977 ins_pipe(pipe_class_default);
7978 %}
7980 // Long negation
7981 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7982 match(Set dst (SubL zero src2));
7983 format %{ "NEG $dst, $src2 \t// long" %}
7984 size(4);
7985 ins_encode %{
7986 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7987 __ neg($dst$$Register, $src2$$Register);
7988 %}
7989 ins_pipe(pipe_class_default);
7990 %}
7992 // NegL + ConvL2I.
7993 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7994 match(Set dst (ConvL2I (SubL zero src2)));
7996 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7997 size(4);
7998 ins_encode %{
7999 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8000 __ neg($dst$$Register, $src2$$Register);
8001 %}
8002 ins_pipe(pipe_class_default);
8003 %}
8005 // Multiplication Instructions
8006 // Integer Multiplication
8008 // Register Multiplication
8009 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8010 match(Set dst (MulI src1 src2));
8011 ins_cost(DEFAULT_COST);
8013 format %{ "MULLW $dst, $src1, $src2" %}
8014 size(4);
8015 ins_encode %{
8016 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8017 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8018 %}
8019 ins_pipe(pipe_class_default);
8020 %}
8022 // Immediate Multiplication
8023 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8024 match(Set dst (MulI src1 src2));
8025 ins_cost(DEFAULT_COST);
8027 format %{ "MULLI $dst, $src1, $src2" %}
8028 size(4);
8029 ins_encode %{
8030 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8031 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8032 %}
8033 ins_pipe(pipe_class_default);
8034 %}
8036 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8037 match(Set dst (MulL src1 src2));
8038 ins_cost(DEFAULT_COST);
8040 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8041 size(4);
8042 ins_encode %{
8043 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8044 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8045 %}
8046 ins_pipe(pipe_class_default);
8047 %}
8049 // Multiply high for optimized long division by constant.
8050 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8051 match(Set dst (MulHiL src1 src2));
8052 ins_cost(DEFAULT_COST);
8054 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8055 size(4);
8056 ins_encode %{
8057 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8058 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8059 %}
8060 ins_pipe(pipe_class_default);
8061 %}
8063 // Immediate Multiplication
8064 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8065 match(Set dst (MulL src1 src2));
8066 ins_cost(DEFAULT_COST);
8068 format %{ "MULLI $dst, $src1, $src2" %}
8069 size(4);
8070 ins_encode %{
8071 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8072 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8073 %}
8074 ins_pipe(pipe_class_default);
8075 %}
8077 // Integer Division with Immediate -1: Negate.
8078 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8079 match(Set dst (DivI src1 src2));
8080 ins_cost(DEFAULT_COST);
8082 format %{ "NEG $dst, $src1 \t// /-1" %}
8083 size(4);
8084 ins_encode %{
8085 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8086 __ neg($dst$$Register, $src1$$Register);
8087 %}
8088 ins_pipe(pipe_class_default);
8089 %}
8091 // Integer Division with constant, but not -1.
8092 // We should be able to improve this by checking the type of src2.
8093 // It might well be that src2 is known to be positive.
8094 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8095 match(Set dst (DivI src1 src2));
8096 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8097 ins_cost(2*DEFAULT_COST);
8099 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8100 size(4);
8101 ins_encode %{
8102 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8103 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8104 %}
8105 ins_pipe(pipe_class_default);
8106 %}
8108 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8109 effect(USE_DEF dst, USE src1, USE crx);
8110 predicate(false);
8112 ins_variable_size_depending_on_alignment(true);
8114 format %{ "CMOVE $dst, neg($src1), $crx" %}
8115 // Worst case is branch + move + stop, no stop without scheduler.
8116 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8117 ins_encode %{
8118 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8119 Label done;
8120 __ bne($crx$$CondRegister, done);
8121 __ neg($dst$$Register, $src1$$Register);
8122 // TODO PPC port __ endgroup_if_needed(_size == 12);
8123 __ bind(done);
8124 %}
8125 ins_pipe(pipe_class_default);
8126 %}
8128 // Integer Division with Registers not containing constants.
8129 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8130 match(Set dst (DivI src1 src2));
8131 ins_cost(10*DEFAULT_COST);
8133 expand %{
8134 immI16 imm %{ (int)-1 %}
8135 flagsReg tmp1;
8136 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8137 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8138 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8139 %}
8140 %}
8142 // Long Division with Immediate -1: Negate.
8143 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8144 match(Set dst (DivL src1 src2));
8145 ins_cost(DEFAULT_COST);
8147 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8148 size(4);
8149 ins_encode %{
8150 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8151 __ neg($dst$$Register, $src1$$Register);
8152 %}
8153 ins_pipe(pipe_class_default);
8154 %}
8156 // Long Division with constant, but not -1.
8157 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8158 match(Set dst (DivL src1 src2));
8159 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8160 ins_cost(2*DEFAULT_COST);
8162 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8163 size(4);
8164 ins_encode %{
8165 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8166 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8167 %}
8168 ins_pipe(pipe_class_default);
8169 %}
8171 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8172 effect(USE_DEF dst, USE src1, USE crx);
8173 predicate(false);
8175 ins_variable_size_depending_on_alignment(true);
8177 format %{ "CMOVE $dst, neg($src1), $crx" %}
8178 // Worst case is branch + move + stop, no stop without scheduler.
8179 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8180 ins_encode %{
8181 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8182 Label done;
8183 __ bne($crx$$CondRegister, done);
8184 __ neg($dst$$Register, $src1$$Register);
8185 // TODO PPC port __ endgroup_if_needed(_size == 12);
8186 __ bind(done);
8187 %}
8188 ins_pipe(pipe_class_default);
8189 %}
8191 // Long Division with Registers not containing constants.
8192 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8193 match(Set dst (DivL src1 src2));
8194 ins_cost(10*DEFAULT_COST);
8196 expand %{
8197 immL16 imm %{ (int)-1 %}
8198 flagsReg tmp1;
8199 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8200 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8201 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8202 %}
8203 %}
8205 // Integer Remainder with registers.
8206 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8207 match(Set dst (ModI src1 src2));
8208 ins_cost(10*DEFAULT_COST);
8210 expand %{
8211 immI16 imm %{ (int)-1 %}
8212 flagsReg tmp1;
8213 iRegIdst tmp2;
8214 iRegIdst tmp3;
8215 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8216 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8217 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8218 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8219 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8220 %}
8221 %}
8223 // Long Remainder with registers
8224 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8225 match(Set dst (ModL src1 src2));
8226 ins_cost(10*DEFAULT_COST);
8228 expand %{
8229 immL16 imm %{ (int)-1 %}
8230 flagsReg tmp1;
8231 iRegLdst tmp2;
8232 iRegLdst tmp3;
8233 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8234 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8235 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8236 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8237 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8238 %}
8239 %}
8241 // Integer Shift Instructions
8243 // Register Shift Left
8245 // Clear all but the lowest #mask bits.
8246 // Used to normalize shift amounts in registers.
8247 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8248 // no match-rule, false predicate
8249 effect(DEF dst, USE src, USE mask);
8250 predicate(false);
8252 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8253 size(4);
8254 ins_encode %{
8255 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8256 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8257 %}
8258 ins_pipe(pipe_class_default);
8259 %}
8261 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8262 // no match-rule, false predicate
8263 effect(DEF dst, USE src1, USE src2);
8264 predicate(false);
8266 format %{ "SLW $dst, $src1, $src2" %}
8267 size(4);
8268 ins_encode %{
8269 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8270 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8271 %}
8272 ins_pipe(pipe_class_default);
8273 %}
8275 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8276 match(Set dst (LShiftI src1 src2));
8277 ins_cost(DEFAULT_COST*2);
8278 expand %{
8279 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8280 iRegIdst tmpI;
8281 maskI_reg_imm(tmpI, src2, mask);
8282 lShiftI_reg_reg(dst, src1, tmpI);
8283 %}
8284 %}
8286 // Register Shift Left Immediate
8287 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8288 match(Set dst (LShiftI src1 src2));
8290 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8291 size(4);
8292 ins_encode %{
8293 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8294 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8295 %}
8296 ins_pipe(pipe_class_default);
8297 %}
8299 // AndI with negpow2-constant + LShiftI
8300 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8301 match(Set dst (LShiftI (AndI src1 src2) src3));
8302 predicate(UseRotateAndMaskInstructionsPPC64);
8304 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8305 size(4);
8306 ins_encode %{
8307 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8308 long src2 = $src2$$constant;
8309 long src3 = $src3$$constant;
8310 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8311 if (maskbits >= 32) {
8312 __ li($dst$$Register, 0); // addi
8313 } else {
8314 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8315 }
8316 %}
8317 ins_pipe(pipe_class_default);
8318 %}
8320 // RShiftI + AndI with negpow2-constant + LShiftI
8321 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8322 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8323 predicate(UseRotateAndMaskInstructionsPPC64);
8325 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8326 size(4);
8327 ins_encode %{
8328 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8329 long src2 = $src2$$constant;
8330 long src3 = $src3$$constant;
8331 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8332 if (maskbits >= 32) {
8333 __ li($dst$$Register, 0); // addi
8334 } else {
8335 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8336 }
8337 %}
8338 ins_pipe(pipe_class_default);
8339 %}
8341 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8342 // no match-rule, false predicate
8343 effect(DEF dst, USE src1, USE src2);
8344 predicate(false);
8346 format %{ "SLD $dst, $src1, $src2" %}
8347 size(4);
8348 ins_encode %{
8349 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8350 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8351 %}
8352 ins_pipe(pipe_class_default);
8353 %}
8355 // Register Shift Left
8356 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8357 match(Set dst (LShiftL src1 src2));
8358 ins_cost(DEFAULT_COST*2);
8359 expand %{
8360 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8361 iRegIdst tmpI;
8362 maskI_reg_imm(tmpI, src2, mask);
8363 lShiftL_regL_regI(dst, src1, tmpI);
8364 %}
8365 %}
8367 // Register Shift Left Immediate
8368 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8369 match(Set dst (LShiftL src1 src2));
8370 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8371 size(4);
8372 ins_encode %{
8373 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8374 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8375 %}
8376 ins_pipe(pipe_class_default);
8377 %}
8379 // If we shift more than 32 bits, we need not convert I2L.
8380 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8381 match(Set dst (LShiftL (ConvI2L src1) src2));
8382 ins_cost(DEFAULT_COST);
8384 size(4);
8385 format %{ "SLDI $dst, i2l($src1), $src2" %}
8386 ins_encode %{
8387 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8388 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8389 %}
8390 ins_pipe(pipe_class_default);
8391 %}
8393 // Shift a postivie int to the left.
8394 // Clrlsldi clears the upper 32 bits and shifts.
8395 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8396 match(Set dst (LShiftL (ConvI2L src1) src2));
8397 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8399 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8400 size(4);
8401 ins_encode %{
8402 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8403 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8404 %}
8405 ins_pipe(pipe_class_default);
8406 %}
8408 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8409 // no match-rule, false predicate
8410 effect(DEF dst, USE src1, USE src2);
8411 predicate(false);
8413 format %{ "SRAW $dst, $src1, $src2" %}
8414 size(4);
8415 ins_encode %{
8416 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8417 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8418 %}
8419 ins_pipe(pipe_class_default);
8420 %}
8422 // Register Arithmetic Shift Right
8423 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8424 match(Set dst (RShiftI src1 src2));
8425 ins_cost(DEFAULT_COST*2);
8426 expand %{
8427 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8428 iRegIdst tmpI;
8429 maskI_reg_imm(tmpI, src2, mask);
8430 arShiftI_reg_reg(dst, src1, tmpI);
8431 %}
8432 %}
8434 // Register Arithmetic Shift Right Immediate
8435 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8436 match(Set dst (RShiftI src1 src2));
8438 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8439 size(4);
8440 ins_encode %{
8441 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8442 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8443 %}
8444 ins_pipe(pipe_class_default);
8445 %}
8447 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8448 // no match-rule, false predicate
8449 effect(DEF dst, USE src1, USE src2);
8450 predicate(false);
8452 format %{ "SRAD $dst, $src1, $src2" %}
8453 size(4);
8454 ins_encode %{
8455 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8456 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8457 %}
8458 ins_pipe(pipe_class_default);
8459 %}
8461 // Register Shift Right Arithmetic Long
8462 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8463 match(Set dst (RShiftL src1 src2));
8464 ins_cost(DEFAULT_COST*2);
8466 expand %{
8467 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8468 iRegIdst tmpI;
8469 maskI_reg_imm(tmpI, src2, mask);
8470 arShiftL_regL_regI(dst, src1, tmpI);
8471 %}
8472 %}
8474 // Register Shift Right Immediate
8475 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8476 match(Set dst (RShiftL src1 src2));
8478 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8479 size(4);
8480 ins_encode %{
8481 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8482 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8483 %}
8484 ins_pipe(pipe_class_default);
8485 %}
8487 // RShiftL + ConvL2I
8488 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8489 match(Set dst (ConvL2I (RShiftL src1 src2)));
8491 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8492 size(4);
8493 ins_encode %{
8494 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8495 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8496 %}
8497 ins_pipe(pipe_class_default);
8498 %}
8500 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8501 // no match-rule, false predicate
8502 effect(DEF dst, USE src1, USE src2);
8503 predicate(false);
8505 format %{ "SRW $dst, $src1, $src2" %}
8506 size(4);
8507 ins_encode %{
8508 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8509 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8510 %}
8511 ins_pipe(pipe_class_default);
8512 %}
8514 // Register Shift Right
8515 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8516 match(Set dst (URShiftI src1 src2));
8517 ins_cost(DEFAULT_COST*2);
8519 expand %{
8520 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8521 iRegIdst tmpI;
8522 maskI_reg_imm(tmpI, src2, mask);
8523 urShiftI_reg_reg(dst, src1, tmpI);
8524 %}
8525 %}
8527 // Register Shift Right Immediate
8528 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8529 match(Set dst (URShiftI src1 src2));
8531 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8532 size(4);
8533 ins_encode %{
8534 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8535 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8536 %}
8537 ins_pipe(pipe_class_default);
8538 %}
8540 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8541 // no match-rule, false predicate
8542 effect(DEF dst, USE src1, USE src2);
8543 predicate(false);
8545 format %{ "SRD $dst, $src1, $src2" %}
8546 size(4);
8547 ins_encode %{
8548 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8549 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8550 %}
8551 ins_pipe(pipe_class_default);
8552 %}
8554 // Register Shift Right
8555 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8556 match(Set dst (URShiftL src1 src2));
8557 ins_cost(DEFAULT_COST*2);
8559 expand %{
8560 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8561 iRegIdst tmpI;
8562 maskI_reg_imm(tmpI, src2, mask);
8563 urShiftL_regL_regI(dst, src1, tmpI);
8564 %}
8565 %}
8567 // Register Shift Right Immediate
8568 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8569 match(Set dst (URShiftL src1 src2));
8571 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8572 size(4);
8573 ins_encode %{
8574 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8575 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8576 %}
8577 ins_pipe(pipe_class_default);
8578 %}
8580 // URShiftL + ConvL2I.
8581 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8582 match(Set dst (ConvL2I (URShiftL src1 src2)));
8584 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8585 size(4);
8586 ins_encode %{
8587 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8588 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8589 %}
8590 ins_pipe(pipe_class_default);
8591 %}
8593 // Register Shift Right Immediate with a CastP2X
8594 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8595 match(Set dst (URShiftL (CastP2X src1) src2));
8597 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8598 size(4);
8599 ins_encode %{
8600 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8601 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8602 %}
8603 ins_pipe(pipe_class_default);
8604 %}
8606 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8607 match(Set dst (ConvL2I (ConvI2L src)));
8609 format %{ "EXTSW $dst, $src \t// int->int" %}
8610 size(4);
8611 ins_encode %{
8612 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8613 __ extsw($dst$$Register, $src$$Register);
8614 %}
8615 ins_pipe(pipe_class_default);
8616 %}
8618 //----------Rotate Instructions------------------------------------------------
8620 // Rotate Left by 8-bit immediate
8621 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8622 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8623 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8625 format %{ "ROTLWI $dst, $src, $lshift" %}
8626 size(4);
8627 ins_encode %{
8628 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8629 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8630 %}
8631 ins_pipe(pipe_class_default);
8632 %}
8634 // Rotate Right by 8-bit immediate
8635 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8636 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8637 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8639 format %{ "ROTRWI $dst, $rshift" %}
8640 size(4);
8641 ins_encode %{
8642 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8643 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8644 %}
8645 ins_pipe(pipe_class_default);
8646 %}
8648 //----------Floating Point Arithmetic Instructions-----------------------------
8650 // Add float single precision
8651 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8652 match(Set dst (AddF src1 src2));
8654 format %{ "FADDS $dst, $src1, $src2" %}
8655 size(4);
8656 ins_encode %{
8657 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8658 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8659 %}
8660 ins_pipe(pipe_class_default);
8661 %}
8663 // Add float double precision
8664 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8665 match(Set dst (AddD src1 src2));
8667 format %{ "FADD $dst, $src1, $src2" %}
8668 size(4);
8669 ins_encode %{
8670 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8671 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8672 %}
8673 ins_pipe(pipe_class_default);
8674 %}
8676 // Sub float single precision
8677 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8678 match(Set dst (SubF src1 src2));
8680 format %{ "FSUBS $dst, $src1, $src2" %}
8681 size(4);
8682 ins_encode %{
8683 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8684 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8685 %}
8686 ins_pipe(pipe_class_default);
8687 %}
8689 // Sub float double precision
8690 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8691 match(Set dst (SubD src1 src2));
8692 format %{ "FSUB $dst, $src1, $src2" %}
8693 size(4);
8694 ins_encode %{
8695 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8696 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8697 %}
8698 ins_pipe(pipe_class_default);
8699 %}
8701 // Mul float single precision
8702 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8703 match(Set dst (MulF src1 src2));
8704 format %{ "FMULS $dst, $src1, $src2" %}
8705 size(4);
8706 ins_encode %{
8707 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8708 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8709 %}
8710 ins_pipe(pipe_class_default);
8711 %}
8713 // Mul float double precision
8714 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8715 match(Set dst (MulD src1 src2));
8716 format %{ "FMUL $dst, $src1, $src2" %}
8717 size(4);
8718 ins_encode %{
8719 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8720 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8721 %}
8722 ins_pipe(pipe_class_default);
8723 %}
8725 // Div float single precision
8726 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8727 match(Set dst (DivF src1 src2));
8728 format %{ "FDIVS $dst, $src1, $src2" %}
8729 size(4);
8730 ins_encode %{
8731 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8732 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8733 %}
8734 ins_pipe(pipe_class_default);
8735 %}
8737 // Div float double precision
8738 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8739 match(Set dst (DivD src1 src2));
8740 format %{ "FDIV $dst, $src1, $src2" %}
8741 size(4);
8742 ins_encode %{
8743 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8744 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8745 %}
8746 ins_pipe(pipe_class_default);
8747 %}
8749 // Absolute float single precision
8750 instruct absF_reg(regF dst, regF src) %{
8751 match(Set dst (AbsF src));
8752 format %{ "FABS $dst, $src \t// float" %}
8753 size(4);
8754 ins_encode %{
8755 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8756 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8757 %}
8758 ins_pipe(pipe_class_default);
8759 %}
8761 // Absolute float double precision
8762 instruct absD_reg(regD dst, regD src) %{
8763 match(Set dst (AbsD src));
8764 format %{ "FABS $dst, $src \t// double" %}
8765 size(4);
8766 ins_encode %{
8767 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8768 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8769 %}
8770 ins_pipe(pipe_class_default);
8771 %}
8773 instruct negF_reg(regF dst, regF src) %{
8774 match(Set dst (NegF src));
8775 format %{ "FNEG $dst, $src \t// float" %}
8776 size(4);
8777 ins_encode %{
8778 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8779 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8780 %}
8781 ins_pipe(pipe_class_default);
8782 %}
8784 instruct negD_reg(regD dst, regD src) %{
8785 match(Set dst (NegD src));
8786 format %{ "FNEG $dst, $src \t// double" %}
8787 size(4);
8788 ins_encode %{
8789 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8790 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8791 %}
8792 ins_pipe(pipe_class_default);
8793 %}
8795 // AbsF + NegF.
8796 instruct negF_absF_reg(regF dst, regF src) %{
8797 match(Set dst (NegF (AbsF src)));
8798 format %{ "FNABS $dst, $src \t// float" %}
8799 size(4);
8800 ins_encode %{
8801 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8802 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8803 %}
8804 ins_pipe(pipe_class_default);
8805 %}
8807 // AbsD + NegD.
8808 instruct negD_absD_reg(regD dst, regD src) %{
8809 match(Set dst (NegD (AbsD src)));
8810 format %{ "FNABS $dst, $src \t// double" %}
8811 size(4);
8812 ins_encode %{
8813 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8814 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8815 %}
8816 ins_pipe(pipe_class_default);
8817 %}
8819 // VM_Version::has_fsqrt() decides if this node will be used.
8820 // Sqrt float double precision
8821 instruct sqrtD_reg(regD dst, regD src) %{
8822 match(Set dst (SqrtD src));
8823 format %{ "FSQRT $dst, $src" %}
8824 size(4);
8825 ins_encode %{
8826 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8827 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8828 %}
8829 ins_pipe(pipe_class_default);
8830 %}
8832 // Single-precision sqrt.
8833 instruct sqrtF_reg(regF dst, regF src) %{
8834 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8835 predicate(VM_Version::has_fsqrts());
8836 ins_cost(DEFAULT_COST);
8838 format %{ "FSQRTS $dst, $src" %}
8839 size(4);
8840 ins_encode %{
8841 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8842 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8843 %}
8844 ins_pipe(pipe_class_default);
8845 %}
8847 instruct roundDouble_nop(regD dst) %{
8848 match(Set dst (RoundDouble dst));
8849 ins_cost(0);
8851 format %{ " -- \t// RoundDouble not needed - empty" %}
8852 size(0);
8853 // PPC results are already "rounded" (i.e., normal-format IEEE).
8854 ins_encode( /*empty*/ );
8855 ins_pipe(pipe_class_default);
8856 %}
8858 instruct roundFloat_nop(regF dst) %{
8859 match(Set dst (RoundFloat dst));
8860 ins_cost(0);
8862 format %{ " -- \t// RoundFloat not needed - empty" %}
8863 size(0);
8864 // PPC results are already "rounded" (i.e., normal-format IEEE).
8865 ins_encode( /*empty*/ );
8866 ins_pipe(pipe_class_default);
8867 %}
8869 //----------Logical Instructions-----------------------------------------------
8871 // And Instructions
8873 // Register And
8874 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8875 match(Set dst (AndI src1 src2));
8876 format %{ "AND $dst, $src1, $src2" %}
8877 size(4);
8878 ins_encode %{
8879 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8880 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8881 %}
8882 ins_pipe(pipe_class_default);
8883 %}
8885 // Immediate And
8886 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8887 match(Set dst (AndI src1 src2));
8888 effect(KILL cr0);
8890 format %{ "ANDI $dst, $src1, $src2" %}
8891 size(4);
8892 ins_encode %{
8893 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8894 // FIXME: avoid andi_ ?
8895 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8896 %}
8897 ins_pipe(pipe_class_default);
8898 %}
8900 // Immediate And where the immediate is a negative power of 2.
8901 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8902 match(Set dst (AndI src1 src2));
8903 format %{ "ANDWI $dst, $src1, $src2" %}
8904 size(4);
8905 ins_encode %{
8906 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8907 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8908 %}
8909 ins_pipe(pipe_class_default);
8910 %}
8912 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8913 match(Set dst (AndI src1 src2));
8914 format %{ "ANDWI $dst, $src1, $src2" %}
8915 size(4);
8916 ins_encode %{
8917 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8918 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8919 %}
8920 ins_pipe(pipe_class_default);
8921 %}
8923 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8924 match(Set dst (AndI src1 src2));
8925 predicate(UseRotateAndMaskInstructionsPPC64);
8926 format %{ "ANDWI $dst, $src1, $src2" %}
8927 size(4);
8928 ins_encode %{
8929 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8930 __ rlwinm($dst$$Register, $src1$$Register, 0,
8931 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8932 %}
8933 ins_pipe(pipe_class_default);
8934 %}
8936 // Register And Long
8937 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8938 match(Set dst (AndL src1 src2));
8939 ins_cost(DEFAULT_COST);
8941 format %{ "AND $dst, $src1, $src2 \t// long" %}
8942 size(4);
8943 ins_encode %{
8944 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8945 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8946 %}
8947 ins_pipe(pipe_class_default);
8948 %}
8950 // Immediate And long
8951 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8952 match(Set dst (AndL src1 src2));
8953 effect(KILL cr0);
8954 ins_cost(DEFAULT_COST);
8956 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8957 size(4);
8958 ins_encode %{
8959 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8960 // FIXME: avoid andi_ ?
8961 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8962 %}
8963 ins_pipe(pipe_class_default);
8964 %}
8966 // Immediate And Long where the immediate is a negative power of 2.
8967 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8968 match(Set dst (AndL src1 src2));
8969 format %{ "ANDDI $dst, $src1, $src2" %}
8970 size(4);
8971 ins_encode %{
8972 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8973 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8974 %}
8975 ins_pipe(pipe_class_default);
8976 %}
8978 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8979 match(Set dst (AndL src1 src2));
8980 format %{ "ANDDI $dst, $src1, $src2" %}
8981 size(4);
8982 ins_encode %{
8983 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8984 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8985 %}
8986 ins_pipe(pipe_class_default);
8987 %}
8989 // AndL + ConvL2I.
8990 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8991 match(Set dst (ConvL2I (AndL src1 src2)));
8992 ins_cost(DEFAULT_COST);
8994 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8995 size(4);
8996 ins_encode %{
8997 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8998 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8999 %}
9000 ins_pipe(pipe_class_default);
9001 %}
9003 // Or Instructions
9005 // Register Or
9006 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9007 match(Set dst (OrI src1 src2));
9008 format %{ "OR $dst, $src1, $src2" %}
9009 size(4);
9010 ins_encode %{
9011 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9012 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9013 %}
9014 ins_pipe(pipe_class_default);
9015 %}
9017 // Expand does not work with above instruct. (??)
9018 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9019 // no match-rule
9020 effect(DEF dst, USE src1, USE src2);
9021 format %{ "OR $dst, $src1, $src2" %}
9022 size(4);
9023 ins_encode %{
9024 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9025 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9026 %}
9027 ins_pipe(pipe_class_default);
9028 %}
9030 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9031 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9032 ins_cost(DEFAULT_COST*3);
9034 expand %{
9035 // FIXME: we should do this in the ideal world.
9036 iRegIdst tmp1;
9037 iRegIdst tmp2;
9038 orI_reg_reg(tmp1, src1, src2);
9039 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9040 orI_reg_reg(dst, tmp1, tmp2);
9041 %}
9042 %}
9044 // Immediate Or
9045 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9046 match(Set dst (OrI src1 src2));
9047 format %{ "ORI $dst, $src1, $src2" %}
9048 size(4);
9049 ins_encode %{
9050 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9051 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9052 %}
9053 ins_pipe(pipe_class_default);
9054 %}
9056 // Register Or Long
9057 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9058 match(Set dst (OrL src1 src2));
9059 ins_cost(DEFAULT_COST);
9061 size(4);
9062 format %{ "OR $dst, $src1, $src2 \t// long" %}
9063 ins_encode %{
9064 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9065 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9066 %}
9067 ins_pipe(pipe_class_default);
9068 %}
9070 // OrL + ConvL2I.
9071 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9072 match(Set dst (ConvL2I (OrL src1 src2)));
9073 ins_cost(DEFAULT_COST);
9075 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9076 size(4);
9077 ins_encode %{
9078 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9079 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9080 %}
9081 ins_pipe(pipe_class_default);
9082 %}
9084 // Immediate Or long
9085 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9086 match(Set dst (OrL src1 con));
9087 ins_cost(DEFAULT_COST);
9089 format %{ "ORI $dst, $src1, $con \t// long" %}
9090 size(4);
9091 ins_encode %{
9092 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9093 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9094 %}
9095 ins_pipe(pipe_class_default);
9096 %}
9098 // Xor Instructions
9100 // Register Xor
9101 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9102 match(Set dst (XorI src1 src2));
9103 format %{ "XOR $dst, $src1, $src2" %}
9104 size(4);
9105 ins_encode %{
9106 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9107 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9108 %}
9109 ins_pipe(pipe_class_default);
9110 %}
9112 // Expand does not work with above instruct. (??)
9113 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9114 // no match-rule
9115 effect(DEF dst, USE src1, USE src2);
9116 format %{ "XOR $dst, $src1, $src2" %}
9117 size(4);
9118 ins_encode %{
9119 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9120 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9121 %}
9122 ins_pipe(pipe_class_default);
9123 %}
9125 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9126 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9127 ins_cost(DEFAULT_COST*3);
9129 expand %{
9130 // FIXME: we should do this in the ideal world.
9131 iRegIdst tmp1;
9132 iRegIdst tmp2;
9133 xorI_reg_reg(tmp1, src1, src2);
9134 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9135 xorI_reg_reg(dst, tmp1, tmp2);
9136 %}
9137 %}
9139 // Immediate Xor
9140 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9141 match(Set dst (XorI src1 src2));
9142 format %{ "XORI $dst, $src1, $src2" %}
9143 size(4);
9144 ins_encode %{
9145 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9146 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9147 %}
9148 ins_pipe(pipe_class_default);
9149 %}
9151 // Register Xor Long
9152 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9153 match(Set dst (XorL src1 src2));
9154 ins_cost(DEFAULT_COST);
9156 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9157 size(4);
9158 ins_encode %{
9159 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9160 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9161 %}
9162 ins_pipe(pipe_class_default);
9163 %}
9165 // XorL + ConvL2I.
9166 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9167 match(Set dst (ConvL2I (XorL src1 src2)));
9168 ins_cost(DEFAULT_COST);
9170 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9171 size(4);
9172 ins_encode %{
9173 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9174 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9175 %}
9176 ins_pipe(pipe_class_default);
9177 %}
9179 // Immediate Xor Long
9180 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9181 match(Set dst (XorL src1 src2));
9182 ins_cost(DEFAULT_COST);
9184 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9185 size(4);
9186 ins_encode %{
9187 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9188 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9189 %}
9190 ins_pipe(pipe_class_default);
9191 %}
9193 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9194 match(Set dst (XorI src1 src2));
9195 ins_cost(DEFAULT_COST);
9197 format %{ "NOT $dst, $src1 ($src2)" %}
9198 size(4);
9199 ins_encode %{
9200 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9201 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9202 %}
9203 ins_pipe(pipe_class_default);
9204 %}
9206 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9207 match(Set dst (XorL src1 src2));
9208 ins_cost(DEFAULT_COST);
9210 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9211 size(4);
9212 ins_encode %{
9213 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9214 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9215 %}
9216 ins_pipe(pipe_class_default);
9217 %}
9219 // And-complement
9220 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9221 match(Set dst (AndI (XorI src1 src2) src3));
9222 ins_cost(DEFAULT_COST);
9224 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9225 size(4);
9226 ins_encode( enc_andc(dst, src3, src1) );
9227 ins_pipe(pipe_class_default);
9228 %}
9230 // And-complement
9231 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9232 // no match-rule, false predicate
9233 effect(DEF dst, USE src1, USE src2);
9234 predicate(false);
9236 format %{ "ANDC $dst, $src1, $src2" %}
9237 size(4);
9238 ins_encode %{
9239 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9240 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9241 %}
9242 ins_pipe(pipe_class_default);
9243 %}
9245 //----------Moves between int/long and float/double----------------------------
9246 //
9247 // The following rules move values from int/long registers/stack-locations
9248 // to float/double registers/stack-locations and vice versa, without doing any
9249 // conversions. These rules are used to implement the bit-conversion methods
9250 // of java.lang.Float etc., e.g.
9251 // int floatToIntBits(float value)
9252 // float intBitsToFloat(int bits)
9253 //
9254 // Notes on the implementation on ppc64:
9255 // We only provide rules which move between a register and a stack-location,
9256 // because we always have to go through memory when moving between a float
9257 // register and an integer register.
9259 //---------- Chain stack slots between similar types --------
9261 // These are needed so that the rules below can match.
9263 // Load integer from stack slot
9264 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9265 match(Set dst src);
9266 ins_cost(MEMORY_REF_COST);
9268 format %{ "LWZ $dst, $src" %}
9269 size(4);
9270 ins_encode( enc_lwz(dst, src) );
9271 ins_pipe(pipe_class_memory);
9272 %}
9274 // Store integer to stack slot
9275 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9276 match(Set dst src);
9277 ins_cost(MEMORY_REF_COST);
9279 format %{ "STW $src, $dst \t// stk" %}
9280 size(4);
9281 ins_encode( enc_stw(src, dst) ); // rs=rt
9282 ins_pipe(pipe_class_memory);
9283 %}
9285 // Load long from stack slot
9286 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9287 match(Set dst src);
9288 ins_cost(MEMORY_REF_COST);
9290 format %{ "LD $dst, $src \t// long" %}
9291 size(4);
9292 ins_encode( enc_ld(dst, src) );
9293 ins_pipe(pipe_class_memory);
9294 %}
9296 // Store long to stack slot
9297 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9298 match(Set dst src);
9299 ins_cost(MEMORY_REF_COST);
9301 format %{ "STD $src, $dst \t// long" %}
9302 size(4);
9303 ins_encode( enc_std(src, dst) ); // rs=rt
9304 ins_pipe(pipe_class_memory);
9305 %}
9307 //----------Moves between int and float
9309 // Move float value from float stack-location to integer register.
9310 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9311 match(Set dst (MoveF2I src));
9312 ins_cost(MEMORY_REF_COST);
9314 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9315 size(4);
9316 ins_encode( enc_lwz(dst, src) );
9317 ins_pipe(pipe_class_memory);
9318 %}
9320 // Move float value from float register to integer stack-location.
9321 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9322 match(Set dst (MoveF2I src));
9323 ins_cost(MEMORY_REF_COST);
9325 format %{ "STFS $src, $dst \t// MoveF2I" %}
9326 size(4);
9327 ins_encode( enc_stfs(src, dst) );
9328 ins_pipe(pipe_class_memory);
9329 %}
9331 // Move integer value from integer stack-location to float register.
9332 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9333 match(Set dst (MoveI2F src));
9334 ins_cost(MEMORY_REF_COST);
9336 format %{ "LFS $dst, $src \t// MoveI2F" %}
9337 size(4);
9338 ins_encode %{
9339 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9340 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9341 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9342 %}
9343 ins_pipe(pipe_class_memory);
9344 %}
9346 // Move integer value from integer register to float stack-location.
9347 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9348 match(Set dst (MoveI2F src));
9349 ins_cost(MEMORY_REF_COST);
9351 format %{ "STW $src, $dst \t// MoveI2F" %}
9352 size(4);
9353 ins_encode( enc_stw(src, dst) );
9354 ins_pipe(pipe_class_memory);
9355 %}
9357 //----------Moves between long and float
9359 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9360 // no match-rule, false predicate
9361 effect(DEF dst, USE src);
9362 predicate(false);
9364 format %{ "storeD $src, $dst \t// STACK" %}
9365 size(4);
9366 ins_encode( enc_stfd(src, dst) );
9367 ins_pipe(pipe_class_default);
9368 %}
9370 //----------Moves between long and double
9372 // Move double value from double stack-location to long register.
9373 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9374 match(Set dst (MoveD2L src));
9375 ins_cost(MEMORY_REF_COST);
9376 size(4);
9377 format %{ "LD $dst, $src \t// MoveD2L" %}
9378 ins_encode( enc_ld(dst, src) );
9379 ins_pipe(pipe_class_memory);
9380 %}
9382 // Move double value from double register to long stack-location.
9383 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9384 match(Set dst (MoveD2L src));
9385 effect(DEF dst, USE src);
9386 ins_cost(MEMORY_REF_COST);
9388 format %{ "STFD $src, $dst \t// MoveD2L" %}
9389 size(4);
9390 ins_encode( enc_stfd(src, dst) );
9391 ins_pipe(pipe_class_memory);
9392 %}
9394 // Move long value from long stack-location to double register.
9395 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9396 match(Set dst (MoveL2D src));
9397 ins_cost(MEMORY_REF_COST);
9399 format %{ "LFD $dst, $src \t// MoveL2D" %}
9400 size(4);
9401 ins_encode( enc_lfd(dst, src) );
9402 ins_pipe(pipe_class_memory);
9403 %}
9405 // Move long value from long register to double stack-location.
9406 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9407 match(Set dst (MoveL2D src));
9408 ins_cost(MEMORY_REF_COST);
9410 format %{ "STD $src, $dst \t// MoveL2D" %}
9411 size(4);
9412 ins_encode( enc_std(src, dst) );
9413 ins_pipe(pipe_class_memory);
9414 %}
9416 //----------Register Move Instructions-----------------------------------------
9418 // Replicate for Superword
9420 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9421 predicate(false);
9422 effect(DEF dst, USE src);
9424 format %{ "MR $dst, $src \t// replicate " %}
9425 // variable size, 0 or 4.
9426 ins_encode %{
9427 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9428 __ mr_if_needed($dst$$Register, $src$$Register);
9429 %}
9430 ins_pipe(pipe_class_default);
9431 %}
9433 //----------Cast instructions (Java-level type cast)---------------------------
9435 // Cast Long to Pointer for unsafe natives.
9436 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9437 match(Set dst (CastX2P src));
9439 format %{ "MR $dst, $src \t// Long->Ptr" %}
9440 // variable size, 0 or 4.
9441 ins_encode %{
9442 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9443 __ mr_if_needed($dst$$Register, $src$$Register);
9444 %}
9445 ins_pipe(pipe_class_default);
9446 %}
9448 // Cast Pointer to Long for unsafe natives.
9449 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9450 match(Set dst (CastP2X src));
9452 format %{ "MR $dst, $src \t// Ptr->Long" %}
9453 // variable size, 0 or 4.
9454 ins_encode %{
9455 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9456 __ mr_if_needed($dst$$Register, $src$$Register);
9457 %}
9458 ins_pipe(pipe_class_default);
9459 %}
9461 instruct castPP(iRegPdst dst) %{
9462 match(Set dst (CastPP dst));
9463 format %{ " -- \t// castPP of $dst" %}
9464 size(0);
9465 ins_encode( /*empty*/ );
9466 ins_pipe(pipe_class_default);
9467 %}
9469 instruct castII(iRegIdst dst) %{
9470 match(Set dst (CastII dst));
9471 format %{ " -- \t// castII of $dst" %}
9472 size(0);
9473 ins_encode( /*empty*/ );
9474 ins_pipe(pipe_class_default);
9475 %}
9477 instruct checkCastPP(iRegPdst dst) %{
9478 match(Set dst (CheckCastPP dst));
9479 format %{ " -- \t// checkcastPP of $dst" %}
9480 size(0);
9481 ins_encode( /*empty*/ );
9482 ins_pipe(pipe_class_default);
9483 %}
9485 //----------Convert instructions-----------------------------------------------
9487 // Convert to boolean.
9489 // int_to_bool(src) : { 1 if src != 0
9490 // { 0 else
9491 //
9492 // strategy:
9493 // 1) Count leading zeros of 32 bit-value src,
9494 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9495 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9496 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9498 // convI2Bool
9499 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9500 match(Set dst (Conv2B src));
9501 predicate(UseCountLeadingZerosInstructionsPPC64);
9502 ins_cost(DEFAULT_COST);
9504 expand %{
9505 immI shiftAmount %{ 0x5 %}
9506 uimmI16 mask %{ 0x1 %}
9507 iRegIdst tmp1;
9508 iRegIdst tmp2;
9509 countLeadingZerosI(tmp1, src);
9510 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9511 xorI_reg_uimm16(dst, tmp2, mask);
9512 %}
9513 %}
9515 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9516 match(Set dst (Conv2B src));
9517 effect(TEMP crx);
9518 predicate(!UseCountLeadingZerosInstructionsPPC64);
9519 ins_cost(DEFAULT_COST);
9521 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9522 "LI $dst, #0\n\t"
9523 "BEQ $crx, done\n\t"
9524 "LI $dst, #1\n"
9525 "done:" %}
9526 size(16);
9527 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9528 ins_pipe(pipe_class_compare);
9529 %}
9531 // ConvI2B + XorI
9532 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9533 match(Set dst (XorI (Conv2B src) mask));
9534 predicate(UseCountLeadingZerosInstructionsPPC64);
9535 ins_cost(DEFAULT_COST);
9537 expand %{
9538 immI shiftAmount %{ 0x5 %}
9539 iRegIdst tmp1;
9540 countLeadingZerosI(tmp1, src);
9541 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9542 %}
9543 %}
9545 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9546 match(Set dst (XorI (Conv2B src) mask));
9547 effect(TEMP crx);
9548 predicate(!UseCountLeadingZerosInstructionsPPC64);
9549 ins_cost(DEFAULT_COST);
9551 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9552 "LI $dst, #1\n\t"
9553 "BEQ $crx, done\n\t"
9554 "LI $dst, #0\n"
9555 "done:" %}
9556 size(16);
9557 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9558 ins_pipe(pipe_class_compare);
9559 %}
9561 // AndI 0b0..010..0 + ConvI2B
9562 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9563 match(Set dst (Conv2B (AndI src mask)));
9564 predicate(UseRotateAndMaskInstructionsPPC64);
9565 ins_cost(DEFAULT_COST);
9567 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9568 size(4);
9569 ins_encode %{
9570 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9571 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9572 %}
9573 ins_pipe(pipe_class_default);
9574 %}
9576 // Convert pointer to boolean.
9577 //
9578 // ptr_to_bool(src) : { 1 if src != 0
9579 // { 0 else
9580 //
9581 // strategy:
9582 // 1) Count leading zeros of 64 bit-value src,
9583 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9584 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9585 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9587 // ConvP2B
9588 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9589 match(Set dst (Conv2B src));
9590 predicate(UseCountLeadingZerosInstructionsPPC64);
9591 ins_cost(DEFAULT_COST);
9593 expand %{
9594 immI shiftAmount %{ 0x6 %}
9595 uimmI16 mask %{ 0x1 %}
9596 iRegIdst tmp1;
9597 iRegIdst tmp2;
9598 countLeadingZerosP(tmp1, src);
9599 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9600 xorI_reg_uimm16(dst, tmp2, mask);
9601 %}
9602 %}
9604 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9605 match(Set dst (Conv2B src));
9606 effect(TEMP crx);
9607 predicate(!UseCountLeadingZerosInstructionsPPC64);
9608 ins_cost(DEFAULT_COST);
9610 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9611 "LI $dst, #0\n\t"
9612 "BEQ $crx, done\n\t"
9613 "LI $dst, #1\n"
9614 "done:" %}
9615 size(16);
9616 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9617 ins_pipe(pipe_class_compare);
9618 %}
9620 // ConvP2B + XorI
9621 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9622 match(Set dst (XorI (Conv2B src) mask));
9623 predicate(UseCountLeadingZerosInstructionsPPC64);
9624 ins_cost(DEFAULT_COST);
9626 expand %{
9627 immI shiftAmount %{ 0x6 %}
9628 iRegIdst tmp1;
9629 countLeadingZerosP(tmp1, src);
9630 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9631 %}
9632 %}
9634 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9635 match(Set dst (XorI (Conv2B src) mask));
9636 effect(TEMP crx);
9637 predicate(!UseCountLeadingZerosInstructionsPPC64);
9638 ins_cost(DEFAULT_COST);
9640 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9641 "LI $dst, #1\n\t"
9642 "BEQ $crx, done\n\t"
9643 "LI $dst, #0\n"
9644 "done:" %}
9645 size(16);
9646 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9647 ins_pipe(pipe_class_compare);
9648 %}
9650 // if src1 < src2, return -1 else return 0
9651 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9652 match(Set dst (CmpLTMask src1 src2));
9653 ins_cost(DEFAULT_COST*4);
9655 expand %{
9656 iRegLdst src1s;
9657 iRegLdst src2s;
9658 iRegLdst diff;
9659 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9660 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9661 subL_reg_reg(diff, src1s, src2s);
9662 // Need to consider >=33 bit result, therefore we need signmaskL.
9663 signmask64I_regL(dst, diff);
9664 %}
9665 %}
9667 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9668 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9669 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9670 size(4);
9671 ins_encode %{
9672 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9673 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9674 %}
9675 ins_pipe(pipe_class_default);
9676 %}
9678 //----------Arithmetic Conversion Instructions---------------------------------
9680 // Convert to Byte -- nop
9681 // Convert to Short -- nop
9683 // Convert to Int
9685 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9686 match(Set dst (RShiftI (LShiftI src amount) amount));
9687 format %{ "EXTSB $dst, $src \t// byte->int" %}
9688 size(4);
9689 ins_encode %{
9690 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9691 __ extsb($dst$$Register, $src$$Register);
9692 %}
9693 ins_pipe(pipe_class_default);
9694 %}
9696 // LShiftI 16 + RShiftI 16 converts short to int.
9697 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9698 match(Set dst (RShiftI (LShiftI src amount) amount));
9699 format %{ "EXTSH $dst, $src \t// short->int" %}
9700 size(4);
9701 ins_encode %{
9702 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9703 __ extsh($dst$$Register, $src$$Register);
9704 %}
9705 ins_pipe(pipe_class_default);
9706 %}
9708 // ConvL2I + ConvI2L: Sign extend int in long register.
9709 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9710 match(Set dst (ConvI2L (ConvL2I src)));
9712 format %{ "EXTSW $dst, $src \t// long->long" %}
9713 size(4);
9714 ins_encode %{
9715 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9716 __ extsw($dst$$Register, $src$$Register);
9717 %}
9718 ins_pipe(pipe_class_default);
9719 %}
9721 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9722 match(Set dst (ConvL2I src));
9723 format %{ "MR $dst, $src \t// long->int" %}
9724 // variable size, 0 or 4
9725 ins_encode %{
9726 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9727 __ mr_if_needed($dst$$Register, $src$$Register);
9728 %}
9729 ins_pipe(pipe_class_default);
9730 %}
9732 instruct convD2IRaw_regD(regD dst, regD src) %{
9733 // no match-rule, false predicate
9734 effect(DEF dst, USE src);
9735 predicate(false);
9737 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9738 size(4);
9739 ins_encode %{
9740 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9741 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9742 %}
9743 ins_pipe(pipe_class_default);
9744 %}
9746 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9747 // no match-rule, false predicate
9748 effect(DEF dst, USE crx, USE src);
9749 predicate(false);
9751 ins_variable_size_depending_on_alignment(true);
9753 format %{ "cmovI $crx, $dst, $src" %}
9754 // Worst case is branch + move + stop, no stop without scheduler.
9755 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9756 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9757 ins_pipe(pipe_class_default);
9758 %}
9760 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9761 // no match-rule, false predicate
9762 effect(DEF dst, USE crx, USE mem);
9763 predicate(false);
9765 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9766 postalloc_expand %{
9767 //
9768 // replaces
9769 //
9770 // region dst crx mem
9771 // \ | | /
9772 // dst=cmovI_bso_stackSlotL_conLvalue0
9773 //
9774 // with
9775 //
9776 // region dst
9777 // \ /
9778 // dst=loadConI16(0)
9779 // |
9780 // ^ region dst crx mem
9781 // | \ | | /
9782 // dst=cmovI_bso_stackSlotL
9783 //
9785 // Create new nodes.
9786 MachNode *m1 = new (C) loadConI16Node();
9787 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9789 // inputs for new nodes
9790 m1->add_req(n_region);
9791 m2->add_req(n_region, n_crx, n_mem);
9793 // precedences for new nodes
9794 m2->add_prec(m1);
9796 // operands for new nodes
9797 m1->_opnds[0] = op_dst;
9798 m1->_opnds[1] = new (C) immI16Oper(0);
9800 m2->_opnds[0] = op_dst;
9801 m2->_opnds[1] = op_crx;
9802 m2->_opnds[2] = op_mem;
9804 // registers for new nodes
9805 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9806 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9808 // Insert new nodes.
9809 nodes->push(m1);
9810 nodes->push(m2);
9811 %}
9812 %}
9814 // Double to Int conversion, NaN is mapped to 0.
9815 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9816 match(Set dst (ConvD2I src));
9817 ins_cost(DEFAULT_COST);
9819 expand %{
9820 regD tmpD;
9821 stackSlotL tmpS;
9822 flagsReg crx;
9823 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9824 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9825 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9826 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9827 %}
9828 %}
9830 instruct convF2IRaw_regF(regF dst, regF src) %{
9831 // no match-rule, false predicate
9832 effect(DEF dst, USE src);
9833 predicate(false);
9835 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9836 size(4);
9837 ins_encode %{
9838 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9839 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9840 %}
9841 ins_pipe(pipe_class_default);
9842 %}
9844 // Float to Int conversion, NaN is mapped to 0.
9845 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9846 match(Set dst (ConvF2I src));
9847 ins_cost(DEFAULT_COST);
9849 expand %{
9850 regF tmpF;
9851 stackSlotL tmpS;
9852 flagsReg crx;
9853 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9854 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9855 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9856 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9857 %}
9858 %}
9860 // Convert to Long
9862 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9863 match(Set dst (ConvI2L src));
9864 format %{ "EXTSW $dst, $src \t// int->long" %}
9865 size(4);
9866 ins_encode %{
9867 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9868 __ extsw($dst$$Register, $src$$Register);
9869 %}
9870 ins_pipe(pipe_class_default);
9871 %}
9873 // Zero-extend: convert unsigned int to long (convUI2L).
9874 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9875 match(Set dst (AndL (ConvI2L src) mask));
9876 ins_cost(DEFAULT_COST);
9878 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9879 size(4);
9880 ins_encode %{
9881 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9882 __ clrldi($dst$$Register, $src$$Register, 32);
9883 %}
9884 ins_pipe(pipe_class_default);
9885 %}
9887 // Zero-extend: convert unsigned int to long in long register.
9888 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9889 match(Set dst (AndL src mask));
9890 ins_cost(DEFAULT_COST);
9892 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9893 size(4);
9894 ins_encode %{
9895 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9896 __ clrldi($dst$$Register, $src$$Register, 32);
9897 %}
9898 ins_pipe(pipe_class_default);
9899 %}
9901 instruct convF2LRaw_regF(regF dst, regF src) %{
9902 // no match-rule, false predicate
9903 effect(DEF dst, USE src);
9904 predicate(false);
9906 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9907 size(4);
9908 ins_encode %{
9909 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9910 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9911 %}
9912 ins_pipe(pipe_class_default);
9913 %}
9915 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9916 // no match-rule, false predicate
9917 effect(DEF dst, USE crx, USE src);
9918 predicate(false);
9920 ins_variable_size_depending_on_alignment(true);
9922 format %{ "cmovL $crx, $dst, $src" %}
9923 // Worst case is branch + move + stop, no stop without scheduler.
9924 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9925 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9926 ins_pipe(pipe_class_default);
9927 %}
9929 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9930 // no match-rule, false predicate
9931 effect(DEF dst, USE crx, USE mem);
9932 predicate(false);
9934 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9935 postalloc_expand %{
9936 //
9937 // replaces
9938 //
9939 // region dst crx mem
9940 // \ | | /
9941 // dst=cmovL_bso_stackSlotL_conLvalue0
9942 //
9943 // with
9944 //
9945 // region dst
9946 // \ /
9947 // dst=loadConL16(0)
9948 // |
9949 // ^ region dst crx mem
9950 // | \ | | /
9951 // dst=cmovL_bso_stackSlotL
9952 //
9954 // Create new nodes.
9955 MachNode *m1 = new (C) loadConL16Node();
9956 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9958 // inputs for new nodes
9959 m1->add_req(n_region);
9960 m2->add_req(n_region, n_crx, n_mem);
9961 m2->add_prec(m1);
9963 // operands for new nodes
9964 m1->_opnds[0] = op_dst;
9965 m1->_opnds[1] = new (C) immL16Oper(0);
9966 m2->_opnds[0] = op_dst;
9967 m2->_opnds[1] = op_crx;
9968 m2->_opnds[2] = op_mem;
9970 // registers for new nodes
9971 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9972 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9974 // Insert new nodes.
9975 nodes->push(m1);
9976 nodes->push(m2);
9977 %}
9978 %}
9980 // Float to Long conversion, NaN is mapped to 0.
9981 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9982 match(Set dst (ConvF2L src));
9983 ins_cost(DEFAULT_COST);
9985 expand %{
9986 regF tmpF;
9987 stackSlotL tmpS;
9988 flagsReg crx;
9989 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9990 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9991 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9992 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9993 %}
9994 %}
9996 instruct convD2LRaw_regD(regD dst, regD src) %{
9997 // no match-rule, false predicate
9998 effect(DEF dst, USE src);
9999 predicate(false);
10001 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10002 size(4);
10003 ins_encode %{
10004 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10005 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10006 %}
10007 ins_pipe(pipe_class_default);
10008 %}
10010 // Double to Long conversion, NaN is mapped to 0.
10011 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10012 match(Set dst (ConvD2L src));
10013 ins_cost(DEFAULT_COST);
10015 expand %{
10016 regD tmpD;
10017 stackSlotL tmpS;
10018 flagsReg crx;
10019 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10020 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10021 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10022 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10023 %}
10024 %}
10026 // Convert to Float
10028 // Placed here as needed in expand.
10029 instruct convL2DRaw_regD(regD dst, regD src) %{
10030 // no match-rule, false predicate
10031 effect(DEF dst, USE src);
10032 predicate(false);
10034 format %{ "FCFID $dst, $src \t// convL2D" %}
10035 size(4);
10036 ins_encode %{
10037 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10038 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10039 %}
10040 ins_pipe(pipe_class_default);
10041 %}
10043 // Placed here as needed in expand.
10044 instruct convD2F_reg(regF dst, regD src) %{
10045 match(Set dst (ConvD2F src));
10046 format %{ "FRSP $dst, $src \t// convD2F" %}
10047 size(4);
10048 ins_encode %{
10049 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10050 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10051 %}
10052 ins_pipe(pipe_class_default);
10053 %}
10055 // Integer to Float conversion.
10056 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10057 match(Set dst (ConvI2F src));
10058 predicate(!VM_Version::has_fcfids());
10059 ins_cost(DEFAULT_COST);
10061 expand %{
10062 iRegLdst tmpL;
10063 stackSlotL tmpS;
10064 regD tmpD;
10065 regD tmpD2;
10066 convI2L_reg(tmpL, src); // Sign-extension int to long.
10067 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10068 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10069 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10070 convD2F_reg(dst, tmpD2); // Convert double to float.
10071 %}
10072 %}
10074 instruct convL2FRaw_regF(regF dst, regD src) %{
10075 // no match-rule, false predicate
10076 effect(DEF dst, USE src);
10077 predicate(false);
10079 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10080 size(4);
10081 ins_encode %{
10082 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10083 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10084 %}
10085 ins_pipe(pipe_class_default);
10086 %}
10088 // Integer to Float conversion. Special version for Power7.
10089 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10090 match(Set dst (ConvI2F src));
10091 predicate(VM_Version::has_fcfids());
10092 ins_cost(DEFAULT_COST);
10094 expand %{
10095 iRegLdst tmpL;
10096 stackSlotL tmpS;
10097 regD tmpD;
10098 convI2L_reg(tmpL, src); // Sign-extension int to long.
10099 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10100 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10101 convL2FRaw_regF(dst, tmpD); // Convert to float.
10102 %}
10103 %}
10105 // L2F to avoid runtime call.
10106 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10107 match(Set dst (ConvL2F src));
10108 predicate(VM_Version::has_fcfids());
10109 ins_cost(DEFAULT_COST);
10111 expand %{
10112 stackSlotL tmpS;
10113 regD tmpD;
10114 regL_to_stkL(tmpS, src); // Store long to stack.
10115 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10116 convL2FRaw_regF(dst, tmpD); // Convert to float.
10117 %}
10118 %}
10120 // Moved up as used in expand.
10121 //instruct convD2F_reg(regF dst, regD src) %{%}
10123 // Convert to Double
10125 // Integer to Double conversion.
10126 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10127 match(Set dst (ConvI2D src));
10128 ins_cost(DEFAULT_COST);
10130 expand %{
10131 iRegLdst tmpL;
10132 stackSlotL tmpS;
10133 regD tmpD;
10134 convI2L_reg(tmpL, src); // Sign-extension int to long.
10135 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10136 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10137 convL2DRaw_regD(dst, tmpD); // Convert to double.
10138 %}
10139 %}
10141 // Long to Double conversion
10142 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10143 match(Set dst (ConvL2D src));
10144 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10146 expand %{
10147 regD tmpD;
10148 moveL2D_stack_reg(tmpD, src);
10149 convL2DRaw_regD(dst, tmpD);
10150 %}
10151 %}
10153 instruct convF2D_reg(regD dst, regF src) %{
10154 match(Set dst (ConvF2D src));
10155 format %{ "FMR $dst, $src \t// float->double" %}
10156 // variable size, 0 or 4
10157 ins_encode %{
10158 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10159 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10160 %}
10161 ins_pipe(pipe_class_default);
10162 %}
10164 //----------Control Flow Instructions------------------------------------------
10165 // Compare Instructions
10167 // Compare Integers
10168 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10169 match(Set crx (CmpI src1 src2));
10170 size(4);
10171 format %{ "CMPW $crx, $src1, $src2" %}
10172 ins_encode %{
10173 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10174 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10175 %}
10176 ins_pipe(pipe_class_compare);
10177 %}
10179 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10180 match(Set crx (CmpI src1 src2));
10181 format %{ "CMPWI $crx, $src1, $src2" %}
10182 size(4);
10183 ins_encode %{
10184 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10185 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10186 %}
10187 ins_pipe(pipe_class_compare);
10188 %}
10190 // (src1 & src2) == 0?
10191 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10192 match(Set cr0 (CmpI (AndI src1 src2) zero));
10193 // r0 is killed
10194 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10195 size(4);
10196 ins_encode %{
10197 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10198 // FIXME: avoid andi_ ?
10199 __ andi_(R0, $src1$$Register, $src2$$constant);
10200 %}
10201 ins_pipe(pipe_class_compare);
10202 %}
10204 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10205 match(Set crx (CmpL src1 src2));
10206 format %{ "CMPD $crx, $src1, $src2" %}
10207 size(4);
10208 ins_encode %{
10209 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10210 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10211 %}
10212 ins_pipe(pipe_class_compare);
10213 %}
10215 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10216 match(Set crx (CmpL src1 src2));
10217 format %{ "CMPDI $crx, $src1, $src2" %}
10218 size(4);
10219 ins_encode %{
10220 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10221 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10222 %}
10223 ins_pipe(pipe_class_compare);
10224 %}
10226 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10227 match(Set cr0 (CmpL (AndL src1 src2) zero));
10228 // r0 is killed
10229 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10230 size(4);
10231 ins_encode %{
10232 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10233 __ and_(R0, $src1$$Register, $src2$$Register);
10234 %}
10235 ins_pipe(pipe_class_compare);
10236 %}
10238 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10239 match(Set cr0 (CmpL (AndL src1 src2) zero));
10240 // r0 is killed
10241 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10242 size(4);
10243 ins_encode %{
10244 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10245 // FIXME: avoid andi_ ?
10246 __ andi_(R0, $src1$$Register, $src2$$constant);
10247 %}
10248 ins_pipe(pipe_class_compare);
10249 %}
10251 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10252 // no match-rule, false predicate
10253 effect(DEF dst, USE crx);
10254 predicate(false);
10256 ins_variable_size_depending_on_alignment(true);
10258 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10259 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10260 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10261 ins_encode %{
10262 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10263 Label done;
10264 // li(Rdst, 0); // equal -> 0
10265 __ beq($crx$$CondRegister, done);
10266 __ li($dst$$Register, 1); // greater -> +1
10267 __ bgt($crx$$CondRegister, done);
10268 __ li($dst$$Register, -1); // unordered or less -> -1
10269 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10270 __ bind(done);
10271 %}
10272 ins_pipe(pipe_class_compare);
10273 %}
10275 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10276 // no match-rule, false predicate
10277 effect(DEF dst, USE crx);
10278 predicate(false);
10280 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10281 postalloc_expand %{
10282 //
10283 // replaces
10284 //
10285 // region crx
10286 // \ |
10287 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10288 //
10289 // with
10290 //
10291 // region
10292 // \
10293 // dst=loadConI16(0)
10294 // |
10295 // ^ region crx
10296 // | \ |
10297 // dst=cmovI_conIvalueMinus1_conIvalue1
10298 //
10300 // Create new nodes.
10301 MachNode *m1 = new (C) loadConI16Node();
10302 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10304 // inputs for new nodes
10305 m1->add_req(n_region);
10306 m2->add_req(n_region, n_crx);
10307 m2->add_prec(m1);
10309 // operands for new nodes
10310 m1->_opnds[0] = op_dst;
10311 m1->_opnds[1] = new (C) immI16Oper(0);
10312 m2->_opnds[0] = op_dst;
10313 m2->_opnds[1] = op_crx;
10315 // registers for new nodes
10316 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10317 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10319 // Insert new nodes.
10320 nodes->push(m1);
10321 nodes->push(m2);
10322 %}
10323 %}
10325 // Manifest a CmpL3 result in an integer register. Very painful.
10326 // This is the test to avoid.
10327 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10328 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10329 match(Set dst (CmpL3 src1 src2));
10330 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10332 expand %{
10333 flagsReg tmp1;
10334 cmpL_reg_reg(tmp1, src1, src2);
10335 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10336 %}
10337 %}
10339 // Implicit range checks.
10340 // A range check in the ideal world has one of the following shapes:
10341 // - (If le (CmpU length index)), (IfTrue throw exception)
10342 // - (If lt (CmpU index length)), (IfFalse throw exception)
10343 //
10344 // Match range check 'If le (CmpU length index)'.
10345 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10346 match(If cmp (CmpU src_length index));
10347 effect(USE labl);
10348 predicate(TrapBasedRangeChecks &&
10349 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10350 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10351 (Matcher::branches_to_uncommon_trap(_leaf)));
10353 ins_is_TrapBasedCheckNode(true);
10355 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10356 size(4);
10357 ins_encode %{
10358 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10359 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10360 __ trap_range_check_le($src_length$$Register, $index$$constant);
10361 } else {
10362 // Both successors are uncommon traps, probability is 0.
10363 // Node got flipped during fixup flow.
10364 assert($cmp$$cmpcode == 0x9, "must be greater");
10365 __ trap_range_check_g($src_length$$Register, $index$$constant);
10366 }
10367 %}
10368 ins_pipe(pipe_class_trap);
10369 %}
10371 // Match range check 'If lt (CmpU index length)'.
10372 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10373 match(If cmp (CmpU src_index src_length));
10374 effect(USE labl);
10375 predicate(TrapBasedRangeChecks &&
10376 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10377 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10378 (Matcher::branches_to_uncommon_trap(_leaf)));
10380 ins_is_TrapBasedCheckNode(true);
10382 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10383 size(4);
10384 ins_encode %{
10385 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10386 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10387 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10388 } else {
10389 // Both successors are uncommon traps, probability is 0.
10390 // Node got flipped during fixup flow.
10391 assert($cmp$$cmpcode == 0x8, "must be less");
10392 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10393 }
10394 %}
10395 ins_pipe(pipe_class_trap);
10396 %}
10398 // Match range check 'If lt (CmpU index length)'.
10399 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10400 match(If cmp (CmpU src_index length));
10401 effect(USE labl);
10402 predicate(TrapBasedRangeChecks &&
10403 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10404 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10405 (Matcher::branches_to_uncommon_trap(_leaf)));
10407 ins_is_TrapBasedCheckNode(true);
10409 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10410 size(4);
10411 ins_encode %{
10412 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10413 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10414 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10415 } else {
10416 // Both successors are uncommon traps, probability is 0.
10417 // Node got flipped during fixup flow.
10418 assert($cmp$$cmpcode == 0x8, "must be less");
10419 __ trap_range_check_l($src_index$$Register, $length$$constant);
10420 }
10421 %}
10422 ins_pipe(pipe_class_trap);
10423 %}
10425 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10426 match(Set crx (CmpU src1 src2));
10427 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10428 size(4);
10429 ins_encode %{
10430 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10431 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10432 %}
10433 ins_pipe(pipe_class_compare);
10434 %}
10436 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10437 match(Set crx (CmpU src1 src2));
10438 size(4);
10439 format %{ "CMPLWI $crx, $src1, $src2" %}
10440 ins_encode %{
10441 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10442 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10443 %}
10444 ins_pipe(pipe_class_compare);
10445 %}
10447 // Implicit zero checks (more implicit null checks).
10448 // No constant pool entries required.
10449 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10450 match(If cmp (CmpN value zero));
10451 effect(USE labl);
10452 predicate(TrapBasedNullChecks &&
10453 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10454 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10455 Matcher::branches_to_uncommon_trap(_leaf));
10456 ins_cost(1);
10458 ins_is_TrapBasedCheckNode(true);
10460 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10461 size(4);
10462 ins_encode %{
10463 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10464 if ($cmp$$cmpcode == 0xA) {
10465 __ trap_null_check($value$$Register);
10466 } else {
10467 // Both successors are uncommon traps, probability is 0.
10468 // Node got flipped during fixup flow.
10469 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10470 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10471 }
10472 %}
10473 ins_pipe(pipe_class_trap);
10474 %}
10476 // Compare narrow oops.
10477 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10478 match(Set crx (CmpN src1 src2));
10480 size(4);
10481 ins_cost(DEFAULT_COST);
10482 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10483 ins_encode %{
10484 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10485 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10486 %}
10487 ins_pipe(pipe_class_compare);
10488 %}
10490 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10491 match(Set crx (CmpN src1 src2));
10492 // Make this more expensive than zeroCheckN_iReg_imm0.
10493 ins_cost(DEFAULT_COST);
10495 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10496 size(4);
10497 ins_encode %{
10498 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10499 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10500 %}
10501 ins_pipe(pipe_class_compare);
10502 %}
10504 // Implicit zero checks (more implicit null checks).
10505 // No constant pool entries required.
10506 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10507 match(If cmp (CmpP value zero));
10508 effect(USE labl);
10509 predicate(TrapBasedNullChecks &&
10510 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10511 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10512 Matcher::branches_to_uncommon_trap(_leaf));
10514 ins_is_TrapBasedCheckNode(true);
10516 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10517 size(4);
10518 ins_encode %{
10519 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10520 if ($cmp$$cmpcode == 0xA) {
10521 __ trap_null_check($value$$Register);
10522 } else {
10523 // Both successors are uncommon traps, probability is 0.
10524 // Node got flipped during fixup flow.
10525 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10526 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10527 }
10528 %}
10529 ins_pipe(pipe_class_trap);
10530 %}
10532 // Compare Pointers
10533 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10534 match(Set crx (CmpP src1 src2));
10535 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10536 size(4);
10537 ins_encode %{
10538 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10539 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10540 %}
10541 ins_pipe(pipe_class_compare);
10542 %}
10544 // Used in postalloc expand.
10545 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10546 // This match rule prevents reordering of node before a safepoint.
10547 // This only makes sense if this instructions is used exclusively
10548 // for the expansion of EncodeP!
10549 match(Set crx (CmpP src1 src2));
10550 predicate(false);
10552 format %{ "CMPDI $crx, $src1, $src2" %}
10553 size(4);
10554 ins_encode %{
10555 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10556 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10557 %}
10558 ins_pipe(pipe_class_compare);
10559 %}
10561 //----------Float Compares----------------------------------------------------
10563 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10564 // no match-rule, false predicate
10565 effect(DEF crx, USE src1, USE src2);
10566 predicate(false);
10568 format %{ "cmpFUrd $crx, $src1, $src2" %}
10569 size(4);
10570 ins_encode %{
10571 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10572 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10573 %}
10574 ins_pipe(pipe_class_default);
10575 %}
10577 instruct cmov_bns_less(flagsReg crx) %{
10578 // no match-rule, false predicate
10579 effect(DEF crx);
10580 predicate(false);
10582 ins_variable_size_depending_on_alignment(true);
10584 format %{ "cmov $crx" %}
10585 // Worst case is branch + move + stop, no stop without scheduler.
10586 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10587 ins_encode %{
10588 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10589 Label done;
10590 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10591 __ li(R0, 0);
10592 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10593 // TODO PPC port __ endgroup_if_needed(_size == 16);
10594 __ bind(done);
10595 %}
10596 ins_pipe(pipe_class_default);
10597 %}
10599 // Compare floating, generate condition code.
10600 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10601 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10602 //
10603 // The following code sequence occurs a lot in mpegaudio:
10604 //
10605 // block BXX:
10606 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10607 // cmpFUrd CCR6, F11, F9
10608 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10609 // cmov CCR6
10610 // 8: instruct branchConSched:
10611 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10612 match(Set crx (CmpF src1 src2));
10613 ins_cost(DEFAULT_COST+BRANCH_COST);
10615 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10616 postalloc_expand %{
10617 //
10618 // replaces
10619 //
10620 // region src1 src2
10621 // \ | |
10622 // crx=cmpF_reg_reg
10623 //
10624 // with
10625 //
10626 // region src1 src2
10627 // \ | |
10628 // crx=cmpFUnordered_reg_reg
10629 // |
10630 // ^ region
10631 // | \
10632 // crx=cmov_bns_less
10633 //
10635 // Create new nodes.
10636 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10637 MachNode *m2 = new (C) cmov_bns_lessNode();
10639 // inputs for new nodes
10640 m1->add_req(n_region, n_src1, n_src2);
10641 m2->add_req(n_region);
10642 m2->add_prec(m1);
10644 // operands for new nodes
10645 m1->_opnds[0] = op_crx;
10646 m1->_opnds[1] = op_src1;
10647 m1->_opnds[2] = op_src2;
10648 m2->_opnds[0] = op_crx;
10650 // registers for new nodes
10651 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10652 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10654 // Insert new nodes.
10655 nodes->push(m1);
10656 nodes->push(m2);
10657 %}
10658 %}
10660 // Compare float, generate -1,0,1
10661 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10662 match(Set dst (CmpF3 src1 src2));
10663 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10665 expand %{
10666 flagsReg tmp1;
10667 cmpFUnordered_reg_reg(tmp1, src1, src2);
10668 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10669 %}
10670 %}
10672 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10673 // no match-rule, false predicate
10674 effect(DEF crx, USE src1, USE src2);
10675 predicate(false);
10677 format %{ "cmpFUrd $crx, $src1, $src2" %}
10678 size(4);
10679 ins_encode %{
10680 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10681 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10682 %}
10683 ins_pipe(pipe_class_default);
10684 %}
10686 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10687 match(Set crx (CmpD src1 src2));
10688 ins_cost(DEFAULT_COST+BRANCH_COST);
10690 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10691 postalloc_expand %{
10692 //
10693 // replaces
10694 //
10695 // region src1 src2
10696 // \ | |
10697 // crx=cmpD_reg_reg
10698 //
10699 // with
10700 //
10701 // region src1 src2
10702 // \ | |
10703 // crx=cmpDUnordered_reg_reg
10704 // |
10705 // ^ region
10706 // | \
10707 // crx=cmov_bns_less
10708 //
10710 // create new nodes
10711 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10712 MachNode *m2 = new (C) cmov_bns_lessNode();
10714 // inputs for new nodes
10715 m1->add_req(n_region, n_src1, n_src2);
10716 m2->add_req(n_region);
10717 m2->add_prec(m1);
10719 // operands for new nodes
10720 m1->_opnds[0] = op_crx;
10721 m1->_opnds[1] = op_src1;
10722 m1->_opnds[2] = op_src2;
10723 m2->_opnds[0] = op_crx;
10725 // registers for new nodes
10726 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10727 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10729 // Insert new nodes.
10730 nodes->push(m1);
10731 nodes->push(m2);
10732 %}
10733 %}
10735 // Compare double, generate -1,0,1
10736 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10737 match(Set dst (CmpD3 src1 src2));
10738 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10740 expand %{
10741 flagsReg tmp1;
10742 cmpDUnordered_reg_reg(tmp1, src1, src2);
10743 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10744 %}
10745 %}
10747 //----------Branches---------------------------------------------------------
10748 // Jump
10750 // Direct Branch.
10751 instruct branch(label labl) %{
10752 match(Goto);
10753 effect(USE labl);
10754 ins_cost(BRANCH_COST);
10756 format %{ "B $labl" %}
10757 size(4);
10758 ins_encode %{
10759 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10760 Label d; // dummy
10761 __ bind(d);
10762 Label* p = $labl$$label;
10763 // `p' is `NULL' when this encoding class is used only to
10764 // determine the size of the encoded instruction.
10765 Label& l = (NULL == p)? d : *(p);
10766 __ b(l);
10767 %}
10768 ins_pipe(pipe_class_default);
10769 %}
10771 // Conditional Near Branch
10772 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10773 // Same match rule as `branchConFar'.
10774 match(If cmp crx);
10775 effect(USE lbl);
10776 ins_cost(BRANCH_COST);
10778 // If set to 1 this indicates that the current instruction is a
10779 // short variant of a long branch. This avoids using this
10780 // instruction in first-pass matching. It will then only be used in
10781 // the `Shorten_branches' pass.
10782 ins_short_branch(1);
10784 format %{ "B$cmp $crx, $lbl" %}
10785 size(4);
10786 ins_encode( enc_bc(crx, cmp, lbl) );
10787 ins_pipe(pipe_class_default);
10788 %}
10790 // This is for cases when the ppc64 `bc' instruction does not
10791 // reach far enough. So we emit a far branch here, which is more
10792 // expensive.
10793 //
10794 // Conditional Far Branch
10795 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10796 // Same match rule as `branchCon'.
10797 match(If cmp crx);
10798 effect(USE crx, USE lbl);
10799 predicate(!false /* TODO: PPC port HB_Schedule*/);
10800 // Higher cost than `branchCon'.
10801 ins_cost(5*BRANCH_COST);
10803 // This is not a short variant of a branch, but the long variant.
10804 ins_short_branch(0);
10806 format %{ "B_FAR$cmp $crx, $lbl" %}
10807 size(8);
10808 ins_encode( enc_bc_far(crx, cmp, lbl) );
10809 ins_pipe(pipe_class_default);
10810 %}
10812 // Conditional Branch used with Power6 scheduler (can be far or short).
10813 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10814 // Same match rule as `branchCon'.
10815 match(If cmp crx);
10816 effect(USE crx, USE lbl);
10817 predicate(false /* TODO: PPC port HB_Schedule*/);
10818 // Higher cost than `branchCon'.
10819 ins_cost(5*BRANCH_COST);
10821 // Actually size doesn't depend on alignment but on shortening.
10822 ins_variable_size_depending_on_alignment(true);
10823 // long variant.
10824 ins_short_branch(0);
10826 format %{ "B_FAR$cmp $crx, $lbl" %}
10827 size(8); // worst case
10828 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10829 ins_pipe(pipe_class_default);
10830 %}
10832 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10833 match(CountedLoopEnd cmp crx);
10834 effect(USE labl);
10835 ins_cost(BRANCH_COST);
10837 // short variant.
10838 ins_short_branch(1);
10840 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10841 size(4);
10842 ins_encode( enc_bc(crx, cmp, labl) );
10843 ins_pipe(pipe_class_default);
10844 %}
10846 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10847 match(CountedLoopEnd cmp crx);
10848 effect(USE labl);
10849 predicate(!false /* TODO: PPC port HB_Schedule */);
10850 ins_cost(BRANCH_COST);
10852 // Long variant.
10853 ins_short_branch(0);
10855 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10856 size(8);
10857 ins_encode( enc_bc_far(crx, cmp, labl) );
10858 ins_pipe(pipe_class_default);
10859 %}
10861 // Conditional Branch used with Power6 scheduler (can be far or short).
10862 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10863 match(CountedLoopEnd cmp crx);
10864 effect(USE labl);
10865 predicate(false /* TODO: PPC port HB_Schedule */);
10866 // Higher cost than `branchCon'.
10867 ins_cost(5*BRANCH_COST);
10869 // Actually size doesn't depend on alignment but on shortening.
10870 ins_variable_size_depending_on_alignment(true);
10871 // Long variant.
10872 ins_short_branch(0);
10874 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10875 size(8); // worst case
10876 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10877 ins_pipe(pipe_class_default);
10878 %}
10880 // ============================================================================
10881 // Java runtime operations, intrinsics and other complex operations.
10883 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10884 // array for an instance of the superklass. Set a hidden internal cache on a
10885 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10886 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10887 //
10888 // GL TODO: Improve this.
10889 // - result should not be a TEMP
10890 // - Add match rule as on sparc avoiding additional Cmp.
10891 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10892 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10893 match(Set result (PartialSubtypeCheck subklass superklass));
10894 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10895 ins_cost(DEFAULT_COST*10);
10897 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10898 ins_encode %{
10899 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10900 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10901 $tmp_klass$$Register, NULL, $result$$Register);
10902 %}
10903 ins_pipe(pipe_class_default);
10904 %}
10906 // inlined locking and unlocking
10908 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10909 match(Set crx (FastLock oop box));
10910 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10911 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10913 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10914 ins_encode %{
10915 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10916 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10917 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10918 // If locking was successfull, crx should indicate 'EQ'.
10919 // The compiler generates a branch to the runtime call to
10920 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10921 %}
10922 ins_pipe(pipe_class_compare);
10923 %}
10925 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10926 match(Set crx (FastUnlock oop box));
10927 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10929 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10930 ins_encode %{
10931 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10932 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10933 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10934 // If unlocking was successfull, crx should indicate 'EQ'.
10935 // The compiler generates a branch to the runtime call to
10936 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10937 %}
10938 ins_pipe(pipe_class_compare);
10939 %}
10941 // Align address.
10942 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10943 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10945 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10946 size(4);
10947 ins_encode %{
10948 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10949 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10950 %}
10951 ins_pipe(pipe_class_default);
10952 %}
10954 // Array size computation.
10955 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10956 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10958 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10959 size(4);
10960 ins_encode %{
10961 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10962 __ subf($dst$$Register, $start$$Register, $end$$Register);
10963 %}
10964 ins_pipe(pipe_class_default);
10965 %}
10967 // Clear-array with dynamic array-size.
10968 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10969 match(Set dummy (ClearArray cnt base));
10970 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10971 ins_cost(MEMORY_REF_COST);
10973 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10975 format %{ "ClearArray $cnt, $base" %}
10976 ins_encode %{
10977 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10978 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10979 %}
10980 ins_pipe(pipe_class_default);
10981 %}
10983 // String_IndexOf for needle of length 1.
10984 //
10985 // Match needle into immediate operands: no loadConP node needed. Saves one
10986 // register and two instructions over string_indexOf_imm1Node.
10987 //
10988 // Assumes register result differs from all input registers.
10989 //
10990 // Preserves registers haystack, haycnt
10991 // Kills registers tmp1, tmp2
10992 // Defines registers result
10993 //
10994 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10995 //
10996 // Unfortunately this does not match too often. In many situations the AddP is used
10997 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10998 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10999 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11000 iRegIdst tmp1, iRegIdst tmp2,
11001 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11002 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
11003 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11005 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11007 ins_cost(150);
11008 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11009 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11011 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11012 ins_encode %{
11013 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11014 immPOper *needleOper = (immPOper *)$needleImm;
11015 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11016 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11018 __ string_indexof_1($result$$Register,
11019 $haystack$$Register, $haycnt$$Register,
11020 R0, needle_values->char_at(0),
11021 $tmp1$$Register, $tmp2$$Register);
11022 %}
11023 ins_pipe(pipe_class_compare);
11024 %}
11026 // String_IndexOf for needle of length 1.
11027 //
11028 // Special case requires less registers and emits less instructions.
11029 //
11030 // Assumes register result differs from all input registers.
11031 //
11032 // Preserves registers haystack, haycnt
11033 // Kills registers tmp1, tmp2, needle
11034 // Defines registers result
11035 //
11036 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11037 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11038 rscratch2RegP needle, immI_1 needlecntImm,
11039 iRegIdst tmp1, iRegIdst tmp2,
11040 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11041 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11042 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
11043 TEMP tmp1, TEMP tmp2);
11044 // Required for EA: check if it is still a type_array.
11045 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11046 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11047 ins_cost(180);
11049 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11051 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11052 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11053 ins_encode %{
11054 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11055 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11056 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11057 guarantee(needle_values, "sanity");
11058 if (needle_values != NULL) {
11059 __ string_indexof_1($result$$Register,
11060 $haystack$$Register, $haycnt$$Register,
11061 R0, needle_values->char_at(0),
11062 $tmp1$$Register, $tmp2$$Register);
11063 } else {
11064 __ string_indexof_1($result$$Register,
11065 $haystack$$Register, $haycnt$$Register,
11066 $needle$$Register, 0,
11067 $tmp1$$Register, $tmp2$$Register);
11068 }
11069 %}
11070 ins_pipe(pipe_class_compare);
11071 %}
11073 // String_IndexOf.
11074 //
11075 // Length of needle as immediate. This saves instruction loading constant needle
11076 // length.
11077 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11078 // completely or do it in vector instruction. This should save registers for
11079 // needlecnt and needle.
11080 //
11081 // Assumes register result differs from all input registers.
11082 // Overwrites haycnt, needlecnt.
11083 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11084 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11085 iRegPsrc needle, uimmI15 needlecntImm,
11086 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11087 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11088 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11089 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11090 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11091 // Required for EA: check if it is still a type_array.
11092 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11093 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11094 ins_cost(250);
11096 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11098 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11099 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11100 ins_encode %{
11101 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11102 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11103 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11105 __ string_indexof($result$$Register,
11106 $haystack$$Register, $haycnt$$Register,
11107 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11108 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11109 %}
11110 ins_pipe(pipe_class_compare);
11111 %}
11113 // StrIndexOf node.
11114 //
11115 // Assumes register result differs from all input registers.
11116 // Overwrites haycnt, needlecnt.
11117 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11118 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11119 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11120 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11121 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11122 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11123 TEMP result,
11124 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11125 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11126 ins_cost(300);
11128 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11130 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11131 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11132 ins_encode %{
11133 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11134 __ string_indexof($result$$Register,
11135 $haystack$$Register, $haycnt$$Register,
11136 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11137 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11138 %}
11139 ins_pipe(pipe_class_compare);
11140 %}
11142 // String equals with immediate.
11143 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11144 iRegPdst tmp1, iRegPdst tmp2,
11145 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11146 match(Set result (StrEquals (Binary str1 str2) cntImm));
11147 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11148 KILL cr0, KILL cr6, KILL ctr);
11149 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11150 ins_cost(250);
11152 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11154 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11155 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11156 ins_encode %{
11157 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11158 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11159 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11160 %}
11161 ins_pipe(pipe_class_compare);
11162 %}
11164 // String equals.
11165 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11166 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11167 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11168 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11169 match(Set result (StrEquals (Binary str1 str2) cnt));
11170 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11171 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11172 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11173 ins_cost(300);
11175 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11177 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11178 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11179 ins_encode %{
11180 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11181 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11182 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11183 %}
11184 ins_pipe(pipe_class_compare);
11185 %}
11187 // String compare.
11188 // Char[] pointers are passed in.
11189 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11190 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11191 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11192 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11193 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11194 ins_cost(300);
11196 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11198 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11199 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11200 ins_encode %{
11201 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11202 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11203 $result$$Register, $tmp$$Register);
11204 %}
11205 ins_pipe(pipe_class_compare);
11206 %}
11208 //---------- Min/Max Instructions ---------------------------------------------
11210 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11211 match(Set dst (MinI src1 src2));
11212 ins_cost(DEFAULT_COST*6);
11214 expand %{
11215 iRegLdst src1s;
11216 iRegLdst src2s;
11217 iRegLdst diff;
11218 iRegLdst sm;
11219 iRegLdst doz; // difference or zero
11220 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11221 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11222 subL_reg_reg(diff, src2s, src1s);
11223 // Need to consider >=33 bit result, therefore we need signmaskL.
11224 signmask64L_regL(sm, diff);
11225 andL_reg_reg(doz, diff, sm); // <=0
11226 addI_regL_regL(dst, doz, src1s);
11227 %}
11228 %}
11230 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11231 match(Set dst (MaxI src1 src2));
11232 ins_cost(DEFAULT_COST*6);
11234 expand %{
11235 iRegLdst src1s;
11236 iRegLdst src2s;
11237 iRegLdst diff;
11238 iRegLdst sm;
11239 iRegLdst doz; // difference or zero
11240 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11241 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11242 subL_reg_reg(diff, src2s, src1s);
11243 // Need to consider >=33 bit result, therefore we need signmaskL.
11244 signmask64L_regL(sm, diff);
11245 andcL_reg_reg(doz, diff, sm); // >=0
11246 addI_regL_regL(dst, doz, src1s);
11247 %}
11248 %}
11250 //---------- Population Count Instructions ------------------------------------
11252 // Popcnt for Power7.
11253 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11254 match(Set dst (PopCountI src));
11255 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11256 ins_cost(DEFAULT_COST);
11258 format %{ "POPCNTW $dst, $src" %}
11259 size(4);
11260 ins_encode %{
11261 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11262 __ popcntw($dst$$Register, $src$$Register);
11263 %}
11264 ins_pipe(pipe_class_default);
11265 %}
11267 // Popcnt for Power7.
11268 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11269 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11270 match(Set dst (PopCountL src));
11271 ins_cost(DEFAULT_COST);
11273 format %{ "POPCNTD $dst, $src" %}
11274 size(4);
11275 ins_encode %{
11276 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11277 __ popcntd($dst$$Register, $src$$Register);
11278 %}
11279 ins_pipe(pipe_class_default);
11280 %}
11282 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11283 match(Set dst (CountLeadingZerosI src));
11284 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11285 ins_cost(DEFAULT_COST);
11287 format %{ "CNTLZW $dst, $src" %}
11288 size(4);
11289 ins_encode %{
11290 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11291 __ cntlzw($dst$$Register, $src$$Register);
11292 %}
11293 ins_pipe(pipe_class_default);
11294 %}
11296 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11297 match(Set dst (CountLeadingZerosL src));
11298 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11299 ins_cost(DEFAULT_COST);
11301 format %{ "CNTLZD $dst, $src" %}
11302 size(4);
11303 ins_encode %{
11304 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11305 __ cntlzd($dst$$Register, $src$$Register);
11306 %}
11307 ins_pipe(pipe_class_default);
11308 %}
11310 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11311 // no match-rule, false predicate
11312 effect(DEF dst, USE src);
11313 predicate(false);
11315 format %{ "CNTLZD $dst, $src" %}
11316 size(4);
11317 ins_encode %{
11318 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11319 __ cntlzd($dst$$Register, $src$$Register);
11320 %}
11321 ins_pipe(pipe_class_default);
11322 %}
11324 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11325 match(Set dst (CountTrailingZerosI src));
11326 predicate(UseCountLeadingZerosInstructionsPPC64);
11327 ins_cost(DEFAULT_COST);
11329 expand %{
11330 immI16 imm1 %{ (int)-1 %}
11331 immI16 imm2 %{ (int)32 %}
11332 immI_minus1 m1 %{ -1 %}
11333 iRegIdst tmpI1;
11334 iRegIdst tmpI2;
11335 iRegIdst tmpI3;
11336 addI_reg_imm16(tmpI1, src, imm1);
11337 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11338 countLeadingZerosI(tmpI3, tmpI2);
11339 subI_imm16_reg(dst, imm2, tmpI3);
11340 %}
11341 %}
11343 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11344 match(Set dst (CountTrailingZerosL src));
11345 predicate(UseCountLeadingZerosInstructionsPPC64);
11346 ins_cost(DEFAULT_COST);
11348 expand %{
11349 immL16 imm1 %{ (long)-1 %}
11350 immI16 imm2 %{ (int)64 %}
11351 iRegLdst tmpL1;
11352 iRegLdst tmpL2;
11353 iRegIdst tmpL3;
11354 addL_reg_imm16(tmpL1, src, imm1);
11355 andcL_reg_reg(tmpL2, tmpL1, src);
11356 countLeadingZerosL(tmpL3, tmpL2);
11357 subI_imm16_reg(dst, imm2, tmpL3);
11358 %}
11359 %}
11361 // Expand nodes for byte_reverse_int.
11362 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11363 effect(DEF dst, USE src, USE pos, USE shift);
11364 predicate(false);
11366 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11367 size(4);
11368 ins_encode %{
11369 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11370 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11371 %}
11372 ins_pipe(pipe_class_default);
11373 %}
11375 // As insrwi_a, but with USE_DEF.
11376 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11377 effect(USE_DEF dst, USE src, USE pos, USE shift);
11378 predicate(false);
11380 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11381 size(4);
11382 ins_encode %{
11383 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11384 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11385 %}
11386 ins_pipe(pipe_class_default);
11387 %}
11389 // Just slightly faster than java implementation.
11390 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11391 match(Set dst (ReverseBytesI src));
11392 predicate(UseCountLeadingZerosInstructionsPPC64);
11393 ins_cost(DEFAULT_COST);
11395 expand %{
11396 immI16 imm24 %{ (int) 24 %}
11397 immI16 imm16 %{ (int) 16 %}
11398 immI16 imm8 %{ (int) 8 %}
11399 immI16 imm4 %{ (int) 4 %}
11400 immI16 imm0 %{ (int) 0 %}
11401 iRegLdst tmpI1;
11402 iRegLdst tmpI2;
11403 iRegLdst tmpI3;
11405 urShiftI_reg_imm(tmpI1, src, imm24);
11406 insrwi_a(dst, tmpI1, imm24, imm8);
11407 urShiftI_reg_imm(tmpI2, src, imm16);
11408 insrwi(dst, tmpI2, imm8, imm16);
11409 urShiftI_reg_imm(tmpI3, src, imm8);
11410 insrwi(dst, tmpI3, imm8, imm8);
11411 insrwi(dst, src, imm0, imm8);
11412 %}
11413 %}
11415 //---------- Replicate Vector Instructions ------------------------------------
11417 // Insrdi does replicate if src == dst.
11418 instruct repl32(iRegLdst dst) %{
11419 predicate(false);
11420 effect(USE_DEF dst);
11422 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11423 size(4);
11424 ins_encode %{
11425 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11426 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11427 %}
11428 ins_pipe(pipe_class_default);
11429 %}
11431 // Insrdi does replicate if src == dst.
11432 instruct repl48(iRegLdst dst) %{
11433 predicate(false);
11434 effect(USE_DEF dst);
11436 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11437 size(4);
11438 ins_encode %{
11439 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11440 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11441 %}
11442 ins_pipe(pipe_class_default);
11443 %}
11445 // Insrdi does replicate if src == dst.
11446 instruct repl56(iRegLdst dst) %{
11447 predicate(false);
11448 effect(USE_DEF dst);
11450 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11451 size(4);
11452 ins_encode %{
11453 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11454 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11455 %}
11456 ins_pipe(pipe_class_default);
11457 %}
11459 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11460 match(Set dst (ReplicateB src));
11461 predicate(n->as_Vector()->length() == 8);
11462 expand %{
11463 moveReg(dst, src);
11464 repl56(dst);
11465 repl48(dst);
11466 repl32(dst);
11467 %}
11468 %}
11470 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11471 match(Set dst (ReplicateB zero));
11472 predicate(n->as_Vector()->length() == 8);
11473 format %{ "LI $dst, #0 \t// replicate8B" %}
11474 size(4);
11475 ins_encode %{
11476 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11477 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11478 %}
11479 ins_pipe(pipe_class_default);
11480 %}
11482 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11483 match(Set dst (ReplicateB src));
11484 predicate(n->as_Vector()->length() == 8);
11485 format %{ "LI $dst, #-1 \t// replicate8B" %}
11486 size(4);
11487 ins_encode %{
11488 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11489 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11490 %}
11491 ins_pipe(pipe_class_default);
11492 %}
11494 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11495 match(Set dst (ReplicateS src));
11496 predicate(n->as_Vector()->length() == 4);
11497 expand %{
11498 moveReg(dst, src);
11499 repl48(dst);
11500 repl32(dst);
11501 %}
11502 %}
11504 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11505 match(Set dst (ReplicateS zero));
11506 predicate(n->as_Vector()->length() == 4);
11507 format %{ "LI $dst, #0 \t// replicate4C" %}
11508 size(4);
11509 ins_encode %{
11510 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11511 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11512 %}
11513 ins_pipe(pipe_class_default);
11514 %}
11516 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11517 match(Set dst (ReplicateS src));
11518 predicate(n->as_Vector()->length() == 4);
11519 format %{ "LI $dst, -1 \t// replicate4C" %}
11520 size(4);
11521 ins_encode %{
11522 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11523 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11524 %}
11525 ins_pipe(pipe_class_default);
11526 %}
11528 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11529 match(Set dst (ReplicateI src));
11530 predicate(n->as_Vector()->length() == 2);
11531 ins_cost(2 * DEFAULT_COST);
11532 expand %{
11533 moveReg(dst, src);
11534 repl32(dst);
11535 %}
11536 %}
11538 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11539 match(Set dst (ReplicateI zero));
11540 predicate(n->as_Vector()->length() == 2);
11541 format %{ "LI $dst, #0 \t// replicate4C" %}
11542 size(4);
11543 ins_encode %{
11544 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11545 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11546 %}
11547 ins_pipe(pipe_class_default);
11548 %}
11550 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11551 match(Set dst (ReplicateI src));
11552 predicate(n->as_Vector()->length() == 2);
11553 format %{ "LI $dst, -1 \t// replicate4C" %}
11554 size(4);
11555 ins_encode %{
11556 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11557 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11558 %}
11559 ins_pipe(pipe_class_default);
11560 %}
11562 // Move float to int register via stack, replicate.
11563 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11564 match(Set dst (ReplicateF src));
11565 predicate(n->as_Vector()->length() == 2);
11566 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11567 expand %{
11568 stackSlotL tmpS;
11569 iRegIdst tmpI;
11570 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11571 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11572 moveReg(dst, tmpI); // Move int to long reg.
11573 repl32(dst); // Replicate bitpattern.
11574 %}
11575 %}
11577 // Replicate scalar constant to packed float values in Double register
11578 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11579 match(Set dst (ReplicateF src));
11580 predicate(n->as_Vector()->length() == 2);
11581 ins_cost(5 * DEFAULT_COST);
11583 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11584 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11585 %}
11587 // Replicate scalar zero constant to packed float values in Double register
11588 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11589 match(Set dst (ReplicateF zero));
11590 predicate(n->as_Vector()->length() == 2);
11592 format %{ "LI $dst, #0 \t// replicate2F" %}
11593 ins_encode %{
11594 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11595 __ li($dst$$Register, 0x0);
11596 %}
11597 ins_pipe(pipe_class_default);
11598 %}
11600 // ============================================================================
11601 // Safepoint Instruction
11603 instruct safePoint_poll(iRegPdst poll) %{
11604 match(SafePoint poll);
11605 predicate(LoadPollAddressFromThread);
11607 // It caused problems to add the effect that r0 is killed, but this
11608 // effect no longer needs to be mentioned, since r0 is not contained
11609 // in a reg_class.
11611 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11612 size(4);
11613 ins_encode( enc_poll(0x0, poll) );
11614 ins_pipe(pipe_class_default);
11615 %}
11617 // Safepoint without per-thread support. Load address of page to poll
11618 // as constant.
11619 // Rscratch2RegP is R12.
11620 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11621 // a seperate node so that the oop map is at the right location.
11622 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11623 match(SafePoint poll);
11624 predicate(!LoadPollAddressFromThread);
11626 // It caused problems to add the effect that r0 is killed, but this
11627 // effect no longer needs to be mentioned, since r0 is not contained
11628 // in a reg_class.
11630 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11631 ins_encode( enc_poll(0x0, poll) );
11632 ins_pipe(pipe_class_default);
11633 %}
11635 // ============================================================================
11636 // Call Instructions
11638 // Call Java Static Instruction
11640 // Schedulable version of call static node.
11641 instruct CallStaticJavaDirect(method meth) %{
11642 match(CallStaticJava);
11643 effect(USE meth);
11644 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11645 ins_cost(CALL_COST);
11647 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11649 format %{ "CALL,static $meth \t// ==> " %}
11650 size(4);
11651 ins_encode( enc_java_static_call(meth) );
11652 ins_pipe(pipe_class_call);
11653 %}
11655 // Schedulable version of call static node.
11656 instruct CallStaticJavaDirectHandle(method meth) %{
11657 match(CallStaticJava);
11658 effect(USE meth);
11659 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11660 ins_cost(CALL_COST);
11662 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11664 format %{ "CALL,static $meth \t// ==> " %}
11665 ins_encode( enc_java_handle_call(meth) );
11666 ins_pipe(pipe_class_call);
11667 %}
11669 // Call Java Dynamic Instruction
11671 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11672 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11673 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11674 // The call destination must still be placed in the constant pool.
11675 instruct CallDynamicJavaDirectSched(method meth) %{
11676 match(CallDynamicJava); // To get all the data fields we need ...
11677 effect(USE meth);
11678 predicate(false); // ... but never match.
11680 ins_field_load_ic_hi_node(loadConL_hiNode*);
11681 ins_field_load_ic_node(loadConLNode*);
11682 ins_num_consts(1 /* 1 patchable constant: call destination */);
11684 format %{ "BL \t// dynamic $meth ==> " %}
11685 size(4);
11686 ins_encode( enc_java_dynamic_call_sched(meth) );
11687 ins_pipe(pipe_class_call);
11688 %}
11690 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11691 // We use postalloc expanded calls if we use inline caches
11692 // and do not update method data.
11693 //
11694 // This instruction has two constants: inline cache (IC) and call destination.
11695 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11696 // one constant.
11697 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11698 match(CallDynamicJava);
11699 effect(USE meth);
11700 predicate(UseInlineCaches);
11701 ins_cost(CALL_COST);
11703 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11705 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11706 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11707 %}
11709 // Compound version of call dynamic java
11710 // We use postalloc expanded calls if we use inline caches
11711 // and do not update method data.
11712 instruct CallDynamicJavaDirect(method meth) %{
11713 match(CallDynamicJava);
11714 effect(USE meth);
11715 predicate(!UseInlineCaches);
11716 ins_cost(CALL_COST);
11718 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11719 ins_num_consts(4);
11721 format %{ "CALL,dynamic $meth \t// ==> " %}
11722 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11723 ins_pipe(pipe_class_call);
11724 %}
11726 // Call Runtime Instruction
11728 instruct CallRuntimeDirect(method meth) %{
11729 match(CallRuntime);
11730 effect(USE meth);
11731 ins_cost(CALL_COST);
11733 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11734 // env for callee, C-toc.
11735 ins_num_consts(3);
11737 format %{ "CALL,runtime" %}
11738 ins_encode( enc_java_to_runtime_call(meth) );
11739 ins_pipe(pipe_class_call);
11740 %}
11742 // Call Leaf
11744 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11745 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11746 effect(DEF dst, USE src);
11748 ins_num_consts(1);
11750 format %{ "MTCTR $src" %}
11751 size(4);
11752 ins_encode( enc_leaf_call_mtctr(src) );
11753 ins_pipe(pipe_class_default);
11754 %}
11756 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11757 instruct CallLeafDirect(method meth) %{
11758 match(CallLeaf); // To get the data all the data fields we need ...
11759 effect(USE meth);
11760 predicate(false); // but never match.
11762 format %{ "BCTRL \t// leaf call $meth ==> " %}
11763 size(4);
11764 ins_encode %{
11765 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11766 __ bctrl();
11767 %}
11768 ins_pipe(pipe_class_call);
11769 %}
11771 // postalloc expand of CallLeafDirect.
11772 // Load adress to call from TOC, then bl to it.
11773 instruct CallLeafDirect_Ex(method meth) %{
11774 match(CallLeaf);
11775 effect(USE meth);
11776 ins_cost(CALL_COST);
11778 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11779 // env for callee, C-toc.
11780 ins_num_consts(3);
11782 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11783 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11784 %}
11786 // Call runtime without safepoint - same as CallLeaf.
11787 // postalloc expand of CallLeafNoFPDirect.
11788 // Load adress to call from TOC, then bl to it.
11789 instruct CallLeafNoFPDirect_Ex(method meth) %{
11790 match(CallLeafNoFP);
11791 effect(USE meth);
11792 ins_cost(CALL_COST);
11794 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11795 // env for callee, C-toc.
11796 ins_num_consts(3);
11798 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11799 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11800 %}
11802 // Tail Call; Jump from runtime stub to Java code.
11803 // Also known as an 'interprocedural jump'.
11804 // Target of jump will eventually return to caller.
11805 // TailJump below removes the return address.
11806 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11807 match(TailCall jump_target method_oop);
11808 ins_cost(CALL_COST);
11810 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11811 "BCTR \t// tail call" %}
11812 size(8);
11813 ins_encode %{
11814 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11815 __ mtctr($jump_target$$Register);
11816 __ bctr();
11817 %}
11818 ins_pipe(pipe_class_call);
11819 %}
11821 // Return Instruction
11822 instruct Ret() %{
11823 match(Return);
11824 format %{ "BLR \t// branch to link register" %}
11825 size(4);
11826 ins_encode %{
11827 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11828 // LR is restored in MachEpilogNode. Just do the RET here.
11829 __ blr();
11830 %}
11831 ins_pipe(pipe_class_default);
11832 %}
11834 // Tail Jump; remove the return address; jump to target.
11835 // TailCall above leaves the return address around.
11836 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11837 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11838 // "restore" before this instruction (in Epilogue), we need to materialize it
11839 // in %i0.
11840 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11841 match(TailJump jump_target ex_oop);
11842 ins_cost(CALL_COST);
11844 format %{ "LD R4_ARG2 = LR\n\t"
11845 "MTCTR $jump_target\n\t"
11846 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11847 size(12);
11848 ins_encode %{
11849 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11850 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11851 __ mtctr($jump_target$$Register);
11852 __ bctr();
11853 %}
11854 ins_pipe(pipe_class_call);
11855 %}
11857 // Create exception oop: created by stack-crawling runtime code.
11858 // Created exception is now available to this handler, and is setup
11859 // just prior to jumping to this handler. No code emitted.
11860 instruct CreateException(rarg1RegP ex_oop) %{
11861 match(Set ex_oop (CreateEx));
11862 ins_cost(0);
11864 format %{ " -- \t// exception oop; no code emitted" %}
11865 size(0);
11866 ins_encode( /*empty*/ );
11867 ins_pipe(pipe_class_default);
11868 %}
11870 // Rethrow exception: The exception oop will come in the first
11871 // argument position. Then JUMP (not call) to the rethrow stub code.
11872 instruct RethrowException() %{
11873 match(Rethrow);
11874 ins_cost(CALL_COST);
11876 format %{ "Jmp rethrow_stub" %}
11877 ins_encode %{
11878 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11879 cbuf.set_insts_mark();
11880 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11881 %}
11882 ins_pipe(pipe_class_call);
11883 %}
11885 // Die now.
11886 instruct ShouldNotReachHere() %{
11887 match(Halt);
11888 ins_cost(CALL_COST);
11890 format %{ "ShouldNotReachHere" %}
11891 size(4);
11892 ins_encode %{
11893 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11894 __ trap_should_not_reach_here();
11895 %}
11896 ins_pipe(pipe_class_default);
11897 %}
11899 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11900 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11901 // Get a DEF on threadRegP, no costs, no encoding, use
11902 // 'ins_should_rematerialize(true)' to avoid spilling.
11903 instruct tlsLoadP(threadRegP dst) %{
11904 match(Set dst (ThreadLocal));
11905 ins_cost(0);
11907 ins_should_rematerialize(true);
11909 format %{ " -- \t// $dst=Thread::current(), empty" %}
11910 size(0);
11911 ins_encode( /*empty*/ );
11912 ins_pipe(pipe_class_empty);
11913 %}
11915 //---Some PPC specific nodes---------------------------------------------------
11917 // Stop a group.
11918 instruct endGroup() %{
11919 ins_cost(0);
11921 ins_is_nop(true);
11923 format %{ "End Bundle (ori r1, r1, 0)" %}
11924 size(4);
11925 ins_encode %{
11926 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11927 __ endgroup();
11928 %}
11929 ins_pipe(pipe_class_default);
11930 %}
11932 // Nop instructions
11934 instruct fxNop() %{
11935 ins_cost(0);
11937 ins_is_nop(true);
11939 format %{ "fxNop" %}
11940 size(4);
11941 ins_encode %{
11942 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11943 __ nop();
11944 %}
11945 ins_pipe(pipe_class_default);
11946 %}
11948 instruct fpNop0() %{
11949 ins_cost(0);
11951 ins_is_nop(true);
11953 format %{ "fpNop0" %}
11954 size(4);
11955 ins_encode %{
11956 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11957 __ fpnop0();
11958 %}
11959 ins_pipe(pipe_class_default);
11960 %}
11962 instruct fpNop1() %{
11963 ins_cost(0);
11965 ins_is_nop(true);
11967 format %{ "fpNop1" %}
11968 size(4);
11969 ins_encode %{
11970 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11971 __ fpnop1();
11972 %}
11973 ins_pipe(pipe_class_default);
11974 %}
11976 instruct brNop0() %{
11977 ins_cost(0);
11978 size(4);
11979 format %{ "brNop0" %}
11980 ins_encode %{
11981 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11982 __ brnop0();
11983 %}
11984 ins_is_nop(true);
11985 ins_pipe(pipe_class_default);
11986 %}
11988 instruct brNop1() %{
11989 ins_cost(0);
11991 ins_is_nop(true);
11993 format %{ "brNop1" %}
11994 size(4);
11995 ins_encode %{
11996 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11997 __ brnop1();
11998 %}
11999 ins_pipe(pipe_class_default);
12000 %}
12002 instruct brNop2() %{
12003 ins_cost(0);
12005 ins_is_nop(true);
12007 format %{ "brNop2" %}
12008 size(4);
12009 ins_encode %{
12010 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12011 __ brnop2();
12012 %}
12013 ins_pipe(pipe_class_default);
12014 %}
12016 //----------PEEPHOLE RULES-----------------------------------------------------
12017 // These must follow all instruction definitions as they use the names
12018 // defined in the instructions definitions.
12019 //
12020 // peepmatch ( root_instr_name [preceeding_instruction]* );
12021 //
12022 // peepconstraint %{
12023 // (instruction_number.operand_name relational_op instruction_number.operand_name
12024 // [, ...] );
12025 // // instruction numbers are zero-based using left to right order in peepmatch
12026 //
12027 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12028 // // provide an instruction_number.operand_name for each operand that appears
12029 // // in the replacement instruction's match rule
12030 //
12031 // ---------VM FLAGS---------------------------------------------------------
12032 //
12033 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12034 //
12035 // Each peephole rule is given an identifying number starting with zero and
12036 // increasing by one in the order seen by the parser. An individual peephole
12037 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12038 // on the command-line.
12039 //
12040 // ---------CURRENT LIMITATIONS----------------------------------------------
12041 //
12042 // Only match adjacent instructions in same basic block
12043 // Only equality constraints
12044 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12045 // Only one replacement instruction
12046 //
12047 // ---------EXAMPLE----------------------------------------------------------
12048 //
12049 // // pertinent parts of existing instructions in architecture description
12050 // instruct movI(eRegI dst, eRegI src) %{
12051 // match(Set dst (CopyI src));
12052 // %}
12053 //
12054 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12055 // match(Set dst (AddI dst src));
12056 // effect(KILL cr);
12057 // %}
12058 //
12059 // // Change (inc mov) to lea
12060 // peephole %{
12061 // // increment preceeded by register-register move
12062 // peepmatch ( incI_eReg movI );
12063 // // require that the destination register of the increment
12064 // // match the destination register of the move
12065 // peepconstraint ( 0.dst == 1.dst );
12066 // // construct a replacement instruction that sets
12067 // // the destination to ( move's source register + one )
12068 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12069 // %}
12070 //
12071 // Implementation no longer uses movX instructions since
12072 // machine-independent system no longer uses CopyX nodes.
12073 //
12074 // peephole %{
12075 // peepmatch ( incI_eReg movI );
12076 // peepconstraint ( 0.dst == 1.dst );
12077 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12078 // %}
12079 //
12080 // peephole %{
12081 // peepmatch ( decI_eReg movI );
12082 // peepconstraint ( 0.dst == 1.dst );
12083 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12084 // %}
12085 //
12086 // peephole %{
12087 // peepmatch ( addI_eReg_imm movI );
12088 // peepconstraint ( 0.dst == 1.dst );
12089 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12090 // %}
12091 //
12092 // peephole %{
12093 // peepmatch ( addP_eReg_imm movP );
12094 // peepconstraint ( 0.dst == 1.dst );
12095 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12096 // %}
12098 // // Change load of spilled value to only a spill
12099 // instruct storeI(memory mem, eRegI src) %{
12100 // match(Set mem (StoreI mem src));
12101 // %}
12102 //
12103 // instruct loadI(eRegI dst, memory mem) %{
12104 // match(Set dst (LoadI mem));
12105 // %}
12106 //
12107 peephole %{
12108 peepmatch ( loadI storeI );
12109 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12110 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12111 %}
12113 peephole %{
12114 peepmatch ( loadL storeL );
12115 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12116 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12117 %}
12119 peephole %{
12120 peepmatch ( loadP storeP );
12121 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12122 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12123 %}
12125 //----------SMARTSPILL RULES---------------------------------------------------
12126 // These must follow all instruction definitions as they use the names
12127 // defined in the instructions definitions.