Tue, 11 Jul 2017 09:40:23 +0800
#5681 make all is OK.
1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
26 // GodSon3 Architecture Description File
28 //----------REGISTER DEFINITION BLOCK------------------------------------------
29 // This information is used by the matcher and the register allocator to
30 // describe individual registers and classes of registers within the target
31 // archtecture.
33 // format:
34 // reg_def name (call convention, c-call convention, ideal type, encoding);
35 // call convention :
36 // NS = No-Save
37 // SOC = Save-On-Call
38 // SOE = Save-On-Entry
39 // AS = Always-Save
40 // ideal type :
41 // see opto/opcodes.hpp for more info
42 // reg_class name (reg, ...);
43 // alloc_class name (reg, ...);
44 register %{
46 // General Registers
47 // Integer Registers
48 reg_def R0 ( NS, NS, Op_RegI, 0, VMRegImpl::Bad());
49 reg_def AT ( NS, NS, Op_RegI, 1, AT->as_VMReg());
50 reg_def AT_H ( NS, NS, Op_RegI, 1, AT->as_VMReg()->next());
51 reg_def V0 (SOC, SOC, Op_RegI, 2, V0->as_VMReg());
52 reg_def V0_H (SOC, SOC, Op_RegI, 2, V0->as_VMReg()->next());
53 reg_def V1 (SOC, SOC, Op_RegI, 3, V1->as_VMReg());
54 reg_def V1_H (SOC, SOC, Op_RegI, 3, V1->as_VMReg()->next());
55 reg_def A0 (SOC, SOC, Op_RegI, 4, A0->as_VMReg());
56 reg_def A0_H (SOC, SOC, Op_RegI, 4, A0->as_VMReg()->next());
57 reg_def A1 (SOC, SOC, Op_RegI, 5, A1->as_VMReg());
58 reg_def A1_H (SOC, SOC, Op_RegI, 5, A1->as_VMReg()->next());
59 reg_def A2 (SOC, SOC, Op_RegI, 6, A2->as_VMReg());
60 reg_def A2_H (SOC, SOC, Op_RegI, 6, A2->as_VMReg()->next());
61 reg_def A3 (SOC, SOC, Op_RegI, 7, A3->as_VMReg());
62 reg_def A3_H (SOC, SOC, Op_RegI, 7, A3->as_VMReg()->next());
63 reg_def A4 (SOC, SOC, Op_RegI, 8, A4->as_VMReg());
64 reg_def A4_H (SOC, SOC, Op_RegI, 8, A4->as_VMReg()->next());
65 reg_def A5 (SOC, SOC, Op_RegI, 9, A5->as_VMReg());
66 reg_def A5_H (SOC, SOC, Op_RegI, 9, A5->as_VMReg()->next());
67 reg_def A6 (SOC, SOC, Op_RegI, 10, A6->as_VMReg());
68 reg_def A6_H (SOC, SOC, Op_RegI, 10, A6->as_VMReg()->next());
69 reg_def A7 (SOC, SOC, Op_RegI, 11, A7->as_VMReg());
70 reg_def A7_H (SOC, SOC, Op_RegI, 11, A7->as_VMReg()->next());
71 reg_def T0 (SOC, SOC, Op_RegI, 12, T0->as_VMReg());
72 reg_def T0_H (SOC, SOC, Op_RegI, 12, T0->as_VMReg()->next());
73 reg_def T1 (SOC, SOC, Op_RegI, 13, T1->as_VMReg());
74 reg_def T1_H (SOC, SOC, Op_RegI, 13, T1->as_VMReg()->next());
75 reg_def T2 (SOC, SOC, Op_RegI, 14, T2->as_VMReg());
76 reg_def T2_H (SOC, SOC, Op_RegI, 14, T2->as_VMReg()->next());
77 reg_def T3 (SOC, SOC, Op_RegI, 15, T3->as_VMReg());
78 reg_def T3_H (SOC, SOC, Op_RegI, 15, T3->as_VMReg()->next());
79 reg_def S0 (SOC, SOE, Op_RegI, 16, S0->as_VMReg());
80 reg_def S0_H (SOC, SOE, Op_RegI, 16, S0->as_VMReg()->next());
81 reg_def S1 (SOC, SOE, Op_RegI, 17, S1->as_VMReg());
82 reg_def S1_H (SOC, SOE, Op_RegI, 17, S1->as_VMReg()->next());
83 reg_def S2 (SOC, SOE, Op_RegI, 18, S2->as_VMReg());
84 reg_def S2_H (SOC, SOE, Op_RegI, 18, S2->as_VMReg()->next());
85 reg_def S3 (SOC, SOE, Op_RegI, 19, S3->as_VMReg());
86 reg_def S3_H (SOC, SOE, Op_RegI, 19, S3->as_VMReg()->next());
87 reg_def S4 (SOC, SOE, Op_RegI, 20, S4->as_VMReg());
88 reg_def S4_H (SOC, SOE, Op_RegI, 20, S4->as_VMReg()->next());
89 reg_def S5 (SOC, SOE, Op_RegI, 21, S5->as_VMReg());
90 reg_def S5_H (SOC, SOE, Op_RegI, 21, S5->as_VMReg()->next());
91 reg_def S6 (SOC, SOE, Op_RegI, 22, S6->as_VMReg());
92 reg_def S6_H (SOC, SOE, Op_RegI, 22, S6->as_VMReg()->next());
93 reg_def S7 (SOC, SOE, Op_RegI, 23, S7->as_VMReg());
94 reg_def S7_H (SOC, SOE, Op_RegI, 23, S7->as_VMReg()->next());
95 reg_def T8 (SOC, SOC, Op_RegI, 24, T8->as_VMReg());
96 reg_def T8_H (SOC, SOC, Op_RegI, 24, T8->as_VMReg()->next());
97 reg_def T9 (SOC, SOC, Op_RegI, 25, T9->as_VMReg());
98 reg_def T9_H (SOC, SOC, Op_RegI, 25, T9->as_VMReg()->next());
100 // Special Registers
101 reg_def K0 ( NS, NS, Op_RegI, 26, K0->as_VMReg());
102 reg_def K1 ( NS, NS, Op_RegI, 27, K1->as_VMReg());
103 reg_def GP ( NS, NS, Op_RegI, 28, GP->as_VMReg());
104 reg_def GP_H ( NS, NS, Op_RegI, 28, GP->as_VMReg()->next());
105 reg_def SP ( NS, NS, Op_RegI, 29, SP->as_VMReg());
106 reg_def SP_H ( NS, NS, Op_RegI, 29, SP->as_VMReg()->next());
107 reg_def FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
108 reg_def FP_H ( NS, NS, Op_RegI, 30, FP->as_VMReg()->next());
109 reg_def RA ( NS, NS, Op_RegI, 31, RA->as_VMReg());
110 reg_def RA_H ( NS, NS, Op_RegI, 31, RA->as_VMReg()->next());
112 // Floating registers.
113 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
114 reg_def F0_H ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()->next());
115 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
116 reg_def F1_H ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()->next());
117 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
118 reg_def F2_H ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()->next());
119 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
120 reg_def F3_H ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()->next());
121 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
122 reg_def F4_H ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()->next());
123 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
124 reg_def F5_H ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()->next());
125 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
126 reg_def F6_H ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()->next());
127 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
128 reg_def F7_H ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()->next());
129 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
130 reg_def F8_H ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()->next());
131 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
132 reg_def F9_H ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()->next());
133 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
134 reg_def F10_H ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()->next());
135 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
136 reg_def F11_H ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()->next());
137 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
138 reg_def F12_H ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()->next());
139 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
140 reg_def F13_H ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()->next());
141 reg_def F14 ( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
142 reg_def F14_H ( SOC, SOC, Op_RegF, 14, F14->as_VMReg()->next());
143 reg_def F15 ( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
144 reg_def F15_H ( SOC, SOC, Op_RegF, 15, F15->as_VMReg()->next());
145 reg_def F16 ( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
146 reg_def F16_H ( SOC, SOC, Op_RegF, 16, F16->as_VMReg()->next());
147 reg_def F17 ( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
148 reg_def F17_H ( SOC, SOC, Op_RegF, 17, F17->as_VMReg()->next());
149 reg_def F18 ( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
150 reg_def F18_H ( SOC, SOC, Op_RegF, 18, F18->as_VMReg()->next());
151 reg_def F19 ( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
152 reg_def F19_H ( SOC, SOC, Op_RegF, 19, F19->as_VMReg()->next());
153 reg_def F20 ( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
154 reg_def F20_H ( SOC, SOC, Op_RegF, 20, F20->as_VMReg()->next());
155 reg_def F21 ( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
156 reg_def F21_H ( SOC, SOC, Op_RegF, 21, F21->as_VMReg()->next());
157 reg_def F22 ( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
158 reg_def F22_H ( SOC, SOC, Op_RegF, 22, F22->as_VMReg()->next());
159 reg_def F23 ( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
160 reg_def F23_H ( SOC, SOC, Op_RegF, 23, F23->as_VMReg()->next());
161 reg_def F24 ( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
162 reg_def F24_H ( SOC, SOC, Op_RegF, 24, F24->as_VMReg()->next());
163 reg_def F25 ( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
164 reg_def F25_H ( SOC, SOC, Op_RegF, 25, F25->as_VMReg()->next());
165 reg_def F26 ( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
166 reg_def F26_H ( SOC, SOC, Op_RegF, 26, F26->as_VMReg()->next());
167 reg_def F27 ( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
168 reg_def F27_H ( SOC, SOC, Op_RegF, 27, F27->as_VMReg()->next());
169 reg_def F28 ( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
170 reg_def F28_H ( SOC, SOC, Op_RegF, 28, F28->as_VMReg()->next());
171 reg_def F29 ( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
172 reg_def F29_H ( SOC, SOC, Op_RegF, 29, F29->as_VMReg()->next());
173 reg_def F30 ( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
174 reg_def F30_H ( SOC, SOC, Op_RegF, 30, F30->as_VMReg()->next());
175 reg_def F31 ( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
176 reg_def F31_H ( SOC, SOC, Op_RegF, 31, F31->as_VMReg()->next());
179 // ----------------------------
180 // Special Registers
181 // Condition Codes Flag Registers
182 reg_def MIPS_FLAG (SOC, SOC, Op_RegFlags, 1, as_Register(1)->as_VMReg());
183 //S6 is used for get_thread(S6)
184 //S5 is uesd for heapbase of compressed oop
185 alloc_class chunk0(
186 S7, S7_H,
187 S0, S0_H,
188 S1, S1_H,
189 S2, S2_H,
190 S4, S4_H,
191 S5, S5_H,
192 S6, S6_H,
193 S3, S3_H,
194 T2, T2_H,
195 T3, T3_H,
196 T8, T8_H,
197 T9, T9_H,
198 T1, T1_H, // inline_cache_reg
199 V1, V1_H,
200 A7, A7_H,
201 A6, A6_H,
202 A5, A5_H,
203 A4, A4_H,
204 V0, V0_H,
205 A3, A3_H,
206 A2, A2_H,
207 A1, A1_H,
208 A0, A0_H,
209 T0, T0_H,
210 GP, GP_H
211 RA, RA_H,
212 SP, SP_H, // stack_pointer
213 FP, FP_H // frame_pointer
214 );
216 alloc_class chunk1( F0, F0_H,
217 F1, F1_H,
218 F2, F2_H,
219 F3, F3_H,
220 F4, F4_H,
221 F5, F5_H,
222 F6, F6_H,
223 F7, F7_H,
224 F8, F8_H,
225 F9, F9_H,
226 F10, F10_H,
227 F11, F11_H,
228 F20, F20_H,
229 F21, F21_H,
230 F22, F22_H,
231 F23, F23_H,
232 F24, F24_H,
233 F25, F25_H,
234 F26, F26_H,
235 F27, F27_H,
236 F28, F28_H,
237 F19, F19_H,
238 F18, F18_H,
239 F17, F17_H,
240 F16, F16_H,
241 F15, F15_H,
242 F14, F14_H,
243 F13, F13_H,
244 F12, F12_H,
245 F29, F29_H,
246 F30, F30_H,
247 F31, F31_H);
249 alloc_class chunk2(MIPS_FLAG);
251 reg_class s_reg( S0, S1, S2, S3, S4, S5, S6, S7 );
252 reg_class s0_reg( S0 );
253 reg_class s1_reg( S1 );
254 reg_class s2_reg( S2 );
255 reg_class s3_reg( S3 );
256 reg_class s4_reg( S4 );
257 reg_class s5_reg( S5 );
258 reg_class s6_reg( S6 );
259 reg_class s7_reg( S7 );
261 reg_class t_reg( T0, T1, T2, T3, T8, T9 );
262 reg_class t0_reg( T0 );
263 reg_class t1_reg( T1 );
264 reg_class t2_reg( T2 );
265 reg_class t3_reg( T3 );
266 reg_class t8_reg( T8 );
267 reg_class t9_reg( T9 );
269 reg_class a_reg( A0, A1, A2, A3, A4, A5, A6, A7 );
270 reg_class a0_reg( A0 );
271 reg_class a1_reg( A1 );
272 reg_class a2_reg( A2 );
273 reg_class a3_reg( A3 );
274 reg_class a4_reg( A4 );
275 reg_class a5_reg( A5 );
276 reg_class a6_reg( A6 );
277 reg_class a7_reg( A7 );
279 reg_class v0_reg( V0 );
280 reg_class v1_reg( V1 );
282 reg_class sp_reg( SP, SP_H );
283 reg_class fp_reg( FP, FP_H );
285 reg_class mips_flags(MIPS_FLAG);
287 reg_class v0_long_reg( V0, V0_H );
288 reg_class v1_long_reg( V1, V1_H );
289 reg_class a0_long_reg( A0, A0_H );
290 reg_class a1_long_reg( A1, A1_H );
291 reg_class a2_long_reg( A2, A2_H );
292 reg_class a3_long_reg( A3, A3_H );
293 reg_class a4_long_reg( A4, A4_H );
294 reg_class a5_long_reg( A5, A5_H );
295 reg_class a6_long_reg( A6, A6_H );
296 reg_class a7_long_reg( A7, A7_H );
297 reg_class t0_long_reg( T0, T0_H );
298 reg_class t1_long_reg( T1, T1_H );
299 reg_class t2_long_reg( T2, T2_H );
300 reg_class t3_long_reg( T3, T3_H );
301 reg_class t8_long_reg( T8, T8_H );
302 reg_class t9_long_reg( T9, T9_H );
303 reg_class s0_long_reg( S0, S0_H );
304 reg_class s1_long_reg( S1, S1_H );
305 reg_class s2_long_reg( S2, S2_H );
306 reg_class s3_long_reg( S3, S3_H );
307 reg_class s4_long_reg( S4, S4_H );
308 reg_class s5_long_reg( S5, S5_H );
309 reg_class s6_long_reg( S6, S6_H );
310 reg_class s7_long_reg( S7, S7_H );
312 reg_class int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, A7, A6, A5, A4, V0, A3, A2, A1, A0, T0 );
314 reg_class no_Ax_int_reg( S7, S0, S1, S2, S4, S3, T8, T2, T3, T1, V1, V0, T0 );
316 reg_class p_reg(
317 S7, S7_H,
318 S0, S0_H,
319 S1, S1_H,
320 S2, S2_H,
321 S4, S4_H,
322 S3, S3_H,
323 T8, T8_H,
324 T2, T2_H,
325 T3, T3_H,
326 T1, T1_H,
327 A7, A7_H,
328 A6, A6_H,
329 A5, A5_H,
330 A4, A4_H,
331 A3, A3_H,
332 A2, A2_H,
333 A1, A1_H,
334 A0, A0_H,
335 T0, T0_H
336 );
338 reg_class no_T8_p_reg(
339 S7, S7_H,
340 S0, S0_H,
341 S1, S1_H,
342 S2, S2_H,
343 S4, S4_H,
344 S3, S3_H,
345 T2, T2_H,
346 T3, T3_H,
347 T1, T1_H,
348 A7, A7_H,
349 A6, A6_H,
350 A5, A5_H,
351 A4, A4_H,
352 A3, A3_H,
353 A2, A2_H,
354 A1, A1_H,
355 A0, A0_H,
356 T0, T0_H
357 );
359 reg_class long_reg(
360 S7, S7_H,
361 S0, S0_H,
362 S1, S1_H,
363 S2, S2_H,
364 S4, S4_H,
365 S3, S3_H,
366 T8, T8_H,
367 T2, T2_H,
368 T3, T3_H,
369 T1, T1_H,
370 A7, A7_H,
371 A6, A6_H,
372 A5, A5_H,
373 A4, A4_H,
374 A3, A3_H,
375 A2, A2_H,
376 A1, A1_H,
377 A0, A0_H,
378 T0, T0_H
379 );
382 // Floating point registers.
383 // 2012/8/23 Fu: F30/F31 are used as temporary registers in D2I
384 // 2016/12/1 aoqi: F31 are not used as temporary registers in D2I
385 reg_class flt_reg( F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17 F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F31);
386 reg_class dbl_reg( F0, F0_H,
387 F1, F1_H,
388 F2, F2_H,
389 F3, F3_H,
390 F4, F4_H,
391 F5, F5_H,
392 F6, F6_H,
393 F7, F7_H,
394 F8, F8_H,
395 F9, F9_H,
396 F10, F10_H,
397 F11, F11_H,
398 F12, F12_H,
399 F13, F13_H,
400 F14, F14_H,
401 F15, F15_H,
402 F16, F16_H,
403 F17, F17_H,
404 F18, F18_H,
405 F19, F19_H,
406 F20, F20_H,
407 F21, F21_H,
408 F22, F22_H,
409 F23, F23_H,
410 F24, F24_H,
411 F25, F25_H,
412 F26, F26_H,
413 F27, F27_H,
414 F28, F28_H,
415 F29, F29_H,
416 F31, F31_H);
418 reg_class flt_arg0( F12 );
419 reg_class dbl_arg0( F12, F12_H );
420 reg_class dbl_arg1( F14, F14_H );
422 %}
424 //----------DEFINITION BLOCK---------------------------------------------------
425 // Define name --> value mappings to inform the ADLC of an integer valued name
426 // Current support includes integer values in the range [0, 0x7FFFFFFF]
427 // Format:
428 // int_def <name> ( <int_value>, <expression>);
429 // Generated Code in ad_<arch>.hpp
430 // #define <name> (<expression>)
431 // // value == <int_value>
432 // Generated code in ad_<arch>.cpp adlc_verification()
433 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
434 //
435 definitions %{
436 int_def DEFAULT_COST ( 100, 100);
437 int_def HUGE_COST (1000000, 1000000);
439 // Memory refs are twice as expensive as run-of-the-mill.
440 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
442 // Branches are even more expensive.
443 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
444 // we use jr instruction to construct call, so more expensive
445 // by yjl 2/28/2006
446 int_def CALL_COST ( 500, DEFAULT_COST * 5);
447 /*
448 int_def EQUAL ( 1, 1 );
449 int_def NOT_EQUAL ( 2, 2 );
450 int_def GREATER ( 3, 3 );
451 int_def GREATER_EQUAL ( 4, 4 );
452 int_def LESS ( 5, 5 );
453 int_def LESS_EQUAL ( 6, 6 );
454 */
455 %}
459 //----------SOURCE BLOCK-------------------------------------------------------
460 // This is a block of C++ code which provides values, functions, and
461 // definitions necessary in the rest of the architecture description
463 source_hpp %{
464 // Header information of the source block.
465 // Method declarations/definitions which are used outside
466 // the ad-scope can conveniently be defined here.
467 //
468 // To keep related declarations/definitions/uses close together,
469 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
471 class CallStubImpl {
473 //--------------------------------------------------------------
474 //---< Used for optimization in Compile::shorten_branches >---
475 //--------------------------------------------------------------
477 public:
478 // Size of call trampoline stub.
479 static uint size_call_trampoline() {
480 return 0; // no call trampolines on this platform
481 }
483 // number of relocations needed by a call trampoline stub
484 static uint reloc_call_trampoline() {
485 return 0; // no call trampolines on this platform
486 }
487 };
489 class HandlerImpl {
491 public:
493 static int emit_exception_handler(CodeBuffer &cbuf);
494 static int emit_deopt_handler(CodeBuffer& cbuf);
496 static uint size_exception_handler() {
497 // NativeCall instruction size is the same as NativeJump.
498 // exception handler starts out as jump and can be patched to
499 // a call be deoptimization. (4932387)
500 // Note that this value is also credited (in output.cpp) to
501 // the size of the code section.
502 // return NativeJump::instruction_size;
503 int size = NativeCall::instruction_size;
504 return round_to(size, 16);
505 }
507 #ifdef _LP64
508 static uint size_deopt_handler() {
509 int size = NativeCall::instruction_size;
510 return round_to(size, 16);
511 }
512 #else
513 static uint size_deopt_handler() {
514 // NativeCall instruction size is the same as NativeJump.
515 // exception handler starts out as jump and can be patched to
516 // a call be deoptimization. (4932387)
517 // Note that this value is also credited (in output.cpp) to
518 // the size of the code section.
519 return 5 + NativeJump::instruction_size; // pushl(); jmp;
520 }
521 #endif
522 };
524 %} // end source_hpp
526 source %{
528 #define NO_INDEX 0
529 #define RELOC_IMM64 Assembler::imm_operand
530 #define RELOC_DISP32 Assembler::disp32_operand
533 #define __ _masm.
536 // Emit exception handler code.
537 // Stuff framesize into a register and call a VM stub routine.
538 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
539 // Note that the code buffer's insts_mark is always relative to insts.
540 // That's why we must use the macroassembler to generate a handler.
541 MacroAssembler _masm(&cbuf);
542 address base =
543 __ start_a_stub(size_exception_handler());
544 if (base == NULL) return 0; // CodeBuffer::expand failed
545 int offset = __ offset();
547 __ block_comment("; emit_exception_handler");
549 cbuf.set_insts_mark();
550 __ relocate(relocInfo::runtime_call_type);
551 __ patchable_jump((address)OptoRuntime::exception_blob()->entry_point());
552 __ align(16);
553 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
554 __ end_a_stub();
555 return offset;
556 }
558 // Emit deopt handler code.
559 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
560 // Note that the code buffer's insts_mark is always relative to insts.
561 // That's why we must use the macroassembler to generate a handler.
562 MacroAssembler _masm(&cbuf);
563 address base =
564 __ start_a_stub(size_deopt_handler());
566 // FIXME
567 if (base == NULL) return 0; // CodeBuffer::expand failed
568 int offset = __ offset();
570 __ block_comment("; emit_deopt_handler");
572 cbuf.set_insts_mark();
573 __ relocate(relocInfo::runtime_call_type);
574 __ patchable_call(SharedRuntime::deopt_blob()->unpack());
575 __ align(16);
576 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
577 __ end_a_stub();
578 return offset;
579 }
582 const bool Matcher::match_rule_supported(int opcode) {
583 if (!has_match_rule(opcode))
584 return false;
586 switch (opcode) {
587 //Op_CountLeadingZerosI Op_CountLeadingZerosL can be deleted, all MIPS CPUs support clz & dclz.
588 case Op_CountLeadingZerosI:
589 case Op_CountLeadingZerosL:
590 if (!UseCountLeadingZerosInstruction)
591 return false;
592 break;
593 case Op_CountTrailingZerosI:
594 case Op_CountTrailingZerosL:
595 if (!UseCountTrailingZerosInstruction)
596 return false;
597 break;
598 }
600 return true; // Per default match rules are supported.
601 }
603 //FIXME
604 // emit call stub, compiled java to interpreter
605 void emit_java_to_interp(CodeBuffer &cbuf ) {
606 // Stub is fixed up when the corresponding call is converted from calling
607 // compiled code to calling interpreted code.
608 // mov rbx,0
609 // jmp -1
611 address mark = cbuf.insts_mark(); // get mark within main instrs section
613 // Note that the code buffer's insts_mark is always relative to insts.
614 // That's why we must use the macroassembler to generate a stub.
615 MacroAssembler _masm(&cbuf);
617 address base =
618 __ start_a_stub(Compile::MAX_stubs_size);
619 if (base == NULL) return; // CodeBuffer::expand failed
620 // static stub relocation stores the instruction address of the call
622 __ relocate(static_stub_Relocation::spec(mark), 0);
624 // static stub relocation also tags the methodOop in the code-stream.
625 __ patchable_set48(S3, (long)0);
626 // This is recognized as unresolved by relocs/nativeInst/ic code
628 __ relocate(relocInfo::runtime_call_type);
630 cbuf.set_insts_mark();
631 address call_pc = (address)-1;
632 __ patchable_jump(call_pc);
633 __ align(16);
634 __ end_a_stub();
635 // Update current stubs pointer and restore code_end.
636 }
638 // size of call stub, compiled java to interpretor
639 uint size_java_to_interp() {
640 int size = 4 * 4 + NativeCall::instruction_size; // sizeof(li48) + NativeCall::instruction_size
641 return round_to(size, 16);
642 }
644 // relocation entries for call stub, compiled java to interpreter
645 uint reloc_java_to_interp() {
646 return 16; // in emit_java_to_interp + in Java_Static_Call
647 }
649 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
650 if( Assembler::is_simm16(offset) ) return true;
651 else {
652 assert(false, "Not implemented yet !" );
653 Unimplemented();
654 }
655 }
658 // No additional cost for CMOVL.
659 const int Matcher::long_cmove_cost() { return 0; }
661 // No CMOVF/CMOVD with SSE2
662 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
664 // Does the CPU require late expand (see block.cpp for description of late expand)?
665 const bool Matcher::require_postalloc_expand = false;
667 // Should the Matcher clone shifts on addressing modes, expecting them
668 // to be subsumed into complex addressing expressions or compute them
669 // into registers? True for Intel but false for most RISCs
670 const bool Matcher::clone_shift_expressions = false;
672 // Do we need to mask the count passed to shift instructions or does
673 // the cpu only look at the lower 5/6 bits anyway?
674 const bool Matcher::need_masked_shift_count = false;
676 bool Matcher::narrow_oop_use_complex_address() {
677 NOT_LP64(ShouldNotCallThis());
678 assert(UseCompressedOops, "only for compressed oops code");
679 return false;
680 }
682 bool Matcher::narrow_klass_use_complex_address() {
683 NOT_LP64(ShouldNotCallThis());
684 assert(UseCompressedClassPointers, "only for compressed klass code");
685 return false;
686 }
688 // This is UltraSparc specific, true just means we have fast l2f conversion
689 const bool Matcher::convL2FSupported(void) {
690 return true;
691 }
693 // Max vector size in bytes. 0 if not supported.
694 const int Matcher::vector_width_in_bytes(BasicType bt) {
695 if (MaxVectorSize == 0)
696 return 0;
697 assert(MaxVectorSize == 8, "");
698 return 8;
699 }
701 // Vector ideal reg
702 const int Matcher::vector_ideal_reg(int size) {
703 assert(MaxVectorSize == 8, "");
704 switch(size) {
705 case 8: return Op_VecD;
706 }
707 ShouldNotReachHere();
708 return 0;
709 }
711 // Only lowest bits of xmm reg are used for vector shift count.
712 const int Matcher::vector_shift_count_ideal_reg(int size) {
713 fatal("vector shift is not supported");
714 return Node::NotAMachineReg;
715 }
717 // Limits on vector size (number of elements) loaded into vector.
718 const int Matcher::max_vector_size(const BasicType bt) {
719 assert(is_java_primitive(bt), "only primitive type vectors");
720 return vector_width_in_bytes(bt)/type2aelembytes(bt);
721 }
723 const int Matcher::min_vector_size(const BasicType bt) {
724 return max_vector_size(bt); // Same as max.
725 }
727 // MIPS supports misaligned vectors store/load? FIXME
728 const bool Matcher::misaligned_vectors_ok() {
729 return false;
730 //return !AlignVector; // can be changed by flag
731 }
733 // Register for DIVI projection of divmodI
734 RegMask Matcher::divI_proj_mask() {
735 ShouldNotReachHere();
736 return RegMask();
737 }
739 // Register for MODI projection of divmodI
740 RegMask Matcher::modI_proj_mask() {
741 ShouldNotReachHere();
742 return RegMask();
743 }
745 // Register for DIVL projection of divmodL
746 RegMask Matcher::divL_proj_mask() {
747 ShouldNotReachHere();
748 return RegMask();
749 }
751 int Matcher::regnum_to_fpu_offset(int regnum) {
752 return regnum - 32; // The FP registers are in the second chunk
753 }
756 const bool Matcher::isSimpleConstant64(jlong value) {
757 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
758 return true;
759 }
762 // Return whether or not this register is ever used as an argument. This
763 // function is used on startup to build the trampoline stubs in generateOptoStub.
764 // Registers not mentioned will be killed by the VM call in the trampoline, and
765 // arguments in those registers not be available to the callee.
766 bool Matcher::can_be_java_arg( int reg ) {
767 /* Refer to: [sharedRuntime_mips_64.cpp] SharedRuntime::java_calling_convention() */
768 if ( reg == T0_num || reg == T0_H_num
769 || reg == A0_num || reg == A0_H_num
770 || reg == A1_num || reg == A1_H_num
771 || reg == A2_num || reg == A2_H_num
772 || reg == A3_num || reg == A3_H_num
773 || reg == A4_num || reg == A4_H_num
774 || reg == A5_num || reg == A5_H_num
775 || reg == A6_num || reg == A6_H_num
776 || reg == A7_num || reg == A7_H_num )
777 return true;
779 if ( reg == F12_num || reg == F12_H_num
780 || reg == F13_num || reg == F13_H_num
781 || reg == F14_num || reg == F14_H_num
782 || reg == F15_num || reg == F15_H_num
783 || reg == F16_num || reg == F16_H_num
784 || reg == F17_num || reg == F17_H_num
785 || reg == F18_num || reg == F18_H_num
786 || reg == F19_num || reg == F19_H_num )
787 return true;
789 return false;
790 }
792 bool Matcher::is_spillable_arg( int reg ) {
793 return can_be_java_arg(reg);
794 }
796 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
797 return false;
798 }
800 // Register for MODL projection of divmodL
801 RegMask Matcher::modL_proj_mask() {
802 ShouldNotReachHere();
803 return RegMask();
804 }
806 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
807 return FP_REG_mask();
808 }
810 // MIPS doesn't support AES intrinsics
811 const bool Matcher::pass_original_key_for_aes() {
812 return false;
813 }
815 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
816 //lui
817 //ori
818 //dsll
819 //ori
821 //jalr
822 //nop
824 return round_to(current_offset, alignment_required()) - current_offset;
825 }
827 int CallLeafDirectNode::compute_padding(int current_offset) const {
828 //lui
829 //ori
830 //dsll
831 //ori
833 //jalr
834 //nop
836 return round_to(current_offset, alignment_required()) - current_offset;
837 }
839 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
840 //lui
841 //ori
842 //dsll
843 //ori
845 //jalr
846 //nop
848 return round_to(current_offset, alignment_required()) - current_offset;
849 }
851 // If CPU can load and store mis-aligned doubles directly then no fixup is
852 // needed. Else we split the double into 2 integer pieces and move it
853 // piece-by-piece. Only happens when passing doubles into C code as the
854 // Java calling convention forces doubles to be aligned.
855 const bool Matcher::misaligned_doubles_ok = false;
856 // Do floats take an entire double register or just half?
857 //const bool Matcher::float_in_double = true;
858 bool Matcher::float_in_double() { return false; }
859 // Threshold size for cleararray.
860 const int Matcher::init_array_short_size = 8 * BytesPerLong;
861 // Do ints take an entire long register or just half?
862 const bool Matcher::int_in_long = true;
863 // Is it better to copy float constants, or load them directly from memory?
864 // Intel can load a float constant from a direct address, requiring no
865 // extra registers. Most RISCs will have to materialize an address into a
866 // register first, so they would do better to copy the constant from stack.
867 const bool Matcher::rematerialize_float_constants = false;
868 // Advertise here if the CPU requires explicit rounding operations
869 // to implement the UseStrictFP mode.
870 const bool Matcher::strict_fp_requires_explicit_rounding = false;
871 // The ecx parameter to rep stos for the ClearArray node is in dwords.
872 const bool Matcher::init_array_count_is_in_bytes = false;
875 // Indicate if the safepoint node needs the polling page as an input.
876 // Since MIPS doesn't have absolute addressing, it needs.
877 bool SafePointNode::needs_polling_address_input() {
878 return false;
879 }
881 // !!!!! Special hack to get all type of calls to specify the byte offset
882 // from the start of the call to the point where the return address
883 // will point.
884 int MachCallStaticJavaNode::ret_addr_offset() {
885 //lui
886 //ori
887 //nop
888 //nop
889 //jalr
890 //nop
891 return 24;
892 }
894 int MachCallDynamicJavaNode::ret_addr_offset() {
895 //lui IC_Klass,
896 //ori IC_Klass,
897 //dsll IC_Klass
898 //ori IC_Klass
900 //lui T9
901 //ori T9
902 //nop
903 //nop
904 //jalr T9
905 //nop
906 return 4 * 4 + 4 * 6;
907 }
909 //=============================================================================
911 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
912 enum RC { rc_bad, rc_int, rc_float, rc_stack };
913 static enum RC rc_class( OptoReg::Name reg ) {
914 if( !OptoReg::is_valid(reg) ) return rc_bad;
915 if (OptoReg::is_stack(reg)) return rc_stack;
916 VMReg r = OptoReg::as_VMReg(reg);
917 if (r->is_Register()) return rc_int;
918 assert(r->is_FloatRegister(), "must be");
919 return rc_float;
920 }
922 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
923 // Get registers to move
924 OptoReg::Name src_second = ra_->get_reg_second(in(1));
925 OptoReg::Name src_first = ra_->get_reg_first(in(1));
926 OptoReg::Name dst_second = ra_->get_reg_second(this );
927 OptoReg::Name dst_first = ra_->get_reg_first(this );
929 enum RC src_second_rc = rc_class(src_second);
930 enum RC src_first_rc = rc_class(src_first);
931 enum RC dst_second_rc = rc_class(dst_second);
932 enum RC dst_first_rc = rc_class(dst_first);
934 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
936 // Generate spill code!
937 int size = 0;
939 if( src_first == dst_first && src_second == dst_second )
940 return 0; // Self copy, no move
942 if (src_first_rc == rc_stack) {
943 // mem ->
944 if (dst_first_rc == rc_stack) {
945 // mem -> mem
946 assert(src_second != dst_first, "overlap");
947 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
948 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
949 // 64-bit
950 int src_offset = ra_->reg2offset(src_first);
951 int dst_offset = ra_->reg2offset(dst_first);
952 if (cbuf) {
953 MacroAssembler _masm(cbuf);
954 __ ld(AT, Address(SP, src_offset));
955 __ sd(AT, Address(SP, dst_offset));
956 #ifndef PRODUCT
957 } else {
958 if(!do_size){
959 if (size != 0) st->print("\n\t");
960 st->print("ld AT, [SP + #%d]\t# 64-bit mem-mem spill 1\n\t"
961 "sd AT, [SP + #%d]",
962 src_offset, dst_offset);
963 }
964 #endif
965 }
966 size += 8;
967 } else {
968 // 32-bit
969 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
970 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
971 // No pushl/popl, so:
972 int src_offset = ra_->reg2offset(src_first);
973 int dst_offset = ra_->reg2offset(dst_first);
974 if (cbuf) {
975 MacroAssembler _masm(cbuf);
976 __ lw(AT, Address(SP, src_offset));
977 __ sw(AT, Address(SP, dst_offset));
978 #ifndef PRODUCT
979 } else {
980 if(!do_size){
981 if (size != 0) st->print("\n\t");
982 st->print("lw AT, [SP + #%d] spill 2\n\t"
983 "sw AT, [SP + #%d]\n\t",
984 src_offset, dst_offset);
985 }
986 #endif
987 }
988 size += 8;
989 }
990 return size;
991 } else if (dst_first_rc == rc_int) {
992 // mem -> gpr
993 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
994 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
995 // 64-bit
996 int offset = ra_->reg2offset(src_first);
997 if (cbuf) {
998 MacroAssembler _masm(cbuf);
999 __ ld(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1000 #ifndef PRODUCT
1001 } else {
1002 if(!do_size){
1003 if (size != 0) st->print("\n\t");
1004 st->print("ld %s, [SP + #%d]\t# spill 3",
1005 Matcher::regName[dst_first],
1006 offset);
1007 }
1008 #endif
1009 }
1010 size += 4;
1011 } else {
1012 // 32-bit
1013 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1014 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1015 int offset = ra_->reg2offset(src_first);
1016 if (cbuf) {
1017 MacroAssembler _masm(cbuf);
1018 if (this->ideal_reg() == Op_RegI)
1019 __ lw(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1020 else
1021 __ lwu(as_Register(Matcher::_regEncode[dst_first]), Address(SP, offset));
1022 #ifndef PRODUCT
1023 } else {
1024 if(!do_size){
1025 if (size != 0) st->print("\n\t");
1026 if (this->ideal_reg() == Op_RegI)
1027 st->print("lw %s, [SP + #%d]\t# spill 4",
1028 Matcher::regName[dst_first],
1029 offset);
1030 else
1031 st->print("lwu %s, [SP + #%d]\t# spill 5",
1032 Matcher::regName[dst_first],
1033 offset);
1034 }
1035 #endif
1036 }
1037 size += 4;
1038 }
1039 return size;
1040 } else if (dst_first_rc == rc_float) {
1041 // mem-> xmm
1042 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1043 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1044 // 64-bit
1045 int offset = ra_->reg2offset(src_first);
1046 if (cbuf) {
1047 MacroAssembler _masm(cbuf);
1048 __ ldc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1049 #ifndef PRODUCT
1050 } else {
1051 if(!do_size){
1052 if (size != 0) st->print("\n\t");
1053 st->print("ldc1 %s, [SP + #%d]\t# spill 6",
1054 Matcher::regName[dst_first],
1055 offset);
1056 }
1057 #endif
1058 }
1059 size += 4;
1060 } else {
1061 // 32-bit
1062 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1063 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1064 int offset = ra_->reg2offset(src_first);
1065 if (cbuf) {
1066 MacroAssembler _masm(cbuf);
1067 __ lwc1( as_FloatRegister(Matcher::_regEncode[dst_first]), Address(SP, offset));
1068 #ifndef PRODUCT
1069 } else {
1070 if(!do_size){
1071 if (size != 0) st->print("\n\t");
1072 st->print("lwc1 %s, [SP + #%d]\t# spill 7",
1073 Matcher::regName[dst_first],
1074 offset);
1075 }
1076 #endif
1077 }
1078 size += 4;
1079 }
1080 return size;
1081 }
1082 } else if (src_first_rc == rc_int) {
1083 // gpr ->
1084 if (dst_first_rc == rc_stack) {
1085 // gpr -> mem
1086 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1087 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1088 // 64-bit
1089 int offset = ra_->reg2offset(dst_first);
1090 if (cbuf) {
1091 MacroAssembler _masm(cbuf);
1092 __ sd(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1093 #ifndef PRODUCT
1094 } else {
1095 if(!do_size){
1096 if (size != 0) st->print("\n\t");
1097 st->print("sd %s, [SP + #%d] # spill 8",
1098 Matcher::regName[src_first],
1099 offset);
1100 }
1101 #endif
1102 }
1103 size += 4;
1104 } else {
1105 // 32-bit
1106 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1107 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1108 int offset = ra_->reg2offset(dst_first);
1109 if (cbuf) {
1110 MacroAssembler _masm(cbuf);
1111 __ sw(as_Register(Matcher::_regEncode[src_first]), Address(SP, offset));
1112 #ifndef PRODUCT
1113 } else {
1114 if(!do_size){
1115 if (size != 0) st->print("\n\t");
1116 st->print("sw %s, [SP + #%d]\t# spill 9",
1117 Matcher::regName[src_first], offset);
1118 }
1119 #endif
1120 }
1121 size += 4;
1122 }
1123 return size;
1124 } else if (dst_first_rc == rc_int) {
1125 // gpr -> gpr
1126 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1127 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1128 // 64-bit
1129 if (cbuf) {
1130 MacroAssembler _masm(cbuf);
1131 __ move(as_Register(Matcher::_regEncode[dst_first]),
1132 as_Register(Matcher::_regEncode[src_first]));
1133 #ifndef PRODUCT
1134 } else {
1135 if(!do_size){
1136 if (size != 0) st->print("\n\t");
1137 st->print("move(64bit) %s <-- %s\t# spill 10",
1138 Matcher::regName[dst_first],
1139 Matcher::regName[src_first]);
1140 }
1141 #endif
1142 }
1143 size += 4;
1144 return size;
1145 } else {
1146 // 32-bit
1147 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1148 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1149 if (cbuf) {
1150 MacroAssembler _masm(cbuf);
1151 if (this->ideal_reg() == Op_RegI)
1152 __ move_u32(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1153 else
1154 __ daddu(as_Register(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]), R0);
1156 #ifndef PRODUCT
1157 } else {
1158 if(!do_size){
1159 if (size != 0) st->print("\n\t");
1160 st->print("move(32-bit) %s <-- %s\t# spill 11",
1161 Matcher::regName[dst_first],
1162 Matcher::regName[src_first]);
1163 }
1164 #endif
1165 }
1166 size += 4;
1167 return size;
1168 }
1169 } else if (dst_first_rc == rc_float) {
1170 // gpr -> xmm
1171 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1172 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1173 // 64-bit
1174 if (cbuf) {
1175 MacroAssembler _masm(cbuf);
1176 __ dmtc1(as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]));
1177 #ifndef PRODUCT
1178 } else {
1179 if(!do_size){
1180 if (size != 0) st->print("\n\t");
1181 st->print("dmtc1 %s, %s\t# spill 12",
1182 Matcher::regName[dst_first],
1183 Matcher::regName[src_first]);
1184 }
1185 #endif
1186 }
1187 size += 4;
1188 } else {
1189 // 32-bit
1190 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1191 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1192 if (cbuf) {
1193 MacroAssembler _masm(cbuf);
1194 __ mtc1( as_Register(Matcher::_regEncode[src_first]), as_FloatRegister(Matcher::_regEncode[dst_first]) );
1195 #ifndef PRODUCT
1196 } else {
1197 if(!do_size){
1198 if (size != 0) st->print("\n\t");
1199 st->print("mtc1 %s, %s\t# spill 13",
1200 Matcher::regName[dst_first],
1201 Matcher::regName[src_first]);
1202 }
1203 #endif
1204 }
1205 size += 4;
1206 }
1207 return size;
1208 }
1209 } else if (src_first_rc == rc_float) {
1210 // xmm ->
1211 if (dst_first_rc == rc_stack) {
1212 // xmm -> mem
1213 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1214 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1215 // 64-bit
1216 int offset = ra_->reg2offset(dst_first);
1217 if (cbuf) {
1218 MacroAssembler _masm(cbuf);
1219 __ sdc1( as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset) );
1220 #ifndef PRODUCT
1221 } else {
1222 if(!do_size){
1223 if (size != 0) st->print("\n\t");
1224 st->print("sdc1 %s, [SP + #%d]\t# spill 14",
1225 Matcher::regName[src_first],
1226 offset);
1227 }
1228 #endif
1229 }
1230 size += 4;
1231 } else {
1232 // 32-bit
1233 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1234 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1235 int offset = ra_->reg2offset(dst_first);
1236 if (cbuf) {
1237 MacroAssembler _masm(cbuf);
1238 __ swc1(as_FloatRegister(Matcher::_regEncode[src_first]), Address(SP, offset));
1239 #ifndef PRODUCT
1240 } else {
1241 if(!do_size){
1242 if (size != 0) st->print("\n\t");
1243 st->print("swc1 %s, [SP + #%d]\t# spill 15",
1244 Matcher::regName[src_first],
1245 offset);
1246 }
1247 #endif
1248 }
1249 size += 4;
1250 }
1251 return size;
1252 } else if (dst_first_rc == rc_int) {
1253 // xmm -> gpr
1254 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1255 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1256 // 64-bit
1257 if (cbuf) {
1258 MacroAssembler _masm(cbuf);
1259 __ dmfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1260 #ifndef PRODUCT
1261 } else {
1262 if(!do_size){
1263 if (size != 0) st->print("\n\t");
1264 st->print("dmfc1 %s, %s\t# spill 16",
1265 Matcher::regName[dst_first],
1266 Matcher::regName[src_first]);
1267 }
1268 #endif
1269 }
1270 size += 4;
1271 } else {
1272 // 32-bit
1273 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1274 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1275 if (cbuf) {
1276 MacroAssembler _masm(cbuf);
1277 __ mfc1( as_Register(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1278 #ifndef PRODUCT
1279 } else {
1280 if(!do_size){
1281 if (size != 0) st->print("\n\t");
1282 st->print("mfc1 %s, %s\t# spill 17",
1283 Matcher::regName[dst_first],
1284 Matcher::regName[src_first]);
1285 }
1286 #endif
1287 }
1288 size += 4;
1289 }
1290 return size;
1291 } else if (dst_first_rc == rc_float) {
1292 // xmm -> xmm
1293 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1294 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1295 // 64-bit
1296 if (cbuf) {
1297 MacroAssembler _masm(cbuf);
1298 __ mov_d( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1299 #ifndef PRODUCT
1300 } else {
1301 if(!do_size){
1302 if (size != 0) st->print("\n\t");
1303 st->print("mov_d %s <-- %s\t# spill 18",
1304 Matcher::regName[dst_first],
1305 Matcher::regName[src_first]);
1306 }
1307 #endif
1308 }
1309 size += 4;
1310 } else {
1311 // 32-bit
1312 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1313 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1314 if (cbuf) {
1315 MacroAssembler _masm(cbuf);
1316 __ mov_s( as_FloatRegister(Matcher::_regEncode[dst_first]), as_FloatRegister(Matcher::_regEncode[src_first]));
1317 #ifndef PRODUCT
1318 } else {
1319 if(!do_size){
1320 if (size != 0) st->print("\n\t");
1321 st->print("mov_s %s <-- %s\t# spill 19",
1322 Matcher::regName[dst_first],
1323 Matcher::regName[src_first]);
1324 }
1325 #endif
1326 }
1327 size += 4;
1328 }
1329 return size;
1330 }
1331 }
1333 assert(0," foo ");
1334 Unimplemented();
1335 return size;
1337 }
1339 #ifndef PRODUCT
1340 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1341 implementation( NULL, ra_, false, st );
1342 }
1343 #endif
1345 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1346 implementation( &cbuf, ra_, false, NULL );
1347 }
1349 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1350 return implementation( NULL, ra_, true, NULL );
1351 }
1353 //=============================================================================
1354 #
1356 #ifndef PRODUCT
1357 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
1358 st->print("INT3");
1359 }
1360 #endif
1362 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc* ra_) const {
1363 MacroAssembler _masm(&cbuf);
1364 __ int3();
1365 }
1367 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
1368 return MachNode::size(ra_);
1369 }
1372 //=============================================================================
1373 #ifndef PRODUCT
1374 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1375 Compile *C = ra_->C;
1376 int framesize = C->frame_size_in_bytes();
1378 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1380 st->print("daddiu SP, SP, %d # Rlease stack @ MachEpilogNode",framesize);
1381 st->cr(); st->print("\t");
1382 if (UseLoongsonISA) {
1383 st->print("gslq RA, FP, SP, %d # Restore FP & RA @ MachEpilogNode", -wordSize*2);
1384 } else {
1385 st->print("ld RA, SP, %d # Restore RA @ MachEpilogNode", -wordSize);
1386 st->cr(); st->print("\t");
1387 st->print("ld FP, SP, %d # Restore FP @ MachEpilogNode", -wordSize*2);
1388 }
1390 if( do_polling() && C->is_method_compilation() ) {
1391 st->print("Poll Safepoint # MachEpilogNode");
1392 }
1393 }
1394 #endif
1396 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1397 Compile *C = ra_->C;
1398 MacroAssembler _masm(&cbuf);
1399 int framesize = C->frame_size_in_bytes();
1401 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1403 __ daddiu(SP, SP, framesize);
1405 if (UseLoongsonISA) {
1406 __ gslq(RA, FP, SP, -wordSize*2);
1407 } else {
1408 __ ld(RA, SP, -wordSize );
1409 __ ld(FP, SP, -wordSize*2 );
1410 }
1412 if( do_polling() && C->is_method_compilation() ) {
1413 __ set64(AT, (long)os::get_polling_page());
1414 __ relocate(relocInfo::poll_return_type);
1415 __ lw(AT, AT, 0);
1416 }
1417 }
1419 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1420 return MachNode::size(ra_); // too many variables; just compute it the hard way fujie debug
1421 }
1423 int MachEpilogNode::reloc() const {
1424 return 0; // a large enough number
1425 }
1427 const Pipeline * MachEpilogNode::pipeline() const {
1428 return MachNode::pipeline_class();
1429 }
1431 int MachEpilogNode::safepoint_offset() const { return 0; }
1433 //=============================================================================
1435 #ifndef PRODUCT
1436 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1437 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1438 int reg = ra_->get_reg_first(this);
1439 st->print("ADDI %s, SP, %d @BoxLockNode",Matcher::regName[reg],offset);
1440 }
1441 #endif
1444 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1445 return 4;
1446 }
1448 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1449 MacroAssembler _masm(&cbuf);
1450 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1451 int reg = ra_->get_encode(this);
1453 __ addi(as_Register(reg), SP, offset);
1454 /*
1455 if( offset >= 128 ) {
1456 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1457 emit_rm(cbuf, 0x2, reg, 0x04);
1458 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1459 emit_d32(cbuf, offset);
1460 }
1461 else {
1462 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1463 emit_rm(cbuf, 0x1, reg, 0x04);
1464 emit_rm(cbuf, 0x0, 0x04, SP_enc);
1465 emit_d8(cbuf, offset);
1466 }
1467 */
1468 }
1471 //static int sizeof_FFree_Float_Stack_All = -1;
1473 int MachCallRuntimeNode::ret_addr_offset() {
1474 //lui
1475 //ori
1476 //dsll
1477 //ori
1478 //jalr
1479 //nop
1480 assert(NativeCall::instruction_size == 24, "in MachCallRuntimeNode::ret_addr_offset()");
1481 return NativeCall::instruction_size;
1482 // return 16;
1483 }
1489 //=============================================================================
1490 #ifndef PRODUCT
1491 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1492 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1493 }
1494 #endif
1496 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1497 MacroAssembler _masm(&cbuf);
1498 int i = 0;
1499 for(i = 0; i < _count; i++)
1500 __ nop();
1501 }
1503 uint MachNopNode::size(PhaseRegAlloc *) const {
1504 return 4 * _count;
1505 }
1506 const Pipeline* MachNopNode::pipeline() const {
1507 return MachNode::pipeline_class();
1508 }
1510 //=============================================================================
1512 //=============================================================================
1513 #ifndef PRODUCT
1514 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1515 st->print_cr("load_klass(T9, T0)");
1516 st->print_cr("\tbeq(T9, iCache, L)");
1517 st->print_cr("\tnop");
1518 st->print_cr("\tjmp(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type)");
1519 st->print_cr("\tnop");
1520 st->print_cr("\tnop");
1521 st->print_cr(" L:");
1522 }
1523 #endif
1526 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1527 MacroAssembler _masm(&cbuf);
1528 #ifdef ASSERT
1529 //uint code_size = cbuf.code_size();
1530 #endif
1531 int ic_reg = Matcher::inline_cache_reg_encode();
1532 Label L;
1533 Register receiver = T0;
1534 Register iCache = as_Register(ic_reg);
1535 __ load_klass(T9, receiver);
1536 __ beq(T9, iCache, L);
1537 __ nop();
1539 __ relocate(relocInfo::runtime_call_type);
1540 __ patchable_jump((address)SharedRuntime::get_ic_miss_stub());
1542 /* WARNING these NOPs are critical so that verified entry point is properly
1543 * 8 bytes aligned for patching by NativeJump::patch_verified_entry() */
1544 __ align(CodeEntryAlignment);
1545 __ bind(L);
1546 }
1548 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1549 return MachNode::size(ra_);
1550 }
1554 //=============================================================================
1556 const RegMask& MachConstantBaseNode::_out_RegMask = P_REG_mask();
1558 int Compile::ConstantTable::calculate_table_base_offset() const {
1559 return 0; // absolute addressing, no offset
1560 }
1562 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1563 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1564 ShouldNotReachHere();
1565 }
1567 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1568 Compile* C = ra_->C;
1569 Compile::ConstantTable& constant_table = C->constant_table();
1570 MacroAssembler _masm(&cbuf);
1572 Register Rtoc = as_Register(ra_->get_encode(this));
1573 CodeSection* consts_section = __ code()->consts();
1574 int consts_size = consts_section->align_at_start(consts_section->size());
1575 assert(constant_table.size() == consts_size, "must be equal");
1577 if (consts_section->size()) {
1578 // Materialize the constant table base.
1579 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1580 // RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1581 __ relocate(relocInfo::internal_pc_type);
1582 __ patchable_set48(Rtoc, (long)baseaddr);
1583 }
1584 }
1586 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1587 // patchable_set48 (4 insts)
1588 return 4 * 4;
1589 }
1591 #ifndef PRODUCT
1592 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1593 Register r = as_Register(ra_->get_encode(this));
1594 st->print("patchable_set48 %s, &constanttable (constant table base) @ MachConstantBaseNode", r->name());
1595 }
1596 #endif
1599 //=============================================================================
1600 #ifndef PRODUCT
1601 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1602 Compile* C = ra_->C;
1604 int framesize = C->frame_size_in_bytes();
1605 int bangsize = C->bang_size_in_bytes();
1606 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1608 // Calls to C2R adapters often do not accept exceptional returns.
1609 // We require that their callers must bang for them. But be careful, because
1610 // some VM calls (such as call site linkage) can use several kilobytes of
1611 // stack. But the stack safety zone should account for that.
1612 // See bugs 4446381, 4468289, 4497237.
1613 if (C->need_stack_bang(bangsize)) {
1614 st->print_cr("# stack bang"); st->print("\t");
1615 }
1616 if (UseLoongsonISA) {
1617 st->print("gssq RA, FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1618 } else {
1619 st->print("sd RA, %d(SP) @ MachPrologNode\n\t", -wordSize);
1620 st->print("sd FP, %d(SP) @ MachPrologNode\n\t", -wordSize*2);
1621 }
1622 st->print("daddiu FP, SP, -%d \n\t", wordSize*2);
1623 st->print("daddiu SP, SP, -%d \t",framesize);
1624 }
1625 #endif
1628 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1629 Compile* C = ra_->C;
1630 MacroAssembler _masm(&cbuf);
1632 int framesize = C->frame_size_in_bytes();
1633 int bangsize = C->bang_size_in_bytes();
1635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1637 if (C->need_stack_bang(bangsize)) {
1638 __ generate_stack_overflow_check(bangsize);
1639 }
1641 if (UseLoongsonISA) {
1642 __ gssq(RA, FP, SP, -wordSize*2);
1643 } else {
1644 __ sd(RA, SP, -wordSize);
1645 __ sd(FP, SP, -wordSize*2);
1646 }
1647 __ daddiu(FP, SP, -wordSize*2);
1648 __ daddiu(SP, SP, -framesize);
1649 __ nop(); /* 2013.10.22 Jin: Make enough room for patch_verified_entry() */
1650 __ nop();
1652 C->set_frame_complete(cbuf.insts_size());
1653 if (C->has_mach_constant_base_node()) {
1654 // NOTE: We set the table base offset here because users might be
1655 // emitted before MachConstantBaseNode.
1656 Compile::ConstantTable& constant_table = C->constant_table();
1657 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1658 }
1660 }
1663 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1664 return MachNode::size(ra_); // too many variables; just compute it the hard way
1665 }
1667 int MachPrologNode::reloc() const {
1668 return 0; // a large enough number
1669 }
1671 %}
1673 //----------ENCODING BLOCK-----------------------------------------------------
1674 // This block specifies the encoding classes used by the compiler to output
1675 // byte streams. Encoding classes generate functions which are called by
1676 // Machine Instruction Nodes in order to generate the bit encoding of the
1677 // instruction. Operands specify their base encoding interface with the
1678 // interface keyword. There are currently supported four interfaces,
1679 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1680 // operand to generate a function which returns its register number when
1681 // queried. CONST_INTER causes an operand to generate a function which
1682 // returns the value of the constant when queried. MEMORY_INTER causes an
1683 // operand to generate four functions which return the Base Register, the
1684 // Index Register, the Scale Value, and the Offset Value of the operand when
1685 // queried. COND_INTER causes an operand to generate six functions which
1686 // return the encoding code (ie - encoding bits for the instruction)
1687 // associated with each basic boolean condition for a conditional instruction.
1688 // Instructions specify two basic values for encoding. They use the
1689 // ins_encode keyword to specify their encoding class (which must be one of
1690 // the class names specified in the encoding block), and they use the
1691 // opcode keyword to specify, in order, their primary, secondary, and
1692 // tertiary opcode. Only the opcode sections which a particular instruction
1693 // needs for encoding need to be specified.
1694 encode %{
1696 //Load byte signed
1697 enc_class load_B_enc (mRegI dst, memory mem) %{
1698 MacroAssembler _masm(&cbuf);
1699 int dst = $dst$$reg;
1700 int base = $mem$$base;
1701 int index = $mem$$index;
1702 int scale = $mem$$scale;
1703 int disp = $mem$$disp;
1705 if( index != 0 ) {
1706 if( Assembler::is_simm16(disp) ) {
1707 if( UseLoongsonISA ) {
1708 if (scale == 0) {
1709 __ gslbx(as_Register(dst), as_Register(base), as_Register(index), disp);
1710 } else {
1711 __ dsll(AT, as_Register(index), scale);
1712 __ gslbx(as_Register(dst), as_Register(base), AT, disp);
1713 }
1714 } else {
1715 if (scale == 0) {
1716 __ addu(AT, as_Register(base), as_Register(index));
1717 } else {
1718 __ dsll(AT, as_Register(index), scale);
1719 __ addu(AT, as_Register(base), AT);
1720 }
1721 __ lb(as_Register(dst), AT, disp);
1722 }
1723 } else {
1724 if (scale == 0) {
1725 __ addu(AT, as_Register(base), as_Register(index));
1726 } else {
1727 __ dsll(AT, as_Register(index), scale);
1728 __ addu(AT, as_Register(base), AT);
1729 }
1730 __ move(T9, disp);
1731 if( UseLoongsonISA ) {
1732 __ gslbx(as_Register(dst), AT, T9, 0);
1733 } else {
1734 __ addu(AT, AT, T9);
1735 __ lb(as_Register(dst), AT, 0);
1736 }
1737 }
1738 } else {
1739 if( Assembler::is_simm16(disp) ) {
1740 __ lb(as_Register(dst), as_Register(base), disp);
1741 } else {
1742 __ move(T9, disp);
1743 if( UseLoongsonISA ) {
1744 __ gslbx(as_Register(dst), as_Register(base), T9, 0);
1745 } else {
1746 __ addu(AT, as_Register(base), T9);
1747 __ lb(as_Register(dst), AT, 0);
1748 }
1749 }
1750 }
1751 %}
1753 //Load byte unsigned
1754 enc_class load_UB_enc (mRegI dst, memory mem) %{
1755 MacroAssembler _masm(&cbuf);
1756 int dst = $dst$$reg;
1757 int base = $mem$$base;
1758 int index = $mem$$index;
1759 int scale = $mem$$scale;
1760 int disp = $mem$$disp;
1762 if( index != 0 ) {
1763 if (scale == 0) {
1764 __ daddu(AT, as_Register(base), as_Register(index));
1765 } else {
1766 __ dsll(AT, as_Register(index), scale);
1767 __ daddu(AT, as_Register(base), AT);
1768 }
1769 if( Assembler::is_simm16(disp) ) {
1770 __ lbu(as_Register(dst), AT, disp);
1771 } else {
1772 __ move(T9, disp);
1773 __ daddu(AT, AT, T9);
1774 __ lbu(as_Register(dst), AT, 0);
1775 }
1776 } else {
1777 if( Assembler::is_simm16(disp) ) {
1778 __ lbu(as_Register(dst), as_Register(base), disp);
1779 } else {
1780 __ move(T9, disp);
1781 __ daddu(AT, as_Register(base), T9);
1782 __ lbu(as_Register(dst), AT, 0);
1783 }
1784 }
1785 %}
1787 enc_class store_B_reg_enc (memory mem, mRegI src) %{
1788 MacroAssembler _masm(&cbuf);
1789 int src = $src$$reg;
1790 int base = $mem$$base;
1791 int index = $mem$$index;
1792 int scale = $mem$$scale;
1793 int disp = $mem$$disp;
1795 if( index != 0 ) {
1796 if (scale == 0) {
1797 if( Assembler::is_simm(disp, 8) ) {
1798 if (UseLoongsonISA) {
1799 __ gssbx(as_Register(src), as_Register(base), as_Register(index), disp);
1800 } else {
1801 __ addu(AT, as_Register(base), as_Register(index));
1802 __ sb(as_Register(src), AT, disp);
1803 }
1804 } else if( Assembler::is_simm16(disp) ) {
1805 __ addu(AT, as_Register(base), as_Register(index));
1806 __ sb(as_Register(src), AT, disp);
1807 } else {
1808 __ addu(AT, as_Register(base), as_Register(index));
1809 __ move(T9, disp);
1810 if (UseLoongsonISA) {
1811 __ gssbx(as_Register(src), AT, T9, 0);
1812 } else {
1813 __ addu(AT, AT, T9);
1814 __ sb(as_Register(src), AT, 0);
1815 }
1816 }
1817 } else {
1818 __ dsll(AT, as_Register(index), scale);
1819 if( Assembler::is_simm(disp, 8) ) {
1820 if (UseLoongsonISA) {
1821 __ gssbx(as_Register(src), AT, as_Register(base), disp);
1822 } else {
1823 __ addu(AT, as_Register(base), AT);
1824 __ sb(as_Register(src), AT, disp);
1825 }
1826 } else if( Assembler::is_simm16(disp) ) {
1827 __ addu(AT, as_Register(base), AT);
1828 __ sb(as_Register(src), AT, disp);
1829 } else {
1830 __ addu(AT, as_Register(base), AT);
1831 __ move(T9, disp);
1832 if (UseLoongsonISA) {
1833 __ gssbx(as_Register(src), AT, T9, 0);
1834 } else {
1835 __ addu(AT, AT, T9);
1836 __ sb(as_Register(src), AT, 0);
1837 }
1838 }
1839 }
1840 } else {
1841 if( Assembler::is_simm16(disp) ) {
1842 __ sb(as_Register(src), as_Register(base), disp);
1843 } else {
1844 __ move(T9, disp);
1845 if (UseLoongsonISA) {
1846 __ gssbx(as_Register(src), as_Register(base), T9, 0);
1847 } else {
1848 __ addu(AT, as_Register(base), T9);
1849 __ sb(as_Register(src), AT, 0);
1850 }
1851 }
1852 }
1853 %}
1855 enc_class store_B_immI_enc (memory mem, immI8 src) %{
1856 MacroAssembler _masm(&cbuf);
1857 int base = $mem$$base;
1858 int index = $mem$$index;
1859 int scale = $mem$$scale;
1860 int disp = $mem$$disp;
1861 int value = $src$$constant;
1863 if( index != 0 ) {
1864 if (!UseLoongsonISA) {
1865 if (scale == 0) {
1866 __ daddu(AT, as_Register(base), as_Register(index));
1867 } else {
1868 __ dsll(AT, as_Register(index), scale);
1869 __ daddu(AT, as_Register(base), AT);
1870 }
1871 if( Assembler::is_simm16(disp) ) {
1872 if (value == 0) {
1873 __ sb(R0, AT, disp);
1874 } else {
1875 __ move(T9, value);
1876 __ sb(T9, AT, disp);
1877 }
1878 } else {
1879 if (value == 0) {
1880 __ move(T9, disp);
1881 __ daddu(AT, AT, T9);
1882 __ sb(R0, AT, 0);
1883 } else {
1884 __ move(T9, disp);
1885 __ daddu(AT, AT, T9);
1886 __ move(T9, value);
1887 __ sb(T9, AT, 0);
1888 }
1889 }
1890 } else {
1892 if (scale == 0) {
1893 if( Assembler::is_simm(disp, 8) ) {
1894 if (value == 0) {
1895 __ gssbx(R0, as_Register(base), as_Register(index), disp);
1896 } else {
1897 __ move(T9, value);
1898 __ gssbx(T9, as_Register(base), as_Register(index), disp);
1899 }
1900 } else if( Assembler::is_simm16(disp) ) {
1901 __ daddu(AT, as_Register(base), as_Register(index));
1902 if (value == 0) {
1903 __ sb(R0, AT, disp);
1904 } else {
1905 __ move(T9, value);
1906 __ sb(T9, AT, disp);
1907 }
1908 } else {
1909 if (value == 0) {
1910 __ daddu(AT, as_Register(base), as_Register(index));
1911 __ move(T9, disp);
1912 __ gssbx(R0, AT, T9, 0);
1913 } else {
1914 __ move(AT, disp);
1915 __ move(T9, value);
1916 __ daddu(AT, as_Register(base), AT);
1917 __ gssbx(T9, AT, as_Register(index), 0);
1918 }
1919 }
1921 } else {
1923 if( Assembler::is_simm(disp, 8) ) {
1924 __ dsll(AT, as_Register(index), scale);
1925 if (value == 0) {
1926 __ gssbx(R0, as_Register(base), AT, disp);
1927 } else {
1928 __ move(T9, value);
1929 __ gssbx(T9, as_Register(base), AT, disp);
1930 }
1931 } else if( Assembler::is_simm16(disp) ) {
1932 __ dsll(AT, as_Register(index), scale);
1933 __ daddu(AT, as_Register(base), AT);
1934 if (value == 0) {
1935 __ sb(R0, AT, disp);
1936 } else {
1937 __ move(T9, value);
1938 __ sb(T9, AT, disp);
1939 }
1940 } else {
1941 __ dsll(AT, as_Register(index), scale);
1942 if (value == 0) {
1943 __ daddu(AT, as_Register(base), AT);
1944 __ move(T9, disp);
1945 __ gssbx(R0, AT, T9, 0);
1946 } else {
1947 __ move(T9, disp);
1948 __ daddu(AT, AT, T9);
1949 __ move(T9, value);
1950 __ gssbx(T9, as_Register(base), AT, 0);
1951 }
1952 }
1953 }
1954 }
1955 } else {
1956 if( Assembler::is_simm16(disp) ) {
1957 if (value == 0) {
1958 __ sb(R0, as_Register(base), disp);
1959 } else {
1960 __ move(AT, value);
1961 __ sb(AT, as_Register(base), disp);
1962 }
1963 } else {
1964 if (value == 0) {
1965 __ move(T9, disp);
1966 if (UseLoongsonISA) {
1967 __ gssbx(R0, as_Register(base), T9, 0);
1968 } else {
1969 __ daddu(AT, as_Register(base), T9);
1970 __ sb(R0, AT, 0);
1971 }
1972 } else {
1973 __ move(T9, disp);
1974 if (UseLoongsonISA) {
1975 __ move(AT, value);
1976 __ gssbx(AT, as_Register(base), T9, 0);
1977 } else {
1978 __ daddu(AT, as_Register(base), T9);
1979 __ move(T9, value);
1980 __ sb(T9, AT, 0);
1981 }
1982 }
1983 }
1984 }
1985 %}
1988 enc_class store_B_immI_enc_sync (memory mem, immI8 src) %{
1989 MacroAssembler _masm(&cbuf);
1990 int base = $mem$$base;
1991 int index = $mem$$index;
1992 int scale = $mem$$scale;
1993 int disp = $mem$$disp;
1994 int value = $src$$constant;
1996 if( index != 0 ) {
1997 if ( UseLoongsonISA ) {
1998 if ( Assembler::is_simm(disp,8) ) {
1999 if ( scale == 0 ) {
2000 if ( value == 0 ) {
2001 __ gssbx(R0, as_Register(base), as_Register(index), disp);
2002 } else {
2003 __ move(AT, value);
2004 __ gssbx(AT, as_Register(base), as_Register(index), disp);
2005 }
2006 } else {
2007 __ dsll(AT, as_Register(index), scale);
2008 if ( value == 0 ) {
2009 __ gssbx(R0, as_Register(base), AT, disp);
2010 } else {
2011 __ move(T9, value);
2012 __ gssbx(T9, as_Register(base), AT, disp);
2013 }
2014 }
2015 } else if ( Assembler::is_simm16(disp) ) {
2016 if ( scale == 0 ) {
2017 __ daddu(AT, as_Register(base), as_Register(index));
2018 if ( value == 0 ){
2019 __ sb(R0, AT, disp);
2020 } else {
2021 __ move(T9, value);
2022 __ sb(T9, AT, disp);
2023 }
2024 } else {
2025 __ dsll(AT, as_Register(index), scale);
2026 __ daddu(AT, as_Register(base), AT);
2027 if ( value == 0 ) {
2028 __ sb(R0, AT, disp);
2029 } else {
2030 __ move(T9, value);
2031 __ sb(T9, AT, disp);
2032 }
2033 }
2034 } else {
2035 if ( scale == 0 ) {
2036 __ move(AT, disp);
2037 __ daddu(AT, as_Register(index), AT);
2038 if ( value == 0 ) {
2039 __ gssbx(R0, as_Register(base), AT, 0);
2040 } else {
2041 __ move(T9, value);
2042 __ gssbx(T9, as_Register(base), AT, 0);
2043 }
2044 } else {
2045 __ dsll(AT, as_Register(index), scale);
2046 __ move(T9, disp);
2047 __ daddu(AT, AT, T9);
2048 if ( value == 0 ) {
2049 __ gssbx(R0, as_Register(base), AT, 0);
2050 } else {
2051 __ move(T9, value);
2052 __ gssbx(T9, as_Register(base), AT, 0);
2053 }
2054 }
2055 }
2056 } else { //not use loongson isa
2057 if (scale == 0) {
2058 __ daddu(AT, as_Register(base), as_Register(index));
2059 } else {
2060 __ dsll(AT, as_Register(index), scale);
2061 __ daddu(AT, as_Register(base), AT);
2062 }
2063 if( Assembler::is_simm16(disp) ) {
2064 if (value == 0) {
2065 __ sb(R0, AT, disp);
2066 } else {
2067 __ move(T9, value);
2068 __ sb(T9, AT, disp);
2069 }
2070 } else {
2071 if (value == 0) {
2072 __ move(T9, disp);
2073 __ daddu(AT, AT, T9);
2074 __ sb(R0, AT, 0);
2075 } else {
2076 __ move(T9, disp);
2077 __ daddu(AT, AT, T9);
2078 __ move(T9, value);
2079 __ sb(T9, AT, 0);
2080 }
2081 }
2082 }
2083 } else {
2084 if ( UseLoongsonISA ){
2085 if ( Assembler::is_simm16(disp) ){
2086 if ( value == 0 ) {
2087 __ sb(R0, as_Register(base), disp);
2088 } else {
2089 __ move(AT, value);
2090 __ sb(AT, as_Register(base), disp);
2091 }
2092 } else {
2093 __ move(AT, disp);
2094 if ( value == 0 ) {
2095 __ gssbx(R0, as_Register(base), AT, 0);
2096 } else {
2097 __ move(T9, value);
2098 __ gssbx(T9, as_Register(base), AT, 0);
2099 }
2100 }
2101 } else {
2102 if( Assembler::is_simm16(disp) ) {
2103 if (value == 0) {
2104 __ sb(R0, as_Register(base), disp);
2105 } else {
2106 __ move(AT, value);
2107 __ sb(AT, as_Register(base), disp);
2108 }
2109 } else {
2110 if (value == 0) {
2111 __ move(T9, disp);
2112 __ daddu(AT, as_Register(base), T9);
2113 __ sb(R0, AT, 0);
2114 } else {
2115 __ move(T9, disp);
2116 __ daddu(AT, as_Register(base), T9);
2117 __ move(T9, value);
2118 __ sb(T9, AT, 0);
2119 }
2120 }
2121 }
2122 }
2124 __ sync();
2125 %}
2127 // Load Short (16bit signed)
2128 enc_class load_S_enc (mRegI dst, memory mem) %{
2129 MacroAssembler _masm(&cbuf);
2130 int dst = $dst$$reg;
2131 int base = $mem$$base;
2132 int index = $mem$$index;
2133 int scale = $mem$$scale;
2134 int disp = $mem$$disp;
2136 if( index != 0 ) {
2137 if ( UseLoongsonISA ) {
2138 if ( Assembler::is_simm(disp, 8) ) {
2139 if (scale == 0) {
2140 __ gslhx(as_Register(dst), as_Register(base), as_Register(index), disp);
2141 } else {
2142 __ dsll(AT, as_Register(index), scale);
2143 __ gslhx(as_Register(dst), as_Register(base), AT, disp);
2144 }
2145 } else if ( Assembler::is_simm16(disp) ) {
2146 if (scale == 0) {
2147 __ daddu(AT, as_Register(base), as_Register(index));
2148 __ lh(as_Register(dst), AT, disp);
2149 } else {
2150 __ dsll(AT, as_Register(index), scale);
2151 __ daddu(AT, as_Register(base), AT);
2152 __ lh(as_Register(dst), AT, disp);
2153 }
2154 } else {
2155 if (scale == 0) {
2156 __ move(AT, disp);
2157 __ daddu(AT, as_Register(index), AT);
2158 __ gslhx(as_Register(dst), as_Register(base), AT, 0);
2159 } else {
2160 __ dsll(AT, as_Register(index), scale);
2161 __ move(T9, disp);
2162 __ daddu(AT, AT, T9);
2163 __ gslhx(as_Register(dst), as_Register(base), AT, 0);
2164 }
2165 }
2166 } else { // not use loongson isa
2167 if (scale == 0) {
2168 __ daddu(AT, as_Register(base), as_Register(index));
2169 } else {
2170 __ dsll(AT, as_Register(index), scale);
2171 __ daddu(AT, as_Register(base), AT);
2172 }
2173 if( Assembler::is_simm16(disp) ) {
2174 __ lh(as_Register(dst), AT, disp);
2175 } else {
2176 __ move(T9, disp);
2177 __ daddu(AT, AT, T9);
2178 __ lh(as_Register(dst), AT, 0);
2179 }
2180 }
2181 } else { // index is 0
2182 if ( UseLoongsonISA ) {
2183 if ( Assembler::is_simm16(disp) ) {
2184 __ lh(as_Register(dst), as_Register(base), disp);
2185 } else {
2186 __ move(T9, disp);
2187 __ gslhx(as_Register(dst), as_Register(base), T9, 0);
2188 }
2189 } else { //not use loongson isa
2190 if( Assembler::is_simm16(disp) ) {
2191 __ lh(as_Register(dst), as_Register(base), disp);
2192 } else {
2193 __ move(T9, disp);
2194 __ daddu(AT, as_Register(base), T9);
2195 __ lh(as_Register(dst), AT, 0);
2196 }
2197 }
2198 }
2199 %}
2201 // Load Char (16bit unsigned)
2202 enc_class load_C_enc (mRegI dst, memory mem) %{
2203 MacroAssembler _masm(&cbuf);
2204 int dst = $dst$$reg;
2205 int base = $mem$$base;
2206 int index = $mem$$index;
2207 int scale = $mem$$scale;
2208 int disp = $mem$$disp;
2210 if( index != 0 ) {
2211 if (scale == 0) {
2212 __ daddu(AT, as_Register(base), as_Register(index));
2213 } else {
2214 __ dsll(AT, as_Register(index), scale);
2215 __ daddu(AT, as_Register(base), AT);
2216 }
2217 if( Assembler::is_simm16(disp) ) {
2218 __ lhu(as_Register(dst), AT, disp);
2219 } else {
2220 __ move(T9, disp);
2221 __ addu(AT, AT, T9);
2222 __ lhu(as_Register(dst), AT, 0);
2223 }
2224 } else {
2225 if( Assembler::is_simm16(disp) ) {
2226 __ lhu(as_Register(dst), as_Register(base), disp);
2227 } else {
2228 __ move(T9, disp);
2229 __ daddu(AT, as_Register(base), T9);
2230 __ lhu(as_Register(dst), AT, 0);
2231 }
2232 }
2233 %}
2235 // Store Char (16bit unsigned)
2236 enc_class store_C_reg_enc (memory mem, mRegI src) %{
2237 MacroAssembler _masm(&cbuf);
2238 int src = $src$$reg;
2239 int base = $mem$$base;
2240 int index = $mem$$index;
2241 int scale = $mem$$scale;
2242 int disp = $mem$$disp;
2244 if( index != 0 ) {
2245 if( Assembler::is_simm16(disp) ) {
2246 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2247 if (scale == 0) {
2248 __ gsshx(as_Register(src), as_Register(base), as_Register(index), disp);
2249 } else {
2250 __ dsll(AT, as_Register(index), scale);
2251 __ gsshx(as_Register(src), as_Register(base), AT, disp);
2252 }
2253 } else {
2254 if (scale == 0) {
2255 __ addu(AT, as_Register(base), as_Register(index));
2256 } else {
2257 __ dsll(AT, as_Register(index), scale);
2258 __ addu(AT, as_Register(base), AT);
2259 }
2260 __ sh(as_Register(src), AT, disp);
2261 }
2262 } else {
2263 if (scale == 0) {
2264 __ addu(AT, as_Register(base), as_Register(index));
2265 } else {
2266 __ dsll(AT, as_Register(index), scale);
2267 __ addu(AT, as_Register(base), AT);
2268 }
2269 __ move(T9, disp);
2270 if( UseLoongsonISA ) {
2271 __ gsshx(as_Register(src), AT, T9, 0);
2272 } else {
2273 __ addu(AT, AT, T9);
2274 __ sh(as_Register(src), AT, 0);
2275 }
2276 }
2277 } else {
2278 if( Assembler::is_simm16(disp) ) {
2279 __ sh(as_Register(src), as_Register(base), disp);
2280 } else {
2281 __ move(T9, disp);
2282 if( UseLoongsonISA ) {
2283 __ gsshx(as_Register(src), as_Register(base), T9, 0);
2284 } else {
2285 __ addu(AT, as_Register(base), T9);
2286 __ sh(as_Register(src), AT, 0);
2287 }
2288 }
2289 }
2290 %}
2292 enc_class store_C0_enc (memory mem) %{
2293 MacroAssembler _masm(&cbuf);
2294 int base = $mem$$base;
2295 int index = $mem$$index;
2296 int scale = $mem$$scale;
2297 int disp = $mem$$disp;
2299 if( index != 0 ) {
2300 if( Assembler::is_simm16(disp) ) {
2301 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2302 if (scale == 0) {
2303 __ gsshx(R0, as_Register(base), as_Register(index), disp);
2304 } else {
2305 __ dsll(AT, as_Register(index), scale);
2306 __ gsshx(R0, as_Register(base), AT, disp);
2307 }
2308 } else {
2309 if (scale == 0) {
2310 __ addu(AT, as_Register(base), as_Register(index));
2311 } else {
2312 __ dsll(AT, as_Register(index), scale);
2313 __ addu(AT, as_Register(base), AT);
2314 }
2315 __ sh(R0, AT, disp);
2316 }
2317 } else {
2318 if (scale == 0) {
2319 __ addu(AT, as_Register(base), as_Register(index));
2320 } else {
2321 __ dsll(AT, as_Register(index), scale);
2322 __ addu(AT, as_Register(base), AT);
2323 }
2324 __ move(T9, disp);
2325 if( UseLoongsonISA ) {
2326 __ gsshx(R0, AT, T9, 0);
2327 } else {
2328 __ addu(AT, AT, T9);
2329 __ sh(R0, AT, 0);
2330 }
2331 }
2332 } else {
2333 if( Assembler::is_simm16(disp) ) {
2334 __ sh(R0, as_Register(base), disp);
2335 } else {
2336 __ move(T9, disp);
2337 if( UseLoongsonISA ) {
2338 __ gsshx(R0, as_Register(base), T9, 0);
2339 } else {
2340 __ addu(AT, as_Register(base), T9);
2341 __ sh(R0, AT, 0);
2342 }
2343 }
2344 }
2345 %}
2347 enc_class load_I_enc (mRegI dst, memory mem) %{
2348 MacroAssembler _masm(&cbuf);
2349 int dst = $dst$$reg;
2350 int base = $mem$$base;
2351 int index = $mem$$index;
2352 int scale = $mem$$scale;
2353 int disp = $mem$$disp;
2355 if( index != 0 ) {
2356 if( Assembler::is_simm16(disp) ) {
2357 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2358 if (scale == 0) {
2359 __ gslwx(as_Register(dst), as_Register(base), as_Register(index), disp);
2360 } else {
2361 __ dsll(AT, as_Register(index), scale);
2362 __ gslwx(as_Register(dst), as_Register(base), AT, disp);
2363 }
2364 } else {
2365 if (scale == 0) {
2366 __ addu(AT, as_Register(base), as_Register(index));
2367 } else {
2368 __ dsll(AT, as_Register(index), scale);
2369 __ addu(AT, as_Register(base), AT);
2370 }
2371 __ lw(as_Register(dst), AT, disp);
2372 }
2373 } else {
2374 if (scale == 0) {
2375 __ addu(AT, as_Register(base), as_Register(index));
2376 } else {
2377 __ dsll(AT, as_Register(index), scale);
2378 __ addu(AT, as_Register(base), AT);
2379 }
2380 __ move(T9, disp);
2381 if( UseLoongsonISA ) {
2382 __ gslwx(as_Register(dst), AT, T9, 0);
2383 } else {
2384 __ addu(AT, AT, T9);
2385 __ lw(as_Register(dst), AT, 0);
2386 }
2387 }
2388 } else {
2389 if( Assembler::is_simm16(disp) ) {
2390 __ lw(as_Register(dst), as_Register(base), disp);
2391 } else {
2392 __ move(T9, disp);
2393 if( UseLoongsonISA ) {
2394 __ gslwx(as_Register(dst), as_Register(base), T9, 0);
2395 } else {
2396 __ addu(AT, as_Register(base), T9);
2397 __ lw(as_Register(dst), AT, 0);
2398 }
2399 }
2400 }
2401 %}
2403 enc_class store_I_reg_enc (memory mem, mRegI src) %{
2404 MacroAssembler _masm(&cbuf);
2405 int src = $src$$reg;
2406 int base = $mem$$base;
2407 int index = $mem$$index;
2408 int scale = $mem$$scale;
2409 int disp = $mem$$disp;
2411 if( index != 0 ) {
2412 if( Assembler::is_simm16(disp) ) {
2413 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
2414 if (scale == 0) {
2415 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
2416 } else {
2417 __ dsll(AT, as_Register(index), scale);
2418 __ gsswx(as_Register(src), as_Register(base), AT, disp);
2419 }
2420 } else {
2421 if (scale == 0) {
2422 __ addu(AT, as_Register(base), as_Register(index));
2423 } else {
2424 __ dsll(AT, as_Register(index), scale);
2425 __ addu(AT, as_Register(base), AT);
2426 }
2427 __ sw(as_Register(src), AT, disp);
2428 }
2429 } else {
2430 if (scale == 0) {
2431 __ addu(AT, as_Register(base), as_Register(index));
2432 } else {
2433 __ dsll(AT, as_Register(index), scale);
2434 __ addu(AT, as_Register(base), AT);
2435 }
2436 __ move(T9, disp);
2437 if( UseLoongsonISA ) {
2438 __ gsswx(as_Register(src), AT, T9, 0);
2439 } else {
2440 __ addu(AT, AT, T9);
2441 __ sw(as_Register(src), AT, 0);
2442 }
2443 }
2444 } else {
2445 if( Assembler::is_simm16(disp) ) {
2446 __ sw(as_Register(src), as_Register(base), disp);
2447 } else {
2448 __ move(T9, disp);
2449 if( UseLoongsonISA ) {
2450 __ gsswx(as_Register(src), as_Register(base), T9, 0);
2451 } else {
2452 __ addu(AT, as_Register(base), T9);
2453 __ sw(as_Register(src), AT, 0);
2454 }
2455 }
2456 }
2457 %}
2459 enc_class store_I_immI_enc (memory mem, immI src) %{
2460 MacroAssembler _masm(&cbuf);
2461 int base = $mem$$base;
2462 int index = $mem$$index;
2463 int scale = $mem$$scale;
2464 int disp = $mem$$disp;
2465 int value = $src$$constant;
2467 if( index != 0 ) {
2468 if ( UseLoongsonISA ) {
2469 if ( Assembler::is_simm(disp, 8) ) {
2470 if ( scale == 0 ) {
2471 if ( value == 0 ) {
2472 __ gsswx(R0, as_Register(base), as_Register(index), disp);
2473 } else {
2474 __ move(T9, value);
2475 __ gsswx(T9, as_Register(base), as_Register(index), disp);
2476 }
2477 } else {
2478 __ dsll(AT, as_Register(index), scale);
2479 if ( value == 0 ) {
2480 __ gsswx(R0, as_Register(base), AT, disp);
2481 } else {
2482 __ move(T9, value);
2483 __ gsswx(T9, as_Register(base), AT, disp);
2484 }
2485 }
2486 } else if ( Assembler::is_simm16(disp) ) {
2487 if ( scale == 0 ) {
2488 __ daddu(AT, as_Register(base), as_Register(index));
2489 if ( value == 0 ) {
2490 __ sw(R0, AT, disp);
2491 } else {
2492 __ move(T9, value);
2493 __ sw(T9, AT, disp);
2494 }
2495 } else {
2496 __ dsll(AT, as_Register(index), scale);
2497 __ daddu(AT, as_Register(base), AT);
2498 if ( value == 0 ) {
2499 __ sw(R0, AT, disp);
2500 } else {
2501 __ move(T9, value);
2502 __ sw(T9, AT, disp);
2503 }
2504 }
2505 } else {
2506 if ( scale == 0 ) {
2507 __ move(T9, disp);
2508 __ daddu(AT, as_Register(index), T9);
2509 if ( value ==0 ) {
2510 __ gsswx(R0, as_Register(base), AT, 0);
2511 } else {
2512 __ move(T9, value);
2513 __ gsswx(T9, as_Register(base), AT, 0);
2514 }
2515 } else {
2516 __ dsll(AT, as_Register(index), scale);
2517 __ move(T9, disp);
2518 __ daddu(AT, AT, T9);
2519 if ( value == 0 ) {
2520 __ gsswx(R0, as_Register(base), AT, 0);
2521 } else {
2522 __ move(T9, value);
2523 __ gsswx(T9, as_Register(base), AT, 0);
2524 }
2525 }
2526 }
2527 } else { //not use loongson isa
2528 if (scale == 0) {
2529 __ daddu(AT, as_Register(base), as_Register(index));
2530 } else {
2531 __ dsll(AT, as_Register(index), scale);
2532 __ daddu(AT, as_Register(base), AT);
2533 }
2534 if( Assembler::is_simm16(disp) ) {
2535 if (value == 0) {
2536 __ sw(R0, AT, disp);
2537 } else {
2538 __ move(T9, value);
2539 __ sw(T9, AT, disp);
2540 }
2541 } else {
2542 if (value == 0) {
2543 __ move(T9, disp);
2544 __ daddu(AT, AT, T9);
2545 __ sw(R0, AT, 0);
2546 } else {
2547 __ move(T9, disp);
2548 __ daddu(AT, AT, T9);
2549 __ move(T9, value);
2550 __ sw(T9, AT, 0);
2551 }
2552 }
2553 }
2554 } else {
2555 if ( UseLoongsonISA ) {
2556 if ( Assembler::is_simm16(disp) ) {
2557 if ( value == 0 ) {
2558 __ sw(R0, as_Register(base), disp);
2559 } else {
2560 __ move(AT, value);
2561 __ sw(AT, as_Register(base), disp);
2562 }
2563 } else {
2564 __ move(T9, disp);
2565 if ( value == 0 ) {
2566 __ gsswx(R0, as_Register(base), T9, 0);
2567 } else {
2568 __ move(AT, value);
2569 __ gsswx(AT, as_Register(base), T9, 0);
2570 }
2571 }
2572 } else {
2573 if( Assembler::is_simm16(disp) ) {
2574 if (value == 0) {
2575 __ sw(R0, as_Register(base), disp);
2576 } else {
2577 __ move(AT, value);
2578 __ sw(AT, as_Register(base), disp);
2579 }
2580 } else {
2581 if (value == 0) {
2582 __ move(T9, disp);
2583 __ daddu(AT, as_Register(base), T9);
2584 __ sw(R0, AT, 0);
2585 } else {
2586 __ move(T9, disp);
2587 __ daddu(AT, as_Register(base), T9);
2588 __ move(T9, value);
2589 __ sw(T9, AT, 0);
2590 }
2591 }
2592 }
2593 }
2594 %}
2596 enc_class load_N_enc (mRegN dst, memory mem) %{
2597 MacroAssembler _masm(&cbuf);
2598 int dst = $dst$$reg;
2599 int base = $mem$$base;
2600 int index = $mem$$index;
2601 int scale = $mem$$scale;
2602 int disp = $mem$$disp;
2603 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2604 assert(disp_reloc == relocInfo::none, "cannot have disp");
2606 if( index != 0 ) {
2607 if (scale == 0) {
2608 __ daddu(AT, as_Register(base), as_Register(index));
2609 } else {
2610 __ dsll(AT, as_Register(index), scale);
2611 __ daddu(AT, as_Register(base), AT);
2612 }
2613 if( Assembler::is_simm16(disp) ) {
2614 __ lwu(as_Register(dst), AT, disp);
2615 } else {
2616 __ set64(T9, disp);
2617 __ daddu(AT, AT, T9);
2618 __ lwu(as_Register(dst), AT, 0);
2619 }
2620 } else {
2621 if( Assembler::is_simm16(disp) ) {
2622 __ lwu(as_Register(dst), as_Register(base), disp);
2623 } else {
2624 __ set64(T9, disp);
2625 __ daddu(AT, as_Register(base), T9);
2626 __ lwu(as_Register(dst), AT, 0);
2627 }
2628 }
2630 %}
2633 enc_class load_P_enc (mRegP dst, memory mem) %{
2634 MacroAssembler _masm(&cbuf);
2635 int dst = $dst$$reg;
2636 int base = $mem$$base;
2637 int index = $mem$$index;
2638 int scale = $mem$$scale;
2639 int disp = $mem$$disp;
2640 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2641 assert(disp_reloc == relocInfo::none, "cannot have disp");
2643 if( index != 0 ) {
2644 if ( UseLoongsonISA ) {
2645 if ( Assembler::is_simm(disp, 8) ) {
2646 if ( scale != 0 ) {
2647 __ dsll(AT, as_Register(index), scale);
2648 __ gsldx(as_Register(dst), as_Register(base), AT, disp);
2649 } else {
2650 __ gsldx(as_Register(dst), as_Register(base), as_Register(index), disp);
2651 }
2652 } else if ( Assembler::is_simm16(disp) ){
2653 if ( scale != 0 ) {
2654 __ dsll(AT, as_Register(index), scale);
2655 __ daddu(AT, AT, as_Register(base));
2656 } else {
2657 __ daddu(AT, as_Register(index), as_Register(base));
2658 }
2659 __ ld(as_Register(dst), AT, disp);
2660 } else {
2661 if ( scale != 0 ) {
2662 __ dsll(AT, as_Register(index), scale);
2663 __ move(T9, disp);
2664 __ daddu(AT, AT, T9);
2665 } else {
2666 __ move(T9, disp);
2667 __ daddu(AT, as_Register(index), T9);
2668 }
2669 __ gsldx(as_Register(dst), as_Register(base), AT, 0);
2670 }
2671 } else { //not use loongson isa
2672 if (scale == 0) {
2673 __ daddu(AT, as_Register(base), as_Register(index));
2674 } else {
2675 __ dsll(AT, as_Register(index), scale);
2676 __ daddu(AT, as_Register(base), AT);
2677 }
2678 if( Assembler::is_simm16(disp) ) {
2679 __ ld(as_Register(dst), AT, disp);
2680 } else {
2681 __ set64(T9, disp);
2682 __ daddu(AT, AT, T9);
2683 __ ld(as_Register(dst), AT, 0);
2684 }
2685 }
2686 } else {
2687 if ( UseLoongsonISA ) {
2688 if ( Assembler::is_simm16(disp) ){
2689 __ ld(as_Register(dst), as_Register(base), disp);
2690 } else {
2691 __ set64(T9, disp);
2692 __ gsldx(as_Register(dst), as_Register(base), T9, 0);
2693 }
2694 } else { //not use loongson isa
2695 if( Assembler::is_simm16(disp) ) {
2696 __ ld(as_Register(dst), as_Register(base), disp);
2697 } else {
2698 __ set64(T9, disp);
2699 __ daddu(AT, as_Register(base), T9);
2700 __ ld(as_Register(dst), AT, 0);
2701 }
2702 }
2703 }
2704 // if( disp_reloc != relocInfo::none) __ ld(as_Register(dst), as_Register(dst), 0);
2705 %}
2707 enc_class store_P_reg_enc (memory mem, mRegP src) %{
2708 MacroAssembler _masm(&cbuf);
2709 int src = $src$$reg;
2710 int base = $mem$$base;
2711 int index = $mem$$index;
2712 int scale = $mem$$scale;
2713 int disp = $mem$$disp;
2715 if( index != 0 ) {
2716 if ( UseLoongsonISA ){
2717 if ( Assembler::is_simm(disp, 8) ) {
2718 if ( scale == 0 ) {
2719 __ gssdx(as_Register(src), as_Register(base), as_Register(index), disp);
2720 } else {
2721 __ dsll(AT, as_Register(index), scale);
2722 __ gssdx(as_Register(src), as_Register(base), AT, disp);
2723 }
2724 } else if ( Assembler::is_simm16(disp) ) {
2725 if ( scale == 0 ) {
2726 __ daddu(AT, as_Register(base), as_Register(index));
2727 } else {
2728 __ dsll(AT, as_Register(index), scale);
2729 __ daddu(AT, as_Register(base), AT);
2730 }
2731 __ sd(as_Register(src), AT, disp);
2732 } else {
2733 if ( scale == 0 ) {
2734 __ move(T9, disp);
2735 __ daddu(AT, as_Register(index), T9);
2736 } else {
2737 __ dsll(AT, as_Register(index), scale);
2738 __ move(T9, disp);
2739 __ daddu(AT, AT, T9);
2740 }
2741 __ gssdx(as_Register(src), as_Register(base), AT, 0);
2742 }
2743 } else { //not use loongson isa
2744 if (scale == 0) {
2745 __ daddu(AT, as_Register(base), as_Register(index));
2746 } else {
2747 __ dsll(AT, as_Register(index), scale);
2748 __ daddu(AT, as_Register(base), AT);
2749 }
2750 if( Assembler::is_simm16(disp) ) {
2751 __ sd(as_Register(src), AT, disp);
2752 } else {
2753 __ move(T9, disp);
2754 __ daddu(AT, AT, T9);
2755 __ sd(as_Register(src), AT, 0);
2756 }
2757 }
2758 } else {
2759 if ( UseLoongsonISA ) {
2760 if ( Assembler::is_simm16(disp) ) {
2761 __ sd(as_Register(src), as_Register(base), disp);
2762 } else {
2763 __ move(T9, disp);
2764 __ gssdx(as_Register(src), as_Register(base), T9, 0);
2765 }
2766 } else {
2767 if( Assembler::is_simm16(disp) ) {
2768 __ sd(as_Register(src), as_Register(base), disp);
2769 } else {
2770 __ move(T9, disp);
2771 __ daddu(AT, as_Register(base), T9);
2772 __ sd(as_Register(src), AT, 0);
2773 }
2774 }
2775 }
2776 %}
2778 enc_class store_N_reg_enc (memory mem, mRegN src) %{
2779 MacroAssembler _masm(&cbuf);
2780 int src = $src$$reg;
2781 int base = $mem$$base;
2782 int index = $mem$$index;
2783 int scale = $mem$$scale;
2784 int disp = $mem$$disp;
2786 if( index != 0 ) {
2787 if ( UseLoongsonISA ){
2788 if ( Assembler::is_simm(disp, 8) ) {
2789 if ( scale == 0 ) {
2790 __ gsswx(as_Register(src), as_Register(base), as_Register(index), disp);
2791 } else {
2792 __ dsll(AT, as_Register(index), scale);
2793 __ gsswx(as_Register(src), as_Register(base), AT, disp);
2794 }
2795 } else if ( Assembler::is_simm16(disp) ) {
2796 if ( scale == 0 ) {
2797 __ daddu(AT, as_Register(base), as_Register(index));
2798 } else {
2799 __ dsll(AT, as_Register(index), scale);
2800 __ daddu(AT, as_Register(base), AT);
2801 }
2802 __ sw(as_Register(src), AT, disp);
2803 } else {
2804 if ( scale == 0 ) {
2805 __ move(T9, disp);
2806 __ daddu(AT, as_Register(index), T9);
2807 } else {
2808 __ dsll(AT, as_Register(index), scale);
2809 __ move(T9, disp);
2810 __ daddu(AT, AT, T9);
2811 }
2812 __ gsswx(as_Register(src), as_Register(base), AT, 0);
2813 }
2814 } else { //not use loongson isa
2815 if (scale == 0) {
2816 __ daddu(AT, as_Register(base), as_Register(index));
2817 } else {
2818 __ dsll(AT, as_Register(index), scale);
2819 __ daddu(AT, as_Register(base), AT);
2820 }
2821 if( Assembler::is_simm16(disp) ) {
2822 __ sw(as_Register(src), AT, disp);
2823 } else {
2824 __ move(T9, disp);
2825 __ daddu(AT, AT, T9);
2826 __ sw(as_Register(src), AT, 0);
2827 }
2828 }
2829 } else {
2830 if ( UseLoongsonISA ) {
2831 if ( Assembler::is_simm16(disp) ) {
2832 __ sw(as_Register(src), as_Register(base), disp);
2833 } else {
2834 __ move(T9, disp);
2835 __ gsswx(as_Register(src), as_Register(base), T9, 0);
2836 }
2837 } else {
2838 if( Assembler::is_simm16(disp) ) {
2839 __ sw(as_Register(src), as_Register(base), disp);
2840 } else {
2841 __ move(T9, disp);
2842 __ daddu(AT, as_Register(base), T9);
2843 __ sw(as_Register(src), AT, 0);
2844 }
2845 }
2846 }
2847 %}
2849 enc_class store_P_immP0_enc (memory mem) %{
2850 MacroAssembler _masm(&cbuf);
2851 int base = $mem$$base;
2852 int index = $mem$$index;
2853 int scale = $mem$$scale;
2854 int disp = $mem$$disp;
2856 if( index != 0 ) {
2857 if (scale == 0) {
2858 if( Assembler::is_simm16(disp) ) {
2859 if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
2860 __ gssdx(R0, as_Register(base), as_Register(index), disp);
2861 } else {
2862 __ daddu(AT, as_Register(base), as_Register(index));
2863 __ sd(R0, AT, disp);
2864 }
2865 } else {
2866 __ daddu(AT, as_Register(base), as_Register(index));
2867 __ move(T9, disp);
2868 if(UseLoongsonISA) {
2869 __ gssdx(R0, AT, T9, 0);
2870 } else {
2871 __ daddu(AT, AT, T9);
2872 __ sd(R0, AT, 0);
2873 }
2874 }
2875 } else {
2876 __ dsll(AT, as_Register(index), scale);
2877 if( Assembler::is_simm16(disp) ) {
2878 if (UseLoongsonISA && Assembler::is_simm(disp, 8)) {
2879 __ gssdx(R0, as_Register(base), AT, disp);
2880 } else {
2881 __ daddu(AT, as_Register(base), AT);
2882 __ sd(R0, AT, disp);
2883 }
2884 } else {
2885 __ daddu(AT, as_Register(base), AT);
2886 __ move(T9, disp);
2887 if (UseLoongsonISA) {
2888 __ gssdx(R0, AT, T9, 0);
2889 } else {
2890 __ daddu(AT, AT, T9);
2891 __ sd(R0, AT, 0);
2892 }
2893 }
2894 }
2895 } else {
2896 if( Assembler::is_simm16(disp) ) {
2897 __ sd(R0, as_Register(base), disp);
2898 } else {
2899 __ move(T9, disp);
2900 if (UseLoongsonISA) {
2901 __ gssdx(R0, as_Register(base), T9, 0);
2902 } else {
2903 __ daddu(AT, as_Register(base), T9);
2904 __ sd(R0, AT, 0);
2905 }
2906 }
2907 }
2908 %}
2910 enc_class storeImmN0_enc(memory mem, ImmN0 src) %{
2911 MacroAssembler _masm(&cbuf);
2912 int base = $mem$$base;
2913 int index = $mem$$index;
2914 int scale = $mem$$scale;
2915 int disp = $mem$$disp;
2917 if(index!=0){
2918 if (scale == 0) {
2919 __ daddu(AT, as_Register(base), as_Register(index));
2920 } else {
2921 __ dsll(AT, as_Register(index), scale);
2922 __ daddu(AT, as_Register(base), AT);
2923 }
2925 if( Assembler::is_simm16(disp) ) {
2926 __ sw(R0, AT, disp);
2927 } else {
2928 __ move(T9, disp);
2929 __ daddu(AT, AT, T9);
2930 __ sw(R0, AT, 0);
2931 }
2932 }
2933 else {
2934 if( Assembler::is_simm16(disp) ) {
2935 __ sw(R0, as_Register(base), disp);
2936 } else {
2937 __ move(T9, disp);
2938 __ daddu(AT, as_Register(base), T9);
2939 __ sw(R0, AT, 0);
2940 }
2941 }
2942 %}
2944 enc_class load_L_enc (mRegL dst, memory mem) %{
2945 MacroAssembler _masm(&cbuf);
2946 int base = $mem$$base;
2947 int index = $mem$$index;
2948 int scale = $mem$$scale;
2949 int disp = $mem$$disp;
2950 Register dst_reg = as_Register($dst$$reg);
2952 // For implicit null check
2953 __ lb(AT, as_Register(base), 0);
2955 if( index != 0 ) {
2956 if (scale == 0) {
2957 __ daddu(AT, as_Register(base), as_Register(index));
2958 } else {
2959 __ dsll(AT, as_Register(index), scale);
2960 __ daddu(AT, as_Register(base), AT);
2961 }
2962 if( Assembler::is_simm16(disp) ) {
2963 __ ld(dst_reg, AT, disp);
2964 } else {
2965 __ move(T9, disp);
2966 __ daddu(AT, AT, T9);
2967 __ ld(dst_reg, AT, 0);
2968 }
2969 } else {
2970 if( Assembler::is_simm16(disp) ) {
2971 __ ld(dst_reg, as_Register(base), disp);
2972 } else {
2973 __ move(T9, disp);
2974 __ daddu(AT, as_Register(base), T9);
2975 __ ld(dst_reg, AT, 0);
2976 }
2977 }
2978 %}
2980 enc_class store_L_reg_enc (memory mem, mRegL src) %{
2981 MacroAssembler _masm(&cbuf);
2982 int base = $mem$$base;
2983 int index = $mem$$index;
2984 int scale = $mem$$scale;
2985 int disp = $mem$$disp;
2986 Register src_reg = as_Register($src$$reg);
2988 if( index != 0 ) {
2989 if (scale == 0) {
2990 __ daddu(AT, as_Register(base), as_Register(index));
2991 } else {
2992 __ dsll(AT, as_Register(index), scale);
2993 __ daddu(AT, as_Register(base), AT);
2994 }
2995 if( Assembler::is_simm16(disp) ) {
2996 __ sd(src_reg, AT, disp);
2997 } else {
2998 __ move(T9, disp);
2999 __ daddu(AT, AT, T9);
3000 __ sd(src_reg, AT, 0);
3001 }
3002 } else {
3003 if( Assembler::is_simm16(disp) ) {
3004 __ sd(src_reg, as_Register(base), disp);
3005 } else {
3006 __ move(T9, disp);
3007 __ daddu(AT, as_Register(base), T9);
3008 __ sd(src_reg, AT, 0);
3009 }
3010 }
3011 %}
3013 enc_class store_L_immL0_enc (memory mem, immL0 src) %{
3014 MacroAssembler _masm(&cbuf);
3015 int base = $mem$$base;
3016 int index = $mem$$index;
3017 int scale = $mem$$scale;
3018 int disp = $mem$$disp;
3020 if( index != 0 ) {
3021 // For implicit null check
3022 __ lb(AT, as_Register(base), 0);
3024 if (scale == 0) {
3025 __ daddu(AT, as_Register(base), as_Register(index));
3026 } else {
3027 __ dsll(AT, as_Register(index), scale);
3028 __ daddu(AT, as_Register(base), AT);
3029 }
3030 if( Assembler::is_simm16(disp) ) {
3031 __ sd(R0, AT, disp);
3032 } else {
3033 __ move(T9, disp);
3034 __ addu(AT, AT, T9);
3035 __ sd(R0, AT, 0);
3036 }
3037 } else {
3038 if( Assembler::is_simm16(disp) ) {
3039 __ sd(R0, as_Register(base), disp);
3040 } else {
3041 __ move(T9, disp);
3042 __ addu(AT, as_Register(base), T9);
3043 __ sd(R0, AT, 0);
3044 }
3045 }
3046 %}
3048 enc_class store_L_immL_enc (memory mem, immL src) %{
3049 MacroAssembler _masm(&cbuf);
3050 int base = $mem$$base;
3051 int index = $mem$$index;
3052 int scale = $mem$$scale;
3053 int disp = $mem$$disp;
3054 long imm = $src$$constant;
3056 if( index != 0 ) {
3057 if (scale == 0) {
3058 __ daddu(AT, as_Register(base), as_Register(index));
3059 } else {
3060 __ dsll(AT, as_Register(index), scale);
3061 __ daddu(AT, as_Register(base), AT);
3062 }
3063 if( Assembler::is_simm16(disp) ) {
3064 __ set64(T9, imm);
3065 __ sd(T9, AT, disp);
3066 } else {
3067 __ move(T9, disp);
3068 __ addu(AT, AT, T9);
3069 __ set64(T9, imm);
3070 __ sd(T9, AT, 0);
3071 }
3072 } else {
3073 if( Assembler::is_simm16(disp) ) {
3074 __ move(AT, as_Register(base));
3075 __ set64(T9, imm);
3076 __ sd(T9, AT, disp);
3077 } else {
3078 __ move(T9, disp);
3079 __ addu(AT, as_Register(base), T9);
3080 __ set64(T9, imm);
3081 __ sd(T9, AT, 0);
3082 }
3083 }
3084 %}
3086 enc_class load_F_enc (regF dst, memory mem) %{
3087 MacroAssembler _masm(&cbuf);
3088 int base = $mem$$base;
3089 int index = $mem$$index;
3090 int scale = $mem$$scale;
3091 int disp = $mem$$disp;
3092 FloatRegister dst = $dst$$FloatRegister;
3094 if( index != 0 ) {
3095 if( Assembler::is_simm16(disp) ) {
3096 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3097 if (scale == 0) {
3098 __ gslwxc1(dst, as_Register(base), as_Register(index), disp);
3099 } else {
3100 __ dsll(AT, as_Register(index), scale);
3101 __ gslwxc1(dst, as_Register(base), AT, disp);
3102 }
3103 } else {
3104 if (scale == 0) {
3105 __ daddu(AT, as_Register(base), as_Register(index));
3106 } else {
3107 __ dsll(AT, as_Register(index), scale);
3108 __ daddu(AT, as_Register(base), AT);
3109 }
3110 __ lwc1(dst, AT, disp);
3111 }
3112 } else {
3113 if (scale == 0) {
3114 __ daddu(AT, as_Register(base), as_Register(index));
3115 } else {
3116 __ dsll(AT, as_Register(index), scale);
3117 __ daddu(AT, as_Register(base), AT);
3118 }
3119 __ move(T9, disp);
3120 if( UseLoongsonISA ) {
3121 __ gslwxc1(dst, AT, T9, 0);
3122 } else {
3123 __ daddu(AT, AT, T9);
3124 __ lwc1(dst, AT, 0);
3125 }
3126 }
3127 } else {
3128 if( Assembler::is_simm16(disp) ) {
3129 __ lwc1(dst, as_Register(base), disp);
3130 } else {
3131 __ move(T9, disp);
3132 if( UseLoongsonISA ) {
3133 __ gslwxc1(dst, as_Register(base), T9, 0);
3134 } else {
3135 __ daddu(AT, as_Register(base), T9);
3136 __ lwc1(dst, AT, 0);
3137 }
3138 }
3139 }
3140 %}
3142 enc_class store_F_reg_enc (memory mem, regF src) %{
3143 MacroAssembler _masm(&cbuf);
3144 int base = $mem$$base;
3145 int index = $mem$$index;
3146 int scale = $mem$$scale;
3147 int disp = $mem$$disp;
3148 FloatRegister src = $src$$FloatRegister;
3150 if( index != 0 ) {
3151 if( Assembler::is_simm16(disp) ) {
3152 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3153 if (scale == 0) {
3154 __ gsswxc1(src, as_Register(base), as_Register(index), disp);
3155 } else {
3156 __ dsll(AT, as_Register(index), scale);
3157 __ gsswxc1(src, as_Register(base), AT, disp);
3158 }
3159 } else {
3160 if (scale == 0) {
3161 __ daddu(AT, as_Register(base), as_Register(index));
3162 } else {
3163 __ dsll(AT, as_Register(index), scale);
3164 __ daddu(AT, as_Register(base), AT);
3165 }
3166 __ swc1(src, AT, disp);
3167 }
3168 } else {
3169 if (scale == 0) {
3170 __ daddu(AT, as_Register(base), as_Register(index));
3171 } else {
3172 __ dsll(AT, as_Register(index), scale);
3173 __ daddu(AT, as_Register(base), AT);
3174 }
3175 __ move(T9, disp);
3176 if( UseLoongsonISA ) {
3177 __ gsswxc1(src, AT, T9, 0);
3178 } else {
3179 __ daddu(AT, AT, T9);
3180 __ swc1(src, AT, 0);
3181 }
3182 }
3183 } else {
3184 if( Assembler::is_simm16(disp) ) {
3185 __ swc1(src, as_Register(base), disp);
3186 } else {
3187 __ move(T9, disp);
3188 if( UseLoongsonISA ) {
3189 __ gsswxc1(src, as_Register(base), T9, 0);
3190 } else {
3191 __ daddu(AT, as_Register(base), T9);
3192 __ swc1(src, AT, 0);
3193 }
3194 }
3195 }
3196 %}
3198 enc_class load_D_enc (regD dst, memory mem) %{
3199 MacroAssembler _masm(&cbuf);
3200 int base = $mem$$base;
3201 int index = $mem$$index;
3202 int scale = $mem$$scale;
3203 int disp = $mem$$disp;
3204 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
3206 if( index != 0 ) {
3207 if( Assembler::is_simm16(disp) ) {
3208 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3209 if (scale == 0) {
3210 __ gsldxc1(dst_reg, as_Register(base), as_Register(index), disp);
3211 } else {
3212 __ dsll(AT, as_Register(index), scale);
3213 __ gsldxc1(dst_reg, as_Register(base), AT, disp);
3214 }
3215 } else {
3216 if (scale == 0) {
3217 __ daddu(AT, as_Register(base), as_Register(index));
3218 } else {
3219 __ dsll(AT, as_Register(index), scale);
3220 __ daddu(AT, as_Register(base), AT);
3221 }
3222 __ ldc1(dst_reg, AT, disp);
3223 }
3224 } else {
3225 if (scale == 0) {
3226 __ daddu(AT, as_Register(base), as_Register(index));
3227 } else {
3228 __ dsll(AT, as_Register(index), scale);
3229 __ daddu(AT, as_Register(base), AT);
3230 }
3231 __ move(T9, disp);
3232 if( UseLoongsonISA ) {
3233 __ gsldxc1(dst_reg, AT, T9, 0);
3234 } else {
3235 __ addu(AT, AT, T9);
3236 __ ldc1(dst_reg, AT, 0);
3237 }
3238 }
3239 } else {
3240 if( Assembler::is_simm16(disp) ) {
3241 __ ldc1(dst_reg, as_Register(base), disp);
3242 } else {
3243 __ move(T9, disp);
3244 if( UseLoongsonISA ) {
3245 __ gsldxc1(dst_reg, as_Register(base), T9, 0);
3246 } else {
3247 __ addu(AT, as_Register(base), T9);
3248 __ ldc1(dst_reg, AT, 0);
3249 }
3250 }
3251 }
3252 %}
3254 enc_class store_D_reg_enc (memory mem, regD src) %{
3255 MacroAssembler _masm(&cbuf);
3256 int base = $mem$$base;
3257 int index = $mem$$index;
3258 int scale = $mem$$scale;
3259 int disp = $mem$$disp;
3260 FloatRegister src_reg = as_FloatRegister($src$$reg);
3262 if( index != 0 ) {
3263 if( Assembler::is_simm16(disp) ) {
3264 if( UseLoongsonISA && Assembler::is_simm(disp, 8) ) {
3265 if (scale == 0) {
3266 __ gssdxc1(src_reg, as_Register(base), as_Register(index), disp);
3267 } else {
3268 __ dsll(AT, as_Register(index), scale);
3269 __ gssdxc1(src_reg, as_Register(base), AT, disp);
3270 }
3271 } else {
3272 if (scale == 0) {
3273 __ daddu(AT, as_Register(base), as_Register(index));
3274 } else {
3275 __ dsll(AT, as_Register(index), scale);
3276 __ daddu(AT, as_Register(base), AT);
3277 }
3278 __ sdc1(src_reg, AT, disp);
3279 }
3280 } else {
3281 if (scale == 0) {
3282 __ daddu(AT, as_Register(base), as_Register(index));
3283 } else {
3284 __ dsll(AT, as_Register(index), scale);
3285 __ daddu(AT, as_Register(base), AT);
3286 }
3287 __ move(T9, disp);
3288 if( UseLoongsonISA ) {
3289 __ gssdxc1(src_reg, AT, T9, 0);
3290 } else {
3291 __ addu(AT, AT, T9);
3292 __ sdc1(src_reg, AT, 0);
3293 }
3294 }
3295 } else {
3296 if( Assembler::is_simm16(disp) ) {
3297 __ sdc1(src_reg, as_Register(base), disp);
3298 } else {
3299 __ move(T9, disp);
3300 if( UseLoongsonISA ) {
3301 __ gssdxc1(src_reg, as_Register(base), T9, 0);
3302 } else {
3303 __ addu(AT, as_Register(base), T9);
3304 __ sdc1(src_reg, AT, 0);
3305 }
3306 }
3307 }
3308 %}
3310 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
3311 MacroAssembler _masm(&cbuf);
3312 // This is the instruction starting address for relocation info.
3313 __ block_comment("Java_To_Runtime");
3314 cbuf.set_insts_mark();
3315 __ relocate(relocInfo::runtime_call_type);
3317 __ patchable_call((address)$meth$$method);
3318 %}
3320 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
3321 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
3322 // who we intended to call.
3323 MacroAssembler _masm(&cbuf);
3324 cbuf.set_insts_mark();
3326 if ( !_method ) {
3327 __ relocate(relocInfo::runtime_call_type);
3328 } else if(_optimized_virtual) {
3329 __ relocate(relocInfo::opt_virtual_call_type);
3330 } else {
3331 __ relocate(relocInfo::static_call_type);
3332 }
3334 __ patchable_call((address)($meth$$method));
3335 if( _method ) { // Emit stub for static call
3336 emit_java_to_interp(cbuf);
3337 }
3338 %}
3341 /*
3342 * [Ref: LIR_Assembler::ic_call() ]
3343 */
3344 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
3345 MacroAssembler _masm(&cbuf);
3346 __ block_comment("Java_Dynamic_Call");
3347 __ ic_call((address)$meth$$method);
3348 %}
3351 enc_class Set_Flags_After_Fast_Lock_Unlock(FlagsReg cr) %{
3352 Register flags = $cr$$Register;
3353 Label L;
3355 MacroAssembler _masm(&cbuf);
3357 __ addu(flags, R0, R0);
3358 __ beq(AT, R0, L);
3359 __ delayed()->nop();
3360 __ move(flags, 0xFFFFFFFF);
3361 __ bind(L);
3362 %}
3364 enc_class enc_PartialSubtypeCheck(mRegP result, mRegP sub, mRegP super, mRegI tmp) %{
3365 Register result = $result$$Register;
3366 Register sub = $sub$$Register;
3367 Register super = $super$$Register;
3368 Register length = $tmp$$Register;
3369 Register tmp = T9;
3370 Label miss;
3372 /* 2012/9/28 Jin: result may be the same as sub
3373 * 47c B40: # B21 B41 <- B20 Freq: 0.155379
3374 * 47c partialSubtypeCheck result=S1, sub=S1, super=S3, length=S0
3375 * 4bc mov S2, NULL #@loadConP
3376 * 4c0 beq S1, S2, B21 #@branchConP P=0.999999 C=-1.000000
3377 */
3378 MacroAssembler _masm(&cbuf);
3379 Label done;
3380 __ check_klass_subtype_slow_path(sub, super, length, tmp,
3381 NULL, &miss,
3382 /*set_cond_codes:*/ true);
3383 /* 2013/7/22 Jin: Refer to X86_64's RDI */
3384 __ move(result, 0);
3385 __ b(done);
3386 __ nop();
3388 __ bind(miss);
3389 __ move(result, 1);
3390 __ bind(done);
3391 %}
3393 %}
3396 //---------MIPS FRAME--------------------------------------------------------------
3397 // Definition of frame structure and management information.
3398 //
3399 // S T A C K L A Y O U T Allocators stack-slot number
3400 // | (to get allocators register number
3401 // G Owned by | | v add SharedInfo::stack0)
3402 // r CALLER | |
3403 // o | +--------+ pad to even-align allocators stack-slot
3404 // w V | pad0 | numbers; owned by CALLER
3405 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3406 // h ^ | in | 5
3407 // | | args | 4 Holes in incoming args owned by SELF
3408 // | | old | | 3
3409 // | | SP-+--------+----> Matcher::_old_SP, even aligned
3410 // v | | ret | 3 return address
3411 // Owned by +--------+
3412 // Self | pad2 | 2 pad to align old SP
3413 // | +--------+ 1
3414 // | | locks | 0
3415 // | +--------+----> SharedInfo::stack0, even aligned
3416 // | | pad1 | 11 pad to align new SP
3417 // | +--------+
3418 // | | | 10
3419 // | | spills | 9 spills
3420 // V | | 8 (pad0 slot for callee)
3421 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3422 // ^ | out | 7
3423 // | | args | 6 Holes in outgoing args owned by CALLEE
3424 // Owned by new | |
3425 // Callee SP-+--------+----> Matcher::_new_SP, even aligned
3426 // | |
3427 //
3428 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3429 // known from SELF's arguments and the Java calling convention.
3430 // Region 6-7 is determined per call site.
3431 // Note 2: If the calling convention leaves holes in the incoming argument
3432 // area, those holes are owned by SELF. Holes in the outgoing area
3433 // are owned by the CALLEE. Holes should not be nessecary in the
3434 // incoming area, as the Java calling convention is completely under
3435 // the control of the AD file. Doubles can be sorted and packed to
3436 // avoid holes. Holes in the outgoing arguments may be nessecary for
3437 // varargs C calling conventions.
3438 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3439 // even aligned with pad0 as needed.
3440 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3441 // region 6-11 is even aligned; it may be padded out more so that
3442 // the region from SP to FP meets the minimum stack alignment.
3443 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
3444 // alignment. Region 11, pad1, may be dynamically extended so that
3445 // SP meets the minimum alignment.
3448 frame %{
3450 stack_direction(TOWARDS_LOW);
3452 // These two registers define part of the calling convention
3453 // between compiled code and the interpreter.
3454 // SEE StartI2CNode::calling_convention & StartC2INode::calling_convention & StartOSRNode::calling_convention
3455 // for more information. by yjl 3/16/2006
3457 inline_cache_reg(T1); // Inline Cache Register
3458 interpreter_method_oop_reg(S3); // Method Oop Register when calling interpreter
3459 /*
3460 inline_cache_reg(T1); // Inline Cache Register or methodOop for I2C
3461 interpreter_arg_ptr_reg(A0); // Argument pointer for I2C adapters
3462 */
3464 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3465 cisc_spilling_operand_name(indOffset32);
3467 // Number of stack slots consumed by locking an object
3468 // generate Compile::sync_stack_slots
3469 #ifdef _LP64
3470 sync_stack_slots(2);
3471 #else
3472 sync_stack_slots(1);
3473 #endif
3475 frame_pointer(SP);
3477 // Interpreter stores its frame pointer in a register which is
3478 // stored to the stack by I2CAdaptors.
3479 // I2CAdaptors convert from interpreted java to compiled java.
3481 interpreter_frame_pointer(FP);
3483 // generate Matcher::stack_alignment
3484 stack_alignment(StackAlignmentInBytes); //wordSize = sizeof(char*);
3486 // Number of stack slots between incoming argument block and the start of
3487 // a new frame. The PROLOG must add this many slots to the stack. The
3488 // EPILOG must remove this many slots. Intel needs one slot for
3489 // return address.
3490 // generate Matcher::in_preserve_stack_slots
3491 //in_preserve_stack_slots(VerifyStackAtCalls + 2); //Now VerifyStackAtCalls is defined as false ! Leave one stack slot for ra and fp
3492 in_preserve_stack_slots(4); //Now VerifyStackAtCalls is defined as false ! Leave two stack slots for ra and fp
3494 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3495 // for calls to C. Supports the var-args backing area for register parms.
3496 varargs_C_out_slots_killed(0);
3498 // The after-PROLOG location of the return address. Location of
3499 // return address specifies a type (REG or STACK) and a number
3500 // representing the register number (i.e. - use a register name) or
3501 // stack slot.
3502 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3503 // Otherwise, it is above the locks and verification slot and alignment word
3504 //return_addr(STACK -1+ round_to(1+VerifyStackAtCalls+Compile::current()->sync()*Compile::current()->sync_stack_slots(),WordsPerLong));
3505 return_addr(REG RA);
3507 // Body of function which returns an integer array locating
3508 // arguments either in registers or in stack slots. Passed an array
3509 // of ideal registers called "sig" and a "length" count. Stack-slot
3510 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3511 // arguments for a CALLEE. Incoming stack arguments are
3512 // automatically biased by the preserve_stack_slots field above.
3515 // will generated to Matcher::calling_convention(OptoRegPair *sig, uint length, bool is_outgoing)
3516 // StartNode::calling_convention call this. by yjl 3/16/2006
3517 calling_convention %{
3518 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3519 %}
3524 // Body of function which returns an integer array locating
3525 // arguments either in registers or in stack slots. Passed an array
3526 // of ideal registers called "sig" and a "length" count. Stack-slot
3527 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3528 // arguments for a CALLEE. Incoming stack arguments are
3529 // automatically biased by the preserve_stack_slots field above.
3532 // SEE CallRuntimeNode::calling_convention for more information. by yjl 3/16/2006
3533 c_calling_convention %{
3534 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3535 %}
3538 // Location of C & interpreter return values
3539 // register(s) contain(s) return value for Op_StartI2C and Op_StartOSR.
3540 // SEE Matcher::match. by yjl 3/16/2006
3541 c_return_value %{
3542 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3543 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3544 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3545 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num };
3546 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3547 %}
3549 // Location of return values
3550 // register(s) contain(s) return value for Op_StartC2I and Op_Start.
3551 // SEE Matcher::match. by yjl 3/16/2006
3553 return_value %{
3554 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3555 /* -- , -- , Op_RegN, Op_RegI, Op_RegP, Op_RegF, Op_RegD, Op_RegL */
3556 static int lo[Op_RegL+1] = { 0, 0, V0_num, V0_num, V0_num, F0_num, F0_num, V0_num };
3557 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, V0_H_num, OptoReg::Bad, F0_H_num, V0_H_num};
3558 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3559 %}
3561 %}
3563 //----------ATTRIBUTES---------------------------------------------------------
3564 //----------Operand Attributes-------------------------------------------------
3565 op_attrib op_cost(0); // Required cost attribute
3567 //----------Instruction Attributes---------------------------------------------
3568 ins_attrib ins_cost(100); // Required cost attribute
3569 ins_attrib ins_size(32); // Required size attribute (in bits)
3570 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3571 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3572 // non-matching short branch variant of some
3573 // long branch?
3574 ins_attrib ins_alignment(4); // Required alignment attribute (must be a power of 2)
3575 // specifies the alignment that some part of the instruction (not
3576 // necessarily the start) requires. If > 1, a compute_padding()
3577 // function must be provided for the instruction
3579 //----------OPERANDS-----------------------------------------------------------
3580 // Operand definitions must precede instruction definitions for correct parsing
3581 // in the ADLC because operands constitute user defined types which are used in
3582 // instruction definitions.
3584 // Vectors
3585 operand vecD() %{
3586 constraint(ALLOC_IN_RC(dbl_reg));
3587 match(VecD);
3589 format %{ %}
3590 interface(REG_INTER);
3591 %}
3593 // Flags register, used as output of compare instructions
3594 operand FlagsReg() %{
3595 constraint(ALLOC_IN_RC(mips_flags));
3596 match(RegFlags);
3598 format %{ "EFLAGS" %}
3599 interface(REG_INTER);
3600 %}
3602 //----------Simple Operands----------------------------------------------------
3603 //TODO: Should we need to define some more special immediate number ?
3604 // Immediate Operands
3605 // Integer Immediate
3606 operand immI() %{
3607 match(ConI);
3608 //TODO: should not match immI8 here LEE
3609 match(immI8);
3611 op_cost(20);
3612 format %{ %}
3613 interface(CONST_INTER);
3614 %}
3616 // Long Immediate 8-bit
3617 operand immL8()
3618 %{
3619 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3620 match(ConL);
3622 op_cost(5);
3623 format %{ %}
3624 interface(CONST_INTER);
3625 %}
3627 // Constant for test vs zero
3628 operand immI0() %{
3629 predicate(n->get_int() == 0);
3630 match(ConI);
3632 op_cost(0);
3633 format %{ %}
3634 interface(CONST_INTER);
3635 %}
3637 // Constant for increment
3638 operand immI1() %{
3639 predicate(n->get_int() == 1);
3640 match(ConI);
3642 op_cost(0);
3643 format %{ %}
3644 interface(CONST_INTER);
3645 %}
3647 // Constant for decrement
3648 operand immI_M1() %{
3649 predicate(n->get_int() == -1);
3650 match(ConI);
3652 op_cost(0);
3653 format %{ %}
3654 interface(CONST_INTER);
3655 %}
3657 operand immI_MaxI() %{
3658 predicate(n->get_int() == 2147483647);
3659 match(ConI);
3661 op_cost(0);
3662 format %{ %}
3663 interface(CONST_INTER);
3664 %}
3666 // Valid scale values for addressing modes
3667 operand immI2() %{
3668 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3669 match(ConI);
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3675 operand immI8() %{
3676 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3677 match(ConI);
3679 op_cost(5);
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3684 operand immI16() %{
3685 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3686 match(ConI);
3688 op_cost(10);
3689 format %{ %}
3690 interface(CONST_INTER);
3691 %}
3693 // Constant for long shifts
3694 operand immI_32() %{
3695 predicate( n->get_int() == 32 );
3696 match(ConI);
3698 op_cost(0);
3699 format %{ %}
3700 interface(CONST_INTER);
3701 %}
3703 operand immI_63() %{
3704 predicate( n->get_int() == 63 );
3705 match(ConI);
3707 op_cost(0);
3708 format %{ %}
3709 interface(CONST_INTER);
3710 %}
3712 operand immI_0_31() %{
3713 predicate( n->get_int() >= 0 && n->get_int() <= 31 );
3714 match(ConI);
3716 op_cost(0);
3717 format %{ %}
3718 interface(CONST_INTER);
3719 %}
3721 // Operand for non-negtive integer mask
3722 operand immI_nonneg_mask() %{
3723 predicate( (n->get_int() >= 0) && (Assembler::is_int_mask(n->get_int()) != -1) );
3724 match(ConI);
3726 op_cost(0);
3727 format %{ %}
3728 interface(CONST_INTER);
3729 %}
3731 operand immI_32_63() %{
3732 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3733 match(ConI);
3734 op_cost(0);
3736 format %{ %}
3737 interface(CONST_INTER);
3738 %}
3740 operand immI16_sub() %{
3741 predicate((-32767 <= n->get_int()) && (n->get_int() <= 32768));
3742 match(ConI);
3744 op_cost(10);
3745 format %{ %}
3746 interface(CONST_INTER);
3747 %}
3749 operand immI_0_32767() %{
3750 predicate( n->get_int() >= 0 && n->get_int() <= 32767 );
3751 match(ConI);
3752 op_cost(0);
3754 format %{ %}
3755 interface(CONST_INTER);
3756 %}
3758 operand immI_0_65535() %{
3759 predicate( n->get_int() >= 0 && n->get_int() <= 65535 );
3760 match(ConI);
3761 op_cost(0);
3763 format %{ %}
3764 interface(CONST_INTER);
3765 %}
3767 operand immI_1() %{
3768 predicate( n->get_int() == 1 );
3769 match(ConI);
3771 op_cost(0);
3772 format %{ %}
3773 interface(CONST_INTER);
3774 %}
3776 operand immI_2() %{
3777 predicate( n->get_int() == 2 );
3778 match(ConI);
3780 op_cost(0);
3781 format %{ %}
3782 interface(CONST_INTER);
3783 %}
3785 operand immI_3() %{
3786 predicate( n->get_int() == 3 );
3787 match(ConI);
3789 op_cost(0);
3790 format %{ %}
3791 interface(CONST_INTER);
3792 %}
3794 operand immI_7() %{
3795 predicate( n->get_int() == 7 );
3796 match(ConI);
3798 format %{ %}
3799 interface(CONST_INTER);
3800 %}
3802 // Immediates for special shifts (sign extend)
3804 // Constants for increment
3805 operand immI_16() %{
3806 predicate( n->get_int() == 16 );
3807 match(ConI);
3809 format %{ %}
3810 interface(CONST_INTER);
3811 %}
3813 operand immI_24() %{
3814 predicate( n->get_int() == 24 );
3815 match(ConI);
3817 format %{ %}
3818 interface(CONST_INTER);
3819 %}
3821 // Constant for byte-wide masking
3822 operand immI_255() %{
3823 predicate( n->get_int() == 255 );
3824 match(ConI);
3826 op_cost(0);
3827 format %{ %}
3828 interface(CONST_INTER);
3829 %}
3831 operand immI_65535() %{
3832 predicate( n->get_int() == 65535 );
3833 match(ConI);
3835 op_cost(5);
3836 format %{ %}
3837 interface(CONST_INTER);
3838 %}
3840 operand immI_65536() %{
3841 predicate( n->get_int() == 65536 );
3842 match(ConI);
3844 op_cost(5);
3845 format %{ %}
3846 interface(CONST_INTER);
3847 %}
3849 operand immI_M65536() %{
3850 predicate( n->get_int() == -65536 );
3851 match(ConI);
3853 op_cost(5);
3854 format %{ %}
3855 interface(CONST_INTER);
3856 %}
3858 // Pointer Immediate
3859 operand immP() %{
3860 match(ConP);
3862 op_cost(10);
3863 format %{ %}
3864 interface(CONST_INTER);
3865 %}
3867 // NULL Pointer Immediate
3868 operand immP0() %{
3869 predicate( n->get_ptr() == 0 );
3870 match(ConP);
3871 op_cost(0);
3873 format %{ %}
3874 interface(CONST_INTER);
3875 %}
3877 // Pointer Immediate: 64-bit
3878 operand immP_set() %{
3879 match(ConP);
3881 op_cost(5);
3882 // formats are generated automatically for constants and base registers
3883 format %{ %}
3884 interface(CONST_INTER);
3885 %}
3887 // Pointer Immediate: 64-bit
3888 operand immP_load() %{
3889 predicate(n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set64(n->get_ptr()) > 3));
3890 match(ConP);
3892 op_cost(5);
3893 // formats are generated automatically for constants and base registers
3894 format %{ %}
3895 interface(CONST_INTER);
3896 %}
3898 // Pointer Immediate: 64-bit
3899 operand immP_no_oop_cheap() %{
3900 predicate(!n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set64(n->get_ptr()) <= 3));
3901 match(ConP);
3903 op_cost(5);
3904 // formats are generated automatically for constants and base registers
3905 format %{ %}
3906 interface(CONST_INTER);
3907 %}
3909 // Pointer for polling page
3910 operand immP_poll() %{
3911 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3912 match(ConP);
3913 op_cost(5);
3915 format %{ %}
3916 interface(CONST_INTER);
3917 %}
3919 // Pointer Immediate
3920 operand immN() %{
3921 match(ConN);
3923 op_cost(10);
3924 format %{ %}
3925 interface(CONST_INTER);
3926 %}
3928 operand immNKlass() %{
3929 match(ConNKlass);
3931 op_cost(10);
3932 format %{ %}
3933 interface(CONST_INTER);
3934 %}
3936 // NULL Pointer Immediate
3937 operand immN0() %{
3938 predicate(n->get_narrowcon() == 0);
3939 match(ConN);
3941 op_cost(5);
3942 format %{ %}
3943 interface(CONST_INTER);
3944 %}
3946 // Long Immediate
3947 operand immL() %{
3948 match(ConL);
3950 op_cost(20);
3951 format %{ %}
3952 interface(CONST_INTER);
3953 %}
3955 // Long Immediate zero
3956 operand immL0() %{
3957 predicate( n->get_long() == 0L );
3958 match(ConL);
3959 op_cost(0);
3961 format %{ %}
3962 interface(CONST_INTER);
3963 %}
3965 operand immL7() %{
3966 predicate( n->get_long() == 7L );
3967 match(ConL);
3968 op_cost(0);
3970 format %{ %}
3971 interface(CONST_INTER);
3972 %}
3974 operand immL_M1() %{
3975 predicate( n->get_long() == -1L );
3976 match(ConL);
3977 op_cost(0);
3979 format %{ %}
3980 interface(CONST_INTER);
3981 %}
3983 // bit 0..2 zero
3984 operand immL_M8() %{
3985 predicate( n->get_long() == -8L );
3986 match(ConL);
3987 op_cost(0);
3989 format %{ %}
3990 interface(CONST_INTER);
3991 %}
3993 // bit 2 zero
3994 operand immL_M5() %{
3995 predicate( n->get_long() == -5L );
3996 match(ConL);
3997 op_cost(0);
3999 format %{ %}
4000 interface(CONST_INTER);
4001 %}
4003 // bit 1..2 zero
4004 operand immL_M7() %{
4005 predicate( n->get_long() == -7L );
4006 match(ConL);
4007 op_cost(0);
4009 format %{ %}
4010 interface(CONST_INTER);
4011 %}
4013 // bit 0..1 zero
4014 operand immL_M4() %{
4015 predicate( n->get_long() == -4L );
4016 match(ConL);
4017 op_cost(0);
4019 format %{ %}
4020 interface(CONST_INTER);
4021 %}
4023 // bit 3..6 zero
4024 operand immL_M121() %{
4025 predicate( n->get_long() == -121L );
4026 match(ConL);
4027 op_cost(0);
4029 format %{ %}
4030 interface(CONST_INTER);
4031 %}
4033 // Long immediate from 0 to 127.
4034 // Used for a shorter form of long mul by 10.
4035 operand immL_127() %{
4036 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4037 match(ConL);
4038 op_cost(0);
4040 format %{ %}
4041 interface(CONST_INTER);
4042 %}
4044 // Operand for non-negtive long mask
4045 operand immL_nonneg_mask() %{
4046 predicate( (n->get_long() >= 0) && (Assembler::is_jlong_mask(n->get_long()) != -1) );
4047 match(ConL);
4049 op_cost(0);
4050 format %{ %}
4051 interface(CONST_INTER);
4052 %}
4054 operand immL_0_65535() %{
4055 predicate( n->get_long() >= 0 && n->get_long() <= 65535 );
4056 match(ConL);
4057 op_cost(0);
4059 format %{ %}
4060 interface(CONST_INTER);
4061 %}
4063 // Long Immediate: cheap (materialize in <= 3 instructions)
4064 operand immL_cheap() %{
4065 predicate(MacroAssembler::insts_for_set64(n->get_long()) <= 3);
4066 match(ConL);
4067 op_cost(0);
4069 format %{ %}
4070 interface(CONST_INTER);
4071 %}
4073 // Long Immediate: expensive (materialize in > 3 instructions)
4074 operand immL_expensive() %{
4075 predicate(MacroAssembler::insts_for_set64(n->get_long()) > 3);
4076 match(ConL);
4077 op_cost(0);
4079 format %{ %}
4080 interface(CONST_INTER);
4081 %}
4083 operand immL16() %{
4084 predicate((-32768 <= n->get_long()) && (n->get_long() <= 32767));
4085 match(ConL);
4087 op_cost(10);
4088 format %{ %}
4089 interface(CONST_INTER);
4090 %}
4092 operand immL16_sub() %{
4093 predicate((-32767 <= n->get_long()) && (n->get_long() <= 32768));
4094 match(ConL);
4096 op_cost(10);
4097 format %{ %}
4098 interface(CONST_INTER);
4099 %}
4101 // Long Immediate: low 32-bit mask
4102 operand immL_32bits() %{
4103 predicate(n->get_long() == 0xFFFFFFFFL);
4104 match(ConL);
4105 op_cost(20);
4107 format %{ %}
4108 interface(CONST_INTER);
4109 %}
4111 // Long Immediate 32-bit signed
4112 operand immL32()
4113 %{
4114 predicate(n->get_long() == (int) (n->get_long()));
4115 match(ConL);
4117 op_cost(15);
4118 format %{ %}
4119 interface(CONST_INTER);
4120 %}
4123 //single-precision floating-point zero
4124 operand immF0() %{
4125 predicate(jint_cast(n->getf()) == 0);
4126 match(ConF);
4128 op_cost(5);
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4133 //single-precision floating-point immediate
4134 operand immF() %{
4135 match(ConF);
4137 op_cost(20);
4138 format %{ %}
4139 interface(CONST_INTER);
4140 %}
4142 //double-precision floating-point zero
4143 operand immD0() %{
4144 predicate(jlong_cast(n->getd()) == 0);
4145 match(ConD);
4147 op_cost(5);
4148 format %{ %}
4149 interface(CONST_INTER);
4150 %}
4152 //double-precision floating-point immediate
4153 operand immD() %{
4154 match(ConD);
4156 op_cost(20);
4157 format %{ %}
4158 interface(CONST_INTER);
4159 %}
4161 // Register Operands
4162 // Integer Register
4163 operand mRegI() %{
4164 constraint(ALLOC_IN_RC(int_reg));
4165 match(RegI);
4167 format %{ %}
4168 interface(REG_INTER);
4169 %}
4171 operand no_Ax_mRegI() %{
4172 constraint(ALLOC_IN_RC(no_Ax_int_reg));
4173 match(RegI);
4174 match(mRegI);
4176 format %{ %}
4177 interface(REG_INTER);
4178 %}
4180 operand mS0RegI() %{
4181 constraint(ALLOC_IN_RC(s0_reg));
4182 match(RegI);
4183 match(mRegI);
4185 format %{ "S0" %}
4186 interface(REG_INTER);
4187 %}
4189 operand mS1RegI() %{
4190 constraint(ALLOC_IN_RC(s1_reg));
4191 match(RegI);
4192 match(mRegI);
4194 format %{ "S1" %}
4195 interface(REG_INTER);
4196 %}
4198 operand mS2RegI() %{
4199 constraint(ALLOC_IN_RC(s2_reg));
4200 match(RegI);
4201 match(mRegI);
4203 format %{ "S2" %}
4204 interface(REG_INTER);
4205 %}
4207 operand mS3RegI() %{
4208 constraint(ALLOC_IN_RC(s3_reg));
4209 match(RegI);
4210 match(mRegI);
4212 format %{ "S3" %}
4213 interface(REG_INTER);
4214 %}
4216 operand mS4RegI() %{
4217 constraint(ALLOC_IN_RC(s4_reg));
4218 match(RegI);
4219 match(mRegI);
4221 format %{ "S4" %}
4222 interface(REG_INTER);
4223 %}
4225 operand mS5RegI() %{
4226 constraint(ALLOC_IN_RC(s5_reg));
4227 match(RegI);
4228 match(mRegI);
4230 format %{ "S5" %}
4231 interface(REG_INTER);
4232 %}
4234 operand mS6RegI() %{
4235 constraint(ALLOC_IN_RC(s6_reg));
4236 match(RegI);
4237 match(mRegI);
4239 format %{ "S6" %}
4240 interface(REG_INTER);
4241 %}
4243 operand mS7RegI() %{
4244 constraint(ALLOC_IN_RC(s7_reg));
4245 match(RegI);
4246 match(mRegI);
4248 format %{ "S7" %}
4249 interface(REG_INTER);
4250 %}
4253 operand mT0RegI() %{
4254 constraint(ALLOC_IN_RC(t0_reg));
4255 match(RegI);
4256 match(mRegI);
4258 format %{ "T0" %}
4259 interface(REG_INTER);
4260 %}
4262 operand mT1RegI() %{
4263 constraint(ALLOC_IN_RC(t1_reg));
4264 match(RegI);
4265 match(mRegI);
4267 format %{ "T1" %}
4268 interface(REG_INTER);
4269 %}
4271 operand mT2RegI() %{
4272 constraint(ALLOC_IN_RC(t2_reg));
4273 match(RegI);
4274 match(mRegI);
4276 format %{ "T2" %}
4277 interface(REG_INTER);
4278 %}
4280 operand mT3RegI() %{
4281 constraint(ALLOC_IN_RC(t3_reg));
4282 match(RegI);
4283 match(mRegI);
4285 format %{ "T3" %}
4286 interface(REG_INTER);
4287 %}
4289 operand mT8RegI() %{
4290 constraint(ALLOC_IN_RC(t8_reg));
4291 match(RegI);
4292 match(mRegI);
4294 format %{ "T8" %}
4295 interface(REG_INTER);
4296 %}
4298 operand mT9RegI() %{
4299 constraint(ALLOC_IN_RC(t9_reg));
4300 match(RegI);
4301 match(mRegI);
4303 format %{ "T9" %}
4304 interface(REG_INTER);
4305 %}
4307 operand mA0RegI() %{
4308 constraint(ALLOC_IN_RC(a0_reg));
4309 match(RegI);
4310 match(mRegI);
4312 format %{ "A0" %}
4313 interface(REG_INTER);
4314 %}
4316 operand mA1RegI() %{
4317 constraint(ALLOC_IN_RC(a1_reg));
4318 match(RegI);
4319 match(mRegI);
4321 format %{ "A1" %}
4322 interface(REG_INTER);
4323 %}
4325 operand mA2RegI() %{
4326 constraint(ALLOC_IN_RC(a2_reg));
4327 match(RegI);
4328 match(mRegI);
4330 format %{ "A2" %}
4331 interface(REG_INTER);
4332 %}
4334 operand mA3RegI() %{
4335 constraint(ALLOC_IN_RC(a3_reg));
4336 match(RegI);
4337 match(mRegI);
4339 format %{ "A3" %}
4340 interface(REG_INTER);
4341 %}
4343 operand mA4RegI() %{
4344 constraint(ALLOC_IN_RC(a4_reg));
4345 match(RegI);
4346 match(mRegI);
4348 format %{ "A4" %}
4349 interface(REG_INTER);
4350 %}
4352 operand mA5RegI() %{
4353 constraint(ALLOC_IN_RC(a5_reg));
4354 match(RegI);
4355 match(mRegI);
4357 format %{ "A5" %}
4358 interface(REG_INTER);
4359 %}
4361 operand mA6RegI() %{
4362 constraint(ALLOC_IN_RC(a6_reg));
4363 match(RegI);
4364 match(mRegI);
4366 format %{ "A6" %}
4367 interface(REG_INTER);
4368 %}
4370 operand mA7RegI() %{
4371 constraint(ALLOC_IN_RC(a7_reg));
4372 match(RegI);
4373 match(mRegI);
4375 format %{ "A7" %}
4376 interface(REG_INTER);
4377 %}
4379 operand mV0RegI() %{
4380 constraint(ALLOC_IN_RC(v0_reg));
4381 match(RegI);
4382 match(mRegI);
4384 format %{ "V0" %}
4385 interface(REG_INTER);
4386 %}
4388 operand mV1RegI() %{
4389 constraint(ALLOC_IN_RC(v1_reg));
4390 match(RegI);
4391 match(mRegI);
4393 format %{ "V1" %}
4394 interface(REG_INTER);
4395 %}
4397 operand mRegN() %{
4398 constraint(ALLOC_IN_RC(int_reg));
4399 match(RegN);
4401 format %{ %}
4402 interface(REG_INTER);
4403 %}
4405 operand t0_RegN() %{
4406 constraint(ALLOC_IN_RC(t0_reg));
4407 match(RegN);
4408 match(mRegN);
4410 format %{ %}
4411 interface(REG_INTER);
4412 %}
4414 operand t1_RegN() %{
4415 constraint(ALLOC_IN_RC(t1_reg));
4416 match(RegN);
4417 match(mRegN);
4419 format %{ %}
4420 interface(REG_INTER);
4421 %}
4423 operand t2_RegN() %{
4424 constraint(ALLOC_IN_RC(t2_reg));
4425 match(RegN);
4426 match(mRegN);
4428 format %{ %}
4429 interface(REG_INTER);
4430 %}
4432 operand t3_RegN() %{
4433 constraint(ALLOC_IN_RC(t3_reg));
4434 match(RegN);
4435 match(mRegN);
4437 format %{ %}
4438 interface(REG_INTER);
4439 %}
4441 operand t8_RegN() %{
4442 constraint(ALLOC_IN_RC(t8_reg));
4443 match(RegN);
4444 match(mRegN);
4446 format %{ %}
4447 interface(REG_INTER);
4448 %}
4450 operand t9_RegN() %{
4451 constraint(ALLOC_IN_RC(t9_reg));
4452 match(RegN);
4453 match(mRegN);
4455 format %{ %}
4456 interface(REG_INTER);
4457 %}
4459 operand a0_RegN() %{
4460 constraint(ALLOC_IN_RC(a0_reg));
4461 match(RegN);
4462 match(mRegN);
4464 format %{ %}
4465 interface(REG_INTER);
4466 %}
4468 operand a1_RegN() %{
4469 constraint(ALLOC_IN_RC(a1_reg));
4470 match(RegN);
4471 match(mRegN);
4473 format %{ %}
4474 interface(REG_INTER);
4475 %}
4477 operand a2_RegN() %{
4478 constraint(ALLOC_IN_RC(a2_reg));
4479 match(RegN);
4480 match(mRegN);
4482 format %{ %}
4483 interface(REG_INTER);
4484 %}
4486 operand a3_RegN() %{
4487 constraint(ALLOC_IN_RC(a3_reg));
4488 match(RegN);
4489 match(mRegN);
4491 format %{ %}
4492 interface(REG_INTER);
4493 %}
4495 operand a4_RegN() %{
4496 constraint(ALLOC_IN_RC(a4_reg));
4497 match(RegN);
4498 match(mRegN);
4500 format %{ %}
4501 interface(REG_INTER);
4502 %}
4504 operand a5_RegN() %{
4505 constraint(ALLOC_IN_RC(a5_reg));
4506 match(RegN);
4507 match(mRegN);
4509 format %{ %}
4510 interface(REG_INTER);
4511 %}
4513 operand a6_RegN() %{
4514 constraint(ALLOC_IN_RC(a6_reg));
4515 match(RegN);
4516 match(mRegN);
4518 format %{ %}
4519 interface(REG_INTER);
4520 %}
4522 operand a7_RegN() %{
4523 constraint(ALLOC_IN_RC(a7_reg));
4524 match(RegN);
4525 match(mRegN);
4527 format %{ %}
4528 interface(REG_INTER);
4529 %}
4531 operand s0_RegN() %{
4532 constraint(ALLOC_IN_RC(s0_reg));
4533 match(RegN);
4534 match(mRegN);
4536 format %{ %}
4537 interface(REG_INTER);
4538 %}
4540 operand s1_RegN() %{
4541 constraint(ALLOC_IN_RC(s1_reg));
4542 match(RegN);
4543 match(mRegN);
4545 format %{ %}
4546 interface(REG_INTER);
4547 %}
4549 operand s2_RegN() %{
4550 constraint(ALLOC_IN_RC(s2_reg));
4551 match(RegN);
4552 match(mRegN);
4554 format %{ %}
4555 interface(REG_INTER);
4556 %}
4558 operand s3_RegN() %{
4559 constraint(ALLOC_IN_RC(s3_reg));
4560 match(RegN);
4561 match(mRegN);
4563 format %{ %}
4564 interface(REG_INTER);
4565 %}
4567 operand s4_RegN() %{
4568 constraint(ALLOC_IN_RC(s4_reg));
4569 match(RegN);
4570 match(mRegN);
4572 format %{ %}
4573 interface(REG_INTER);
4574 %}
4576 operand s5_RegN() %{
4577 constraint(ALLOC_IN_RC(s5_reg));
4578 match(RegN);
4579 match(mRegN);
4581 format %{ %}
4582 interface(REG_INTER);
4583 %}
4585 operand s6_RegN() %{
4586 constraint(ALLOC_IN_RC(s6_reg));
4587 match(RegN);
4588 match(mRegN);
4590 format %{ %}
4591 interface(REG_INTER);
4592 %}
4594 operand s7_RegN() %{
4595 constraint(ALLOC_IN_RC(s7_reg));
4596 match(RegN);
4597 match(mRegN);
4599 format %{ %}
4600 interface(REG_INTER);
4601 %}
4603 operand v0_RegN() %{
4604 constraint(ALLOC_IN_RC(v0_reg));
4605 match(RegN);
4606 match(mRegN);
4608 format %{ %}
4609 interface(REG_INTER);
4610 %}
4612 operand v1_RegN() %{
4613 constraint(ALLOC_IN_RC(v1_reg));
4614 match(RegN);
4615 match(mRegN);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4621 // Pointer Register
4622 operand mRegP() %{
4623 constraint(ALLOC_IN_RC(p_reg));
4624 match(RegP);
4626 format %{ %}
4627 interface(REG_INTER);
4628 %}
4630 operand no_T8_mRegP() %{
4631 constraint(ALLOC_IN_RC(no_T8_p_reg));
4632 match(RegP);
4633 match(mRegP);
4635 format %{ %}
4636 interface(REG_INTER);
4637 %}
4639 operand s0_RegP()
4640 %{
4641 constraint(ALLOC_IN_RC(s0_long_reg));
4642 match(RegP);
4643 match(mRegP);
4644 match(no_T8_mRegP);
4646 format %{ %}
4647 interface(REG_INTER);
4648 %}
4650 operand s1_RegP()
4651 %{
4652 constraint(ALLOC_IN_RC(s1_long_reg));
4653 match(RegP);
4654 match(mRegP);
4655 match(no_T8_mRegP);
4657 format %{ %}
4658 interface(REG_INTER);
4659 %}
4661 operand s2_RegP()
4662 %{
4663 constraint(ALLOC_IN_RC(s2_long_reg));
4664 match(RegP);
4665 match(mRegP);
4666 match(no_T8_mRegP);
4668 format %{ %}
4669 interface(REG_INTER);
4670 %}
4672 operand s3_RegP()
4673 %{
4674 constraint(ALLOC_IN_RC(s3_long_reg));
4675 match(RegP);
4676 match(mRegP);
4677 match(no_T8_mRegP);
4679 format %{ %}
4680 interface(REG_INTER);
4681 %}
4683 operand s4_RegP()
4684 %{
4685 constraint(ALLOC_IN_RC(s4_long_reg));
4686 match(RegP);
4687 match(mRegP);
4688 match(no_T8_mRegP);
4690 format %{ %}
4691 interface(REG_INTER);
4692 %}
4694 operand s5_RegP()
4695 %{
4696 constraint(ALLOC_IN_RC(s5_long_reg));
4697 match(RegP);
4698 match(mRegP);
4699 match(no_T8_mRegP);
4701 format %{ %}
4702 interface(REG_INTER);
4703 %}
4705 operand s6_RegP()
4706 %{
4707 constraint(ALLOC_IN_RC(s6_long_reg));
4708 match(RegP);
4709 match(mRegP);
4710 match(no_T8_mRegP);
4712 format %{ %}
4713 interface(REG_INTER);
4714 %}
4716 operand s7_RegP()
4717 %{
4718 constraint(ALLOC_IN_RC(s7_long_reg));
4719 match(RegP);
4720 match(mRegP);
4721 match(no_T8_mRegP);
4723 format %{ %}
4724 interface(REG_INTER);
4725 %}
4727 operand t0_RegP()
4728 %{
4729 constraint(ALLOC_IN_RC(t0_long_reg));
4730 match(RegP);
4731 match(mRegP);
4732 match(no_T8_mRegP);
4734 format %{ %}
4735 interface(REG_INTER);
4736 %}
4738 operand t1_RegP()
4739 %{
4740 constraint(ALLOC_IN_RC(t1_long_reg));
4741 match(RegP);
4742 match(mRegP);
4743 match(no_T8_mRegP);
4745 format %{ %}
4746 interface(REG_INTER);
4747 %}
4749 operand t2_RegP()
4750 %{
4751 constraint(ALLOC_IN_RC(t2_long_reg));
4752 match(RegP);
4753 match(mRegP);
4754 match(no_T8_mRegP);
4756 format %{ %}
4757 interface(REG_INTER);
4758 %}
4760 operand t3_RegP()
4761 %{
4762 constraint(ALLOC_IN_RC(t3_long_reg));
4763 match(RegP);
4764 match(mRegP);
4765 match(no_T8_mRegP);
4767 format %{ %}
4768 interface(REG_INTER);
4769 %}
4771 operand t8_RegP()
4772 %{
4773 constraint(ALLOC_IN_RC(t8_long_reg));
4774 match(RegP);
4775 match(mRegP);
4777 format %{ %}
4778 interface(REG_INTER);
4779 %}
4781 operand t9_RegP()
4782 %{
4783 constraint(ALLOC_IN_RC(t9_long_reg));
4784 match(RegP);
4785 match(mRegP);
4786 match(no_T8_mRegP);
4788 format %{ %}
4789 interface(REG_INTER);
4790 %}
4792 operand a0_RegP()
4793 %{
4794 constraint(ALLOC_IN_RC(a0_long_reg));
4795 match(RegP);
4796 match(mRegP);
4797 match(no_T8_mRegP);
4799 format %{ %}
4800 interface(REG_INTER);
4801 %}
4803 operand a1_RegP()
4804 %{
4805 constraint(ALLOC_IN_RC(a1_long_reg));
4806 match(RegP);
4807 match(mRegP);
4808 match(no_T8_mRegP);
4810 format %{ %}
4811 interface(REG_INTER);
4812 %}
4814 operand a2_RegP()
4815 %{
4816 constraint(ALLOC_IN_RC(a2_long_reg));
4817 match(RegP);
4818 match(mRegP);
4819 match(no_T8_mRegP);
4821 format %{ %}
4822 interface(REG_INTER);
4823 %}
4825 operand a3_RegP()
4826 %{
4827 constraint(ALLOC_IN_RC(a3_long_reg));
4828 match(RegP);
4829 match(mRegP);
4830 match(no_T8_mRegP);
4832 format %{ %}
4833 interface(REG_INTER);
4834 %}
4836 operand a4_RegP()
4837 %{
4838 constraint(ALLOC_IN_RC(a4_long_reg));
4839 match(RegP);
4840 match(mRegP);
4841 match(no_T8_mRegP);
4843 format %{ %}
4844 interface(REG_INTER);
4845 %}
4848 operand a5_RegP()
4849 %{
4850 constraint(ALLOC_IN_RC(a5_long_reg));
4851 match(RegP);
4852 match(mRegP);
4853 match(no_T8_mRegP);
4855 format %{ %}
4856 interface(REG_INTER);
4857 %}
4859 operand a6_RegP()
4860 %{
4861 constraint(ALLOC_IN_RC(a6_long_reg));
4862 match(RegP);
4863 match(mRegP);
4864 match(no_T8_mRegP);
4866 format %{ %}
4867 interface(REG_INTER);
4868 %}
4870 operand a7_RegP()
4871 %{
4872 constraint(ALLOC_IN_RC(a7_long_reg));
4873 match(RegP);
4874 match(mRegP);
4875 match(no_T8_mRegP);
4877 format %{ %}
4878 interface(REG_INTER);
4879 %}
4881 operand v0_RegP()
4882 %{
4883 constraint(ALLOC_IN_RC(v0_long_reg));
4884 match(RegP);
4885 match(mRegP);
4886 match(no_T8_mRegP);
4888 format %{ %}
4889 interface(REG_INTER);
4890 %}
4892 operand v1_RegP()
4893 %{
4894 constraint(ALLOC_IN_RC(v1_long_reg));
4895 match(RegP);
4896 match(mRegP);
4897 match(no_T8_mRegP);
4899 format %{ %}
4900 interface(REG_INTER);
4901 %}
4903 /*
4904 operand mSPRegP(mRegP reg) %{
4905 constraint(ALLOC_IN_RC(sp_reg));
4906 match(reg);
4908 format %{ "SP" %}
4909 interface(REG_INTER);
4910 %}
4912 operand mFPRegP(mRegP reg) %{
4913 constraint(ALLOC_IN_RC(fp_reg));
4914 match(reg);
4916 format %{ "FP" %}
4917 interface(REG_INTER);
4918 %}
4919 */
4921 operand mRegL() %{
4922 constraint(ALLOC_IN_RC(long_reg));
4923 match(RegL);
4925 format %{ %}
4926 interface(REG_INTER);
4927 %}
4929 operand v0RegL() %{
4930 constraint(ALLOC_IN_RC(v0_long_reg));
4931 match(RegL);
4932 match(mRegL);
4934 format %{ %}
4935 interface(REG_INTER);
4936 %}
4938 operand v1RegL() %{
4939 constraint(ALLOC_IN_RC(v1_long_reg));
4940 match(RegL);
4941 match(mRegL);
4943 format %{ %}
4944 interface(REG_INTER);
4945 %}
4947 operand a0RegL() %{
4948 constraint(ALLOC_IN_RC(a0_long_reg));
4949 match(RegL);
4950 match(mRegL);
4952 format %{ "A0" %}
4953 interface(REG_INTER);
4954 %}
4956 operand a1RegL() %{
4957 constraint(ALLOC_IN_RC(a1_long_reg));
4958 match(RegL);
4959 match(mRegL);
4961 format %{ %}
4962 interface(REG_INTER);
4963 %}
4965 operand a2RegL() %{
4966 constraint(ALLOC_IN_RC(a2_long_reg));
4967 match(RegL);
4968 match(mRegL);
4970 format %{ %}
4971 interface(REG_INTER);
4972 %}
4974 operand a3RegL() %{
4975 constraint(ALLOC_IN_RC(a3_long_reg));
4976 match(RegL);
4977 match(mRegL);
4979 format %{ %}
4980 interface(REG_INTER);
4981 %}
4983 operand t0RegL() %{
4984 constraint(ALLOC_IN_RC(t0_long_reg));
4985 match(RegL);
4986 match(mRegL);
4988 format %{ %}
4989 interface(REG_INTER);
4990 %}
4992 operand t1RegL() %{
4993 constraint(ALLOC_IN_RC(t1_long_reg));
4994 match(RegL);
4995 match(mRegL);
4997 format %{ %}
4998 interface(REG_INTER);
4999 %}
5001 operand t2RegL() %{
5002 constraint(ALLOC_IN_RC(t2_long_reg));
5003 match(RegL);
5004 match(mRegL);
5006 format %{ %}
5007 interface(REG_INTER);
5008 %}
5010 operand t3RegL() %{
5011 constraint(ALLOC_IN_RC(t3_long_reg));
5012 match(RegL);
5013 match(mRegL);
5015 format %{ %}
5016 interface(REG_INTER);
5017 %}
5019 operand t8RegL() %{
5020 constraint(ALLOC_IN_RC(t8_long_reg));
5021 match(RegL);
5022 match(mRegL);
5024 format %{ %}
5025 interface(REG_INTER);
5026 %}
5028 operand a4RegL() %{
5029 constraint(ALLOC_IN_RC(a4_long_reg));
5030 match(RegL);
5031 match(mRegL);
5033 format %{ %}
5034 interface(REG_INTER);
5035 %}
5037 operand a5RegL() %{
5038 constraint(ALLOC_IN_RC(a5_long_reg));
5039 match(RegL);
5040 match(mRegL);
5042 format %{ %}
5043 interface(REG_INTER);
5044 %}
5046 operand a6RegL() %{
5047 constraint(ALLOC_IN_RC(a6_long_reg));
5048 match(RegL);
5049 match(mRegL);
5051 format %{ %}
5052 interface(REG_INTER);
5053 %}
5055 operand a7RegL() %{
5056 constraint(ALLOC_IN_RC(a7_long_reg));
5057 match(RegL);
5058 match(mRegL);
5060 format %{ %}
5061 interface(REG_INTER);
5062 %}
5064 operand s0RegL() %{
5065 constraint(ALLOC_IN_RC(s0_long_reg));
5066 match(RegL);
5067 match(mRegL);
5069 format %{ %}
5070 interface(REG_INTER);
5071 %}
5073 operand s1RegL() %{
5074 constraint(ALLOC_IN_RC(s1_long_reg));
5075 match(RegL);
5076 match(mRegL);
5078 format %{ %}
5079 interface(REG_INTER);
5080 %}
5082 operand s2RegL() %{
5083 constraint(ALLOC_IN_RC(s2_long_reg));
5084 match(RegL);
5085 match(mRegL);
5087 format %{ %}
5088 interface(REG_INTER);
5089 %}
5091 operand s3RegL() %{
5092 constraint(ALLOC_IN_RC(s3_long_reg));
5093 match(RegL);
5094 match(mRegL);
5096 format %{ %}
5097 interface(REG_INTER);
5098 %}
5100 operand s4RegL() %{
5101 constraint(ALLOC_IN_RC(s4_long_reg));
5102 match(RegL);
5103 match(mRegL);
5105 format %{ %}
5106 interface(REG_INTER);
5107 %}
5109 operand s7RegL() %{
5110 constraint(ALLOC_IN_RC(s7_long_reg));
5111 match(RegL);
5112 match(mRegL);
5114 format %{ %}
5115 interface(REG_INTER);
5116 %}
5118 // Floating register operands
5119 operand regF() %{
5120 constraint(ALLOC_IN_RC(flt_reg));
5121 match(RegF);
5123 format %{ %}
5124 interface(REG_INTER);
5125 %}
5127 //Double Precision Floating register operands
5128 operand regD() %{
5129 constraint(ALLOC_IN_RC(dbl_reg));
5130 match(RegD);
5132 format %{ %}
5133 interface(REG_INTER);
5134 %}
5136 //----------Memory Operands----------------------------------------------------
5137 // Indirect Memory Operand
5138 operand indirect(mRegP reg) %{
5139 constraint(ALLOC_IN_RC(p_reg));
5140 match(reg);
5142 format %{ "[$reg] @ indirect" %}
5143 interface(MEMORY_INTER) %{
5144 base($reg);
5145 index(0x0); /* NO_INDEX */
5146 scale(0x0);
5147 disp(0x0);
5148 %}
5149 %}
5151 // Indirect Memory Plus Short Offset Operand
5152 operand indOffset8(mRegP reg, immL8 off)
5153 %{
5154 constraint(ALLOC_IN_RC(p_reg));
5155 match(AddP reg off);
5157 op_cost(10);
5158 format %{ "[$reg + $off (8-bit)] @ indOffset8" %}
5159 interface(MEMORY_INTER) %{
5160 base($reg);
5161 index(0x0); /* NO_INDEX */
5162 scale(0x0);
5163 disp($off);
5164 %}
5165 %}
5167 // Indirect Memory Times Scale Plus Index Register
5168 operand indIndexScale(mRegP reg, mRegL lreg, immI2 scale)
5169 %{
5170 constraint(ALLOC_IN_RC(p_reg));
5171 match(AddP reg (LShiftL lreg scale));
5173 op_cost(10);
5174 format %{"[$reg + $lreg << $scale] @ indIndexScale" %}
5175 interface(MEMORY_INTER) %{
5176 base($reg);
5177 index($lreg);
5178 scale($scale);
5179 disp(0x0);
5180 %}
5181 %}
5184 // [base + index + offset]
5185 operand baseIndexOffset8(mRegP base, mRegL index, immL8 off)
5186 %{
5187 constraint(ALLOC_IN_RC(p_reg));
5188 op_cost(5);
5189 match(AddP (AddP base index) off);
5191 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8" %}
5192 interface(MEMORY_INTER) %{
5193 base($base);
5194 index($index);
5195 scale(0x0);
5196 disp($off);
5197 %}
5198 %}
5200 // [base + index + offset]
5201 operand baseIndexOffset8_convI2L(mRegP base, mRegI index, immL8 off)
5202 %{
5203 constraint(ALLOC_IN_RC(p_reg));
5204 op_cost(5);
5205 match(AddP (AddP base (ConvI2L index)) off);
5207 format %{ "[$base + $index + $off (8-bit)] @ baseIndexOffset8_convI2L" %}
5208 interface(MEMORY_INTER) %{
5209 base($base);
5210 index($index);
5211 scale(0x0);
5212 disp($off);
5213 %}
5214 %}
5216 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5217 operand indIndexScaleOffset8(mRegP reg, immL8 off, mRegL lreg, immI2 scale)
5218 %{
5219 constraint(ALLOC_IN_RC(p_reg));
5220 match(AddP (AddP reg (LShiftL lreg scale)) off);
5222 op_cost(10);
5223 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffset8" %}
5224 interface(MEMORY_INTER) %{
5225 base($reg);
5226 index($lreg);
5227 scale($scale);
5228 disp($off);
5229 %}
5230 %}
5232 operand indIndexScaleOffset8_convI2L(mRegP reg, immL8 off, mRegI ireg, immI2 scale)
5233 %{
5234 constraint(ALLOC_IN_RC(p_reg));
5235 match(AddP (AddP reg (LShiftL (ConvI2L ireg) scale)) off);
5237 op_cost(10);
5238 format %{"[$reg + $off + $ireg << $scale] @ indIndexScaleOffset8_convI2L" %}
5239 interface(MEMORY_INTER) %{
5240 base($reg);
5241 index($ireg);
5242 scale($scale);
5243 disp($off);
5244 %}
5245 %}
5247 // [base + index<<scale + offset]
5248 operand basePosIndexScaleOffset8(mRegP base, mRegI index, immL8 off, immI_0_31 scale)
5249 %{
5250 constraint(ALLOC_IN_RC(p_reg));
5251 //predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5252 op_cost(10);
5253 match(AddP (AddP base (LShiftL (ConvI2L index) scale)) off);
5255 format %{ "[$base + $index << $scale + $off (8-bit)] @ basePosIndexScaleOffset8" %}
5256 interface(MEMORY_INTER) %{
5257 base($base);
5258 index($index);
5259 scale($scale);
5260 disp($off);
5261 %}
5262 %}
5264 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5265 operand indIndexScaleOffsetNarrow(mRegN reg, immL8 off, mRegL lreg, immI2 scale)
5266 %{
5267 predicate(Universe::narrow_oop_shift() == 0);
5268 constraint(ALLOC_IN_RC(p_reg));
5269 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
5271 op_cost(10);
5272 format %{"[$reg + $off + $lreg << $scale] @ indIndexScaleOffsetNarrow" %}
5273 interface(MEMORY_INTER) %{
5274 base($reg);
5275 index($lreg);
5276 scale($scale);
5277 disp($off);
5278 %}
5279 %}
5281 // [base + index<<scale + offset] for compressd Oops
5282 operand indPosIndexI2LScaleOffset8Narrow(mRegN base, mRegI index, immL8 off, immI_0_31 scale)
5283 %{
5284 constraint(ALLOC_IN_RC(p_reg));
5285 //predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5286 predicate(Universe::narrow_oop_shift() == 0);
5287 op_cost(10);
5288 match(AddP (AddP (DecodeN base) (LShiftL (ConvI2L index) scale)) off);
5290 format %{ "[$base + $index << $scale + $off (8-bit)] @ indPosIndexI2LScaleOffset8Narrow" %}
5291 interface(MEMORY_INTER) %{
5292 base($base);
5293 index($index);
5294 scale($scale);
5295 disp($off);
5296 %}
5297 %}
5299 //FIXME: I think it's better to limit the immI to be 16-bit at most!
5300 // Indirect Memory Plus Long Offset Operand
5301 operand indOffset32(mRegP reg, immL32 off) %{
5302 constraint(ALLOC_IN_RC(p_reg));
5303 op_cost(20);
5304 match(AddP reg off);
5306 format %{ "[$reg + $off (32-bit)] @ indOffset32" %}
5307 interface(MEMORY_INTER) %{
5308 base($reg);
5309 index(0x0); /* NO_INDEX */
5310 scale(0x0);
5311 disp($off);
5312 %}
5313 %}
5315 // Indirect Memory Plus Index Register
5316 operand indIndex(mRegP addr, mRegL index) %{
5317 constraint(ALLOC_IN_RC(p_reg));
5318 match(AddP addr index);
5320 op_cost(20);
5321 format %{"[$addr + $index] @ indIndex" %}
5322 interface(MEMORY_INTER) %{
5323 base($addr);
5324 index($index);
5325 scale(0x0);
5326 disp(0x0);
5327 %}
5328 %}
5330 operand indirectNarrowKlass(mRegN reg)
5331 %{
5332 predicate(Universe::narrow_klass_shift() == 0);
5333 constraint(ALLOC_IN_RC(p_reg));
5334 op_cost(10);
5335 match(DecodeNKlass reg);
5337 format %{ "[$reg] @ indirectNarrowKlass" %}
5338 interface(MEMORY_INTER) %{
5339 base($reg);
5340 index(0x0);
5341 scale(0x0);
5342 disp(0x0);
5343 %}
5344 %}
5346 operand indOffset8NarrowKlass(mRegN reg, immL8 off)
5347 %{
5348 predicate(Universe::narrow_klass_shift() == 0);
5349 constraint(ALLOC_IN_RC(p_reg));
5350 op_cost(10);
5351 match(AddP (DecodeNKlass reg) off);
5353 format %{ "[$reg + $off (8-bit)] @ indOffset8NarrowKlass" %}
5354 interface(MEMORY_INTER) %{
5355 base($reg);
5356 index(0x0);
5357 scale(0x0);
5358 disp($off);
5359 %}
5360 %}
5362 operand indOffset32NarrowKlass(mRegN reg, immL32 off)
5363 %{
5364 predicate(Universe::narrow_klass_shift() == 0);
5365 constraint(ALLOC_IN_RC(p_reg));
5366 op_cost(10);
5367 match(AddP (DecodeNKlass reg) off);
5369 format %{ "[$reg + $off (32-bit)] @ indOffset32NarrowKlass" %}
5370 interface(MEMORY_INTER) %{
5371 base($reg);
5372 index(0x0);
5373 scale(0x0);
5374 disp($off);
5375 %}
5376 %}
5378 operand indIndexOffsetNarrowKlass(mRegN reg, mRegL lreg, immL32 off)
5379 %{
5380 predicate(Universe::narrow_klass_shift() == 0);
5381 constraint(ALLOC_IN_RC(p_reg));
5382 match(AddP (AddP (DecodeNKlass reg) lreg) off);
5384 op_cost(10);
5385 format %{"[$reg + $off + $lreg] @ indIndexOffsetNarrowKlass" %}
5386 interface(MEMORY_INTER) %{
5387 base($reg);
5388 index($lreg);
5389 scale(0x0);
5390 disp($off);
5391 %}
5392 %}
5394 operand indIndexNarrowKlass(mRegN reg, mRegL lreg)
5395 %{
5396 predicate(Universe::narrow_klass_shift() == 0);
5397 constraint(ALLOC_IN_RC(p_reg));
5398 match(AddP (DecodeNKlass reg) lreg);
5400 op_cost(10);
5401 format %{"[$reg + $lreg] @ indIndexNarrowKlass" %}
5402 interface(MEMORY_INTER) %{
5403 base($reg);
5404 index($lreg);
5405 scale(0x0);
5406 disp(0x0);
5407 %}
5408 %}
5410 // Indirect Memory Operand
5411 operand indirectNarrow(mRegN reg)
5412 %{
5413 predicate(Universe::narrow_oop_shift() == 0);
5414 constraint(ALLOC_IN_RC(p_reg));
5415 op_cost(10);
5416 match(DecodeN reg);
5418 format %{ "[$reg] @ indirectNarrow" %}
5419 interface(MEMORY_INTER) %{
5420 base($reg);
5421 index(0x0);
5422 scale(0x0);
5423 disp(0x0);
5424 %}
5425 %}
5427 // Indirect Memory Plus Short Offset Operand
5428 operand indOffset8Narrow(mRegN reg, immL8 off)
5429 %{
5430 predicate(Universe::narrow_oop_shift() == 0);
5431 constraint(ALLOC_IN_RC(p_reg));
5432 op_cost(10);
5433 match(AddP (DecodeN reg) off);
5435 format %{ "[$reg + $off (8-bit)] @ indOffset8Narrow" %}
5436 interface(MEMORY_INTER) %{
5437 base($reg);
5438 index(0x0);
5439 scale(0x0);
5440 disp($off);
5441 %}
5442 %}
5444 // Indirect Memory Plus Index Register Plus Offset Operand
5445 operand indIndexOffset8Narrow(mRegN reg, mRegL lreg, immL8 off)
5446 %{
5447 predicate(Universe::narrow_oop_shift() == 0);
5448 constraint(ALLOC_IN_RC(p_reg));
5449 match(AddP (AddP (DecodeN reg) lreg) off);
5451 op_cost(10);
5452 format %{"[$reg + $off + $lreg] @ indIndexOffset8Narrow" %}
5453 interface(MEMORY_INTER) %{
5454 base($reg);
5455 index($lreg);
5456 scale(0x0);
5457 disp($off);
5458 %}
5459 %}
5461 //----------Load Long Memory Operands------------------------------------------
5462 // The load-long idiom will use it's address expression again after loading
5463 // the first word of the long. If the load-long destination overlaps with
5464 // registers used in the addressing expression, the 2nd half will be loaded
5465 // from a clobbered address. Fix this by requiring that load-long use
5466 // address registers that do not overlap with the load-long target.
5468 // load-long support
5469 operand load_long_RegP() %{
5470 constraint(ALLOC_IN_RC(p_reg));
5471 match(RegP);
5472 match(mRegP);
5473 op_cost(100);
5474 format %{ %}
5475 interface(REG_INTER);
5476 %}
5478 // Indirect Memory Operand Long
5479 operand load_long_indirect(load_long_RegP reg) %{
5480 constraint(ALLOC_IN_RC(p_reg));
5481 match(reg);
5483 format %{ "[$reg]" %}
5484 interface(MEMORY_INTER) %{
5485 base($reg);
5486 index(0x0);
5487 scale(0x0);
5488 disp(0x0);
5489 %}
5490 %}
5492 // Indirect Memory Plus Long Offset Operand
5493 operand load_long_indOffset32(load_long_RegP reg, immL32 off) %{
5494 match(AddP reg off);
5496 format %{ "[$reg + $off]" %}
5497 interface(MEMORY_INTER) %{
5498 base($reg);
5499 index(0x0);
5500 scale(0x0);
5501 disp($off);
5502 %}
5503 %}
5505 //----------Conditional Branch Operands----------------------------------------
5506 // Comparison Op - This is the operation of the comparison, and is limited to
5507 // the following set of codes:
5508 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5509 //
5510 // Other attributes of the comparison, such as unsignedness, are specified
5511 // by the comparison instruction that sets a condition code flags register.
5512 // That result is represented by a flags operand whose subtype is appropriate
5513 // to the unsignedness (etc.) of the comparison.
5514 //
5515 // Later, the instruction which matches both the Comparison Op (a Bool) and
5516 // the flags (produced by the Cmp) specifies the coding of the comparison op
5517 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5519 // Comparision Code
5520 operand cmpOp() %{
5521 match(Bool);
5523 format %{ "" %}
5524 interface(COND_INTER) %{
5525 equal(0x01);
5526 not_equal(0x02);
5527 greater(0x03);
5528 greater_equal(0x04);
5529 less(0x05);
5530 less_equal(0x06);
5531 overflow(0x7);
5532 no_overflow(0x8);
5533 %}
5534 %}
5537 // Comparision Code
5538 // Comparison Code, unsigned compare. Used by FP also, with
5539 // C2 (unordered) turned into GT or LT already. The other bits
5540 // C0 and C3 are turned into Carry & Zero flags.
5541 operand cmpOpU() %{
5542 match(Bool);
5544 format %{ "" %}
5545 interface(COND_INTER) %{
5546 equal(0x01);
5547 not_equal(0x02);
5548 greater(0x03);
5549 greater_equal(0x04);
5550 less(0x05);
5551 less_equal(0x06);
5552 overflow(0x7);
5553 no_overflow(0x8);
5554 %}
5555 %}
5557 /*
5558 // Comparison Code, unsigned compare. Used by FP also, with
5559 // C2 (unordered) turned into GT or LT already. The other bits
5560 // C0 and C3 are turned into Carry & Zero flags.
5561 operand cmpOpU() %{
5562 match(Bool);
5564 format %{ "" %}
5565 interface(COND_INTER) %{
5566 equal(0x4);
5567 not_equal(0x5);
5568 less(0x2);
5569 greater_equal(0x3);
5570 less_equal(0x6);
5571 greater(0x7);
5572 %}
5573 %}
5574 */
5575 /*
5576 // Comparison Code for FP conditional move
5577 operand cmpOp_fcmov() %{
5578 match(Bool);
5580 format %{ "" %}
5581 interface(COND_INTER) %{
5582 equal (0x01);
5583 not_equal (0x02);
5584 greater (0x03);
5585 greater_equal(0x04);
5586 less (0x05);
5587 less_equal (0x06);
5588 %}
5589 %}
5591 // Comparision Code used in long compares
5592 operand cmpOp_commute() %{
5593 match(Bool);
5595 format %{ "" %}
5596 interface(COND_INTER) %{
5597 equal(0x4);
5598 not_equal(0x5);
5599 less(0xF);
5600 greater_equal(0xE);
5601 less_equal(0xD);
5602 greater(0xC);
5603 %}
5604 %}
5605 */
5607 //----------Special Memory Operands--------------------------------------------
5608 // Stack Slot Operand - This operand is used for loading and storing temporary
5609 // values on the stack where a match requires a value to
5610 // flow through memory.
5611 operand stackSlotP(sRegP reg) %{
5612 constraint(ALLOC_IN_RC(stack_slots));
5613 // No match rule because this operand is only generated in matching
5614 op_cost(50);
5615 format %{ "[$reg]" %}
5616 interface(MEMORY_INTER) %{
5617 base(0x1d); // SP
5618 index(0x0); // No Index
5619 scale(0x0); // No Scale
5620 disp($reg); // Stack Offset
5621 %}
5622 %}
5624 operand stackSlotI(sRegI reg) %{
5625 constraint(ALLOC_IN_RC(stack_slots));
5626 // No match rule because this operand is only generated in matching
5627 op_cost(50);
5628 format %{ "[$reg]" %}
5629 interface(MEMORY_INTER) %{
5630 base(0x1d); // SP
5631 index(0x0); // No Index
5632 scale(0x0); // No Scale
5633 disp($reg); // Stack Offset
5634 %}
5635 %}
5637 operand stackSlotF(sRegF reg) %{
5638 constraint(ALLOC_IN_RC(stack_slots));
5639 // No match rule because this operand is only generated in matching
5640 op_cost(50);
5641 format %{ "[$reg]" %}
5642 interface(MEMORY_INTER) %{
5643 base(0x1d); // SP
5644 index(0x0); // No Index
5645 scale(0x0); // No Scale
5646 disp($reg); // Stack Offset
5647 %}
5648 %}
5650 operand stackSlotD(sRegD reg) %{
5651 constraint(ALLOC_IN_RC(stack_slots));
5652 // No match rule because this operand is only generated in matching
5653 op_cost(50);
5654 format %{ "[$reg]" %}
5655 interface(MEMORY_INTER) %{
5656 base(0x1d); // SP
5657 index(0x0); // No Index
5658 scale(0x0); // No Scale
5659 disp($reg); // Stack Offset
5660 %}
5661 %}
5663 operand stackSlotL(sRegL reg) %{
5664 constraint(ALLOC_IN_RC(stack_slots));
5665 // No match rule because this operand is only generated in matching
5666 op_cost(50);
5667 format %{ "[$reg]" %}
5668 interface(MEMORY_INTER) %{
5669 base(0x1d); // SP
5670 index(0x0); // No Index
5671 scale(0x0); // No Scale
5672 disp($reg); // Stack Offset
5673 %}
5674 %}
5677 //------------------------OPERAND CLASSES--------------------------------------
5678 //opclass memory( direct, indirect, indOffset16, indOffset32, indOffset32X, indIndexOffset );
5679 opclass memory( indirect, indirectNarrow, indOffset8, indOffset32, indIndex, indIndexScale, load_long_indirect, load_long_indOffset32, baseIndexOffset8, baseIndexOffset8_convI2L, indIndexScaleOffset8, indIndexScaleOffset8_convI2L, basePosIndexScaleOffset8, indIndexScaleOffsetNarrow, indPosIndexI2LScaleOffset8Narrow, indOffset8Narrow, indIndexOffset8Narrow);
5682 //----------PIPELINE-----------------------------------------------------------
5683 // Rules which define the behavior of the target architectures pipeline.
5685 pipeline %{
5687 //----------ATTRIBUTES---------------------------------------------------------
5688 attributes %{
5689 fixed_size_instructions; // Fixed size instructions
5690 branch_has_delay_slot; // branch have delay slot in gs2
5691 max_instructions_per_bundle = 1; // 1 instruction per bundle
5692 max_bundles_per_cycle = 4; // Up to 4 bundles per cycle
5693 bundle_unit_size=4;
5694 instruction_unit_size = 4; // An instruction is 4 bytes long
5695 instruction_fetch_unit_size = 16; // The processor fetches one line
5696 instruction_fetch_units = 1; // of 16 bytes
5698 // List of nop instructions
5699 nops( MachNop );
5700 %}
5702 //----------RESOURCES----------------------------------------------------------
5703 // Resources are the functional units available to the machine
5705 resources(D1, D2, D3, D4, DECODE = D1 | D2 | D3| D4, ALU1, ALU2, ALU = ALU1 | ALU2, FPU1, FPU2, FPU = FPU1 | FPU2, MEM, BR);
5707 //----------PIPELINE DESCRIPTION-----------------------------------------------
5708 // Pipeline Description specifies the stages in the machine's pipeline
5710 // IF: fetch
5711 // ID: decode
5712 // RD: read
5713 // CA: caculate
5714 // WB: write back
5715 // CM: commit
5717 pipe_desc(IF, ID, RD, CA, WB, CM);
5720 //----------PIPELINE CLASSES---------------------------------------------------
5721 // Pipeline Classes describe the stages in which input and output are
5722 // referenced by the hardware pipeline.
5724 //No.1 Integer ALU reg-reg operation : dst <-- reg1 op reg2
5725 pipe_class ialu_regI_regI(mRegI dst, mRegI src1, mRegI src2) %{
5726 single_instruction;
5727 src1 : RD(read);
5728 src2 : RD(read);
5729 dst : WB(write)+1;
5730 DECODE : ID;
5731 ALU : CA;
5732 %}
5734 //No.19 Integer mult operation : dst <-- reg1 mult reg2
5735 pipe_class ialu_mult(mRegI dst, mRegI src1, mRegI src2) %{
5736 src1 : RD(read);
5737 src2 : RD(read);
5738 dst : WB(write)+5;
5739 DECODE : ID;
5740 ALU2 : CA;
5741 %}
5743 pipe_class mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
5744 src1 : RD(read);
5745 src2 : RD(read);
5746 dst : WB(write)+10;
5747 DECODE : ID;
5748 ALU2 : CA;
5749 %}
5751 //No.19 Integer div operation : dst <-- reg1 div reg2
5752 pipe_class ialu_div(mRegI dst, mRegI src1, mRegI src2) %{
5753 src1 : RD(read);
5754 src2 : RD(read);
5755 dst : WB(write)+10;
5756 DECODE : ID;
5757 ALU2 : CA;
5758 %}
5760 //No.19 Integer mod operation : dst <-- reg1 mod reg2
5761 pipe_class ialu_mod(mRegI dst, mRegI src1, mRegI src2) %{
5762 instruction_count(2);
5763 src1 : RD(read);
5764 src2 : RD(read);
5765 dst : WB(write)+10;
5766 DECODE : ID;
5767 ALU2 : CA;
5768 %}
5770 //No.15 Long ALU reg-reg operation : dst <-- reg1 op reg2
5771 pipe_class ialu_regL_regL(mRegL dst, mRegL src1, mRegL src2) %{
5772 instruction_count(2);
5773 src1 : RD(read);
5774 src2 : RD(read);
5775 dst : WB(write);
5776 DECODE : ID;
5777 ALU : CA;
5778 %}
5780 //No.18 Long ALU reg-imm16 operation : dst <-- reg1 op imm16
5781 pipe_class ialu_regL_imm16(mRegL dst, mRegL src) %{
5782 instruction_count(2);
5783 src : RD(read);
5784 dst : WB(write);
5785 DECODE : ID;
5786 ALU : CA;
5787 %}
5789 //no.16 load Long from memory :
5790 pipe_class ialu_loadL(mRegL dst, memory mem) %{
5791 instruction_count(2);
5792 mem : RD(read);
5793 dst : WB(write)+5;
5794 DECODE : ID;
5795 MEM : RD;
5796 %}
5798 //No.17 Store Long to Memory :
5799 pipe_class ialu_storeL(mRegL src, memory mem) %{
5800 instruction_count(2);
5801 mem : RD(read);
5802 src : RD(read);
5803 DECODE : ID;
5804 MEM : RD;
5805 %}
5807 //No.2 Integer ALU reg-imm16 operation : dst <-- reg1 op imm16
5808 pipe_class ialu_regI_imm16(mRegI dst, mRegI src) %{
5809 single_instruction;
5810 src : RD(read);
5811 dst : WB(write);
5812 DECODE : ID;
5813 ALU : CA;
5814 %}
5816 //No.3 Integer move operation : dst <-- reg
5817 pipe_class ialu_regI_mov(mRegI dst, mRegI src) %{
5818 src : RD(read);
5819 dst : WB(write);
5820 DECODE : ID;
5821 ALU : CA;
5822 %}
5824 //No.4 No instructions : do nothing
5825 pipe_class empty( ) %{
5826 instruction_count(0);
5827 %}
5829 //No.5 UnConditional branch :
5830 pipe_class pipe_jump( label labl ) %{
5831 multiple_bundles;
5832 DECODE : ID;
5833 BR : RD;
5834 %}
5836 //No.6 ALU Conditional branch :
5837 pipe_class pipe_alu_branch(mRegI src1, mRegI src2, label labl ) %{
5838 multiple_bundles;
5839 src1 : RD(read);
5840 src2 : RD(read);
5841 DECODE : ID;
5842 BR : RD;
5843 %}
5845 //no.7 load integer from memory :
5846 pipe_class ialu_loadI(mRegI dst, memory mem) %{
5847 mem : RD(read);
5848 dst : WB(write)+3;
5849 DECODE : ID;
5850 MEM : RD;
5851 %}
5853 //No.8 Store Integer to Memory :
5854 pipe_class ialu_storeI(mRegI src, memory mem) %{
5855 mem : RD(read);
5856 src : RD(read);
5857 DECODE : ID;
5858 MEM : RD;
5859 %}
5862 //No.10 Floating FPU reg-reg operation : dst <-- reg1 op reg2
5863 pipe_class fpu_regF_regF(regF dst, regF src1, regF src2) %{
5864 src1 : RD(read);
5865 src2 : RD(read);
5866 dst : WB(write);
5867 DECODE : ID;
5868 FPU : CA;
5869 %}
5871 //No.22 Floating div operation : dst <-- reg1 div reg2
5872 pipe_class fpu_div(regF dst, regF src1, regF src2) %{
5873 src1 : RD(read);
5874 src2 : RD(read);
5875 dst : WB(write);
5876 DECODE : ID;
5877 FPU2 : CA;
5878 %}
5880 pipe_class fcvt_I2D(regD dst, mRegI src) %{
5881 src : RD(read);
5882 dst : WB(write);
5883 DECODE : ID;
5884 FPU1 : CA;
5885 %}
5887 pipe_class fcvt_D2I(mRegI dst, regD src) %{
5888 src : RD(read);
5889 dst : WB(write);
5890 DECODE : ID;
5891 FPU1 : CA;
5892 %}
5894 pipe_class pipe_mfc1(mRegI dst, regD src) %{
5895 src : RD(read);
5896 dst : WB(write);
5897 DECODE : ID;
5898 MEM : RD;
5899 %}
5901 pipe_class pipe_mtc1(regD dst, mRegI src) %{
5902 src : RD(read);
5903 dst : WB(write);
5904 DECODE : ID;
5905 MEM : RD(5);
5906 %}
5908 //No.23 Floating sqrt operation : dst <-- reg1 sqrt reg2
5909 pipe_class fpu_sqrt(regF dst, regF src1, regF src2) %{
5910 multiple_bundles;
5911 src1 : RD(read);
5912 src2 : RD(read);
5913 dst : WB(write);
5914 DECODE : ID;
5915 FPU2 : CA;
5916 %}
5918 //No.11 Load Floating from Memory :
5919 pipe_class fpu_loadF(regF dst, memory mem) %{
5920 instruction_count(1);
5921 mem : RD(read);
5922 dst : WB(write)+3;
5923 DECODE : ID;
5924 MEM : RD;
5925 %}
5927 //No.12 Store Floating to Memory :
5928 pipe_class fpu_storeF(regF src, memory mem) %{
5929 instruction_count(1);
5930 mem : RD(read);
5931 src : RD(read);
5932 DECODE : ID;
5933 MEM : RD;
5934 %}
5936 //No.13 FPU Conditional branch :
5937 pipe_class pipe_fpu_branch(regF src1, regF src2, label labl ) %{
5938 multiple_bundles;
5939 src1 : RD(read);
5940 src2 : RD(read);
5941 DECODE : ID;
5942 BR : RD;
5943 %}
5945 //No.14 Floating FPU reg operation : dst <-- op reg
5946 pipe_class fpu1_regF(regF dst, regF src) %{
5947 src : RD(read);
5948 dst : WB(write);
5949 DECODE : ID;
5950 FPU : CA;
5951 %}
5953 pipe_class long_memory_op() %{
5954 instruction_count(10); multiple_bundles; force_serialization;
5955 fixed_latency(30);
5956 %}
5958 pipe_class simple_call() %{
5959 instruction_count(10); multiple_bundles; force_serialization;
5960 fixed_latency(200);
5961 BR : RD;
5962 %}
5964 pipe_class call() %{
5965 instruction_count(10); multiple_bundles; force_serialization;
5966 fixed_latency(200);
5967 %}
5969 //FIXME:
5970 //No.9 Piple slow : for multi-instructions
5971 pipe_class pipe_slow( ) %{
5972 instruction_count(20);
5973 force_serialization;
5974 multiple_bundles;
5975 fixed_latency(50);
5976 %}
5978 %}
5982 //----------INSTRUCTIONS-------------------------------------------------------
5983 //
5984 // match -- States which machine-independent subtree may be replaced
5985 // by this instruction.
5986 // ins_cost -- The estimated cost of this instruction is used by instruction
5987 // selection to identify a minimum cost tree of machine
5988 // instructions that matches a tree of machine-independent
5989 // instructions.
5990 // format -- A string providing the disassembly for this instruction.
5991 // The value of an instruction's operand may be inserted
5992 // by referring to it with a '$' prefix.
5993 // opcode -- Three instruction opcodes may be provided. These are referred
5994 // to within an encode class as $primary, $secondary, and $tertiary
5995 // respectively. The primary opcode is commonly used to
5996 // indicate the type of machine instruction, while secondary
5997 // and tertiary are often used for prefix options or addressing
5998 // modes.
5999 // ins_encode -- A list of encode classes with parameters. The encode class
6000 // name must have been defined in an 'enc_class' specification
6001 // in the encode section of the architecture description.
6004 // Load Integer
6005 instruct loadI(mRegI dst, memory mem) %{
6006 match(Set dst (LoadI mem));
6008 ins_cost(125);
6009 format %{ "lw $dst, $mem #@loadI" %}
6010 ins_encode (load_I_enc(dst, mem));
6011 ins_pipe( ialu_loadI );
6012 %}
6014 instruct loadI_convI2L(mRegL dst, memory mem) %{
6015 match(Set dst (ConvI2L (LoadI mem)));
6017 ins_cost(125);
6018 format %{ "lw $dst, $mem #@loadI_convI2L" %}
6019 ins_encode (load_I_enc(dst, mem));
6020 ins_pipe( ialu_loadI );
6021 %}
6023 // Load Integer (32 bit signed) to Byte (8 bit signed)
6024 instruct loadI2B(mRegI dst, memory mem, immI_24 twentyfour) %{
6025 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6027 ins_cost(125);
6028 format %{ "lb $dst, $mem\t# int -> byte #@loadI2B" %}
6029 ins_encode(load_B_enc(dst, mem));
6030 ins_pipe(ialu_loadI);
6031 %}
6033 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6034 instruct loadI2UB(mRegI dst, memory mem, immI_255 mask) %{
6035 match(Set dst (AndI (LoadI mem) mask));
6037 ins_cost(125);
6038 format %{ "lbu $dst, $mem\t# int -> ubyte #@loadI2UB" %}
6039 ins_encode(load_UB_enc(dst, mem));
6040 ins_pipe(ialu_loadI);
6041 %}
6043 // Load Integer (32 bit signed) to Short (16 bit signed)
6044 instruct loadI2S(mRegI dst, memory mem, immI_16 sixteen) %{
6045 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6047 ins_cost(125);
6048 format %{ "lh $dst, $mem\t# int -> short #@loadI2S" %}
6049 ins_encode(load_S_enc(dst, mem));
6050 ins_pipe(ialu_loadI);
6051 %}
6053 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6054 instruct loadI2US(mRegI dst, memory mem, immI_65535 mask) %{
6055 match(Set dst (AndI (LoadI mem) mask));
6057 ins_cost(125);
6058 format %{ "lhu $dst, $mem\t# int -> ushort/char #@loadI2US" %}
6059 ins_encode(load_C_enc(dst, mem));
6060 ins_pipe(ialu_loadI);
6061 %}
6063 // Load Long.
6064 instruct loadL(mRegL dst, memory mem) %{
6065 // predicate(!((LoadLNode*)n)->require_atomic_access());
6066 match(Set dst (LoadL mem));
6068 ins_cost(250);
6069 format %{ "ld $dst, $mem #@loadL" %}
6070 ins_encode(load_L_enc(dst, mem));
6071 ins_pipe( ialu_loadL );
6072 %}
6074 // Load Long - UNaligned
6075 instruct loadL_unaligned(mRegL dst, memory mem) %{
6076 match(Set dst (LoadL_unaligned mem));
6078 // FIXME: Jin: Need more effective ldl/ldr
6079 ins_cost(450);
6080 format %{ "ld $dst, $mem #@loadL_unaligned\n\t" %}
6081 ins_encode(load_L_enc(dst, mem));
6082 ins_pipe( ialu_loadL );
6083 %}
6085 // Store Long
6086 instruct storeL_reg(memory mem, mRegL src) %{
6087 match(Set mem (StoreL mem src));
6089 ins_cost(200);
6090 format %{ "sd $mem, $src #@storeL_reg\n" %}
6091 ins_encode(store_L_reg_enc(mem, src));
6092 ins_pipe( ialu_storeL );
6093 %}
6095 instruct storeL_immL0(memory mem, immL0 zero) %{
6096 match(Set mem (StoreL mem zero));
6098 ins_cost(180);
6099 format %{ "sd zero, $mem #@storeL_immL0" %}
6100 ins_encode(store_L_immL0_enc(mem, zero));
6101 ins_pipe( ialu_storeL );
6102 %}
6104 instruct storeL_imm(memory mem, immL src) %{
6105 match(Set mem (StoreL mem src));
6107 ins_cost(200);
6108 format %{ "sd $src, $mem #@storeL_imm" %}
6109 ins_encode(store_L_immL_enc(mem, src));
6110 ins_pipe( ialu_storeL );
6111 %}
6113 // Load Compressed Pointer
6114 instruct loadN(mRegN dst, memory mem)
6115 %{
6116 match(Set dst (LoadN mem));
6118 ins_cost(125); // XXX
6119 format %{ "lwu $dst, $mem\t# compressed ptr @ loadN" %}
6120 ins_encode (load_N_enc(dst, mem));
6121 ins_pipe( ialu_loadI ); // XXX
6122 %}
6124 instruct loadN2P(mRegP dst, memory mem)
6125 %{
6126 match(Set dst (DecodeN (LoadN mem)));
6127 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6129 ins_cost(125); // XXX
6130 format %{ "lwu $dst, $mem\t# @ loadN2P" %}
6131 ins_encode (load_N_enc(dst, mem));
6132 ins_pipe( ialu_loadI ); // XXX
6133 %}
6135 // Load Pointer
6136 instruct loadP(mRegP dst, memory mem) %{
6137 match(Set dst (LoadP mem));
6139 ins_cost(125);
6140 format %{ "ld $dst, $mem #@loadP" %}
6141 ins_encode (load_P_enc(dst, mem));
6142 ins_pipe( ialu_loadI );
6143 %}
6145 // Load Klass Pointer
6146 instruct loadKlass(mRegP dst, memory mem) %{
6147 match(Set dst (LoadKlass mem));
6149 ins_cost(125);
6150 format %{ "MOV $dst,$mem @ loadKlass" %}
6151 ins_encode (load_P_enc(dst, mem));
6152 ins_pipe( ialu_loadI );
6153 %}
6155 // Load narrow Klass Pointer
6156 instruct loadNKlass(mRegN dst, memory mem)
6157 %{
6158 match(Set dst (LoadNKlass mem));
6160 ins_cost(125); // XXX
6161 format %{ "lwu $dst, $mem\t# compressed klass ptr @ loadNKlass" %}
6162 ins_encode (load_N_enc(dst, mem));
6163 ins_pipe( ialu_loadI ); // XXX
6164 %}
6166 instruct loadN2PKlass(mRegP dst, memory mem)
6167 %{
6168 match(Set dst (DecodeNKlass (LoadNKlass mem)));
6169 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
6171 ins_cost(125); // XXX
6172 format %{ "lwu $dst, $mem\t# compressed klass ptr @ loadN2PKlass" %}
6173 ins_encode (load_N_enc(dst, mem));
6174 ins_pipe( ialu_loadI ); // XXX
6175 %}
6177 // Load Constant
6178 instruct loadConI(mRegI dst, immI src) %{
6179 match(Set dst src);
6181 ins_cost(150);
6182 format %{ "mov $dst, $src #@loadConI" %}
6183 ins_encode %{
6184 Register dst = $dst$$Register;
6185 int value = $src$$constant;
6186 __ move(dst, value);
6187 %}
6188 ins_pipe( ialu_regI_regI );
6189 %}
6192 instruct loadConL_set64(mRegL dst, immL src) %{
6193 match(Set dst src);
6194 ins_cost(120);
6195 format %{ "li $dst, $src @ loadConL_set64" %}
6196 ins_encode %{
6197 __ set64($dst$$Register, $src$$constant);
6198 %}
6199 ins_pipe(ialu_regL_regL);
6200 %}
6202 /*
6203 // Load long value from constant table (predicated by immL_expensive).
6204 instruct loadConL_load(mRegL dst, immL_expensive src) %{
6205 match(Set dst src);
6206 ins_cost(150);
6207 format %{ "ld $dst, $constantoffset[$constanttablebase] # load long $src from table @ loadConL_ldx" %}
6208 ins_encode %{
6209 int con_offset = $constantoffset($src);
6211 if (Assembler::is_simm16(con_offset)) {
6212 __ ld($dst$$Register, $constanttablebase, con_offset);
6213 } else {
6214 __ set64(AT, con_offset);
6215 if (UseLoongsonISA) {
6216 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6217 } else {
6218 __ daddu(AT, $constanttablebase, AT);
6219 __ ld($dst$$Register, AT, 0);
6220 }
6221 }
6222 %}
6223 ins_pipe(ialu_loadI);
6224 %}
6225 */
6227 instruct loadConL16(mRegL dst, immL16 src) %{
6228 match(Set dst src);
6229 ins_cost(105);
6230 format %{ "mov $dst, $src #@loadConL16" %}
6231 ins_encode %{
6232 Register dst_reg = as_Register($dst$$reg);
6233 int value = $src$$constant;
6234 __ daddiu(dst_reg, R0, value);
6235 %}
6236 ins_pipe( ialu_regL_regL );
6237 %}
6240 instruct loadConL0(mRegL dst, immL0 src) %{
6241 match(Set dst src);
6242 ins_cost(100);
6243 format %{ "mov $dst, zero #@loadConL0" %}
6244 ins_encode %{
6245 Register dst_reg = as_Register($dst$$reg);
6246 __ daddu(dst_reg, R0, R0);
6247 %}
6248 ins_pipe( ialu_regL_regL );
6249 %}
6251 // Load Range
6252 instruct loadRange(mRegI dst, memory mem) %{
6253 match(Set dst (LoadRange mem));
6255 ins_cost(125);
6256 format %{ "MOV $dst,$mem @ loadRange" %}
6257 ins_encode(load_I_enc(dst, mem));
6258 ins_pipe( ialu_loadI );
6259 %}
6262 instruct storeP(memory mem, mRegP src ) %{
6263 match(Set mem (StoreP mem src));
6265 ins_cost(125);
6266 format %{ "sd $src, $mem #@storeP" %}
6267 ins_encode(store_P_reg_enc(mem, src));
6268 ins_pipe( ialu_storeI );
6269 %}
6271 // Store NULL Pointer, mark word, or other simple pointer constant.
6272 instruct storeImmP0(memory mem, immP0 zero) %{
6273 match(Set mem (StoreP mem zero));
6275 ins_cost(125);
6276 format %{ "mov $mem, $zero #@storeImmP0" %}
6277 ins_encode(store_P_immP0_enc(mem));
6278 ins_pipe( ialu_storeI );
6279 %}
6281 // Store Byte Immediate
6282 instruct storeImmB(memory mem, immI8 src) %{
6283 match(Set mem (StoreB mem src));
6285 ins_cost(150);
6286 format %{ "movb $mem, $src #@storeImmB" %}
6287 ins_encode(store_B_immI_enc(mem, src));
6288 ins_pipe( ialu_storeI );
6289 %}
6291 // Store Compressed Pointer
6292 instruct storeN(memory mem, mRegN src)
6293 %{
6294 match(Set mem (StoreN mem src));
6296 ins_cost(125); // XXX
6297 format %{ "sw $mem, $src\t# compressed ptr @ storeN" %}
6298 ins_encode(store_N_reg_enc(mem, src));
6299 ins_pipe( ialu_storeI );
6300 %}
6302 instruct storeP2N(memory mem, mRegP src)
6303 %{
6304 match(Set mem (StoreN mem (EncodeP src)));
6305 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6307 ins_cost(125); // XXX
6308 format %{ "sw $mem, $src\t# @ storeP2N" %}
6309 ins_encode(store_N_reg_enc(mem, src));
6310 ins_pipe( ialu_storeI );
6311 %}
6313 instruct storeNKlass(memory mem, mRegN src)
6314 %{
6315 match(Set mem (StoreNKlass mem src));
6317 ins_cost(125); // XXX
6318 format %{ "sw $mem, $src\t# compressed klass ptr @ storeNKlass" %}
6319 ins_encode(store_N_reg_enc(mem, src));
6320 ins_pipe( ialu_storeI );
6321 %}
6323 instruct storeP2NKlass(memory mem, mRegP src)
6324 %{
6325 match(Set mem (StoreNKlass mem (EncodePKlass src)));
6326 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
6328 ins_cost(125); // XXX
6329 format %{ "sw $mem, $src\t# @ storeP2NKlass" %}
6330 ins_encode(store_N_reg_enc(mem, src));
6331 ins_pipe( ialu_storeI );
6332 %}
6334 instruct storeImmN0(memory mem, immN0 zero)
6335 %{
6336 match(Set mem (StoreN mem zero));
6338 ins_cost(125); // XXX
6339 format %{ "storeN0 zero, $mem\t# compressed ptr" %}
6340 ins_encode(storeImmN0_enc(mem, zero));
6341 ins_pipe( ialu_storeI );
6342 %}
6344 // Store Byte
6345 instruct storeB(memory mem, mRegI src) %{
6346 match(Set mem (StoreB mem src));
6348 ins_cost(125);
6349 format %{ "sb $src, $mem #@storeB" %}
6350 ins_encode(store_B_reg_enc(mem, src));
6351 ins_pipe( ialu_storeI );
6352 %}
6354 instruct storeB_convL2I(memory mem, mRegL src) %{
6355 match(Set mem (StoreB mem (ConvL2I src)));
6357 ins_cost(125);
6358 format %{ "sb $src, $mem #@storeB_convL2I" %}
6359 ins_encode(store_B_reg_enc(mem, src));
6360 ins_pipe( ialu_storeI );
6361 %}
6363 // Load Byte (8bit signed)
6364 instruct loadB(mRegI dst, memory mem) %{
6365 match(Set dst (LoadB mem));
6367 ins_cost(125);
6368 format %{ "lb $dst, $mem #@loadB" %}
6369 ins_encode(load_B_enc(dst, mem));
6370 ins_pipe( ialu_loadI );
6371 %}
6373 instruct loadB_convI2L(mRegL dst, memory mem) %{
6374 match(Set dst (ConvI2L (LoadB mem)));
6376 ins_cost(125);
6377 format %{ "lb $dst, $mem #@loadB_convI2L" %}
6378 ins_encode(load_B_enc(dst, mem));
6379 ins_pipe( ialu_loadI );
6380 %}
6382 // Load Byte (8bit UNsigned)
6383 instruct loadUB(mRegI dst, memory mem) %{
6384 match(Set dst (LoadUB mem));
6386 ins_cost(125);
6387 format %{ "lbu $dst, $mem #@loadUB" %}
6388 ins_encode(load_UB_enc(dst, mem));
6389 ins_pipe( ialu_loadI );
6390 %}
6392 instruct loadUB_convI2L(mRegL dst, memory mem) %{
6393 match(Set dst (ConvI2L (LoadUB mem)));
6395 ins_cost(125);
6396 format %{ "lbu $dst, $mem #@loadUB_convI2L" %}
6397 ins_encode(load_UB_enc(dst, mem));
6398 ins_pipe( ialu_loadI );
6399 %}
6401 // Load Short (16bit signed)
6402 instruct loadS(mRegI dst, memory mem) %{
6403 match(Set dst (LoadS mem));
6405 ins_cost(125);
6406 format %{ "lh $dst, $mem #@loadS" %}
6407 ins_encode(load_S_enc(dst, mem));
6408 ins_pipe( ialu_loadI );
6409 %}
6411 // Load Short (16 bit signed) to Byte (8 bit signed)
6412 instruct loadS2B(mRegI dst, memory mem, immI_24 twentyfour) %{
6413 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
6415 ins_cost(125);
6416 format %{ "lb $dst, $mem\t# short -> byte #@loadS2B" %}
6417 ins_encode(load_B_enc(dst, mem));
6418 ins_pipe(ialu_loadI);
6419 %}
6421 instruct loadS_convI2L(mRegL dst, memory mem) %{
6422 match(Set dst (ConvI2L (LoadS mem)));
6424 ins_cost(125);
6425 format %{ "lh $dst, $mem #@loadS_convI2L" %}
6426 ins_encode(load_S_enc(dst, mem));
6427 ins_pipe( ialu_loadI );
6428 %}
6430 // Store Integer Immediate
6431 instruct storeImmI(memory mem, immI src) %{
6432 match(Set mem (StoreI mem src));
6434 ins_cost(150);
6435 format %{ "mov $mem, $src #@storeImmI" %}
6436 ins_encode(store_I_immI_enc(mem, src));
6437 ins_pipe( ialu_storeI );
6438 %}
6440 // Store Integer
6441 instruct storeI(memory mem, mRegI src) %{
6442 match(Set mem (StoreI mem src));
6444 ins_cost(125);
6445 format %{ "sw $mem, $src #@storeI" %}
6446 ins_encode(store_I_reg_enc(mem, src));
6447 ins_pipe( ialu_storeI );
6448 %}
6450 instruct storeI_convL2I(memory mem, mRegL src) %{
6451 match(Set mem (StoreI mem (ConvL2I src)));
6453 ins_cost(125);
6454 format %{ "sw $mem, $src #@storeI_convL2I" %}
6455 ins_encode(store_I_reg_enc(mem, src));
6456 ins_pipe( ialu_storeI );
6457 %}
6459 // Load Float
6460 instruct loadF(regF dst, memory mem) %{
6461 match(Set dst (LoadF mem));
6463 ins_cost(150);
6464 format %{ "loadF $dst, $mem #@loadF" %}
6465 ins_encode(load_F_enc(dst, mem));
6466 ins_pipe( ialu_loadI );
6467 %}
6469 instruct loadConP_general(mRegP dst, immP src) %{
6470 match(Set dst src);
6472 ins_cost(120);
6473 format %{ "li $dst, $src #@loadConP_general" %}
6475 ins_encode %{
6476 Register dst = $dst$$Register;
6477 long* value = (long*)$src$$constant;
6479 if($src->constant_reloc() == relocInfo::metadata_type){
6480 int klass_index = __ oop_recorder()->find_index((Klass*)value);
6481 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6483 __ relocate(rspec);
6484 __ patchable_set48(dst, (long)value);
6485 }else if($src->constant_reloc() == relocInfo::oop_type){
6486 int oop_index = __ oop_recorder()->find_index((jobject)value);
6487 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6489 __ relocate(rspec);
6490 __ patchable_set48(dst, (long)value);
6491 } else if ($src->constant_reloc() == relocInfo::none) {
6492 __ set64(dst, (long)value);
6493 }
6494 %}
6496 ins_pipe( ialu_regI_regI );
6497 %}
6499 /*
6500 instruct loadConP_load(mRegP dst, immP_load src) %{
6501 match(Set dst src);
6503 ins_cost(100);
6504 format %{ "ld $dst, [$constanttablebase + $constantoffset] load from constant table: ptr=$src @ loadConP_load" %}
6506 ins_encode %{
6508 int con_offset = $constantoffset($src);
6510 if (Assembler::is_simm16(con_offset)) {
6511 __ ld($dst$$Register, $constanttablebase, con_offset);
6512 } else {
6513 __ set64(AT, con_offset);
6514 if (UseLoongsonISA) {
6515 __ gsldx($dst$$Register, $constanttablebase, AT, 0);
6516 } else {
6517 __ daddu(AT, $constanttablebase, AT);
6518 __ ld($dst$$Register, AT, 0);
6519 }
6520 }
6521 %}
6523 ins_pipe(ialu_loadI);
6524 %}
6525 */
6527 instruct loadConP_no_oop_cheap(mRegP dst, immP_no_oop_cheap src) %{
6528 match(Set dst src);
6530 ins_cost(80);
6531 format %{ "li $dst, $src @ loadConP_no_oop_cheap" %}
6533 ins_encode %{
6534 __ set64($dst$$Register, $src$$constant);
6535 %}
6537 ins_pipe(ialu_regI_regI);
6538 %}
6541 instruct loadConP_poll(mRegP dst, immP_poll src) %{
6542 match(Set dst src);
6544 ins_cost(50);
6545 format %{ "li $dst, $src #@loadConP_poll" %}
6547 ins_encode %{
6548 Register dst = $dst$$Register;
6549 intptr_t value = (intptr_t)$src$$constant;
6551 __ set64(dst, (jlong)value);
6552 %}
6554 ins_pipe( ialu_regI_regI );
6555 %}
6557 instruct loadConP0(mRegP dst, immP0 src)
6558 %{
6559 match(Set dst src);
6561 ins_cost(50);
6562 format %{ "mov $dst, R0\t# ptr" %}
6563 ins_encode %{
6564 Register dst_reg = $dst$$Register;
6565 __ daddu(dst_reg, R0, R0);
6566 %}
6567 ins_pipe( ialu_regI_regI );
6568 %}
6570 instruct loadConN0(mRegN dst, immN0 src) %{
6571 match(Set dst src);
6572 format %{ "move $dst, R0\t# compressed NULL ptr" %}
6573 ins_encode %{
6574 __ move($dst$$Register, R0);
6575 %}
6576 ins_pipe( ialu_regI_regI );
6577 %}
6579 instruct loadConN(mRegN dst, immN src) %{
6580 match(Set dst src);
6582 ins_cost(125);
6583 format %{ "li $dst, $src\t# compressed ptr @ loadConN" %}
6584 ins_encode %{
6585 Register dst = $dst$$Register;
6586 __ set_narrow_oop(dst, (jobject)$src$$constant);
6587 %}
6588 ins_pipe( ialu_regI_regI ); // XXX
6589 %}
6591 instruct loadConNKlass(mRegN dst, immNKlass src) %{
6592 match(Set dst src);
6594 ins_cost(125);
6595 format %{ "li $dst, $src\t# compressed klass ptr @ loadConNKlass" %}
6596 ins_encode %{
6597 Register dst = $dst$$Register;
6598 __ set_narrow_klass(dst, (Klass*)$src$$constant);
6599 %}
6600 ins_pipe( ialu_regI_regI ); // XXX
6601 %}
6603 //FIXME
6604 // Tail Call; Jump from runtime stub to Java code.
6605 // Also known as an 'interprocedural jump'.
6606 // Target of jump will eventually return to caller.
6607 // TailJump below removes the return address.
6608 instruct TailCalljmpInd(mRegP jump_target, mRegP method_oop) %{
6609 match(TailCall jump_target method_oop );
6610 ins_cost(300);
6611 format %{ "JMP $jump_target \t# @TailCalljmpInd" %}
6613 ins_encode %{
6614 Register target = $jump_target$$Register;
6615 Register oop = $method_oop$$Register;
6617 /* 2012/10/12 Jin: RA will be used in generate_forward_exception() */
6618 __ push(RA);
6620 __ move(S3, oop);
6621 __ jr(target);
6622 __ nop();
6623 %}
6625 ins_pipe( pipe_jump );
6626 %}
6628 // Create exception oop: created by stack-crawling runtime code.
6629 // Created exception is now available to this handler, and is setup
6630 // just prior to jumping to this handler. No code emitted.
6631 instruct CreateException( a0_RegP ex_oop )
6632 %{
6633 match(Set ex_oop (CreateEx));
6635 // use the following format syntax
6636 format %{ "# exception oop is in A0; no code emitted @CreateException" %}
6637 ins_encode %{
6638 /* Jin: X86 leaves this function empty */
6639 __ block_comment("CreateException is empty in X86/MIPS");
6640 %}
6641 ins_pipe( empty );
6642 // ins_pipe( pipe_jump );
6643 %}
6646 /* 2012/9/14 Jin: The mechanism of exception handling is clear now.
6648 - Common try/catch:
6649 2012/9/14 Jin: [stubGenerator_mips.cpp] generate_forward_exception()
6650 |- V0, V1 are created
6651 |- T9 <= SharedRuntime::exception_handler_for_return_address
6652 `- jr T9
6653 `- the caller's exception_handler
6654 `- jr OptoRuntime::exception_blob
6655 `- here
6656 - Rethrow(e.g. 'unwind'):
6657 * The callee:
6658 |- an exception is triggered during execution
6659 `- exits the callee method through RethrowException node
6660 |- The callee pushes exception_oop(T0) and exception_pc(RA)
6661 `- The callee jumps to OptoRuntime::rethrow_stub()
6662 * In OptoRuntime::rethrow_stub:
6663 |- The VM calls _rethrow_Java to determine the return address in the caller method
6664 `- exits the stub with tailjmpInd
6665 |- pops exception_oop(V0) and exception_pc(V1)
6666 `- jumps to the return address(usually an exception_handler)
6667 * The caller:
6668 `- continues processing the exception_blob with V0/V1
6669 */
6671 /*
6672 Disassembling OptoRuntime::rethrow_stub()
6674 ; locals
6675 0x2d3bf320: addiu sp, sp, 0xfffffff8
6676 0x2d3bf324: sw ra, 0x4(sp)
6677 0x2d3bf328: sw fp, 0x0(sp)
6678 0x2d3bf32c: addu fp, sp, zero
6679 0x2d3bf330: addiu sp, sp, 0xfffffff0
6680 0x2d3bf334: sw ra, 0x8(sp)
6681 0x2d3bf338: sw t0, 0x4(sp)
6682 0x2d3bf33c: sw sp, 0x0(sp)
6684 ; get_thread(S2)
6685 0x2d3bf340: addu s2, sp, zero
6686 0x2d3bf344: srl s2, s2, 12
6687 0x2d3bf348: sll s2, s2, 2
6688 0x2d3bf34c: lui at, 0x2c85
6689 0x2d3bf350: addu at, at, s2
6690 0x2d3bf354: lw s2, 0xffffcc80(at)
6692 0x2d3bf358: lw s0, 0x0(sp)
6693 0x2d3bf35c: sw s0, 0x118(s2) // last_sp -> threa
6694 0x2d3bf360: sw s2, 0xc(sp)
6696 ; OptoRuntime::rethrow_C(oopDesc* exception, JavaThread* thread, address ret_pc)
6697 0x2d3bf364: lw a0, 0x4(sp)
6698 0x2d3bf368: lw a1, 0xc(sp)
6699 0x2d3bf36c: lw a2, 0x8(sp)
6700 ;; Java_To_Runtime
6701 0x2d3bf370: lui t9, 0x2c34
6702 0x2d3bf374: addiu t9, t9, 0xffff8a48
6703 0x2d3bf378: jalr t9
6704 0x2d3bf37c: nop
6706 0x2d3bf380: addu s3, v0, zero ; S3: SharedRuntime::raw_exception_handler_for_return_address()
6708 0x2d3bf384: lw s0, 0xc(sp)
6709 0x2d3bf388: sw zero, 0x118(s0)
6710 0x2d3bf38c: sw zero, 0x11c(s0)
6711 0x2d3bf390: lw s1, 0x144(s0) ; ex_oop: S1
6712 0x2d3bf394: addu s2, s0, zero
6713 0x2d3bf398: sw zero, 0x144(s2)
6714 0x2d3bf39c: lw s0, 0x4(s2)
6715 0x2d3bf3a0: addiu s4, zero, 0x0
6716 0x2d3bf3a4: bne s0, s4, 0x2d3bf3d4
6717 0x2d3bf3a8: nop
6718 0x2d3bf3ac: addiu sp, sp, 0x10
6719 0x2d3bf3b0: addiu sp, sp, 0x8
6720 0x2d3bf3b4: lw ra, 0xfffffffc(sp)
6721 0x2d3bf3b8: lw fp, 0xfffffff8(sp)
6722 0x2d3bf3bc: lui at, 0x2b48
6723 0x2d3bf3c0: lw at, 0x100(at)
6725 ; tailjmpInd: Restores exception_oop & exception_pc
6726 0x2d3bf3c4: addu v1, ra, zero
6727 0x2d3bf3c8: addu v0, s1, zero
6728 0x2d3bf3cc: jr s3
6729 0x2d3bf3d0: nop
6730 ; Exception:
6731 0x2d3bf3d4: lui s1, 0x2cc8 ; generate_forward_exception()
6732 0x2d3bf3d8: addiu s1, s1, 0x40
6733 0x2d3bf3dc: addiu s2, zero, 0x0
6734 0x2d3bf3e0: addiu sp, sp, 0x10
6735 0x2d3bf3e4: addiu sp, sp, 0x8
6736 0x2d3bf3e8: lw ra, 0xfffffffc(sp)
6737 0x2d3bf3ec: lw fp, 0xfffffff8(sp)
6738 0x2d3bf3f0: lui at, 0x2b48
6739 0x2d3bf3f4: lw at, 0x100(at)
6740 ; TailCalljmpInd
6741 __ push(RA); ; to be used in generate_forward_exception()
6742 0x2d3bf3f8: addu t7, s2, zero
6743 0x2d3bf3fc: jr s1
6744 0x2d3bf400: nop
6745 */
6746 // Rethrow exception:
6747 // The exception oop will come in the first argument position.
6748 // Then JUMP (not call) to the rethrow stub code.
6749 instruct RethrowException()
6750 %{
6751 match(Rethrow);
6753 // use the following format syntax
6754 format %{ "JMP rethrow_stub #@RethrowException" %}
6755 ins_encode %{
6756 __ block_comment("@ RethrowException");
6758 cbuf.set_insts_mark();
6759 cbuf.relocate(cbuf.insts_mark(), runtime_call_Relocation::spec());
6761 // call OptoRuntime::rethrow_stub to get the exception handler in parent method
6762 __ patchable_jump((address)OptoRuntime::rethrow_stub());
6763 %}
6764 ins_pipe( pipe_jump );
6765 %}
6767 instruct branchConP_zero(cmpOpU cmp, mRegP op1, immP0 zero, label labl) %{
6768 match(If cmp (CmpP op1 zero));
6769 effect(USE labl);
6771 ins_cost(180);
6772 format %{ "b$cmp $op1, R0, $labl #@branchConP_zero" %}
6774 ins_encode %{
6775 Register op1 = $op1$$Register;
6776 Register op2 = R0;
6777 Label &L = *($labl$$label);
6778 int flag = $cmp$$cmpcode;
6780 switch(flag)
6781 {
6782 case 0x01: //equal
6783 if (&L)
6784 __ beq(op1, op2, L);
6785 else
6786 __ beq(op1, op2, (int)0);
6787 break;
6788 case 0x02: //not_equal
6789 if (&L)
6790 __ bne(op1, op2, L);
6791 else
6792 __ bne(op1, op2, (int)0);
6793 break;
6794 /*
6795 case 0x03: //above
6796 __ sltu(AT, op2, op1);
6797 if(&L)
6798 __ bne(R0, AT, L);
6799 else
6800 __ bne(R0, AT, (int)0);
6801 break;
6802 case 0x04: //above_equal
6803 __ sltu(AT, op1, op2);
6804 if(&L)
6805 __ beq(AT, R0, L);
6806 else
6807 __ beq(AT, R0, (int)0);
6808 break;
6809 case 0x05: //below
6810 __ sltu(AT, op1, op2);
6811 if(&L)
6812 __ bne(R0, AT, L);
6813 else
6814 __ bne(R0, AT, (int)0);
6815 break;
6816 case 0x06: //below_equal
6817 __ sltu(AT, op2, op1);
6818 if(&L)
6819 __ beq(AT, R0, L);
6820 else
6821 __ beq(AT, R0, (int)0);
6822 break;
6823 */
6824 default:
6825 Unimplemented();
6826 }
6827 __ nop();
6828 %}
6830 ins_pc_relative(1);
6831 ins_pipe( pipe_alu_branch );
6832 %}
6834 instruct branchConN2P_zero(cmpOpU cmp, mRegN op1, immP0 zero, label labl) %{
6835 match(If cmp (CmpP (DecodeN op1) zero));
6836 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0);
6837 effect(USE labl);
6839 ins_cost(180);
6840 format %{ "b$cmp $op1, R0, $labl #@branchConN2P_zero" %}
6842 ins_encode %{
6843 Register op1 = $op1$$Register;
6844 Register op2 = R0;
6845 Label &L = *($labl$$label);
6846 int flag = $cmp$$cmpcode;
6848 switch(flag)
6849 {
6850 case 0x01: //equal
6851 if (&L)
6852 __ beq(op1, op2, L);
6853 else
6854 __ beq(op1, op2, (int)0);
6855 break;
6856 case 0x02: //not_equal
6857 if (&L)
6858 __ bne(op1, op2, L);
6859 else
6860 __ bne(op1, op2, (int)0);
6861 break;
6862 default:
6863 Unimplemented();
6864 }
6865 __ nop();
6866 %}
6868 ins_pc_relative(1);
6869 ins_pipe( pipe_alu_branch );
6870 %}
6873 instruct branchConP(cmpOpU cmp, mRegP op1, mRegP op2, label labl) %{
6874 match(If cmp (CmpP op1 op2));
6875 // predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
6876 effect(USE labl);
6878 ins_cost(200);
6879 format %{ "b$cmp $op1, $op2, $labl #@branchConP" %}
6881 ins_encode %{
6882 Register op1 = $op1$$Register;
6883 Register op2 = $op2$$Register;
6884 Label &L = *($labl$$label);
6885 int flag = $cmp$$cmpcode;
6887 switch(flag)
6888 {
6889 case 0x01: //equal
6890 if (&L)
6891 __ beq(op1, op2, L);
6892 else
6893 __ beq(op1, op2, (int)0);
6894 break;
6895 case 0x02: //not_equal
6896 if (&L)
6897 __ bne(op1, op2, L);
6898 else
6899 __ bne(op1, op2, (int)0);
6900 break;
6901 case 0x03: //above
6902 __ sltu(AT, op2, op1);
6903 if(&L)
6904 __ bne(R0, AT, L);
6905 else
6906 __ bne(R0, AT, (int)0);
6907 break;
6908 case 0x04: //above_equal
6909 __ sltu(AT, op1, op2);
6910 if(&L)
6911 __ beq(AT, R0, L);
6912 else
6913 __ beq(AT, R0, (int)0);
6914 break;
6915 case 0x05: //below
6916 __ sltu(AT, op1, op2);
6917 if(&L)
6918 __ bne(R0, AT, L);
6919 else
6920 __ bne(R0, AT, (int)0);
6921 break;
6922 case 0x06: //below_equal
6923 __ sltu(AT, op2, op1);
6924 if(&L)
6925 __ beq(AT, R0, L);
6926 else
6927 __ beq(AT, R0, (int)0);
6928 break;
6929 default:
6930 Unimplemented();
6931 }
6932 __ nop();
6933 %}
6935 ins_pc_relative(1);
6936 ins_pipe( pipe_alu_branch );
6937 %}
6939 instruct cmpN_null_branch(cmpOp cmp, mRegN op1, immN0 null, label labl) %{
6940 match(If cmp (CmpN op1 null));
6941 effect(USE labl);
6943 ins_cost(180);
6944 format %{ "CMP $op1,0\t! compressed ptr\n\t"
6945 "BP$cmp $labl @ cmpN_null_branch" %}
6946 ins_encode %{
6947 Register op1 = $op1$$Register;
6948 Register op2 = R0;
6949 Label &L = *($labl$$label);
6950 int flag = $cmp$$cmpcode;
6952 switch(flag)
6953 {
6954 case 0x01: //equal
6955 if (&L)
6956 __ beq(op1, op2, L);
6957 else
6958 __ beq(op1, op2, (int)0);
6959 break;
6960 case 0x02: //not_equal
6961 if (&L)
6962 __ bne(op1, op2, L);
6963 else
6964 __ bne(op1, op2, (int)0);
6965 break;
6966 default:
6967 Unimplemented();
6968 }
6969 __ nop();
6970 %}
6971 //TODO: pipe_branchP or create pipe_branchN LEE
6972 ins_pc_relative(1);
6973 ins_pipe( pipe_alu_branch );
6974 %}
6976 instruct cmpN_reg_branch(cmpOp cmp, mRegN op1, mRegN op2, label labl) %{
6977 match(If cmp (CmpN op1 op2));
6978 effect(USE labl);
6980 ins_cost(180);
6981 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
6982 "BP$cmp $labl" %}
6983 ins_encode %{
6984 Register op1_reg = $op1$$Register;
6985 Register op2_reg = $op2$$Register;
6986 Label &L = *($labl$$label);
6987 int flag = $cmp$$cmpcode;
6989 switch(flag)
6990 {
6991 case 0x01: //equal
6992 if (&L)
6993 __ beq(op1_reg, op2_reg, L);
6994 else
6995 __ beq(op1_reg, op2_reg, (int)0);
6996 break;
6997 case 0x02: //not_equal
6998 if (&L)
6999 __ bne(op1_reg, op2_reg, L);
7000 else
7001 __ bne(op1_reg, op2_reg, (int)0);
7002 break;
7003 case 0x03: //above
7004 __ sltu(AT, op2_reg, op1_reg);
7005 if(&L)
7006 __ bne(R0, AT, L);
7007 else
7008 __ bne(R0, AT, (int)0);
7009 break;
7010 case 0x04: //above_equal
7011 __ sltu(AT, op1_reg, op2_reg);
7012 if(&L)
7013 __ beq(AT, R0, L);
7014 else
7015 __ beq(AT, R0, (int)0);
7016 break;
7017 case 0x05: //below
7018 __ sltu(AT, op1_reg, op2_reg);
7019 if(&L)
7020 __ bne(R0, AT, L);
7021 else
7022 __ bne(R0, AT, (int)0);
7023 break;
7024 case 0x06: //below_equal
7025 __ sltu(AT, op2_reg, op1_reg);
7026 if(&L)
7027 __ beq(AT, R0, L);
7028 else
7029 __ beq(AT, R0, (int)0);
7030 break;
7031 default:
7032 Unimplemented();
7033 }
7034 __ nop();
7035 %}
7036 ins_pc_relative(1);
7037 ins_pipe( pipe_alu_branch );
7038 %}
7040 instruct branchConIU_reg_reg(cmpOpU cmp, mRegI src1, mRegI src2, label labl) %{
7041 match( If cmp (CmpU src1 src2) );
7042 effect(USE labl);
7043 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_reg" %}
7045 ins_encode %{
7046 Register op1 = $src1$$Register;
7047 Register op2 = $src2$$Register;
7048 Label &L = *($labl$$label);
7049 int flag = $cmp$$cmpcode;
7051 switch(flag)
7052 {
7053 case 0x01: //equal
7054 if (&L)
7055 __ beq(op1, op2, L);
7056 else
7057 __ beq(op1, op2, (int)0);
7058 break;
7059 case 0x02: //not_equal
7060 if (&L)
7061 __ bne(op1, op2, L);
7062 else
7063 __ bne(op1, op2, (int)0);
7064 break;
7065 case 0x03: //above
7066 __ sltu(AT, op2, op1);
7067 if(&L)
7068 __ bne(AT, R0, L);
7069 else
7070 __ bne(AT, R0, (int)0);
7071 break;
7072 case 0x04: //above_equal
7073 __ sltu(AT, op1, op2);
7074 if(&L)
7075 __ beq(AT, R0, L);
7076 else
7077 __ beq(AT, R0, (int)0);
7078 break;
7079 case 0x05: //below
7080 __ sltu(AT, op1, op2);
7081 if(&L)
7082 __ bne(AT, R0, L);
7083 else
7084 __ bne(AT, R0, (int)0);
7085 break;
7086 case 0x06: //below_equal
7087 __ sltu(AT, op2, op1);
7088 if(&L)
7089 __ beq(AT, R0, L);
7090 else
7091 __ beq(AT, R0, (int)0);
7092 break;
7093 default:
7094 Unimplemented();
7095 }
7096 __ nop();
7097 %}
7099 ins_pc_relative(1);
7100 ins_pipe( pipe_alu_branch );
7101 %}
7104 instruct branchConIU_reg_imm(cmpOpU cmp, mRegI src1, immI src2, label labl) %{
7105 match( If cmp (CmpU src1 src2) );
7106 effect(USE labl);
7107 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_imm" %}
7109 ins_encode %{
7110 Register op1 = $src1$$Register;
7111 int val = $src2$$constant;
7112 Label &L = *($labl$$label);
7113 int flag = $cmp$$cmpcode;
7115 __ move(AT, val);
7116 switch(flag)
7117 {
7118 case 0x01: //equal
7119 if (&L)
7120 __ beq(op1, AT, L);
7121 else
7122 __ beq(op1, AT, (int)0);
7123 break;
7124 case 0x02: //not_equal
7125 if (&L)
7126 __ bne(op1, AT, L);
7127 else
7128 __ bne(op1, AT, (int)0);
7129 break;
7130 case 0x03: //above
7131 __ sltu(AT, AT, op1);
7132 if(&L)
7133 __ bne(R0, AT, L);
7134 else
7135 __ bne(R0, AT, (int)0);
7136 break;
7137 case 0x04: //above_equal
7138 __ sltu(AT, op1, AT);
7139 if(&L)
7140 __ beq(AT, R0, L);
7141 else
7142 __ beq(AT, R0, (int)0);
7143 break;
7144 case 0x05: //below
7145 __ sltu(AT, op1, AT);
7146 if(&L)
7147 __ bne(R0, AT, L);
7148 else
7149 __ bne(R0, AT, (int)0);
7150 break;
7151 case 0x06: //below_equal
7152 __ sltu(AT, AT, op1);
7153 if(&L)
7154 __ beq(AT, R0, L);
7155 else
7156 __ beq(AT, R0, (int)0);
7157 break;
7158 default:
7159 Unimplemented();
7160 }
7161 __ nop();
7162 %}
7164 ins_pc_relative(1);
7165 ins_pipe( pipe_alu_branch );
7166 %}
7168 instruct branchConI_reg_reg(cmpOp cmp, mRegI src1, mRegI src2, label labl) %{
7169 match( If cmp (CmpI src1 src2) );
7170 effect(USE labl);
7171 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_reg" %}
7173 ins_encode %{
7174 Register op1 = $src1$$Register;
7175 Register op2 = $src2$$Register;
7176 Label &L = *($labl$$label);
7177 int flag = $cmp$$cmpcode;
7179 switch(flag)
7180 {
7181 case 0x01: //equal
7182 if (&L)
7183 __ beq(op1, op2, L);
7184 else
7185 __ beq(op1, op2, (int)0);
7186 break;
7187 case 0x02: //not_equal
7188 if (&L)
7189 __ bne(op1, op2, L);
7190 else
7191 __ bne(op1, op2, (int)0);
7192 break;
7193 case 0x03: //above
7194 __ slt(AT, op2, op1);
7195 if(&L)
7196 __ bne(R0, AT, L);
7197 else
7198 __ bne(R0, AT, (int)0);
7199 break;
7200 case 0x04: //above_equal
7201 __ slt(AT, op1, op2);
7202 if(&L)
7203 __ beq(AT, R0, L);
7204 else
7205 __ beq(AT, R0, (int)0);
7206 break;
7207 case 0x05: //below
7208 __ slt(AT, op1, op2);
7209 if(&L)
7210 __ bne(R0, AT, L);
7211 else
7212 __ bne(R0, AT, (int)0);
7213 break;
7214 case 0x06: //below_equal
7215 __ slt(AT, op2, op1);
7216 if(&L)
7217 __ beq(AT, R0, L);
7218 else
7219 __ beq(AT, R0, (int)0);
7220 break;
7221 default:
7222 Unimplemented();
7223 }
7224 __ nop();
7225 %}
7227 ins_pc_relative(1);
7228 ins_pipe( pipe_alu_branch );
7229 %}
7231 instruct branchConI_reg_imm0(cmpOp cmp, mRegI src1, immI0 src2, label labl) %{
7232 match( If cmp (CmpI src1 src2) );
7233 effect(USE labl);
7234 ins_cost(170);
7235 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm0" %}
7237 ins_encode %{
7238 Register op1 = $src1$$Register;
7239 // int val = $src2$$constant;
7240 Label &L = *($labl$$label);
7241 int flag = $cmp$$cmpcode;
7243 //__ move(AT, val);
7244 switch(flag)
7245 {
7246 case 0x01: //equal
7247 if (&L)
7248 __ beq(op1, R0, L);
7249 else
7250 __ beq(op1, R0, (int)0);
7251 break;
7252 case 0x02: //not_equal
7253 if (&L)
7254 __ bne(op1, R0, L);
7255 else
7256 __ bne(op1, R0, (int)0);
7257 break;
7258 case 0x03: //greater
7259 if(&L)
7260 __ bgtz(op1, L);
7261 else
7262 __ bgtz(op1, (int)0);
7263 break;
7264 case 0x04: //greater_equal
7265 if(&L)
7266 __ bgez(op1, L);
7267 else
7268 __ bgez(op1, (int)0);
7269 break;
7270 case 0x05: //less
7271 if(&L)
7272 __ bltz(op1, L);
7273 else
7274 __ bltz(op1, (int)0);
7275 break;
7276 case 0x06: //less_equal
7277 if(&L)
7278 __ blez(op1, L);
7279 else
7280 __ blez(op1, (int)0);
7281 break;
7282 default:
7283 Unimplemented();
7284 }
7285 __ nop();
7286 %}
7288 ins_pc_relative(1);
7289 ins_pipe( pipe_alu_branch );
7290 %}
7293 instruct branchConI_reg_imm(cmpOp cmp, mRegI src1, immI src2, label labl) %{
7294 match( If cmp (CmpI src1 src2) );
7295 effect(USE labl);
7296 ins_cost(200);
7297 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm" %}
7299 ins_encode %{
7300 Register op1 = $src1$$Register;
7301 int val = $src2$$constant;
7302 Label &L = *($labl$$label);
7303 int flag = $cmp$$cmpcode;
7305 __ move(AT, val);
7306 switch(flag)
7307 {
7308 case 0x01: //equal
7309 if (&L)
7310 __ beq(op1, AT, L);
7311 else
7312 __ beq(op1, AT, (int)0);
7313 break;
7314 case 0x02: //not_equal
7315 if (&L)
7316 __ bne(op1, AT, L);
7317 else
7318 __ bne(op1, AT, (int)0);
7319 break;
7320 case 0x03: //greater
7321 __ slt(AT, AT, op1);
7322 if(&L)
7323 __ bne(R0, AT, L);
7324 else
7325 __ bne(R0, AT, (int)0);
7326 break;
7327 case 0x04: //greater_equal
7328 __ slt(AT, op1, AT);
7329 if(&L)
7330 __ beq(AT, R0, L);
7331 else
7332 __ beq(AT, R0, (int)0);
7333 break;
7334 case 0x05: //less
7335 __ slt(AT, op1, AT);
7336 if(&L)
7337 __ bne(R0, AT, L);
7338 else
7339 __ bne(R0, AT, (int)0);
7340 break;
7341 case 0x06: //less_equal
7342 __ slt(AT, AT, op1);
7343 if(&L)
7344 __ beq(AT, R0, L);
7345 else
7346 __ beq(AT, R0, (int)0);
7347 break;
7348 default:
7349 Unimplemented();
7350 }
7351 __ nop();
7352 %}
7354 ins_pc_relative(1);
7355 ins_pipe( pipe_alu_branch );
7356 %}
7358 instruct branchConIU_reg_imm0(cmpOpU cmp, mRegI src1, immI0 zero, label labl) %{
7359 match( If cmp (CmpU src1 zero) );
7360 effect(USE labl);
7361 format %{ "BR$cmp $src1, zero, $labl #@branchConIU_reg_imm0" %}
7363 ins_encode %{
7364 Register op1 = $src1$$Register;
7365 Label &L = *($labl$$label);
7366 int flag = $cmp$$cmpcode;
7368 switch(flag)
7369 {
7370 case 0x01: //equal
7371 if (&L)
7372 __ beq(op1, R0, L);
7373 else
7374 __ beq(op1, R0, (int)0);
7375 break;
7376 case 0x02: //not_equal
7377 if (&L)
7378 __ bne(op1, R0, L);
7379 else
7380 __ bne(op1, R0, (int)0);
7381 break;
7382 case 0x03: //above
7383 if(&L)
7384 __ bne(R0, op1, L);
7385 else
7386 __ bne(R0, op1, (int)0);
7387 break;
7388 case 0x04: //above_equal
7389 if(&L)
7390 __ beq(R0, R0, L);
7391 else
7392 __ beq(R0, R0, (int)0);
7393 break;
7394 case 0x05: //below
7395 return;
7396 break;
7397 case 0x06: //below_equal
7398 if(&L)
7399 __ beq(op1, R0, L);
7400 else
7401 __ beq(op1, R0, (int)0);
7402 break;
7403 default:
7404 Unimplemented();
7405 }
7406 __ nop();
7407 %}
7409 ins_pc_relative(1);
7410 ins_pipe( pipe_alu_branch );
7411 %}
7414 instruct branchConIU_reg_immI16(cmpOpU cmp, mRegI src1, immI16 src2, label labl) %{
7415 match( If cmp (CmpU src1 src2) );
7416 effect(USE labl);
7417 ins_cost(180);
7418 format %{ "BR$cmp $src1, $src2, $labl #@branchConIU_reg_immI16" %}
7420 ins_encode %{
7421 Register op1 = $src1$$Register;
7422 int val = $src2$$constant;
7423 Label &L = *($labl$$label);
7424 int flag = $cmp$$cmpcode;
7426 switch(flag)
7427 {
7428 case 0x01: //equal
7429 __ move(AT, val);
7430 if (&L)
7431 __ beq(op1, AT, L);
7432 else
7433 __ beq(op1, AT, (int)0);
7434 break;
7435 case 0x02: //not_equal
7436 __ move(AT, val);
7437 if (&L)
7438 __ bne(op1, AT, L);
7439 else
7440 __ bne(op1, AT, (int)0);
7441 break;
7442 case 0x03: //above
7443 __ move(AT, val);
7444 __ sltu(AT, AT, op1);
7445 if(&L)
7446 __ bne(R0, AT, L);
7447 else
7448 __ bne(R0, AT, (int)0);
7449 break;
7450 case 0x04: //above_equal
7451 __ sltiu(AT, op1, val);
7452 if(&L)
7453 __ beq(AT, R0, L);
7454 else
7455 __ beq(AT, R0, (int)0);
7456 break;
7457 case 0x05: //below
7458 __ sltiu(AT, op1, val);
7459 if(&L)
7460 __ bne(R0, AT, L);
7461 else
7462 __ bne(R0, AT, (int)0);
7463 break;
7464 case 0x06: //below_equal
7465 __ move(AT, val);
7466 __ sltu(AT, AT, op1);
7467 if(&L)
7468 __ beq(AT, R0, L);
7469 else
7470 __ beq(AT, R0, (int)0);
7471 break;
7472 default:
7473 Unimplemented();
7474 }
7475 __ nop();
7476 %}
7478 ins_pc_relative(1);
7479 ins_pipe( pipe_alu_branch );
7480 %}
7483 instruct branchConL_regL_regL(cmpOp cmp, mRegL src1, mRegL src2, label labl) %{
7484 match( If cmp (CmpL src1 src2) );
7485 effect(USE labl);
7486 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_regL_regL" %}
7487 ins_cost(250);
7489 ins_encode %{
7490 Register opr1_reg = as_Register($src1$$reg);
7491 Register opr2_reg = as_Register($src2$$reg);
7493 Label &target = *($labl$$label);
7494 int flag = $cmp$$cmpcode;
7496 switch(flag)
7497 {
7498 case 0x01: //equal
7499 if (&target)
7500 __ beq(opr1_reg, opr2_reg, target);
7501 else
7502 __ beq(opr1_reg, opr2_reg, (int)0);
7503 __ delayed()->nop();
7504 break;
7506 case 0x02: //not_equal
7507 if(&target)
7508 __ bne(opr1_reg, opr2_reg, target);
7509 else
7510 __ bne(opr1_reg, opr2_reg, (int)0);
7511 __ delayed()->nop();
7512 break;
7514 case 0x03: //greater
7515 __ slt(AT, opr2_reg, opr1_reg);
7516 if(&target)
7517 __ bne(AT, R0, target);
7518 else
7519 __ bne(AT, R0, (int)0);
7520 __ delayed()->nop();
7521 break;
7523 case 0x04: //greater_equal
7524 __ slt(AT, opr1_reg, opr2_reg);
7525 if(&target)
7526 __ beq(AT, R0, target);
7527 else
7528 __ beq(AT, R0, (int)0);
7529 __ delayed()->nop();
7531 break;
7533 case 0x05: //less
7534 __ slt(AT, opr1_reg, opr2_reg);
7535 if(&target)
7536 __ bne(AT, R0, target);
7537 else
7538 __ bne(AT, R0, (int)0);
7539 __ delayed()->nop();
7541 break;
7543 case 0x06: //less_equal
7544 __ slt(AT, opr2_reg, opr1_reg);
7546 if(&target)
7547 __ beq(AT, R0, target);
7548 else
7549 __ beq(AT, R0, (int)0);
7550 __ delayed()->nop();
7552 break;
7554 default:
7555 Unimplemented();
7556 }
7557 %}
7560 ins_pc_relative(1);
7561 ins_pipe( pipe_alu_branch );
7562 %}
7564 instruct branchConL_reg_immL16_sub(cmpOp cmp, mRegL src1, immL16_sub src2, label labl) %{
7565 match( If cmp (CmpL src1 src2) );
7566 effect(USE labl);
7567 ins_cost(180);
7568 format %{ "BR$cmp $src1, $src2, $labl #@branchConL_reg_immL16_sub" %}
7570 ins_encode %{
7571 Register op1 = $src1$$Register;
7572 int val = $src2$$constant;
7573 Label &L = *($labl$$label);
7574 int flag = $cmp$$cmpcode;
7576 __ daddiu(AT, op1, -1 * val);
7577 switch(flag)
7578 {
7579 case 0x01: //equal
7580 if (&L)
7581 __ beq(R0, AT, L);
7582 else
7583 __ beq(R0, AT, (int)0);
7584 break;
7585 case 0x02: //not_equal
7586 if (&L)
7587 __ bne(R0, AT, L);
7588 else
7589 __ bne(R0, AT, (int)0);
7590 break;
7591 case 0x03: //greater
7592 if(&L)
7593 __ bgtz(AT, L);
7594 else
7595 __ bgtz(AT, (int)0);
7596 break;
7597 case 0x04: //greater_equal
7598 if(&L)
7599 __ bgez(AT, L);
7600 else
7601 __ bgez(AT, (int)0);
7602 break;
7603 case 0x05: //less
7604 if(&L)
7605 __ bltz(AT, L);
7606 else
7607 __ bltz(AT, (int)0);
7608 break;
7609 case 0x06: //less_equal
7610 if(&L)
7611 __ blez(AT, L);
7612 else
7613 __ blez(AT, (int)0);
7614 break;
7615 default:
7616 Unimplemented();
7617 }
7618 __ nop();
7619 %}
7621 ins_pc_relative(1);
7622 ins_pipe( pipe_alu_branch );
7623 %}
7626 instruct branchConI_reg_imm16_sub(cmpOp cmp, mRegI src1, immI16_sub src2, label labl) %{
7627 match( If cmp (CmpI src1 src2) );
7628 effect(USE labl);
7629 ins_cost(180);
7630 format %{ "BR$cmp $src1, $src2, $labl #@branchConI_reg_imm16_sub" %}
7632 ins_encode %{
7633 Register op1 = $src1$$Register;
7634 int val = $src2$$constant;
7635 Label &L = *($labl$$label);
7636 int flag = $cmp$$cmpcode;
7638 __ addiu32(AT, op1, -1 * val);
7639 switch(flag)
7640 {
7641 case 0x01: //equal
7642 if (&L)
7643 __ beq(R0, AT, L);
7644 else
7645 __ beq(R0, AT, (int)0);
7646 break;
7647 case 0x02: //not_equal
7648 if (&L)
7649 __ bne(R0, AT, L);
7650 else
7651 __ bne(R0, AT, (int)0);
7652 break;
7653 case 0x03: //greater
7654 if(&L)
7655 __ bgtz(AT, L);
7656 else
7657 __ bgtz(AT, (int)0);
7658 break;
7659 case 0x04: //greater_equal
7660 if(&L)
7661 __ bgez(AT, L);
7662 else
7663 __ bgez(AT, (int)0);
7664 break;
7665 case 0x05: //less
7666 if(&L)
7667 __ bltz(AT, L);
7668 else
7669 __ bltz(AT, (int)0);
7670 break;
7671 case 0x06: //less_equal
7672 if(&L)
7673 __ blez(AT, L);
7674 else
7675 __ blez(AT, (int)0);
7676 break;
7677 default:
7678 Unimplemented();
7679 }
7680 __ nop();
7681 %}
7683 ins_pc_relative(1);
7684 ins_pipe( pipe_alu_branch );
7685 %}
7687 instruct branchConL_regL_immL0(cmpOp cmp, mRegL src1, immL0 zero, label labl) %{
7688 match( If cmp (CmpL src1 zero) );
7689 effect(USE labl);
7690 format %{ "BR$cmp $src1, zero, $labl #@branchConL_regL_immL0" %}
7691 ins_cost(150);
7693 ins_encode %{
7694 Register opr1_reg = as_Register($src1$$reg);
7695 Label &target = *($labl$$label);
7696 int flag = $cmp$$cmpcode;
7698 switch(flag)
7699 {
7700 case 0x01: //equal
7701 if (&target)
7702 __ beq(opr1_reg, R0, target);
7703 else
7704 __ beq(opr1_reg, R0, int(0));
7705 break;
7707 case 0x02: //not_equal
7708 if(&target)
7709 __ bne(opr1_reg, R0, target);
7710 else
7711 __ bne(opr1_reg, R0, (int)0);
7712 break;
7714 case 0x03: //greater
7715 if(&target)
7716 __ bgtz(opr1_reg, target);
7717 else
7718 __ bgtz(opr1_reg, (int)0);
7719 break;
7721 case 0x04: //greater_equal
7722 if(&target)
7723 __ bgez(opr1_reg, target);
7724 else
7725 __ bgez(opr1_reg, (int)0);
7726 break;
7728 case 0x05: //less
7729 __ slt(AT, opr1_reg, R0);
7730 if(&target)
7731 __ bne(AT, R0, target);
7732 else
7733 __ bne(AT, R0, (int)0);
7734 break;
7736 case 0x06: //less_equal
7737 if (&target)
7738 __ blez(opr1_reg, target);
7739 else
7740 __ blez(opr1_reg, int(0));
7741 break;
7743 default:
7744 Unimplemented();
7745 }
7746 __ delayed()->nop();
7747 %}
7750 ins_pc_relative(1);
7751 ins_pipe( pipe_alu_branch );
7752 %}
7755 //FIXME
7756 instruct branchConF_reg_reg(cmpOp cmp, regF src1, regF src2, label labl) %{
7757 match( If cmp (CmpF src1 src2) );
7758 effect(USE labl);
7759 format %{ "BR$cmp $src1, $src2, $labl #@branchConF_reg_reg" %}
7761 ins_encode %{
7762 FloatRegister reg_op1 = $src1$$FloatRegister;
7763 FloatRegister reg_op2 = $src2$$FloatRegister;
7764 Label &L = *($labl$$label);
7765 int flag = $cmp$$cmpcode;
7767 switch(flag)
7768 {
7769 case 0x01: //equal
7770 __ c_eq_s(reg_op1, reg_op2);
7771 if (&L)
7772 __ bc1t(L);
7773 else
7774 __ bc1t((int)0);
7775 break;
7776 case 0x02: //not_equal
7777 __ c_eq_s(reg_op1, reg_op2);
7778 if (&L)
7779 __ bc1f(L);
7780 else
7781 __ bc1f((int)0);
7782 break;
7783 case 0x03: //greater
7784 __ c_ule_s(reg_op1, reg_op2);
7785 if(&L)
7786 __ bc1f(L);
7787 else
7788 __ bc1f((int)0);
7789 break;
7790 case 0x04: //greater_equal
7791 __ c_ult_s(reg_op1, reg_op2);
7792 if(&L)
7793 __ bc1f(L);
7794 else
7795 __ bc1f((int)0);
7796 break;
7797 case 0x05: //less
7798 __ c_ult_s(reg_op1, reg_op2);
7799 if(&L)
7800 __ bc1t(L);
7801 else
7802 __ bc1t((int)0);
7803 break;
7804 case 0x06: //less_equal
7805 __ c_ule_s(reg_op1, reg_op2);
7806 if(&L)
7807 __ bc1t(L);
7808 else
7809 __ bc1t((int)0);
7810 break;
7811 default:
7812 Unimplemented();
7813 }
7814 __ nop();
7815 %}
7817 ins_pc_relative(1);
7818 ins_pipe(pipe_slow);
7819 %}
7821 instruct branchConD_reg_reg(cmpOp cmp, regD src1, regD src2, label labl) %{
7822 match( If cmp (CmpD src1 src2) );
7823 effect(USE labl);
7824 format %{ "BR$cmp $src1, $src2, $labl #@branchConD_reg_reg" %}
7826 ins_encode %{
7827 FloatRegister reg_op1 = $src1$$FloatRegister;
7828 FloatRegister reg_op2 = $src2$$FloatRegister;
7829 Label &L = *($labl$$label);
7830 int flag = $cmp$$cmpcode;
7832 switch(flag)
7833 {
7834 case 0x01: //equal
7835 __ c_eq_d(reg_op1, reg_op2);
7836 if (&L)
7837 __ bc1t(L);
7838 else
7839 __ bc1t((int)0);
7840 break;
7841 case 0x02: //not_equal
7842 //2016/4/19 aoqi: c_ueq_d cannot distinguish NaN from equal. Double.isNaN(Double) is implemented by 'f != f', so the use of c_ueq_d causes bugs.
7843 __ c_eq_d(reg_op1, reg_op2);
7844 if (&L)
7845 __ bc1f(L);
7846 else
7847 __ bc1f((int)0);
7848 break;
7849 case 0x03: //greater
7850 __ c_ule_d(reg_op1, reg_op2);
7851 if(&L)
7852 __ bc1f(L);
7853 else
7854 __ bc1f((int)0);
7855 break;
7856 case 0x04: //greater_equal
7857 __ c_ult_d(reg_op1, reg_op2);
7858 if(&L)
7859 __ bc1f(L);
7860 else
7861 __ bc1f((int)0);
7862 break;
7863 case 0x05: //less
7864 __ c_ult_d(reg_op1, reg_op2);
7865 if(&L)
7866 __ bc1t(L);
7867 else
7868 __ bc1t((int)0);
7869 break;
7870 case 0x06: //less_equal
7871 __ c_ule_d(reg_op1, reg_op2);
7872 if(&L)
7873 __ bc1t(L);
7874 else
7875 __ bc1t((int)0);
7876 break;
7877 default:
7878 Unimplemented();
7879 }
7880 __ nop();
7881 %}
7883 ins_pc_relative(1);
7884 ins_pipe(pipe_slow);
7885 %}
7888 // Call Runtime Instruction
7889 instruct CallRuntimeDirect(method meth) %{
7890 match(CallRuntime );
7891 effect(USE meth);
7893 ins_cost(300);
7894 format %{ "CALL,runtime #@CallRuntimeDirect" %}
7895 ins_encode( Java_To_Runtime( meth ) );
7896 ins_pipe( pipe_slow );
7897 ins_alignment(16);
7898 %}
7902 //------------------------MemBar Instructions-------------------------------
7903 //Memory barrier flavors
7905 instruct membar_acquire() %{
7906 match(MemBarAcquire);
7907 ins_cost(0);
7909 size(0);
7910 format %{ "MEMBAR-acquire (empty) @ membar_acquire" %}
7911 ins_encode();
7912 ins_pipe(empty);
7913 %}
7915 instruct load_fence() %{
7916 match(LoadFence);
7917 ins_cost(400);
7919 format %{ "MEMBAR @ load_fence" %}
7920 ins_encode %{
7921 __ sync();
7922 %}
7923 ins_pipe(pipe_slow);
7924 %}
7926 instruct membar_acquire_lock()
7927 %{
7928 match(MemBarAcquireLock);
7929 ins_cost(0);
7931 size(0);
7932 format %{ "MEMBAR-acquire (acquire as part of CAS in prior FastLock so empty encoding) @ membar_acquire_lock" %}
7933 ins_encode();
7934 ins_pipe(empty);
7935 %}
7937 instruct membar_release() %{
7938 match(MemBarRelease);
7939 ins_cost(400);
7941 format %{ "MEMBAR-release @ membar_release" %}
7943 ins_encode %{
7944 // Attention: DO NOT DELETE THIS GUY!
7945 __ sync();
7946 %}
7948 ins_pipe(pipe_slow);
7949 %}
7951 instruct store_fence() %{
7952 match(StoreFence);
7953 ins_cost(400);
7955 format %{ "MEMBAR @ store_fence" %}
7957 ins_encode %{
7958 __ sync();
7959 %}
7961 ins_pipe(pipe_slow);
7962 %}
7964 instruct membar_release_lock()
7965 %{
7966 match(MemBarReleaseLock);
7967 ins_cost(0);
7969 size(0);
7970 format %{ "MEMBAR-release-lock (release in FastUnlock so empty) @ membar_release_lock" %}
7971 ins_encode();
7972 ins_pipe(empty);
7973 %}
7976 instruct membar_volatile() %{
7977 match(MemBarVolatile);
7978 ins_cost(400);
7980 format %{ "MEMBAR-volatile" %}
7981 ins_encode %{
7982 if( !os::is_MP() ) return; // Not needed on single CPU
7983 __ sync();
7985 %}
7986 ins_pipe(pipe_slow);
7987 %}
7989 instruct unnecessary_membar_volatile() %{
7990 match(MemBarVolatile);
7991 predicate(Matcher::post_store_load_barrier(n));
7992 ins_cost(0);
7994 size(0);
7995 format %{ "MEMBAR-volatile (unnecessary so empty encoding) @ unnecessary_membar_volatile" %}
7996 ins_encode( );
7997 ins_pipe(empty);
7998 %}
8000 instruct membar_storestore() %{
8001 match(MemBarStoreStore);
8003 ins_cost(0);
8004 size(0);
8005 format %{ "MEMBAR-storestore (empty encoding) @ membar_storestore" %}
8006 ins_encode( );
8007 ins_pipe(empty);
8008 %}
8010 //----------Move Instructions--------------------------------------------------
8011 instruct castX2P(mRegP dst, mRegL src) %{
8012 match(Set dst (CastX2P src));
8013 format %{ "castX2P $dst, $src @ castX2P" %}
8014 ins_encode %{
8015 Register src = $src$$Register;
8016 Register dst = $dst$$Register;
8018 if(src != dst)
8019 __ move(dst, src);
8020 %}
8021 ins_cost(10);
8022 ins_pipe( ialu_regI_mov );
8023 %}
8025 instruct castP2X(mRegL dst, mRegP src ) %{
8026 match(Set dst (CastP2X src));
8028 format %{ "mov $dst, $src\t #@castP2X" %}
8029 ins_encode %{
8030 Register src = $src$$Register;
8031 Register dst = $dst$$Register;
8033 if(src != dst)
8034 __ move(dst, src);
8035 %}
8036 ins_pipe( ialu_regI_mov );
8037 %}
8039 instruct MoveF2I_reg_reg(mRegI dst, regF src) %{
8040 match(Set dst (MoveF2I src));
8041 effect(DEF dst, USE src);
8042 ins_cost(85);
8043 format %{ "MoveF2I $dst, $src @ MoveF2I_reg_reg" %}
8044 ins_encode %{
8045 Register dst = as_Register($dst$$reg);
8046 FloatRegister src = as_FloatRegister($src$$reg);
8048 __ mfc1(dst, src);
8049 %}
8050 ins_pipe( pipe_slow );
8051 %}
8053 instruct MoveI2F_reg_reg(regF dst, mRegI src) %{
8054 match(Set dst (MoveI2F src));
8055 effect(DEF dst, USE src);
8056 ins_cost(85);
8057 format %{ "MoveI2F $dst, $src @ MoveI2F_reg_reg" %}
8058 ins_encode %{
8059 Register src = as_Register($src$$reg);
8060 FloatRegister dst = as_FloatRegister($dst$$reg);
8062 __ mtc1(src, dst);
8063 %}
8064 ins_pipe( pipe_slow );
8065 %}
8067 instruct MoveD2L_reg_reg(mRegL dst, regD src) %{
8068 match(Set dst (MoveD2L src));
8069 effect(DEF dst, USE src);
8070 ins_cost(85);
8071 format %{ "MoveD2L $dst, $src @ MoveD2L_reg_reg" %}
8072 ins_encode %{
8073 Register dst = as_Register($dst$$reg);
8074 FloatRegister src = as_FloatRegister($src$$reg);
8076 __ dmfc1(dst, src);
8077 %}
8078 ins_pipe( pipe_slow );
8079 %}
8081 instruct MoveL2D_reg_reg(regD dst, mRegL src) %{
8082 match(Set dst (MoveL2D src));
8083 effect(DEF dst, USE src);
8084 ins_cost(85);
8085 format %{ "MoveL2D $dst, $src @ MoveL2D_reg_reg" %}
8086 ins_encode %{
8087 FloatRegister dst = as_FloatRegister($dst$$reg);
8088 Register src = as_Register($src$$reg);
8090 __ dmtc1(src, dst);
8091 %}
8092 ins_pipe( pipe_slow );
8093 %}
8095 //----------Conditional Move---------------------------------------------------
8096 // Conditional move
8097 instruct cmovI_cmpI_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8098 match(Set dst (CMoveI (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8099 ins_cost(80);
8100 format %{
8101 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpI_reg_reg\n"
8102 "\tCMOV $dst,$src \t @cmovI_cmpI_reg_reg"
8103 %}
8105 ins_encode %{
8106 Register op1 = $tmp1$$Register;
8107 Register op2 = $tmp2$$Register;
8108 Register dst = $dst$$Register;
8109 Register src = $src$$Register;
8110 int flag = $cop$$cmpcode;
8112 switch(flag)
8113 {
8114 case 0x01: //equal
8115 __ subu32(AT, op1, op2);
8116 __ movz(dst, src, AT);
8117 break;
8119 case 0x02: //not_equal
8120 __ subu32(AT, op1, op2);
8121 __ movn(dst, src, AT);
8122 break;
8124 case 0x03: //great
8125 __ slt(AT, op2, op1);
8126 __ movn(dst, src, AT);
8127 break;
8129 case 0x04: //great_equal
8130 __ slt(AT, op1, op2);
8131 __ movz(dst, src, AT);
8132 break;
8134 case 0x05: //less
8135 __ slt(AT, op1, op2);
8136 __ movn(dst, src, AT);
8137 break;
8139 case 0x06: //less_equal
8140 __ slt(AT, op2, op1);
8141 __ movz(dst, src, AT);
8142 break;
8144 default:
8145 Unimplemented();
8146 }
8147 %}
8149 ins_pipe( pipe_slow );
8150 %}
8152 instruct cmovI_cmpP_reg_reg(mRegI dst, mRegI src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8153 match(Set dst (CMoveI (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8154 ins_cost(80);
8155 format %{
8156 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpP_reg_reg\n\t"
8157 "CMOV $dst,$src\t @cmovI_cmpP_reg_reg"
8158 %}
8159 ins_encode %{
8160 Register op1 = $tmp1$$Register;
8161 Register op2 = $tmp2$$Register;
8162 Register dst = $dst$$Register;
8163 Register src = $src$$Register;
8164 int flag = $cop$$cmpcode;
8166 switch(flag)
8167 {
8168 case 0x01: //equal
8169 __ subu(AT, op1, op2);
8170 __ movz(dst, src, AT);
8171 break;
8173 case 0x02: //not_equal
8174 __ subu(AT, op1, op2);
8175 __ movn(dst, src, AT);
8176 break;
8178 case 0x03: //above
8179 __ sltu(AT, op2, op1);
8180 __ movn(dst, src, AT);
8181 break;
8183 case 0x04: //above_equal
8184 __ sltu(AT, op1, op2);
8185 __ movz(dst, src, AT);
8186 break;
8188 case 0x05: //below
8189 __ sltu(AT, op1, op2);
8190 __ movn(dst, src, AT);
8191 break;
8193 case 0x06: //below_equal
8194 __ sltu(AT, op2, op1);
8195 __ movz(dst, src, AT);
8196 break;
8198 default:
8199 Unimplemented();
8200 }
8201 %}
8203 ins_pipe( pipe_slow );
8204 %}
8206 instruct cmovI_cmpN_reg_reg(mRegI dst, mRegI src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8207 match(Set dst (CMoveI (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8208 ins_cost(80);
8209 format %{
8210 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpN_reg_reg\n\t"
8211 "CMOV $dst,$src\t @cmovI_cmpN_reg_reg"
8212 %}
8213 ins_encode %{
8214 Register op1 = $tmp1$$Register;
8215 Register op2 = $tmp2$$Register;
8216 Register dst = $dst$$Register;
8217 Register src = $src$$Register;
8218 int flag = $cop$$cmpcode;
8220 switch(flag)
8221 {
8222 case 0x01: //equal
8223 __ subu32(AT, op1, op2);
8224 __ movz(dst, src, AT);
8225 break;
8227 case 0x02: //not_equal
8228 __ subu32(AT, op1, op2);
8229 __ movn(dst, src, AT);
8230 break;
8232 case 0x03: //above
8233 __ sltu(AT, op2, op1);
8234 __ movn(dst, src, AT);
8235 break;
8237 case 0x04: //above_equal
8238 __ sltu(AT, op1, op2);
8239 __ movz(dst, src, AT);
8240 break;
8242 case 0x05: //below
8243 __ sltu(AT, op1, op2);
8244 __ movn(dst, src, AT);
8245 break;
8247 case 0x06: //below_equal
8248 __ sltu(AT, op2, op1);
8249 __ movz(dst, src, AT);
8250 break;
8252 default:
8253 Unimplemented();
8254 }
8255 %}
8257 ins_pipe( pipe_slow );
8258 %}
8260 instruct cmovP_cmpN_reg_reg(mRegP dst, mRegP src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8261 match(Set dst (CMoveP (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8262 ins_cost(80);
8263 format %{
8264 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpN_reg_reg\n\t"
8265 "CMOV $dst,$src\t @cmovP_cmpN_reg_reg"
8266 %}
8267 ins_encode %{
8268 Register op1 = $tmp1$$Register;
8269 Register op2 = $tmp2$$Register;
8270 Register dst = $dst$$Register;
8271 Register src = $src$$Register;
8272 int flag = $cop$$cmpcode;
8274 switch(flag)
8275 {
8276 case 0x01: //equal
8277 __ subu32(AT, op1, op2);
8278 __ movz(dst, src, AT);
8279 break;
8281 case 0x02: //not_equal
8282 __ subu32(AT, op1, op2);
8283 __ movn(dst, src, AT);
8284 break;
8286 case 0x03: //above
8287 __ sltu(AT, op2, op1);
8288 __ movn(dst, src, AT);
8289 break;
8291 case 0x04: //above_equal
8292 __ sltu(AT, op1, op2);
8293 __ movz(dst, src, AT);
8294 break;
8296 case 0x05: //below
8297 __ sltu(AT, op1, op2);
8298 __ movn(dst, src, AT);
8299 break;
8301 case 0x06: //below_equal
8302 __ sltu(AT, op2, op1);
8303 __ movz(dst, src, AT);
8304 break;
8306 default:
8307 Unimplemented();
8308 }
8309 %}
8311 ins_pipe( pipe_slow );
8312 %}
8314 instruct cmovN_cmpP_reg_reg(mRegN dst, mRegN src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8315 match(Set dst (CMoveN (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8316 ins_cost(80);
8317 format %{
8318 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpP_reg_reg\n\t"
8319 "CMOV $dst,$src\t @cmovN_cmpP_reg_reg"
8320 %}
8321 ins_encode %{
8322 Register op1 = $tmp1$$Register;
8323 Register op2 = $tmp2$$Register;
8324 Register dst = $dst$$Register;
8325 Register src = $src$$Register;
8326 int flag = $cop$$cmpcode;
8328 switch(flag)
8329 {
8330 case 0x01: //equal
8331 __ subu(AT, op1, op2);
8332 __ movz(dst, src, AT);
8333 break;
8335 case 0x02: //not_equal
8336 __ subu(AT, op1, op2);
8337 __ movn(dst, src, AT);
8338 break;
8340 case 0x03: //above
8341 __ sltu(AT, op2, op1);
8342 __ movn(dst, src, AT);
8343 break;
8345 case 0x04: //above_equal
8346 __ sltu(AT, op1, op2);
8347 __ movz(dst, src, AT);
8348 break;
8350 case 0x05: //below
8351 __ sltu(AT, op1, op2);
8352 __ movn(dst, src, AT);
8353 break;
8355 case 0x06: //below_equal
8356 __ sltu(AT, op2, op1);
8357 __ movz(dst, src, AT);
8358 break;
8360 default:
8361 Unimplemented();
8362 }
8363 %}
8365 ins_pipe( pipe_slow );
8366 %}
8368 instruct cmovP_cmpD_reg_reg(mRegP dst, mRegP src, regD tmp1, regD tmp2, cmpOp cop ) %{
8369 match(Set dst (CMoveP (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8370 ins_cost(80);
8371 format %{
8372 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpD_reg_reg\n"
8373 "\tCMOV $dst,$src \t @cmovP_cmpD_reg_reg"
8374 %}
8375 ins_encode %{
8376 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8377 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8378 Register dst = as_Register($dst$$reg);
8379 Register src = as_Register($src$$reg);
8381 int flag = $cop$$cmpcode;
8383 switch(flag)
8384 {
8385 case 0x01: //equal
8386 __ c_eq_d(reg_op1, reg_op2);
8387 __ movt(dst, src);
8388 break;
8389 case 0x02: //not_equal
8390 __ c_eq_d(reg_op1, reg_op2);
8391 __ movf(dst, src);
8392 break;
8393 case 0x03: //greater
8394 __ c_ole_d(reg_op1, reg_op2);
8395 __ movf(dst, src);
8396 break;
8397 case 0x04: //greater_equal
8398 __ c_olt_d(reg_op1, reg_op2);
8399 __ movf(dst, src);
8400 break;
8401 case 0x05: //less
8402 __ c_ult_d(reg_op1, reg_op2);
8403 __ movt(dst, src);
8404 break;
8405 case 0x06: //less_equal
8406 __ c_ule_d(reg_op1, reg_op2);
8407 __ movt(dst, src);
8408 break;
8409 default:
8410 Unimplemented();
8411 }
8412 %}
8414 ins_pipe( pipe_slow );
8415 %}
8418 instruct cmovN_cmpN_reg_reg(mRegN dst, mRegN src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8419 match(Set dst (CMoveN (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8420 ins_cost(80);
8421 format %{
8422 "CMPU$cop $tmp1,$tmp2\t @cmovN_cmpN_reg_reg\n\t"
8423 "CMOV $dst,$src\t @cmovN_cmpN_reg_reg"
8424 %}
8425 ins_encode %{
8426 Register op1 = $tmp1$$Register;
8427 Register op2 = $tmp2$$Register;
8428 Register dst = $dst$$Register;
8429 Register src = $src$$Register;
8430 int flag = $cop$$cmpcode;
8432 switch(flag)
8433 {
8434 case 0x01: //equal
8435 __ subu32(AT, op1, op2);
8436 __ movz(dst, src, AT);
8437 break;
8439 case 0x02: //not_equal
8440 __ subu32(AT, op1, op2);
8441 __ movn(dst, src, AT);
8442 break;
8444 case 0x03: //above
8445 __ sltu(AT, op2, op1);
8446 __ movn(dst, src, AT);
8447 break;
8449 case 0x04: //above_equal
8450 __ sltu(AT, op1, op2);
8451 __ movz(dst, src, AT);
8452 break;
8454 case 0x05: //below
8455 __ sltu(AT, op1, op2);
8456 __ movn(dst, src, AT);
8457 break;
8459 case 0x06: //below_equal
8460 __ sltu(AT, op2, op1);
8461 __ movz(dst, src, AT);
8462 break;
8464 default:
8465 Unimplemented();
8466 }
8467 %}
8469 ins_pipe( pipe_slow );
8470 %}
8473 instruct cmovI_cmpU_reg_reg(mRegI dst, mRegI src, mRegI tmp1, mRegI tmp2, cmpOpU cop ) %{
8474 match(Set dst (CMoveI (Binary cop (CmpU tmp1 tmp2)) (Binary dst src)));
8475 ins_cost(80);
8476 format %{
8477 "CMPU$cop $tmp1,$tmp2\t @cmovI_cmpU_reg_reg\n\t"
8478 "CMOV $dst,$src\t @cmovI_cmpU_reg_reg"
8479 %}
8480 ins_encode %{
8481 Register op1 = $tmp1$$Register;
8482 Register op2 = $tmp2$$Register;
8483 Register dst = $dst$$Register;
8484 Register src = $src$$Register;
8485 int flag = $cop$$cmpcode;
8487 switch(flag)
8488 {
8489 case 0x01: //equal
8490 __ subu(AT, op1, op2);
8491 __ movz(dst, src, AT);
8492 break;
8494 case 0x02: //not_equal
8495 __ subu(AT, op1, op2);
8496 __ movn(dst, src, AT);
8497 break;
8499 case 0x03: //above
8500 __ sltu(AT, op2, op1);
8501 __ movn(dst, src, AT);
8502 break;
8504 case 0x04: //above_equal
8505 __ sltu(AT, op1, op2);
8506 __ movz(dst, src, AT);
8507 break;
8509 case 0x05: //below
8510 __ sltu(AT, op1, op2);
8511 __ movn(dst, src, AT);
8512 break;
8514 case 0x06: //below_equal
8515 __ sltu(AT, op2, op1);
8516 __ movz(dst, src, AT);
8517 break;
8519 default:
8520 Unimplemented();
8521 }
8522 %}
8524 ins_pipe( pipe_slow );
8525 %}
8527 instruct cmovI_cmpL_reg_reg(mRegI dst, mRegI src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8528 match(Set dst (CMoveI (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8529 ins_cost(80);
8530 format %{
8531 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpL_reg_reg\n"
8532 "\tCMOV $dst,$src \t @cmovI_cmpL_reg_reg"
8533 %}
8534 ins_encode %{
8535 Register opr1 = as_Register($tmp1$$reg);
8536 Register opr2 = as_Register($tmp2$$reg);
8537 Register dst = $dst$$Register;
8538 Register src = $src$$Register;
8539 int flag = $cop$$cmpcode;
8541 switch(flag)
8542 {
8543 case 0x01: //equal
8544 __ subu(AT, opr1, opr2);
8545 __ movz(dst, src, AT);
8546 break;
8548 case 0x02: //not_equal
8549 __ subu(AT, opr1, opr2);
8550 __ movn(dst, src, AT);
8551 break;
8553 case 0x03: //greater
8554 __ slt(AT, opr2, opr1);
8555 __ movn(dst, src, AT);
8556 break;
8558 case 0x04: //greater_equal
8559 __ slt(AT, opr1, opr2);
8560 __ movz(dst, src, AT);
8561 break;
8563 case 0x05: //less
8564 __ slt(AT, opr1, opr2);
8565 __ movn(dst, src, AT);
8566 break;
8568 case 0x06: //less_equal
8569 __ slt(AT, opr2, opr1);
8570 __ movz(dst, src, AT);
8571 break;
8573 default:
8574 Unimplemented();
8575 }
8576 %}
8578 ins_pipe( pipe_slow );
8579 %}
8581 instruct cmovP_cmpL_reg_reg(mRegP dst, mRegP src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8582 match(Set dst (CMoveP (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8583 ins_cost(80);
8584 format %{
8585 "CMP$cop $tmp1, $tmp2\t @cmovP_cmpL_reg_reg\n"
8586 "\tCMOV $dst,$src \t @cmovP_cmpL_reg_reg"
8587 %}
8588 ins_encode %{
8589 Register opr1 = as_Register($tmp1$$reg);
8590 Register opr2 = as_Register($tmp2$$reg);
8591 Register dst = $dst$$Register;
8592 Register src = $src$$Register;
8593 int flag = $cop$$cmpcode;
8595 switch(flag)
8596 {
8597 case 0x01: //equal
8598 __ subu(AT, opr1, opr2);
8599 __ movz(dst, src, AT);
8600 break;
8602 case 0x02: //not_equal
8603 __ subu(AT, opr1, opr2);
8604 __ movn(dst, src, AT);
8605 break;
8607 case 0x03: //greater
8608 __ slt(AT, opr2, opr1);
8609 __ movn(dst, src, AT);
8610 break;
8612 case 0x04: //greater_equal
8613 __ slt(AT, opr1, opr2);
8614 __ movz(dst, src, AT);
8615 break;
8617 case 0x05: //less
8618 __ slt(AT, opr1, opr2);
8619 __ movn(dst, src, AT);
8620 break;
8622 case 0x06: //less_equal
8623 __ slt(AT, opr2, opr1);
8624 __ movz(dst, src, AT);
8625 break;
8627 default:
8628 Unimplemented();
8629 }
8630 %}
8632 ins_pipe( pipe_slow );
8633 %}
8635 instruct cmovI_cmpD_reg_reg(mRegI dst, mRegI src, regD tmp1, regD tmp2, cmpOp cop ) %{
8636 match(Set dst (CMoveI (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
8637 ins_cost(80);
8638 format %{
8639 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpD_reg_reg\n"
8640 "\tCMOV $dst,$src \t @cmovI_cmpD_reg_reg"
8641 %}
8642 ins_encode %{
8643 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
8644 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
8645 Register dst = as_Register($dst$$reg);
8646 Register src = as_Register($src$$reg);
8648 int flag = $cop$$cmpcode;
8650 switch(flag)
8651 {
8652 case 0x01: //equal
8653 __ c_eq_d(reg_op1, reg_op2);
8654 __ movt(dst, src);
8655 break;
8656 case 0x02: //not_equal
8657 //2016/4/19 aoqi: See instruct branchConD_reg_reg. The change in branchConD_reg_reg fixed a bug. It seems similar here, so I made thesame change.
8658 __ c_eq_d(reg_op1, reg_op2);
8659 __ movf(dst, src);
8660 break;
8661 case 0x03: //greater
8662 __ c_ole_d(reg_op1, reg_op2);
8663 __ movf(dst, src);
8664 break;
8665 case 0x04: //greater_equal
8666 __ c_olt_d(reg_op1, reg_op2);
8667 __ movf(dst, src);
8668 break;
8669 case 0x05: //less
8670 __ c_ult_d(reg_op1, reg_op2);
8671 __ movt(dst, src);
8672 break;
8673 case 0x06: //less_equal
8674 __ c_ule_d(reg_op1, reg_op2);
8675 __ movt(dst, src);
8676 break;
8677 default:
8678 Unimplemented();
8679 }
8680 %}
8682 ins_pipe( pipe_slow );
8683 %}
8686 instruct cmovP_cmpP_reg_reg(mRegP dst, mRegP src, mRegP tmp1, mRegP tmp2, cmpOpU cop ) %{
8687 match(Set dst (CMoveP (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
8688 ins_cost(80);
8689 format %{
8690 "CMPU$cop $tmp1,$tmp2\t @cmovP_cmpP_reg_reg\n\t"
8691 "CMOV $dst,$src\t @cmovP_cmpP_reg_reg"
8692 %}
8693 ins_encode %{
8694 Register op1 = $tmp1$$Register;
8695 Register op2 = $tmp2$$Register;
8696 Register dst = $dst$$Register;
8697 Register src = $src$$Register;
8698 int flag = $cop$$cmpcode;
8700 switch(flag)
8701 {
8702 case 0x01: //equal
8703 __ subu(AT, op1, op2);
8704 __ movz(dst, src, AT);
8705 break;
8707 case 0x02: //not_equal
8708 __ subu(AT, op1, op2);
8709 __ movn(dst, src, AT);
8710 break;
8712 case 0x03: //above
8713 __ sltu(AT, op2, op1);
8714 __ movn(dst, src, AT);
8715 break;
8717 case 0x04: //above_equal
8718 __ sltu(AT, op1, op2);
8719 __ movz(dst, src, AT);
8720 break;
8722 case 0x05: //below
8723 __ sltu(AT, op1, op2);
8724 __ movn(dst, src, AT);
8725 break;
8727 case 0x06: //below_equal
8728 __ sltu(AT, op2, op1);
8729 __ movz(dst, src, AT);
8730 break;
8732 default:
8733 Unimplemented();
8734 }
8735 %}
8737 ins_pipe( pipe_slow );
8738 %}
8740 instruct cmovP_cmpI_reg_reg(mRegP dst, mRegP src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8741 match(Set dst (CMoveP (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8742 ins_cost(80);
8743 format %{
8744 "CMP$cop $tmp1,$tmp2\t @cmovP_cmpI_reg_reg\n\t"
8745 "CMOV $dst,$src\t @cmovP_cmpI_reg_reg"
8746 %}
8747 ins_encode %{
8748 Register op1 = $tmp1$$Register;
8749 Register op2 = $tmp2$$Register;
8750 Register dst = $dst$$Register;
8751 Register src = $src$$Register;
8752 int flag = $cop$$cmpcode;
8754 switch(flag)
8755 {
8756 case 0x01: //equal
8757 __ subu32(AT, op1, op2);
8758 __ movz(dst, src, AT);
8759 break;
8761 case 0x02: //not_equal
8762 __ subu32(AT, op1, op2);
8763 __ movn(dst, src, AT);
8764 break;
8766 case 0x03: //above
8767 __ slt(AT, op2, op1);
8768 __ movn(dst, src, AT);
8769 break;
8771 case 0x04: //above_equal
8772 __ slt(AT, op1, op2);
8773 __ movz(dst, src, AT);
8774 break;
8776 case 0x05: //below
8777 __ slt(AT, op1, op2);
8778 __ movn(dst, src, AT);
8779 break;
8781 case 0x06: //below_equal
8782 __ slt(AT, op2, op1);
8783 __ movz(dst, src, AT);
8784 break;
8786 default:
8787 Unimplemented();
8788 }
8789 %}
8791 ins_pipe( pipe_slow );
8792 %}
8794 instruct cmovN_cmpI_reg_reg(mRegN dst, mRegN src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8795 match(Set dst (CMoveN (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8796 ins_cost(80);
8797 format %{
8798 "CMP$cop $tmp1,$tmp2\t @cmovN_cmpI_reg_reg\n\t"
8799 "CMOV $dst,$src\t @cmovN_cmpI_reg_reg"
8800 %}
8801 ins_encode %{
8802 Register op1 = $tmp1$$Register;
8803 Register op2 = $tmp2$$Register;
8804 Register dst = $dst$$Register;
8805 Register src = $src$$Register;
8806 int flag = $cop$$cmpcode;
8808 switch(flag)
8809 {
8810 case 0x01: //equal
8811 __ subu32(AT, op1, op2);
8812 __ movz(dst, src, AT);
8813 break;
8815 case 0x02: //not_equal
8816 __ subu32(AT, op1, op2);
8817 __ movn(dst, src, AT);
8818 break;
8820 case 0x03: //above
8821 __ slt(AT, op2, op1);
8822 __ movn(dst, src, AT);
8823 break;
8825 case 0x04: //above_equal
8826 __ slt(AT, op1, op2);
8827 __ movz(dst, src, AT);
8828 break;
8830 case 0x05: //below
8831 __ slt(AT, op1, op2);
8832 __ movn(dst, src, AT);
8833 break;
8835 case 0x06: //below_equal
8836 __ slt(AT, op2, op1);
8837 __ movz(dst, src, AT);
8838 break;
8840 default:
8841 Unimplemented();
8842 }
8843 %}
8845 ins_pipe( pipe_slow );
8846 %}
8849 instruct cmovL_cmpI_reg_reg(mRegL dst, mRegL src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
8850 match(Set dst (CMoveL (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
8851 ins_cost(80);
8852 format %{
8853 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpI_reg_reg\n"
8854 "\tCMOV $dst,$src \t @cmovL_cmpI_reg_reg"
8855 %}
8857 ins_encode %{
8858 Register op1 = $tmp1$$Register;
8859 Register op2 = $tmp2$$Register;
8860 Register dst = as_Register($dst$$reg);
8861 Register src = as_Register($src$$reg);
8862 int flag = $cop$$cmpcode;
8864 switch(flag)
8865 {
8866 case 0x01: //equal
8867 __ subu32(AT, op1, op2);
8868 __ movz(dst, src, AT);
8869 break;
8871 case 0x02: //not_equal
8872 __ subu32(AT, op1, op2);
8873 __ movn(dst, src, AT);
8874 break;
8876 case 0x03: //great
8877 __ slt(AT, op2, op1);
8878 __ movn(dst, src, AT);
8879 break;
8881 case 0x04: //great_equal
8882 __ slt(AT, op1, op2);
8883 __ movz(dst, src, AT);
8884 break;
8886 case 0x05: //less
8887 __ slt(AT, op1, op2);
8888 __ movn(dst, src, AT);
8889 break;
8891 case 0x06: //less_equal
8892 __ slt(AT, op2, op1);
8893 __ movz(dst, src, AT);
8894 break;
8896 default:
8897 Unimplemented();
8898 }
8899 %}
8901 ins_pipe( pipe_slow );
8902 %}
8904 instruct cmovL_cmpL_reg_reg(mRegL dst, mRegL src, mRegL tmp1, mRegL tmp2, cmpOp cop ) %{
8905 match(Set dst (CMoveL (Binary cop (CmpL tmp1 tmp2)) (Binary dst src)));
8906 ins_cost(80);
8907 format %{
8908 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpL_reg_reg\n"
8909 "\tCMOV $dst,$src \t @cmovL_cmpL_reg_reg"
8910 %}
8911 ins_encode %{
8912 Register opr1 = as_Register($tmp1$$reg);
8913 Register opr2 = as_Register($tmp2$$reg);
8914 Register dst = as_Register($dst$$reg);
8915 Register src = as_Register($src$$reg);
8916 int flag = $cop$$cmpcode;
8918 switch(flag)
8919 {
8920 case 0x01: //equal
8921 __ subu(AT, opr1, opr2);
8922 __ movz(dst, src, AT);
8923 break;
8925 case 0x02: //not_equal
8926 __ subu(AT, opr1, opr2);
8927 __ movn(dst, src, AT);
8928 break;
8930 case 0x03: //greater
8931 __ slt(AT, opr2, opr1);
8932 __ movn(dst, src, AT);
8933 break;
8935 case 0x04: //greater_equal
8936 __ slt(AT, opr1, opr2);
8937 __ movz(dst, src, AT);
8938 break;
8940 case 0x05: //less
8941 __ slt(AT, opr1, opr2);
8942 __ movn(dst, src, AT);
8943 break;
8945 case 0x06: //less_equal
8946 __ slt(AT, opr2, opr1);
8947 __ movz(dst, src, AT);
8948 break;
8950 default:
8951 Unimplemented();
8952 }
8953 %}
8955 ins_pipe( pipe_slow );
8956 %}
8958 instruct cmovL_cmpN_reg_reg(mRegL dst, mRegL src, mRegN tmp1, mRegN tmp2, cmpOpU cop ) %{
8959 match(Set dst (CMoveL (Binary cop (CmpN tmp1 tmp2)) (Binary dst src)));
8960 ins_cost(80);
8961 format %{
8962 "CMPU$cop $tmp1,$tmp2\t @cmovL_cmpN_reg_reg\n\t"
8963 "CMOV $dst,$src\t @cmovL_cmpN_reg_reg"
8964 %}
8965 ins_encode %{
8966 Register op1 = $tmp1$$Register;
8967 Register op2 = $tmp2$$Register;
8968 Register dst = $dst$$Register;
8969 Register src = $src$$Register;
8970 int flag = $cop$$cmpcode;
8972 switch(flag)
8973 {
8974 case 0x01: //equal
8975 __ subu32(AT, op1, op2);
8976 __ movz(dst, src, AT);
8977 break;
8979 case 0x02: //not_equal
8980 __ subu32(AT, op1, op2);
8981 __ movn(dst, src, AT);
8982 break;
8984 case 0x03: //above
8985 __ sltu(AT, op2, op1);
8986 __ movn(dst, src, AT);
8987 break;
8989 case 0x04: //above_equal
8990 __ sltu(AT, op1, op2);
8991 __ movz(dst, src, AT);
8992 break;
8994 case 0x05: //below
8995 __ sltu(AT, op1, op2);
8996 __ movn(dst, src, AT);
8997 break;
8999 case 0x06: //below_equal
9000 __ sltu(AT, op2, op1);
9001 __ movz(dst, src, AT);
9002 break;
9004 default:
9005 Unimplemented();
9006 }
9007 %}
9009 ins_pipe( pipe_slow );
9010 %}
9013 instruct cmovL_cmpD_reg_reg(mRegL dst, mRegL src, regD tmp1, regD tmp2, cmpOp cop ) %{
9014 match(Set dst (CMoveL (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9015 ins_cost(80);
9016 format %{
9017 "CMP$cop $tmp1, $tmp2\t @cmovL_cmpD_reg_reg\n"
9018 "\tCMOV $dst,$src \t @cmovL_cmpD_reg_reg"
9019 %}
9020 ins_encode %{
9021 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9022 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9023 Register dst = as_Register($dst$$reg);
9024 Register src = as_Register($src$$reg);
9026 int flag = $cop$$cmpcode;
9028 switch(flag)
9029 {
9030 case 0x01: //equal
9031 __ c_eq_d(reg_op1, reg_op2);
9032 __ movt(dst, src);
9033 break;
9034 case 0x02: //not_equal
9035 __ c_eq_d(reg_op1, reg_op2);
9036 __ movf(dst, src);
9037 break;
9038 case 0x03: //greater
9039 __ c_ole_d(reg_op1, reg_op2);
9040 __ movf(dst, src);
9041 break;
9042 case 0x04: //greater_equal
9043 __ c_olt_d(reg_op1, reg_op2);
9044 __ movf(dst, src);
9045 break;
9046 case 0x05: //less
9047 __ c_ult_d(reg_op1, reg_op2);
9048 __ movt(dst, src);
9049 break;
9050 case 0x06: //less_equal
9051 __ c_ule_d(reg_op1, reg_op2);
9052 __ movt(dst, src);
9053 break;
9054 default:
9055 Unimplemented();
9056 }
9057 %}
9059 ins_pipe( pipe_slow );
9060 %}
9062 instruct cmovD_cmpD_reg_reg(regD dst, regD src, regD tmp1, regD tmp2, cmpOp cop ) %{
9063 match(Set dst (CMoveD (Binary cop (CmpD tmp1 tmp2)) (Binary dst src)));
9064 ins_cost(200);
9065 format %{
9066 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpD_reg_reg\n"
9067 "\tCMOV $dst,$src \t @cmovD_cmpD_reg_reg"
9068 %}
9069 ins_encode %{
9070 FloatRegister reg_op1 = as_FloatRegister($tmp1$$reg);
9071 FloatRegister reg_op2 = as_FloatRegister($tmp2$$reg);
9072 FloatRegister dst = as_FloatRegister($dst$$reg);
9073 FloatRegister src = as_FloatRegister($src$$reg);
9075 int flag = $cop$$cmpcode;
9077 switch(flag)
9078 {
9079 case 0x01: //equal
9080 __ c_eq_d(reg_op1, reg_op2);
9081 __ movt_d(dst, src);
9082 break;
9083 case 0x02: //not_equal
9084 __ c_eq_d(reg_op1, reg_op2);
9085 __ movf_d(dst, src);
9086 break;
9087 case 0x03: //greater
9088 __ c_ole_d(reg_op1, reg_op2);
9089 __ movf_d(dst, src);
9090 break;
9091 case 0x04: //greater_equal
9092 __ c_olt_d(reg_op1, reg_op2);
9093 __ movf_d(dst, src);
9094 break;
9095 case 0x05: //less
9096 __ c_ult_d(reg_op1, reg_op2);
9097 __ movt_d(dst, src);
9098 break;
9099 case 0x06: //less_equal
9100 __ c_ule_d(reg_op1, reg_op2);
9101 __ movt_d(dst, src);
9102 break;
9103 default:
9104 Unimplemented();
9105 }
9106 %}
9108 ins_pipe( pipe_slow );
9109 %}
9111 instruct cmovF_cmpI_reg_reg(regF dst, regF src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9112 match(Set dst (CMoveF (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9113 ins_cost(200);
9114 format %{
9115 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpI_reg_reg\n"
9116 "\tCMOV $dst, $src \t @cmovF_cmpI_reg_reg"
9117 %}
9119 ins_encode %{
9120 Register op1 = $tmp1$$Register;
9121 Register op2 = $tmp2$$Register;
9122 FloatRegister dst = as_FloatRegister($dst$$reg);
9123 FloatRegister src = as_FloatRegister($src$$reg);
9124 int flag = $cop$$cmpcode;
9125 Label L;
9127 switch(flag)
9128 {
9129 case 0x01: //equal
9130 __ bne(op1, op2, L);
9131 __ nop();
9132 __ mov_s(dst, src);
9133 __ bind(L);
9134 break;
9135 case 0x02: //not_equal
9136 __ beq(op1, op2, L);
9137 __ nop();
9138 __ mov_s(dst, src);
9139 __ bind(L);
9140 break;
9141 case 0x03: //great
9142 __ slt(AT, op2, op1);
9143 __ beq(AT, R0, L);
9144 __ nop();
9145 __ mov_s(dst, src);
9146 __ bind(L);
9147 break;
9148 case 0x04: //great_equal
9149 __ slt(AT, op1, op2);
9150 __ bne(AT, R0, L);
9151 __ nop();
9152 __ mov_s(dst, src);
9153 __ bind(L);
9154 break;
9155 case 0x05: //less
9156 __ slt(AT, op1, op2);
9157 __ beq(AT, R0, L);
9158 __ nop();
9159 __ mov_s(dst, src);
9160 __ bind(L);
9161 break;
9162 case 0x06: //less_equal
9163 __ slt(AT, op2, op1);
9164 __ bne(AT, R0, L);
9165 __ nop();
9166 __ mov_s(dst, src);
9167 __ bind(L);
9168 break;
9169 default:
9170 Unimplemented();
9171 }
9172 %}
9174 ins_pipe( pipe_slow );
9175 %}
9177 instruct cmovD_cmpI_reg_reg(regD dst, regD src, mRegI tmp1, mRegI tmp2, cmpOp cop ) %{
9178 match(Set dst (CMoveD (Binary cop (CmpI tmp1 tmp2)) (Binary dst src)));
9179 ins_cost(200);
9180 format %{
9181 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpI_reg_reg\n"
9182 "\tCMOV $dst, $src \t @cmovD_cmpI_reg_reg"
9183 %}
9185 ins_encode %{
9186 Register op1 = $tmp1$$Register;
9187 Register op2 = $tmp2$$Register;
9188 FloatRegister dst = as_FloatRegister($dst$$reg);
9189 FloatRegister src = as_FloatRegister($src$$reg);
9190 int flag = $cop$$cmpcode;
9191 Label L;
9193 switch(flag)
9194 {
9195 case 0x01: //equal
9196 __ bne(op1, op2, L);
9197 __ nop();
9198 __ mov_d(dst, src);
9199 __ bind(L);
9200 break;
9201 case 0x02: //not_equal
9202 __ beq(op1, op2, L);
9203 __ nop();
9204 __ mov_d(dst, src);
9205 __ bind(L);
9206 break;
9207 case 0x03: //great
9208 __ slt(AT, op2, op1);
9209 __ beq(AT, R0, L);
9210 __ nop();
9211 __ mov_d(dst, src);
9212 __ bind(L);
9213 break;
9214 case 0x04: //great_equal
9215 __ slt(AT, op1, op2);
9216 __ bne(AT, R0, L);
9217 __ nop();
9218 __ mov_d(dst, src);
9219 __ bind(L);
9220 break;
9221 case 0x05: //less
9222 __ slt(AT, op1, op2);
9223 __ beq(AT, R0, L);
9224 __ nop();
9225 __ mov_d(dst, src);
9226 __ bind(L);
9227 break;
9228 case 0x06: //less_equal
9229 __ slt(AT, op2, op1);
9230 __ bne(AT, R0, L);
9231 __ nop();
9232 __ mov_d(dst, src);
9233 __ bind(L);
9234 break;
9235 default:
9236 Unimplemented();
9237 }
9238 %}
9240 ins_pipe( pipe_slow );
9241 %}
9243 instruct cmovD_cmpP_reg_reg(regD dst, regD src, mRegP tmp1, mRegP tmp2, cmpOp cop ) %{
9244 match(Set dst (CMoveD (Binary cop (CmpP tmp1 tmp2)) (Binary dst src)));
9245 ins_cost(200);
9246 format %{
9247 "CMP$cop $tmp1, $tmp2\t @cmovD_cmpP_reg_reg\n"
9248 "\tCMOV $dst, $src \t @cmovD_cmpP_reg_reg"
9249 %}
9251 ins_encode %{
9252 Register op1 = $tmp1$$Register;
9253 Register op2 = $tmp2$$Register;
9254 FloatRegister dst = as_FloatRegister($dst$$reg);
9255 FloatRegister src = as_FloatRegister($src$$reg);
9256 int flag = $cop$$cmpcode;
9257 Label L;
9259 switch(flag)
9260 {
9261 case 0x01: //equal
9262 __ bne(op1, op2, L);
9263 __ nop();
9264 __ mov_d(dst, src);
9265 __ bind(L);
9266 break;
9267 case 0x02: //not_equal
9268 __ beq(op1, op2, L);
9269 __ nop();
9270 __ mov_d(dst, src);
9271 __ bind(L);
9272 break;
9273 case 0x03: //great
9274 __ slt(AT, op2, op1);
9275 __ beq(AT, R0, L);
9276 __ nop();
9277 __ mov_d(dst, src);
9278 __ bind(L);
9279 break;
9280 case 0x04: //great_equal
9281 __ slt(AT, op1, op2);
9282 __ bne(AT, R0, L);
9283 __ nop();
9284 __ mov_d(dst, src);
9285 __ bind(L);
9286 break;
9287 case 0x05: //less
9288 __ slt(AT, op1, op2);
9289 __ beq(AT, R0, L);
9290 __ nop();
9291 __ mov_d(dst, src);
9292 __ bind(L);
9293 break;
9294 case 0x06: //less_equal
9295 __ slt(AT, op2, op1);
9296 __ bne(AT, R0, L);
9297 __ nop();
9298 __ mov_d(dst, src);
9299 __ bind(L);
9300 break;
9301 default:
9302 Unimplemented();
9303 }
9304 %}
9306 ins_pipe( pipe_slow );
9307 %}
9309 //FIXME
9310 instruct cmovI_cmpF_reg_reg(mRegI dst, mRegI src, regF tmp1, regF tmp2, cmpOp cop ) %{
9311 match(Set dst (CMoveI (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9312 ins_cost(80);
9313 format %{
9314 "CMP$cop $tmp1, $tmp2\t @cmovI_cmpF_reg_reg\n"
9315 "\tCMOV $dst,$src \t @cmovI_cmpF_reg_reg"
9316 %}
9318 ins_encode %{
9319 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9320 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9321 Register dst = $dst$$Register;
9322 Register src = $src$$Register;
9323 int flag = $cop$$cmpcode;
9325 switch(flag)
9326 {
9327 case 0x01: //equal
9328 __ c_eq_s(reg_op1, reg_op2);
9329 __ movt(dst, src);
9330 break;
9331 case 0x02: //not_equal
9332 __ c_eq_s(reg_op1, reg_op2);
9333 __ movf(dst, src);
9334 break;
9335 case 0x03: //greater
9336 __ c_ole_s(reg_op1, reg_op2);
9337 __ movf(dst, src);
9338 break;
9339 case 0x04: //greater_equal
9340 __ c_olt_s(reg_op1, reg_op2);
9341 __ movf(dst, src);
9342 break;
9343 case 0x05: //less
9344 __ c_ult_s(reg_op1, reg_op2);
9345 __ movt(dst, src);
9346 break;
9347 case 0x06: //less_equal
9348 __ c_ule_s(reg_op1, reg_op2);
9349 __ movt(dst, src);
9350 break;
9351 default:
9352 Unimplemented();
9353 }
9354 %}
9355 ins_pipe( pipe_slow );
9356 %}
9358 instruct cmovF_cmpF_reg_reg(regF dst, regF src, regF tmp1, regF tmp2, cmpOp cop ) %{
9359 match(Set dst (CMoveF (Binary cop (CmpF tmp1 tmp2)) (Binary dst src)));
9360 ins_cost(200);
9361 format %{
9362 "CMP$cop $tmp1, $tmp2\t @cmovF_cmpF_reg_reg\n"
9363 "\tCMOV $dst,$src \t @cmovF_cmpF_reg_reg"
9364 %}
9366 ins_encode %{
9367 FloatRegister reg_op1 = $tmp1$$FloatRegister;
9368 FloatRegister reg_op2 = $tmp2$$FloatRegister;
9369 FloatRegister dst = $dst$$FloatRegister;
9370 FloatRegister src = $src$$FloatRegister;
9371 int flag = $cop$$cmpcode;
9373 switch(flag)
9374 {
9375 case 0x01: //equal
9376 __ c_eq_s(reg_op1, reg_op2);
9377 __ movt_s(dst, src);
9378 break;
9379 case 0x02: //not_equal
9380 __ c_eq_s(reg_op1, reg_op2);
9381 __ movf_s(dst, src);
9382 break;
9383 case 0x03: //greater
9384 __ c_ole_s(reg_op1, reg_op2);
9385 __ movf_s(dst, src);
9386 break;
9387 case 0x04: //greater_equal
9388 __ c_olt_s(reg_op1, reg_op2);
9389 __ movf_s(dst, src);
9390 break;
9391 case 0x05: //less
9392 __ c_ult_s(reg_op1, reg_op2);
9393 __ movt_s(dst, src);
9394 break;
9395 case 0x06: //less_equal
9396 __ c_ule_s(reg_op1, reg_op2);
9397 __ movt_s(dst, src);
9398 break;
9399 default:
9400 Unimplemented();
9401 }
9402 %}
9403 ins_pipe( pipe_slow );
9404 %}
9406 // Manifest a CmpL result in an integer register. Very painful.
9407 // This is the test to avoid.
9408 instruct cmpL3_reg_reg(mRegI dst, mRegL src1, mRegL src2) %{
9409 match(Set dst (CmpL3 src1 src2));
9410 ins_cost(1000);
9411 format %{ "cmpL3 $dst, $src1, $src2 @ cmpL3_reg_reg" %}
9412 ins_encode %{
9413 Register opr1 = as_Register($src1$$reg);
9414 Register opr2 = as_Register($src2$$reg);
9415 Register dst = as_Register($dst$$reg);
9417 Label Done;
9419 __ subu(AT, opr1, opr2);
9420 __ bltz(AT, Done);
9421 __ delayed()->daddiu(dst, R0, -1);
9423 __ move(dst, 1);
9424 __ movz(dst, R0, AT);
9426 __ bind(Done);
9427 %}
9428 ins_pipe( pipe_slow );
9429 %}
9431 //
9432 // less_rsult = -1
9433 // greater_result = 1
9434 // equal_result = 0
9435 // nan_result = -1
9436 //
9437 instruct cmpF3_reg_reg(mRegI dst, regF src1, regF src2) %{
9438 match(Set dst (CmpF3 src1 src2));
9439 ins_cost(1000);
9440 format %{ "cmpF3 $dst, $src1, $src2 @ cmpF3_reg_reg" %}
9441 ins_encode %{
9442 FloatRegister src1 = as_FloatRegister($src1$$reg);
9443 FloatRegister src2 = as_FloatRegister($src2$$reg);
9444 Register dst = as_Register($dst$$reg);
9446 Label Done;
9448 __ c_ult_s(src1, src2);
9449 __ bc1t(Done);
9450 __ delayed()->daddiu(dst, R0, -1);
9452 __ c_eq_s(src1, src2);
9453 __ move(dst, 1);
9454 __ movt(dst, R0);
9456 __ bind(Done);
9457 %}
9458 ins_pipe( pipe_slow );
9459 %}
9461 instruct cmpD3_reg_reg(mRegI dst, regD src1, regD src2) %{
9462 match(Set dst (CmpD3 src1 src2));
9463 ins_cost(1000);
9464 format %{ "cmpD3 $dst, $src1, $src2 @ cmpD3_reg_reg" %}
9465 ins_encode %{
9466 FloatRegister src1 = as_FloatRegister($src1$$reg);
9467 FloatRegister src2 = as_FloatRegister($src2$$reg);
9468 Register dst = as_Register($dst$$reg);
9470 Label Done;
9472 __ c_ult_d(src1, src2);
9473 __ bc1t(Done);
9474 __ delayed()->daddiu(dst, R0, -1);
9476 __ c_eq_d(src1, src2);
9477 __ move(dst, 1);
9478 __ movt(dst, R0);
9480 __ bind(Done);
9481 %}
9482 ins_pipe( pipe_slow );
9483 %}
9485 instruct clear_array(mRegL cnt, mRegP base, Universe dummy) %{
9486 match(Set dummy (ClearArray cnt base));
9487 format %{ "CLEAR_ARRAY base = $base, cnt = $cnt # Clear doublewords" %}
9488 ins_encode %{
9489 //Assume cnt is the number of bytes in an array to be cleared,
9490 //and base points to the starting address of the array.
9491 Register base = $base$$Register;
9492 Register num = $cnt$$Register;
9493 Label Loop, done;
9495 __ beq(num, R0, done);
9496 __ delayed()->daddu(AT, base, R0);
9498 __ move(T9, num); /* T9 = words */
9500 __ bind(Loop);
9501 __ sd(R0, AT, 0);
9502 __ daddi(T9, T9, -1);
9503 __ bne(T9, R0, Loop);
9504 __ delayed()->daddi(AT, AT, wordSize);
9506 __ bind(done);
9507 %}
9508 ins_pipe( pipe_slow );
9509 %}
9511 instruct string_compare(a4_RegP str1, mA5RegI cnt1, a6_RegP str2, mA7RegI cnt2, no_Ax_mRegI result) %{
9512 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9513 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2);
9515 format %{ "String Compare $str1[len: $cnt1], $str2[len: $cnt2] -> $result @ string_compare" %}
9516 ins_encode %{
9517 // Get the first character position in both strings
9518 // [8] char array, [12] offset, [16] count
9519 Register str1 = $str1$$Register;
9520 Register str2 = $str2$$Register;
9521 Register cnt1 = $cnt1$$Register;
9522 Register cnt2 = $cnt2$$Register;
9523 Register result = $result$$Register;
9525 Label L, Loop, haveResult, done;
9527 // compute the and difference of lengths (in result)
9528 __ subu(result, cnt1, cnt2); // result holds the difference of two lengths
9530 // compute the shorter length (in cnt1)
9531 __ slt(AT, cnt2, cnt1);
9532 __ movn(cnt1, cnt2, AT);
9534 // Now the shorter length is in cnt1 and cnt2 can be used as a tmp register
9535 __ bind(Loop); // Loop begin
9536 __ beq(cnt1, R0, done);
9537 __ delayed()->lhu(AT, str1, 0);;
9539 // compare current character
9540 __ lhu(cnt2, str2, 0);
9541 __ bne(AT, cnt2, haveResult);
9542 __ delayed()->addi(str1, str1, 2);
9543 __ addi(str2, str2, 2);
9544 __ b(Loop);
9545 __ delayed()->addi(cnt1, cnt1, -1); // Loop end
9547 __ bind(haveResult);
9548 __ subu(result, AT, cnt2);
9550 __ bind(done);
9551 %}
9553 ins_pipe( pipe_slow );
9554 %}
9556 // intrinsic optimization
9557 instruct string_equals(a4_RegP str1, a5_RegP str2, mA6RegI cnt, mA7RegI temp, no_Ax_mRegI result) %{
9558 match(Set result (StrEquals (Binary str1 str2) cnt));
9559 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL temp);
9561 format %{ "String Equal $str1, $str2, len:$cnt tmp:$temp -> $result @ string_equals" %}
9562 ins_encode %{
9563 // Get the first character position in both strings
9564 // [8] char array, [12] offset, [16] count
9565 Register str1 = $str1$$Register;
9566 Register str2 = $str2$$Register;
9567 Register cnt = $cnt$$Register;
9568 Register tmp = $temp$$Register;
9569 Register result = $result$$Register;
9571 Label Loop, done;
9574 __ beq(str1, str2, done); // same char[] ?
9575 __ daddiu(result, R0, 1);
9577 __ bind(Loop); // Loop begin
9578 __ beq(cnt, R0, done);
9579 __ daddiu(result, R0, 1); // count == 0
9581 // compare current character
9582 __ lhu(AT, str1, 0);;
9583 __ lhu(tmp, str2, 0);
9584 __ bne(AT, tmp, done);
9585 __ delayed()->daddi(result, R0, 0);
9586 __ addi(str1, str1, 2);
9587 __ addi(str2, str2, 2);
9588 __ b(Loop);
9589 __ delayed()->addi(cnt, cnt, -1); // Loop end
9591 __ bind(done);
9592 %}
9594 ins_pipe( pipe_slow );
9595 %}
9597 //----------Arithmetic Instructions-------------------------------------------
9598 //----------Addition Instructions---------------------------------------------
9599 instruct addI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9600 match(Set dst (AddI src1 src2));
9602 format %{ "add $dst, $src1, $src2 #@addI_Reg_Reg" %}
9603 ins_encode %{
9604 Register dst = $dst$$Register;
9605 Register src1 = $src1$$Register;
9606 Register src2 = $src2$$Register;
9607 __ addu32(dst, src1, src2);
9608 %}
9609 ins_pipe( ialu_regI_regI );
9610 %}
9612 instruct addI_Reg_imm(mRegI dst, mRegI src1, immI src2) %{
9613 match(Set dst (AddI src1 src2));
9615 format %{ "add $dst, $src1, $src2 #@addI_Reg_imm" %}
9616 ins_encode %{
9617 Register dst = $dst$$Register;
9618 Register src1 = $src1$$Register;
9619 int imm = $src2$$constant;
9621 if(Assembler::is_simm16(imm)) {
9622 __ addiu32(dst, src1, imm);
9623 } else {
9624 __ move(AT, imm);
9625 __ addu32(dst, src1, AT);
9626 }
9627 %}
9628 ins_pipe( ialu_regI_regI );
9629 %}
9631 instruct addP_reg_reg(mRegP dst, mRegP src1, mRegL src2) %{
9632 match(Set dst (AddP src1 src2));
9634 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
9636 ins_encode %{
9637 Register dst = $dst$$Register;
9638 Register src1 = $src1$$Register;
9639 Register src2 = $src2$$Register;
9640 __ daddu(dst, src1, src2);
9641 %}
9643 ins_pipe( ialu_regI_regI );
9644 %}
9646 instruct addP_reg_reg_convI2L(mRegP dst, mRegP src1, mRegI src2) %{
9647 match(Set dst (AddP src1 (ConvI2L src2)));
9649 format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg_convI2L" %}
9651 ins_encode %{
9652 Register dst = $dst$$Register;
9653 Register src1 = $src1$$Register;
9654 Register src2 = $src2$$Register;
9655 __ daddu(dst, src1, src2);
9656 %}
9658 ins_pipe( ialu_regI_regI );
9659 %}
9661 instruct addP_reg_imm(mRegP dst, mRegP src1, immL src2) %{
9662 match(Set dst (AddP src1 src2));
9664 format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm" %}
9665 ins_encode %{
9666 Register src1 = $src1$$Register;
9667 long src2 = $src2$$constant;
9668 Register dst = $dst$$Register;
9670 if(Assembler::is_simm16(src2)) {
9671 __ daddiu(dst, src1, src2);
9672 } else {
9673 __ set64(AT, src2);
9674 __ daddu(dst, src1, AT);
9675 }
9676 %}
9677 ins_pipe( ialu_regI_imm16 );
9678 %}
9680 // Add Long Register with Register
9681 instruct addL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9682 match(Set dst (AddL src1 src2));
9683 ins_cost(200);
9684 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_Reg\t" %}
9686 ins_encode %{
9687 Register dst_reg = as_Register($dst$$reg);
9688 Register src1_reg = as_Register($src1$$reg);
9689 Register src2_reg = as_Register($src2$$reg);
9691 __ daddu(dst_reg, src1_reg, src2_reg);
9692 %}
9694 ins_pipe( ialu_regL_regL );
9695 %}
9697 instruct addL_Reg_imm(mRegL dst, mRegL src1, immL16 src2)
9698 %{
9699 match(Set dst (AddL src1 src2));
9701 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_imm " %}
9702 ins_encode %{
9703 Register dst_reg = as_Register($dst$$reg);
9704 Register src1_reg = as_Register($src1$$reg);
9705 int src2_imm = $src2$$constant;
9707 __ daddiu(dst_reg, src1_reg, src2_imm);
9708 %}
9710 ins_pipe( ialu_regL_regL );
9711 %}
9713 instruct addL_RegI2L_imm(mRegL dst, mRegI src1, immL16 src2)
9714 %{
9715 match(Set dst (AddL (ConvI2L src1) src2));
9717 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_imm " %}
9718 ins_encode %{
9719 Register dst_reg = as_Register($dst$$reg);
9720 Register src1_reg = as_Register($src1$$reg);
9721 int src2_imm = $src2$$constant;
9723 __ daddiu(dst_reg, src1_reg, src2_imm);
9724 %}
9726 ins_pipe( ialu_regL_regL );
9727 %}
9729 instruct addL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9730 match(Set dst (AddL (ConvI2L src1) src2));
9731 ins_cost(200);
9732 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_Reg\t" %}
9734 ins_encode %{
9735 Register dst_reg = as_Register($dst$$reg);
9736 Register src1_reg = as_Register($src1$$reg);
9737 Register src2_reg = as_Register($src2$$reg);
9739 __ daddu(dst_reg, src1_reg, src2_reg);
9740 %}
9742 ins_pipe( ialu_regL_regL );
9743 %}
9745 instruct addL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9746 match(Set dst (AddL (ConvI2L src1) (ConvI2L src2)));
9747 ins_cost(200);
9748 format %{ "ADD $dst, $src1, $src2 #@addL_RegI2L_RegI2L\t" %}
9750 ins_encode %{
9751 Register dst_reg = as_Register($dst$$reg);
9752 Register src1_reg = as_Register($src1$$reg);
9753 Register src2_reg = as_Register($src2$$reg);
9755 __ daddu(dst_reg, src1_reg, src2_reg);
9756 %}
9758 ins_pipe( ialu_regL_regL );
9759 %}
9761 instruct addL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9762 match(Set dst (AddL src1 (ConvI2L src2)));
9763 ins_cost(200);
9764 format %{ "ADD $dst, $src1, $src2 #@addL_Reg_RegI2L\t" %}
9766 ins_encode %{
9767 Register dst_reg = as_Register($dst$$reg);
9768 Register src1_reg = as_Register($src1$$reg);
9769 Register src2_reg = as_Register($src2$$reg);
9771 __ daddu(dst_reg, src1_reg, src2_reg);
9772 %}
9774 ins_pipe( ialu_regL_regL );
9775 %}
9777 //----------Subtraction Instructions-------------------------------------------
9778 // Integer Subtraction Instructions
9779 instruct subI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9780 match(Set dst (SubI src1 src2));
9781 ins_cost(100);
9783 format %{ "sub $dst, $src1, $src2 #@subI_Reg_Reg" %}
9784 ins_encode %{
9785 Register dst = $dst$$Register;
9786 Register src1 = $src1$$Register;
9787 Register src2 = $src2$$Register;
9788 __ subu32(dst, src1, src2);
9789 %}
9790 ins_pipe( ialu_regI_regI );
9791 %}
9793 instruct subI_Reg_immI16_sub(mRegI dst, mRegI src1, immI16_sub src2) %{
9794 match(Set dst (SubI src1 src2));
9795 ins_cost(80);
9797 format %{ "sub $dst, $src1, $src2 #@subI_Reg_immI16_sub" %}
9798 ins_encode %{
9799 Register dst = $dst$$Register;
9800 Register src1 = $src1$$Register;
9801 __ addiu32(dst, src1, -1 * $src2$$constant);
9802 %}
9803 ins_pipe( ialu_regI_regI );
9804 %}
9806 instruct negI_Reg(mRegI dst, immI0 zero, mRegI src) %{
9807 match(Set dst (SubI zero src));
9808 ins_cost(80);
9810 format %{ "neg $dst, $src #@negI_Reg" %}
9811 ins_encode %{
9812 Register dst = $dst$$Register;
9813 Register src = $src$$Register;
9814 __ subu32(dst, R0, src);
9815 %}
9816 ins_pipe( ialu_regI_regI );
9817 %}
9819 instruct negL_Reg(mRegL dst, immL0 zero, mRegL src) %{
9820 match(Set dst (SubL zero src));
9821 ins_cost(80);
9823 format %{ "neg $dst, $src #@negL_Reg" %}
9824 ins_encode %{
9825 Register dst = $dst$$Register;
9826 Register src = $src$$Register;
9827 __ subu(dst, R0, src);
9828 %}
9829 ins_pipe( ialu_regI_regI );
9830 %}
9832 instruct subL_Reg_immL16_sub(mRegL dst, mRegL src1, immL16_sub src2) %{
9833 match(Set dst (SubL src1 src2));
9834 ins_cost(80);
9836 format %{ "sub $dst, $src1, $src2 #@subL_Reg_immL16_sub" %}
9837 ins_encode %{
9838 Register dst = $dst$$Register;
9839 Register src1 = $src1$$Register;
9840 __ daddiu(dst, src1, -1 * $src2$$constant);
9841 %}
9842 ins_pipe( ialu_regI_regI );
9843 %}
9845 // Subtract Long Register with Register.
9846 instruct subL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
9847 match(Set dst (SubL src1 src2));
9848 ins_cost(100);
9849 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_Reg" %}
9850 ins_encode %{
9851 Register dst = as_Register($dst$$reg);
9852 Register src1 = as_Register($src1$$reg);
9853 Register src2 = as_Register($src2$$reg);
9855 __ subu(dst, src1, src2);
9856 %}
9857 ins_pipe( ialu_regL_regL );
9858 %}
9860 instruct subL_Reg_RegI2L(mRegL dst, mRegL src1, mRegI src2) %{
9861 match(Set dst (SubL src1 (ConvI2L src2)));
9862 ins_cost(100);
9863 format %{ "SubL $dst, $src1, $src2 @ subL_Reg_RegI2L" %}
9864 ins_encode %{
9865 Register dst = as_Register($dst$$reg);
9866 Register src1 = as_Register($src1$$reg);
9867 Register src2 = as_Register($src2$$reg);
9869 __ subu(dst, src1, src2);
9870 %}
9871 ins_pipe( ialu_regL_regL );
9872 %}
9874 instruct subL_RegI2L_Reg(mRegL dst, mRegI src1, mRegL src2) %{
9875 match(Set dst (SubL (ConvI2L src1) src2));
9876 ins_cost(200);
9877 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_Reg" %}
9878 ins_encode %{
9879 Register dst = as_Register($dst$$reg);
9880 Register src1 = as_Register($src1$$reg);
9881 Register src2 = as_Register($src2$$reg);
9883 __ subu(dst, src1, src2);
9884 %}
9885 ins_pipe( ialu_regL_regL );
9886 %}
9888 instruct subL_RegI2L_RegI2L(mRegL dst, mRegI src1, mRegI src2) %{
9889 match(Set dst (SubL (ConvI2L src1) (ConvI2L src2)));
9890 ins_cost(200);
9891 format %{ "SubL $dst, $src1, $src2 @ subL_RegI2L_RegI2L" %}
9892 ins_encode %{
9893 Register dst = as_Register($dst$$reg);
9894 Register src1 = as_Register($src1$$reg);
9895 Register src2 = as_Register($src2$$reg);
9897 __ subu(dst, src1, src2);
9898 %}
9899 ins_pipe( ialu_regL_regL );
9900 %}
9902 // Integer MOD with Register
9903 instruct modI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9904 match(Set dst (ModI src1 src2));
9905 ins_cost(300);
9906 format %{ "modi $dst, $src1, $src2 @ modI_Reg_Reg" %}
9907 ins_encode %{
9908 Register dst = $dst$$Register;
9909 Register src1 = $src1$$Register;
9910 Register src2 = $src2$$Register;
9912 //if (UseLoongsonISA) {
9913 if (0) {
9914 // 2016.08.10
9915 // Experiments show that gsmod is slower that div+mfhi.
9916 // So I just disable it here.
9917 __ gsmod(dst, src1, src2);
9918 } else {
9919 __ div(src1, src2);
9920 __ mfhi(dst);
9921 }
9922 %}
9924 //ins_pipe( ialu_mod );
9925 ins_pipe( ialu_regI_regI );
9926 %}
9928 instruct modL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
9929 match(Set dst (ModL src1 src2));
9930 format %{ "modL $dst, $src1, $src2 @modL_reg_reg" %}
9932 ins_encode %{
9933 Register dst = as_Register($dst$$reg);
9934 Register op1 = as_Register($src1$$reg);
9935 Register op2 = as_Register($src2$$reg);
9937 if (UseLoongsonISA) {
9938 __ gsdmod(dst, op1, op2);
9939 } else {
9940 __ ddiv(op1, op2);
9941 __ mfhi(dst);
9942 }
9943 %}
9944 ins_pipe( pipe_slow );
9945 %}
9947 instruct mulI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9948 match(Set dst (MulI src1 src2));
9950 ins_cost(300);
9951 format %{ "mul $dst, $src1, $src2 @ mulI_Reg_Reg" %}
9952 ins_encode %{
9953 Register src1 = $src1$$Register;
9954 Register src2 = $src2$$Register;
9955 Register dst = $dst$$Register;
9957 __ mul(dst, src1, src2);
9958 %}
9959 ins_pipe( ialu_mult );
9960 %}
9962 instruct maddI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2, mRegI src3) %{
9963 match(Set dst (AddI (MulI src1 src2) src3));
9965 ins_cost(999);
9966 format %{ "madd $dst, $src1 * $src2 + $src3 #@maddI_Reg_Reg" %}
9967 ins_encode %{
9968 Register src1 = $src1$$Register;
9969 Register src2 = $src2$$Register;
9970 Register src3 = $src3$$Register;
9971 Register dst = $dst$$Register;
9973 __ mtlo(src3);
9974 __ madd(src1, src2);
9975 __ mflo(dst);
9976 %}
9977 ins_pipe( ialu_mult );
9978 %}
9980 instruct divI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
9981 match(Set dst (DivI src1 src2));
9983 ins_cost(300);
9984 format %{ "div $dst, $src1, $src2 @ divI_Reg_Reg" %}
9985 ins_encode %{
9986 Register src1 = $src1$$Register;
9987 Register src2 = $src2$$Register;
9988 Register dst = $dst$$Register;
9990 /* 2012/4/21 Jin: In MIPS, div does not cause exception.
9991 We must trap an exception manually. */
9992 __ teq(R0, src2, 0x7);
9994 if (UseLoongsonISA) {
9995 __ gsdiv(dst, src1, src2);
9996 } else {
9997 __ div(src1, src2);
9999 __ nop();
10000 __ nop();
10001 __ mflo(dst);
10002 }
10003 %}
10004 ins_pipe( ialu_mod );
10005 %}
10007 instruct divF_Reg_Reg(regF dst, regF src1, regF src2) %{
10008 match(Set dst (DivF src1 src2));
10010 ins_cost(300);
10011 format %{ "divF $dst, $src1, $src2 @ divF_Reg_Reg" %}
10012 ins_encode %{
10013 FloatRegister src1 = $src1$$FloatRegister;
10014 FloatRegister src2 = $src2$$FloatRegister;
10015 FloatRegister dst = $dst$$FloatRegister;
10017 /* Here do we need to trap an exception manually ? */
10018 __ div_s(dst, src1, src2);
10019 %}
10020 ins_pipe( pipe_slow );
10021 %}
10023 instruct divD_Reg_Reg(regD dst, regD src1, regD src2) %{
10024 match(Set dst (DivD src1 src2));
10026 ins_cost(300);
10027 format %{ "divD $dst, $src1, $src2 @ divD_Reg_Reg" %}
10028 ins_encode %{
10029 FloatRegister src1 = $src1$$FloatRegister;
10030 FloatRegister src2 = $src2$$FloatRegister;
10031 FloatRegister dst = $dst$$FloatRegister;
10033 /* Here do we need to trap an exception manually ? */
10034 __ div_d(dst, src1, src2);
10035 %}
10036 ins_pipe( pipe_slow );
10037 %}
10039 instruct mulL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10040 match(Set dst (MulL src1 src2));
10041 format %{ "mulL $dst, $src1, $src2 @mulL_reg_reg" %}
10042 ins_encode %{
10043 Register dst = as_Register($dst$$reg);
10044 Register op1 = as_Register($src1$$reg);
10045 Register op2 = as_Register($src2$$reg);
10047 if (UseLoongsonISA) {
10048 __ gsdmult(dst, op1, op2);
10049 } else {
10050 __ dmult(op1, op2);
10051 __ mflo(dst);
10052 }
10053 %}
10054 ins_pipe( pipe_slow );
10055 %}
10057 instruct mulL_reg_regI2L(mRegL dst, mRegL src1, mRegI src2) %{
10058 match(Set dst (MulL src1 (ConvI2L src2)));
10059 format %{ "mulL $dst, $src1, $src2 @mulL_reg_regI2L" %}
10060 ins_encode %{
10061 Register dst = as_Register($dst$$reg);
10062 Register op1 = as_Register($src1$$reg);
10063 Register op2 = as_Register($src2$$reg);
10065 if (UseLoongsonISA) {
10066 __ gsdmult(dst, op1, op2);
10067 } else {
10068 __ dmult(op1, op2);
10069 __ mflo(dst);
10070 }
10071 %}
10072 ins_pipe( pipe_slow );
10073 %}
10075 instruct divL_reg_reg(mRegL dst, mRegL src1, mRegL src2) %{
10076 match(Set dst (DivL src1 src2));
10077 format %{ "divL $dst, $src1, $src2 @divL_reg_reg" %}
10079 ins_encode %{
10080 Register dst = as_Register($dst$$reg);
10081 Register op1 = as_Register($src1$$reg);
10082 Register op2 = as_Register($src2$$reg);
10084 if (UseLoongsonISA) {
10085 __ gsddiv(dst, op1, op2);
10086 } else {
10087 __ ddiv(op1, op2);
10088 __ mflo(dst);
10089 }
10090 %}
10091 ins_pipe( pipe_slow );
10092 %}
10094 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
10095 match(Set dst (AddF src1 src2));
10096 format %{ "AddF $dst, $src1, $src2 @addF_reg_reg" %}
10097 ins_encode %{
10098 FloatRegister src1 = as_FloatRegister($src1$$reg);
10099 FloatRegister src2 = as_FloatRegister($src2$$reg);
10100 FloatRegister dst = as_FloatRegister($dst$$reg);
10102 __ add_s(dst, src1, src2);
10103 %}
10104 ins_pipe( fpu_regF_regF );
10105 %}
10107 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
10108 match(Set dst (SubF src1 src2));
10109 format %{ "SubF $dst, $src1, $src2 @subF_reg_reg" %}
10110 ins_encode %{
10111 FloatRegister src1 = as_FloatRegister($src1$$reg);
10112 FloatRegister src2 = as_FloatRegister($src2$$reg);
10113 FloatRegister dst = as_FloatRegister($dst$$reg);
10115 __ sub_s(dst, src1, src2);
10116 %}
10117 ins_pipe( fpu_regF_regF );
10118 %}
10119 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
10120 match(Set dst (AddD src1 src2));
10121 format %{ "AddD $dst, $src1, $src2 @addD_reg_reg" %}
10122 ins_encode %{
10123 FloatRegister src1 = as_FloatRegister($src1$$reg);
10124 FloatRegister src2 = as_FloatRegister($src2$$reg);
10125 FloatRegister dst = as_FloatRegister($dst$$reg);
10127 __ add_d(dst, src1, src2);
10128 %}
10129 ins_pipe( fpu_regF_regF );
10130 %}
10132 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
10133 match(Set dst (SubD src1 src2));
10134 format %{ "SubD $dst, $src1, $src2 @subD_reg_reg" %}
10135 ins_encode %{
10136 FloatRegister src1 = as_FloatRegister($src1$$reg);
10137 FloatRegister src2 = as_FloatRegister($src2$$reg);
10138 FloatRegister dst = as_FloatRegister($dst$$reg);
10140 __ sub_d(dst, src1, src2);
10141 %}
10142 ins_pipe( fpu_regF_regF );
10143 %}
10145 instruct negF_reg(regF dst, regF src) %{
10146 match(Set dst (NegF src));
10147 format %{ "negF $dst, $src @negF_reg" %}
10148 ins_encode %{
10149 FloatRegister src = as_FloatRegister($src$$reg);
10150 FloatRegister dst = as_FloatRegister($dst$$reg);
10152 __ neg_s(dst, src);
10153 %}
10154 ins_pipe( fpu_regF_regF );
10155 %}
10157 instruct negD_reg(regD dst, regD src) %{
10158 match(Set dst (NegD src));
10159 format %{ "negD $dst, $src @negD_reg" %}
10160 ins_encode %{
10161 FloatRegister src = as_FloatRegister($src$$reg);
10162 FloatRegister dst = as_FloatRegister($dst$$reg);
10164 __ neg_d(dst, src);
10165 %}
10166 ins_pipe( fpu_regF_regF );
10167 %}
10170 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
10171 match(Set dst (MulF src1 src2));
10172 format %{ "MULF $dst, $src1, $src2 @mulF_reg_reg" %}
10173 ins_encode %{
10174 FloatRegister src1 = $src1$$FloatRegister;
10175 FloatRegister src2 = $src2$$FloatRegister;
10176 FloatRegister dst = $dst$$FloatRegister;
10178 __ mul_s(dst, src1, src2);
10179 %}
10180 ins_pipe( fpu_regF_regF );
10181 %}
10183 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
10184 match(Set dst (AddF (MulF src1 src2) src3));
10185 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10186 ins_cost(44444);
10187 format %{ "maddF $dst, $src1, $src2, $src3 @maddF_reg_reg" %}
10188 ins_encode %{
10189 FloatRegister src1 = $src1$$FloatRegister;
10190 FloatRegister src2 = $src2$$FloatRegister;
10191 FloatRegister src3 = $src3$$FloatRegister;
10192 FloatRegister dst = $dst$$FloatRegister;
10194 __ madd_s(dst, src1, src2, src3);
10195 %}
10196 ins_pipe( fpu_regF_regF );
10197 %}
10199 // Mul two double precision floating piont number
10200 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
10201 match(Set dst (MulD src1 src2));
10202 format %{ "MULD $dst, $src1, $src2 @mulD_reg_reg" %}
10203 ins_encode %{
10204 FloatRegister src1 = $src1$$FloatRegister;
10205 FloatRegister src2 = $src2$$FloatRegister;
10206 FloatRegister dst = $dst$$FloatRegister;
10208 __ mul_d(dst, src1, src2);
10209 %}
10210 ins_pipe( fpu_regF_regF );
10211 %}
10213 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
10214 match(Set dst (AddD (MulD src1 src2) src3));
10215 // For compatibility reason (e.g. on the Loongson platform), disable this guy.
10216 ins_cost(44444);
10217 format %{ "maddD $dst, $src1, $src2, $src3 @maddD_reg_reg" %}
10218 ins_encode %{
10219 FloatRegister src1 = $src1$$FloatRegister;
10220 FloatRegister src2 = $src2$$FloatRegister;
10221 FloatRegister src3 = $src3$$FloatRegister;
10222 FloatRegister dst = $dst$$FloatRegister;
10224 __ madd_d(dst, src1, src2, src3);
10225 %}
10226 ins_pipe( fpu_regF_regF );
10227 %}
10229 instruct absF_reg(regF dst, regF src) %{
10230 match(Set dst (AbsF src));
10231 ins_cost(100);
10232 format %{ "absF $dst, $src @absF_reg" %}
10233 ins_encode %{
10234 FloatRegister src = as_FloatRegister($src$$reg);
10235 FloatRegister dst = as_FloatRegister($dst$$reg);
10237 __ abs_s(dst, src);
10238 %}
10239 ins_pipe( fpu_regF_regF );
10240 %}
10243 // intrinsics for math_native.
10244 // AbsD SqrtD CosD SinD TanD LogD Log10D
10246 instruct absD_reg(regD dst, regD src) %{
10247 match(Set dst (AbsD src));
10248 ins_cost(100);
10249 format %{ "absD $dst, $src @absD_reg" %}
10250 ins_encode %{
10251 FloatRegister src = as_FloatRegister($src$$reg);
10252 FloatRegister dst = as_FloatRegister($dst$$reg);
10254 __ abs_d(dst, src);
10255 %}
10256 ins_pipe( fpu_regF_regF );
10257 %}
10259 instruct sqrtD_reg(regD dst, regD src) %{
10260 match(Set dst (SqrtD src));
10261 ins_cost(100);
10262 format %{ "SqrtD $dst, $src @sqrtD_reg" %}
10263 ins_encode %{
10264 FloatRegister src = as_FloatRegister($src$$reg);
10265 FloatRegister dst = as_FloatRegister($dst$$reg);
10267 __ sqrt_d(dst, src);
10268 %}
10269 ins_pipe( fpu_regF_regF );
10270 %}
10272 instruct sqrtF_reg(regF dst, regF src) %{
10273 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10274 ins_cost(100);
10275 format %{ "SqrtF $dst, $src @sqrtF_reg" %}
10276 ins_encode %{
10277 FloatRegister src = as_FloatRegister($src$$reg);
10278 FloatRegister dst = as_FloatRegister($dst$$reg);
10280 __ sqrt_s(dst, src);
10281 %}
10282 ins_pipe( fpu_regF_regF );
10283 %}
10284 //----------------------------------Logical Instructions----------------------
10285 //__________________________________Integer Logical Instructions-------------
10287 //And Instuctions
10288 // And Register with Immediate
10289 instruct andI_Reg_immI(mRegI dst, mRegI src1, immI src2) %{
10290 match(Set dst (AndI src1 src2));
10292 format %{ "and $dst, $src1, $src2 #@andI_Reg_immI" %}
10293 ins_encode %{
10294 Register dst = $dst$$Register;
10295 Register src = $src1$$Register;
10296 int val = $src2$$constant;
10298 __ move(AT, val);
10299 __ andr(dst, src, AT);
10300 %}
10301 ins_pipe( ialu_regI_regI );
10302 %}
10304 instruct andI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10305 match(Set dst (AndI src1 src2));
10306 ins_cost(60);
10308 format %{ "and $dst, $src1, $src2 #@andI_Reg_imm_0_65535" %}
10309 ins_encode %{
10310 Register dst = $dst$$Register;
10311 Register src = $src1$$Register;
10312 int val = $src2$$constant;
10314 __ andi(dst, src, val);
10315 %}
10316 ins_pipe( ialu_regI_regI );
10317 %}
10319 instruct andI_Reg_immI_nonneg_mask(mRegI dst, mRegI src1, immI_nonneg_mask mask) %{
10320 match(Set dst (AndI src1 mask));
10321 ins_cost(60);
10323 format %{ "and $dst, $src1, $mask #@andI_Reg_immI_nonneg_mask" %}
10324 ins_encode %{
10325 Register dst = $dst$$Register;
10326 Register src = $src1$$Register;
10327 int size = Assembler::is_int_mask($mask$$constant);
10329 __ ext(dst, src, 0, size);
10330 %}
10331 ins_pipe( ialu_regI_regI );
10332 %}
10334 instruct andL_Reg_immL_nonneg_mask(mRegL dst, mRegL src1, immL_nonneg_mask mask) %{
10335 match(Set dst (AndL src1 mask));
10336 ins_cost(60);
10338 format %{ "and $dst, $src1, $mask #@andL_Reg_immL_nonneg_mask" %}
10339 ins_encode %{
10340 Register dst = $dst$$Register;
10341 Register src = $src1$$Register;
10342 int size = Assembler::is_jlong_mask($mask$$constant);
10344 __ dext(dst, src, 0, size);
10345 %}
10346 ins_pipe( ialu_regI_regI );
10347 %}
10349 instruct xorI_Reg_imm_0_65535(mRegI dst, mRegI src1, immI_0_65535 src2) %{
10350 match(Set dst (XorI src1 src2));
10351 ins_cost(60);
10353 format %{ "xori $dst, $src1, $src2 #@xorI_Reg_imm_0_65535" %}
10354 ins_encode %{
10355 Register dst = $dst$$Register;
10356 Register src = $src1$$Register;
10357 int val = $src2$$constant;
10359 __ xori(dst, src, val);
10360 %}
10361 ins_pipe( ialu_regI_regI );
10362 %}
10364 instruct xorI_Reg_immI_M1(mRegI dst, mRegI src1, immI_M1 M1) %{
10365 match(Set dst (XorI src1 M1));
10366 predicate(UseLoongsonISA && Use3A2000);
10367 ins_cost(60);
10369 format %{ "xor $dst, $src1, $M1 #@xorI_Reg_immI_M1" %}
10370 ins_encode %{
10371 Register dst = $dst$$Register;
10372 Register src = $src1$$Register;
10374 __ gsorn(dst, R0, src);
10375 %}
10376 ins_pipe( ialu_regI_regI );
10377 %}
10379 instruct xorL2I_Reg_immI_M1(mRegI dst, mRegL src1, immI_M1 M1) %{
10380 match(Set dst (XorI (ConvL2I src1) M1));
10381 predicate(UseLoongsonISA && Use3A2000);
10382 ins_cost(60);
10384 format %{ "xor $dst, $src1, $M1 #@xorL2I_Reg_immI_M1" %}
10385 ins_encode %{
10386 Register dst = $dst$$Register;
10387 Register src = $src1$$Register;
10389 __ gsorn(dst, R0, src);
10390 %}
10391 ins_pipe( ialu_regI_regI );
10392 %}
10394 instruct xorL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10395 match(Set dst (XorL src1 src2));
10396 ins_cost(60);
10398 format %{ "xori $dst, $src1, $src2 #@xorL_Reg_imm_0_65535" %}
10399 ins_encode %{
10400 Register dst = $dst$$Register;
10401 Register src = $src1$$Register;
10402 int val = $src2$$constant;
10404 __ xori(dst, src, val);
10405 %}
10406 ins_pipe( ialu_regI_regI );
10407 %}
10409 /*
10410 instruct xorL_Reg_immL_M1(mRegL dst, mRegL src1, immL_M1 M1) %{
10411 match(Set dst (XorL src1 M1));
10412 predicate(UseLoongsonISA);
10413 ins_cost(60);
10415 format %{ "xor $dst, $src1, $M1 #@xorL_Reg_immL_M1" %}
10416 ins_encode %{
10417 Register dst = $dst$$Register;
10418 Register src = $src1$$Register;
10420 __ gsorn(dst, R0, src);
10421 %}
10422 ins_pipe( ialu_regI_regI );
10423 %}
10424 */
10426 instruct lbu_and_lmask(mRegI dst, memory mem, immI_255 mask) %{
10427 match(Set dst (AndI mask (LoadB mem)));
10428 ins_cost(60);
10430 format %{ "lhu $dst, $mem #@lbu_and_lmask" %}
10431 ins_encode(load_UB_enc(dst, mem));
10432 ins_pipe( ialu_loadI );
10433 %}
10435 instruct lbu_and_rmask(mRegI dst, memory mem, immI_255 mask) %{
10436 match(Set dst (AndI (LoadB mem) mask));
10437 ins_cost(60);
10439 format %{ "lhu $dst, $mem #@lbu_and_rmask" %}
10440 ins_encode(load_UB_enc(dst, mem));
10441 ins_pipe( ialu_loadI );
10442 %}
10444 instruct andI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
10445 match(Set dst (AndI src1 src2));
10447 format %{ "and $dst, $src1, $src2 #@andI_Reg_Reg" %}
10448 ins_encode %{
10449 Register dst = $dst$$Register;
10450 Register src1 = $src1$$Register;
10451 Register src2 = $src2$$Register;
10452 __ andr(dst, src1, src2);
10453 %}
10454 ins_pipe( ialu_regI_regI );
10455 %}
10457 instruct andnI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10458 match(Set dst (AndI src1 (XorI src2 M1)));
10459 predicate(UseLoongsonISA && Use3A2000);
10461 format %{ "andn $dst, $src1, $src2 #@andnI_Reg_nReg" %}
10462 ins_encode %{
10463 Register dst = $dst$$Register;
10464 Register src1 = $src1$$Register;
10465 Register src2 = $src2$$Register;
10467 __ gsandn(dst, src1, src2);
10468 %}
10469 ins_pipe( ialu_regI_regI );
10470 %}
10472 instruct ornI_Reg_nReg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10473 match(Set dst (OrI src1 (XorI src2 M1)));
10474 predicate(UseLoongsonISA && Use3A2000);
10476 format %{ "orn $dst, $src1, $src2 #@ornI_Reg_nReg" %}
10477 ins_encode %{
10478 Register dst = $dst$$Register;
10479 Register src1 = $src1$$Register;
10480 Register src2 = $src2$$Register;
10482 __ gsorn(dst, src1, src2);
10483 %}
10484 ins_pipe( ialu_regI_regI );
10485 %}
10487 instruct andnI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10488 match(Set dst (AndI (XorI src1 M1) src2));
10489 predicate(UseLoongsonISA && Use3A2000);
10491 format %{ "andn $dst, $src2, $src1 #@andnI_nReg_Reg" %}
10492 ins_encode %{
10493 Register dst = $dst$$Register;
10494 Register src1 = $src1$$Register;
10495 Register src2 = $src2$$Register;
10497 __ gsandn(dst, src2, src1);
10498 %}
10499 ins_pipe( ialu_regI_regI );
10500 %}
10502 instruct ornI_nReg_Reg(mRegI dst, mRegI src1, mRegI src2, immI_M1 M1) %{
10503 match(Set dst (OrI (XorI src1 M1) src2));
10504 predicate(UseLoongsonISA && Use3A2000);
10506 format %{ "orn $dst, $src2, $src1 #@ornI_nReg_Reg" %}
10507 ins_encode %{
10508 Register dst = $dst$$Register;
10509 Register src1 = $src1$$Register;
10510 Register src2 = $src2$$Register;
10512 __ gsorn(dst, src2, src1);
10513 %}
10514 ins_pipe( ialu_regI_regI );
10515 %}
10517 // And Long Register with Register
10518 instruct andL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10519 match(Set dst (AndL src1 src2));
10520 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg\n\t" %}
10521 ins_encode %{
10522 Register dst_reg = as_Register($dst$$reg);
10523 Register src1_reg = as_Register($src1$$reg);
10524 Register src2_reg = as_Register($src2$$reg);
10526 __ andr(dst_reg, src1_reg, src2_reg);
10527 %}
10528 ins_pipe( ialu_regL_regL );
10529 %}
10531 instruct andL_Reg_Reg_convI2L(mRegL dst, mRegL src1, mRegI src2) %{
10532 match(Set dst (AndL src1 (ConvI2L src2)));
10533 format %{ "AND $dst, $src1, $src2 @ andL_Reg_Reg_convI2L\n\t" %}
10534 ins_encode %{
10535 Register dst_reg = as_Register($dst$$reg);
10536 Register src1_reg = as_Register($src1$$reg);
10537 Register src2_reg = as_Register($src2$$reg);
10539 __ andr(dst_reg, src1_reg, src2_reg);
10540 %}
10541 ins_pipe( ialu_regL_regL );
10542 %}
10544 instruct andL_Reg_imm_0_65535(mRegL dst, mRegL src1, immL_0_65535 src2) %{
10545 match(Set dst (AndL src1 src2));
10546 ins_cost(60);
10548 format %{ "and $dst, $src1, $src2 #@andL_Reg_imm_0_65535" %}
10549 ins_encode %{
10550 Register dst = $dst$$Register;
10551 Register src = $src1$$Register;
10552 long val = $src2$$constant;
10554 __ andi(dst, src, val);
10555 %}
10556 ins_pipe( ialu_regI_regI );
10557 %}
10559 instruct andL2I_Reg_imm_0_65535(mRegI dst, mRegL src1, immL_0_65535 src2) %{
10560 match(Set dst (ConvL2I (AndL src1 src2)));
10561 ins_cost(60);
10563 format %{ "and $dst, $src1, $src2 #@andL2I_Reg_imm_0_65535" %}
10564 ins_encode %{
10565 Register dst = $dst$$Register;
10566 Register src = $src1$$Register;
10567 long val = $src2$$constant;
10569 __ andi(dst, src, val);
10570 %}
10571 ins_pipe( ialu_regI_regI );
10572 %}
10574 /*
10575 instruct andnL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10576 match(Set dst (AndL src1 (XorL src2 M1)));
10577 predicate(UseLoongsonISA);
10579 format %{ "andn $dst, $src1, $src2 #@andnL_Reg_nReg" %}
10580 ins_encode %{
10581 Register dst = $dst$$Register;
10582 Register src1 = $src1$$Register;
10583 Register src2 = $src2$$Register;
10585 __ gsandn(dst, src1, src2);
10586 %}
10587 ins_pipe( ialu_regI_regI );
10588 %}
10589 */
10591 /*
10592 instruct ornL_Reg_nReg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10593 match(Set dst (OrL src1 (XorL src2 M1)));
10594 predicate(UseLoongsonISA);
10596 format %{ "orn $dst, $src1, $src2 #@ornL_Reg_nReg" %}
10597 ins_encode %{
10598 Register dst = $dst$$Register;
10599 Register src1 = $src1$$Register;
10600 Register src2 = $src2$$Register;
10602 __ gsorn(dst, src1, src2);
10603 %}
10604 ins_pipe( ialu_regI_regI );
10605 %}
10606 */
10608 /*
10609 instruct andnL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10610 match(Set dst (AndL (XorL src1 M1) src2));
10611 predicate(UseLoongsonISA);
10613 format %{ "andn $dst, $src2, $src1 #@andnL_nReg_Reg" %}
10614 ins_encode %{
10615 Register dst = $dst$$Register;
10616 Register src1 = $src1$$Register;
10617 Register src2 = $src2$$Register;
10619 __ gsandn(dst, src2, src1);
10620 %}
10621 ins_pipe( ialu_regI_regI );
10622 %}
10623 */
10625 /*
10626 instruct ornL_nReg_Reg(mRegL dst, mRegL src1, mRegL src2, immL_M1 M1) %{
10627 match(Set dst (OrL (XorL src1 M1) src2));
10628 predicate(UseLoongsonISA);
10630 format %{ "orn $dst, $src2, $src1 #@ornL_nReg_Reg" %}
10631 ins_encode %{
10632 Register dst = $dst$$Register;
10633 Register src1 = $src1$$Register;
10634 Register src2 = $src2$$Register;
10636 __ gsorn(dst, src2, src1);
10637 %}
10638 ins_pipe( ialu_regI_regI );
10639 %}
10640 */
10642 instruct andL_Reg_immL_M8(mRegL dst, immL_M8 M8) %{
10643 match(Set dst (AndL dst M8));
10644 ins_cost(60);
10646 format %{ "and $dst, $dst, $M8 #@andL_Reg_immL_M8" %}
10647 ins_encode %{
10648 Register dst = $dst$$Register;
10650 __ dins(dst, R0, 0, 3);
10651 %}
10652 ins_pipe( ialu_regI_regI );
10653 %}
10655 instruct andL_Reg_immL_M5(mRegL dst, immL_M5 M5) %{
10656 match(Set dst (AndL dst M5));
10657 ins_cost(60);
10659 format %{ "and $dst, $dst, $M5 #@andL_Reg_immL_M5" %}
10660 ins_encode %{
10661 Register dst = $dst$$Register;
10663 __ dins(dst, R0, 2, 1);
10664 %}
10665 ins_pipe( ialu_regI_regI );
10666 %}
10668 instruct andL_Reg_immL_M7(mRegL dst, immL_M7 M7) %{
10669 match(Set dst (AndL dst M7));
10670 ins_cost(60);
10672 format %{ "and $dst, $dst, $M7 #@andL_Reg_immL_M7" %}
10673 ins_encode %{
10674 Register dst = $dst$$Register;
10676 __ dins(dst, R0, 1, 2);
10677 %}
10678 ins_pipe( ialu_regI_regI );
10679 %}
10681 instruct andL_Reg_immL_M4(mRegL dst, immL_M4 M4) %{
10682 match(Set dst (AndL dst M4));
10683 ins_cost(60);
10685 format %{ "and $dst, $dst, $M4 #@andL_Reg_immL_M4" %}
10686 ins_encode %{
10687 Register dst = $dst$$Register;
10689 __ dins(dst, R0, 0, 2);
10690 %}
10691 ins_pipe( ialu_regI_regI );
10692 %}
10694 instruct andL_Reg_immL_M121(mRegL dst, immL_M121 M121) %{
10695 match(Set dst (AndL dst M121));
10696 ins_cost(60);
10698 format %{ "and $dst, $dst, $M121 #@andL_Reg_immL_M121" %}
10699 ins_encode %{
10700 Register dst = $dst$$Register;
10702 __ dins(dst, R0, 3, 4);
10703 %}
10704 ins_pipe( ialu_regI_regI );
10705 %}
10707 // Or Long Register with Register
10708 instruct orL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10709 match(Set dst (OrL src1 src2));
10710 format %{ "OR $dst, $src1, $src2 @ orL_Reg_Reg\t" %}
10711 ins_encode %{
10712 Register dst_reg = $dst$$Register;
10713 Register src1_reg = $src1$$Register;
10714 Register src2_reg = $src2$$Register;
10716 __ orr(dst_reg, src1_reg, src2_reg);
10717 %}
10718 ins_pipe( ialu_regL_regL );
10719 %}
10721 instruct orL_Reg_P2XReg(mRegL dst, mRegP src1, mRegL src2) %{
10722 match(Set dst (OrL (CastP2X src1) src2));
10723 format %{ "OR $dst, $src1, $src2 @ orL_Reg_P2XReg\t" %}
10724 ins_encode %{
10725 Register dst_reg = $dst$$Register;
10726 Register src1_reg = $src1$$Register;
10727 Register src2_reg = $src2$$Register;
10729 __ orr(dst_reg, src1_reg, src2_reg);
10730 %}
10731 ins_pipe( ialu_regL_regL );
10732 %}
10734 // Xor Long Register with Register
10735 instruct xorL_Reg_Reg(mRegL dst, mRegL src1, mRegL src2) %{
10736 match(Set dst (XorL src1 src2));
10737 format %{ "XOR $dst, $src1, $src2 @ xorL_Reg_Reg\t" %}
10738 ins_encode %{
10739 Register dst_reg = as_Register($dst$$reg);
10740 Register src1_reg = as_Register($src1$$reg);
10741 Register src2_reg = as_Register($src2$$reg);
10743 __ xorr(dst_reg, src1_reg, src2_reg);
10744 %}
10745 ins_pipe( ialu_regL_regL );
10746 %}
10748 // Shift Left by 8-bit immediate
10749 instruct salI_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
10750 match(Set dst (LShiftI src shift));
10752 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm" %}
10753 ins_encode %{
10754 Register src = $src$$Register;
10755 Register dst = $dst$$Register;
10756 int shamt = $shift$$constant;
10758 __ sll(dst, src, shamt);
10759 %}
10760 ins_pipe( ialu_regI_regI );
10761 %}
10763 instruct salL2I_Reg_imm(mRegI dst, mRegL src, immI8 shift) %{
10764 match(Set dst (LShiftI (ConvL2I src) shift));
10766 format %{ "SHL $dst, $src, $shift #@salL2I_Reg_imm" %}
10767 ins_encode %{
10768 Register src = $src$$Register;
10769 Register dst = $dst$$Register;
10770 int shamt = $shift$$constant;
10772 __ sll(dst, src, shamt);
10773 %}
10774 ins_pipe( ialu_regI_regI );
10775 %}
10777 instruct salI_Reg_imm_and_M65536(mRegI dst, mRegI src, immI_16 shift, immI_M65536 mask) %{
10778 match(Set dst (AndI (LShiftI src shift) mask));
10780 format %{ "SHL $dst, $src, $shift #@salI_Reg_imm_and_M65536" %}
10781 ins_encode %{
10782 Register src = $src$$Register;
10783 Register dst = $dst$$Register;
10785 __ sll(dst, src, 16);
10786 %}
10787 ins_pipe( ialu_regI_regI );
10788 %}
10790 instruct land7_2_s(mRegI dst, mRegL src, immL7 seven, immI_16 sixteen)
10791 %{
10792 match(Set dst (RShiftI (LShiftI (ConvL2I (AndL src seven)) sixteen) sixteen));
10794 format %{ "andi $dst, $src, 7\t# @land7_2_s" %}
10795 ins_encode %{
10796 Register src = $src$$Register;
10797 Register dst = $dst$$Register;
10799 __ andi(dst, src, 7);
10800 %}
10801 ins_pipe(ialu_regI_regI);
10802 %}
10804 instruct ori2s(mRegI dst, mRegI src1, immI_0_32767 src2, immI_16 sixteen)
10805 %{
10806 match(Set dst (RShiftI (LShiftI (OrI src1 src2) sixteen) sixteen));
10808 format %{ "ori $dst, $src1, $src2\t# @ori2s" %}
10809 ins_encode %{
10810 Register src = $src1$$Register;
10811 int val = $src2$$constant;
10812 Register dst = $dst$$Register;
10814 __ ori(dst, src, val);
10815 %}
10816 ins_pipe(ialu_regI_regI);
10817 %}
10819 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
10820 // This idiom is used by the compiler the i2s bytecode.
10821 instruct i2s(mRegI dst, mRegI src, immI_16 sixteen)
10822 %{
10823 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
10825 format %{ "i2s $dst, $src\t# @i2s" %}
10826 ins_encode %{
10827 Register src = $src$$Register;
10828 Register dst = $dst$$Register;
10830 __ seh(dst, src);
10831 %}
10832 ins_pipe(ialu_regI_regI);
10833 %}
10835 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
10836 // This idiom is used by the compiler for the i2b bytecode.
10837 instruct i2b(mRegI dst, mRegI src, immI_24 twentyfour)
10838 %{
10839 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
10841 format %{ "i2b $dst, $src\t# @i2b" %}
10842 ins_encode %{
10843 Register src = $src$$Register;
10844 Register dst = $dst$$Register;
10846 __ seb(dst, src);
10847 %}
10848 ins_pipe(ialu_regI_regI);
10849 %}
10852 instruct salI_RegL2I_imm(mRegI dst, mRegL src, immI8 shift) %{
10853 match(Set dst (LShiftI (ConvL2I src) shift));
10855 format %{ "SHL $dst, $src, $shift #@salI_RegL2I_imm" %}
10856 ins_encode %{
10857 Register src = $src$$Register;
10858 Register dst = $dst$$Register;
10859 int shamt = $shift$$constant;
10861 __ sll(dst, src, shamt);
10862 %}
10863 ins_pipe( ialu_regI_regI );
10864 %}
10866 // Shift Left by 8-bit immediate
10867 instruct salI_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
10868 match(Set dst (LShiftI src shift));
10870 format %{ "SHL $dst, $src, $shift #@salI_Reg_Reg" %}
10871 ins_encode %{
10872 Register src = $src$$Register;
10873 Register dst = $dst$$Register;
10874 Register shamt = $shift$$Register;
10875 __ sllv(dst, src, shamt);
10876 %}
10877 ins_pipe( ialu_regI_regI );
10878 %}
10881 // Shift Left Long
10882 instruct salL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10883 //predicate(UseNewLongLShift);
10884 match(Set dst (LShiftL src shift));
10885 ins_cost(100);
10886 format %{ "salL $dst, $src, $shift @ salL_Reg_imm" %}
10887 ins_encode %{
10888 Register src_reg = as_Register($src$$reg);
10889 Register dst_reg = as_Register($dst$$reg);
10890 int shamt = $shift$$constant;
10892 if (__ is_simm(shamt, 5))
10893 __ dsll(dst_reg, src_reg, shamt);
10894 else
10895 {
10896 int sa = Assembler::low(shamt, 6);
10897 if (sa < 32) {
10898 __ dsll(dst_reg, src_reg, sa);
10899 } else {
10900 __ dsll32(dst_reg, src_reg, sa - 32);
10901 }
10902 }
10903 %}
10904 ins_pipe( ialu_regL_regL );
10905 %}
10907 instruct salL_RegI2L_imm(mRegL dst, mRegI src, immI8 shift) %{
10908 //predicate(UseNewLongLShift);
10909 match(Set dst (LShiftL (ConvI2L src) shift));
10910 ins_cost(100);
10911 format %{ "salL $dst, $src, $shift @ salL_RegI2L_imm" %}
10912 ins_encode %{
10913 Register src_reg = as_Register($src$$reg);
10914 Register dst_reg = as_Register($dst$$reg);
10915 int shamt = $shift$$constant;
10917 if (__ is_simm(shamt, 5))
10918 __ dsll(dst_reg, src_reg, shamt);
10919 else
10920 {
10921 int sa = Assembler::low(shamt, 6);
10922 if (sa < 32) {
10923 __ dsll(dst_reg, src_reg, sa);
10924 } else {
10925 __ dsll32(dst_reg, src_reg, sa - 32);
10926 }
10927 }
10928 %}
10929 ins_pipe( ialu_regL_regL );
10930 %}
10932 // Shift Left Long
10933 instruct salL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
10934 //predicate(UseNewLongLShift);
10935 match(Set dst (LShiftL src shift));
10936 ins_cost(100);
10937 format %{ "salL $dst, $src, $shift @ salL_Reg_Reg" %}
10938 ins_encode %{
10939 Register src_reg = as_Register($src$$reg);
10940 Register dst_reg = as_Register($dst$$reg);
10942 __ dsllv(dst_reg, src_reg, $shift$$Register);
10943 %}
10944 ins_pipe( ialu_regL_regL );
10945 %}
10947 instruct salL_convI2L_Reg_imm(mRegL dst, mRegI src, immI8 shift) %{
10948 match(Set dst (LShiftL (ConvI2L src) shift));
10949 ins_cost(100);
10950 format %{ "salL $dst, $src, $shift @ salL_convI2L_Reg_imm" %}
10951 ins_encode %{
10952 Register src_reg = as_Register($src$$reg);
10953 Register dst_reg = as_Register($dst$$reg);
10954 int shamt = $shift$$constant;
10956 if (__ is_simm(shamt, 5)) {
10957 __ dsll(dst_reg, src_reg, shamt);
10958 } else {
10959 int sa = Assembler::low(shamt, 6);
10960 if (sa < 32) {
10961 __ dsll(dst_reg, src_reg, sa);
10962 } else {
10963 __ dsll32(dst_reg, src_reg, sa - 32);
10964 }
10965 }
10966 %}
10967 ins_pipe( ialu_regL_regL );
10968 %}
10970 // Shift Right Long
10971 instruct sarL_Reg_imm(mRegL dst, mRegL src, immI8 shift) %{
10972 match(Set dst (RShiftL src shift));
10973 ins_cost(100);
10974 format %{ "sarL $dst, $src, $shift @ sarL_Reg_imm" %}
10975 ins_encode %{
10976 Register src_reg = as_Register($src$$reg);
10977 Register dst_reg = as_Register($dst$$reg);
10978 int shamt = ($shift$$constant & 0x3f);
10979 if (__ is_simm(shamt, 5))
10980 __ dsra(dst_reg, src_reg, shamt);
10981 else {
10982 int sa = Assembler::low(shamt, 6);
10983 if (sa < 32) {
10984 __ dsra(dst_reg, src_reg, sa);
10985 } else {
10986 __ dsra32(dst_reg, src_reg, sa - 32);
10987 }
10988 }
10989 %}
10990 ins_pipe( ialu_regL_regL );
10991 %}
10993 instruct sarL2I_Reg_immI_32_63(mRegI dst, mRegL src, immI_32_63 shift) %{
10994 match(Set dst (ConvL2I (RShiftL src shift)));
10995 ins_cost(100);
10996 format %{ "sarL $dst, $src, $shift @ sarL2I_Reg_immI_32_63" %}
10997 ins_encode %{
10998 Register src_reg = as_Register($src$$reg);
10999 Register dst_reg = as_Register($dst$$reg);
11000 int shamt = $shift$$constant;
11002 __ dsra32(dst_reg, src_reg, shamt - 32);
11003 %}
11004 ins_pipe( ialu_regL_regL );
11005 %}
11007 // Shift Right Long arithmetically
11008 instruct sarL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
11009 //predicate(UseNewLongLShift);
11010 match(Set dst (RShiftL src shift));
11011 ins_cost(100);
11012 format %{ "sarL $dst, $src, $shift @ sarL_Reg_Reg" %}
11013 ins_encode %{
11014 Register src_reg = as_Register($src$$reg);
11015 Register dst_reg = as_Register($dst$$reg);
11017 __ dsrav(dst_reg, src_reg, $shift$$Register);
11018 %}
11019 ins_pipe( ialu_regL_regL );
11020 %}
11022 // Shift Right Long logically
11023 instruct slrL_Reg_Reg(mRegL dst, mRegL src, mRegI shift) %{
11024 match(Set dst (URShiftL src shift));
11025 ins_cost(100);
11026 format %{ "slrL $dst, $src, $shift @ slrL_Reg_Reg" %}
11027 ins_encode %{
11028 Register src_reg = as_Register($src$$reg);
11029 Register dst_reg = as_Register($dst$$reg);
11031 __ dsrlv(dst_reg, src_reg, $shift$$Register);
11032 %}
11033 ins_pipe( ialu_regL_regL );
11034 %}
11036 instruct slrL_Reg_immI_0_31(mRegL dst, mRegL src, immI_0_31 shift) %{
11037 match(Set dst (URShiftL src shift));
11038 ins_cost(80);
11039 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_0_31" %}
11040 ins_encode %{
11041 Register src_reg = as_Register($src$$reg);
11042 Register dst_reg = as_Register($dst$$reg);
11043 int shamt = $shift$$constant;
11045 __ dsrl(dst_reg, src_reg, shamt);
11046 %}
11047 ins_pipe( ialu_regL_regL );
11048 %}
11050 instruct slrL_Reg_immI_0_31_and_max_int(mRegI dst, mRegL src, immI_0_31 shift, immI_MaxI max_int) %{
11051 match(Set dst (AndI (ConvL2I (URShiftL src shift)) max_int));
11052 ins_cost(80);
11053 format %{ "dext $dst, $src, $shift, 31 @ slrL_Reg_immI_0_31_and_max_int" %}
11054 ins_encode %{
11055 Register src_reg = as_Register($src$$reg);
11056 Register dst_reg = as_Register($dst$$reg);
11057 int shamt = $shift$$constant;
11059 __ dext(dst_reg, src_reg, shamt, 31);
11060 %}
11061 ins_pipe( ialu_regL_regL );
11062 %}
11064 instruct slrL_P2XReg_immI_0_31(mRegL dst, mRegP src, immI_0_31 shift) %{
11065 match(Set dst (URShiftL (CastP2X src) shift));
11066 ins_cost(80);
11067 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_0_31" %}
11068 ins_encode %{
11069 Register src_reg = as_Register($src$$reg);
11070 Register dst_reg = as_Register($dst$$reg);
11071 int shamt = $shift$$constant;
11073 __ dsrl(dst_reg, src_reg, shamt);
11074 %}
11075 ins_pipe( ialu_regL_regL );
11076 %}
11078 instruct slrL_Reg_immI_32_63(mRegL dst, mRegL src, immI_32_63 shift) %{
11079 match(Set dst (URShiftL src shift));
11080 ins_cost(80);
11081 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_32_63" %}
11082 ins_encode %{
11083 Register src_reg = as_Register($src$$reg);
11084 Register dst_reg = as_Register($dst$$reg);
11085 int shamt = $shift$$constant;
11087 __ dsrl32(dst_reg, src_reg, shamt - 32);
11088 %}
11089 ins_pipe( ialu_regL_regL );
11090 %}
11092 instruct slrL_Reg_immI_convL2I(mRegI dst, mRegL src, immI_32_63 shift) %{
11093 match(Set dst (ConvL2I (URShiftL src shift)));
11094 predicate(n->in(1)->in(2)->get_int() > 32);
11095 ins_cost(80);
11096 format %{ "slrL $dst, $src, $shift @ slrL_Reg_immI_convL2I" %}
11097 ins_encode %{
11098 Register src_reg = as_Register($src$$reg);
11099 Register dst_reg = as_Register($dst$$reg);
11100 int shamt = $shift$$constant;
11102 __ dsrl32(dst_reg, src_reg, shamt - 32);
11103 %}
11104 ins_pipe( ialu_regL_regL );
11105 %}
11107 instruct slrL_P2XReg_immI_32_63(mRegL dst, mRegP src, immI_32_63 shift) %{
11108 match(Set dst (URShiftL (CastP2X src) shift));
11109 ins_cost(80);
11110 format %{ "slrL $dst, $src, $shift @ slrL_P2XReg_immI_32_63" %}
11111 ins_encode %{
11112 Register src_reg = as_Register($src$$reg);
11113 Register dst_reg = as_Register($dst$$reg);
11114 int shamt = $shift$$constant;
11116 __ dsrl32(dst_reg, src_reg, shamt - 32);
11117 %}
11118 ins_pipe( ialu_regL_regL );
11119 %}
11121 // Xor Instructions
11122 // Xor Register with Register
11123 instruct xorI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11124 match(Set dst (XorI src1 src2));
11126 format %{ "XOR $dst, $src1, $src2 #@xorI_Reg_Reg" %}
11128 ins_encode %{
11129 Register dst = $dst$$Register;
11130 Register src1 = $src1$$Register;
11131 Register src2 = $src2$$Register;
11132 __ xorr(dst, src1, src2);
11133 __ sll(dst, dst, 0); /* long -> int */
11134 %}
11136 ins_pipe( ialu_regI_regI );
11137 %}
11139 // Or Instructions
11140 // Or Register with Register
11141 instruct orI_Reg_Reg(mRegI dst, mRegI src1, mRegI src2) %{
11142 match(Set dst (OrI src1 src2));
11144 format %{ "OR $dst, $src1, $src2 #@orI_Reg_Reg" %}
11145 ins_encode %{
11146 Register dst = $dst$$Register;
11147 Register src1 = $src1$$Register;
11148 Register src2 = $src2$$Register;
11149 __ orr(dst, src1, src2);
11150 %}
11152 ins_pipe( ialu_regI_regI );
11153 %}
11155 instruct rotI_shr_logical_Reg(mRegI dst, mRegI src, immI_0_31 rshift, immI_0_31 lshift, immI_1 one) %{
11156 match(Set dst (OrI (URShiftI src rshift) (LShiftI (AndI src one) lshift)));
11157 predicate(32 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int())));
11159 format %{ "rotr $dst, $src, 1 ...\n\t"
11160 "srl $dst, $dst, ($rshift-1) @ rotI_shr_logical_Reg" %}
11161 ins_encode %{
11162 Register dst = $dst$$Register;
11163 Register src = $src$$Register;
11164 int rshift = $rshift$$constant;
11166 __ rotr(dst, src, 1);
11167 if (rshift - 1) {
11168 __ srl(dst, dst, rshift - 1);
11169 }
11170 %}
11172 ins_pipe( ialu_regI_regI );
11173 %}
11175 instruct orI_Reg_castP2X(mRegL dst, mRegL src1, mRegP src2) %{
11176 match(Set dst (OrI src1 (CastP2X src2)));
11178 format %{ "OR $dst, $src1, $src2 #@orI_Reg_castP2X" %}
11179 ins_encode %{
11180 Register dst = $dst$$Register;
11181 Register src1 = $src1$$Register;
11182 Register src2 = $src2$$Register;
11183 __ orr(dst, src1, src2);
11184 %}
11186 ins_pipe( ialu_regI_regI );
11187 %}
11189 // Logical Shift Right by 8-bit immediate
11190 instruct shr_logical_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11191 match(Set dst (URShiftI src shift));
11192 // effect(KILL cr);
11194 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_imm" %}
11195 ins_encode %{
11196 Register src = $src$$Register;
11197 Register dst = $dst$$Register;
11198 int shift = $shift$$constant;
11200 __ srl(dst, src, shift);
11201 %}
11202 ins_pipe( ialu_regI_regI );
11203 %}
11205 instruct shr_logical_Reg_imm_nonneg_mask(mRegI dst, mRegI src, immI_0_31 shift, immI_nonneg_mask mask) %{
11206 match(Set dst (AndI (URShiftI src shift) mask));
11208 format %{ "ext $dst, $src, $shift, one-bits($mask) #@shr_logical_Reg_imm_nonneg_mask" %}
11209 ins_encode %{
11210 Register src = $src$$Register;
11211 Register dst = $dst$$Register;
11212 int pos = $shift$$constant;
11213 int size = Assembler::is_int_mask($mask$$constant);
11215 __ ext(dst, src, pos, size);
11216 %}
11217 ins_pipe( ialu_regI_regI );
11218 %}
11220 instruct rolI_Reg_immI_0_31(mRegI dst, immI_0_31 lshift, immI_0_31 rshift)
11221 %{
11222 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11223 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
11225 ins_cost(100);
11226 format %{ "rotr $dst, $dst, $rshift #@rolI_Reg_immI_0_31" %}
11227 ins_encode %{
11228 Register dst = $dst$$Register;
11229 int sa = $rshift$$constant;
11231 __ rotr(dst, dst, sa);
11232 %}
11233 ins_pipe( ialu_regI_regI );
11234 %}
11236 instruct rolL_Reg_immI_0_31(mRegL dst, immI_32_63 lshift, immI_0_31 rshift)
11237 %{
11238 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11239 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
11241 ins_cost(100);
11242 format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_0_31" %}
11243 ins_encode %{
11244 Register dst = $dst$$Register;
11245 int sa = $rshift$$constant;
11247 __ drotr(dst, dst, sa);
11248 %}
11249 ins_pipe( ialu_regI_regI );
11250 %}
11252 instruct rolL_Reg_immI_32_63(mRegL dst, immI_0_31 lshift, immI_32_63 rshift)
11253 %{
11254 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11255 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
11257 ins_cost(100);
11258 format %{ "rotr $dst, $dst, $rshift #@rolL_Reg_immI_32_63" %}
11259 ins_encode %{
11260 Register dst = $dst$$Register;
11261 int sa = $rshift$$constant;
11263 __ drotr32(dst, dst, sa - 32);
11264 %}
11265 ins_pipe( ialu_regI_regI );
11266 %}
11268 instruct rorI_Reg_immI_0_31(mRegI dst, immI_0_31 rshift, immI_0_31 lshift)
11269 %{
11270 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
11271 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
11273 ins_cost(100);
11274 format %{ "rotr $dst, $dst, $rshift #@rorI_Reg_immI_0_31" %}
11275 ins_encode %{
11276 Register dst = $dst$$Register;
11277 int sa = $rshift$$constant;
11279 __ rotr(dst, dst, sa);
11280 %}
11281 ins_pipe( ialu_regI_regI );
11282 %}
11284 instruct rorL_Reg_immI_0_31(mRegL dst, immI_0_31 rshift, immI_32_63 lshift)
11285 %{
11286 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11287 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
11289 ins_cost(100);
11290 format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_0_31" %}
11291 ins_encode %{
11292 Register dst = $dst$$Register;
11293 int sa = $rshift$$constant;
11295 __ drotr(dst, dst, sa);
11296 %}
11297 ins_pipe( ialu_regI_regI );
11298 %}
11300 instruct rorL_Reg_immI_32_63(mRegL dst, immI_32_63 rshift, immI_0_31 lshift)
11301 %{
11302 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
11303 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
11305 ins_cost(100);
11306 format %{ "rotr $dst, $dst, $rshift #@rorL_Reg_immI_32_63" %}
11307 ins_encode %{
11308 Register dst = $dst$$Register;
11309 int sa = $rshift$$constant;
11311 __ drotr32(dst, dst, sa - 32);
11312 %}
11313 ins_pipe( ialu_regI_regI );
11314 %}
11316 // Logical Shift Right
11317 instruct shr_logical_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11318 match(Set dst (URShiftI src shift));
11320 format %{ "SRL $dst, $src, $shift #@shr_logical_Reg_Reg" %}
11321 ins_encode %{
11322 Register src = $src$$Register;
11323 Register dst = $dst$$Register;
11324 Register shift = $shift$$Register;
11325 __ srlv(dst, src, shift);
11326 %}
11327 ins_pipe( ialu_regI_regI );
11328 %}
11331 instruct shr_arith_Reg_imm(mRegI dst, mRegI src, immI8 shift) %{
11332 match(Set dst (RShiftI src shift));
11333 // effect(KILL cr);
11335 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_imm" %}
11336 ins_encode %{
11337 Register src = $src$$Register;
11338 Register dst = $dst$$Register;
11339 int shift = $shift$$constant;
11340 __ sra(dst, src, shift);
11341 %}
11342 ins_pipe( ialu_regI_regI );
11343 %}
11345 instruct shr_arith_Reg_Reg(mRegI dst, mRegI src, mRegI shift) %{
11346 match(Set dst (RShiftI src shift));
11347 // effect(KILL cr);
11349 format %{ "SRA $dst, $src, $shift #@shr_arith_Reg_Reg" %}
11350 ins_encode %{
11351 Register src = $src$$Register;
11352 Register dst = $dst$$Register;
11353 Register shift = $shift$$Register;
11354 __ srav(dst, src, shift);
11355 %}
11356 ins_pipe( ialu_regI_regI );
11357 %}
11359 //----------Convert Int to Boolean---------------------------------------------
11361 instruct convI2B(mRegI dst, mRegI src) %{
11362 match(Set dst (Conv2B src));
11364 ins_cost(100);
11365 format %{ "convI2B $dst, $src @ convI2B" %}
11366 ins_encode %{
11367 Register dst = as_Register($dst$$reg);
11368 Register src = as_Register($src$$reg);
11370 if (dst != src) {
11371 __ daddiu(dst, R0, 1);
11372 __ movz(dst, R0, src);
11373 } else {
11374 __ move(AT, src);
11375 __ daddiu(dst, R0, 1);
11376 __ movz(dst, R0, AT);
11377 }
11378 %}
11380 ins_pipe( ialu_regL_regL );
11381 %}
11383 instruct convI2L_reg( mRegL dst, mRegI src) %{
11384 match(Set dst (ConvI2L src));
11386 ins_cost(100);
11387 format %{ "SLL $dst, $src @ convI2L_reg\t" %}
11388 ins_encode %{
11389 Register dst = as_Register($dst$$reg);
11390 Register src = as_Register($src$$reg);
11392 if(dst != src) __ sll(dst, src, 0);
11393 %}
11394 ins_pipe( ialu_regL_regL );
11395 %}
11398 instruct convL2I_reg( mRegI dst, mRegL src ) %{
11399 match(Set dst (ConvL2I src));
11401 format %{ "MOV $dst, $src @ convL2I_reg" %}
11402 ins_encode %{
11403 Register dst = as_Register($dst$$reg);
11404 Register src = as_Register($src$$reg);
11406 __ sll(dst, src, 0);
11407 %}
11409 ins_pipe( ialu_regI_regI );
11410 %}
11412 instruct convL2I2L_reg( mRegL dst, mRegL src ) %{
11413 match(Set dst (ConvI2L (ConvL2I src)));
11415 format %{ "sll $dst, $src, 0 @ convL2I2L_reg" %}
11416 ins_encode %{
11417 Register dst = as_Register($dst$$reg);
11418 Register src = as_Register($src$$reg);
11420 __ sll(dst, src, 0);
11421 %}
11423 ins_pipe( ialu_regI_regI );
11424 %}
11426 instruct convL2D_reg( regD dst, mRegL src ) %{
11427 match(Set dst (ConvL2D src));
11428 format %{ "convL2D $dst, $src @ convL2D_reg" %}
11429 ins_encode %{
11430 Register src = as_Register($src$$reg);
11431 FloatRegister dst = as_FloatRegister($dst$$reg);
11433 __ dmtc1(src, dst);
11434 __ cvt_d_l(dst, dst);
11435 %}
11437 ins_pipe( pipe_slow );
11438 %}
11441 instruct convD2L_reg_fast( mRegL dst, regD src ) %{
11442 match(Set dst (ConvD2L src));
11443 ins_cost(150);
11444 format %{ "convD2L $dst, $src @ convD2L_reg_fast" %}
11445 ins_encode %{
11446 Register dst = as_Register($dst$$reg);
11447 FloatRegister src = as_FloatRegister($src$$reg);
11449 Label Done;
11451 __ trunc_l_d(F30, src);
11452 // max_long: 0x7fffffffffffffff
11453 // __ set64(AT, 0x7fffffffffffffff);
11454 __ daddiu(AT, R0, -1);
11455 __ dsrl(AT, AT, 1);
11456 __ dmfc1(dst, F30);
11458 __ bne(dst, AT, Done);
11459 __ delayed()->mtc1(R0, F30);
11461 __ cvt_d_w(F30, F30);
11462 __ c_ult_d(src, F30);
11463 __ bc1f(Done);
11464 __ delayed()->daddiu(T9, R0, -1);
11466 __ c_un_d(src, src); //NaN?
11467 __ subu(dst, T9, AT);
11468 __ movt(dst, R0);
11470 __ bind(Done);
11471 %}
11473 ins_pipe( pipe_slow );
11474 %}
11477 instruct convD2L_reg_slow( mRegL dst, regD src ) %{
11478 match(Set dst (ConvD2L src));
11479 ins_cost(250);
11480 format %{ "convD2L $dst, $src @ convD2L_reg_slow" %}
11481 ins_encode %{
11482 Register dst = as_Register($dst$$reg);
11483 FloatRegister src = as_FloatRegister($src$$reg);
11485 Label L;
11487 __ c_un_d(src, src); //NaN?
11488 __ bc1t(L);
11489 __ delayed();
11490 __ move(dst, R0);
11492 __ trunc_l_d(F30, src);
11493 __ cfc1(AT, 31);
11494 __ li(T9, 0x10000);
11495 __ andr(AT, AT, T9);
11496 __ beq(AT, R0, L);
11497 __ delayed()->dmfc1(dst, F30);
11499 __ mov_d(F12, src);
11500 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2l), 1);
11501 __ move(dst, V0);
11502 __ bind(L);
11503 %}
11505 ins_pipe( pipe_slow );
11506 %}
11509 instruct convF2I_reg_fast( mRegI dst, regF src ) %{
11510 match(Set dst (ConvF2I src));
11511 ins_cost(150);
11512 format %{ "convf2i $dst, $src @ convF2I_reg_fast" %}
11513 ins_encode %{
11514 Register dreg = $dst$$Register;
11515 FloatRegister fval = $src$$FloatRegister;
11516 Label L;
11518 __ trunc_w_s(F30, fval);
11519 __ move(AT, 0x7fffffff);
11520 __ mfc1(dreg, F30);
11521 __ c_un_s(fval, fval); //NaN?
11522 __ movt(dreg, R0);
11524 __ bne(AT, dreg, L);
11525 __ delayed()->lui(T9, 0x8000);
11527 __ mfc1(AT, fval);
11528 __ andr(AT, AT, T9);
11530 __ movn(dreg, T9, AT);
11532 __ bind(L);
11534 %}
11536 ins_pipe( pipe_slow );
11537 %}
11541 instruct convF2I_reg_slow( mRegI dst, regF src ) %{
11542 match(Set dst (ConvF2I src));
11543 ins_cost(250);
11544 format %{ "convf2i $dst, $src @ convF2I_reg_slow" %}
11545 ins_encode %{
11546 Register dreg = $dst$$Register;
11547 FloatRegister fval = $src$$FloatRegister;
11548 Label L;
11550 __ c_un_s(fval, fval); //NaN?
11551 __ bc1t(L);
11552 __ delayed();
11553 __ move(dreg, R0);
11555 __ trunc_w_s(F30, fval);
11557 /* Call SharedRuntime:f2i() to do valid convention */
11558 __ cfc1(AT, 31);
11559 __ li(T9, 0x10000);
11560 __ andr(AT, AT, T9);
11561 __ beq(AT, R0, L);
11562 __ delayed()->mfc1(dreg, F30);
11564 __ mov_s(F12, fval);
11566 /* 2014/01/08 Fu : This bug was found when running ezDS's control-panel.
11567 * J 982 C2 javax.swing.text.BoxView.layoutMajorAxis(II[I[I)V (283 bytes) @ 0x000000555c46aa74
11568 *
11569 * An interger array index has been assigned to V0, and then changed from 1 to Integer.MAX_VALUE.
11570 * V0 is corrupted during call_VM_leaf(), and should be preserved.
11571 */
11572 __ push(fval);
11573 if(dreg != V0) {
11574 __ push(V0);
11575 }
11576 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2i), 1);
11577 if(dreg != V0) {
11578 __ move(dreg, V0);
11579 __ pop(V0);
11580 }
11581 __ pop(fval);
11582 __ bind(L);
11583 %}
11585 ins_pipe( pipe_slow );
11586 %}
11589 instruct convF2L_reg_fast( mRegL dst, regF src ) %{
11590 match(Set dst (ConvF2L src));
11591 ins_cost(150);
11592 format %{ "convf2l $dst, $src @ convF2L_reg_fast" %}
11593 ins_encode %{
11594 Register dreg = $dst$$Register;
11595 FloatRegister fval = $src$$FloatRegister;
11596 Label L;
11598 __ trunc_l_s(F30, fval);
11599 __ daddiu(AT, R0, -1);
11600 __ dsrl(AT, AT, 1);
11601 __ dmfc1(dreg, F30);
11602 __ c_un_s(fval, fval); //NaN?
11603 __ movt(dreg, R0);
11605 __ bne(AT, dreg, L);
11606 __ delayed()->lui(T9, 0x8000);
11608 __ mfc1(AT, fval);
11609 __ andr(AT, AT, T9);
11611 __ dsll32(T9, T9, 0);
11612 __ movn(dreg, T9, AT);
11614 __ bind(L);
11615 %}
11617 ins_pipe( pipe_slow );
11618 %}
11621 instruct convF2L_reg_slow( mRegL dst, regF src ) %{
11622 match(Set dst (ConvF2L src));
11623 ins_cost(250);
11624 format %{ "convf2l $dst, $src @ convF2L_reg_slow" %}
11625 ins_encode %{
11626 Register dst = as_Register($dst$$reg);
11627 FloatRegister fval = $src$$FloatRegister;
11628 Label L;
11630 __ c_un_s(fval, fval); //NaN?
11631 __ bc1t(L);
11632 __ delayed();
11633 __ move(dst, R0);
11635 __ trunc_l_s(F30, fval);
11636 __ cfc1(AT, 31);
11637 __ li(T9, 0x10000);
11638 __ andr(AT, AT, T9);
11639 __ beq(AT, R0, L);
11640 __ delayed()->dmfc1(dst, F30);
11642 __ mov_s(F12, fval);
11643 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::f2l), 1);
11644 __ move(dst, V0);
11645 __ bind(L);
11646 %}
11648 ins_pipe( pipe_slow );
11649 %}
11651 instruct convL2F_reg( regF dst, mRegL src ) %{
11652 match(Set dst (ConvL2F src));
11653 format %{ "convl2f $dst, $src @ convL2F_reg" %}
11654 ins_encode %{
11655 FloatRegister dst = $dst$$FloatRegister;
11656 Register src = as_Register($src$$reg);
11657 Label L;
11659 __ dmtc1(src, dst);
11660 __ cvt_s_l(dst, dst);
11661 %}
11663 ins_pipe( pipe_slow );
11664 %}
11666 instruct convI2F_reg( regF dst, mRegI src ) %{
11667 match(Set dst (ConvI2F src));
11668 format %{ "convi2f $dst, $src @ convI2F_reg" %}
11669 ins_encode %{
11670 Register src = $src$$Register;
11671 FloatRegister dst = $dst$$FloatRegister;
11673 __ mtc1(src, dst);
11674 __ cvt_s_w(dst, dst);
11675 %}
11677 ins_pipe( fpu_regF_regF );
11678 %}
11680 instruct cmpLTMask_immI0( mRegI dst, mRegI p, immI0 zero ) %{
11681 match(Set dst (CmpLTMask p zero));
11682 ins_cost(100);
11684 format %{ "sra $dst, $p, 31 @ cmpLTMask_immI0" %}
11685 ins_encode %{
11686 Register src = $p$$Register;
11687 Register dst = $dst$$Register;
11689 __ sra(dst, src, 31);
11690 %}
11691 ins_pipe( pipe_slow );
11692 %}
11695 instruct cmpLTMask( mRegI dst, mRegI p, mRegI q ) %{
11696 match(Set dst (CmpLTMask p q));
11697 ins_cost(400);
11699 format %{ "cmpLTMask $dst, $p, $q @ cmpLTMask" %}
11700 ins_encode %{
11701 Register p = $p$$Register;
11702 Register q = $q$$Register;
11703 Register dst = $dst$$Register;
11705 __ slt(dst, p, q);
11706 __ subu(dst, R0, dst);
11707 %}
11708 ins_pipe( pipe_slow );
11709 %}
11711 instruct convP2B(mRegI dst, mRegP src) %{
11712 match(Set dst (Conv2B src));
11714 ins_cost(100);
11715 format %{ "convP2B $dst, $src @ convP2B" %}
11716 ins_encode %{
11717 Register dst = as_Register($dst$$reg);
11718 Register src = as_Register($src$$reg);
11720 if (dst != src) {
11721 __ daddiu(dst, R0, 1);
11722 __ movz(dst, R0, src);
11723 } else {
11724 __ move(AT, src);
11725 __ daddiu(dst, R0, 1);
11726 __ movz(dst, R0, AT);
11727 }
11728 %}
11730 ins_pipe( ialu_regL_regL );
11731 %}
11734 instruct convI2D_reg_reg(regD dst, mRegI src) %{
11735 match(Set dst (ConvI2D src));
11736 format %{ "conI2D $dst, $src @convI2D_reg" %}
11737 ins_encode %{
11738 Register src = $src$$Register;
11739 FloatRegister dst = $dst$$FloatRegister;
11740 __ mtc1(src, dst);
11741 __ cvt_d_w(dst, dst);
11742 %}
11743 ins_pipe( fpu_regF_regF );
11744 %}
11746 instruct convF2D_reg_reg(regD dst, regF src) %{
11747 match(Set dst (ConvF2D src));
11748 format %{ "convF2D $dst, $src\t# @convF2D_reg_reg" %}
11749 ins_encode %{
11750 FloatRegister dst = $dst$$FloatRegister;
11751 FloatRegister src = $src$$FloatRegister;
11753 __ cvt_d_s(dst, src);
11754 %}
11755 ins_pipe( fpu_regF_regF );
11756 %}
11758 instruct convD2F_reg_reg(regF dst, regD src) %{
11759 match(Set dst (ConvD2F src));
11760 format %{ "convD2F $dst, $src\t# @convD2F_reg_reg" %}
11761 ins_encode %{
11762 FloatRegister dst = $dst$$FloatRegister;
11763 FloatRegister src = $src$$FloatRegister;
11765 __ cvt_s_d(dst, src);
11766 %}
11767 ins_pipe( fpu_regF_regF );
11768 %}
11771 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11772 instruct convD2I_reg_reg_fast( mRegI dst, regD src ) %{
11773 match(Set dst (ConvD2I src));
11775 ins_cost(150);
11776 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_fast" %}
11778 ins_encode %{
11779 FloatRegister src = $src$$FloatRegister;
11780 Register dst = $dst$$Register;
11782 Label Done;
11784 __ trunc_w_d(F30, src);
11785 // max_int: 2147483647
11786 __ move(AT, 0x7fffffff);
11787 __ mfc1(dst, F30);
11789 __ bne(dst, AT, Done);
11790 __ delayed()->mtc1(R0, F30);
11792 __ cvt_d_w(F30, F30);
11793 __ c_ult_d(src, F30);
11794 __ bc1f(Done);
11795 __ delayed()->addiu(T9, R0, -1);
11797 __ c_un_d(src, src); //NaN?
11798 __ subu32(dst, T9, AT);
11799 __ movt(dst, R0);
11801 __ bind(Done);
11802 %}
11803 ins_pipe( pipe_slow );
11804 %}
11807 instruct convD2I_reg_reg_slow( mRegI dst, regD src ) %{
11808 match(Set dst (ConvD2I src));
11810 ins_cost(250);
11811 format %{ "convD2I $dst, $src\t# @ convD2I_reg_reg_slow" %}
11813 ins_encode %{
11814 FloatRegister src = $src$$FloatRegister;
11815 Register dst = $dst$$Register;
11816 Label L;
11818 __ trunc_w_d(F30, src);
11819 __ cfc1(AT, 31);
11820 __ li(T9, 0x10000);
11821 __ andr(AT, AT, T9);
11822 __ beq(AT, R0, L);
11823 __ delayed()->mfc1(dst, F30);
11825 __ mov_d(F12, src);
11826 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::d2i), 1);
11827 __ move(dst, V0);
11828 __ bind(L);
11830 %}
11831 ins_pipe( pipe_slow );
11832 %}
11834 // Convert oop pointer into compressed form
11835 instruct encodeHeapOop(mRegN dst, mRegP src) %{
11836 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
11837 match(Set dst (EncodeP src));
11838 format %{ "encode_heap_oop $dst,$src" %}
11839 ins_encode %{
11840 Register src = $src$$Register;
11841 Register dst = $dst$$Register;
11843 __ encode_heap_oop(dst, src);
11844 %}
11845 ins_pipe( ialu_regL_regL );
11846 %}
11848 instruct encodeHeapOop_not_null(mRegN dst, mRegP src) %{
11849 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
11850 match(Set dst (EncodeP src));
11851 format %{ "encode_heap_oop_not_null $dst,$src @ encodeHeapOop_not_null" %}
11852 ins_encode %{
11853 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
11854 %}
11855 ins_pipe( ialu_regL_regL );
11856 %}
11858 instruct decodeHeapOop(mRegP dst, mRegN src) %{
11859 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
11860 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
11861 match(Set dst (DecodeN src));
11862 format %{ "decode_heap_oop $dst,$src @ decodeHeapOop" %}
11863 ins_encode %{
11864 Register s = $src$$Register;
11865 Register d = $dst$$Register;
11867 __ decode_heap_oop(d, s);
11868 %}
11869 ins_pipe( ialu_regL_regL );
11870 %}
11872 instruct decodeHeapOop_not_null(mRegP dst, mRegN src) %{
11873 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
11874 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
11875 match(Set dst (DecodeN src));
11876 format %{ "decode_heap_oop_not_null $dst,$src @ decodeHeapOop_not_null" %}
11877 ins_encode %{
11878 Register s = $src$$Register;
11879 Register d = $dst$$Register;
11880 if (s != d) {
11881 __ decode_heap_oop_not_null(d, s);
11882 } else {
11883 __ decode_heap_oop_not_null(d);
11884 }
11885 %}
11886 ins_pipe( ialu_regL_regL );
11887 %}
11889 instruct encodeKlass_not_null(mRegN dst, mRegP src) %{
11890 match(Set dst (EncodePKlass src));
11891 format %{ "encode_heap_oop_not_null $dst,$src @ encodeKlass_not_null" %}
11892 ins_encode %{
11893 __ encode_klass_not_null($dst$$Register, $src$$Register);
11894 %}
11895 ins_pipe( ialu_regL_regL );
11896 %}
11898 instruct decodeKlass_not_null(mRegP dst, mRegN src) %{
11899 match(Set dst (DecodeNKlass src));
11900 format %{ "decode_heap_klass_not_null $dst,$src" %}
11901 ins_encode %{
11902 Register s = $src$$Register;
11903 Register d = $dst$$Register;
11904 if (s != d) {
11905 __ decode_klass_not_null(d, s);
11906 } else {
11907 __ decode_klass_not_null(d);
11908 }
11909 %}
11910 ins_pipe( ialu_regL_regL );
11911 %}
11913 //FIXME
11914 instruct tlsLoadP(mRegP dst) %{
11915 match(Set dst (ThreadLocal));
11917 ins_cost(0);
11918 format %{ " get_thread in $dst #@tlsLoadP" %}
11919 ins_encode %{
11920 Register dst = $dst$$Register;
11921 #ifdef OPT_THREAD
11922 __ move(dst, TREG);
11923 #else
11924 __ get_thread(dst);
11925 #endif
11926 %}
11928 ins_pipe( ialu_loadI );
11929 %}
11932 instruct checkCastPP( mRegP dst ) %{
11933 match(Set dst (CheckCastPP dst));
11935 format %{ "#checkcastPP of $dst (empty encoding) #@chekCastPP" %}
11936 ins_encode( /*empty encoding*/ );
11937 ins_pipe( empty );
11938 %}
11940 instruct castPP(mRegP dst)
11941 %{
11942 match(Set dst (CastPP dst));
11944 size(0);
11945 format %{ "# castPP of $dst" %}
11946 ins_encode(/* empty encoding */);
11947 ins_pipe(empty);
11948 %}
11950 instruct castII( mRegI dst ) %{
11951 match(Set dst (CastII dst));
11952 format %{ "#castII of $dst empty encoding" %}
11953 ins_encode( /*empty encoding*/ );
11954 ins_cost(0);
11955 ins_pipe( empty );
11956 %}
11958 // Return Instruction
11959 // Remove the return address & jump to it.
11960 instruct Ret() %{
11961 match(Return);
11962 format %{ "RET #@Ret" %}
11964 ins_encode %{
11965 __ jr(RA);
11966 __ nop();
11967 %}
11969 ins_pipe( pipe_jump );
11970 %}
11972 /*
11973 // For Loongson CPUs, jr seems too slow, so this rule shouldn't be imported.
11974 instruct jumpXtnd(mRegL switch_val) %{
11975 match(Jump switch_val);
11977 ins_cost(350);
11979 format %{ "load T9 <-- [$constanttablebase, $switch_val, $constantoffset] @ jumpXtnd\n\t"
11980 "jr T9\n\t"
11981 "nop" %}
11982 ins_encode %{
11983 Register table_base = $constanttablebase;
11984 int con_offset = $constantoffset;
11985 Register switch_reg = $switch_val$$Register;
11987 if (UseLoongsonISA) {
11988 if (Assembler::is_simm(con_offset, 8)) {
11989 __ gsldx(T9, table_base, switch_reg, con_offset);
11990 } else if (Assembler::is_simm16(con_offset)) {
11991 __ daddu(T9, table_base, switch_reg);
11992 __ ld(T9, T9, con_offset);
11993 } else {
11994 __ move(T9, con_offset);
11995 __ daddu(AT, table_base, switch_reg);
11996 __ gsldx(T9, AT, T9, 0);
11997 }
11998 } else {
11999 if (Assembler::is_simm16(con_offset)) {
12000 __ daddu(T9, table_base, switch_reg);
12001 __ ld(T9, T9, con_offset);
12002 } else {
12003 __ move(T9, con_offset);
12004 __ daddu(AT, table_base, switch_reg);
12005 __ daddu(AT, T9, AT);
12006 __ ld(T9, AT, 0);
12007 }
12008 }
12010 __ jr(T9);
12011 __ nop();
12013 %}
12014 ins_pipe(pipe_jump);
12015 %}
12016 */
12018 // Jump Direct - Label defines a relative address from JMP
12019 instruct jmpDir(label labl) %{
12020 match(Goto);
12021 effect(USE labl);
12023 ins_cost(300);
12024 format %{ "JMP $labl #@jmpDir" %}
12026 ins_encode %{
12027 Label &L = *($labl$$label);
12028 if(&L)
12029 __ b(L);
12030 else
12031 __ b(int(0));
12032 __ nop();
12033 %}
12035 ins_pipe( pipe_jump );
12036 ins_pc_relative(1);
12037 %}
12041 // Tail Jump; remove the return address; jump to target.
12042 // TailCall above leaves the return address around.
12043 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
12044 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
12045 // "restore" before this instruction (in Epilogue), we need to materialize it
12046 // in %i0.
12047 //FIXME
12048 instruct tailjmpInd(mRegP jump_target,mRegP ex_oop) %{
12049 match( TailJump jump_target ex_oop );
12050 ins_cost(200);
12051 format %{ "Jmp $jump_target ; ex_oop = $ex_oop #@tailjmpInd" %}
12052 ins_encode %{
12053 Register target = $jump_target$$Register;
12055 /* 2012/9/14 Jin: V0, V1 are indicated in:
12056 * [stubGenerator_mips.cpp] generate_forward_exception()
12057 * [runtime_mips.cpp] OptoRuntime::generate_exception_blob()
12058 */
12059 Register oop = $ex_oop$$Register;
12060 Register exception_oop = V0;
12061 Register exception_pc = V1;
12063 __ move(exception_pc, RA);
12064 __ move(exception_oop, oop);
12066 __ jr(target);
12067 __ nop();
12068 %}
12069 ins_pipe( pipe_jump );
12070 %}
12072 // ============================================================================
12073 // Procedure Call/Return Instructions
12074 // Call Java Static Instruction
12075 // Note: If this code changes, the corresponding ret_addr_offset() and
12076 // compute_padding() functions will have to be adjusted.
12077 instruct CallStaticJavaDirect(method meth) %{
12078 match(CallStaticJava);
12079 effect(USE meth);
12081 ins_cost(300);
12082 format %{ "CALL,static #@CallStaticJavaDirect " %}
12083 ins_encode( Java_Static_Call( meth ) );
12084 ins_pipe( pipe_slow );
12085 ins_pc_relative(1);
12086 %}
12088 // Call Java Dynamic Instruction
12089 // Note: If this code changes, the corresponding ret_addr_offset() and
12090 // compute_padding() functions will have to be adjusted.
12091 instruct CallDynamicJavaDirect(method meth) %{
12092 match(CallDynamicJava);
12093 effect(USE meth);
12095 ins_cost(300);
12096 format %{"MOV IC_Klass, (oop)-1\n\t"
12097 "CallDynamic @ CallDynamicJavaDirect" %}
12098 ins_encode( Java_Dynamic_Call( meth ) );
12099 ins_pipe( pipe_slow );
12100 ins_pc_relative(1);
12101 %}
12103 instruct CallLeafNoFPDirect(method meth) %{
12104 match(CallLeafNoFP);
12105 effect(USE meth);
12107 ins_cost(300);
12108 format %{ "CALL_LEAF_NOFP,runtime " %}
12109 ins_encode(Java_To_Runtime(meth));
12110 ins_pipe( pipe_slow );
12111 ins_pc_relative(1);
12112 ins_alignment(16);
12113 %}
12115 // Prefetch instructions.
12117 instruct prefetchrNTA( memory mem ) %{
12118 match(PrefetchRead mem);
12119 ins_cost(125);
12121 format %{ "pref $mem\t# Prefetch into non-temporal cache for read @ prefetchrNTA" %}
12122 ins_encode %{
12123 int base = $mem$$base;
12124 int index = $mem$$index;
12125 int scale = $mem$$scale;
12126 int disp = $mem$$disp;
12128 if( index != 0 ) {
12129 if (scale == 0) {
12130 __ daddu(AT, as_Register(base), as_Register(index));
12131 } else {
12132 __ dsll(AT, as_Register(index), scale);
12133 __ daddu(AT, as_Register(base), AT);
12134 }
12135 } else {
12136 __ move(AT, as_Register(base));
12137 }
12138 if( Assembler::is_simm16(disp) ) {
12139 __ daddiu(AT, as_Register(base), disp);
12140 __ daddiu(AT, AT, disp);
12141 } else {
12142 __ move(T9, disp);
12143 __ daddu(AT, as_Register(base), T9);
12144 }
12145 __ pref(0, AT, 0); //hint: 0:load
12146 %}
12147 ins_pipe(pipe_slow);
12148 %}
12150 instruct prefetchwNTA( memory mem ) %{
12151 match(PrefetchWrite mem);
12152 ins_cost(125);
12153 format %{ "pref $mem\t# Prefetch to non-temporal cache for write @ prefetchwNTA" %}
12154 ins_encode %{
12155 int base = $mem$$base;
12156 int index = $mem$$index;
12157 int scale = $mem$$scale;
12158 int disp = $mem$$disp;
12160 if( index != 0 ) {
12161 if (scale == 0) {
12162 __ daddu(AT, as_Register(base), as_Register(index));
12163 } else {
12164 __ dsll(AT, as_Register(index), scale);
12165 __ daddu(AT, as_Register(base), AT);
12166 }
12167 } else {
12168 __ move(AT, as_Register(base));
12169 }
12170 if( Assembler::is_simm16(disp) ) {
12171 __ daddiu(AT, as_Register(base), disp);
12172 __ daddiu(AT, AT, disp);
12173 } else {
12174 __ move(T9, disp);
12175 __ daddu(AT, as_Register(base), T9);
12176 }
12177 __ pref(1, AT, 0); //hint: 1:store
12178 %}
12179 ins_pipe(pipe_slow);
12180 %}
12182 // Prefetch instructions for allocation.
12184 instruct prefetchAllocNTA( memory mem ) %{
12185 match(PrefetchAllocation mem);
12186 ins_cost(125);
12187 format %{ "pref $mem\t# Prefetch allocation @ prefetchAllocNTA" %}
12188 ins_encode %{
12189 int base = $mem$$base;
12190 int index = $mem$$index;
12191 int scale = $mem$$scale;
12192 int disp = $mem$$disp;
12194 Register dst = R0;
12196 if( index != 0 ) {
12197 if( Assembler::is_simm16(disp) ) {
12198 if( UseLoongsonISA ) {
12199 if (scale == 0) {
12200 __ gslbx(dst, as_Register(base), as_Register(index), disp);
12201 } else {
12202 __ dsll(AT, as_Register(index), scale);
12203 __ gslbx(dst, as_Register(base), AT, disp);
12204 }
12205 } else {
12206 if (scale == 0) {
12207 __ addu(AT, as_Register(base), as_Register(index));
12208 } else {
12209 __ dsll(AT, as_Register(index), scale);
12210 __ addu(AT, as_Register(base), AT);
12211 }
12212 __ lb(dst, AT, disp);
12213 }
12214 } else {
12215 if (scale == 0) {
12216 __ addu(AT, as_Register(base), as_Register(index));
12217 } else {
12218 __ dsll(AT, as_Register(index), scale);
12219 __ addu(AT, as_Register(base), AT);
12220 }
12221 __ move(T9, disp);
12222 if( UseLoongsonISA ) {
12223 __ gslbx(dst, AT, T9, 0);
12224 } else {
12225 __ addu(AT, AT, T9);
12226 __ lb(dst, AT, 0);
12227 }
12228 }
12229 } else {
12230 if( Assembler::is_simm16(disp) ) {
12231 __ lb(dst, as_Register(base), disp);
12232 } else {
12233 __ move(T9, disp);
12234 if( UseLoongsonISA ) {
12235 __ gslbx(dst, as_Register(base), T9, 0);
12236 } else {
12237 __ addu(AT, as_Register(base), T9);
12238 __ lb(dst, AT, 0);
12239 }
12240 }
12241 }
12242 %}
12243 ins_pipe(pipe_slow);
12244 %}
12247 // Call runtime without safepoint
12248 instruct CallLeafDirect(method meth) %{
12249 match(CallLeaf);
12250 effect(USE meth);
12252 ins_cost(300);
12253 format %{ "CALL_LEAF,runtime #@CallLeafDirect " %}
12254 ins_encode(Java_To_Runtime(meth));
12255 ins_pipe( pipe_slow );
12256 ins_pc_relative(1);
12257 ins_alignment(16);
12258 %}
12260 // Load Char (16bit unsigned)
12261 instruct loadUS(mRegI dst, memory mem) %{
12262 match(Set dst (LoadUS mem));
12264 ins_cost(125);
12265 format %{ "loadUS $dst,$mem @ loadC" %}
12266 ins_encode(load_C_enc(dst, mem));
12267 ins_pipe( ialu_loadI );
12268 %}
12270 instruct loadUS_convI2L(mRegL dst, memory mem) %{
12271 match(Set dst (ConvI2L (LoadUS mem)));
12273 ins_cost(125);
12274 format %{ "loadUS $dst,$mem @ loadUS_convI2L" %}
12275 ins_encode(load_C_enc(dst, mem));
12276 ins_pipe( ialu_loadI );
12277 %}
12279 // Store Char (16bit unsigned)
12280 instruct storeC(memory mem, mRegI src) %{
12281 match(Set mem (StoreC mem src));
12283 ins_cost(125);
12284 format %{ "storeC $src, $mem @ storeC" %}
12285 ins_encode(store_C_reg_enc(mem, src));
12286 ins_pipe( ialu_loadI );
12287 %}
12289 instruct storeC0(memory mem, immI0 zero) %{
12290 match(Set mem (StoreC mem zero));
12292 ins_cost(125);
12293 format %{ "storeC $zero, $mem @ storeC0" %}
12294 ins_encode(store_C0_enc(mem));
12295 ins_pipe( ialu_loadI );
12296 %}
12299 instruct loadConF0(regF dst, immF0 zero) %{
12300 match(Set dst zero);
12301 ins_cost(100);
12303 format %{ "mov $dst, zero @ loadConF0\n"%}
12304 ins_encode %{
12305 FloatRegister dst = $dst$$FloatRegister;
12307 __ mtc1(R0, dst);
12308 %}
12309 ins_pipe( fpu_loadF );
12310 %}
12313 instruct loadConF(regF dst, immF src) %{
12314 match(Set dst src);
12315 ins_cost(125);
12317 format %{ "lwc1 $dst, $constantoffset[$constanttablebase] # load FLOAT $src from table @ loadConF" %}
12318 ins_encode %{
12319 int con_offset = $constantoffset($src);
12321 if (Assembler::is_simm16(con_offset)) {
12322 __ lwc1($dst$$FloatRegister, $constanttablebase, con_offset);
12323 } else {
12324 __ set64(AT, con_offset);
12325 if (UseLoongsonISA) {
12326 __ gslwxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12327 } else {
12328 __ daddu(AT, $constanttablebase, AT);
12329 __ lwc1($dst$$FloatRegister, AT, 0);
12330 }
12331 }
12332 %}
12333 ins_pipe( fpu_loadF );
12334 %}
12337 instruct loadConD0(regD dst, immD0 zero) %{
12338 match(Set dst zero);
12339 ins_cost(100);
12341 format %{ "mov $dst, zero @ loadConD0"%}
12342 ins_encode %{
12343 FloatRegister dst = as_FloatRegister($dst$$reg);
12345 __ dmtc1(R0, dst);
12346 %}
12347 ins_pipe( fpu_loadF );
12348 %}
12350 instruct loadConD(regD dst, immD src) %{
12351 match(Set dst src);
12352 ins_cost(125);
12354 format %{ "ldc1 $dst, $constantoffset[$constanttablebase] # load DOUBLE $src from table @ loadConD" %}
12355 ins_encode %{
12356 int con_offset = $constantoffset($src);
12358 if (Assembler::is_simm16(con_offset)) {
12359 __ ldc1($dst$$FloatRegister, $constanttablebase, con_offset);
12360 } else {
12361 __ set64(AT, con_offset);
12362 if (UseLoongsonISA) {
12363 __ gsldxc1($dst$$FloatRegister, $constanttablebase, AT, 0);
12364 } else {
12365 __ daddu(AT, $constanttablebase, AT);
12366 __ ldc1($dst$$FloatRegister, AT, 0);
12367 }
12368 }
12369 %}
12370 ins_pipe( fpu_loadF );
12371 %}
12373 // Store register Float value (it is faster than store from FPU register)
12374 instruct storeF_reg( memory mem, regF src) %{
12375 match(Set mem (StoreF mem src));
12377 ins_cost(50);
12378 format %{ "store $mem, $src\t# store float @ storeF_reg" %}
12379 ins_encode(store_F_reg_enc(mem, src));
12380 ins_pipe( fpu_storeF );
12381 %}
12383 instruct storeF_imm0( memory mem, immF0 zero) %{
12384 match(Set mem (StoreF mem zero));
12386 ins_cost(40);
12387 format %{ "store $mem, zero\t# store float @ storeF_imm0" %}
12388 ins_encode %{
12389 int base = $mem$$base;
12390 int index = $mem$$index;
12391 int scale = $mem$$scale;
12392 int disp = $mem$$disp;
12394 if( index != 0 ) {
12395 if ( UseLoongsonISA ) {
12396 if ( Assembler::is_simm(disp, 8) ) {
12397 if ( scale == 0 ) {
12398 __ gsswx(R0, as_Register(base), as_Register(index), disp);
12399 } else {
12400 __ dsll(T9, as_Register(index), scale);
12401 __ gsswx(R0, as_Register(base), T9, disp);
12402 }
12403 } else if ( Assembler::is_simm16(disp) ) {
12404 if ( scale == 0 ) {
12405 __ daddu(AT, as_Register(base), as_Register(index));
12406 } else {
12407 __ dsll(T9, as_Register(index), scale);
12408 __ daddu(AT, as_Register(base), T9);
12409 }
12410 __ sw(R0, AT, disp);
12411 } else {
12412 if ( scale == 0 ) {
12413 __ move(T9, disp);
12414 __ daddu(AT, as_Register(index), T9);
12415 __ gsswx(R0, as_Register(base), AT, 0);
12416 } else {
12417 __ dsll(T9, as_Register(index), scale);
12418 __ move(AT, disp);
12419 __ daddu(AT, AT, T9);
12420 __ gsswx(R0, as_Register(base), AT, 0);
12421 }
12422 }
12423 } else { //not use loongson isa
12424 if(scale != 0) {
12425 __ dsll(T9, as_Register(index), scale);
12426 __ daddu(AT, as_Register(base), T9);
12427 } else {
12428 __ daddu(AT, as_Register(base), as_Register(index));
12429 }
12430 if( Assembler::is_simm16(disp) ) {
12431 __ sw(R0, AT, disp);
12432 } else {
12433 __ move(T9, disp);
12434 __ daddu(AT, AT, T9);
12435 __ sw(R0, AT, 0);
12436 }
12437 }
12438 } else { //index is 0
12439 if ( UseLoongsonISA ) {
12440 if ( Assembler::is_simm16(disp) ) {
12441 __ sw(R0, as_Register(base), disp);
12442 } else {
12443 __ move(T9, disp);
12444 __ gsswx(R0, as_Register(base), T9, 0);
12445 }
12446 } else {
12447 if( Assembler::is_simm16(disp) ) {
12448 __ sw(R0, as_Register(base), disp);
12449 } else {
12450 __ move(T9, disp);
12451 __ daddu(AT, as_Register(base), T9);
12452 __ sw(R0, AT, 0);
12453 }
12454 }
12455 }
12456 %}
12457 ins_pipe( ialu_storeI );
12458 %}
12460 // Load Double
12461 instruct loadD(regD dst, memory mem) %{
12462 match(Set dst (LoadD mem));
12464 ins_cost(150);
12465 format %{ "loadD $dst, $mem #@loadD" %}
12466 ins_encode(load_D_enc(dst, mem));
12467 ins_pipe( ialu_loadI );
12468 %}
12470 // Load Double - UNaligned
12471 instruct loadD_unaligned(regD dst, memory mem ) %{
12472 match(Set dst (LoadD_unaligned mem));
12473 ins_cost(250);
12474 // FIXME: Jin: Need more effective ldl/ldr
12475 format %{ "loadD_unaligned $dst, $mem #@loadD_unaligned" %}
12476 ins_encode(load_D_enc(dst, mem));
12477 ins_pipe( ialu_loadI );
12478 %}
12480 instruct storeD_reg( memory mem, regD src) %{
12481 match(Set mem (StoreD mem src));
12483 ins_cost(50);
12484 format %{ "store $mem, $src\t# store float @ storeD_reg" %}
12485 ins_encode(store_D_reg_enc(mem, src));
12486 ins_pipe( fpu_storeF );
12487 %}
12489 instruct storeD_imm0( memory mem, immD0 zero) %{
12490 match(Set mem (StoreD mem zero));
12492 ins_cost(40);
12493 format %{ "store $mem, zero\t# store float @ storeD_imm0" %}
12494 ins_encode %{
12495 int base = $mem$$base;
12496 int index = $mem$$index;
12497 int scale = $mem$$scale;
12498 int disp = $mem$$disp;
12500 __ mtc1(R0, F30);
12501 __ cvt_d_w(F30, F30);
12503 if( index != 0 ) {
12504 if ( UseLoongsonISA ) {
12505 if ( Assembler::is_simm(disp, 8) ) {
12506 if (scale == 0) {
12507 __ gssdxc1(F30, as_Register(base), as_Register(index), disp);
12508 } else {
12509 __ dsll(T9, as_Register(index), scale);
12510 __ gssdxc1(F30, as_Register(base), T9, disp);
12511 }
12512 } else if ( Assembler::is_simm16(disp) ) {
12513 if (scale == 0) {
12514 __ daddu(AT, as_Register(base), as_Register(index));
12515 __ sdc1(F30, AT, disp);
12516 } else {
12517 __ dsll(T9, as_Register(index), scale);
12518 __ daddu(AT, as_Register(base), T9);
12519 __ sdc1(F30, AT, disp);
12520 }
12521 } else {
12522 if (scale == 0) {
12523 __ move(T9, disp);
12524 __ daddu(AT, as_Register(index), T9);
12525 __ gssdxc1(F30, as_Register(base), AT, 0);
12526 } else {
12527 __ move(T9, disp);
12528 __ dsll(AT, as_Register(index), scale);
12529 __ daddu(AT, AT, T9);
12530 __ gssdxc1(F30, as_Register(base), AT, 0);
12531 }
12532 }
12533 } else { // not use loongson isa
12534 if(scale != 0) {
12535 __ dsll(T9, as_Register(index), scale);
12536 __ daddu(AT, as_Register(base), T9);
12537 } else {
12538 __ daddu(AT, as_Register(base), as_Register(index));
12539 }
12540 if( Assembler::is_simm16(disp) ) {
12541 __ sdc1(F30, AT, disp);
12542 } else {
12543 __ move(T9, disp);
12544 __ daddu(AT, AT, T9);
12545 __ sdc1(F30, AT, 0);
12546 }
12547 }
12548 } else {// index is 0
12549 if ( UseLoongsonISA ) {
12550 if ( Assembler::is_simm16(disp) ) {
12551 __ sdc1(F30, as_Register(base), disp);
12552 } else {
12553 __ move(T9, disp);
12554 __ gssdxc1(F30, as_Register(base), T9, 0);
12555 }
12556 } else {
12557 if( Assembler::is_simm16(disp) ) {
12558 __ sdc1(F30, as_Register(base), disp);
12559 } else {
12560 __ move(T9, disp);
12561 __ daddu(AT, as_Register(base), T9);
12562 __ sdc1(F30, AT, 0);
12563 }
12564 }
12565 }
12566 %}
12567 ins_pipe( ialu_storeI );
12568 %}
12570 instruct loadSSI(mRegI dst, stackSlotI src)
12571 %{
12572 match(Set dst src);
12574 ins_cost(125);
12575 format %{ "lw $dst, $src\t# int stk @ loadSSI" %}
12576 ins_encode %{
12577 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSI) !");
12578 __ lw($dst$$Register, SP, $src$$disp);
12579 %}
12580 ins_pipe(ialu_loadI);
12581 %}
12583 instruct storeSSI(stackSlotI dst, mRegI src)
12584 %{
12585 match(Set dst src);
12587 ins_cost(100);
12588 format %{ "sw $dst, $src\t# int stk @ storeSSI" %}
12589 ins_encode %{
12590 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSI) !");
12591 __ sw($src$$Register, SP, $dst$$disp);
12592 %}
12593 ins_pipe(ialu_storeI);
12594 %}
12596 instruct loadSSL(mRegL dst, stackSlotL src)
12597 %{
12598 match(Set dst src);
12600 ins_cost(125);
12601 format %{ "ld $dst, $src\t# long stk @ loadSSL" %}
12602 ins_encode %{
12603 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSL) !");
12604 __ ld($dst$$Register, SP, $src$$disp);
12605 %}
12606 ins_pipe(ialu_loadI);
12607 %}
12609 instruct storeSSL(stackSlotL dst, mRegL src)
12610 %{
12611 match(Set dst src);
12613 ins_cost(100);
12614 format %{ "sd $dst, $src\t# long stk @ storeSSL" %}
12615 ins_encode %{
12616 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSL) !");
12617 __ sd($src$$Register, SP, $dst$$disp);
12618 %}
12619 ins_pipe(ialu_storeI);
12620 %}
12622 instruct loadSSP(mRegP dst, stackSlotP src)
12623 %{
12624 match(Set dst src);
12626 ins_cost(125);
12627 format %{ "ld $dst, $src\t# ptr stk @ loadSSP" %}
12628 ins_encode %{
12629 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSP) !");
12630 __ ld($dst$$Register, SP, $src$$disp);
12631 %}
12632 ins_pipe(ialu_loadI);
12633 %}
12635 instruct storeSSP(stackSlotP dst, mRegP src)
12636 %{
12637 match(Set dst src);
12639 ins_cost(100);
12640 format %{ "sd $dst, $src\t# ptr stk @ storeSSP" %}
12641 ins_encode %{
12642 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSP) !");
12643 __ sd($src$$Register, SP, $dst$$disp);
12644 %}
12645 ins_pipe(ialu_storeI);
12646 %}
12648 instruct loadSSF(regF dst, stackSlotF src)
12649 %{
12650 match(Set dst src);
12652 ins_cost(125);
12653 format %{ "lwc1 $dst, $src\t# float stk @ loadSSF" %}
12654 ins_encode %{
12655 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSF) !");
12656 __ lwc1($dst$$FloatRegister, SP, $src$$disp);
12657 %}
12658 ins_pipe(ialu_loadI);
12659 %}
12661 instruct storeSSF(stackSlotF dst, regF src)
12662 %{
12663 match(Set dst src);
12665 ins_cost(100);
12666 format %{ "swc1 $dst, $src\t# float stk @ storeSSF" %}
12667 ins_encode %{
12668 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSF) !");
12669 __ swc1($src$$FloatRegister, SP, $dst$$disp);
12670 %}
12671 ins_pipe(fpu_storeF);
12672 %}
12674 // Use the same format since predicate() can not be used here.
12675 instruct loadSSD(regD dst, stackSlotD src)
12676 %{
12677 match(Set dst src);
12679 ins_cost(125);
12680 format %{ "ldc1 $dst, $src\t# double stk @ loadSSD" %}
12681 ins_encode %{
12682 guarantee( Assembler::is_simm16($src$$disp), "disp too long (loadSSD) !");
12683 __ ldc1($dst$$FloatRegister, SP, $src$$disp);
12684 %}
12685 ins_pipe(ialu_loadI);
12686 %}
12688 instruct storeSSD(stackSlotD dst, regD src)
12689 %{
12690 match(Set dst src);
12692 ins_cost(100);
12693 format %{ "sdc1 $dst, $src\t# double stk @ storeSSD" %}
12694 ins_encode %{
12695 guarantee( Assembler::is_simm16($dst$$disp), "disp too long (storeSSD) !");
12696 __ sdc1($src$$FloatRegister, SP, $dst$$disp);
12697 %}
12698 ins_pipe(fpu_storeF);
12699 %}
12701 instruct cmpFastLock( FlagsReg cr, mRegP object, s0_RegP box, mRegI tmp, mRegP scr) %{
12702 match( Set cr (FastLock object box) );
12703 effect( TEMP tmp, TEMP scr, USE_KILL box );
12704 ins_cost(300);
12705 format %{ "FASTLOCK $cr $object, $box, $tmp #@ cmpFastLock" %}
12706 ins_encode %{
12707 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, $scr$$Register);
12708 %}
12710 ins_pipe( pipe_slow );
12711 ins_pc_relative(1);
12712 %}
12714 instruct cmpFastUnlock( FlagsReg cr, mRegP object, s0_RegP box, mRegP tmp ) %{
12715 match( Set cr (FastUnlock object box) );
12716 effect( TEMP tmp, USE_KILL box );
12717 ins_cost(300);
12718 format %{ "FASTUNLOCK $object, $box, $tmp #@cmpFastUnlock" %}
12719 ins_encode %{
12720 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12721 %}
12723 ins_pipe( pipe_slow );
12724 ins_pc_relative(1);
12725 %}
12727 // Store CMS card-mark Immediate
12728 instruct storeImmCM(memory mem, immI8 src) %{
12729 match(Set mem (StoreCM mem src));
12731 ins_cost(150);
12732 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
12733 // opcode(0xC6);
12734 ins_encode(store_B_immI_enc_sync(mem, src));
12735 ins_pipe( ialu_storeI );
12736 %}
12738 // Die now
12739 instruct ShouldNotReachHere( )
12740 %{
12741 match(Halt);
12742 ins_cost(300);
12744 // Use the following format syntax
12745 format %{ "ILLTRAP ;#@ShouldNotReachHere" %}
12746 ins_encode %{
12747 // Here we should emit illtrap !
12749 __ stop("in ShoudNotReachHere");
12751 %}
12752 ins_pipe( pipe_jump );
12753 %}
12755 instruct leaP8Narrow(mRegP dst, indOffset8Narrow mem)
12756 %{
12757 predicate(Universe::narrow_oop_shift() == 0);
12758 match(Set dst mem);
12760 ins_cost(110);
12761 format %{ "leaq $dst, $mem\t# ptr off8narrow @ leaP8Narrow" %}
12762 ins_encode %{
12763 Register dst = $dst$$Register;
12764 Register base = as_Register($mem$$base);
12765 int disp = $mem$$disp;
12767 __ daddiu(dst, base, disp);
12768 %}
12769 ins_pipe( ialu_regI_imm16 );
12770 %}
12772 instruct leaPPosIdxScaleOff8(mRegP dst, basePosIndexScaleOffset8 mem)
12773 %{
12774 match(Set dst mem);
12776 ins_cost(110);
12777 format %{ "leaq $dst, $mem\t# @ PosIdxScaleOff8" %}
12778 ins_encode %{
12779 Register dst = $dst$$Register;
12780 Register base = as_Register($mem$$base);
12781 Register index = as_Register($mem$$index);
12782 int scale = $mem$$scale;
12783 int disp = $mem$$disp;
12785 if (scale == 0) {
12786 __ daddu(AT, base, index);
12787 __ daddiu(dst, AT, disp);
12788 } else {
12789 __ dsll(AT, index, scale);
12790 __ daddu(AT, base, AT);
12791 __ daddiu(dst, AT, disp);
12792 }
12793 %}
12795 ins_pipe( ialu_regI_imm16 );
12796 %}
12798 instruct leaPIdxScale(mRegP dst, indIndexScale mem)
12799 %{
12800 match(Set dst mem);
12802 ins_cost(110);
12803 format %{ "leaq $dst, $mem\t# @ leaPIdxScale" %}
12804 ins_encode %{
12805 Register dst = $dst$$Register;
12806 Register base = as_Register($mem$$base);
12807 Register index = as_Register($mem$$index);
12808 int scale = $mem$$scale;
12810 if (scale == 0) {
12811 __ daddu(dst, base, index);
12812 } else {
12813 __ dsll(AT, index, scale);
12814 __ daddu(dst, base, AT);
12815 }
12816 %}
12818 ins_pipe( ialu_regI_imm16 );
12819 %}
12821 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12822 instruct jmpLoopEnd(cmpOp cop, mRegI src1, mRegI src2, label labl) %{
12823 match(CountedLoopEnd cop (CmpI src1 src2));
12824 effect(USE labl);
12826 ins_cost(300);
12827 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd" %}
12828 ins_encode %{
12829 Register op1 = $src1$$Register;
12830 Register op2 = $src2$$Register;
12831 Label &L = *($labl$$label);
12832 int flag = $cop$$cmpcode;
12834 switch(flag)
12835 {
12836 case 0x01: //equal
12837 if (&L)
12838 __ beq(op1, op2, L);
12839 else
12840 __ beq(op1, op2, (int)0);
12841 break;
12842 case 0x02: //not_equal
12843 if (&L)
12844 __ bne(op1, op2, L);
12845 else
12846 __ bne(op1, op2, (int)0);
12847 break;
12848 case 0x03: //above
12849 __ slt(AT, op2, op1);
12850 if(&L)
12851 __ bne(AT, R0, L);
12852 else
12853 __ bne(AT, R0, (int)0);
12854 break;
12855 case 0x04: //above_equal
12856 __ slt(AT, op1, op2);
12857 if(&L)
12858 __ beq(AT, R0, L);
12859 else
12860 __ beq(AT, R0, (int)0);
12861 break;
12862 case 0x05: //below
12863 __ slt(AT, op1, op2);
12864 if(&L)
12865 __ bne(AT, R0, L);
12866 else
12867 __ bne(AT, R0, (int)0);
12868 break;
12869 case 0x06: //below_equal
12870 __ slt(AT, op2, op1);
12871 if(&L)
12872 __ beq(AT, R0, L);
12873 else
12874 __ beq(AT, R0, (int)0);
12875 break;
12876 default:
12877 Unimplemented();
12878 }
12879 __ nop();
12880 %}
12881 ins_pipe( pipe_jump );
12882 ins_pc_relative(1);
12883 %}
12886 instruct jmpLoopEnd_reg_imm16_sub(cmpOp cop, mRegI src1, immI16_sub src2, label labl) %{
12887 match(CountedLoopEnd cop (CmpI src1 src2));
12888 effect(USE labl);
12890 ins_cost(250);
12891 format %{ "J$cop $src1, $src2, $labl\t# Loop end @ jmpLoopEnd_reg_imm16_sub" %}
12892 ins_encode %{
12893 Register op1 = $src1$$Register;
12894 int op2 = $src2$$constant;
12895 Label &L = *($labl$$label);
12896 int flag = $cop$$cmpcode;
12898 __ addiu32(AT, op1, -1 * op2);
12900 switch(flag)
12901 {
12902 case 0x01: //equal
12903 if (&L)
12904 __ beq(AT, R0, L);
12905 else
12906 __ beq(AT, R0, (int)0);
12907 break;
12908 case 0x02: //not_equal
12909 if (&L)
12910 __ bne(AT, R0, L);
12911 else
12912 __ bne(AT, R0, (int)0);
12913 break;
12914 case 0x03: //above
12915 if(&L)
12916 __ bgtz(AT, L);
12917 else
12918 __ bgtz(AT, (int)0);
12919 break;
12920 case 0x04: //above_equal
12921 if(&L)
12922 __ bgez(AT, L);
12923 else
12924 __ bgez(AT,(int)0);
12925 break;
12926 case 0x05: //below
12927 if(&L)
12928 __ bltz(AT, L);
12929 else
12930 __ bltz(AT, (int)0);
12931 break;
12932 case 0x06: //below_equal
12933 if(&L)
12934 __ blez(AT, L);
12935 else
12936 __ blez(AT, (int)0);
12937 break;
12938 default:
12939 Unimplemented();
12940 }
12941 __ nop();
12942 %}
12943 ins_pipe( pipe_jump );
12944 ins_pc_relative(1);
12945 %}
12948 /*
12949 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12950 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12951 match(CountedLoopEnd cop cmp);
12952 effect(USE labl);
12954 ins_cost(300);
12955 format %{ "J$cop,u $labl\t# Loop end" %}
12956 size(6);
12957 opcode(0x0F, 0x80);
12958 ins_encode( Jcc( cop, labl) );
12959 ins_pipe( pipe_jump );
12960 ins_pc_relative(1);
12961 %}
12963 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12964 match(CountedLoopEnd cop cmp);
12965 effect(USE labl);
12967 ins_cost(200);
12968 format %{ "J$cop,u $labl\t# Loop end" %}
12969 opcode(0x0F, 0x80);
12970 ins_encode( Jcc( cop, labl) );
12971 ins_pipe( pipe_jump );
12972 ins_pc_relative(1);
12973 %}
12974 */
12976 // This match pattern is created for StoreIConditional since I cannot match IfNode without a RegFlags! fujie 2012/07/17
12977 instruct jmpCon_flags(cmpOp cop, FlagsReg cr, label labl) %{
12978 match(If cop cr);
12979 effect(USE labl);
12981 ins_cost(300);
12982 format %{ "J$cop $labl #mips uses AT as eflag @jmpCon_flags" %}
12984 ins_encode %{
12985 Label &L = *($labl$$label);
12986 switch($cop$$cmpcode)
12987 {
12988 case 0x01: //equal
12989 if (&L)
12990 __ bne(AT, R0, L);
12991 else
12992 __ bne(AT, R0, (int)0);
12993 break;
12994 case 0x02: //not equal
12995 if (&L)
12996 __ beq(AT, R0, L);
12997 else
12998 __ beq(AT, R0, (int)0);
12999 break;
13000 default:
13001 Unimplemented();
13002 }
13003 __ nop();
13004 %}
13006 ins_pipe( pipe_jump );
13007 ins_pc_relative(1);
13008 %}
13011 // ============================================================================
13012 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
13013 // array for an instance of the superklass. Set a hidden internal cache on a
13014 // hit (cache is checked with exposed code in gen_subtype_check()). Return
13015 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
13016 instruct partialSubtypeCheck( mRegP result, no_T8_mRegP sub, no_T8_mRegP super, mT8RegI tmp ) %{
13017 match(Set result (PartialSubtypeCheck sub super));
13018 effect(KILL tmp);
13019 ins_cost(1100); // slightly larger than the next version
13020 format %{ "partialSubtypeCheck result=$result, sub=$sub, super=$super, tmp=$tmp " %}
13022 ins_encode( enc_PartialSubtypeCheck(result, sub, super, tmp) );
13023 ins_pipe( pipe_slow );
13024 %}
13027 // Conditional-store of an int value.
13028 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
13029 instruct storeIConditional( memory mem, mRegI oldval, mRegI newval, FlagsReg cr ) %{
13030 match(Set cr (StoreIConditional mem (Binary oldval newval)));
13031 // effect(KILL oldval);
13032 format %{ "CMPXCHG $newval, $mem, $oldval \t# @storeIConditional" %}
13034 ins_encode %{
13035 Register oldval = $oldval$$Register;
13036 Register newval = $newval$$Register;
13037 Address addr(as_Register($mem$$base), $mem$$disp);
13038 Label again, failure;
13040 // int base = $mem$$base;
13041 int index = $mem$$index;
13042 int scale = $mem$$scale;
13043 int disp = $mem$$disp;
13045 guarantee(Assembler::is_simm16(disp), "");
13047 if( index != 0 ) {
13048 __ stop("in storeIConditional: index != 0");
13049 } else {
13050 __ bind(again);
13051 if(!Use3A2000) __ sync();
13052 __ ll(AT, addr);
13053 __ bne(AT, oldval, failure);
13054 __ delayed()->addu(AT, R0, R0);
13056 __ addu(AT, newval, R0);
13057 __ sc(AT, addr);
13058 __ beq(AT, R0, again);
13059 __ delayed()->addiu(AT, R0, 0xFF);
13060 __ bind(failure);
13061 __ sync();
13062 }
13063 %}
13065 ins_pipe( long_memory_op );
13066 %}
13068 // Conditional-store of a long value.
13069 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
13070 instruct storeLConditional(memory mem, t2RegL oldval, mRegL newval, FlagsReg cr )
13071 %{
13072 match(Set cr (StoreLConditional mem (Binary oldval newval)));
13073 effect(KILL oldval);
13075 format %{ "cmpxchg $mem, $newval\t# If $oldval == $mem then store $newval into $mem" %}
13076 ins_encode%{
13077 Register oldval = $oldval$$Register;
13078 Register newval = $newval$$Register;
13079 Address addr((Register)$mem$$base, $mem$$disp);
13081 int index = $mem$$index;
13082 int scale = $mem$$scale;
13083 int disp = $mem$$disp;
13085 guarantee(Assembler::is_simm16(disp), "");
13087 if( index != 0 ) {
13088 __ stop("in storeIConditional: index != 0");
13089 } else {
13090 __ cmpxchg(newval, addr, oldval);
13091 }
13092 %}
13093 ins_pipe( long_memory_op );
13094 %}
13097 instruct compareAndSwapI( mRegI res, mRegP mem_ptr, mS2RegI oldval, mRegI newval) %{
13098 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
13099 effect(KILL oldval);
13100 // match(CompareAndSwapI mem_ptr (Binary oldval newval));
13101 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapI\n\t"
13102 "MOV $res, 1 @ compareAndSwapI\n\t"
13103 "BNE AT, R0 @ compareAndSwapI\n\t"
13104 "MOV $res, 0 @ compareAndSwapI\n"
13105 "L:" %}
13106 ins_encode %{
13107 Register newval = $newval$$Register;
13108 Register oldval = $oldval$$Register;
13109 Register res = $res$$Register;
13110 Address addr($mem_ptr$$Register, 0);
13111 Label L;
13113 __ cmpxchg32(newval, addr, oldval);
13114 __ move(res, AT);
13115 %}
13116 ins_pipe( long_memory_op );
13117 %}
13119 //FIXME:
13120 instruct compareAndSwapP( mRegI res, mRegP mem_ptr, s2_RegP oldval, mRegP newval) %{
13121 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
13122 effect(KILL oldval);
13123 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapP\n\t"
13124 "MOV $res, AT @ compareAndSwapP\n\t"
13125 "L:" %}
13126 ins_encode %{
13127 Register newval = $newval$$Register;
13128 Register oldval = $oldval$$Register;
13129 Register res = $res$$Register;
13130 Address addr($mem_ptr$$Register, 0);
13131 Label L;
13133 __ cmpxchg(newval, addr, oldval);
13134 __ move(res, AT);
13135 %}
13136 ins_pipe( long_memory_op );
13137 %}
13139 instruct compareAndSwapN( mRegI res, mRegP mem_ptr, t2_RegN oldval, mRegN newval) %{
13140 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
13141 effect(KILL oldval);
13142 format %{ "CMPXCHG $newval, [$mem_ptr], $oldval @ compareAndSwapN\n\t"
13143 "MOV $res, AT @ compareAndSwapN\n\t"
13144 "L:" %}
13145 ins_encode %{
13146 Register newval = $newval$$Register;
13147 Register oldval = $oldval$$Register;
13148 Register res = $res$$Register;
13149 Address addr($mem_ptr$$Register, 0);
13150 Label L;
13152 /* 2013/7/19 Jin: cmpxchg32 is implemented with ll/sc, which will do sign extension.
13153 * Thus, we should extend oldval's sign for correct comparision.
13154 */
13155 __ sll(oldval, oldval, 0);
13157 __ cmpxchg32(newval, addr, oldval);
13158 __ move(res, AT);
13159 %}
13160 ins_pipe( long_memory_op );
13161 %}
13163 //----------Max and Min--------------------------------------------------------
13164 // Min Instructions
13165 ////
13166 // *** Min and Max using the conditional move are slower than the
13167 // *** branch version on a Pentium III.
13168 // // Conditional move for min
13169 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13170 // effect( USE_DEF op2, USE op1, USE cr );
13171 // format %{ "CMOVlt $op2,$op1\t! min" %}
13172 // opcode(0x4C,0x0F);
13173 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13174 // ins_pipe( pipe_cmov_reg );
13175 //%}
13176 //
13177 //// Min Register with Register (P6 version)
13178 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
13179 // predicate(VM_Version::supports_cmov() );
13180 // match(Set op2 (MinI op1 op2));
13181 // ins_cost(200);
13182 // expand %{
13183 // eFlagsReg cr;
13184 // compI_eReg(cr,op1,op2);
13185 // cmovI_reg_lt(op2,op1,cr);
13186 // %}
13187 //%}
13189 // Min Register with Register (generic version)
13190 instruct minI_Reg_Reg(mRegI dst, mRegI src) %{
13191 match(Set dst (MinI dst src));
13192 //effect(KILL flags);
13193 ins_cost(80);
13195 format %{ "MIN $dst, $src @minI_Reg_Reg" %}
13196 ins_encode %{
13197 Register dst = $dst$$Register;
13198 Register src = $src$$Register;
13200 __ slt(AT, src, dst);
13201 __ movn(dst, src, AT);
13203 %}
13205 ins_pipe( pipe_slow );
13206 %}
13208 // Max Register with Register
13209 // *** Min and Max using the conditional move are slower than the
13210 // *** branch version on a Pentium III.
13211 // // Conditional move for max
13212 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
13213 // effect( USE_DEF op2, USE op1, USE cr );
13214 // format %{ "CMOVgt $op2,$op1\t! max" %}
13215 // opcode(0x4F,0x0F);
13216 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
13217 // ins_pipe( pipe_cmov_reg );
13218 //%}
13219 //
13220 // // Max Register with Register (P6 version)
13221 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
13222 // predicate(VM_Version::supports_cmov() );
13223 // match(Set op2 (MaxI op1 op2));
13224 // ins_cost(200);
13225 // expand %{
13226 // eFlagsReg cr;
13227 // compI_eReg(cr,op1,op2);
13228 // cmovI_reg_gt(op2,op1,cr);
13229 // %}
13230 //%}
13232 // Max Register with Register (generic version)
13233 instruct maxI_Reg_Reg(mRegI dst, mRegI src) %{
13234 match(Set dst (MaxI dst src));
13235 ins_cost(80);
13237 format %{ "MAX $dst, $src @maxI_Reg_Reg" %}
13239 ins_encode %{
13240 Register dst = $dst$$Register;
13241 Register src = $src$$Register;
13243 __ slt(AT, dst, src);
13244 __ movn(dst, src, AT);
13246 %}
13248 ins_pipe( pipe_slow );
13249 %}
13251 instruct maxI_Reg_zero(mRegI dst, immI0 zero) %{
13252 match(Set dst (MaxI dst zero));
13253 ins_cost(50);
13255 format %{ "MAX $dst, 0 @maxI_Reg_zero" %}
13257 ins_encode %{
13258 Register dst = $dst$$Register;
13260 __ slt(AT, dst, R0);
13261 __ movn(dst, R0, AT);
13263 %}
13265 ins_pipe( pipe_slow );
13266 %}
13268 instruct zerox_long_reg_reg(mRegL dst, mRegL src, immL_32bits mask)
13269 %{
13270 match(Set dst (AndL src mask));
13272 format %{ "movl $dst, $src\t# zero-extend long @ zerox_long_reg_reg" %}
13273 ins_encode %{
13274 Register dst = $dst$$Register;
13275 Register src = $src$$Register;
13277 __ dext(dst, src, 0, 32);
13278 %}
13279 ins_pipe(ialu_regI_regI);
13280 %}
13282 instruct combine_i2l(mRegL dst, mRegI src1, immL_32bits mask, mRegI src2, immI_32 shift32)
13283 %{
13284 match(Set dst (OrL (AndL (ConvI2L src1) mask) (LShiftL (ConvI2L src2) shift32)));
13286 format %{ "combine_i2l $dst, $src2(H), $src1(L) @ combine_i2l" %}
13287 ins_encode %{
13288 Register dst = $dst$$Register;
13289 Register src1 = $src1$$Register;
13290 Register src2 = $src2$$Register;
13292 if (src1 == dst) {
13293 __ dinsu(dst, src2, 32, 32);
13294 } else if (src2 == dst) {
13295 __ dsll32(dst, dst, 0);
13296 __ dins(dst, src1, 0, 32);
13297 } else {
13298 __ dext(dst, src1, 0, 32);
13299 __ dinsu(dst, src2, 32, 32);
13300 }
13301 %}
13302 ins_pipe(ialu_regI_regI);
13303 %}
13305 // Zero-extend convert int to long
13306 instruct convI2L_reg_reg_zex(mRegL dst, mRegI src, immL_32bits mask)
13307 %{
13308 match(Set dst (AndL (ConvI2L src) mask));
13310 format %{ "movl $dst, $src\t# i2l zero-extend @ convI2L_reg_reg_zex" %}
13311 ins_encode %{
13312 Register dst = $dst$$Register;
13313 Register src = $src$$Register;
13315 __ dext(dst, src, 0, 32);
13316 %}
13317 ins_pipe(ialu_regI_regI);
13318 %}
13320 instruct convL2I2L_reg_reg_zex(mRegL dst, mRegL src, immL_32bits mask)
13321 %{
13322 match(Set dst (AndL (ConvI2L (ConvL2I src)) mask));
13324 format %{ "movl $dst, $src\t# i2l zero-extend @ convL2I2L_reg_reg_zex" %}
13325 ins_encode %{
13326 Register dst = $dst$$Register;
13327 Register src = $src$$Register;
13329 __ dext(dst, src, 0, 32);
13330 %}
13331 ins_pipe(ialu_regI_regI);
13332 %}
13334 // Match loading integer and casting it to unsigned int in long register.
13335 // LoadI + ConvI2L + AndL 0xffffffff.
13336 instruct loadUI2L_rmask(mRegL dst, memory mem, immL_32bits mask) %{
13337 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
13339 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_rmask" %}
13340 ins_encode (load_N_enc(dst, mem));
13341 ins_pipe(ialu_loadI);
13342 %}
13344 instruct loadUI2L_lmask(mRegL dst, memory mem, immL_32bits mask) %{
13345 match(Set dst (AndL mask (ConvI2L (LoadI mem))));
13347 format %{ "lwu $dst, $mem \t// zero-extend to long @ loadUI2L_lmask" %}
13348 ins_encode (load_N_enc(dst, mem));
13349 ins_pipe(ialu_loadI);
13350 %}
13353 // ============================================================================
13354 // Safepoint Instruction
13355 instruct safePoint_poll_reg(mRegP poll) %{
13356 match(SafePoint poll);
13357 predicate(false);
13358 effect(USE poll);
13360 ins_cost(125);
13361 format %{ "Safepoint @ [$poll] : poll for GC @ safePoint_poll_reg" %}
13363 ins_encode %{
13364 Register poll_reg = $poll$$Register;
13366 __ block_comment("Safepoint:");
13367 __ relocate(relocInfo::poll_type);
13368 __ lw(AT, poll_reg, 0);
13369 %}
13371 ins_pipe( ialu_storeI );
13372 %}
13374 instruct safePoint_poll() %{
13375 match(SafePoint);
13377 ins_cost(105);
13378 format %{ "poll for GC @ safePoint_poll" %}
13380 ins_encode %{
13381 __ block_comment("Safepoint:");
13382 __ set64(T9, (long)os::get_polling_page());
13383 __ relocate(relocInfo::poll_type);
13384 __ lw(AT, T9, 0);
13385 %}
13387 ins_pipe( ialu_storeI );
13388 %}
13390 //----------Arithmetic Conversion Instructions---------------------------------
13392 instruct roundFloat_nop(regF dst)
13393 %{
13394 match(Set dst (RoundFloat dst));
13396 ins_cost(0);
13397 ins_encode();
13398 ins_pipe(empty);
13399 %}
13401 instruct roundDouble_nop(regD dst)
13402 %{
13403 match(Set dst (RoundDouble dst));
13405 ins_cost(0);
13406 ins_encode();
13407 ins_pipe(empty);
13408 %}
13410 //---------- Zeros Count Instructions ------------------------------------------
13411 // CountLeadingZerosINode CountTrailingZerosINode
13412 instruct countLeadingZerosI(mRegI dst, mRegI src) %{
13413 predicate(UseCountLeadingZerosInstruction);
13414 match(Set dst (CountLeadingZerosI src));
13416 format %{ "clz $dst, $src\t# count leading zeros (int)" %}
13417 ins_encode %{
13418 __ clz($dst$$Register, $src$$Register);
13419 %}
13420 ins_pipe( ialu_regL_regL );
13421 %}
13423 instruct countLeadingZerosL(mRegI dst, mRegL src) %{
13424 predicate(UseCountLeadingZerosInstruction);
13425 match(Set dst (CountLeadingZerosL src));
13427 format %{ "dclz $dst, $src\t# count leading zeros (long)" %}
13428 ins_encode %{
13429 __ dclz($dst$$Register, $src$$Register);
13430 %}
13431 ins_pipe( ialu_regL_regL );
13432 %}
13434 instruct countTrailingZerosI(mRegI dst, mRegI src) %{
13435 predicate(UseCountTrailingZerosInstruction);
13436 match(Set dst (CountTrailingZerosI src));
13438 format %{ "ctz $dst, $src\t# count trailing zeros (int)" %}
13439 ins_encode %{
13440 // ctz and dctz is gs instructions.
13441 __ ctz($dst$$Register, $src$$Register);
13442 %}
13443 ins_pipe( ialu_regL_regL );
13444 %}
13446 instruct countTrailingZerosL(mRegI dst, mRegL src) %{
13447 predicate(UseCountTrailingZerosInstruction);
13448 match(Set dst (CountTrailingZerosL src));
13450 format %{ "dcto $dst, $src\t# count trailing zeros (long)" %}
13451 ins_encode %{
13452 __ dctz($dst$$Register, $src$$Register);
13453 %}
13454 ins_pipe( ialu_regL_regL );
13455 %}
13457 // ====================VECTOR INSTRUCTIONS=====================================
13459 // Load vectors (8 bytes long)
13460 instruct loadV8(vecD dst, memory mem) %{
13461 predicate(n->as_LoadVector()->memory_size() == 8);
13462 match(Set dst (LoadVector mem));
13463 ins_cost(125);
13464 format %{ "load $dst, $mem\t! load vector (8 bytes)" %}
13465 ins_encode(load_D_enc(dst, mem));
13466 ins_pipe( fpu_loadF );
13467 %}
13469 // Store vectors (8 bytes long)
13470 instruct storeV8(memory mem, vecD src) %{
13471 predicate(n->as_StoreVector()->memory_size() == 8);
13472 match(Set mem (StoreVector mem src));
13473 ins_cost(145);
13474 format %{ "store $mem, $src\t! store vector (8 bytes)" %}
13475 ins_encode(store_D_reg_enc(mem, src));
13476 ins_pipe( fpu_storeF );
13477 %}
13479 instruct Repl8B_DSP(vecD dst, mRegI src) %{
13480 predicate(n->as_Vector()->length() == 8 && Use3A2000);
13481 match(Set dst (ReplicateB src));
13482 ins_cost(100);
13483 format %{ "replv_ob AT, $src\n\t"
13484 "dmtc1 AT, $dst\t! replicate8B" %}
13485 ins_encode %{
13486 __ replv_ob(AT, $src$$Register);
13487 __ dmtc1(AT, $dst$$FloatRegister);
13488 %}
13489 ins_pipe( pipe_mtc1 );
13490 %}
13492 instruct Repl8B(vecD dst, mRegI src) %{
13493 predicate(n->as_Vector()->length() == 8);
13494 match(Set dst (ReplicateB src));
13495 ins_cost(140);
13496 format %{ "move AT, $src\n\t"
13497 "dins AT, AT, 8, 8\n\t"
13498 "dins AT, AT, 16, 16\n\t"
13499 "dinsu AT, AT, 32, 32\n\t"
13500 "dmtc1 AT, $dst\t! replicate8B" %}
13501 ins_encode %{
13502 __ move(AT, $src$$Register);
13503 __ dins(AT, AT, 8, 8);
13504 __ dins(AT, AT, 16, 16);
13505 __ dinsu(AT, AT, 32, 32);
13506 __ dmtc1(AT, $dst$$FloatRegister);
13507 %}
13508 ins_pipe( pipe_mtc1 );
13509 %}
13511 instruct Repl8B_imm_DSP(vecD dst, immI con) %{
13512 predicate(n->as_Vector()->length() == 8 && Use3A2000);
13513 match(Set dst (ReplicateB con));
13514 ins_cost(110);
13515 format %{ "repl_ob AT, [$con]\n\t"
13516 "dmtc1 AT, $dst,0x00\t! replicate8B($con)" %}
13517 ins_encode %{
13518 int val = $con$$constant;
13519 __ repl_ob(AT, val);
13520 __ dmtc1(AT, $dst$$FloatRegister);
13521 %}
13522 ins_pipe( pipe_mtc1 );
13523 %}
13525 instruct Repl8B_imm(vecD dst, immI con) %{
13526 predicate(n->as_Vector()->length() == 8);
13527 match(Set dst (ReplicateB con));
13528 ins_cost(150);
13529 format %{ "move AT, [$con]\n\t"
13530 "dins AT, AT, 8, 8\n\t"
13531 "dins AT, AT, 16, 16\n\t"
13532 "dinsu AT, AT, 32, 32\n\t"
13533 "dmtc1 AT, $dst,0x00\t! replicate8B($con)" %}
13534 ins_encode %{
13535 __ move(AT, $con$$constant);
13536 __ dins(AT, AT, 8, 8);
13537 __ dins(AT, AT, 16, 16);
13538 __ dinsu(AT, AT, 32, 32);
13539 __ dmtc1(AT, $dst$$FloatRegister);
13540 %}
13541 ins_pipe( pipe_mtc1 );
13542 %}
13544 instruct Repl8B_zero(vecD dst, immI0 zero) %{
13545 predicate(n->as_Vector()->length() == 8);
13546 match(Set dst (ReplicateB zero));
13547 ins_cost(90);
13548 format %{ "dmtc1 R0, $dst\t! replicate8B zero" %}
13549 ins_encode %{
13550 __ dmtc1(R0, $dst$$FloatRegister);
13551 %}
13552 ins_pipe( pipe_mtc1 );
13553 %}
13555 instruct Repl8B_M1(vecD dst, immI_M1 M1) %{
13556 predicate(n->as_Vector()->length() == 8);
13557 match(Set dst (ReplicateB M1));
13558 ins_cost(80);
13559 format %{ "dmtc1 -1, $dst\t! replicate8B -1" %}
13560 ins_encode %{
13561 __ nor(AT, R0, R0);
13562 __ dmtc1(AT, $dst$$FloatRegister);
13563 %}
13564 ins_pipe( pipe_mtc1 );
13565 %}
13567 instruct Repl4S_DSP(vecD dst, mRegI src) %{
13568 predicate(n->as_Vector()->length() == 4 && Use3A2000);
13569 match(Set dst (ReplicateS src));
13570 ins_cost(100);
13571 format %{ "replv_qh AT, $src\n\t"
13572 "dmtc1 AT, $dst\t! replicate4S" %}
13573 ins_encode %{
13574 __ replv_qh(AT, $src$$Register);
13575 __ dmtc1(AT, $dst$$FloatRegister);
13576 %}
13577 ins_pipe( pipe_mtc1 );
13578 %}
13580 instruct Repl4S(vecD dst, mRegI src) %{
13581 predicate(n->as_Vector()->length() == 4);
13582 match(Set dst (ReplicateS src));
13583 ins_cost(120);
13584 format %{ "move AT, $src \n\t"
13585 "dins AT, AT, 16, 16\n\t"
13586 "dinsu AT, AT, 32, 32\n\t"
13587 "dmtc1 AT, $dst\t! replicate4S" %}
13588 ins_encode %{
13589 __ move(AT, $src$$Register);
13590 __ dins(AT, AT, 16, 16);
13591 __ dinsu(AT, AT, 32, 32);
13592 __ dmtc1(AT, $dst$$FloatRegister);
13593 %}
13594 ins_pipe( pipe_mtc1 );
13595 %}
13597 instruct Repl4S_imm_DSP(vecD dst, immI con) %{
13598 predicate(n->as_Vector()->length() == 4 && Use3A2000);
13599 match(Set dst (ReplicateS con));
13600 ins_cost(100);
13601 format %{ "replv_qh AT, [$con]\n\t"
13602 "dmtc1 AT, $dst\t! replicate4S($con)" %}
13603 ins_encode %{
13604 int val = $con$$constant;
13605 if ( Assembler::is_simm(val, 10)) {
13606 //repl_qh supports 10 bits immediate
13607 __ repl_qh(AT, val);
13608 } else {
13609 __ li32(AT, val);
13610 __ replv_qh(AT, AT);
13611 }
13612 __ dmtc1(AT, $dst$$FloatRegister);
13613 %}
13614 ins_pipe( pipe_mtc1 );
13615 %}
13617 instruct Repl4S_imm(vecD dst, immI con) %{
13618 predicate(n->as_Vector()->length() == 4);
13619 match(Set dst (ReplicateS con));
13620 ins_cost(110);
13621 format %{ "move AT, [$con]\n\t"
13622 "dins AT, AT, 16, 16\n\t"
13623 "dinsu AT, AT, 32, 32\n\t"
13624 "dmtc1 AT, $dst\t! replicate4S($con)" %}
13625 ins_encode %{
13626 __ move(AT, $con$$constant);
13627 __ dins(AT, AT, 16, 16);
13628 __ dinsu(AT, AT, 32, 32);
13629 __ dmtc1(AT, $dst$$FloatRegister);
13630 %}
13631 ins_pipe( pipe_mtc1 );
13632 %}
13634 instruct Repl4S_zero(vecD dst, immI0 zero) %{
13635 predicate(n->as_Vector()->length() == 4);
13636 match(Set dst (ReplicateS zero));
13637 format %{ "dmtc1 R0, $dst\t! replicate4S zero" %}
13638 ins_encode %{
13639 __ dmtc1(R0, $dst$$FloatRegister);
13640 %}
13641 ins_pipe( pipe_mtc1 );
13642 %}
13644 instruct Repl4S_M1(vecD dst, immI_M1 M1) %{
13645 predicate(n->as_Vector()->length() == 4);
13646 match(Set dst (ReplicateS M1));
13647 format %{ "dmtc1 -1, $dst\t! replicate4S -1" %}
13648 ins_encode %{
13649 __ nor(AT, R0, R0);
13650 __ dmtc1(AT, $dst$$FloatRegister);
13651 %}
13652 ins_pipe( pipe_mtc1 );
13653 %}
13655 // Replicate integer (4 byte) scalar to be vector
13656 instruct Repl2I(vecD dst, mRegI src) %{
13657 predicate(n->as_Vector()->length() == 2);
13658 match(Set dst (ReplicateI src));
13659 format %{ "dins AT, $src, 0, 32\n\t"
13660 "dinsu AT, $src, 32, 32\n\t"
13661 "dmtc1 AT, $dst\t! replicate2I" %}
13662 ins_encode %{
13663 __ dins(AT, $src$$Register, 0, 32);
13664 __ dinsu(AT, $src$$Register, 32, 32);
13665 __ dmtc1(AT, $dst$$FloatRegister);
13666 %}
13667 ins_pipe( pipe_mtc1 );
13668 %}
13670 // Replicate integer (4 byte) scalar immediate to be vector by loading from const table.
13671 instruct Repl2I_imm(vecD dst, immI con, mA7RegI tmp) %{
13672 predicate(n->as_Vector()->length() == 2);
13673 match(Set dst (ReplicateI con));
13674 effect(KILL tmp);
13675 format %{ "li32 AT, [$con], 32\n\t"
13676 "dinsu AT, AT\n\t"
13677 "dmtc1 AT, $dst\t! replicate2I($con)" %}
13678 ins_encode %{
13679 int val = $con$$constant;
13680 __ li32(AT, val);
13681 __ dinsu(AT, AT, 32, 32);
13682 __ dmtc1(AT, $dst$$FloatRegister);
13683 %}
13684 ins_pipe( pipe_mtc1 );
13685 %}
13687 // Replicate integer (4 byte) scalar zero to be vector
13688 instruct Repl2I_zero(vecD dst, immI0 zero) %{
13689 predicate(n->as_Vector()->length() == 2);
13690 match(Set dst (ReplicateI zero));
13691 format %{ "dmtc1 R0, $dst\t! replicate2I zero" %}
13692 ins_encode %{
13693 __ dmtc1(R0, $dst$$FloatRegister);
13694 %}
13695 ins_pipe( pipe_mtc1 );
13696 %}
13698 // Replicate integer (4 byte) scalar -1 to be vector
13699 instruct Repl2I_M1(vecD dst, immI_M1 M1) %{
13700 predicate(n->as_Vector()->length() == 2);
13701 match(Set dst (ReplicateI M1));
13702 format %{ "dmtc1 -1, $dst\t! replicate2I -1, use AT" %}
13703 ins_encode %{
13704 __ nor(AT, R0, R0);
13705 __ dmtc1(AT, $dst$$FloatRegister);
13706 %}
13707 ins_pipe( pipe_mtc1 );
13708 %}
13710 // Replicate float (4 byte) scalar to be vector
13711 instruct Repl2F(vecD dst, regF src) %{
13712 predicate(n->as_Vector()->length() == 2);
13713 match(Set dst (ReplicateF src));
13714 format %{ "cvt.ps $dst, $src, $src\t! replicate2F" %}
13715 ins_encode %{
13716 __ cvt_ps_s($dst$$FloatRegister, $src$$FloatRegister, $src$$FloatRegister);
13717 %}
13718 ins_pipe( pipe_slow );
13719 %}
13721 // Replicate float (4 byte) scalar zero to be vector
13722 instruct Repl2F_zero(vecD dst, immF0 zero) %{
13723 predicate(n->as_Vector()->length() == 2);
13724 match(Set dst (ReplicateF zero));
13725 format %{ "dmtc1 R0, $dst\t! replicate2F zero" %}
13726 ins_encode %{
13727 __ dmtc1(R0, $dst$$FloatRegister);
13728 %}
13729 ins_pipe( pipe_mtc1 );
13730 %}
13733 // ====================VECTOR ARITHMETIC=======================================
13735 // --------------------------------- ADD --------------------------------------
13737 // Floats vector add
13738 // kernel does not have emulation of PS instructions yet, so PS instructions is disabled.
13739 instruct vadd2F(vecD dst, vecD src) %{
13740 predicate(n->as_Vector()->length() == 2);
13741 match(Set dst (AddVF dst src));
13742 format %{ "add.ps $dst,$src\t! add packed2F" %}
13743 ins_encode %{
13744 __ add_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13745 %}
13746 ins_pipe( pipe_slow );
13747 %}
13749 instruct vadd2F3(vecD dst, vecD src1, vecD src2) %{
13750 predicate(n->as_Vector()->length() == 2);
13751 match(Set dst (AddVF src1 src2));
13752 format %{ "add.ps $dst,$src1,$src2\t! add packed2F" %}
13753 ins_encode %{
13754 __ add_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13755 %}
13756 ins_pipe( fpu_regF_regF );
13757 %}
13759 // --------------------------------- SUB --------------------------------------
13761 // Floats vector sub
13762 instruct vsub2F(vecD dst, vecD src) %{
13763 predicate(n->as_Vector()->length() == 2);
13764 match(Set dst (SubVF dst src));
13765 format %{ "sub.ps $dst,$src\t! sub packed2F" %}
13766 ins_encode %{
13767 __ sub_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13768 %}
13769 ins_pipe( fpu_regF_regF );
13770 %}
13772 // --------------------------------- MUL --------------------------------------
13774 // Floats vector mul
13775 instruct vmul2F(vecD dst, vecD src) %{
13776 predicate(n->as_Vector()->length() == 2);
13777 match(Set dst (MulVF dst src));
13778 format %{ "mul.ps $dst, $src\t! mul packed2F" %}
13779 ins_encode %{
13780 __ mul_ps($dst$$FloatRegister, $dst$$FloatRegister, $src$$FloatRegister);
13781 %}
13782 ins_pipe( fpu_regF_regF );
13783 %}
13785 instruct vmul2F3(vecD dst, vecD src1, vecD src2) %{
13786 predicate(n->as_Vector()->length() == 2);
13787 match(Set dst (MulVF src1 src2));
13788 format %{ "mul.ps $dst, $src1, $src2\t! mul packed2F" %}
13789 ins_encode %{
13790 __ mul_ps($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13791 %}
13792 ins_pipe( fpu_regF_regF );
13793 %}
13795 // --------------------------------- DIV --------------------------------------
13796 // MIPS do not have div.ps
13798 // --------------------------------- MADD --------------------------------------
13799 // Floats vector madd
13800 //instruct vmadd2F(vecD dst, vecD src1, vecD src2, vecD src3) %{
13801 // predicate(n->as_Vector()->length() == 2);
13802 // match(Set dst (AddVF (MulVF src1 src2) src3));
13803 // ins_cost(50);
13804 // format %{ "madd.ps $dst, $src3, $src1, $src2\t! madd packed2F" %}
13805 // ins_encode %{
13806 // __ madd_ps($dst$$FloatRegister, $src3$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
13807 // %}
13808 // ins_pipe( fpu_regF_regF );
13809 //%}
13812 //----------PEEPHOLE RULES-----------------------------------------------------
13813 // These must follow all instruction definitions as they use the names
13814 // defined in the instructions definitions.
13815 //
13816 // peepmatch ( root_instr_name [preceeding_instruction]* );
13817 //
13818 // peepconstraint %{
13819 // (instruction_number.operand_name relational_op instruction_number.operand_name
13820 // [, ...] );
13821 // // instruction numbers are zero-based using left to right order in peepmatch
13822 //
13823 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13824 // // provide an instruction_number.operand_name for each operand that appears
13825 // // in the replacement instruction's match rule
13826 //
13827 // ---------VM FLAGS---------------------------------------------------------
13828 //
13829 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13830 //
13831 // Each peephole rule is given an identifying number starting with zero and
13832 // increasing by one in the order seen by the parser. An individual peephole
13833 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13834 // on the command-line.
13835 //
13836 // ---------CURRENT LIMITATIONS----------------------------------------------
13837 //
13838 // Only match adjacent instructions in same basic block
13839 // Only equality constraints
13840 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13841 // Only one replacement instruction
13842 //
13843 // ---------EXAMPLE----------------------------------------------------------
13844 //
13845 // // pertinent parts of existing instructions in architecture description
13846 // instruct movI(eRegI dst, eRegI src) %{
13847 // match(Set dst (CopyI src));
13848 // %}
13849 //
13850 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13851 // match(Set dst (AddI dst src));
13852 // effect(KILL cr);
13853 // %}
13854 //
13855 // // Change (inc mov) to lea
13856 // peephole %{
13857 // // increment preceeded by register-register move
13858 // peepmatch ( incI_eReg movI );
13859 // // require that the destination register of the increment
13860 // // match the destination register of the move
13861 // peepconstraint ( 0.dst == 1.dst );
13862 // // construct a replacement instruction that sets
13863 // // the destination to ( move's source register + one )
13864 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13865 // %}
13866 //
13867 // Implementation no longer uses movX instructions since
13868 // machine-independent system no longer uses CopyX nodes.
13869 //
13870 // peephole %{
13871 // peepmatch ( incI_eReg movI );
13872 // peepconstraint ( 0.dst == 1.dst );
13873 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13874 // %}
13875 //
13876 // peephole %{
13877 // peepmatch ( decI_eReg movI );
13878 // peepconstraint ( 0.dst == 1.dst );
13879 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13880 // %}
13881 //
13882 // peephole %{
13883 // peepmatch ( addI_eReg_imm movI );
13884 // peepconstraint ( 0.dst == 1.dst );
13885 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13886 // %}
13887 //
13888 // peephole %{
13889 // peepmatch ( addP_eReg_imm movP );
13890 // peepconstraint ( 0.dst == 1.dst );
13891 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13892 // %}
13894 // // Change load of spilled value to only a spill
13895 // instruct storeI(memory mem, eRegI src) %{
13896 // match(Set mem (StoreI mem src));
13897 // %}
13898 //
13899 // instruct loadI(eRegI dst, memory mem) %{
13900 // match(Set dst (LoadI mem));
13901 // %}
13902 //
13903 //peephole %{
13904 // peepmatch ( loadI storeI );
13905 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13906 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13907 //%}
13909 //----------SMARTSPILL RULES---------------------------------------------------
13910 // These must follow all instruction definitions as they use the names
13911 // defined in the instructions definitions.