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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp@a3f7f95b0165
src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
Tue, 05 Oct 2010 11:16:12 -0700
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- Tue, 05 Oct 2010 11:16:12 -0700
- changeset 2185
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6988018: dtrace/hotspot/MethodInvocation/MethodInvocation002 crashes with client compiler
Reviewed-by: iveresov, kvn, kamg
1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_x86.cpp.incl"
29 // These masks are used to provide 128-bit aligned bitmasks to the XMM
30 // instructions, to allow sign-masking or sign-bit flipping. They allow
31 // fast versions of NegF/NegD and AbsF/AbsD.
33 // Note: 'double' and 'long long' have 32-bits alignment on x86.
34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
36 // of 128-bits operands for SSE instructions.
37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF)));
38 // Store the value to a 128-bits operand.
39 operand[0] = lo;
40 operand[1] = hi;
41 return operand;
42 }
44 // Buffer for 128-bits masks used by SSE instructions.
45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
47 // Static initialization during VM startup.
48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register IC_Klass = rax; // where the IC klass is cached
57 const Register SYNC_header = rax; // synchronization header
58 const Register SHIFT_count = rcx; // where count for shift operations must be
60 #define __ _masm->
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
100 if (opr->is_constant()) {
101 LIR_Const* constant = opr->as_constant_ptr();
102 switch (constant->type()) {
103 case T_INT: {
104 return true;
105 }
107 default:
108 return false;
109 }
110 }
111 return false;
112 }
115 LIR_Opr LIR_Assembler::receiverOpr() {
116 return FrameMap::receiver_opr;
117 }
119 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
120 return receiverOpr();
121 }
123 LIR_Opr LIR_Assembler::osrBufferPointer() {
124 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
125 }
127 //--------------fpu register translations-----------------------
130 address LIR_Assembler::float_constant(float f) {
131 address const_addr = __ float_constant(f);
132 if (const_addr == NULL) {
133 bailout("const section overflow");
134 return __ code()->consts()->start();
135 } else {
136 return const_addr;
137 }
138 }
141 address LIR_Assembler::double_constant(double d) {
142 address const_addr = __ double_constant(d);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
152 void LIR_Assembler::set_24bit_FPU() {
153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
154 }
156 void LIR_Assembler::reset_FPU() {
157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
158 }
160 void LIR_Assembler::fpop() {
161 __ fpop();
162 }
164 void LIR_Assembler::fxch(int i) {
165 __ fxch(i);
166 }
168 void LIR_Assembler::fld(int i) {
169 __ fld_s(i);
170 }
172 void LIR_Assembler::ffree(int i) {
173 __ ffree(i);
174 }
176 void LIR_Assembler::breakpoint() {
177 __ int3();
178 }
180 void LIR_Assembler::push(LIR_Opr opr) {
181 if (opr->is_single_cpu()) {
182 __ push_reg(opr->as_register());
183 } else if (opr->is_double_cpu()) {
184 NOT_LP64(__ push_reg(opr->as_register_hi()));
185 __ push_reg(opr->as_register_lo());
186 } else if (opr->is_stack()) {
187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
188 } else if (opr->is_constant()) {
189 LIR_Const* const_opr = opr->as_constant_ptr();
190 if (const_opr->type() == T_OBJECT) {
191 __ push_oop(const_opr->as_jobject());
192 } else if (const_opr->type() == T_INT) {
193 __ push_jint(const_opr->as_jint());
194 } else {
195 ShouldNotReachHere();
196 }
198 } else {
199 ShouldNotReachHere();
200 }
201 }
203 void LIR_Assembler::pop(LIR_Opr opr) {
204 if (opr->is_single_cpu()) {
205 __ pop_reg(opr->as_register());
206 } else {
207 ShouldNotReachHere();
208 }
209 }
211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
212 return addr->base()->is_illegal() && addr->index()->is_illegal();
213 }
215 //-------------------------------------------
217 Address LIR_Assembler::as_Address(LIR_Address* addr) {
218 return as_Address(addr, rscratch1);
219 }
221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
222 if (addr->base()->is_illegal()) {
223 assert(addr->index()->is_illegal(), "must be illegal too");
224 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
225 if (! __ reachable(laddr)) {
226 __ movptr(tmp, laddr.addr());
227 Address res(tmp, 0);
228 return res;
229 } else {
230 return __ as_Address(laddr);
231 }
232 }
234 Register base = addr->base()->as_pointer_register();
236 if (addr->index()->is_illegal()) {
237 return Address( base, addr->disp());
238 } else if (addr->index()->is_cpu_register()) {
239 Register index = addr->index()->as_pointer_register();
240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
241 } else if (addr->index()->is_constant()) {
242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
243 assert(Assembler::is_simm32(addr_offset), "must be");
245 return Address(base, addr_offset);
246 } else {
247 Unimplemented();
248 return Address();
249 }
250 }
253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
254 Address base = as_Address(addr);
255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
256 }
259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
260 return as_Address(addr);
261 }
264 void LIR_Assembler::osr_entry() {
265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
266 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
267 ValueStack* entry_state = osr_entry->state();
268 int number_of_locks = entry_state->locks_size();
270 // we jump here if osr happens with the interpreter
271 // state set up to continue at the beginning of the
272 // loop that triggered osr - in particular, we have
273 // the following registers setup:
274 //
275 // rcx: osr buffer
276 //
278 // build frame
279 ciMethod* m = compilation()->method();
280 __ build_frame(initial_frame_size_in_bytes());
282 // OSR buffer is
283 //
284 // locals[nlocals-1..0]
285 // monitors[0..number_of_locks]
286 //
287 // locals is a direct copy of the interpreter frame so in the osr buffer
288 // so first slot in the local array is the last local from the interpreter
289 // and last slot is local[0] (receiver) from the interpreter
290 //
291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
293 // in the interpreter frame (the method lock if a sync method)
295 // Initialize monitors in the compiled activation.
296 // rcx: pointer to osr buffer
297 //
298 // All other registers are dead at this point and the locals will be
299 // copied into place by code emitted in the IR.
301 Register OSR_buf = osrBufferPointer()->as_pointer_register();
302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
303 int monitor_offset = BytesPerWord * method()->max_locals() +
304 (2 * BytesPerWord) * (number_of_locks - 1);
305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
306 // the OSR buffer using 2 word entries: first the lock and then
307 // the oop.
308 for (int i = 0; i < number_of_locks; i++) {
309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
310 #ifdef ASSERT
311 // verify the interpreter's monitor has a non-null object
312 {
313 Label L;
314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
315 __ jcc(Assembler::notZero, L);
316 __ stop("locked object is NULL");
317 __ bind(L);
318 }
319 #endif
320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
323 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
324 }
325 }
326 }
329 // inline cache check; done before the frame is built.
330 int LIR_Assembler::check_icache() {
331 Register receiver = FrameMap::receiver_opr->as_register();
332 Register ic_klass = IC_Klass;
333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
335 if (!VerifyOops) {
336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
338 __ nop();
339 }
340 }
341 int offset = __ offset();
342 __ inline_cache_check(receiver, IC_Klass);
343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct");
344 if (VerifyOops) {
345 // force alignment after the cache check.
346 // It's been verified to be aligned if !VerifyOops
347 __ align(CodeEntryAlignment);
348 }
349 return offset;
350 }
353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
354 jobject o = NULL;
355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
356 __ movoop(reg, o);
357 patching_epilog(patch, lir_patch_normal, reg, info);
358 }
361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) {
362 if (exception->is_valid()) {
363 // preserve exception
364 // note: the monitor_exit runtime call is a leaf routine
365 // and cannot block => no GC can happen
366 // The slow case (MonitorAccessStub) uses the first two stack slots
367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8]
368 __ movptr (Address(rsp, 2*wordSize), exception);
369 }
371 Register obj_reg = obj_opr->as_register();
372 Register lock_reg = lock_opr->as_register();
374 // setup registers (lock_reg must be rax, for lock_object)
375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here");
376 Register hdr = lock_reg;
377 assert(new_hdr == SYNC_header, "wrong register");
378 lock_reg = new_hdr;
379 // compute pointer to BasicLock
380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no);
381 __ lea(lock_reg, lock_addr);
382 // unlock object
383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no);
384 // _slow_case_stubs->append(slow_case);
385 // temporary fix: must be created after exceptionhandler, therefore as call stub
386 _slow_case_stubs->append(slow_case);
387 if (UseFastLocking) {
388 // try inlined fast unlocking first, revert to slow locking if it fails
389 // note: lock_reg points to the displaced header since the displaced header offset is 0!
390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
392 } else {
393 // always do slow unlocking
394 // note: the slow unlocking code could be inlined here, however if we use
395 // slow unlocking, speed doesn't matter anyway and this solution is
396 // simpler and requires less duplicated code - additionally, the
397 // slow unlocking code is the same in either case which simplifies
398 // debugging
399 __ jmp(*slow_case->entry());
400 }
401 // done
402 __ bind(*slow_case->continuation());
404 if (exception->is_valid()) {
405 // restore exception
406 __ movptr (exception, Address(rsp, 2 * wordSize));
407 }
408 }
410 // This specifies the rsp decrement needed to build the frame
411 int LIR_Assembler::initial_frame_size_in_bytes() {
412 // if rounding, must let FrameMap know!
414 // The frame_map records size in slots (32bit word)
416 // subtract two words to account for return address and link
417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
418 }
421 int LIR_Assembler::emit_exception_handler() {
422 // if the last instruction is a call (typically to do a throw which
423 // is coming at the end after block reordering) the return address
424 // must still point into the code area in order to avoid assertion
425 // failures when searching for the corresponding bci => add a nop
426 // (was bug 5/14/1999 - gri)
427 __ nop();
429 // generate code for exception handler
430 address handler_base = __ start_a_stub(exception_handler_size);
431 if (handler_base == NULL) {
432 // not enough space left for the handler
433 bailout("exception handler overflow");
434 return -1;
435 }
437 int offset = code_offset();
439 // the exception oop and pc are in rax, and rdx
440 // no other registers need to be preserved, so invalidate them
441 __ invalidate_registers(false, true, true, false, true, true);
443 // check that there is really an exception
444 __ verify_not_null_oop(rax);
446 // search an exception handler (rax: exception oop, rdx: throwing pc)
447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id)));
449 __ stop("should not reach here");
451 assert(code_offset() - offset <= exception_handler_size, "overflow");
452 __ end_a_stub();
454 return offset;
455 }
458 // Emit the code to remove the frame from the stack in the exception
459 // unwind path.
460 int LIR_Assembler::emit_unwind_handler() {
461 #ifndef PRODUCT
462 if (CommentedAssembly) {
463 _masm->block_comment("Unwind handler");
464 }
465 #endif
467 int offset = code_offset();
469 // Fetch the exception from TLS and clear out exception related thread state
470 __ get_thread(rsi);
471 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
472 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
473 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
475 __ bind(_unwind_handler_entry);
476 __ verify_not_null_oop(rax);
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
478 __ mov(rsi, rax); // Preserve the exception
479 }
481 // Preform needed unlocking
482 MonitorExitStub* stub = NULL;
483 if (method()->is_synchronized()) {
484 monitor_address(0, FrameMap::rax_opr);
485 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
486 __ unlock_object(rdi, rbx, rax, *stub->entry());
487 __ bind(*stub->continuation());
488 }
490 if (compilation()->env()->dtrace_method_probes()) {
491 __ get_thread(rax);
492 __ movptr(Address(rsp, 0), rax);
493 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding());
494 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
495 }
497 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
498 __ mov(rax, rsi); // Restore the exception
499 }
501 // remove the activation and dispatch to the unwind handler
502 __ remove_frame(initial_frame_size_in_bytes());
503 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
505 // Emit the slow path assembly
506 if (stub != NULL) {
507 stub->emit_code(this);
508 }
510 return offset;
511 }
514 int LIR_Assembler::emit_deopt_handler() {
515 // if the last instruction is a call (typically to do a throw which
516 // is coming at the end after block reordering) the return address
517 // must still point into the code area in order to avoid assertion
518 // failures when searching for the corresponding bci => add a nop
519 // (was bug 5/14/1999 - gri)
520 __ nop();
522 // generate code for exception handler
523 address handler_base = __ start_a_stub(deopt_handler_size);
524 if (handler_base == NULL) {
525 // not enough space left for the handler
526 bailout("deopt handler overflow");
527 return -1;
528 }
530 int offset = code_offset();
531 InternalAddress here(__ pc());
533 __ pushptr(here.addr());
534 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
536 assert(code_offset() - offset <= deopt_handler_size, "overflow");
537 __ end_a_stub();
539 return offset;
540 }
543 // This is the fast version of java.lang.String.compare; it has not
544 // OSR-entry and therefore, we generate a slow version for OSR's
545 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
546 __ movptr (rbx, rcx); // receiver is in rcx
547 __ movptr (rax, arg1->as_register());
549 // Get addresses of first characters from both Strings
550 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
551 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
552 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
555 // rbx, may be NULL
556 add_debug_info_for_null_check_here(info);
557 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
558 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
559 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
561 // compute minimum length (in rax) and difference of lengths (on top of stack)
562 if (VM_Version::supports_cmov()) {
563 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
564 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
565 __ mov (rcx, rbx);
566 __ subptr (rbx, rax); // subtract lengths
567 __ push (rbx); // result
568 __ cmov (Assembler::lessEqual, rax, rcx);
569 } else {
570 Label L;
571 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
572 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes()));
573 __ mov (rax, rbx);
574 __ subptr (rbx, rcx);
575 __ push (rbx);
576 __ jcc (Assembler::lessEqual, L);
577 __ mov (rax, rcx);
578 __ bind (L);
579 }
580 // is minimum length 0?
581 Label noLoop, haveResult;
582 __ testptr (rax, rax);
583 __ jcc (Assembler::zero, noLoop);
585 // compare first characters
586 __ load_unsigned_short(rcx, Address(rdi, 0));
587 __ load_unsigned_short(rbx, Address(rsi, 0));
588 __ subl(rcx, rbx);
589 __ jcc(Assembler::notZero, haveResult);
590 // starting loop
591 __ decrement(rax); // we already tested index: skip one
592 __ jcc(Assembler::zero, noLoop);
594 // set rsi.edi to the end of the arrays (arrays have same length)
595 // negate the index
597 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
598 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
599 __ negptr(rax);
601 // compare the strings in a loop
603 Label loop;
604 __ align(wordSize);
605 __ bind(loop);
606 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
607 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
608 __ subl(rcx, rbx);
609 __ jcc(Assembler::notZero, haveResult);
610 __ increment(rax);
611 __ jcc(Assembler::notZero, loop);
613 // strings are equal up to min length
615 __ bind(noLoop);
616 __ pop(rax);
617 return_op(LIR_OprFact::illegalOpr);
619 __ bind(haveResult);
620 // leave instruction is going to discard the TOS value
621 __ mov (rax, rcx); // result of call is in rax,
622 }
625 void LIR_Assembler::return_op(LIR_Opr result) {
626 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
627 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
628 assert(result->fpu() == 0, "result must already be on TOS");
629 }
631 // Pop the stack before the safepoint code
632 __ remove_frame(initial_frame_size_in_bytes());
634 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
636 // Note: we do not need to round double result; float result has the right precision
637 // the poll sets the condition code, but no data registers
638 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
639 relocInfo::poll_return_type);
641 // NOTE: the requires that the polling page be reachable else the reloc
642 // goes to the movq that loads the address and not the faulting instruction
643 // which breaks the signal handler code
645 __ test32(rax, polling_page);
647 __ ret(0);
648 }
651 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
652 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
653 relocInfo::poll_type);
655 if (info != NULL) {
656 add_debug_info_for_branch(info);
657 } else {
658 ShouldNotReachHere();
659 }
661 int offset = __ offset();
663 // NOTE: the requires that the polling page be reachable else the reloc
664 // goes to the movq that loads the address and not the faulting instruction
665 // which breaks the signal handler code
667 __ test32(rax, polling_page);
668 return offset;
669 }
672 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
673 if (from_reg != to_reg) __ mov(to_reg, from_reg);
674 }
676 void LIR_Assembler::swap_reg(Register a, Register b) {
677 __ xchgptr(a, b);
678 }
681 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
682 assert(src->is_constant(), "should not call otherwise");
683 assert(dest->is_register(), "should not call otherwise");
684 LIR_Const* c = src->as_constant_ptr();
686 switch (c->type()) {
687 case T_INT:
688 case T_ADDRESS: {
689 assert(patch_code == lir_patch_none, "no patching handled here");
690 __ movl(dest->as_register(), c->as_jint());
691 break;
692 }
694 case T_LONG: {
695 assert(patch_code == lir_patch_none, "no patching handled here");
696 #ifdef _LP64
697 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
698 #else
699 __ movptr(dest->as_register_lo(), c->as_jint_lo());
700 __ movptr(dest->as_register_hi(), c->as_jint_hi());
701 #endif // _LP64
702 break;
703 }
705 case T_OBJECT: {
706 if (patch_code != lir_patch_none) {
707 jobject2reg_with_patching(dest->as_register(), info);
708 } else {
709 __ movoop(dest->as_register(), c->as_jobject());
710 }
711 break;
712 }
714 case T_FLOAT: {
715 if (dest->is_single_xmm()) {
716 if (c->is_zero_float()) {
717 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
718 } else {
719 __ movflt(dest->as_xmm_float_reg(),
720 InternalAddress(float_constant(c->as_jfloat())));
721 }
722 } else {
723 assert(dest->is_single_fpu(), "must be");
724 assert(dest->fpu_regnr() == 0, "dest must be TOS");
725 if (c->is_zero_float()) {
726 __ fldz();
727 } else if (c->is_one_float()) {
728 __ fld1();
729 } else {
730 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
731 }
732 }
733 break;
734 }
736 case T_DOUBLE: {
737 if (dest->is_double_xmm()) {
738 if (c->is_zero_double()) {
739 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
740 } else {
741 __ movdbl(dest->as_xmm_double_reg(),
742 InternalAddress(double_constant(c->as_jdouble())));
743 }
744 } else {
745 assert(dest->is_double_fpu(), "must be");
746 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
747 if (c->is_zero_double()) {
748 __ fldz();
749 } else if (c->is_one_double()) {
750 __ fld1();
751 } else {
752 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
753 }
754 }
755 break;
756 }
758 default:
759 ShouldNotReachHere();
760 }
761 }
763 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
764 assert(src->is_constant(), "should not call otherwise");
765 assert(dest->is_stack(), "should not call otherwise");
766 LIR_Const* c = src->as_constant_ptr();
768 switch (c->type()) {
769 case T_INT: // fall through
770 case T_FLOAT:
771 case T_ADDRESS:
772 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
773 break;
775 case T_OBJECT:
776 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
777 break;
779 case T_LONG: // fall through
780 case T_DOUBLE:
781 #ifdef _LP64
782 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
783 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
784 #else
785 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
786 lo_word_offset_in_bytes), c->as_jint_lo_bits());
787 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
788 hi_word_offset_in_bytes), c->as_jint_hi_bits());
789 #endif // _LP64
790 break;
792 default:
793 ShouldNotReachHere();
794 }
795 }
797 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
798 assert(src->is_constant(), "should not call otherwise");
799 assert(dest->is_address(), "should not call otherwise");
800 LIR_Const* c = src->as_constant_ptr();
801 LIR_Address* addr = dest->as_address_ptr();
803 int null_check_here = code_offset();
804 switch (type) {
805 case T_INT: // fall through
806 case T_FLOAT:
807 case T_ADDRESS:
808 __ movl(as_Address(addr), c->as_jint_bits());
809 break;
811 case T_OBJECT: // fall through
812 case T_ARRAY:
813 if (c->as_jobject() == NULL) {
814 __ movptr(as_Address(addr), NULL_WORD);
815 } else {
816 if (is_literal_address(addr)) {
817 ShouldNotReachHere();
818 __ movoop(as_Address(addr, noreg), c->as_jobject());
819 } else {
820 #ifdef _LP64
821 __ movoop(rscratch1, c->as_jobject());
822 null_check_here = code_offset();
823 __ movptr(as_Address_lo(addr), rscratch1);
824 #else
825 __ movoop(as_Address(addr), c->as_jobject());
826 #endif
827 }
828 }
829 break;
831 case T_LONG: // fall through
832 case T_DOUBLE:
833 #ifdef _LP64
834 if (is_literal_address(addr)) {
835 ShouldNotReachHere();
836 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
837 } else {
838 __ movptr(r10, (intptr_t)c->as_jlong_bits());
839 null_check_here = code_offset();
840 __ movptr(as_Address_lo(addr), r10);
841 }
842 #else
843 // Always reachable in 32bit so this doesn't produce useless move literal
844 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
845 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
846 #endif // _LP64
847 break;
849 case T_BOOLEAN: // fall through
850 case T_BYTE:
851 __ movb(as_Address(addr), c->as_jint() & 0xFF);
852 break;
854 case T_CHAR: // fall through
855 case T_SHORT:
856 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
857 break;
859 default:
860 ShouldNotReachHere();
861 };
863 if (info != NULL) {
864 add_debug_info_for_null_check(null_check_here, info);
865 }
866 }
869 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
870 assert(src->is_register(), "should not call otherwise");
871 assert(dest->is_register(), "should not call otherwise");
873 // move between cpu-registers
874 if (dest->is_single_cpu()) {
875 #ifdef _LP64
876 if (src->type() == T_LONG) {
877 // Can do LONG -> OBJECT
878 move_regs(src->as_register_lo(), dest->as_register());
879 return;
880 }
881 #endif
882 assert(src->is_single_cpu(), "must match");
883 if (src->type() == T_OBJECT) {
884 __ verify_oop(src->as_register());
885 }
886 move_regs(src->as_register(), dest->as_register());
888 } else if (dest->is_double_cpu()) {
889 #ifdef _LP64
890 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
891 // Surprising to me but we can see move of a long to t_object
892 __ verify_oop(src->as_register());
893 move_regs(src->as_register(), dest->as_register_lo());
894 return;
895 }
896 #endif
897 assert(src->is_double_cpu(), "must match");
898 Register f_lo = src->as_register_lo();
899 Register f_hi = src->as_register_hi();
900 Register t_lo = dest->as_register_lo();
901 Register t_hi = dest->as_register_hi();
902 #ifdef _LP64
903 assert(f_hi == f_lo, "must be same");
904 assert(t_hi == t_lo, "must be same");
905 move_regs(f_lo, t_lo);
906 #else
907 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
910 if (f_lo == t_hi && f_hi == t_lo) {
911 swap_reg(f_lo, f_hi);
912 } else if (f_hi == t_lo) {
913 assert(f_lo != t_hi, "overwriting register");
914 move_regs(f_hi, t_hi);
915 move_regs(f_lo, t_lo);
916 } else {
917 assert(f_hi != t_lo, "overwriting register");
918 move_regs(f_lo, t_lo);
919 move_regs(f_hi, t_hi);
920 }
921 #endif // LP64
923 // special moves from fpu-register to xmm-register
924 // necessary for method results
925 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
926 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
927 __ fld_s(Address(rsp, 0));
928 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
929 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
930 __ fld_d(Address(rsp, 0));
931 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
932 __ fstp_s(Address(rsp, 0));
933 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
934 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
935 __ fstp_d(Address(rsp, 0));
936 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
938 // move between xmm-registers
939 } else if (dest->is_single_xmm()) {
940 assert(src->is_single_xmm(), "must match");
941 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
942 } else if (dest->is_double_xmm()) {
943 assert(src->is_double_xmm(), "must match");
944 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
946 // move between fpu-registers (no instruction necessary because of fpu-stack)
947 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
948 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
949 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
950 } else {
951 ShouldNotReachHere();
952 }
953 }
955 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
956 assert(src->is_register(), "should not call otherwise");
957 assert(dest->is_stack(), "should not call otherwise");
959 if (src->is_single_cpu()) {
960 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
961 if (type == T_OBJECT || type == T_ARRAY) {
962 __ verify_oop(src->as_register());
963 __ movptr (dst, src->as_register());
964 } else {
965 __ movl (dst, src->as_register());
966 }
968 } else if (src->is_double_cpu()) {
969 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
970 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
971 __ movptr (dstLO, src->as_register_lo());
972 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
974 } else if (src->is_single_xmm()) {
975 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
976 __ movflt(dst_addr, src->as_xmm_float_reg());
978 } else if (src->is_double_xmm()) {
979 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
980 __ movdbl(dst_addr, src->as_xmm_double_reg());
982 } else if (src->is_single_fpu()) {
983 assert(src->fpu_regnr() == 0, "argument must be on TOS");
984 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
985 if (pop_fpu_stack) __ fstp_s (dst_addr);
986 else __ fst_s (dst_addr);
988 } else if (src->is_double_fpu()) {
989 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
990 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
991 if (pop_fpu_stack) __ fstp_d (dst_addr);
992 else __ fst_d (dst_addr);
994 } else {
995 ShouldNotReachHere();
996 }
997 }
1000 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) {
1001 LIR_Address* to_addr = dest->as_address_ptr();
1002 PatchingStub* patch = NULL;
1004 if (type == T_ARRAY || type == T_OBJECT) {
1005 __ verify_oop(src->as_register());
1006 }
1007 if (patch_code != lir_patch_none) {
1008 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1009 Address toa = as_Address(to_addr);
1010 assert(toa.disp() != 0, "must have");
1011 }
1012 if (info != NULL) {
1013 add_debug_info_for_null_check_here(info);
1014 }
1016 switch (type) {
1017 case T_FLOAT: {
1018 if (src->is_single_xmm()) {
1019 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1020 } else {
1021 assert(src->is_single_fpu(), "must be");
1022 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1023 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1024 else __ fst_s (as_Address(to_addr));
1025 }
1026 break;
1027 }
1029 case T_DOUBLE: {
1030 if (src->is_double_xmm()) {
1031 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1032 } else {
1033 assert(src->is_double_fpu(), "must be");
1034 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1035 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1036 else __ fst_d (as_Address(to_addr));
1037 }
1038 break;
1039 }
1041 case T_ADDRESS: // fall through
1042 case T_ARRAY: // fall through
1043 case T_OBJECT: // fall through
1044 #ifdef _LP64
1045 __ movptr(as_Address(to_addr), src->as_register());
1046 break;
1047 #endif // _LP64
1048 case T_INT:
1049 __ movl(as_Address(to_addr), src->as_register());
1050 break;
1052 case T_LONG: {
1053 Register from_lo = src->as_register_lo();
1054 Register from_hi = src->as_register_hi();
1055 #ifdef _LP64
1056 __ movptr(as_Address_lo(to_addr), from_lo);
1057 #else
1058 Register base = to_addr->base()->as_register();
1059 Register index = noreg;
1060 if (to_addr->index()->is_register()) {
1061 index = to_addr->index()->as_register();
1062 }
1063 if (base == from_lo || index == from_lo) {
1064 assert(base != from_hi, "can't be");
1065 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1066 __ movl(as_Address_hi(to_addr), from_hi);
1067 if (patch != NULL) {
1068 patching_epilog(patch, lir_patch_high, base, info);
1069 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1070 patch_code = lir_patch_low;
1071 }
1072 __ movl(as_Address_lo(to_addr), from_lo);
1073 } else {
1074 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1075 __ movl(as_Address_lo(to_addr), from_lo);
1076 if (patch != NULL) {
1077 patching_epilog(patch, lir_patch_low, base, info);
1078 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1079 patch_code = lir_patch_high;
1080 }
1081 __ movl(as_Address_hi(to_addr), from_hi);
1082 }
1083 #endif // _LP64
1084 break;
1085 }
1087 case T_BYTE: // fall through
1088 case T_BOOLEAN: {
1089 Register src_reg = src->as_register();
1090 Address dst_addr = as_Address(to_addr);
1091 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1092 __ movb(dst_addr, src_reg);
1093 break;
1094 }
1096 case T_CHAR: // fall through
1097 case T_SHORT:
1098 __ movw(as_Address(to_addr), src->as_register());
1099 break;
1101 default:
1102 ShouldNotReachHere();
1103 }
1105 if (patch_code != lir_patch_none) {
1106 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1107 }
1108 }
1111 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1112 assert(src->is_stack(), "should not call otherwise");
1113 assert(dest->is_register(), "should not call otherwise");
1115 if (dest->is_single_cpu()) {
1116 if (type == T_ARRAY || type == T_OBJECT) {
1117 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1118 __ verify_oop(dest->as_register());
1119 } else {
1120 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1121 }
1123 } else if (dest->is_double_cpu()) {
1124 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1125 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1126 __ movptr(dest->as_register_lo(), src_addr_LO);
1127 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1129 } else if (dest->is_single_xmm()) {
1130 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1131 __ movflt(dest->as_xmm_float_reg(), src_addr);
1133 } else if (dest->is_double_xmm()) {
1134 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1135 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1137 } else if (dest->is_single_fpu()) {
1138 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1139 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1140 __ fld_s(src_addr);
1142 } else if (dest->is_double_fpu()) {
1143 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1144 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1145 __ fld_d(src_addr);
1147 } else {
1148 ShouldNotReachHere();
1149 }
1150 }
1153 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1154 if (src->is_single_stack()) {
1155 if (type == T_OBJECT || type == T_ARRAY) {
1156 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1157 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1158 } else {
1159 #ifndef _LP64
1160 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1161 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1162 #else
1163 //no pushl on 64bits
1164 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1165 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1166 #endif
1167 }
1169 } else if (src->is_double_stack()) {
1170 #ifdef _LP64
1171 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1172 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1173 #else
1174 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1175 // push and pop the part at src + wordSize, adding wordSize for the previous push
1176 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1177 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1178 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1179 #endif // _LP64
1181 } else {
1182 ShouldNotReachHere();
1183 }
1184 }
1187 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) {
1188 assert(src->is_address(), "should not call otherwise");
1189 assert(dest->is_register(), "should not call otherwise");
1191 LIR_Address* addr = src->as_address_ptr();
1192 Address from_addr = as_Address(addr);
1194 switch (type) {
1195 case T_BOOLEAN: // fall through
1196 case T_BYTE: // fall through
1197 case T_CHAR: // fall through
1198 case T_SHORT:
1199 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1200 // on pre P6 processors we may get partial register stalls
1201 // so blow away the value of to_rinfo before loading a
1202 // partial word into it. Do it here so that it precedes
1203 // the potential patch point below.
1204 __ xorptr(dest->as_register(), dest->as_register());
1205 }
1206 break;
1207 }
1209 PatchingStub* patch = NULL;
1210 if (patch_code != lir_patch_none) {
1211 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1212 assert(from_addr.disp() != 0, "must have");
1213 }
1214 if (info != NULL) {
1215 add_debug_info_for_null_check_here(info);
1216 }
1218 switch (type) {
1219 case T_FLOAT: {
1220 if (dest->is_single_xmm()) {
1221 __ movflt(dest->as_xmm_float_reg(), from_addr);
1222 } else {
1223 assert(dest->is_single_fpu(), "must be");
1224 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1225 __ fld_s(from_addr);
1226 }
1227 break;
1228 }
1230 case T_DOUBLE: {
1231 if (dest->is_double_xmm()) {
1232 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1233 } else {
1234 assert(dest->is_double_fpu(), "must be");
1235 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1236 __ fld_d(from_addr);
1237 }
1238 break;
1239 }
1241 case T_ADDRESS: // fall through
1242 case T_OBJECT: // fall through
1243 case T_ARRAY: // fall through
1244 #ifdef _LP64
1245 __ movptr(dest->as_register(), from_addr);
1246 break;
1247 #endif // _L64
1248 case T_INT:
1249 __ movl(dest->as_register(), from_addr);
1250 break;
1252 case T_LONG: {
1253 Register to_lo = dest->as_register_lo();
1254 Register to_hi = dest->as_register_hi();
1255 #ifdef _LP64
1256 __ movptr(to_lo, as_Address_lo(addr));
1257 #else
1258 Register base = addr->base()->as_register();
1259 Register index = noreg;
1260 if (addr->index()->is_register()) {
1261 index = addr->index()->as_register();
1262 }
1263 if ((base == to_lo && index == to_hi) ||
1264 (base == to_hi && index == to_lo)) {
1265 // addresses with 2 registers are only formed as a result of
1266 // array access so this code will never have to deal with
1267 // patches or null checks.
1268 assert(info == NULL && patch == NULL, "must be");
1269 __ lea(to_hi, as_Address(addr));
1270 __ movl(to_lo, Address(to_hi, 0));
1271 __ movl(to_hi, Address(to_hi, BytesPerWord));
1272 } else if (base == to_lo || index == to_lo) {
1273 assert(base != to_hi, "can't be");
1274 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1275 __ movl(to_hi, as_Address_hi(addr));
1276 if (patch != NULL) {
1277 patching_epilog(patch, lir_patch_high, base, info);
1278 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1279 patch_code = lir_patch_low;
1280 }
1281 __ movl(to_lo, as_Address_lo(addr));
1282 } else {
1283 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1284 __ movl(to_lo, as_Address_lo(addr));
1285 if (patch != NULL) {
1286 patching_epilog(patch, lir_patch_low, base, info);
1287 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1288 patch_code = lir_patch_high;
1289 }
1290 __ movl(to_hi, as_Address_hi(addr));
1291 }
1292 #endif // _LP64
1293 break;
1294 }
1296 case T_BOOLEAN: // fall through
1297 case T_BYTE: {
1298 Register dest_reg = dest->as_register();
1299 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1300 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1301 __ movsbl(dest_reg, from_addr);
1302 } else {
1303 __ movb(dest_reg, from_addr);
1304 __ shll(dest_reg, 24);
1305 __ sarl(dest_reg, 24);
1306 }
1307 break;
1308 }
1310 case T_CHAR: {
1311 Register dest_reg = dest->as_register();
1312 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1313 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1314 __ movzwl(dest_reg, from_addr);
1315 } else {
1316 __ movw(dest_reg, from_addr);
1317 }
1318 break;
1319 }
1321 case T_SHORT: {
1322 Register dest_reg = dest->as_register();
1323 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1324 __ movswl(dest_reg, from_addr);
1325 } else {
1326 __ movw(dest_reg, from_addr);
1327 __ shll(dest_reg, 16);
1328 __ sarl(dest_reg, 16);
1329 }
1330 break;
1331 }
1333 default:
1334 ShouldNotReachHere();
1335 }
1337 if (patch != NULL) {
1338 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1339 }
1341 if (type == T_ARRAY || type == T_OBJECT) {
1342 __ verify_oop(dest->as_register());
1343 }
1344 }
1347 void LIR_Assembler::prefetchr(LIR_Opr src) {
1348 LIR_Address* addr = src->as_address_ptr();
1349 Address from_addr = as_Address(addr);
1351 if (VM_Version::supports_sse()) {
1352 switch (ReadPrefetchInstr) {
1353 case 0:
1354 __ prefetchnta(from_addr); break;
1355 case 1:
1356 __ prefetcht0(from_addr); break;
1357 case 2:
1358 __ prefetcht2(from_addr); break;
1359 default:
1360 ShouldNotReachHere(); break;
1361 }
1362 } else if (VM_Version::supports_3dnow()) {
1363 __ prefetchr(from_addr);
1364 }
1365 }
1368 void LIR_Assembler::prefetchw(LIR_Opr src) {
1369 LIR_Address* addr = src->as_address_ptr();
1370 Address from_addr = as_Address(addr);
1372 if (VM_Version::supports_sse()) {
1373 switch (AllocatePrefetchInstr) {
1374 case 0:
1375 __ prefetchnta(from_addr); break;
1376 case 1:
1377 __ prefetcht0(from_addr); break;
1378 case 2:
1379 __ prefetcht2(from_addr); break;
1380 case 3:
1381 __ prefetchw(from_addr); break;
1382 default:
1383 ShouldNotReachHere(); break;
1384 }
1385 } else if (VM_Version::supports_3dnow()) {
1386 __ prefetchw(from_addr);
1387 }
1388 }
1391 NEEDS_CLEANUP; // This could be static?
1392 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1393 int elem_size = type2aelembytes(type);
1394 switch (elem_size) {
1395 case 1: return Address::times_1;
1396 case 2: return Address::times_2;
1397 case 4: return Address::times_4;
1398 case 8: return Address::times_8;
1399 }
1400 ShouldNotReachHere();
1401 return Address::no_scale;
1402 }
1405 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1406 switch (op->code()) {
1407 case lir_idiv:
1408 case lir_irem:
1409 arithmetic_idiv(op->code(),
1410 op->in_opr1(),
1411 op->in_opr2(),
1412 op->in_opr3(),
1413 op->result_opr(),
1414 op->info());
1415 break;
1416 default: ShouldNotReachHere(); break;
1417 }
1418 }
1420 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1421 #ifdef ASSERT
1422 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1423 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1424 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1425 #endif
1427 if (op->cond() == lir_cond_always) {
1428 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1429 __ jmp (*(op->label()));
1430 } else {
1431 Assembler::Condition acond = Assembler::zero;
1432 if (op->code() == lir_cond_float_branch) {
1433 assert(op->ublock() != NULL, "must have unordered successor");
1434 __ jcc(Assembler::parity, *(op->ublock()->label()));
1435 switch(op->cond()) {
1436 case lir_cond_equal: acond = Assembler::equal; break;
1437 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1438 case lir_cond_less: acond = Assembler::below; break;
1439 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1440 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1441 case lir_cond_greater: acond = Assembler::above; break;
1442 default: ShouldNotReachHere();
1443 }
1444 } else {
1445 switch (op->cond()) {
1446 case lir_cond_equal: acond = Assembler::equal; break;
1447 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1448 case lir_cond_less: acond = Assembler::less; break;
1449 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1450 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1451 case lir_cond_greater: acond = Assembler::greater; break;
1452 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1453 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1454 default: ShouldNotReachHere();
1455 }
1456 }
1457 __ jcc(acond,*(op->label()));
1458 }
1459 }
1461 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1462 LIR_Opr src = op->in_opr();
1463 LIR_Opr dest = op->result_opr();
1465 switch (op->bytecode()) {
1466 case Bytecodes::_i2l:
1467 #ifdef _LP64
1468 __ movl2ptr(dest->as_register_lo(), src->as_register());
1469 #else
1470 move_regs(src->as_register(), dest->as_register_lo());
1471 move_regs(src->as_register(), dest->as_register_hi());
1472 __ sarl(dest->as_register_hi(), 31);
1473 #endif // LP64
1474 break;
1476 case Bytecodes::_l2i:
1477 move_regs(src->as_register_lo(), dest->as_register());
1478 break;
1480 case Bytecodes::_i2b:
1481 move_regs(src->as_register(), dest->as_register());
1482 __ sign_extend_byte(dest->as_register());
1483 break;
1485 case Bytecodes::_i2c:
1486 move_regs(src->as_register(), dest->as_register());
1487 __ andl(dest->as_register(), 0xFFFF);
1488 break;
1490 case Bytecodes::_i2s:
1491 move_regs(src->as_register(), dest->as_register());
1492 __ sign_extend_short(dest->as_register());
1493 break;
1496 case Bytecodes::_f2d:
1497 case Bytecodes::_d2f:
1498 if (dest->is_single_xmm()) {
1499 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1500 } else if (dest->is_double_xmm()) {
1501 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1502 } else {
1503 assert(src->fpu() == dest->fpu(), "register must be equal");
1504 // do nothing (float result is rounded later through spilling)
1505 }
1506 break;
1508 case Bytecodes::_i2f:
1509 case Bytecodes::_i2d:
1510 if (dest->is_single_xmm()) {
1511 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1512 } else if (dest->is_double_xmm()) {
1513 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1514 } else {
1515 assert(dest->fpu() == 0, "result must be on TOS");
1516 __ movl(Address(rsp, 0), src->as_register());
1517 __ fild_s(Address(rsp, 0));
1518 }
1519 break;
1521 case Bytecodes::_f2i:
1522 case Bytecodes::_d2i:
1523 if (src->is_single_xmm()) {
1524 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1525 } else if (src->is_double_xmm()) {
1526 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1527 } else {
1528 assert(src->fpu() == 0, "input must be on TOS");
1529 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1530 __ fist_s(Address(rsp, 0));
1531 __ movl(dest->as_register(), Address(rsp, 0));
1532 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1533 }
1535 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1536 assert(op->stub() != NULL, "stub required");
1537 __ cmpl(dest->as_register(), 0x80000000);
1538 __ jcc(Assembler::equal, *op->stub()->entry());
1539 __ bind(*op->stub()->continuation());
1540 break;
1542 case Bytecodes::_l2f:
1543 case Bytecodes::_l2d:
1544 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1545 assert(dest->fpu() == 0, "result must be on TOS");
1547 __ movptr(Address(rsp, 0), src->as_register_lo());
1548 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1549 __ fild_d(Address(rsp, 0));
1550 // float result is rounded later through spilling
1551 break;
1553 case Bytecodes::_f2l:
1554 case Bytecodes::_d2l:
1555 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1556 assert(src->fpu() == 0, "input must be on TOS");
1557 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1559 // instruction sequence too long to inline it here
1560 {
1561 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1562 }
1563 break;
1565 default: ShouldNotReachHere();
1566 }
1567 }
1569 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1570 if (op->init_check()) {
1571 __ cmpl(Address(op->klass()->as_register(),
1572 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)),
1573 instanceKlass::fully_initialized);
1574 add_debug_info_for_null_check_here(op->stub()->info());
1575 __ jcc(Assembler::notEqual, *op->stub()->entry());
1576 }
1577 __ allocate_object(op->obj()->as_register(),
1578 op->tmp1()->as_register(),
1579 op->tmp2()->as_register(),
1580 op->header_size(),
1581 op->object_size(),
1582 op->klass()->as_register(),
1583 *op->stub()->entry());
1584 __ bind(*op->stub()->continuation());
1585 }
1587 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1588 if (UseSlowPath ||
1589 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1590 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1591 __ jmp(*op->stub()->entry());
1592 } else {
1593 Register len = op->len()->as_register();
1594 Register tmp1 = op->tmp1()->as_register();
1595 Register tmp2 = op->tmp2()->as_register();
1596 Register tmp3 = op->tmp3()->as_register();
1597 if (len == tmp1) {
1598 tmp1 = tmp3;
1599 } else if (len == tmp2) {
1600 tmp2 = tmp3;
1601 } else if (len == tmp3) {
1602 // everything is ok
1603 } else {
1604 __ mov(tmp3, len);
1605 }
1606 __ allocate_array(op->obj()->as_register(),
1607 len,
1608 tmp1,
1609 tmp2,
1610 arrayOopDesc::header_size(op->type()),
1611 array_element_size(op->type()),
1612 op->klass()->as_register(),
1613 *op->stub()->entry());
1614 }
1615 __ bind(*op->stub()->continuation());
1616 }
1618 void LIR_Assembler::type_profile_helper(Register mdo,
1619 ciMethodData *md, ciProfileData *data,
1620 Register recv, Label* update_done) {
1621 uint i;
1622 for (i = 0; i < ReceiverTypeData::row_limit(); i++) {
1623 Label next_test;
1624 // See if the receiver is receiver[n].
1625 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1626 __ jccb(Assembler::notEqual, next_test);
1627 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1628 __ addptr(data_addr, DataLayout::counter_increment);
1629 __ jmp(*update_done);
1630 __ bind(next_test);
1631 }
1633 // Didn't find receiver; find next empty slot and fill it in
1634 for (i = 0; i < ReceiverTypeData::row_limit(); i++) {
1635 Label next_test;
1636 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1637 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1638 __ jccb(Assembler::notEqual, next_test);
1639 __ movptr(recv_addr, recv);
1640 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1641 __ jmp(*update_done);
1642 __ bind(next_test);
1643 }
1644 }
1646 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1647 // we always need a stub for the failure case.
1648 CodeStub* stub = op->stub();
1649 Register obj = op->object()->as_register();
1650 Register k_RInfo = op->tmp1()->as_register();
1651 Register klass_RInfo = op->tmp2()->as_register();
1652 Register dst = op->result_opr()->as_register();
1653 ciKlass* k = op->klass();
1654 Register Rtmp1 = noreg;
1656 // check if it needs to be profiled
1657 ciMethodData* md;
1658 ciProfileData* data;
1660 if (op->should_profile()) {
1661 ciMethod* method = op->profiled_method();
1662 assert(method != NULL, "Should have method");
1663 int bci = op->profiled_bci();
1664 md = method->method_data();
1665 if (md == NULL) {
1666 bailout("out of memory building methodDataOop");
1667 return;
1668 }
1669 data = md->bci_to_data(bci);
1670 assert(data != NULL, "need data for type check");
1671 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1672 }
1673 Label profile_cast_success, profile_cast_failure;
1674 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1675 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1677 if (obj == k_RInfo) {
1678 k_RInfo = dst;
1679 } else if (obj == klass_RInfo) {
1680 klass_RInfo = dst;
1681 }
1682 if (k->is_loaded()) {
1683 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1684 } else {
1685 Rtmp1 = op->tmp3()->as_register();
1686 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1687 }
1689 assert_different_registers(obj, k_RInfo, klass_RInfo);
1690 if (!k->is_loaded()) {
1691 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
1692 } else {
1693 #ifdef _LP64
1694 __ movoop(k_RInfo, k->constant_encoding());
1695 #endif // _LP64
1696 }
1697 assert(obj != k_RInfo, "must be different");
1699 __ cmpptr(obj, (int32_t)NULL_WORD);
1700 if (op->should_profile()) {
1701 Label not_null;
1702 __ jccb(Assembler::notEqual, not_null);
1703 // Object is null; update MDO and exit
1704 Register mdo = klass_RInfo;
1705 __ movoop(mdo, md->constant_encoding());
1706 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1707 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1708 __ orl(data_addr, header_bits);
1709 __ jmp(*obj_is_null);
1710 __ bind(not_null);
1711 } else {
1712 __ jcc(Assembler::equal, *obj_is_null);
1713 }
1714 __ verify_oop(obj);
1716 if (op->fast_check()) {
1717 // get object class
1718 // not a safepoint as obj null check happens earlier
1719 if (k->is_loaded()) {
1720 #ifdef _LP64
1721 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1722 #else
1723 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1724 #endif // _LP64
1725 } else {
1726 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1727 }
1728 __ jcc(Assembler::notEqual, *failure_target);
1729 // successful cast, fall through to profile or jump
1730 } else {
1731 // get object class
1732 // not a safepoint as obj null check happens earlier
1733 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1734 if (k->is_loaded()) {
1735 // See if we get an immediate positive hit
1736 #ifdef _LP64
1737 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1738 #else
1739 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1740 #endif // _LP64
1741 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) {
1742 __ jcc(Assembler::notEqual, *failure_target);
1743 // successful cast, fall through to profile or jump
1744 } else {
1745 // See if we get an immediate positive hit
1746 __ jcc(Assembler::equal, *success_target);
1747 // check for self
1748 #ifdef _LP64
1749 __ cmpptr(klass_RInfo, k_RInfo);
1750 #else
1751 __ cmpoop(klass_RInfo, k->constant_encoding());
1752 #endif // _LP64
1753 __ jcc(Assembler::equal, *success_target);
1755 __ push(klass_RInfo);
1756 #ifdef _LP64
1757 __ push(k_RInfo);
1758 #else
1759 __ pushoop(k->constant_encoding());
1760 #endif // _LP64
1761 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1762 __ pop(klass_RInfo);
1763 __ pop(klass_RInfo);
1764 // result is a boolean
1765 __ cmpl(klass_RInfo, 0);
1766 __ jcc(Assembler::equal, *failure_target);
1767 // successful cast, fall through to profile or jump
1768 }
1769 } else {
1770 // perform the fast part of the checking logic
1771 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1772 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1773 __ push(klass_RInfo);
1774 __ push(k_RInfo);
1775 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1776 __ pop(klass_RInfo);
1777 __ pop(k_RInfo);
1778 // result is a boolean
1779 __ cmpl(k_RInfo, 0);
1780 __ jcc(Assembler::equal, *failure_target);
1781 // successful cast, fall through to profile or jump
1782 }
1783 }
1784 if (op->should_profile()) {
1785 Register mdo = klass_RInfo, recv = k_RInfo;
1786 __ bind(profile_cast_success);
1787 __ movoop(mdo, md->constant_encoding());
1788 __ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes()));
1789 Label update_done;
1790 type_profile_helper(mdo, md, data, recv, success);
1791 __ jmp(*success);
1793 __ bind(profile_cast_failure);
1794 __ movoop(mdo, md->constant_encoding());
1795 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1796 __ subptr(counter_addr, DataLayout::counter_increment);
1797 __ jmp(*failure);
1798 }
1799 __ jmp(*success);
1800 }
1803 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1804 LIR_Code code = op->code();
1805 if (code == lir_store_check) {
1806 Register value = op->object()->as_register();
1807 Register array = op->array()->as_register();
1808 Register k_RInfo = op->tmp1()->as_register();
1809 Register klass_RInfo = op->tmp2()->as_register();
1810 Register Rtmp1 = op->tmp3()->as_register();
1812 CodeStub* stub = op->stub();
1814 // check if it needs to be profiled
1815 ciMethodData* md;
1816 ciProfileData* data;
1818 if (op->should_profile()) {
1819 ciMethod* method = op->profiled_method();
1820 assert(method != NULL, "Should have method");
1821 int bci = op->profiled_bci();
1822 md = method->method_data();
1823 if (md == NULL) {
1824 bailout("out of memory building methodDataOop");
1825 return;
1826 }
1827 data = md->bci_to_data(bci);
1828 assert(data != NULL, "need data for type check");
1829 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1830 }
1831 Label profile_cast_success, profile_cast_failure, done;
1832 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1833 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1835 __ cmpptr(value, (int32_t)NULL_WORD);
1836 if (op->should_profile()) {
1837 Label not_null;
1838 __ jccb(Assembler::notEqual, not_null);
1839 // Object is null; update MDO and exit
1840 Register mdo = klass_RInfo;
1841 __ movoop(mdo, md->constant_encoding());
1842 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1843 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1844 __ orl(data_addr, header_bits);
1845 __ jmp(done);
1846 __ bind(not_null);
1847 } else {
1848 __ jcc(Assembler::equal, done);
1849 }
1851 add_debug_info_for_null_check_here(op->info_for_exception());
1852 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes()));
1853 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes()));
1855 // get instance klass
1856 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc)));
1857 // perform the fast part of the checking logic
1858 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1859 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1860 __ push(klass_RInfo);
1861 __ push(k_RInfo);
1862 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1863 __ pop(klass_RInfo);
1864 __ pop(k_RInfo);
1865 // result is a boolean
1866 __ cmpl(k_RInfo, 0);
1867 __ jcc(Assembler::equal, *failure_target);
1868 // fall through to the success case
1870 if (op->should_profile()) {
1871 Register mdo = klass_RInfo, recv = k_RInfo;
1872 __ bind(profile_cast_success);
1873 __ movoop(mdo, md->constant_encoding());
1874 __ movptr(recv, Address(value, oopDesc::klass_offset_in_bytes()));
1875 Label update_done;
1876 type_profile_helper(mdo, md, data, recv, &done);
1877 __ jmpb(done);
1879 __ bind(profile_cast_failure);
1880 __ movoop(mdo, md->constant_encoding());
1881 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1882 __ subptr(counter_addr, DataLayout::counter_increment);
1883 __ jmp(*stub->entry());
1884 }
1886 __ bind(done);
1887 } else
1888 if (code == lir_checkcast) {
1889 Register obj = op->object()->as_register();
1890 Register dst = op->result_opr()->as_register();
1891 Label success;
1892 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1893 __ bind(success);
1894 if (dst != obj) {
1895 __ mov(dst, obj);
1896 }
1897 } else
1898 if (code == lir_instanceof) {
1899 Register obj = op->object()->as_register();
1900 Register dst = op->result_opr()->as_register();
1901 Label success, failure, done;
1902 emit_typecheck_helper(op, &success, &failure, &failure);
1903 __ bind(failure);
1904 __ xorptr(dst, dst);
1905 __ jmpb(done);
1906 __ bind(success);
1907 __ movptr(dst, 1);
1908 __ bind(done);
1909 } else {
1910 ShouldNotReachHere();
1911 }
1913 }
1916 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1917 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1918 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1919 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1920 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1921 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1922 Register addr = op->addr()->as_register();
1923 if (os::is_MP()) {
1924 __ lock();
1925 }
1926 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1928 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1929 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1930 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1931 Register newval = op->new_value()->as_register();
1932 Register cmpval = op->cmp_value()->as_register();
1933 assert(cmpval == rax, "wrong register");
1934 assert(newval != NULL, "new val must be register");
1935 assert(cmpval != newval, "cmp and new values must be in different registers");
1936 assert(cmpval != addr, "cmp and addr must be in different registers");
1937 assert(newval != addr, "new value and addr must be in different registers");
1938 if (os::is_MP()) {
1939 __ lock();
1940 }
1941 if ( op->code() == lir_cas_obj) {
1942 __ cmpxchgptr(newval, Address(addr, 0));
1943 } else if (op->code() == lir_cas_int) {
1944 __ cmpxchgl(newval, Address(addr, 0));
1945 } else {
1946 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
1947 }
1948 #ifdef _LP64
1949 } else if (op->code() == lir_cas_long) {
1950 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1951 Register newval = op->new_value()->as_register_lo();
1952 Register cmpval = op->cmp_value()->as_register_lo();
1953 assert(cmpval == rax, "wrong register");
1954 assert(newval != NULL, "new val must be register");
1955 assert(cmpval != newval, "cmp and new values must be in different registers");
1956 assert(cmpval != addr, "cmp and addr must be in different registers");
1957 assert(newval != addr, "new value and addr must be in different registers");
1958 if (os::is_MP()) {
1959 __ lock();
1960 }
1961 __ cmpxchgq(newval, Address(addr, 0));
1962 #endif // _LP64
1963 } else {
1964 Unimplemented();
1965 }
1966 }
1968 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1969 Assembler::Condition acond, ncond;
1970 switch (condition) {
1971 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1972 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1973 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1974 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1975 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1976 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1977 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1978 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1979 default: ShouldNotReachHere();
1980 }
1982 if (opr1->is_cpu_register()) {
1983 reg2reg(opr1, result);
1984 } else if (opr1->is_stack()) {
1985 stack2reg(opr1, result, result->type());
1986 } else if (opr1->is_constant()) {
1987 const2reg(opr1, result, lir_patch_none, NULL);
1988 } else {
1989 ShouldNotReachHere();
1990 }
1992 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1993 // optimized version that does not require a branch
1994 if (opr2->is_single_cpu()) {
1995 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1996 __ cmov(ncond, result->as_register(), opr2->as_register());
1997 } else if (opr2->is_double_cpu()) {
1998 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1999 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2000 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2001 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2002 } else if (opr2->is_single_stack()) {
2003 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2004 } else if (opr2->is_double_stack()) {
2005 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2006 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2007 } else {
2008 ShouldNotReachHere();
2009 }
2011 } else {
2012 Label skip;
2013 __ jcc (acond, skip);
2014 if (opr2->is_cpu_register()) {
2015 reg2reg(opr2, result);
2016 } else if (opr2->is_stack()) {
2017 stack2reg(opr2, result, result->type());
2018 } else if (opr2->is_constant()) {
2019 const2reg(opr2, result, lir_patch_none, NULL);
2020 } else {
2021 ShouldNotReachHere();
2022 }
2023 __ bind(skip);
2024 }
2025 }
2028 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2029 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2031 if (left->is_single_cpu()) {
2032 assert(left == dest, "left and dest must be equal");
2033 Register lreg = left->as_register();
2035 if (right->is_single_cpu()) {
2036 // cpu register - cpu register
2037 Register rreg = right->as_register();
2038 switch (code) {
2039 case lir_add: __ addl (lreg, rreg); break;
2040 case lir_sub: __ subl (lreg, rreg); break;
2041 case lir_mul: __ imull(lreg, rreg); break;
2042 default: ShouldNotReachHere();
2043 }
2045 } else if (right->is_stack()) {
2046 // cpu register - stack
2047 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2048 switch (code) {
2049 case lir_add: __ addl(lreg, raddr); break;
2050 case lir_sub: __ subl(lreg, raddr); break;
2051 default: ShouldNotReachHere();
2052 }
2054 } else if (right->is_constant()) {
2055 // cpu register - constant
2056 jint c = right->as_constant_ptr()->as_jint();
2057 switch (code) {
2058 case lir_add: {
2059 __ incrementl(lreg, c);
2060 break;
2061 }
2062 case lir_sub: {
2063 __ decrementl(lreg, c);
2064 break;
2065 }
2066 default: ShouldNotReachHere();
2067 }
2069 } else {
2070 ShouldNotReachHere();
2071 }
2073 } else if (left->is_double_cpu()) {
2074 assert(left == dest, "left and dest must be equal");
2075 Register lreg_lo = left->as_register_lo();
2076 Register lreg_hi = left->as_register_hi();
2078 if (right->is_double_cpu()) {
2079 // cpu register - cpu register
2080 Register rreg_lo = right->as_register_lo();
2081 Register rreg_hi = right->as_register_hi();
2082 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2083 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2084 switch (code) {
2085 case lir_add:
2086 __ addptr(lreg_lo, rreg_lo);
2087 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2088 break;
2089 case lir_sub:
2090 __ subptr(lreg_lo, rreg_lo);
2091 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2092 break;
2093 case lir_mul:
2094 #ifdef _LP64
2095 __ imulq(lreg_lo, rreg_lo);
2096 #else
2097 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2098 __ imull(lreg_hi, rreg_lo);
2099 __ imull(rreg_hi, lreg_lo);
2100 __ addl (rreg_hi, lreg_hi);
2101 __ mull (rreg_lo);
2102 __ addl (lreg_hi, rreg_hi);
2103 #endif // _LP64
2104 break;
2105 default:
2106 ShouldNotReachHere();
2107 }
2109 } else if (right->is_constant()) {
2110 // cpu register - constant
2111 #ifdef _LP64
2112 jlong c = right->as_constant_ptr()->as_jlong_bits();
2113 __ movptr(r10, (intptr_t) c);
2114 switch (code) {
2115 case lir_add:
2116 __ addptr(lreg_lo, r10);
2117 break;
2118 case lir_sub:
2119 __ subptr(lreg_lo, r10);
2120 break;
2121 default:
2122 ShouldNotReachHere();
2123 }
2124 #else
2125 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2126 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2127 switch (code) {
2128 case lir_add:
2129 __ addptr(lreg_lo, c_lo);
2130 __ adcl(lreg_hi, c_hi);
2131 break;
2132 case lir_sub:
2133 __ subptr(lreg_lo, c_lo);
2134 __ sbbl(lreg_hi, c_hi);
2135 break;
2136 default:
2137 ShouldNotReachHere();
2138 }
2139 #endif // _LP64
2141 } else {
2142 ShouldNotReachHere();
2143 }
2145 } else if (left->is_single_xmm()) {
2146 assert(left == dest, "left and dest must be equal");
2147 XMMRegister lreg = left->as_xmm_float_reg();
2149 if (right->is_single_xmm()) {
2150 XMMRegister rreg = right->as_xmm_float_reg();
2151 switch (code) {
2152 case lir_add: __ addss(lreg, rreg); break;
2153 case lir_sub: __ subss(lreg, rreg); break;
2154 case lir_mul_strictfp: // fall through
2155 case lir_mul: __ mulss(lreg, rreg); break;
2156 case lir_div_strictfp: // fall through
2157 case lir_div: __ divss(lreg, rreg); break;
2158 default: ShouldNotReachHere();
2159 }
2160 } else {
2161 Address raddr;
2162 if (right->is_single_stack()) {
2163 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2164 } else if (right->is_constant()) {
2165 // hack for now
2166 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2167 } else {
2168 ShouldNotReachHere();
2169 }
2170 switch (code) {
2171 case lir_add: __ addss(lreg, raddr); break;
2172 case lir_sub: __ subss(lreg, raddr); break;
2173 case lir_mul_strictfp: // fall through
2174 case lir_mul: __ mulss(lreg, raddr); break;
2175 case lir_div_strictfp: // fall through
2176 case lir_div: __ divss(lreg, raddr); break;
2177 default: ShouldNotReachHere();
2178 }
2179 }
2181 } else if (left->is_double_xmm()) {
2182 assert(left == dest, "left and dest must be equal");
2184 XMMRegister lreg = left->as_xmm_double_reg();
2185 if (right->is_double_xmm()) {
2186 XMMRegister rreg = right->as_xmm_double_reg();
2187 switch (code) {
2188 case lir_add: __ addsd(lreg, rreg); break;
2189 case lir_sub: __ subsd(lreg, rreg); break;
2190 case lir_mul_strictfp: // fall through
2191 case lir_mul: __ mulsd(lreg, rreg); break;
2192 case lir_div_strictfp: // fall through
2193 case lir_div: __ divsd(lreg, rreg); break;
2194 default: ShouldNotReachHere();
2195 }
2196 } else {
2197 Address raddr;
2198 if (right->is_double_stack()) {
2199 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2200 } else if (right->is_constant()) {
2201 // hack for now
2202 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2203 } else {
2204 ShouldNotReachHere();
2205 }
2206 switch (code) {
2207 case lir_add: __ addsd(lreg, raddr); break;
2208 case lir_sub: __ subsd(lreg, raddr); break;
2209 case lir_mul_strictfp: // fall through
2210 case lir_mul: __ mulsd(lreg, raddr); break;
2211 case lir_div_strictfp: // fall through
2212 case lir_div: __ divsd(lreg, raddr); break;
2213 default: ShouldNotReachHere();
2214 }
2215 }
2217 } else if (left->is_single_fpu()) {
2218 assert(dest->is_single_fpu(), "fpu stack allocation required");
2220 if (right->is_single_fpu()) {
2221 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2223 } else {
2224 assert(left->fpu_regnr() == 0, "left must be on TOS");
2225 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2227 Address raddr;
2228 if (right->is_single_stack()) {
2229 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2230 } else if (right->is_constant()) {
2231 address const_addr = float_constant(right->as_jfloat());
2232 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2233 // hack for now
2234 raddr = __ as_Address(InternalAddress(const_addr));
2235 } else {
2236 ShouldNotReachHere();
2237 }
2239 switch (code) {
2240 case lir_add: __ fadd_s(raddr); break;
2241 case lir_sub: __ fsub_s(raddr); break;
2242 case lir_mul_strictfp: // fall through
2243 case lir_mul: __ fmul_s(raddr); break;
2244 case lir_div_strictfp: // fall through
2245 case lir_div: __ fdiv_s(raddr); break;
2246 default: ShouldNotReachHere();
2247 }
2248 }
2250 } else if (left->is_double_fpu()) {
2251 assert(dest->is_double_fpu(), "fpu stack allocation required");
2253 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2254 // Double values require special handling for strictfp mul/div on x86
2255 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2256 __ fmulp(left->fpu_regnrLo() + 1);
2257 }
2259 if (right->is_double_fpu()) {
2260 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2262 } else {
2263 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2264 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2266 Address raddr;
2267 if (right->is_double_stack()) {
2268 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2269 } else if (right->is_constant()) {
2270 // hack for now
2271 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2272 } else {
2273 ShouldNotReachHere();
2274 }
2276 switch (code) {
2277 case lir_add: __ fadd_d(raddr); break;
2278 case lir_sub: __ fsub_d(raddr); break;
2279 case lir_mul_strictfp: // fall through
2280 case lir_mul: __ fmul_d(raddr); break;
2281 case lir_div_strictfp: // fall through
2282 case lir_div: __ fdiv_d(raddr); break;
2283 default: ShouldNotReachHere();
2284 }
2285 }
2287 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2288 // Double values require special handling for strictfp mul/div on x86
2289 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2290 __ fmulp(dest->fpu_regnrLo() + 1);
2291 }
2293 } else if (left->is_single_stack() || left->is_address()) {
2294 assert(left == dest, "left and dest must be equal");
2296 Address laddr;
2297 if (left->is_single_stack()) {
2298 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2299 } else if (left->is_address()) {
2300 laddr = as_Address(left->as_address_ptr());
2301 } else {
2302 ShouldNotReachHere();
2303 }
2305 if (right->is_single_cpu()) {
2306 Register rreg = right->as_register();
2307 switch (code) {
2308 case lir_add: __ addl(laddr, rreg); break;
2309 case lir_sub: __ subl(laddr, rreg); break;
2310 default: ShouldNotReachHere();
2311 }
2312 } else if (right->is_constant()) {
2313 jint c = right->as_constant_ptr()->as_jint();
2314 switch (code) {
2315 case lir_add: {
2316 __ incrementl(laddr, c);
2317 break;
2318 }
2319 case lir_sub: {
2320 __ decrementl(laddr, c);
2321 break;
2322 }
2323 default: ShouldNotReachHere();
2324 }
2325 } else {
2326 ShouldNotReachHere();
2327 }
2329 } else {
2330 ShouldNotReachHere();
2331 }
2332 }
2334 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2335 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2336 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2337 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2339 bool left_is_tos = (left_index == 0);
2340 bool dest_is_tos = (dest_index == 0);
2341 int non_tos_index = (left_is_tos ? right_index : left_index);
2343 switch (code) {
2344 case lir_add:
2345 if (pop_fpu_stack) __ faddp(non_tos_index);
2346 else if (dest_is_tos) __ fadd (non_tos_index);
2347 else __ fadda(non_tos_index);
2348 break;
2350 case lir_sub:
2351 if (left_is_tos) {
2352 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2353 else if (dest_is_tos) __ fsub (non_tos_index);
2354 else __ fsubra(non_tos_index);
2355 } else {
2356 if (pop_fpu_stack) __ fsubp (non_tos_index);
2357 else if (dest_is_tos) __ fsubr (non_tos_index);
2358 else __ fsuba (non_tos_index);
2359 }
2360 break;
2362 case lir_mul_strictfp: // fall through
2363 case lir_mul:
2364 if (pop_fpu_stack) __ fmulp(non_tos_index);
2365 else if (dest_is_tos) __ fmul (non_tos_index);
2366 else __ fmula(non_tos_index);
2367 break;
2369 case lir_div_strictfp: // fall through
2370 case lir_div:
2371 if (left_is_tos) {
2372 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2373 else if (dest_is_tos) __ fdiv (non_tos_index);
2374 else __ fdivra(non_tos_index);
2375 } else {
2376 if (pop_fpu_stack) __ fdivp (non_tos_index);
2377 else if (dest_is_tos) __ fdivr (non_tos_index);
2378 else __ fdiva (non_tos_index);
2379 }
2380 break;
2382 case lir_rem:
2383 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2384 __ fremr(noreg);
2385 break;
2387 default:
2388 ShouldNotReachHere();
2389 }
2390 }
2393 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2394 if (value->is_double_xmm()) {
2395 switch(code) {
2396 case lir_abs :
2397 {
2398 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2399 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2400 }
2401 __ andpd(dest->as_xmm_double_reg(),
2402 ExternalAddress((address)double_signmask_pool));
2403 }
2404 break;
2406 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2407 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2408 default : ShouldNotReachHere();
2409 }
2411 } else if (value->is_double_fpu()) {
2412 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2413 switch(code) {
2414 case lir_log : __ flog() ; break;
2415 case lir_log10 : __ flog10() ; break;
2416 case lir_abs : __ fabs() ; break;
2417 case lir_sqrt : __ fsqrt(); break;
2418 case lir_sin :
2419 // Should consider not saving rbx, if not necessary
2420 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2421 break;
2422 case lir_cos :
2423 // Should consider not saving rbx, if not necessary
2424 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2425 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2426 break;
2427 case lir_tan :
2428 // Should consider not saving rbx, if not necessary
2429 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2430 break;
2431 default : ShouldNotReachHere();
2432 }
2433 } else {
2434 Unimplemented();
2435 }
2436 }
2438 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2439 // assert(left->destroys_register(), "check");
2440 if (left->is_single_cpu()) {
2441 Register reg = left->as_register();
2442 if (right->is_constant()) {
2443 int val = right->as_constant_ptr()->as_jint();
2444 switch (code) {
2445 case lir_logic_and: __ andl (reg, val); break;
2446 case lir_logic_or: __ orl (reg, val); break;
2447 case lir_logic_xor: __ xorl (reg, val); break;
2448 default: ShouldNotReachHere();
2449 }
2450 } else if (right->is_stack()) {
2451 // added support for stack operands
2452 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2453 switch (code) {
2454 case lir_logic_and: __ andl (reg, raddr); break;
2455 case lir_logic_or: __ orl (reg, raddr); break;
2456 case lir_logic_xor: __ xorl (reg, raddr); break;
2457 default: ShouldNotReachHere();
2458 }
2459 } else {
2460 Register rright = right->as_register();
2461 switch (code) {
2462 case lir_logic_and: __ andptr (reg, rright); break;
2463 case lir_logic_or : __ orptr (reg, rright); break;
2464 case lir_logic_xor: __ xorptr (reg, rright); break;
2465 default: ShouldNotReachHere();
2466 }
2467 }
2468 move_regs(reg, dst->as_register());
2469 } else {
2470 Register l_lo = left->as_register_lo();
2471 Register l_hi = left->as_register_hi();
2472 if (right->is_constant()) {
2473 #ifdef _LP64
2474 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2475 switch (code) {
2476 case lir_logic_and:
2477 __ andq(l_lo, rscratch1);
2478 break;
2479 case lir_logic_or:
2480 __ orq(l_lo, rscratch1);
2481 break;
2482 case lir_logic_xor:
2483 __ xorq(l_lo, rscratch1);
2484 break;
2485 default: ShouldNotReachHere();
2486 }
2487 #else
2488 int r_lo = right->as_constant_ptr()->as_jint_lo();
2489 int r_hi = right->as_constant_ptr()->as_jint_hi();
2490 switch (code) {
2491 case lir_logic_and:
2492 __ andl(l_lo, r_lo);
2493 __ andl(l_hi, r_hi);
2494 break;
2495 case lir_logic_or:
2496 __ orl(l_lo, r_lo);
2497 __ orl(l_hi, r_hi);
2498 break;
2499 case lir_logic_xor:
2500 __ xorl(l_lo, r_lo);
2501 __ xorl(l_hi, r_hi);
2502 break;
2503 default: ShouldNotReachHere();
2504 }
2505 #endif // _LP64
2506 } else {
2507 #ifdef _LP64
2508 Register r_lo;
2509 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2510 r_lo = right->as_register();
2511 } else {
2512 r_lo = right->as_register_lo();
2513 }
2514 #else
2515 Register r_lo = right->as_register_lo();
2516 Register r_hi = right->as_register_hi();
2517 assert(l_lo != r_hi, "overwriting registers");
2518 #endif
2519 switch (code) {
2520 case lir_logic_and:
2521 __ andptr(l_lo, r_lo);
2522 NOT_LP64(__ andptr(l_hi, r_hi);)
2523 break;
2524 case lir_logic_or:
2525 __ orptr(l_lo, r_lo);
2526 NOT_LP64(__ orptr(l_hi, r_hi);)
2527 break;
2528 case lir_logic_xor:
2529 __ xorptr(l_lo, r_lo);
2530 NOT_LP64(__ xorptr(l_hi, r_hi);)
2531 break;
2532 default: ShouldNotReachHere();
2533 }
2534 }
2536 Register dst_lo = dst->as_register_lo();
2537 Register dst_hi = dst->as_register_hi();
2539 #ifdef _LP64
2540 move_regs(l_lo, dst_lo);
2541 #else
2542 if (dst_lo == l_hi) {
2543 assert(dst_hi != l_lo, "overwriting registers");
2544 move_regs(l_hi, dst_hi);
2545 move_regs(l_lo, dst_lo);
2546 } else {
2547 assert(dst_lo != l_hi, "overwriting registers");
2548 move_regs(l_lo, dst_lo);
2549 move_regs(l_hi, dst_hi);
2550 }
2551 #endif // _LP64
2552 }
2553 }
2556 // we assume that rax, and rdx can be overwritten
2557 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2559 assert(left->is_single_cpu(), "left must be register");
2560 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2561 assert(result->is_single_cpu(), "result must be register");
2563 // assert(left->destroys_register(), "check");
2564 // assert(right->destroys_register(), "check");
2566 Register lreg = left->as_register();
2567 Register dreg = result->as_register();
2569 if (right->is_constant()) {
2570 int divisor = right->as_constant_ptr()->as_jint();
2571 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2572 if (code == lir_idiv) {
2573 assert(lreg == rax, "must be rax,");
2574 assert(temp->as_register() == rdx, "tmp register must be rdx");
2575 __ cdql(); // sign extend into rdx:rax
2576 if (divisor == 2) {
2577 __ subl(lreg, rdx);
2578 } else {
2579 __ andl(rdx, divisor - 1);
2580 __ addl(lreg, rdx);
2581 }
2582 __ sarl(lreg, log2_intptr(divisor));
2583 move_regs(lreg, dreg);
2584 } else if (code == lir_irem) {
2585 Label done;
2586 __ mov(dreg, lreg);
2587 __ andl(dreg, 0x80000000 | (divisor - 1));
2588 __ jcc(Assembler::positive, done);
2589 __ decrement(dreg);
2590 __ orl(dreg, ~(divisor - 1));
2591 __ increment(dreg);
2592 __ bind(done);
2593 } else {
2594 ShouldNotReachHere();
2595 }
2596 } else {
2597 Register rreg = right->as_register();
2598 assert(lreg == rax, "left register must be rax,");
2599 assert(rreg != rdx, "right register must not be rdx");
2600 assert(temp->as_register() == rdx, "tmp register must be rdx");
2602 move_regs(lreg, rax);
2604 int idivl_offset = __ corrected_idivl(rreg);
2605 add_debug_info_for_div0(idivl_offset, info);
2606 if (code == lir_irem) {
2607 move_regs(rdx, dreg); // result is in rdx
2608 } else {
2609 move_regs(rax, dreg);
2610 }
2611 }
2612 }
2615 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2616 if (opr1->is_single_cpu()) {
2617 Register reg1 = opr1->as_register();
2618 if (opr2->is_single_cpu()) {
2619 // cpu register - cpu register
2620 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2621 __ cmpptr(reg1, opr2->as_register());
2622 } else {
2623 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2624 __ cmpl(reg1, opr2->as_register());
2625 }
2626 } else if (opr2->is_stack()) {
2627 // cpu register - stack
2628 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2629 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2630 } else {
2631 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2632 }
2633 } else if (opr2->is_constant()) {
2634 // cpu register - constant
2635 LIR_Const* c = opr2->as_constant_ptr();
2636 if (c->type() == T_INT) {
2637 __ cmpl(reg1, c->as_jint());
2638 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2639 // In 64bit oops are single register
2640 jobject o = c->as_jobject();
2641 if (o == NULL) {
2642 __ cmpptr(reg1, (int32_t)NULL_WORD);
2643 } else {
2644 #ifdef _LP64
2645 __ movoop(rscratch1, o);
2646 __ cmpptr(reg1, rscratch1);
2647 #else
2648 __ cmpoop(reg1, c->as_jobject());
2649 #endif // _LP64
2650 }
2651 } else {
2652 ShouldNotReachHere();
2653 }
2654 // cpu register - address
2655 } else if (opr2->is_address()) {
2656 if (op->info() != NULL) {
2657 add_debug_info_for_null_check_here(op->info());
2658 }
2659 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2660 } else {
2661 ShouldNotReachHere();
2662 }
2664 } else if(opr1->is_double_cpu()) {
2665 Register xlo = opr1->as_register_lo();
2666 Register xhi = opr1->as_register_hi();
2667 if (opr2->is_double_cpu()) {
2668 #ifdef _LP64
2669 __ cmpptr(xlo, opr2->as_register_lo());
2670 #else
2671 // cpu register - cpu register
2672 Register ylo = opr2->as_register_lo();
2673 Register yhi = opr2->as_register_hi();
2674 __ subl(xlo, ylo);
2675 __ sbbl(xhi, yhi);
2676 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2677 __ orl(xhi, xlo);
2678 }
2679 #endif // _LP64
2680 } else if (opr2->is_constant()) {
2681 // cpu register - constant 0
2682 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2683 #ifdef _LP64
2684 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2685 #else
2686 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2687 __ orl(xhi, xlo);
2688 #endif // _LP64
2689 } else {
2690 ShouldNotReachHere();
2691 }
2693 } else if (opr1->is_single_xmm()) {
2694 XMMRegister reg1 = opr1->as_xmm_float_reg();
2695 if (opr2->is_single_xmm()) {
2696 // xmm register - xmm register
2697 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2698 } else if (opr2->is_stack()) {
2699 // xmm register - stack
2700 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2701 } else if (opr2->is_constant()) {
2702 // xmm register - constant
2703 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2704 } else if (opr2->is_address()) {
2705 // xmm register - address
2706 if (op->info() != NULL) {
2707 add_debug_info_for_null_check_here(op->info());
2708 }
2709 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2710 } else {
2711 ShouldNotReachHere();
2712 }
2714 } else if (opr1->is_double_xmm()) {
2715 XMMRegister reg1 = opr1->as_xmm_double_reg();
2716 if (opr2->is_double_xmm()) {
2717 // xmm register - xmm register
2718 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2719 } else if (opr2->is_stack()) {
2720 // xmm register - stack
2721 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2722 } else if (opr2->is_constant()) {
2723 // xmm register - constant
2724 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2725 } else if (opr2->is_address()) {
2726 // xmm register - address
2727 if (op->info() != NULL) {
2728 add_debug_info_for_null_check_here(op->info());
2729 }
2730 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2731 } else {
2732 ShouldNotReachHere();
2733 }
2735 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2736 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2737 assert(opr2->is_fpu_register(), "both must be registers");
2738 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2740 } else if (opr1->is_address() && opr2->is_constant()) {
2741 LIR_Const* c = opr2->as_constant_ptr();
2742 #ifdef _LP64
2743 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2744 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2745 __ movoop(rscratch1, c->as_jobject());
2746 }
2747 #endif // LP64
2748 if (op->info() != NULL) {
2749 add_debug_info_for_null_check_here(op->info());
2750 }
2751 // special case: address - constant
2752 LIR_Address* addr = opr1->as_address_ptr();
2753 if (c->type() == T_INT) {
2754 __ cmpl(as_Address(addr), c->as_jint());
2755 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2756 #ifdef _LP64
2757 // %%% Make this explode if addr isn't reachable until we figure out a
2758 // better strategy by giving noreg as the temp for as_Address
2759 __ cmpptr(rscratch1, as_Address(addr, noreg));
2760 #else
2761 __ cmpoop(as_Address(addr), c->as_jobject());
2762 #endif // _LP64
2763 } else {
2764 ShouldNotReachHere();
2765 }
2767 } else {
2768 ShouldNotReachHere();
2769 }
2770 }
2772 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2773 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2774 if (left->is_single_xmm()) {
2775 assert(right->is_single_xmm(), "must match");
2776 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2777 } else if (left->is_double_xmm()) {
2778 assert(right->is_double_xmm(), "must match");
2779 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2781 } else {
2782 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2783 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2785 assert(left->fpu() == 0, "left must be on TOS");
2786 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2787 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2788 }
2789 } else {
2790 assert(code == lir_cmp_l2i, "check");
2791 #ifdef _LP64
2792 Label done;
2793 Register dest = dst->as_register();
2794 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2795 __ movl(dest, -1);
2796 __ jccb(Assembler::less, done);
2797 __ set_byte_if_not_zero(dest);
2798 __ movzbl(dest, dest);
2799 __ bind(done);
2800 #else
2801 __ lcmp2int(left->as_register_hi(),
2802 left->as_register_lo(),
2803 right->as_register_hi(),
2804 right->as_register_lo());
2805 move_regs(left->as_register_hi(), dst->as_register());
2806 #endif // _LP64
2807 }
2808 }
2811 void LIR_Assembler::align_call(LIR_Code code) {
2812 if (os::is_MP()) {
2813 // make sure that the displacement word of the call ends up word aligned
2814 int offset = __ offset();
2815 switch (code) {
2816 case lir_static_call:
2817 case lir_optvirtual_call:
2818 case lir_dynamic_call:
2819 offset += NativeCall::displacement_offset;
2820 break;
2821 case lir_icvirtual_call:
2822 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2823 break;
2824 case lir_virtual_call: // currently, sparc-specific for niagara
2825 default: ShouldNotReachHere();
2826 }
2827 while (offset++ % BytesPerWord != 0) {
2828 __ nop();
2829 }
2830 }
2831 }
2834 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2835 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2836 "must be aligned");
2837 __ call(AddressLiteral(op->addr(), rtype));
2838 add_call_info(code_offset(), op->info());
2839 }
2842 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2843 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2844 __ movoop(IC_Klass, (jobject)Universe::non_oop_word());
2845 assert(!os::is_MP() ||
2846 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2847 "must be aligned");
2848 __ call(AddressLiteral(op->addr(), rh));
2849 add_call_info(code_offset(), op->info());
2850 }
2853 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2854 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2855 ShouldNotReachHere();
2856 }
2859 void LIR_Assembler::emit_static_call_stub() {
2860 address call_pc = __ pc();
2861 address stub = __ start_a_stub(call_stub_size);
2862 if (stub == NULL) {
2863 bailout("static call stub overflow");
2864 return;
2865 }
2867 int start = __ offset();
2868 if (os::is_MP()) {
2869 // make sure that the displacement word of the call ends up word aligned
2870 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2871 while (offset++ % BytesPerWord != 0) {
2872 __ nop();
2873 }
2874 }
2875 __ relocate(static_stub_Relocation::spec(call_pc));
2876 __ movoop(rbx, (jobject)NULL);
2877 // must be set to -1 at code generation time
2878 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2879 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2880 __ jump(RuntimeAddress(__ pc()));
2882 assert(__ offset() - start <= call_stub_size, "stub too big");
2883 __ end_a_stub();
2884 }
2887 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2888 assert(exceptionOop->as_register() == rax, "must match");
2889 assert(exceptionPC->as_register() == rdx, "must match");
2891 // exception object is not added to oop map by LinearScan
2892 // (LinearScan assumes that no oops are in fixed registers)
2893 info->add_register_oop(exceptionOop);
2894 Runtime1::StubID unwind_id;
2896 // get current pc information
2897 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2898 int pc_for_athrow_offset = __ offset();
2899 InternalAddress pc_for_athrow(__ pc());
2900 __ lea(exceptionPC->as_register(), pc_for_athrow);
2901 add_call_info(pc_for_athrow_offset, info); // for exception handler
2903 __ verify_not_null_oop(rax);
2904 // search an exception handler (rax: exception oop, rdx: throwing pc)
2905 if (compilation()->has_fpu_code()) {
2906 unwind_id = Runtime1::handle_exception_id;
2907 } else {
2908 unwind_id = Runtime1::handle_exception_nofpu_id;
2909 }
2910 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2912 // enough room for two byte trap
2913 __ nop();
2914 }
2917 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2918 assert(exceptionOop->as_register() == rax, "must match");
2920 __ jmp(_unwind_handler_entry);
2921 }
2924 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2926 // optimized version for linear scan:
2927 // * count must be already in ECX (guaranteed by LinearScan)
2928 // * left and dest must be equal
2929 // * tmp must be unused
2930 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2931 assert(left == dest, "left and dest must be equal");
2932 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2934 if (left->is_single_cpu()) {
2935 Register value = left->as_register();
2936 assert(value != SHIFT_count, "left cannot be ECX");
2938 switch (code) {
2939 case lir_shl: __ shll(value); break;
2940 case lir_shr: __ sarl(value); break;
2941 case lir_ushr: __ shrl(value); break;
2942 default: ShouldNotReachHere();
2943 }
2944 } else if (left->is_double_cpu()) {
2945 Register lo = left->as_register_lo();
2946 Register hi = left->as_register_hi();
2947 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2948 #ifdef _LP64
2949 switch (code) {
2950 case lir_shl: __ shlptr(lo); break;
2951 case lir_shr: __ sarptr(lo); break;
2952 case lir_ushr: __ shrptr(lo); break;
2953 default: ShouldNotReachHere();
2954 }
2955 #else
2957 switch (code) {
2958 case lir_shl: __ lshl(hi, lo); break;
2959 case lir_shr: __ lshr(hi, lo, true); break;
2960 case lir_ushr: __ lshr(hi, lo, false); break;
2961 default: ShouldNotReachHere();
2962 }
2963 #endif // LP64
2964 } else {
2965 ShouldNotReachHere();
2966 }
2967 }
2970 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2971 if (dest->is_single_cpu()) {
2972 // first move left into dest so that left is not destroyed by the shift
2973 Register value = dest->as_register();
2974 count = count & 0x1F; // Java spec
2976 move_regs(left->as_register(), value);
2977 switch (code) {
2978 case lir_shl: __ shll(value, count); break;
2979 case lir_shr: __ sarl(value, count); break;
2980 case lir_ushr: __ shrl(value, count); break;
2981 default: ShouldNotReachHere();
2982 }
2983 } else if (dest->is_double_cpu()) {
2984 #ifndef _LP64
2985 Unimplemented();
2986 #else
2987 // first move left into dest so that left is not destroyed by the shift
2988 Register value = dest->as_register_lo();
2989 count = count & 0x1F; // Java spec
2991 move_regs(left->as_register_lo(), value);
2992 switch (code) {
2993 case lir_shl: __ shlptr(value, count); break;
2994 case lir_shr: __ sarptr(value, count); break;
2995 case lir_ushr: __ shrptr(value, count); break;
2996 default: ShouldNotReachHere();
2997 }
2998 #endif // _LP64
2999 } else {
3000 ShouldNotReachHere();
3001 }
3002 }
3005 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3006 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3007 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3008 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3009 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3010 }
3013 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3014 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3015 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3016 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3017 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3018 }
3021 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3022 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3023 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3024 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3025 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3026 }
3029 // This code replaces a call to arraycopy; no exception may
3030 // be thrown in this code, they must be thrown in the System.arraycopy
3031 // activation frame; we could save some checks if this would not be the case
3032 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3033 ciArrayKlass* default_type = op->expected_type();
3034 Register src = op->src()->as_register();
3035 Register dst = op->dst()->as_register();
3036 Register src_pos = op->src_pos()->as_register();
3037 Register dst_pos = op->dst_pos()->as_register();
3038 Register length = op->length()->as_register();
3039 Register tmp = op->tmp()->as_register();
3041 CodeStub* stub = op->stub();
3042 int flags = op->flags();
3043 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3044 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3046 // if we don't know anything or it's an object array, just go through the generic arraycopy
3047 if (default_type == NULL) {
3048 Label done;
3049 // save outgoing arguments on stack in case call to System.arraycopy is needed
3050 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3051 // for interpreter calling conventions. Now we have to do it in new style conventions.
3052 // For the moment until C1 gets the new register allocator I just force all the
3053 // args to the right place (except the register args) and then on the back side
3054 // reload the register args properly if we go slow path. Yuck
3056 // These are proper for the calling convention
3058 store_parameter(length, 2);
3059 store_parameter(dst_pos, 1);
3060 store_parameter(dst, 0);
3062 // these are just temporary placements until we need to reload
3063 store_parameter(src_pos, 3);
3064 store_parameter(src, 4);
3065 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3067 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3069 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3070 #ifdef _LP64
3071 // The arguments are in java calling convention so we can trivially shift them to C
3072 // convention
3073 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3074 __ mov(c_rarg0, j_rarg0);
3075 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3076 __ mov(c_rarg1, j_rarg1);
3077 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3078 __ mov(c_rarg2, j_rarg2);
3079 assert_different_registers(c_rarg3, j_rarg4);
3080 __ mov(c_rarg3, j_rarg3);
3081 #ifdef _WIN64
3082 // Allocate abi space for args but be sure to keep stack aligned
3083 __ subptr(rsp, 6*wordSize);
3084 store_parameter(j_rarg4, 4);
3085 __ call(RuntimeAddress(entry));
3086 __ addptr(rsp, 6*wordSize);
3087 #else
3088 __ mov(c_rarg4, j_rarg4);
3089 __ call(RuntimeAddress(entry));
3090 #endif // _WIN64
3091 #else
3092 __ push(length);
3093 __ push(dst_pos);
3094 __ push(dst);
3095 __ push(src_pos);
3096 __ push(src);
3097 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack
3099 #endif // _LP64
3101 __ cmpl(rax, 0);
3102 __ jcc(Assembler::equal, *stub->continuation());
3104 // Reload values from the stack so they are where the stub
3105 // expects them.
3106 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3107 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3108 __ movptr (length, Address(rsp, 2*BytesPerWord));
3109 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3110 __ movptr (src, Address(rsp, 4*BytesPerWord));
3111 __ jmp(*stub->entry());
3113 __ bind(*stub->continuation());
3114 return;
3115 }
3117 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3119 int elem_size = type2aelembytes(basic_type);
3120 int shift_amount;
3121 Address::ScaleFactor scale;
3123 switch (elem_size) {
3124 case 1 :
3125 shift_amount = 0;
3126 scale = Address::times_1;
3127 break;
3128 case 2 :
3129 shift_amount = 1;
3130 scale = Address::times_2;
3131 break;
3132 case 4 :
3133 shift_amount = 2;
3134 scale = Address::times_4;
3135 break;
3136 case 8 :
3137 shift_amount = 3;
3138 scale = Address::times_8;
3139 break;
3140 default:
3141 ShouldNotReachHere();
3142 }
3144 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3145 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3146 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3147 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3149 // length and pos's are all sign extended at this point on 64bit
3151 // test for NULL
3152 if (flags & LIR_OpArrayCopy::src_null_check) {
3153 __ testptr(src, src);
3154 __ jcc(Assembler::zero, *stub->entry());
3155 }
3156 if (flags & LIR_OpArrayCopy::dst_null_check) {
3157 __ testptr(dst, dst);
3158 __ jcc(Assembler::zero, *stub->entry());
3159 }
3161 // check if negative
3162 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3163 __ testl(src_pos, src_pos);
3164 __ jcc(Assembler::less, *stub->entry());
3165 }
3166 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3167 __ testl(dst_pos, dst_pos);
3168 __ jcc(Assembler::less, *stub->entry());
3169 }
3170 if (flags & LIR_OpArrayCopy::length_positive_check) {
3171 __ testl(length, length);
3172 __ jcc(Assembler::less, *stub->entry());
3173 }
3175 if (flags & LIR_OpArrayCopy::src_range_check) {
3176 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3177 __ cmpl(tmp, src_length_addr);
3178 __ jcc(Assembler::above, *stub->entry());
3179 }
3180 if (flags & LIR_OpArrayCopy::dst_range_check) {
3181 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3182 __ cmpl(tmp, dst_length_addr);
3183 __ jcc(Assembler::above, *stub->entry());
3184 }
3186 if (flags & LIR_OpArrayCopy::type_check) {
3187 __ movptr(tmp, src_klass_addr);
3188 __ cmpptr(tmp, dst_klass_addr);
3189 __ jcc(Assembler::notEqual, *stub->entry());
3190 }
3192 #ifdef ASSERT
3193 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3194 // Sanity check the known type with the incoming class. For the
3195 // primitive case the types must match exactly with src.klass and
3196 // dst.klass each exactly matching the default type. For the
3197 // object array case, if no type check is needed then either the
3198 // dst type is exactly the expected type and the src type is a
3199 // subtype which we can't check or src is the same array as dst
3200 // but not necessarily exactly of type default_type.
3201 Label known_ok, halt;
3202 __ movoop(tmp, default_type->constant_encoding());
3203 if (basic_type != T_OBJECT) {
3204 __ cmpptr(tmp, dst_klass_addr);
3205 __ jcc(Assembler::notEqual, halt);
3206 __ cmpptr(tmp, src_klass_addr);
3207 __ jcc(Assembler::equal, known_ok);
3208 } else {
3209 __ cmpptr(tmp, dst_klass_addr);
3210 __ jcc(Assembler::equal, known_ok);
3211 __ cmpptr(src, dst);
3212 __ jcc(Assembler::equal, known_ok);
3213 }
3214 __ bind(halt);
3215 __ stop("incorrect type information in arraycopy");
3216 __ bind(known_ok);
3217 }
3218 #endif
3220 if (shift_amount > 0 && basic_type != T_OBJECT) {
3221 __ shlptr(length, shift_amount);
3222 }
3224 #ifdef _LP64
3225 assert_different_registers(c_rarg0, dst, dst_pos, length);
3226 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3227 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3228 assert_different_registers(c_rarg1, length);
3229 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3230 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3231 __ mov(c_rarg2, length);
3233 #else
3234 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3235 store_parameter(tmp, 0);
3236 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3237 store_parameter(tmp, 1);
3238 store_parameter(length, 2);
3239 #endif // _LP64
3240 if (basic_type == T_OBJECT) {
3241 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0);
3242 } else {
3243 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0);
3244 }
3246 __ bind(*stub->continuation());
3247 }
3250 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3251 Register obj = op->obj_opr()->as_register(); // may not be an oop
3252 Register hdr = op->hdr_opr()->as_register();
3253 Register lock = op->lock_opr()->as_register();
3254 if (!UseFastLocking) {
3255 __ jmp(*op->stub()->entry());
3256 } else if (op->code() == lir_lock) {
3257 Register scratch = noreg;
3258 if (UseBiasedLocking) {
3259 scratch = op->scratch_opr()->as_register();
3260 }
3261 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3262 // add debug info for NullPointerException only if one is possible
3263 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3264 if (op->info() != NULL) {
3265 add_debug_info_for_null_check(null_check_offset, op->info());
3266 }
3267 // done
3268 } else if (op->code() == lir_unlock) {
3269 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3270 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3271 } else {
3272 Unimplemented();
3273 }
3274 __ bind(*op->stub()->continuation());
3275 }
3278 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3279 ciMethod* method = op->profiled_method();
3280 int bci = op->profiled_bci();
3282 // Update counter for all call types
3283 ciMethodData* md = method->method_data();
3284 if (md == NULL) {
3285 bailout("out of memory building methodDataOop");
3286 return;
3287 }
3288 ciProfileData* data = md->bci_to_data(bci);
3289 assert(data->is_CounterData(), "need CounterData for calls");
3290 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3291 Register mdo = op->mdo()->as_register();
3292 __ movoop(mdo, md->constant_encoding());
3293 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3294 Bytecodes::Code bc = method->java_code_at_bci(bci);
3295 // Perform additional virtual call profiling for invokevirtual and
3296 // invokeinterface bytecodes
3297 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3298 C1ProfileVirtualCalls) {
3299 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3300 Register recv = op->recv()->as_register();
3301 assert_different_registers(mdo, recv);
3302 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3303 ciKlass* known_klass = op->known_holder();
3304 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3305 // We know the type that will be seen at this call site; we can
3306 // statically update the methodDataOop rather than needing to do
3307 // dynamic tests on the receiver type
3309 // NOTE: we should probably put a lock around this search to
3310 // avoid collisions by concurrent compilations
3311 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3312 uint i;
3313 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3314 ciKlass* receiver = vc_data->receiver(i);
3315 if (known_klass->equals(receiver)) {
3316 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3317 __ addptr(data_addr, DataLayout::counter_increment);
3318 return;
3319 }
3320 }
3322 // Receiver type not found in profile data; select an empty slot
3324 // Note that this is less efficient than it should be because it
3325 // always does a write to the receiver part of the
3326 // VirtualCallData rather than just the first time
3327 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3328 ciKlass* receiver = vc_data->receiver(i);
3329 if (receiver == NULL) {
3330 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3331 __ movoop(recv_addr, known_klass->constant_encoding());
3332 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3333 __ addptr(data_addr, DataLayout::counter_increment);
3334 return;
3335 }
3336 }
3337 } else {
3338 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes()));
3339 Label update_done;
3340 type_profile_helper(mdo, md, data, recv, &update_done);
3341 // Receiver did not match any saved receiver and there is no empty row for it.
3342 // Increment total counter to indicate polymorphic case.
3343 __ addptr(counter_addr, DataLayout::counter_increment);
3345 __ bind(update_done);
3346 }
3347 } else {
3348 // Static call
3349 __ addptr(counter_addr, DataLayout::counter_increment);
3350 }
3351 }
3353 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3354 Unimplemented();
3355 }
3358 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3359 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3360 }
3363 void LIR_Assembler::align_backward_branch_target() {
3364 __ align(BytesPerWord);
3365 }
3368 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3369 if (left->is_single_cpu()) {
3370 __ negl(left->as_register());
3371 move_regs(left->as_register(), dest->as_register());
3373 } else if (left->is_double_cpu()) {
3374 Register lo = left->as_register_lo();
3375 #ifdef _LP64
3376 Register dst = dest->as_register_lo();
3377 __ movptr(dst, lo);
3378 __ negptr(dst);
3379 #else
3380 Register hi = left->as_register_hi();
3381 __ lneg(hi, lo);
3382 if (dest->as_register_lo() == hi) {
3383 assert(dest->as_register_hi() != lo, "destroying register");
3384 move_regs(hi, dest->as_register_hi());
3385 move_regs(lo, dest->as_register_lo());
3386 } else {
3387 move_regs(lo, dest->as_register_lo());
3388 move_regs(hi, dest->as_register_hi());
3389 }
3390 #endif // _LP64
3392 } else if (dest->is_single_xmm()) {
3393 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3394 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3395 }
3396 __ xorps(dest->as_xmm_float_reg(),
3397 ExternalAddress((address)float_signflip_pool));
3399 } else if (dest->is_double_xmm()) {
3400 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3401 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3402 }
3403 __ xorpd(dest->as_xmm_double_reg(),
3404 ExternalAddress((address)double_signflip_pool));
3406 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3407 assert(left->fpu() == 0, "arg must be on TOS");
3408 assert(dest->fpu() == 0, "dest must be TOS");
3409 __ fchs();
3411 } else {
3412 ShouldNotReachHere();
3413 }
3414 }
3417 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3418 assert(addr->is_address() && dest->is_register(), "check");
3419 Register reg;
3420 reg = dest->as_pointer_register();
3421 __ lea(reg, as_Address(addr->as_address_ptr()));
3422 }
3426 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3427 assert(!tmp->is_valid(), "don't need temporary");
3428 __ call(RuntimeAddress(dest));
3429 if (info != NULL) {
3430 add_call_info_here(info);
3431 }
3432 }
3435 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3436 assert(type == T_LONG, "only for volatile long fields");
3438 if (info != NULL) {
3439 add_debug_info_for_null_check_here(info);
3440 }
3442 if (src->is_double_xmm()) {
3443 if (dest->is_double_cpu()) {
3444 #ifdef _LP64
3445 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3446 #else
3447 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3448 __ psrlq(src->as_xmm_double_reg(), 32);
3449 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3450 #endif // _LP64
3451 } else if (dest->is_double_stack()) {
3452 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3453 } else if (dest->is_address()) {
3454 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3455 } else {
3456 ShouldNotReachHere();
3457 }
3459 } else if (dest->is_double_xmm()) {
3460 if (src->is_double_stack()) {
3461 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3462 } else if (src->is_address()) {
3463 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3464 } else {
3465 ShouldNotReachHere();
3466 }
3468 } else if (src->is_double_fpu()) {
3469 assert(src->fpu_regnrLo() == 0, "must be TOS");
3470 if (dest->is_double_stack()) {
3471 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3472 } else if (dest->is_address()) {
3473 __ fistp_d(as_Address(dest->as_address_ptr()));
3474 } else {
3475 ShouldNotReachHere();
3476 }
3478 } else if (dest->is_double_fpu()) {
3479 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3480 if (src->is_double_stack()) {
3481 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3482 } else if (src->is_address()) {
3483 __ fild_d(as_Address(src->as_address_ptr()));
3484 } else {
3485 ShouldNotReachHere();
3486 }
3487 } else {
3488 ShouldNotReachHere();
3489 }
3490 }
3493 void LIR_Assembler::membar() {
3494 // QQQ sparc TSO uses this,
3495 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3496 }
3498 void LIR_Assembler::membar_acquire() {
3499 // No x86 machines currently require load fences
3500 // __ load_fence();
3501 }
3503 void LIR_Assembler::membar_release() {
3504 // No x86 machines currently require store fences
3505 // __ store_fence();
3506 }
3508 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3509 assert(result_reg->is_register(), "check");
3510 #ifdef _LP64
3511 // __ get_thread(result_reg->as_register_lo());
3512 __ mov(result_reg->as_register(), r15_thread);
3513 #else
3514 __ get_thread(result_reg->as_register());
3515 #endif // _LP64
3516 }
3519 void LIR_Assembler::peephole(LIR_List*) {
3520 // do nothing for now
3521 }
3524 #undef __
