Fri, 25 Jan 2013 10:04:08 -0500
8000692: Remove old KERNEL code
Summary: Removed depreciated kernel VM source code from hotspot VM
Reviewed-by: dholmes, acorn
1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #ifndef SERIALGC
40 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
41 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
42 #include "gc_implementation/g1/heapRegion.hpp"
43 #endif
45 #ifdef PRODUCT
46 #define BLOCK_COMMENT(str) /* nothing */
47 #define STOP(error) stop(error)
48 #else
49 #define BLOCK_COMMENT(str) block_comment(str)
50 #define STOP(error) block_comment(error); stop(error)
51 #endif
53 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
54 // Implementation of AddressLiteral
56 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
57 _is_lval = false;
58 _target = target;
59 switch (rtype) {
60 case relocInfo::oop_type:
61 case relocInfo::metadata_type:
62 // Oops are a special case. Normally they would be their own section
63 // but in cases like icBuffer they are literals in the code stream that
64 // we don't have a section for. We use none so that we get a literal address
65 // which is always patchable.
66 break;
67 case relocInfo::external_word_type:
68 _rspec = external_word_Relocation::spec(target);
69 break;
70 case relocInfo::internal_word_type:
71 _rspec = internal_word_Relocation::spec(target);
72 break;
73 case relocInfo::opt_virtual_call_type:
74 _rspec = opt_virtual_call_Relocation::spec();
75 break;
76 case relocInfo::static_call_type:
77 _rspec = static_call_Relocation::spec();
78 break;
79 case relocInfo::runtime_call_type:
80 _rspec = runtime_call_Relocation::spec();
81 break;
82 case relocInfo::poll_type:
83 case relocInfo::poll_return_type:
84 _rspec = Relocation::spec_simple(rtype);
85 break;
86 case relocInfo::none:
87 break;
88 default:
89 ShouldNotReachHere();
90 break;
91 }
92 }
94 // Implementation of Address
96 #ifdef _LP64
98 Address Address::make_array(ArrayAddress adr) {
99 // Not implementable on 64bit machines
100 // Should have been handled higher up the call chain.
101 ShouldNotReachHere();
102 return Address();
103 }
105 // exceedingly dangerous constructor
106 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
107 _base = noreg;
108 _index = noreg;
109 _scale = no_scale;
110 _disp = disp;
111 switch (rtype) {
112 case relocInfo::external_word_type:
113 _rspec = external_word_Relocation::spec(loc);
114 break;
115 case relocInfo::internal_word_type:
116 _rspec = internal_word_Relocation::spec(loc);
117 break;
118 case relocInfo::runtime_call_type:
119 // HMM
120 _rspec = runtime_call_Relocation::spec();
121 break;
122 case relocInfo::poll_type:
123 case relocInfo::poll_return_type:
124 _rspec = Relocation::spec_simple(rtype);
125 break;
126 case relocInfo::none:
127 break;
128 default:
129 ShouldNotReachHere();
130 }
131 }
132 #else // LP64
134 Address Address::make_array(ArrayAddress adr) {
135 AddressLiteral base = adr.base();
136 Address index = adr.index();
137 assert(index._disp == 0, "must not have disp"); // maybe it can?
138 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
139 array._rspec = base._rspec;
140 return array;
141 }
143 // exceedingly dangerous constructor
144 Address::Address(address loc, RelocationHolder spec) {
145 _base = noreg;
146 _index = noreg;
147 _scale = no_scale;
148 _disp = (intptr_t) loc;
149 _rspec = spec;
150 }
152 #endif // _LP64
156 // Convert the raw encoding form into the form expected by the constructor for
157 // Address. An index of 4 (rsp) corresponds to having no index, so convert
158 // that to noreg for the Address constructor.
159 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
160 RelocationHolder rspec;
161 if (disp_reloc != relocInfo::none) {
162 rspec = Relocation::spec_simple(disp_reloc);
163 }
164 bool valid_index = index != rsp->encoding();
165 if (valid_index) {
166 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
167 madr._rspec = rspec;
168 return madr;
169 } else {
170 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
171 madr._rspec = rspec;
172 return madr;
173 }
174 }
176 // Implementation of Assembler
178 int AbstractAssembler::code_fill_byte() {
179 return (u_char)'\xF4'; // hlt
180 }
182 // make this go away someday
183 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
184 if (rtype == relocInfo::none)
185 emit_int32(data);
186 else emit_data(data, Relocation::spec_simple(rtype), format);
187 }
189 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
190 assert(imm_operand == 0, "default format must be immediate in this file");
191 assert(inst_mark() != NULL, "must be inside InstructionMark");
192 if (rspec.type() != relocInfo::none) {
193 #ifdef ASSERT
194 check_relocation(rspec, format);
195 #endif
196 // Do not use AbstractAssembler::relocate, which is not intended for
197 // embedded words. Instead, relocate to the enclosing instruction.
199 // hack. call32 is too wide for mask so use disp32
200 if (format == call32_operand)
201 code_section()->relocate(inst_mark(), rspec, disp32_operand);
202 else
203 code_section()->relocate(inst_mark(), rspec, format);
204 }
205 emit_int32(data);
206 }
208 static int encode(Register r) {
209 int enc = r->encoding();
210 if (enc >= 8) {
211 enc -= 8;
212 }
213 return enc;
214 }
216 static int encode(XMMRegister r) {
217 int enc = r->encoding();
218 if (enc >= 8) {
219 enc -= 8;
220 }
221 return enc;
222 }
224 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
225 assert(dst->has_byte_register(), "must have byte register");
226 assert(isByte(op1) && isByte(op2), "wrong opcode");
227 assert(isByte(imm8), "not a byte");
228 assert((op1 & 0x01) == 0, "should be 8bit operation");
229 emit_int8(op1);
230 emit_int8(op2 | encode(dst));
231 emit_int8(imm8);
232 }
235 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
236 assert(isByte(op1) && isByte(op2), "wrong opcode");
237 assert((op1 & 0x01) == 1, "should be 32bit operation");
238 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
239 if (is8bit(imm32)) {
240 emit_int8(op1 | 0x02); // set sign bit
241 emit_int8(op2 | encode(dst));
242 emit_int8(imm32 & 0xFF);
243 } else {
244 emit_int8(op1);
245 emit_int8(op2 | encode(dst));
246 emit_int32(imm32);
247 }
248 }
250 // Force generation of a 4 byte immediate value even if it fits into 8bit
251 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
252 assert(isByte(op1) && isByte(op2), "wrong opcode");
253 assert((op1 & 0x01) == 1, "should be 32bit operation");
254 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
255 emit_int8(op1);
256 emit_int8(op2 | encode(dst));
257 emit_int32(imm32);
258 }
260 // immediate-to-memory forms
261 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
262 assert((op1 & 0x01) == 1, "should be 32bit operation");
263 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
264 if (is8bit(imm32)) {
265 emit_int8(op1 | 0x02); // set sign bit
266 emit_operand(rm, adr, 1);
267 emit_int8(imm32 & 0xFF);
268 } else {
269 emit_int8(op1);
270 emit_operand(rm, adr, 4);
271 emit_int32(imm32);
272 }
273 }
276 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
277 assert(isByte(op1) && isByte(op2), "wrong opcode");
278 emit_int8(op1);
279 emit_int8(op2 | encode(dst) << 3 | encode(src));
280 }
283 void Assembler::emit_operand(Register reg, Register base, Register index,
284 Address::ScaleFactor scale, int disp,
285 RelocationHolder const& rspec,
286 int rip_relative_correction) {
287 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
289 // Encode the registers as needed in the fields they are used in
291 int regenc = encode(reg) << 3;
292 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
293 int baseenc = base->is_valid() ? encode(base) : 0;
295 if (base->is_valid()) {
296 if (index->is_valid()) {
297 assert(scale != Address::no_scale, "inconsistent address");
298 // [base + index*scale + disp]
299 if (disp == 0 && rtype == relocInfo::none &&
300 base != rbp LP64_ONLY(&& base != r13)) {
301 // [base + index*scale]
302 // [00 reg 100][ss index base]
303 assert(index != rsp, "illegal addressing mode");
304 emit_int8(0x04 | regenc);
305 emit_int8(scale << 6 | indexenc | baseenc);
306 } else if (is8bit(disp) && rtype == relocInfo::none) {
307 // [base + index*scale + imm8]
308 // [01 reg 100][ss index base] imm8
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x44 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_int8(disp & 0xFF);
313 } else {
314 // [base + index*scale + disp32]
315 // [10 reg 100][ss index base] disp32
316 assert(index != rsp, "illegal addressing mode");
317 emit_int8(0x84 | regenc);
318 emit_int8(scale << 6 | indexenc | baseenc);
319 emit_data(disp, rspec, disp32_operand);
320 }
321 } else if (base == rsp LP64_ONLY(|| base == r12)) {
322 // [rsp + disp]
323 if (disp == 0 && rtype == relocInfo::none) {
324 // [rsp]
325 // [00 reg 100][00 100 100]
326 emit_int8(0x04 | regenc);
327 emit_int8(0x24);
328 } else if (is8bit(disp) && rtype == relocInfo::none) {
329 // [rsp + imm8]
330 // [01 reg 100][00 100 100] disp8
331 emit_int8(0x44 | regenc);
332 emit_int8(0x24);
333 emit_int8(disp & 0xFF);
334 } else {
335 // [rsp + imm32]
336 // [10 reg 100][00 100 100] disp32
337 emit_int8(0x84 | regenc);
338 emit_int8(0x24);
339 emit_data(disp, rspec, disp32_operand);
340 }
341 } else {
342 // [base + disp]
343 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
344 if (disp == 0 && rtype == relocInfo::none &&
345 base != rbp LP64_ONLY(&& base != r13)) {
346 // [base]
347 // [00 reg base]
348 emit_int8(0x00 | regenc | baseenc);
349 } else if (is8bit(disp) && rtype == relocInfo::none) {
350 // [base + disp8]
351 // [01 reg base] disp8
352 emit_int8(0x40 | regenc | baseenc);
353 emit_int8(disp & 0xFF);
354 } else {
355 // [base + disp32]
356 // [10 reg base] disp32
357 emit_int8(0x80 | regenc | baseenc);
358 emit_data(disp, rspec, disp32_operand);
359 }
360 }
361 } else {
362 if (index->is_valid()) {
363 assert(scale != Address::no_scale, "inconsistent address");
364 // [index*scale + disp]
365 // [00 reg 100][ss index 101] disp32
366 assert(index != rsp, "illegal addressing mode");
367 emit_int8(0x04 | regenc);
368 emit_int8(scale << 6 | indexenc | 0x05);
369 emit_data(disp, rspec, disp32_operand);
370 } else if (rtype != relocInfo::none ) {
371 // [disp] (64bit) RIP-RELATIVE (32bit) abs
372 // [00 000 101] disp32
374 emit_int8(0x05 | regenc);
375 // Note that the RIP-rel. correction applies to the generated
376 // disp field, but _not_ to the target address in the rspec.
378 // disp was created by converting the target address minus the pc
379 // at the start of the instruction. That needs more correction here.
380 // intptr_t disp = target - next_ip;
381 assert(inst_mark() != NULL, "must be inside InstructionMark");
382 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
383 int64_t adjusted = disp;
384 // Do rip-rel adjustment for 64bit
385 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
386 assert(is_simm32(adjusted),
387 "must be 32bit offset (RIP relative address)");
388 emit_data((int32_t) adjusted, rspec, disp32_operand);
390 } else {
391 // 32bit never did this, did everything as the rip-rel/disp code above
392 // [disp] ABSOLUTE
393 // [00 reg 100][00 100 101] disp32
394 emit_int8(0x04 | regenc);
395 emit_int8(0x25);
396 emit_data(disp, rspec, disp32_operand);
397 }
398 }
399 }
401 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
402 Address::ScaleFactor scale, int disp,
403 RelocationHolder const& rspec) {
404 emit_operand((Register)reg, base, index, scale, disp, rspec);
405 }
407 // Secret local extension to Assembler::WhichOperand:
408 #define end_pc_operand (_WhichOperand_limit)
410 address Assembler::locate_operand(address inst, WhichOperand which) {
411 // Decode the given instruction, and return the address of
412 // an embedded 32-bit operand word.
414 // If "which" is disp32_operand, selects the displacement portion
415 // of an effective address specifier.
416 // If "which" is imm64_operand, selects the trailing immediate constant.
417 // If "which" is call32_operand, selects the displacement of a call or jump.
418 // Caller is responsible for ensuring that there is such an operand,
419 // and that it is 32/64 bits wide.
421 // If "which" is end_pc_operand, find the end of the instruction.
423 address ip = inst;
424 bool is_64bit = false;
426 debug_only(bool has_disp32 = false);
427 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
429 again_after_prefix:
430 switch (0xFF & *ip++) {
432 // These convenience macros generate groups of "case" labels for the switch.
433 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
434 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
435 case (x)+4: case (x)+5: case (x)+6: case (x)+7
436 #define REP16(x) REP8((x)+0): \
437 case REP8((x)+8)
439 case CS_segment:
440 case SS_segment:
441 case DS_segment:
442 case ES_segment:
443 case FS_segment:
444 case GS_segment:
445 // Seems dubious
446 LP64_ONLY(assert(false, "shouldn't have that prefix"));
447 assert(ip == inst+1, "only one prefix allowed");
448 goto again_after_prefix;
450 case 0x67:
451 case REX:
452 case REX_B:
453 case REX_X:
454 case REX_XB:
455 case REX_R:
456 case REX_RB:
457 case REX_RX:
458 case REX_RXB:
459 NOT_LP64(assert(false, "64bit prefixes"));
460 goto again_after_prefix;
462 case REX_W:
463 case REX_WB:
464 case REX_WX:
465 case REX_WXB:
466 case REX_WR:
467 case REX_WRB:
468 case REX_WRX:
469 case REX_WRXB:
470 NOT_LP64(assert(false, "64bit prefixes"));
471 is_64bit = true;
472 goto again_after_prefix;
474 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
475 case 0x88: // movb a, r
476 case 0x89: // movl a, r
477 case 0x8A: // movb r, a
478 case 0x8B: // movl r, a
479 case 0x8F: // popl a
480 debug_only(has_disp32 = true);
481 break;
483 case 0x68: // pushq #32
484 if (which == end_pc_operand) {
485 return ip + 4;
486 }
487 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
488 return ip; // not produced by emit_operand
490 case 0x66: // movw ... (size prefix)
491 again_after_size_prefix2:
492 switch (0xFF & *ip++) {
493 case REX:
494 case REX_B:
495 case REX_X:
496 case REX_XB:
497 case REX_R:
498 case REX_RB:
499 case REX_RX:
500 case REX_RXB:
501 case REX_W:
502 case REX_WB:
503 case REX_WX:
504 case REX_WXB:
505 case REX_WR:
506 case REX_WRB:
507 case REX_WRX:
508 case REX_WRXB:
509 NOT_LP64(assert(false, "64bit prefix found"));
510 goto again_after_size_prefix2;
511 case 0x8B: // movw r, a
512 case 0x89: // movw a, r
513 debug_only(has_disp32 = true);
514 break;
515 case 0xC7: // movw a, #16
516 debug_only(has_disp32 = true);
517 tail_size = 2; // the imm16
518 break;
519 case 0x0F: // several SSE/SSE2 variants
520 ip--; // reparse the 0x0F
521 goto again_after_prefix;
522 default:
523 ShouldNotReachHere();
524 }
525 break;
527 case REP8(0xB8): // movl/q r, #32/#64(oop?)
528 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
529 // these asserts are somewhat nonsensical
530 #ifndef _LP64
531 assert(which == imm_operand || which == disp32_operand,
532 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
533 #else
534 assert((which == call32_operand || which == imm_operand) && is_64bit ||
535 which == narrow_oop_operand && !is_64bit,
536 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip));
537 #endif // _LP64
538 return ip;
540 case 0x69: // imul r, a, #32
541 case 0xC7: // movl a, #32(oop?)
542 tail_size = 4;
543 debug_only(has_disp32 = true); // has both kinds of operands!
544 break;
546 case 0x0F: // movx..., etc.
547 switch (0xFF & *ip++) {
548 case 0x3A: // pcmpestri
549 tail_size = 1;
550 case 0x38: // ptest, pmovzxbw
551 ip++; // skip opcode
552 debug_only(has_disp32 = true); // has both kinds of operands!
553 break;
555 case 0x70: // pshufd r, r/a, #8
556 debug_only(has_disp32 = true); // has both kinds of operands!
557 case 0x73: // psrldq r, #8
558 tail_size = 1;
559 break;
561 case 0x12: // movlps
562 case 0x28: // movaps
563 case 0x2E: // ucomiss
564 case 0x2F: // comiss
565 case 0x54: // andps
566 case 0x55: // andnps
567 case 0x56: // orps
568 case 0x57: // xorps
569 case 0x6E: // movd
570 case 0x7E: // movd
571 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
572 debug_only(has_disp32 = true);
573 break;
575 case 0xAD: // shrd r, a, %cl
576 case 0xAF: // imul r, a
577 case 0xBE: // movsbl r, a (movsxb)
578 case 0xBF: // movswl r, a (movsxw)
579 case 0xB6: // movzbl r, a (movzxb)
580 case 0xB7: // movzwl r, a (movzxw)
581 case REP16(0x40): // cmovl cc, r, a
582 case 0xB0: // cmpxchgb
583 case 0xB1: // cmpxchg
584 case 0xC1: // xaddl
585 case 0xC7: // cmpxchg8
586 case REP16(0x90): // setcc a
587 debug_only(has_disp32 = true);
588 // fall out of the switch to decode the address
589 break;
591 case 0xC4: // pinsrw r, a, #8
592 debug_only(has_disp32 = true);
593 case 0xC5: // pextrw r, r, #8
594 tail_size = 1; // the imm8
595 break;
597 case 0xAC: // shrd r, a, #8
598 debug_only(has_disp32 = true);
599 tail_size = 1; // the imm8
600 break;
602 case REP16(0x80): // jcc rdisp32
603 if (which == end_pc_operand) return ip + 4;
604 assert(which == call32_operand, "jcc has no disp32 or imm");
605 return ip;
606 default:
607 ShouldNotReachHere();
608 }
609 break;
611 case 0x81: // addl a, #32; addl r, #32
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 // on 32bit in the case of cmpl, the imm might be an oop
614 tail_size = 4;
615 debug_only(has_disp32 = true); // has both kinds of operands!
616 break;
618 case 0x83: // addl a, #8; addl r, #8
619 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
620 debug_only(has_disp32 = true); // has both kinds of operands!
621 tail_size = 1;
622 break;
624 case 0x9B:
625 switch (0xFF & *ip++) {
626 case 0xD9: // fnstcw a
627 debug_only(has_disp32 = true);
628 break;
629 default:
630 ShouldNotReachHere();
631 }
632 break;
634 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
635 case REP4(0x10): // adc...
636 case REP4(0x20): // and...
637 case REP4(0x30): // xor...
638 case REP4(0x08): // or...
639 case REP4(0x18): // sbb...
640 case REP4(0x28): // sub...
641 case 0xF7: // mull a
642 case 0x8D: // lea r, a
643 case 0x87: // xchg r, a
644 case REP4(0x38): // cmp...
645 case 0x85: // test r, a
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 break;
649 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
650 case 0xC6: // movb a, #8
651 case 0x80: // cmpb a, #8
652 case 0x6B: // imul r, a, #8
653 debug_only(has_disp32 = true); // has both kinds of operands!
654 tail_size = 1; // the imm8
655 break;
657 case 0xC4: // VEX_3bytes
658 case 0xC5: // VEX_2bytes
659 assert((UseAVX > 0), "shouldn't have VEX prefix");
660 assert(ip == inst+1, "no prefixes allowed");
661 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
662 // but they have prefix 0x0F and processed when 0x0F processed above.
663 //
664 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
665 // instructions (these instructions are not supported in 64-bit mode).
666 // To distinguish them bits [7:6] are set in the VEX second byte since
667 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
668 // those VEX bits REX and vvvv bits are inverted.
669 //
670 // Fortunately C2 doesn't generate these instructions so we don't need
671 // to check for them in product version.
673 // Check second byte
674 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
676 // First byte
677 if ((0xFF & *inst) == VEX_3bytes) {
678 ip++; // third byte
679 is_64bit = ((VEX_W & *ip) == VEX_W);
680 }
681 ip++; // opcode
682 // To find the end of instruction (which == end_pc_operand).
683 switch (0xFF & *ip) {
684 case 0x61: // pcmpestri r, r/a, #8
685 case 0x70: // pshufd r, r/a, #8
686 case 0x73: // psrldq r, #8
687 tail_size = 1; // the imm8
688 break;
689 default:
690 break;
691 }
692 ip++; // skip opcode
693 debug_only(has_disp32 = true); // has both kinds of operands!
694 break;
696 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
697 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
698 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
699 case 0xDD: // fld_d a; fst_d a; fstp_d a
700 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
701 case 0xDF: // fild_d a; fistp_d a
702 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
703 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
704 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
705 debug_only(has_disp32 = true);
706 break;
708 case 0xE8: // call rdisp32
709 case 0xE9: // jmp rdisp32
710 if (which == end_pc_operand) return ip + 4;
711 assert(which == call32_operand, "call has no disp32 or imm");
712 return ip;
714 case 0xF0: // Lock
715 assert(os::is_MP(), "only on MP");
716 goto again_after_prefix;
718 case 0xF3: // For SSE
719 case 0xF2: // For SSE2
720 switch (0xFF & *ip++) {
721 case REX:
722 case REX_B:
723 case REX_X:
724 case REX_XB:
725 case REX_R:
726 case REX_RB:
727 case REX_RX:
728 case REX_RXB:
729 case REX_W:
730 case REX_WB:
731 case REX_WX:
732 case REX_WXB:
733 case REX_WR:
734 case REX_WRB:
735 case REX_WRX:
736 case REX_WRXB:
737 NOT_LP64(assert(false, "found 64bit prefix"));
738 ip++;
739 default:
740 ip++;
741 }
742 debug_only(has_disp32 = true); // has both kinds of operands!
743 break;
745 default:
746 ShouldNotReachHere();
748 #undef REP8
749 #undef REP16
750 }
752 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
753 #ifdef _LP64
754 assert(which != imm_operand, "instruction is not a movq reg, imm64");
755 #else
756 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
757 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
758 #endif // LP64
759 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
761 // parse the output of emit_operand
762 int op2 = 0xFF & *ip++;
763 int base = op2 & 0x07;
764 int op3 = -1;
765 const int b100 = 4;
766 const int b101 = 5;
767 if (base == b100 && (op2 >> 6) != 3) {
768 op3 = 0xFF & *ip++;
769 base = op3 & 0x07; // refetch the base
770 }
771 // now ip points at the disp (if any)
773 switch (op2 >> 6) {
774 case 0:
775 // [00 reg 100][ss index base]
776 // [00 reg 100][00 100 esp]
777 // [00 reg base]
778 // [00 reg 100][ss index 101][disp32]
779 // [00 reg 101] [disp32]
781 if (base == b101) {
782 if (which == disp32_operand)
783 return ip; // caller wants the disp32
784 ip += 4; // skip the disp32
785 }
786 break;
788 case 1:
789 // [01 reg 100][ss index base][disp8]
790 // [01 reg 100][00 100 esp][disp8]
791 // [01 reg base] [disp8]
792 ip += 1; // skip the disp8
793 break;
795 case 2:
796 // [10 reg 100][ss index base][disp32]
797 // [10 reg 100][00 100 esp][disp32]
798 // [10 reg base] [disp32]
799 if (which == disp32_operand)
800 return ip; // caller wants the disp32
801 ip += 4; // skip the disp32
802 break;
804 case 3:
805 // [11 reg base] (not a memory addressing mode)
806 break;
807 }
809 if (which == end_pc_operand) {
810 return ip + tail_size;
811 }
813 #ifdef _LP64
814 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
815 #else
816 assert(which == imm_operand, "instruction has only an imm field");
817 #endif // LP64
818 return ip;
819 }
821 address Assembler::locate_next_instruction(address inst) {
822 // Secretly share code with locate_operand:
823 return locate_operand(inst, end_pc_operand);
824 }
827 #ifdef ASSERT
828 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
829 address inst = inst_mark();
830 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
831 address opnd;
833 Relocation* r = rspec.reloc();
834 if (r->type() == relocInfo::none) {
835 return;
836 } else if (r->is_call() || format == call32_operand) {
837 // assert(format == imm32_operand, "cannot specify a nonzero format");
838 opnd = locate_operand(inst, call32_operand);
839 } else if (r->is_data()) {
840 assert(format == imm_operand || format == disp32_operand
841 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
842 opnd = locate_operand(inst, (WhichOperand)format);
843 } else {
844 assert(format == imm_operand, "cannot specify a format");
845 return;
846 }
847 assert(opnd == pc(), "must put operand where relocs can find it");
848 }
849 #endif // ASSERT
851 void Assembler::emit_operand32(Register reg, Address adr) {
852 assert(reg->encoding() < 8, "no extended registers");
853 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
854 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
855 adr._rspec);
856 }
858 void Assembler::emit_operand(Register reg, Address adr,
859 int rip_relative_correction) {
860 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
861 adr._rspec,
862 rip_relative_correction);
863 }
865 void Assembler::emit_operand(XMMRegister reg, Address adr) {
866 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
867 adr._rspec);
868 }
870 // MMX operations
871 void Assembler::emit_operand(MMXRegister reg, Address adr) {
872 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
873 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
874 }
876 // work around gcc (3.2.1-7a) bug
877 void Assembler::emit_operand(Address adr, MMXRegister reg) {
878 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
879 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
880 }
883 void Assembler::emit_farith(int b1, int b2, int i) {
884 assert(isByte(b1) && isByte(b2), "wrong opcode");
885 assert(0 <= i && i < 8, "illegal stack offset");
886 emit_int8(b1);
887 emit_int8(b2 + i);
888 }
891 // Now the Assembler instructions (identical for 32/64 bits)
893 void Assembler::adcl(Address dst, int32_t imm32) {
894 InstructionMark im(this);
895 prefix(dst);
896 emit_arith_operand(0x81, rdx, dst, imm32);
897 }
899 void Assembler::adcl(Address dst, Register src) {
900 InstructionMark im(this);
901 prefix(dst, src);
902 emit_int8(0x11);
903 emit_operand(src, dst);
904 }
906 void Assembler::adcl(Register dst, int32_t imm32) {
907 prefix(dst);
908 emit_arith(0x81, 0xD0, dst, imm32);
909 }
911 void Assembler::adcl(Register dst, Address src) {
912 InstructionMark im(this);
913 prefix(src, dst);
914 emit_int8(0x13);
915 emit_operand(dst, src);
916 }
918 void Assembler::adcl(Register dst, Register src) {
919 (void) prefix_and_encode(dst->encoding(), src->encoding());
920 emit_arith(0x13, 0xC0, dst, src);
921 }
923 void Assembler::addl(Address dst, int32_t imm32) {
924 InstructionMark im(this);
925 prefix(dst);
926 emit_arith_operand(0x81, rax, dst, imm32);
927 }
929 void Assembler::addl(Address dst, Register src) {
930 InstructionMark im(this);
931 prefix(dst, src);
932 emit_int8(0x01);
933 emit_operand(src, dst);
934 }
936 void Assembler::addl(Register dst, int32_t imm32) {
937 prefix(dst);
938 emit_arith(0x81, 0xC0, dst, imm32);
939 }
941 void Assembler::addl(Register dst, Address src) {
942 InstructionMark im(this);
943 prefix(src, dst);
944 emit_int8(0x03);
945 emit_operand(dst, src);
946 }
948 void Assembler::addl(Register dst, Register src) {
949 (void) prefix_and_encode(dst->encoding(), src->encoding());
950 emit_arith(0x03, 0xC0, dst, src);
951 }
953 void Assembler::addr_nop_4() {
954 assert(UseAddressNop, "no CPU support");
955 // 4 bytes: NOP DWORD PTR [EAX+0]
956 emit_int8(0x0F);
957 emit_int8(0x1F);
958 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
959 emit_int8(0); // 8-bits offset (1 byte)
960 }
962 void Assembler::addr_nop_5() {
963 assert(UseAddressNop, "no CPU support");
964 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
965 emit_int8(0x0F);
966 emit_int8(0x1F);
967 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
968 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
969 emit_int8(0); // 8-bits offset (1 byte)
970 }
972 void Assembler::addr_nop_7() {
973 assert(UseAddressNop, "no CPU support");
974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
975 emit_int8(0x0F);
976 emit_int8(0x1F);
977 emit_int8((unsigned char)0x80);
978 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
979 emit_int32(0); // 32-bits offset (4 bytes)
980 }
982 void Assembler::addr_nop_8() {
983 assert(UseAddressNop, "no CPU support");
984 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
985 emit_int8(0x0F);
986 emit_int8(0x1F);
987 emit_int8((unsigned char)0x84);
988 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
989 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
990 emit_int32(0); // 32-bits offset (4 bytes)
991 }
993 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
995 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
996 }
998 void Assembler::addsd(XMMRegister dst, Address src) {
999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1000 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
1001 }
1003 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1005 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1006 }
1008 void Assembler::addss(XMMRegister dst, Address src) {
1009 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1010 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1011 }
1013 void Assembler::aesdec(XMMRegister dst, Address src) {
1014 assert(VM_Version::supports_aes(), "");
1015 InstructionMark im(this);
1016 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_operand(dst, src);
1019 }
1021 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1022 assert(VM_Version::supports_aes(), "");
1023 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1024 emit_int8((unsigned char)0xDE);
1025 emit_int8(0xC0 | encode);
1026 }
1028 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1029 assert(VM_Version::supports_aes(), "");
1030 InstructionMark im(this);
1031 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_operand(dst, src);
1034 }
1036 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1037 assert(VM_Version::supports_aes(), "");
1038 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1039 emit_int8((unsigned char)0xDF);
1040 emit_int8((unsigned char)(0xC0 | encode));
1041 }
1043 void Assembler::aesenc(XMMRegister dst, Address src) {
1044 assert(VM_Version::supports_aes(), "");
1045 InstructionMark im(this);
1046 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_operand(dst, src);
1049 }
1051 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1052 assert(VM_Version::supports_aes(), "");
1053 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1054 emit_int8((unsigned char)0xDC);
1055 emit_int8(0xC0 | encode);
1056 }
1058 void Assembler::aesenclast(XMMRegister dst, Address src) {
1059 assert(VM_Version::supports_aes(), "");
1060 InstructionMark im(this);
1061 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_operand(dst, src);
1064 }
1066 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1067 assert(VM_Version::supports_aes(), "");
1068 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1069 emit_int8((unsigned char)0xDD);
1070 emit_int8((unsigned char)(0xC0 | encode));
1071 }
1074 void Assembler::andl(Address dst, int32_t imm32) {
1075 InstructionMark im(this);
1076 prefix(dst);
1077 emit_int8((unsigned char)0x81);
1078 emit_operand(rsp, dst, 4);
1079 emit_int32(imm32);
1080 }
1082 void Assembler::andl(Register dst, int32_t imm32) {
1083 prefix(dst);
1084 emit_arith(0x81, 0xE0, dst, imm32);
1085 }
1087 void Assembler::andl(Register dst, Address src) {
1088 InstructionMark im(this);
1089 prefix(src, dst);
1090 emit_int8(0x23);
1091 emit_operand(dst, src);
1092 }
1094 void Assembler::andl(Register dst, Register src) {
1095 (void) prefix_and_encode(dst->encoding(), src->encoding());
1096 emit_arith(0x23, 0xC0, dst, src);
1097 }
1099 void Assembler::bsfl(Register dst, Register src) {
1100 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1101 emit_int8(0x0F);
1102 emit_int8((unsigned char)0xBC);
1103 emit_int8((unsigned char)(0xC0 | encode));
1104 }
1106 void Assembler::bsrl(Register dst, Register src) {
1107 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBD);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1114 void Assembler::bswapl(Register reg) { // bswap
1115 int encode = prefix_and_encode(reg->encoding());
1116 emit_int8(0x0F);
1117 emit_int8((unsigned char)(0xC8 | encode));
1118 }
1120 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1121 // suspect disp32 is always good
1122 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1124 if (L.is_bound()) {
1125 const int long_size = 5;
1126 int offs = (int)( target(L) - pc() );
1127 assert(offs <= 0, "assembler error");
1128 InstructionMark im(this);
1129 // 1110 1000 #32-bit disp
1130 emit_int8((unsigned char)0xE8);
1131 emit_data(offs - long_size, rtype, operand);
1132 } else {
1133 InstructionMark im(this);
1134 // 1110 1000 #32-bit disp
1135 L.add_patch_at(code(), locator());
1137 emit_int8((unsigned char)0xE8);
1138 emit_data(int(0), rtype, operand);
1139 }
1140 }
1142 void Assembler::call(Register dst) {
1143 int encode = prefix_and_encode(dst->encoding());
1144 emit_int8((unsigned char)0xFF);
1145 emit_int8((unsigned char)(0xD0 | encode));
1146 }
1149 void Assembler::call(Address adr) {
1150 InstructionMark im(this);
1151 prefix(adr);
1152 emit_int8((unsigned char)0xFF);
1153 emit_operand(rdx, adr);
1154 }
1156 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1157 assert(entry != NULL, "call most probably wrong");
1158 InstructionMark im(this);
1159 emit_int8((unsigned char)0xE8);
1160 intptr_t disp = entry - (pc() + sizeof(int32_t));
1161 assert(is_simm32(disp), "must be 32bit offset (call2)");
1162 // Technically, should use call32_operand, but this format is
1163 // implied by the fact that we're emitting a call instruction.
1165 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1166 emit_data((int) disp, rspec, operand);
1167 }
1169 void Assembler::cdql() {
1170 emit_int8((unsigned char)0x99);
1171 }
1173 void Assembler::cld() {
1174 emit_int8((unsigned char)0xFC);
1175 }
1177 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1178 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1179 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1180 emit_int8(0x0F);
1181 emit_int8(0x40 | cc);
1182 emit_int8((unsigned char)(0xC0 | encode));
1183 }
1186 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1187 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1188 prefix(src, dst);
1189 emit_int8(0x0F);
1190 emit_int8(0x40 | cc);
1191 emit_operand(dst, src);
1192 }
1194 void Assembler::cmpb(Address dst, int imm8) {
1195 InstructionMark im(this);
1196 prefix(dst);
1197 emit_int8((unsigned char)0x80);
1198 emit_operand(rdi, dst, 1);
1199 emit_int8(imm8);
1200 }
1202 void Assembler::cmpl(Address dst, int32_t imm32) {
1203 InstructionMark im(this);
1204 prefix(dst);
1205 emit_int8((unsigned char)0x81);
1206 emit_operand(rdi, dst, 4);
1207 emit_int32(imm32);
1208 }
1210 void Assembler::cmpl(Register dst, int32_t imm32) {
1211 prefix(dst);
1212 emit_arith(0x81, 0xF8, dst, imm32);
1213 }
1215 void Assembler::cmpl(Register dst, Register src) {
1216 (void) prefix_and_encode(dst->encoding(), src->encoding());
1217 emit_arith(0x3B, 0xC0, dst, src);
1218 }
1221 void Assembler::cmpl(Register dst, Address src) {
1222 InstructionMark im(this);
1223 prefix(src, dst);
1224 emit_int8((unsigned char)0x3B);
1225 emit_operand(dst, src);
1226 }
1228 void Assembler::cmpw(Address dst, int imm16) {
1229 InstructionMark im(this);
1230 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1231 emit_int8(0x66);
1232 emit_int8((unsigned char)0x81);
1233 emit_operand(rdi, dst, 2);
1234 emit_int16(imm16);
1235 }
1237 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1238 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1239 // The ZF is set if the compared values were equal, and cleared otherwise.
1240 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1241 InstructionMark im(this);
1242 prefix(adr, reg);
1243 emit_int8(0x0F);
1244 emit_int8((unsigned char)0xB1);
1245 emit_operand(reg, adr);
1246 }
1248 void Assembler::comisd(XMMRegister dst, Address src) {
1249 // NOTE: dbx seems to decode this as comiss even though the
1250 // 0x66 is there. Strangly ucomisd comes out correct
1251 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1252 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1253 }
1255 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1257 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1258 }
1260 void Assembler::comiss(XMMRegister dst, Address src) {
1261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1262 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1263 }
1265 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1266 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1267 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1268 }
1270 void Assembler::cpuid() {
1271 emit_int8(0x0F);
1272 emit_int8((unsigned char)0xA2);
1273 }
1275 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1277 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1278 }
1280 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1281 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1282 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1283 }
1285 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1286 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1287 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1288 }
1290 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1292 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1293 }
1295 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1298 emit_int8(0x2A);
1299 emit_int8((unsigned char)(0xC0 | encode));
1300 }
1302 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1303 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1304 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1305 }
1307 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1308 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1309 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1310 emit_int8(0x2A);
1311 emit_int8((unsigned char)(0xC0 | encode));
1312 }
1314 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1315 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1316 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1317 }
1319 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1321 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1322 }
1324 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1326 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1327 }
1330 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1331 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1332 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1333 emit_int8(0x2C);
1334 emit_int8((unsigned char)(0xC0 | encode));
1335 }
1337 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1338 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1339 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1340 emit_int8(0x2C);
1341 emit_int8((unsigned char)(0xC0 | encode));
1342 }
1344 void Assembler::decl(Address dst) {
1345 // Don't use it directly. Use MacroAssembler::decrement() instead.
1346 InstructionMark im(this);
1347 prefix(dst);
1348 emit_int8((unsigned char)0xFF);
1349 emit_operand(rcx, dst);
1350 }
1352 void Assembler::divsd(XMMRegister dst, Address src) {
1353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1354 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1355 }
1357 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1358 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1359 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1360 }
1362 void Assembler::divss(XMMRegister dst, Address src) {
1363 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1364 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1365 }
1367 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1368 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1369 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1370 }
1372 void Assembler::emms() {
1373 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1374 emit_int8(0x0F);
1375 emit_int8(0x77);
1376 }
1378 void Assembler::hlt() {
1379 emit_int8((unsigned char)0xF4);
1380 }
1382 void Assembler::idivl(Register src) {
1383 int encode = prefix_and_encode(src->encoding());
1384 emit_int8((unsigned char)0xF7);
1385 emit_int8((unsigned char)(0xF8 | encode));
1386 }
1388 void Assembler::divl(Register src) { // Unsigned
1389 int encode = prefix_and_encode(src->encoding());
1390 emit_int8((unsigned char)0xF7);
1391 emit_int8((unsigned char)(0xF0 | encode));
1392 }
1394 void Assembler::imull(Register dst, Register src) {
1395 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1396 emit_int8(0x0F);
1397 emit_int8((unsigned char)0xAF);
1398 emit_int8((unsigned char)(0xC0 | encode));
1399 }
1402 void Assembler::imull(Register dst, Register src, int value) {
1403 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1404 if (is8bit(value)) {
1405 emit_int8(0x6B);
1406 emit_int8((unsigned char)(0xC0 | encode));
1407 emit_int8(value & 0xFF);
1408 } else {
1409 emit_int8(0x69);
1410 emit_int8((unsigned char)(0xC0 | encode));
1411 emit_int32(value);
1412 }
1413 }
1415 void Assembler::incl(Address dst) {
1416 // Don't use it directly. Use MacroAssembler::increment() instead.
1417 InstructionMark im(this);
1418 prefix(dst);
1419 emit_int8((unsigned char)0xFF);
1420 emit_operand(rax, dst);
1421 }
1423 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1424 InstructionMark im(this);
1425 assert((0 <= cc) && (cc < 16), "illegal cc");
1426 if (L.is_bound()) {
1427 address dst = target(L);
1428 assert(dst != NULL, "jcc most probably wrong");
1430 const int short_size = 2;
1431 const int long_size = 6;
1432 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1433 if (maybe_short && is8bit(offs - short_size)) {
1434 // 0111 tttn #8-bit disp
1435 emit_int8(0x70 | cc);
1436 emit_int8((offs - short_size) & 0xFF);
1437 } else {
1438 // 0000 1111 1000 tttn #32-bit disp
1439 assert(is_simm32(offs - long_size),
1440 "must be 32bit offset (call4)");
1441 emit_int8(0x0F);
1442 emit_int8((unsigned char)(0x80 | cc));
1443 emit_int32(offs - long_size);
1444 }
1445 } else {
1446 // Note: could eliminate cond. jumps to this jump if condition
1447 // is the same however, seems to be rather unlikely case.
1448 // Note: use jccb() if label to be bound is very close to get
1449 // an 8-bit displacement
1450 L.add_patch_at(code(), locator());
1451 emit_int8(0x0F);
1452 emit_int8((unsigned char)(0x80 | cc));
1453 emit_int32(0);
1454 }
1455 }
1457 void Assembler::jccb(Condition cc, Label& L) {
1458 if (L.is_bound()) {
1459 const int short_size = 2;
1460 address entry = target(L);
1461 #ifdef ASSERT
1462 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1463 intptr_t delta = short_branch_delta();
1464 if (delta != 0) {
1465 dist += (dist < 0 ? (-delta) :delta);
1466 }
1467 assert(is8bit(dist), "Dispacement too large for a short jmp");
1468 #endif
1469 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1470 // 0111 tttn #8-bit disp
1471 emit_int8(0x70 | cc);
1472 emit_int8((offs - short_size) & 0xFF);
1473 } else {
1474 InstructionMark im(this);
1475 L.add_patch_at(code(), locator());
1476 emit_int8(0x70 | cc);
1477 emit_int8(0);
1478 }
1479 }
1481 void Assembler::jmp(Address adr) {
1482 InstructionMark im(this);
1483 prefix(adr);
1484 emit_int8((unsigned char)0xFF);
1485 emit_operand(rsp, adr);
1486 }
1488 void Assembler::jmp(Label& L, bool maybe_short) {
1489 if (L.is_bound()) {
1490 address entry = target(L);
1491 assert(entry != NULL, "jmp most probably wrong");
1492 InstructionMark im(this);
1493 const int short_size = 2;
1494 const int long_size = 5;
1495 intptr_t offs = entry - pc();
1496 if (maybe_short && is8bit(offs - short_size)) {
1497 emit_int8((unsigned char)0xEB);
1498 emit_int8((offs - short_size) & 0xFF);
1499 } else {
1500 emit_int8((unsigned char)0xE9);
1501 emit_int32(offs - long_size);
1502 }
1503 } else {
1504 // By default, forward jumps are always 32-bit displacements, since
1505 // we can't yet know where the label will be bound. If you're sure that
1506 // the forward jump will not run beyond 256 bytes, use jmpb to
1507 // force an 8-bit displacement.
1508 InstructionMark im(this);
1509 L.add_patch_at(code(), locator());
1510 emit_int8((unsigned char)0xE9);
1511 emit_int32(0);
1512 }
1513 }
1515 void Assembler::jmp(Register entry) {
1516 int encode = prefix_and_encode(entry->encoding());
1517 emit_int8((unsigned char)0xFF);
1518 emit_int8((unsigned char)(0xE0 | encode));
1519 }
1521 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1522 InstructionMark im(this);
1523 emit_int8((unsigned char)0xE9);
1524 assert(dest != NULL, "must have a target");
1525 intptr_t disp = dest - (pc() + sizeof(int32_t));
1526 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1527 emit_data(disp, rspec.reloc(), call32_operand);
1528 }
1530 void Assembler::jmpb(Label& L) {
1531 if (L.is_bound()) {
1532 const int short_size = 2;
1533 address entry = target(L);
1534 assert(entry != NULL, "jmp most probably wrong");
1535 #ifdef ASSERT
1536 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1537 intptr_t delta = short_branch_delta();
1538 if (delta != 0) {
1539 dist += (dist < 0 ? (-delta) :delta);
1540 }
1541 assert(is8bit(dist), "Dispacement too large for a short jmp");
1542 #endif
1543 intptr_t offs = entry - pc();
1544 emit_int8((unsigned char)0xEB);
1545 emit_int8((offs - short_size) & 0xFF);
1546 } else {
1547 InstructionMark im(this);
1548 L.add_patch_at(code(), locator());
1549 emit_int8((unsigned char)0xEB);
1550 emit_int8(0);
1551 }
1552 }
1554 void Assembler::ldmxcsr( Address src) {
1555 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1556 InstructionMark im(this);
1557 prefix(src);
1558 emit_int8(0x0F);
1559 emit_int8((unsigned char)0xAE);
1560 emit_operand(as_Register(2), src);
1561 }
1563 void Assembler::leal(Register dst, Address src) {
1564 InstructionMark im(this);
1565 #ifdef _LP64
1566 emit_int8(0x67); // addr32
1567 prefix(src, dst);
1568 #endif // LP64
1569 emit_int8((unsigned char)0x8D);
1570 emit_operand(dst, src);
1571 }
1573 void Assembler::lfence() {
1574 emit_int8(0x0F);
1575 emit_int8((unsigned char)0xAE);
1576 emit_int8((unsigned char)0xE8);
1577 }
1579 void Assembler::lock() {
1580 emit_int8((unsigned char)0xF0);
1581 }
1583 void Assembler::lzcntl(Register dst, Register src) {
1584 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1585 emit_int8((unsigned char)0xF3);
1586 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1587 emit_int8(0x0F);
1588 emit_int8((unsigned char)0xBD);
1589 emit_int8((unsigned char)(0xC0 | encode));
1590 }
1592 // Emit mfence instruction
1593 void Assembler::mfence() {
1594 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1595 emit_int8(0x0F);
1596 emit_int8((unsigned char)0xAE);
1597 emit_int8((unsigned char)0xF0);
1598 }
1600 void Assembler::mov(Register dst, Register src) {
1601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1602 }
1604 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1607 }
1609 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1610 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1611 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1612 }
1614 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1615 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1616 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1617 emit_int8(0x16);
1618 emit_int8((unsigned char)(0xC0 | encode));
1619 }
1621 void Assembler::movb(Register dst, Address src) {
1622 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1623 InstructionMark im(this);
1624 prefix(src, dst, true);
1625 emit_int8((unsigned char)0x8A);
1626 emit_operand(dst, src);
1627 }
1630 void Assembler::movb(Address dst, int imm8) {
1631 InstructionMark im(this);
1632 prefix(dst);
1633 emit_int8((unsigned char)0xC6);
1634 emit_operand(rax, dst, 1);
1635 emit_int8(imm8);
1636 }
1639 void Assembler::movb(Address dst, Register src) {
1640 assert(src->has_byte_register(), "must have byte register");
1641 InstructionMark im(this);
1642 prefix(dst, src, true);
1643 emit_int8((unsigned char)0x88);
1644 emit_operand(src, dst);
1645 }
1647 void Assembler::movdl(XMMRegister dst, Register src) {
1648 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1649 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1650 emit_int8(0x6E);
1651 emit_int8((unsigned char)(0xC0 | encode));
1652 }
1654 void Assembler::movdl(Register dst, XMMRegister src) {
1655 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1656 // swap src/dst to get correct prefix
1657 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1658 emit_int8(0x7E);
1659 emit_int8((unsigned char)(0xC0 | encode));
1660 }
1662 void Assembler::movdl(XMMRegister dst, Address src) {
1663 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1664 InstructionMark im(this);
1665 simd_prefix(dst, src, VEX_SIMD_66);
1666 emit_int8(0x6E);
1667 emit_operand(dst, src);
1668 }
1670 void Assembler::movdl(Address dst, XMMRegister src) {
1671 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1672 InstructionMark im(this);
1673 simd_prefix(dst, src, VEX_SIMD_66);
1674 emit_int8(0x7E);
1675 emit_operand(src, dst);
1676 }
1678 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1679 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1680 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1681 }
1683 void Assembler::movdqu(XMMRegister dst, Address src) {
1684 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1685 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1686 }
1688 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1689 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1690 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1691 }
1693 void Assembler::movdqu(Address dst, XMMRegister src) {
1694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1695 InstructionMark im(this);
1696 simd_prefix(dst, src, VEX_SIMD_F3);
1697 emit_int8(0x7F);
1698 emit_operand(src, dst);
1699 }
1701 // Move Unaligned 256bit Vector
1702 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1703 assert(UseAVX, "");
1704 bool vector256 = true;
1705 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1706 emit_int8(0x6F);
1707 emit_int8((unsigned char)(0xC0 | encode));
1708 }
1710 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1711 assert(UseAVX, "");
1712 InstructionMark im(this);
1713 bool vector256 = true;
1714 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1715 emit_int8(0x6F);
1716 emit_operand(dst, src);
1717 }
1719 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1720 assert(UseAVX, "");
1721 InstructionMark im(this);
1722 bool vector256 = true;
1723 // swap src<->dst for encoding
1724 assert(src != xnoreg, "sanity");
1725 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1726 emit_int8(0x7F);
1727 emit_operand(src, dst);
1728 }
1730 // Uses zero extension on 64bit
1732 void Assembler::movl(Register dst, int32_t imm32) {
1733 int encode = prefix_and_encode(dst->encoding());
1734 emit_int8((unsigned char)(0xB8 | encode));
1735 emit_int32(imm32);
1736 }
1738 void Assembler::movl(Register dst, Register src) {
1739 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1740 emit_int8((unsigned char)0x8B);
1741 emit_int8((unsigned char)(0xC0 | encode));
1742 }
1744 void Assembler::movl(Register dst, Address src) {
1745 InstructionMark im(this);
1746 prefix(src, dst);
1747 emit_int8((unsigned char)0x8B);
1748 emit_operand(dst, src);
1749 }
1751 void Assembler::movl(Address dst, int32_t imm32) {
1752 InstructionMark im(this);
1753 prefix(dst);
1754 emit_int8((unsigned char)0xC7);
1755 emit_operand(rax, dst, 4);
1756 emit_int32(imm32);
1757 }
1759 void Assembler::movl(Address dst, Register src) {
1760 InstructionMark im(this);
1761 prefix(dst, src);
1762 emit_int8((unsigned char)0x89);
1763 emit_operand(src, dst);
1764 }
1766 // New cpus require to use movsd and movss to avoid partial register stall
1767 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1768 // The selection is done in MacroAssembler::movdbl() and movflt().
1769 void Assembler::movlpd(XMMRegister dst, Address src) {
1770 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1771 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1772 }
1774 void Assembler::movq( MMXRegister dst, Address src ) {
1775 assert( VM_Version::supports_mmx(), "" );
1776 emit_int8(0x0F);
1777 emit_int8(0x6F);
1778 emit_operand(dst, src);
1779 }
1781 void Assembler::movq( Address dst, MMXRegister src ) {
1782 assert( VM_Version::supports_mmx(), "" );
1783 emit_int8(0x0F);
1784 emit_int8(0x7F);
1785 // workaround gcc (3.2.1-7a) bug
1786 // In that version of gcc with only an emit_operand(MMX, Address)
1787 // gcc will tail jump and try and reverse the parameters completely
1788 // obliterating dst in the process. By having a version available
1789 // that doesn't need to swap the args at the tail jump the bug is
1790 // avoided.
1791 emit_operand(dst, src);
1792 }
1794 void Assembler::movq(XMMRegister dst, Address src) {
1795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1796 InstructionMark im(this);
1797 simd_prefix(dst, src, VEX_SIMD_F3);
1798 emit_int8(0x7E);
1799 emit_operand(dst, src);
1800 }
1802 void Assembler::movq(Address dst, XMMRegister src) {
1803 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1804 InstructionMark im(this);
1805 simd_prefix(dst, src, VEX_SIMD_66);
1806 emit_int8((unsigned char)0xD6);
1807 emit_operand(src, dst);
1808 }
1810 void Assembler::movsbl(Register dst, Address src) { // movsxb
1811 InstructionMark im(this);
1812 prefix(src, dst);
1813 emit_int8(0x0F);
1814 emit_int8((unsigned char)0xBE);
1815 emit_operand(dst, src);
1816 }
1818 void Assembler::movsbl(Register dst, Register src) { // movsxb
1819 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1820 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1821 emit_int8(0x0F);
1822 emit_int8((unsigned char)0xBE);
1823 emit_int8((unsigned char)(0xC0 | encode));
1824 }
1826 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1827 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1828 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1829 }
1831 void Assembler::movsd(XMMRegister dst, Address src) {
1832 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1833 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1834 }
1836 void Assembler::movsd(Address dst, XMMRegister src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 InstructionMark im(this);
1839 simd_prefix(dst, src, VEX_SIMD_F2);
1840 emit_int8(0x11);
1841 emit_operand(src, dst);
1842 }
1844 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1845 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1846 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1847 }
1849 void Assembler::movss(XMMRegister dst, Address src) {
1850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1851 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1852 }
1854 void Assembler::movss(Address dst, XMMRegister src) {
1855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1856 InstructionMark im(this);
1857 simd_prefix(dst, src, VEX_SIMD_F3);
1858 emit_int8(0x11);
1859 emit_operand(src, dst);
1860 }
1862 void Assembler::movswl(Register dst, Address src) { // movsxw
1863 InstructionMark im(this);
1864 prefix(src, dst);
1865 emit_int8(0x0F);
1866 emit_int8((unsigned char)0xBF);
1867 emit_operand(dst, src);
1868 }
1870 void Assembler::movswl(Register dst, Register src) { // movsxw
1871 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1872 emit_int8(0x0F);
1873 emit_int8((unsigned char)0xBF);
1874 emit_int8((unsigned char)(0xC0 | encode));
1875 }
1877 void Assembler::movw(Address dst, int imm16) {
1878 InstructionMark im(this);
1880 emit_int8(0x66); // switch to 16-bit mode
1881 prefix(dst);
1882 emit_int8((unsigned char)0xC7);
1883 emit_operand(rax, dst, 2);
1884 emit_int16(imm16);
1885 }
1887 void Assembler::movw(Register dst, Address src) {
1888 InstructionMark im(this);
1889 emit_int8(0x66);
1890 prefix(src, dst);
1891 emit_int8((unsigned char)0x8B);
1892 emit_operand(dst, src);
1893 }
1895 void Assembler::movw(Address dst, Register src) {
1896 InstructionMark im(this);
1897 emit_int8(0x66);
1898 prefix(dst, src);
1899 emit_int8((unsigned char)0x89);
1900 emit_operand(src, dst);
1901 }
1903 void Assembler::movzbl(Register dst, Address src) { // movzxb
1904 InstructionMark im(this);
1905 prefix(src, dst);
1906 emit_int8(0x0F);
1907 emit_int8((unsigned char)0xB6);
1908 emit_operand(dst, src);
1909 }
1911 void Assembler::movzbl(Register dst, Register src) { // movzxb
1912 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1913 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1914 emit_int8(0x0F);
1915 emit_int8((unsigned char)0xB6);
1916 emit_int8(0xC0 | encode);
1917 }
1919 void Assembler::movzwl(Register dst, Address src) { // movzxw
1920 InstructionMark im(this);
1921 prefix(src, dst);
1922 emit_int8(0x0F);
1923 emit_int8((unsigned char)0xB7);
1924 emit_operand(dst, src);
1925 }
1927 void Assembler::movzwl(Register dst, Register src) { // movzxw
1928 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1929 emit_int8(0x0F);
1930 emit_int8((unsigned char)0xB7);
1931 emit_int8(0xC0 | encode);
1932 }
1934 void Assembler::mull(Address src) {
1935 InstructionMark im(this);
1936 prefix(src);
1937 emit_int8((unsigned char)0xF7);
1938 emit_operand(rsp, src);
1939 }
1941 void Assembler::mull(Register src) {
1942 int encode = prefix_and_encode(src->encoding());
1943 emit_int8((unsigned char)0xF7);
1944 emit_int8((unsigned char)(0xE0 | encode));
1945 }
1947 void Assembler::mulsd(XMMRegister dst, Address src) {
1948 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1949 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1950 }
1952 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1953 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1954 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1955 }
1957 void Assembler::mulss(XMMRegister dst, Address src) {
1958 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1959 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1960 }
1962 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1963 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1964 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1965 }
1967 void Assembler::negl(Register dst) {
1968 int encode = prefix_and_encode(dst->encoding());
1969 emit_int8((unsigned char)0xF7);
1970 emit_int8((unsigned char)(0xD8 | encode));
1971 }
1973 void Assembler::nop(int i) {
1974 #ifdef ASSERT
1975 assert(i > 0, " ");
1976 // The fancy nops aren't currently recognized by debuggers making it a
1977 // pain to disassemble code while debugging. If asserts are on clearly
1978 // speed is not an issue so simply use the single byte traditional nop
1979 // to do alignment.
1981 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
1982 return;
1984 #endif // ASSERT
1986 if (UseAddressNop && VM_Version::is_intel()) {
1987 //
1988 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1989 // 1: 0x90
1990 // 2: 0x66 0x90
1991 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1992 // 4: 0x0F 0x1F 0x40 0x00
1993 // 5: 0x0F 0x1F 0x44 0x00 0x00
1994 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1995 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1996 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1997 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1998 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1999 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2001 // The rest coding is Intel specific - don't use consecutive address nops
2003 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2004 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2005 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2006 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2008 while(i >= 15) {
2009 // For Intel don't generate consecutive addess nops (mix with regular nops)
2010 i -= 15;
2011 emit_int8(0x66); // size prefix
2012 emit_int8(0x66); // size prefix
2013 emit_int8(0x66); // size prefix
2014 addr_nop_8();
2015 emit_int8(0x66); // size prefix
2016 emit_int8(0x66); // size prefix
2017 emit_int8(0x66); // size prefix
2018 emit_int8((unsigned char)0x90);
2019 // nop
2020 }
2021 switch (i) {
2022 case 14:
2023 emit_int8(0x66); // size prefix
2024 case 13:
2025 emit_int8(0x66); // size prefix
2026 case 12:
2027 addr_nop_8();
2028 emit_int8(0x66); // size prefix
2029 emit_int8(0x66); // size prefix
2030 emit_int8(0x66); // size prefix
2031 emit_int8((unsigned char)0x90);
2032 // nop
2033 break;
2034 case 11:
2035 emit_int8(0x66); // size prefix
2036 case 10:
2037 emit_int8(0x66); // size prefix
2038 case 9:
2039 emit_int8(0x66); // size prefix
2040 case 8:
2041 addr_nop_8();
2042 break;
2043 case 7:
2044 addr_nop_7();
2045 break;
2046 case 6:
2047 emit_int8(0x66); // size prefix
2048 case 5:
2049 addr_nop_5();
2050 break;
2051 case 4:
2052 addr_nop_4();
2053 break;
2054 case 3:
2055 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2056 emit_int8(0x66); // size prefix
2057 case 2:
2058 emit_int8(0x66); // size prefix
2059 case 1:
2060 emit_int8((unsigned char)0x90);
2061 // nop
2062 break;
2063 default:
2064 assert(i == 0, " ");
2065 }
2066 return;
2067 }
2068 if (UseAddressNop && VM_Version::is_amd()) {
2069 //
2070 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2071 // 1: 0x90
2072 // 2: 0x66 0x90
2073 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2074 // 4: 0x0F 0x1F 0x40 0x00
2075 // 5: 0x0F 0x1F 0x44 0x00 0x00
2076 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2077 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2078 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2079 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2080 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2081 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2083 // The rest coding is AMD specific - use consecutive address nops
2085 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2086 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2087 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2088 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2089 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2090 // Size prefixes (0x66) are added for larger sizes
2092 while(i >= 22) {
2093 i -= 11;
2094 emit_int8(0x66); // size prefix
2095 emit_int8(0x66); // size prefix
2096 emit_int8(0x66); // size prefix
2097 addr_nop_8();
2098 }
2099 // Generate first nop for size between 21-12
2100 switch (i) {
2101 case 21:
2102 i -= 1;
2103 emit_int8(0x66); // size prefix
2104 case 20:
2105 case 19:
2106 i -= 1;
2107 emit_int8(0x66); // size prefix
2108 case 18:
2109 case 17:
2110 i -= 1;
2111 emit_int8(0x66); // size prefix
2112 case 16:
2113 case 15:
2114 i -= 8;
2115 addr_nop_8();
2116 break;
2117 case 14:
2118 case 13:
2119 i -= 7;
2120 addr_nop_7();
2121 break;
2122 case 12:
2123 i -= 6;
2124 emit_int8(0x66); // size prefix
2125 addr_nop_5();
2126 break;
2127 default:
2128 assert(i < 12, " ");
2129 }
2131 // Generate second nop for size between 11-1
2132 switch (i) {
2133 case 11:
2134 emit_int8(0x66); // size prefix
2135 case 10:
2136 emit_int8(0x66); // size prefix
2137 case 9:
2138 emit_int8(0x66); // size prefix
2139 case 8:
2140 addr_nop_8();
2141 break;
2142 case 7:
2143 addr_nop_7();
2144 break;
2145 case 6:
2146 emit_int8(0x66); // size prefix
2147 case 5:
2148 addr_nop_5();
2149 break;
2150 case 4:
2151 addr_nop_4();
2152 break;
2153 case 3:
2154 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2155 emit_int8(0x66); // size prefix
2156 case 2:
2157 emit_int8(0x66); // size prefix
2158 case 1:
2159 emit_int8((unsigned char)0x90);
2160 // nop
2161 break;
2162 default:
2163 assert(i == 0, " ");
2164 }
2165 return;
2166 }
2168 // Using nops with size prefixes "0x66 0x90".
2169 // From AMD Optimization Guide:
2170 // 1: 0x90
2171 // 2: 0x66 0x90
2172 // 3: 0x66 0x66 0x90
2173 // 4: 0x66 0x66 0x66 0x90
2174 // 5: 0x66 0x66 0x90 0x66 0x90
2175 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2176 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2177 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2178 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2179 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2180 //
2181 while(i > 12) {
2182 i -= 4;
2183 emit_int8(0x66); // size prefix
2184 emit_int8(0x66);
2185 emit_int8(0x66);
2186 emit_int8((unsigned char)0x90);
2187 // nop
2188 }
2189 // 1 - 12 nops
2190 if(i > 8) {
2191 if(i > 9) {
2192 i -= 1;
2193 emit_int8(0x66);
2194 }
2195 i -= 3;
2196 emit_int8(0x66);
2197 emit_int8(0x66);
2198 emit_int8((unsigned char)0x90);
2199 }
2200 // 1 - 8 nops
2201 if(i > 4) {
2202 if(i > 6) {
2203 i -= 1;
2204 emit_int8(0x66);
2205 }
2206 i -= 3;
2207 emit_int8(0x66);
2208 emit_int8(0x66);
2209 emit_int8((unsigned char)0x90);
2210 }
2211 switch (i) {
2212 case 4:
2213 emit_int8(0x66);
2214 case 3:
2215 emit_int8(0x66);
2216 case 2:
2217 emit_int8(0x66);
2218 case 1:
2219 emit_int8((unsigned char)0x90);
2220 break;
2221 default:
2222 assert(i == 0, " ");
2223 }
2224 }
2226 void Assembler::notl(Register dst) {
2227 int encode = prefix_and_encode(dst->encoding());
2228 emit_int8((unsigned char)0xF7);
2229 emit_int8((unsigned char)(0xD0 | encode));
2230 }
2232 void Assembler::orl(Address dst, int32_t imm32) {
2233 InstructionMark im(this);
2234 prefix(dst);
2235 emit_arith_operand(0x81, rcx, dst, imm32);
2236 }
2238 void Assembler::orl(Register dst, int32_t imm32) {
2239 prefix(dst);
2240 emit_arith(0x81, 0xC8, dst, imm32);
2241 }
2243 void Assembler::orl(Register dst, Address src) {
2244 InstructionMark im(this);
2245 prefix(src, dst);
2246 emit_int8(0x0B);
2247 emit_operand(dst, src);
2248 }
2250 void Assembler::orl(Register dst, Register src) {
2251 (void) prefix_and_encode(dst->encoding(), src->encoding());
2252 emit_arith(0x0B, 0xC0, dst, src);
2253 }
2255 void Assembler::packuswb(XMMRegister dst, Address src) {
2256 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2257 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2258 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2259 }
2261 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2263 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2264 }
2266 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2267 assert(VM_Version::supports_sse4_2(), "");
2268 InstructionMark im(this);
2269 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2270 emit_int8(0x61);
2271 emit_operand(dst, src);
2272 emit_int8(imm8);
2273 }
2275 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2276 assert(VM_Version::supports_sse4_2(), "");
2277 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2278 emit_int8(0x61);
2279 emit_int8((unsigned char)(0xC0 | encode));
2280 emit_int8(imm8);
2281 }
2283 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2284 assert(VM_Version::supports_sse4_1(), "");
2285 InstructionMark im(this);
2286 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2287 emit_int8(0x30);
2288 emit_operand(dst, src);
2289 }
2291 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2292 assert(VM_Version::supports_sse4_1(), "");
2293 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2294 emit_int8(0x30);
2295 emit_int8((unsigned char)(0xC0 | encode));
2296 }
2298 // generic
2299 void Assembler::pop(Register dst) {
2300 int encode = prefix_and_encode(dst->encoding());
2301 emit_int8(0x58 | encode);
2302 }
2304 void Assembler::popcntl(Register dst, Address src) {
2305 assert(VM_Version::supports_popcnt(), "must support");
2306 InstructionMark im(this);
2307 emit_int8((unsigned char)0xF3);
2308 prefix(src, dst);
2309 emit_int8(0x0F);
2310 emit_int8((unsigned char)0xB8);
2311 emit_operand(dst, src);
2312 }
2314 void Assembler::popcntl(Register dst, Register src) {
2315 assert(VM_Version::supports_popcnt(), "must support");
2316 emit_int8((unsigned char)0xF3);
2317 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2318 emit_int8(0x0F);
2319 emit_int8((unsigned char)0xB8);
2320 emit_int8((unsigned char)(0xC0 | encode));
2321 }
2323 void Assembler::popf() {
2324 emit_int8((unsigned char)0x9D);
2325 }
2327 #ifndef _LP64 // no 32bit push/pop on amd64
2328 void Assembler::popl(Address dst) {
2329 // NOTE: this will adjust stack by 8byte on 64bits
2330 InstructionMark im(this);
2331 prefix(dst);
2332 emit_int8((unsigned char)0x8F);
2333 emit_operand(rax, dst);
2334 }
2335 #endif
2337 void Assembler::prefetch_prefix(Address src) {
2338 prefix(src);
2339 emit_int8(0x0F);
2340 }
2342 void Assembler::prefetchnta(Address src) {
2343 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2344 InstructionMark im(this);
2345 prefetch_prefix(src);
2346 emit_int8(0x18);
2347 emit_operand(rax, src); // 0, src
2348 }
2350 void Assembler::prefetchr(Address src) {
2351 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2352 InstructionMark im(this);
2353 prefetch_prefix(src);
2354 emit_int8(0x0D);
2355 emit_operand(rax, src); // 0, src
2356 }
2358 void Assembler::prefetcht0(Address src) {
2359 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2360 InstructionMark im(this);
2361 prefetch_prefix(src);
2362 emit_int8(0x18);
2363 emit_operand(rcx, src); // 1, src
2364 }
2366 void Assembler::prefetcht1(Address src) {
2367 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2368 InstructionMark im(this);
2369 prefetch_prefix(src);
2370 emit_int8(0x18);
2371 emit_operand(rdx, src); // 2, src
2372 }
2374 void Assembler::prefetcht2(Address src) {
2375 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2376 InstructionMark im(this);
2377 prefetch_prefix(src);
2378 emit_int8(0x18);
2379 emit_operand(rbx, src); // 3, src
2380 }
2382 void Assembler::prefetchw(Address src) {
2383 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2384 InstructionMark im(this);
2385 prefetch_prefix(src);
2386 emit_int8(0x0D);
2387 emit_operand(rcx, src); // 1, src
2388 }
2390 void Assembler::prefix(Prefix p) {
2391 emit_int8(p);
2392 }
2394 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2395 assert(VM_Version::supports_ssse3(), "");
2396 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2397 emit_int8(0x00);
2398 emit_int8((unsigned char)(0xC0 | encode));
2399 }
2401 void Assembler::pshufb(XMMRegister dst, Address src) {
2402 assert(VM_Version::supports_ssse3(), "");
2403 InstructionMark im(this);
2404 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2405 emit_int8(0x00);
2406 emit_operand(dst, src);
2407 }
2409 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2410 assert(isByte(mode), "invalid value");
2411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2412 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2413 emit_int8(mode & 0xFF);
2415 }
2417 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2418 assert(isByte(mode), "invalid value");
2419 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2420 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2421 InstructionMark im(this);
2422 simd_prefix(dst, src, VEX_SIMD_66);
2423 emit_int8(0x70);
2424 emit_operand(dst, src);
2425 emit_int8(mode & 0xFF);
2426 }
2428 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2429 assert(isByte(mode), "invalid value");
2430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2431 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2432 emit_int8(mode & 0xFF);
2433 }
2435 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2436 assert(isByte(mode), "invalid value");
2437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2438 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2439 InstructionMark im(this);
2440 simd_prefix(dst, src, VEX_SIMD_F2);
2441 emit_int8(0x70);
2442 emit_operand(dst, src);
2443 emit_int8(mode & 0xFF);
2444 }
2446 void Assembler::psrldq(XMMRegister dst, int shift) {
2447 // Shift 128 bit value in xmm register by number of bytes.
2448 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2449 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2450 emit_int8(0x73);
2451 emit_int8((unsigned char)(0xC0 | encode));
2452 emit_int8(shift);
2453 }
2455 void Assembler::ptest(XMMRegister dst, Address src) {
2456 assert(VM_Version::supports_sse4_1(), "");
2457 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2458 InstructionMark im(this);
2459 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2460 emit_int8(0x17);
2461 emit_operand(dst, src);
2462 }
2464 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2465 assert(VM_Version::supports_sse4_1(), "");
2466 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2467 emit_int8(0x17);
2468 emit_int8((unsigned char)(0xC0 | encode));
2469 }
2471 void Assembler::vptest(XMMRegister dst, Address src) {
2472 assert(VM_Version::supports_avx(), "");
2473 InstructionMark im(this);
2474 bool vector256 = true;
2475 assert(dst != xnoreg, "sanity");
2476 int dst_enc = dst->encoding();
2477 // swap src<->dst for encoding
2478 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2479 emit_int8(0x17);
2480 emit_operand(dst, src);
2481 }
2483 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2484 assert(VM_Version::supports_avx(), "");
2485 bool vector256 = true;
2486 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2487 emit_int8(0x17);
2488 emit_int8((unsigned char)(0xC0 | encode));
2489 }
2491 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2492 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2493 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2494 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2495 }
2497 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2499 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2500 }
2502 void Assembler::punpckldq(XMMRegister dst, Address src) {
2503 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2504 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2505 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2506 }
2508 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2510 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2511 }
2513 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2514 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2515 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2516 }
2518 void Assembler::push(int32_t imm32) {
2519 // in 64bits we push 64bits onto the stack but only
2520 // take a 32bit immediate
2521 emit_int8(0x68);
2522 emit_int32(imm32);
2523 }
2525 void Assembler::push(Register src) {
2526 int encode = prefix_and_encode(src->encoding());
2528 emit_int8(0x50 | encode);
2529 }
2531 void Assembler::pushf() {
2532 emit_int8((unsigned char)0x9C);
2533 }
2535 #ifndef _LP64 // no 32bit push/pop on amd64
2536 void Assembler::pushl(Address src) {
2537 // Note this will push 64bit on 64bit
2538 InstructionMark im(this);
2539 prefix(src);
2540 emit_int8((unsigned char)0xFF);
2541 emit_operand(rsi, src);
2542 }
2543 #endif
2545 void Assembler::rcll(Register dst, int imm8) {
2546 assert(isShiftCount(imm8), "illegal shift count");
2547 int encode = prefix_and_encode(dst->encoding());
2548 if (imm8 == 1) {
2549 emit_int8((unsigned char)0xD1);
2550 emit_int8((unsigned char)(0xD0 | encode));
2551 } else {
2552 emit_int8((unsigned char)0xC1);
2553 emit_int8((unsigned char)0xD0 | encode);
2554 emit_int8(imm8);
2555 }
2556 }
2558 // copies data from [esi] to [edi] using rcx pointer sized words
2559 // generic
2560 void Assembler::rep_mov() {
2561 emit_int8((unsigned char)0xF3);
2562 // MOVSQ
2563 LP64_ONLY(prefix(REX_W));
2564 emit_int8((unsigned char)0xA5);
2565 }
2567 // sets rcx bytes with rax, value at [edi]
2568 void Assembler::rep_stosb() {
2569 emit_int8((unsigned char)0xF3); // REP
2570 LP64_ONLY(prefix(REX_W));
2571 emit_int8((unsigned char)0xAA); // STOSB
2572 }
2574 // sets rcx pointer sized words with rax, value at [edi]
2575 // generic
2576 void Assembler::rep_stos() {
2577 emit_int8((unsigned char)0xF3); // REP
2578 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2579 emit_int8((unsigned char)0xAB);
2580 }
2582 // scans rcx pointer sized words at [edi] for occurance of rax,
2583 // generic
2584 void Assembler::repne_scan() { // repne_scan
2585 emit_int8((unsigned char)0xF2);
2586 // SCASQ
2587 LP64_ONLY(prefix(REX_W));
2588 emit_int8((unsigned char)0xAF);
2589 }
2591 #ifdef _LP64
2592 // scans rcx 4 byte words at [edi] for occurance of rax,
2593 // generic
2594 void Assembler::repne_scanl() { // repne_scan
2595 emit_int8((unsigned char)0xF2);
2596 // SCASL
2597 emit_int8((unsigned char)0xAF);
2598 }
2599 #endif
2601 void Assembler::ret(int imm16) {
2602 if (imm16 == 0) {
2603 emit_int8((unsigned char)0xC3);
2604 } else {
2605 emit_int8((unsigned char)0xC2);
2606 emit_int16(imm16);
2607 }
2608 }
2610 void Assembler::sahf() {
2611 #ifdef _LP64
2612 // Not supported in 64bit mode
2613 ShouldNotReachHere();
2614 #endif
2615 emit_int8((unsigned char)0x9E);
2616 }
2618 void Assembler::sarl(Register dst, int imm8) {
2619 int encode = prefix_and_encode(dst->encoding());
2620 assert(isShiftCount(imm8), "illegal shift count");
2621 if (imm8 == 1) {
2622 emit_int8((unsigned char)0xD1);
2623 emit_int8((unsigned char)(0xF8 | encode));
2624 } else {
2625 emit_int8((unsigned char)0xC1);
2626 emit_int8((unsigned char)(0xF8 | encode));
2627 emit_int8(imm8);
2628 }
2629 }
2631 void Assembler::sarl(Register dst) {
2632 int encode = prefix_and_encode(dst->encoding());
2633 emit_int8((unsigned char)0xD3);
2634 emit_int8((unsigned char)(0xF8 | encode));
2635 }
2637 void Assembler::sbbl(Address dst, int32_t imm32) {
2638 InstructionMark im(this);
2639 prefix(dst);
2640 emit_arith_operand(0x81, rbx, dst, imm32);
2641 }
2643 void Assembler::sbbl(Register dst, int32_t imm32) {
2644 prefix(dst);
2645 emit_arith(0x81, 0xD8, dst, imm32);
2646 }
2649 void Assembler::sbbl(Register dst, Address src) {
2650 InstructionMark im(this);
2651 prefix(src, dst);
2652 emit_int8(0x1B);
2653 emit_operand(dst, src);
2654 }
2656 void Assembler::sbbl(Register dst, Register src) {
2657 (void) prefix_and_encode(dst->encoding(), src->encoding());
2658 emit_arith(0x1B, 0xC0, dst, src);
2659 }
2661 void Assembler::setb(Condition cc, Register dst) {
2662 assert(0 <= cc && cc < 16, "illegal cc");
2663 int encode = prefix_and_encode(dst->encoding(), true);
2664 emit_int8(0x0F);
2665 emit_int8((unsigned char)0x90 | cc);
2666 emit_int8((unsigned char)(0xC0 | encode));
2667 }
2669 void Assembler::shll(Register dst, int imm8) {
2670 assert(isShiftCount(imm8), "illegal shift count");
2671 int encode = prefix_and_encode(dst->encoding());
2672 if (imm8 == 1 ) {
2673 emit_int8((unsigned char)0xD1);
2674 emit_int8((unsigned char)(0xE0 | encode));
2675 } else {
2676 emit_int8((unsigned char)0xC1);
2677 emit_int8((unsigned char)(0xE0 | encode));
2678 emit_int8(imm8);
2679 }
2680 }
2682 void Assembler::shll(Register dst) {
2683 int encode = prefix_and_encode(dst->encoding());
2684 emit_int8((unsigned char)0xD3);
2685 emit_int8((unsigned char)(0xE0 | encode));
2686 }
2688 void Assembler::shrl(Register dst, int imm8) {
2689 assert(isShiftCount(imm8), "illegal shift count");
2690 int encode = prefix_and_encode(dst->encoding());
2691 emit_int8((unsigned char)0xC1);
2692 emit_int8((unsigned char)(0xE8 | encode));
2693 emit_int8(imm8);
2694 }
2696 void Assembler::shrl(Register dst) {
2697 int encode = prefix_and_encode(dst->encoding());
2698 emit_int8((unsigned char)0xD3);
2699 emit_int8((unsigned char)(0xE8 | encode));
2700 }
2702 // copies a single word from [esi] to [edi]
2703 void Assembler::smovl() {
2704 emit_int8((unsigned char)0xA5);
2705 }
2707 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2708 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2709 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2710 }
2712 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2713 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2714 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2715 }
2717 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2718 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2719 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2720 }
2722 void Assembler::std() {
2723 emit_int8((unsigned char)0xFD);
2724 }
2726 void Assembler::sqrtss(XMMRegister dst, Address src) {
2727 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2728 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2729 }
2731 void Assembler::stmxcsr( Address dst) {
2732 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2733 InstructionMark im(this);
2734 prefix(dst);
2735 emit_int8(0x0F);
2736 emit_int8((unsigned char)0xAE);
2737 emit_operand(as_Register(3), dst);
2738 }
2740 void Assembler::subl(Address dst, int32_t imm32) {
2741 InstructionMark im(this);
2742 prefix(dst);
2743 emit_arith_operand(0x81, rbp, dst, imm32);
2744 }
2746 void Assembler::subl(Address dst, Register src) {
2747 InstructionMark im(this);
2748 prefix(dst, src);
2749 emit_int8(0x29);
2750 emit_operand(src, dst);
2751 }
2753 void Assembler::subl(Register dst, int32_t imm32) {
2754 prefix(dst);
2755 emit_arith(0x81, 0xE8, dst, imm32);
2756 }
2758 // Force generation of a 4 byte immediate value even if it fits into 8bit
2759 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2760 prefix(dst);
2761 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2762 }
2764 void Assembler::subl(Register dst, Address src) {
2765 InstructionMark im(this);
2766 prefix(src, dst);
2767 emit_int8(0x2B);
2768 emit_operand(dst, src);
2769 }
2771 void Assembler::subl(Register dst, Register src) {
2772 (void) prefix_and_encode(dst->encoding(), src->encoding());
2773 emit_arith(0x2B, 0xC0, dst, src);
2774 }
2776 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2777 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2778 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2779 }
2781 void Assembler::subsd(XMMRegister dst, Address src) {
2782 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2783 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2784 }
2786 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2787 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2788 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2789 }
2791 void Assembler::subss(XMMRegister dst, Address src) {
2792 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2793 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2794 }
2796 void Assembler::testb(Register dst, int imm8) {
2797 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2798 (void) prefix_and_encode(dst->encoding(), true);
2799 emit_arith_b(0xF6, 0xC0, dst, imm8);
2800 }
2802 void Assembler::testl(Register dst, int32_t imm32) {
2803 // not using emit_arith because test
2804 // doesn't support sign-extension of
2805 // 8bit operands
2806 int encode = dst->encoding();
2807 if (encode == 0) {
2808 emit_int8((unsigned char)0xA9);
2809 } else {
2810 encode = prefix_and_encode(encode);
2811 emit_int8((unsigned char)0xF7);
2812 emit_int8((unsigned char)(0xC0 | encode));
2813 }
2814 emit_int32(imm32);
2815 }
2817 void Assembler::testl(Register dst, Register src) {
2818 (void) prefix_and_encode(dst->encoding(), src->encoding());
2819 emit_arith(0x85, 0xC0, dst, src);
2820 }
2822 void Assembler::testl(Register dst, Address src) {
2823 InstructionMark im(this);
2824 prefix(src, dst);
2825 emit_int8((unsigned char)0x85);
2826 emit_operand(dst, src);
2827 }
2829 void Assembler::ucomisd(XMMRegister dst, Address src) {
2830 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2831 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2832 }
2834 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2835 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2836 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2837 }
2839 void Assembler::ucomiss(XMMRegister dst, Address src) {
2840 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2841 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2842 }
2844 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2845 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2846 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2847 }
2850 void Assembler::xaddl(Address dst, Register src) {
2851 InstructionMark im(this);
2852 prefix(dst, src);
2853 emit_int8(0x0F);
2854 emit_int8((unsigned char)0xC1);
2855 emit_operand(src, dst);
2856 }
2858 void Assembler::xchgl(Register dst, Address src) { // xchg
2859 InstructionMark im(this);
2860 prefix(src, dst);
2861 emit_int8((unsigned char)0x87);
2862 emit_operand(dst, src);
2863 }
2865 void Assembler::xchgl(Register dst, Register src) {
2866 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2867 emit_int8((unsigned char)0x87);
2868 emit_int8((unsigned char)(0xC0 | encode));
2869 }
2871 void Assembler::xgetbv() {
2872 emit_int8(0x0F);
2873 emit_int8(0x01);
2874 emit_int8((unsigned char)0xD0);
2875 }
2877 void Assembler::xorl(Register dst, int32_t imm32) {
2878 prefix(dst);
2879 emit_arith(0x81, 0xF0, dst, imm32);
2880 }
2882 void Assembler::xorl(Register dst, Address src) {
2883 InstructionMark im(this);
2884 prefix(src, dst);
2885 emit_int8(0x33);
2886 emit_operand(dst, src);
2887 }
2889 void Assembler::xorl(Register dst, Register src) {
2890 (void) prefix_and_encode(dst->encoding(), src->encoding());
2891 emit_arith(0x33, 0xC0, dst, src);
2892 }
2895 // AVX 3-operands scalar float-point arithmetic instructions
2897 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
2898 assert(VM_Version::supports_avx(), "");
2899 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2900 }
2902 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2903 assert(VM_Version::supports_avx(), "");
2904 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2905 }
2907 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
2908 assert(VM_Version::supports_avx(), "");
2909 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2910 }
2912 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2913 assert(VM_Version::supports_avx(), "");
2914 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2915 }
2917 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
2918 assert(VM_Version::supports_avx(), "");
2919 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2920 }
2922 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2923 assert(VM_Version::supports_avx(), "");
2924 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2925 }
2927 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
2928 assert(VM_Version::supports_avx(), "");
2929 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2930 }
2932 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2933 assert(VM_Version::supports_avx(), "");
2934 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2935 }
2937 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
2938 assert(VM_Version::supports_avx(), "");
2939 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2940 }
2942 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2943 assert(VM_Version::supports_avx(), "");
2944 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2945 }
2947 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
2948 assert(VM_Version::supports_avx(), "");
2949 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2950 }
2952 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2953 assert(VM_Version::supports_avx(), "");
2954 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2955 }
2957 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
2958 assert(VM_Version::supports_avx(), "");
2959 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2960 }
2962 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2963 assert(VM_Version::supports_avx(), "");
2964 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2965 }
2967 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
2968 assert(VM_Version::supports_avx(), "");
2969 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2970 }
2972 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2973 assert(VM_Version::supports_avx(), "");
2974 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2975 }
2977 //====================VECTOR ARITHMETIC=====================================
2979 // Float-point vector arithmetic
2981 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
2982 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2983 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
2984 }
2986 void Assembler::addps(XMMRegister dst, XMMRegister src) {
2987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2988 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
2989 }
2991 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2992 assert(VM_Version::supports_avx(), "");
2993 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
2994 }
2996 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2997 assert(VM_Version::supports_avx(), "");
2998 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
2999 }
3001 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3002 assert(VM_Version::supports_avx(), "");
3003 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3004 }
3006 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3007 assert(VM_Version::supports_avx(), "");
3008 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3009 }
3011 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3012 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3013 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3014 }
3016 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3017 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3018 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3019 }
3021 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3022 assert(VM_Version::supports_avx(), "");
3023 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3024 }
3026 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3027 assert(VM_Version::supports_avx(), "");
3028 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3029 }
3031 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3032 assert(VM_Version::supports_avx(), "");
3033 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3034 }
3036 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3037 assert(VM_Version::supports_avx(), "");
3038 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3039 }
3041 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3042 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3043 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3044 }
3046 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3047 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3048 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3049 }
3051 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3052 assert(VM_Version::supports_avx(), "");
3053 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3054 }
3056 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3057 assert(VM_Version::supports_avx(), "");
3058 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3059 }
3061 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3062 assert(VM_Version::supports_avx(), "");
3063 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3064 }
3066 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3067 assert(VM_Version::supports_avx(), "");
3068 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3069 }
3071 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3072 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3073 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3074 }
3076 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3077 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3078 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3079 }
3081 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3082 assert(VM_Version::supports_avx(), "");
3083 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3084 }
3086 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3087 assert(VM_Version::supports_avx(), "");
3088 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3089 }
3091 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3092 assert(VM_Version::supports_avx(), "");
3093 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3094 }
3096 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3097 assert(VM_Version::supports_avx(), "");
3098 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3099 }
3101 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3102 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3103 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3104 }
3106 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3107 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3108 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3109 }
3111 void Assembler::andps(XMMRegister dst, Address src) {
3112 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3113 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3114 }
3116 void Assembler::andpd(XMMRegister dst, Address src) {
3117 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3118 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3119 }
3121 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3122 assert(VM_Version::supports_avx(), "");
3123 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3124 }
3126 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3127 assert(VM_Version::supports_avx(), "");
3128 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3129 }
3131 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3132 assert(VM_Version::supports_avx(), "");
3133 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3134 }
3136 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3137 assert(VM_Version::supports_avx(), "");
3138 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3139 }
3141 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3142 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3143 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3144 }
3146 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3147 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3148 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3149 }
3151 void Assembler::xorpd(XMMRegister dst, Address src) {
3152 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3153 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3154 }
3156 void Assembler::xorps(XMMRegister dst, Address src) {
3157 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3158 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3159 }
3161 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3162 assert(VM_Version::supports_avx(), "");
3163 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3164 }
3166 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3167 assert(VM_Version::supports_avx(), "");
3168 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3169 }
3171 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3172 assert(VM_Version::supports_avx(), "");
3173 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3174 }
3176 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3177 assert(VM_Version::supports_avx(), "");
3178 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3179 }
3182 // Integer vector arithmetic
3183 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3184 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3185 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3186 }
3188 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3190 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3191 }
3193 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3194 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3195 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3196 }
3198 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3200 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3201 }
3203 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3204 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3205 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3206 }
3208 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3209 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3210 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3211 }
3213 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3214 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3215 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3216 }
3218 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3219 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3220 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3221 }
3223 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3224 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3225 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3226 }
3228 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3229 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3230 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3231 }
3233 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3234 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3235 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3236 }
3238 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3239 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3240 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3241 }
3243 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3244 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3245 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3246 }
3248 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3250 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3251 }
3253 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3254 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3255 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3256 }
3258 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3260 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3261 }
3263 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3264 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3265 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3266 }
3268 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3269 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3270 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3271 }
3273 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3274 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3275 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3276 }
3278 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3279 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3280 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3281 }
3283 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3284 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3285 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3286 }
3288 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3289 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3290 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3291 }
3293 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3294 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3295 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3296 }
3298 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3299 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3300 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3301 }
3303 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3304 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3305 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3306 }
3308 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3309 assert(VM_Version::supports_sse4_1(), "");
3310 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3311 emit_int8(0x40);
3312 emit_int8((unsigned char)(0xC0 | encode));
3313 }
3315 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3316 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3317 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3318 }
3320 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3321 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3322 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3323 emit_int8(0x40);
3324 emit_int8((unsigned char)(0xC0 | encode));
3325 }
3327 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3328 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3329 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3330 }
3332 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3333 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3334 InstructionMark im(this);
3335 int dst_enc = dst->encoding();
3336 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3337 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3338 emit_int8(0x40);
3339 emit_operand(dst, src);
3340 }
3342 // Shift packed integers left by specified number of bits.
3343 void Assembler::psllw(XMMRegister dst, int shift) {
3344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3345 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3346 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3347 emit_int8(0x71);
3348 emit_int8((unsigned char)(0xC0 | encode));
3349 emit_int8(shift & 0xFF);
3350 }
3352 void Assembler::pslld(XMMRegister dst, int shift) {
3353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3354 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3355 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3356 emit_int8(0x72);
3357 emit_int8((unsigned char)(0xC0 | encode));
3358 emit_int8(shift & 0xFF);
3359 }
3361 void Assembler::psllq(XMMRegister dst, int shift) {
3362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3363 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3364 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3365 emit_int8(0x73);
3366 emit_int8((unsigned char)(0xC0 | encode));
3367 emit_int8(shift & 0xFF);
3368 }
3370 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3371 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3372 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3373 }
3375 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3376 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3377 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3378 }
3380 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3381 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3382 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3383 }
3385 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3386 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3387 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3388 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3389 emit_int8(shift & 0xFF);
3390 }
3392 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3393 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3394 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3395 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3396 emit_int8(shift & 0xFF);
3397 }
3399 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3400 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3401 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3402 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3403 emit_int8(shift & 0xFF);
3404 }
3406 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3407 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3408 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3409 }
3411 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3412 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3413 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3414 }
3416 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3417 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3418 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3419 }
3421 // Shift packed integers logically right by specified number of bits.
3422 void Assembler::psrlw(XMMRegister dst, int shift) {
3423 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3424 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3425 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3426 emit_int8(0x71);
3427 emit_int8((unsigned char)(0xC0 | encode));
3428 emit_int8(shift & 0xFF);
3429 }
3431 void Assembler::psrld(XMMRegister dst, int shift) {
3432 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3433 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3434 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3435 emit_int8(0x72);
3436 emit_int8((unsigned char)(0xC0 | encode));
3437 emit_int8(shift & 0xFF);
3438 }
3440 void Assembler::psrlq(XMMRegister dst, int shift) {
3441 // Do not confuse it with psrldq SSE2 instruction which
3442 // shifts 128 bit value in xmm register by number of bytes.
3443 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3444 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3445 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3446 emit_int8(0x73);
3447 emit_int8((unsigned char)(0xC0 | encode));
3448 emit_int8(shift & 0xFF);
3449 }
3451 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3452 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3453 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3454 }
3456 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3457 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3458 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3459 }
3461 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3462 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3463 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3464 }
3466 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3467 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3468 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3469 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3470 emit_int8(shift & 0xFF);
3471 }
3473 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3474 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3475 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3476 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3477 emit_int8(shift & 0xFF);
3478 }
3480 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3481 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3482 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3483 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3484 emit_int8(shift & 0xFF);
3485 }
3487 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3488 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3489 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3490 }
3492 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3493 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3494 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3495 }
3497 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3498 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3499 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3500 }
3502 // Shift packed integers arithmetically right by specified number of bits.
3503 void Assembler::psraw(XMMRegister dst, int shift) {
3504 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3505 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3506 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3507 emit_int8(0x71);
3508 emit_int8((unsigned char)(0xC0 | encode));
3509 emit_int8(shift & 0xFF);
3510 }
3512 void Assembler::psrad(XMMRegister dst, int shift) {
3513 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3514 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3515 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3516 emit_int8(0x72);
3517 emit_int8((unsigned char)(0xC0 | encode));
3518 emit_int8(shift & 0xFF);
3519 }
3521 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3522 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3523 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3524 }
3526 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3528 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3529 }
3531 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3532 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3533 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3534 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3535 emit_int8(shift & 0xFF);
3536 }
3538 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3539 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3540 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3541 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3542 emit_int8(shift & 0xFF);
3543 }
3545 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3546 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3547 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3548 }
3550 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3551 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3552 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3553 }
3556 // AND packed integers
3557 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3558 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3559 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3560 }
3562 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3563 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3564 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3565 }
3567 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3568 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3569 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3570 }
3572 void Assembler::por(XMMRegister dst, XMMRegister src) {
3573 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3574 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3575 }
3577 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3578 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3579 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3580 }
3582 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3583 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3584 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3585 }
3587 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3588 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3589 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3590 }
3592 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3593 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3594 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3595 }
3597 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3598 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3599 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3600 }
3603 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3604 assert(VM_Version::supports_avx(), "");
3605 bool vector256 = true;
3606 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3607 emit_int8(0x18);
3608 emit_int8((unsigned char)(0xC0 | encode));
3609 // 0x00 - insert into lower 128 bits
3610 // 0x01 - insert into upper 128 bits
3611 emit_int8(0x01);
3612 }
3614 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3615 assert(VM_Version::supports_avx(), "");
3616 InstructionMark im(this);
3617 bool vector256 = true;
3618 assert(dst != xnoreg, "sanity");
3619 int dst_enc = dst->encoding();
3620 // swap src<->dst for encoding
3621 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3622 emit_int8(0x18);
3623 emit_operand(dst, src);
3624 // 0x01 - insert into upper 128 bits
3625 emit_int8(0x01);
3626 }
3628 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3629 assert(VM_Version::supports_avx(), "");
3630 InstructionMark im(this);
3631 bool vector256 = true;
3632 assert(src != xnoreg, "sanity");
3633 int src_enc = src->encoding();
3634 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3635 emit_int8(0x19);
3636 emit_operand(src, dst);
3637 // 0x01 - extract from upper 128 bits
3638 emit_int8(0x01);
3639 }
3641 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3642 assert(VM_Version::supports_avx2(), "");
3643 bool vector256 = true;
3644 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3645 emit_int8(0x38);
3646 emit_int8((unsigned char)(0xC0 | encode));
3647 // 0x00 - insert into lower 128 bits
3648 // 0x01 - insert into upper 128 bits
3649 emit_int8(0x01);
3650 }
3652 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3653 assert(VM_Version::supports_avx2(), "");
3654 InstructionMark im(this);
3655 bool vector256 = true;
3656 assert(dst != xnoreg, "sanity");
3657 int dst_enc = dst->encoding();
3658 // swap src<->dst for encoding
3659 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3660 emit_int8(0x38);
3661 emit_operand(dst, src);
3662 // 0x01 - insert into upper 128 bits
3663 emit_int8(0x01);
3664 }
3666 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3667 assert(VM_Version::supports_avx2(), "");
3668 InstructionMark im(this);
3669 bool vector256 = true;
3670 assert(src != xnoreg, "sanity");
3671 int src_enc = src->encoding();
3672 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3673 emit_int8(0x39);
3674 emit_operand(src, dst);
3675 // 0x01 - extract from upper 128 bits
3676 emit_int8(0x01);
3677 }
3679 // duplicate 4-bytes integer data from src into 8 locations in dest
3680 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3681 assert(VM_Version::supports_avx2(), "");
3682 bool vector256 = true;
3683 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3684 emit_int8(0x58);
3685 emit_int8((unsigned char)(0xC0 | encode));
3686 }
3688 void Assembler::vzeroupper() {
3689 assert(VM_Version::supports_avx(), "");
3690 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3691 emit_int8(0x77);
3692 }
3695 #ifndef _LP64
3696 // 32bit only pieces of the assembler
3698 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3699 // NO PREFIX AS NEVER 64BIT
3700 InstructionMark im(this);
3701 emit_int8((unsigned char)0x81);
3702 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3703 emit_data(imm32, rspec, 0);
3704 }
3706 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3707 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3708 InstructionMark im(this);
3709 emit_int8((unsigned char)0x81);
3710 emit_operand(rdi, src1);
3711 emit_data(imm32, rspec, 0);
3712 }
3714 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3715 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3716 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3717 void Assembler::cmpxchg8(Address adr) {
3718 InstructionMark im(this);
3719 emit_int8(0x0F);
3720 emit_int8((unsigned char)0xC7);
3721 emit_operand(rcx, adr);
3722 }
3724 void Assembler::decl(Register dst) {
3725 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3726 emit_int8(0x48 | dst->encoding());
3727 }
3729 #endif // _LP64
3731 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3733 void Assembler::fabs() {
3734 emit_int8((unsigned char)0xD9);
3735 emit_int8((unsigned char)0xE1);
3736 }
3738 void Assembler::fadd(int i) {
3739 emit_farith(0xD8, 0xC0, i);
3740 }
3742 void Assembler::fadd_d(Address src) {
3743 InstructionMark im(this);
3744 emit_int8((unsigned char)0xDC);
3745 emit_operand32(rax, src);
3746 }
3748 void Assembler::fadd_s(Address src) {
3749 InstructionMark im(this);
3750 emit_int8((unsigned char)0xD8);
3751 emit_operand32(rax, src);
3752 }
3754 void Assembler::fadda(int i) {
3755 emit_farith(0xDC, 0xC0, i);
3756 }
3758 void Assembler::faddp(int i) {
3759 emit_farith(0xDE, 0xC0, i);
3760 }
3762 void Assembler::fchs() {
3763 emit_int8((unsigned char)0xD9);
3764 emit_int8((unsigned char)0xE0);
3765 }
3767 void Assembler::fcom(int i) {
3768 emit_farith(0xD8, 0xD0, i);
3769 }
3771 void Assembler::fcomp(int i) {
3772 emit_farith(0xD8, 0xD8, i);
3773 }
3775 void Assembler::fcomp_d(Address src) {
3776 InstructionMark im(this);
3777 emit_int8((unsigned char)0xDC);
3778 emit_operand32(rbx, src);
3779 }
3781 void Assembler::fcomp_s(Address src) {
3782 InstructionMark im(this);
3783 emit_int8((unsigned char)0xD8);
3784 emit_operand32(rbx, src);
3785 }
3787 void Assembler::fcompp() {
3788 emit_int8((unsigned char)0xDE);
3789 emit_int8((unsigned char)0xD9);
3790 }
3792 void Assembler::fcos() {
3793 emit_int8((unsigned char)0xD9);
3794 emit_int8((unsigned char)0xFF);
3795 }
3797 void Assembler::fdecstp() {
3798 emit_int8((unsigned char)0xD9);
3799 emit_int8((unsigned char)0xF6);
3800 }
3802 void Assembler::fdiv(int i) {
3803 emit_farith(0xD8, 0xF0, i);
3804 }
3806 void Assembler::fdiv_d(Address src) {
3807 InstructionMark im(this);
3808 emit_int8((unsigned char)0xDC);
3809 emit_operand32(rsi, src);
3810 }
3812 void Assembler::fdiv_s(Address src) {
3813 InstructionMark im(this);
3814 emit_int8((unsigned char)0xD8);
3815 emit_operand32(rsi, src);
3816 }
3818 void Assembler::fdiva(int i) {
3819 emit_farith(0xDC, 0xF8, i);
3820 }
3822 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
3823 // is erroneous for some of the floating-point instructions below.
3825 void Assembler::fdivp(int i) {
3826 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
3827 }
3829 void Assembler::fdivr(int i) {
3830 emit_farith(0xD8, 0xF8, i);
3831 }
3833 void Assembler::fdivr_d(Address src) {
3834 InstructionMark im(this);
3835 emit_int8((unsigned char)0xDC);
3836 emit_operand32(rdi, src);
3837 }
3839 void Assembler::fdivr_s(Address src) {
3840 InstructionMark im(this);
3841 emit_int8((unsigned char)0xD8);
3842 emit_operand32(rdi, src);
3843 }
3845 void Assembler::fdivra(int i) {
3846 emit_farith(0xDC, 0xF0, i);
3847 }
3849 void Assembler::fdivrp(int i) {
3850 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
3851 }
3853 void Assembler::ffree(int i) {
3854 emit_farith(0xDD, 0xC0, i);
3855 }
3857 void Assembler::fild_d(Address adr) {
3858 InstructionMark im(this);
3859 emit_int8((unsigned char)0xDF);
3860 emit_operand32(rbp, adr);
3861 }
3863 void Assembler::fild_s(Address adr) {
3864 InstructionMark im(this);
3865 emit_int8((unsigned char)0xDB);
3866 emit_operand32(rax, adr);
3867 }
3869 void Assembler::fincstp() {
3870 emit_int8((unsigned char)0xD9);
3871 emit_int8((unsigned char)0xF7);
3872 }
3874 void Assembler::finit() {
3875 emit_int8((unsigned char)0x9B);
3876 emit_int8((unsigned char)0xDB);
3877 emit_int8((unsigned char)0xE3);
3878 }
3880 void Assembler::fist_s(Address adr) {
3881 InstructionMark im(this);
3882 emit_int8((unsigned char)0xDB);
3883 emit_operand32(rdx, adr);
3884 }
3886 void Assembler::fistp_d(Address adr) {
3887 InstructionMark im(this);
3888 emit_int8((unsigned char)0xDF);
3889 emit_operand32(rdi, adr);
3890 }
3892 void Assembler::fistp_s(Address adr) {
3893 InstructionMark im(this);
3894 emit_int8((unsigned char)0xDB);
3895 emit_operand32(rbx, adr);
3896 }
3898 void Assembler::fld1() {
3899 emit_int8((unsigned char)0xD9);
3900 emit_int8((unsigned char)0xE8);
3901 }
3903 void Assembler::fld_d(Address adr) {
3904 InstructionMark im(this);
3905 emit_int8((unsigned char)0xDD);
3906 emit_operand32(rax, adr);
3907 }
3909 void Assembler::fld_s(Address adr) {
3910 InstructionMark im(this);
3911 emit_int8((unsigned char)0xD9);
3912 emit_operand32(rax, adr);
3913 }
3916 void Assembler::fld_s(int index) {
3917 emit_farith(0xD9, 0xC0, index);
3918 }
3920 void Assembler::fld_x(Address adr) {
3921 InstructionMark im(this);
3922 emit_int8((unsigned char)0xDB);
3923 emit_operand32(rbp, adr);
3924 }
3926 void Assembler::fldcw(Address src) {
3927 InstructionMark im(this);
3928 emit_int8((unsigned char)0xD9);
3929 emit_operand32(rbp, src);
3930 }
3932 void Assembler::fldenv(Address src) {
3933 InstructionMark im(this);
3934 emit_int8((unsigned char)0xD9);
3935 emit_operand32(rsp, src);
3936 }
3938 void Assembler::fldlg2() {
3939 emit_int8((unsigned char)0xD9);
3940 emit_int8((unsigned char)0xEC);
3941 }
3943 void Assembler::fldln2() {
3944 emit_int8((unsigned char)0xD9);
3945 emit_int8((unsigned char)0xED);
3946 }
3948 void Assembler::fldz() {
3949 emit_int8((unsigned char)0xD9);
3950 emit_int8((unsigned char)0xEE);
3951 }
3953 void Assembler::flog() {
3954 fldln2();
3955 fxch();
3956 fyl2x();
3957 }
3959 void Assembler::flog10() {
3960 fldlg2();
3961 fxch();
3962 fyl2x();
3963 }
3965 void Assembler::fmul(int i) {
3966 emit_farith(0xD8, 0xC8, i);
3967 }
3969 void Assembler::fmul_d(Address src) {
3970 InstructionMark im(this);
3971 emit_int8((unsigned char)0xDC);
3972 emit_operand32(rcx, src);
3973 }
3975 void Assembler::fmul_s(Address src) {
3976 InstructionMark im(this);
3977 emit_int8((unsigned char)0xD8);
3978 emit_operand32(rcx, src);
3979 }
3981 void Assembler::fmula(int i) {
3982 emit_farith(0xDC, 0xC8, i);
3983 }
3985 void Assembler::fmulp(int i) {
3986 emit_farith(0xDE, 0xC8, i);
3987 }
3989 void Assembler::fnsave(Address dst) {
3990 InstructionMark im(this);
3991 emit_int8((unsigned char)0xDD);
3992 emit_operand32(rsi, dst);
3993 }
3995 void Assembler::fnstcw(Address src) {
3996 InstructionMark im(this);
3997 emit_int8((unsigned char)0x9B);
3998 emit_int8((unsigned char)0xD9);
3999 emit_operand32(rdi, src);
4000 }
4002 void Assembler::fnstsw_ax() {
4003 emit_int8((unsigned char)0xDF);
4004 emit_int8((unsigned char)0xE0);
4005 }
4007 void Assembler::fprem() {
4008 emit_int8((unsigned char)0xD9);
4009 emit_int8((unsigned char)0xF8);
4010 }
4012 void Assembler::fprem1() {
4013 emit_int8((unsigned char)0xD9);
4014 emit_int8((unsigned char)0xF5);
4015 }
4017 void Assembler::frstor(Address src) {
4018 InstructionMark im(this);
4019 emit_int8((unsigned char)0xDD);
4020 emit_operand32(rsp, src);
4021 }
4023 void Assembler::fsin() {
4024 emit_int8((unsigned char)0xD9);
4025 emit_int8((unsigned char)0xFE);
4026 }
4028 void Assembler::fsqrt() {
4029 emit_int8((unsigned char)0xD9);
4030 emit_int8((unsigned char)0xFA);
4031 }
4033 void Assembler::fst_d(Address adr) {
4034 InstructionMark im(this);
4035 emit_int8((unsigned char)0xDD);
4036 emit_operand32(rdx, adr);
4037 }
4039 void Assembler::fst_s(Address adr) {
4040 InstructionMark im(this);
4041 emit_int8((unsigned char)0xD9);
4042 emit_operand32(rdx, adr);
4043 }
4045 void Assembler::fstp_d(Address adr) {
4046 InstructionMark im(this);
4047 emit_int8((unsigned char)0xDD);
4048 emit_operand32(rbx, adr);
4049 }
4051 void Assembler::fstp_d(int index) {
4052 emit_farith(0xDD, 0xD8, index);
4053 }
4055 void Assembler::fstp_s(Address adr) {
4056 InstructionMark im(this);
4057 emit_int8((unsigned char)0xD9);
4058 emit_operand32(rbx, adr);
4059 }
4061 void Assembler::fstp_x(Address adr) {
4062 InstructionMark im(this);
4063 emit_int8((unsigned char)0xDB);
4064 emit_operand32(rdi, adr);
4065 }
4067 void Assembler::fsub(int i) {
4068 emit_farith(0xD8, 0xE0, i);
4069 }
4071 void Assembler::fsub_d(Address src) {
4072 InstructionMark im(this);
4073 emit_int8((unsigned char)0xDC);
4074 emit_operand32(rsp, src);
4075 }
4077 void Assembler::fsub_s(Address src) {
4078 InstructionMark im(this);
4079 emit_int8((unsigned char)0xD8);
4080 emit_operand32(rsp, src);
4081 }
4083 void Assembler::fsuba(int i) {
4084 emit_farith(0xDC, 0xE8, i);
4085 }
4087 void Assembler::fsubp(int i) {
4088 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4089 }
4091 void Assembler::fsubr(int i) {
4092 emit_farith(0xD8, 0xE8, i);
4093 }
4095 void Assembler::fsubr_d(Address src) {
4096 InstructionMark im(this);
4097 emit_int8((unsigned char)0xDC);
4098 emit_operand32(rbp, src);
4099 }
4101 void Assembler::fsubr_s(Address src) {
4102 InstructionMark im(this);
4103 emit_int8((unsigned char)0xD8);
4104 emit_operand32(rbp, src);
4105 }
4107 void Assembler::fsubra(int i) {
4108 emit_farith(0xDC, 0xE0, i);
4109 }
4111 void Assembler::fsubrp(int i) {
4112 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4113 }
4115 void Assembler::ftan() {
4116 emit_int8((unsigned char)0xD9);
4117 emit_int8((unsigned char)0xF2);
4118 emit_int8((unsigned char)0xDD);
4119 emit_int8((unsigned char)0xD8);
4120 }
4122 void Assembler::ftst() {
4123 emit_int8((unsigned char)0xD9);
4124 emit_int8((unsigned char)0xE4);
4125 }
4127 void Assembler::fucomi(int i) {
4128 // make sure the instruction is supported (introduced for P6, together with cmov)
4129 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4130 emit_farith(0xDB, 0xE8, i);
4131 }
4133 void Assembler::fucomip(int i) {
4134 // make sure the instruction is supported (introduced for P6, together with cmov)
4135 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4136 emit_farith(0xDF, 0xE8, i);
4137 }
4139 void Assembler::fwait() {
4140 emit_int8((unsigned char)0x9B);
4141 }
4143 void Assembler::fxch(int i) {
4144 emit_farith(0xD9, 0xC8, i);
4145 }
4147 void Assembler::fyl2x() {
4148 emit_int8((unsigned char)0xD9);
4149 emit_int8((unsigned char)0xF1);
4150 }
4152 void Assembler::frndint() {
4153 emit_int8((unsigned char)0xD9);
4154 emit_int8((unsigned char)0xFC);
4155 }
4157 void Assembler::f2xm1() {
4158 emit_int8((unsigned char)0xD9);
4159 emit_int8((unsigned char)0xF0);
4160 }
4162 void Assembler::fldl2e() {
4163 emit_int8((unsigned char)0xD9);
4164 emit_int8((unsigned char)0xEA);
4165 }
4167 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4168 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4169 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4170 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4172 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4173 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4174 if (pre > 0) {
4175 emit_int8(simd_pre[pre]);
4176 }
4177 if (rex_w) {
4178 prefixq(adr, xreg);
4179 } else {
4180 prefix(adr, xreg);
4181 }
4182 if (opc > 0) {
4183 emit_int8(0x0F);
4184 int opc2 = simd_opc[opc];
4185 if (opc2 > 0) {
4186 emit_int8(opc2);
4187 }
4188 }
4189 }
4191 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4192 if (pre > 0) {
4193 emit_int8(simd_pre[pre]);
4194 }
4195 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4196 prefix_and_encode(dst_enc, src_enc);
4197 if (opc > 0) {
4198 emit_int8(0x0F);
4199 int opc2 = simd_opc[opc];
4200 if (opc2 > 0) {
4201 emit_int8(opc2);
4202 }
4203 }
4204 return encode;
4205 }
4208 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4209 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4210 prefix(VEX_3bytes);
4212 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4213 byte1 = (~byte1) & 0xE0;
4214 byte1 |= opc;
4215 emit_int8(byte1);
4217 int byte2 = ((~nds_enc) & 0xf) << 3;
4218 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4219 emit_int8(byte2);
4220 } else {
4221 prefix(VEX_2bytes);
4223 int byte1 = vex_r ? VEX_R : 0;
4224 byte1 = (~byte1) & 0x80;
4225 byte1 |= ((~nds_enc) & 0xf) << 3;
4226 byte1 |= (vector256 ? 4 : 0) | pre;
4227 emit_int8(byte1);
4228 }
4229 }
4231 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4232 bool vex_r = (xreg_enc >= 8);
4233 bool vex_b = adr.base_needs_rex();
4234 bool vex_x = adr.index_needs_rex();
4235 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4236 }
4238 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4239 bool vex_r = (dst_enc >= 8);
4240 bool vex_b = (src_enc >= 8);
4241 bool vex_x = false;
4242 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4243 return (((dst_enc & 7) << 3) | (src_enc & 7));
4244 }
4247 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4248 if (UseAVX > 0) {
4249 int xreg_enc = xreg->encoding();
4250 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4251 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4252 } else {
4253 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4254 rex_prefix(adr, xreg, pre, opc, rex_w);
4255 }
4256 }
4258 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4259 int dst_enc = dst->encoding();
4260 int src_enc = src->encoding();
4261 if (UseAVX > 0) {
4262 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4263 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4264 } else {
4265 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4266 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4267 }
4268 }
4270 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4271 InstructionMark im(this);
4272 simd_prefix(dst, dst, src, pre);
4273 emit_int8(opcode);
4274 emit_operand(dst, src);
4275 }
4277 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4278 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4279 emit_int8(opcode);
4280 emit_int8((unsigned char)(0xC0 | encode));
4281 }
4283 // Versions with no second source register (non-destructive source).
4284 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4285 InstructionMark im(this);
4286 simd_prefix(dst, xnoreg, src, pre);
4287 emit_int8(opcode);
4288 emit_operand(dst, src);
4289 }
4291 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4292 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4293 emit_int8(opcode);
4294 emit_int8((unsigned char)(0xC0 | encode));
4295 }
4297 // 3-operands AVX instructions
4298 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4299 Address src, VexSimdPrefix pre, bool vector256) {
4300 InstructionMark im(this);
4301 vex_prefix(dst, nds, src, pre, vector256);
4302 emit_int8(opcode);
4303 emit_operand(dst, src);
4304 }
4306 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4307 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4308 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4309 emit_int8(opcode);
4310 emit_int8((unsigned char)(0xC0 | encode));
4311 }
4313 #ifndef _LP64
4315 void Assembler::incl(Register dst) {
4316 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4317 emit_int8(0x40 | dst->encoding());
4318 }
4320 void Assembler::lea(Register dst, Address src) {
4321 leal(dst, src);
4322 }
4324 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4325 InstructionMark im(this);
4326 emit_int8((unsigned char)0xC7);
4327 emit_operand(rax, dst);
4328 emit_data((int)imm32, rspec, 0);
4329 }
4331 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4332 InstructionMark im(this);
4333 int encode = prefix_and_encode(dst->encoding());
4334 emit_int8((unsigned char)(0xB8 | encode));
4335 emit_data((int)imm32, rspec, 0);
4336 }
4338 void Assembler::popa() { // 32bit
4339 emit_int8(0x61);
4340 }
4342 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4343 InstructionMark im(this);
4344 emit_int8(0x68);
4345 emit_data(imm32, rspec, 0);
4346 }
4348 void Assembler::pusha() { // 32bit
4349 emit_int8(0x60);
4350 }
4352 void Assembler::set_byte_if_not_zero(Register dst) {
4353 emit_int8(0x0F);
4354 emit_int8((unsigned char)0x95);
4355 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4356 }
4358 void Assembler::shldl(Register dst, Register src) {
4359 emit_int8(0x0F);
4360 emit_int8((unsigned char)0xA5);
4361 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4362 }
4364 void Assembler::shrdl(Register dst, Register src) {
4365 emit_int8(0x0F);
4366 emit_int8((unsigned char)0xAD);
4367 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4368 }
4370 #else // LP64
4372 void Assembler::set_byte_if_not_zero(Register dst) {
4373 int enc = prefix_and_encode(dst->encoding(), true);
4374 emit_int8(0x0F);
4375 emit_int8((unsigned char)0x95);
4376 emit_int8((unsigned char)(0xE0 | enc));
4377 }
4379 // 64bit only pieces of the assembler
4380 // This should only be used by 64bit instructions that can use rip-relative
4381 // it cannot be used by instructions that want an immediate value.
4383 bool Assembler::reachable(AddressLiteral adr) {
4384 int64_t disp;
4385 // None will force a 64bit literal to the code stream. Likely a placeholder
4386 // for something that will be patched later and we need to certain it will
4387 // always be reachable.
4388 if (adr.reloc() == relocInfo::none) {
4389 return false;
4390 }
4391 if (adr.reloc() == relocInfo::internal_word_type) {
4392 // This should be rip relative and easily reachable.
4393 return true;
4394 }
4395 if (adr.reloc() == relocInfo::virtual_call_type ||
4396 adr.reloc() == relocInfo::opt_virtual_call_type ||
4397 adr.reloc() == relocInfo::static_call_type ||
4398 adr.reloc() == relocInfo::static_stub_type ) {
4399 // This should be rip relative within the code cache and easily
4400 // reachable until we get huge code caches. (At which point
4401 // ic code is going to have issues).
4402 return true;
4403 }
4404 if (adr.reloc() != relocInfo::external_word_type &&
4405 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4406 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4407 adr.reloc() != relocInfo::runtime_call_type ) {
4408 return false;
4409 }
4411 // Stress the correction code
4412 if (ForceUnreachable) {
4413 // Must be runtimecall reloc, see if it is in the codecache
4414 // Flipping stuff in the codecache to be unreachable causes issues
4415 // with things like inline caches where the additional instructions
4416 // are not handled.
4417 if (CodeCache::find_blob(adr._target) == NULL) {
4418 return false;
4419 }
4420 }
4421 // For external_word_type/runtime_call_type if it is reachable from where we
4422 // are now (possibly a temp buffer) and where we might end up
4423 // anywhere in the codeCache then we are always reachable.
4424 // This would have to change if we ever save/restore shared code
4425 // to be more pessimistic.
4426 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4427 if (!is_simm32(disp)) return false;
4428 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4429 if (!is_simm32(disp)) return false;
4431 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4433 // Because rip relative is a disp + address_of_next_instruction and we
4434 // don't know the value of address_of_next_instruction we apply a fudge factor
4435 // to make sure we will be ok no matter the size of the instruction we get placed into.
4436 // We don't have to fudge the checks above here because they are already worst case.
4438 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4439 // + 4 because better safe than sorry.
4440 const int fudge = 12 + 4;
4441 if (disp < 0) {
4442 disp -= fudge;
4443 } else {
4444 disp += fudge;
4445 }
4446 return is_simm32(disp);
4447 }
4449 // Check if the polling page is not reachable from the code cache using rip-relative
4450 // addressing.
4451 bool Assembler::is_polling_page_far() {
4452 intptr_t addr = (intptr_t)os::get_polling_page();
4453 return ForceUnreachable ||
4454 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4455 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4456 }
4458 void Assembler::emit_data64(jlong data,
4459 relocInfo::relocType rtype,
4460 int format) {
4461 if (rtype == relocInfo::none) {
4462 emit_int64(data);
4463 } else {
4464 emit_data64(data, Relocation::spec_simple(rtype), format);
4465 }
4466 }
4468 void Assembler::emit_data64(jlong data,
4469 RelocationHolder const& rspec,
4470 int format) {
4471 assert(imm_operand == 0, "default format must be immediate in this file");
4472 assert(imm_operand == format, "must be immediate");
4473 assert(inst_mark() != NULL, "must be inside InstructionMark");
4474 // Do not use AbstractAssembler::relocate, which is not intended for
4475 // embedded words. Instead, relocate to the enclosing instruction.
4476 code_section()->relocate(inst_mark(), rspec, format);
4477 #ifdef ASSERT
4478 check_relocation(rspec, format);
4479 #endif
4480 emit_int64(data);
4481 }
4483 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4484 if (reg_enc >= 8) {
4485 prefix(REX_B);
4486 reg_enc -= 8;
4487 } else if (byteinst && reg_enc >= 4) {
4488 prefix(REX);
4489 }
4490 return reg_enc;
4491 }
4493 int Assembler::prefixq_and_encode(int reg_enc) {
4494 if (reg_enc < 8) {
4495 prefix(REX_W);
4496 } else {
4497 prefix(REX_WB);
4498 reg_enc -= 8;
4499 }
4500 return reg_enc;
4501 }
4503 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4504 if (dst_enc < 8) {
4505 if (src_enc >= 8) {
4506 prefix(REX_B);
4507 src_enc -= 8;
4508 } else if (byteinst && src_enc >= 4) {
4509 prefix(REX);
4510 }
4511 } else {
4512 if (src_enc < 8) {
4513 prefix(REX_R);
4514 } else {
4515 prefix(REX_RB);
4516 src_enc -= 8;
4517 }
4518 dst_enc -= 8;
4519 }
4520 return dst_enc << 3 | src_enc;
4521 }
4523 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4524 if (dst_enc < 8) {
4525 if (src_enc < 8) {
4526 prefix(REX_W);
4527 } else {
4528 prefix(REX_WB);
4529 src_enc -= 8;
4530 }
4531 } else {
4532 if (src_enc < 8) {
4533 prefix(REX_WR);
4534 } else {
4535 prefix(REX_WRB);
4536 src_enc -= 8;
4537 }
4538 dst_enc -= 8;
4539 }
4540 return dst_enc << 3 | src_enc;
4541 }
4543 void Assembler::prefix(Register reg) {
4544 if (reg->encoding() >= 8) {
4545 prefix(REX_B);
4546 }
4547 }
4549 void Assembler::prefix(Address adr) {
4550 if (adr.base_needs_rex()) {
4551 if (adr.index_needs_rex()) {
4552 prefix(REX_XB);
4553 } else {
4554 prefix(REX_B);
4555 }
4556 } else {
4557 if (adr.index_needs_rex()) {
4558 prefix(REX_X);
4559 }
4560 }
4561 }
4563 void Assembler::prefixq(Address adr) {
4564 if (adr.base_needs_rex()) {
4565 if (adr.index_needs_rex()) {
4566 prefix(REX_WXB);
4567 } else {
4568 prefix(REX_WB);
4569 }
4570 } else {
4571 if (adr.index_needs_rex()) {
4572 prefix(REX_WX);
4573 } else {
4574 prefix(REX_W);
4575 }
4576 }
4577 }
4580 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4581 if (reg->encoding() < 8) {
4582 if (adr.base_needs_rex()) {
4583 if (adr.index_needs_rex()) {
4584 prefix(REX_XB);
4585 } else {
4586 prefix(REX_B);
4587 }
4588 } else {
4589 if (adr.index_needs_rex()) {
4590 prefix(REX_X);
4591 } else if (byteinst && reg->encoding() >= 4 ) {
4592 prefix(REX);
4593 }
4594 }
4595 } else {
4596 if (adr.base_needs_rex()) {
4597 if (adr.index_needs_rex()) {
4598 prefix(REX_RXB);
4599 } else {
4600 prefix(REX_RB);
4601 }
4602 } else {
4603 if (adr.index_needs_rex()) {
4604 prefix(REX_RX);
4605 } else {
4606 prefix(REX_R);
4607 }
4608 }
4609 }
4610 }
4612 void Assembler::prefixq(Address adr, Register src) {
4613 if (src->encoding() < 8) {
4614 if (adr.base_needs_rex()) {
4615 if (adr.index_needs_rex()) {
4616 prefix(REX_WXB);
4617 } else {
4618 prefix(REX_WB);
4619 }
4620 } else {
4621 if (adr.index_needs_rex()) {
4622 prefix(REX_WX);
4623 } else {
4624 prefix(REX_W);
4625 }
4626 }
4627 } else {
4628 if (adr.base_needs_rex()) {
4629 if (adr.index_needs_rex()) {
4630 prefix(REX_WRXB);
4631 } else {
4632 prefix(REX_WRB);
4633 }
4634 } else {
4635 if (adr.index_needs_rex()) {
4636 prefix(REX_WRX);
4637 } else {
4638 prefix(REX_WR);
4639 }
4640 }
4641 }
4642 }
4644 void Assembler::prefix(Address adr, XMMRegister reg) {
4645 if (reg->encoding() < 8) {
4646 if (adr.base_needs_rex()) {
4647 if (adr.index_needs_rex()) {
4648 prefix(REX_XB);
4649 } else {
4650 prefix(REX_B);
4651 }
4652 } else {
4653 if (adr.index_needs_rex()) {
4654 prefix(REX_X);
4655 }
4656 }
4657 } else {
4658 if (adr.base_needs_rex()) {
4659 if (adr.index_needs_rex()) {
4660 prefix(REX_RXB);
4661 } else {
4662 prefix(REX_RB);
4663 }
4664 } else {
4665 if (adr.index_needs_rex()) {
4666 prefix(REX_RX);
4667 } else {
4668 prefix(REX_R);
4669 }
4670 }
4671 }
4672 }
4674 void Assembler::prefixq(Address adr, XMMRegister src) {
4675 if (src->encoding() < 8) {
4676 if (adr.base_needs_rex()) {
4677 if (adr.index_needs_rex()) {
4678 prefix(REX_WXB);
4679 } else {
4680 prefix(REX_WB);
4681 }
4682 } else {
4683 if (adr.index_needs_rex()) {
4684 prefix(REX_WX);
4685 } else {
4686 prefix(REX_W);
4687 }
4688 }
4689 } else {
4690 if (adr.base_needs_rex()) {
4691 if (adr.index_needs_rex()) {
4692 prefix(REX_WRXB);
4693 } else {
4694 prefix(REX_WRB);
4695 }
4696 } else {
4697 if (adr.index_needs_rex()) {
4698 prefix(REX_WRX);
4699 } else {
4700 prefix(REX_WR);
4701 }
4702 }
4703 }
4704 }
4706 void Assembler::adcq(Register dst, int32_t imm32) {
4707 (void) prefixq_and_encode(dst->encoding());
4708 emit_arith(0x81, 0xD0, dst, imm32);
4709 }
4711 void Assembler::adcq(Register dst, Address src) {
4712 InstructionMark im(this);
4713 prefixq(src, dst);
4714 emit_int8(0x13);
4715 emit_operand(dst, src);
4716 }
4718 void Assembler::adcq(Register dst, Register src) {
4719 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4720 emit_arith(0x13, 0xC0, dst, src);
4721 }
4723 void Assembler::addq(Address dst, int32_t imm32) {
4724 InstructionMark im(this);
4725 prefixq(dst);
4726 emit_arith_operand(0x81, rax, dst,imm32);
4727 }
4729 void Assembler::addq(Address dst, Register src) {
4730 InstructionMark im(this);
4731 prefixq(dst, src);
4732 emit_int8(0x01);
4733 emit_operand(src, dst);
4734 }
4736 void Assembler::addq(Register dst, int32_t imm32) {
4737 (void) prefixq_and_encode(dst->encoding());
4738 emit_arith(0x81, 0xC0, dst, imm32);
4739 }
4741 void Assembler::addq(Register dst, Address src) {
4742 InstructionMark im(this);
4743 prefixq(src, dst);
4744 emit_int8(0x03);
4745 emit_operand(dst, src);
4746 }
4748 void Assembler::addq(Register dst, Register src) {
4749 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4750 emit_arith(0x03, 0xC0, dst, src);
4751 }
4753 void Assembler::andq(Address dst, int32_t imm32) {
4754 InstructionMark im(this);
4755 prefixq(dst);
4756 emit_int8((unsigned char)0x81);
4757 emit_operand(rsp, dst, 4);
4758 emit_int32(imm32);
4759 }
4761 void Assembler::andq(Register dst, int32_t imm32) {
4762 (void) prefixq_and_encode(dst->encoding());
4763 emit_arith(0x81, 0xE0, dst, imm32);
4764 }
4766 void Assembler::andq(Register dst, Address src) {
4767 InstructionMark im(this);
4768 prefixq(src, dst);
4769 emit_int8(0x23);
4770 emit_operand(dst, src);
4771 }
4773 void Assembler::andq(Register dst, Register src) {
4774 (int) prefixq_and_encode(dst->encoding(), src->encoding());
4775 emit_arith(0x23, 0xC0, dst, src);
4776 }
4778 void Assembler::bsfq(Register dst, Register src) {
4779 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4780 emit_int8(0x0F);
4781 emit_int8((unsigned char)0xBC);
4782 emit_int8((unsigned char)(0xC0 | encode));
4783 }
4785 void Assembler::bsrq(Register dst, Register src) {
4786 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
4787 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4788 emit_int8(0x0F);
4789 emit_int8((unsigned char)0xBD);
4790 emit_int8((unsigned char)(0xC0 | encode));
4791 }
4793 void Assembler::bswapq(Register reg) {
4794 int encode = prefixq_and_encode(reg->encoding());
4795 emit_int8(0x0F);
4796 emit_int8((unsigned char)(0xC8 | encode));
4797 }
4799 void Assembler::cdqq() {
4800 prefix(REX_W);
4801 emit_int8((unsigned char)0x99);
4802 }
4804 void Assembler::clflush(Address adr) {
4805 prefix(adr);
4806 emit_int8(0x0F);
4807 emit_int8((unsigned char)0xAE);
4808 emit_operand(rdi, adr);
4809 }
4811 void Assembler::cmovq(Condition cc, Register dst, Register src) {
4812 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4813 emit_int8(0x0F);
4814 emit_int8(0x40 | cc);
4815 emit_int8((unsigned char)(0xC0 | encode));
4816 }
4818 void Assembler::cmovq(Condition cc, Register dst, Address src) {
4819 InstructionMark im(this);
4820 prefixq(src, dst);
4821 emit_int8(0x0F);
4822 emit_int8(0x40 | cc);
4823 emit_operand(dst, src);
4824 }
4826 void Assembler::cmpq(Address dst, int32_t imm32) {
4827 InstructionMark im(this);
4828 prefixq(dst);
4829 emit_int8((unsigned char)0x81);
4830 emit_operand(rdi, dst, 4);
4831 emit_int32(imm32);
4832 }
4834 void Assembler::cmpq(Register dst, int32_t imm32) {
4835 (void) prefixq_and_encode(dst->encoding());
4836 emit_arith(0x81, 0xF8, dst, imm32);
4837 }
4839 void Assembler::cmpq(Address dst, Register src) {
4840 InstructionMark im(this);
4841 prefixq(dst, src);
4842 emit_int8(0x3B);
4843 emit_operand(src, dst);
4844 }
4846 void Assembler::cmpq(Register dst, Register src) {
4847 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4848 emit_arith(0x3B, 0xC0, dst, src);
4849 }
4851 void Assembler::cmpq(Register dst, Address src) {
4852 InstructionMark im(this);
4853 prefixq(src, dst);
4854 emit_int8(0x3B);
4855 emit_operand(dst, src);
4856 }
4858 void Assembler::cmpxchgq(Register reg, Address adr) {
4859 InstructionMark im(this);
4860 prefixq(adr, reg);
4861 emit_int8(0x0F);
4862 emit_int8((unsigned char)0xB1);
4863 emit_operand(reg, adr);
4864 }
4866 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
4867 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4868 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
4869 emit_int8(0x2A);
4870 emit_int8((unsigned char)(0xC0 | encode));
4871 }
4873 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
4874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4875 InstructionMark im(this);
4876 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
4877 emit_int8(0x2A);
4878 emit_operand(dst, src);
4879 }
4881 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
4882 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4883 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
4884 emit_int8(0x2A);
4885 emit_int8((unsigned char)(0xC0 | encode));
4886 }
4888 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
4889 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4890 InstructionMark im(this);
4891 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
4892 emit_int8(0x2A);
4893 emit_operand(dst, src);
4894 }
4896 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
4897 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4898 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
4899 emit_int8(0x2C);
4900 emit_int8((unsigned char)(0xC0 | encode));
4901 }
4903 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
4904 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4905 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
4906 emit_int8(0x2C);
4907 emit_int8((unsigned char)(0xC0 | encode));
4908 }
4910 void Assembler::decl(Register dst) {
4911 // Don't use it directly. Use MacroAssembler::decrementl() instead.
4912 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
4913 int encode = prefix_and_encode(dst->encoding());
4914 emit_int8((unsigned char)0xFF);
4915 emit_int8((unsigned char)(0xC8 | encode));
4916 }
4918 void Assembler::decq(Register dst) {
4919 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4920 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4921 int encode = prefixq_and_encode(dst->encoding());
4922 emit_int8((unsigned char)0xFF);
4923 emit_int8(0xC8 | encode);
4924 }
4926 void Assembler::decq(Address dst) {
4927 // Don't use it directly. Use MacroAssembler::decrementq() instead.
4928 InstructionMark im(this);
4929 prefixq(dst);
4930 emit_int8((unsigned char)0xFF);
4931 emit_operand(rcx, dst);
4932 }
4934 void Assembler::fxrstor(Address src) {
4935 prefixq(src);
4936 emit_int8(0x0F);
4937 emit_int8((unsigned char)0xAE);
4938 emit_operand(as_Register(1), src);
4939 }
4941 void Assembler::fxsave(Address dst) {
4942 prefixq(dst);
4943 emit_int8(0x0F);
4944 emit_int8((unsigned char)0xAE);
4945 emit_operand(as_Register(0), dst);
4946 }
4948 void Assembler::idivq(Register src) {
4949 int encode = prefixq_and_encode(src->encoding());
4950 emit_int8((unsigned char)0xF7);
4951 emit_int8((unsigned char)(0xF8 | encode));
4952 }
4954 void Assembler::imulq(Register dst, Register src) {
4955 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4956 emit_int8(0x0F);
4957 emit_int8((unsigned char)0xAF);
4958 emit_int8((unsigned char)(0xC0 | encode));
4959 }
4961 void Assembler::imulq(Register dst, Register src, int value) {
4962 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4963 if (is8bit(value)) {
4964 emit_int8(0x6B);
4965 emit_int8((unsigned char)(0xC0 | encode));
4966 emit_int8(value & 0xFF);
4967 } else {
4968 emit_int8(0x69);
4969 emit_int8((unsigned char)(0xC0 | encode));
4970 emit_int32(value);
4971 }
4972 }
4974 void Assembler::incl(Register dst) {
4975 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4976 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4977 int encode = prefix_and_encode(dst->encoding());
4978 emit_int8((unsigned char)0xFF);
4979 emit_int8((unsigned char)(0xC0 | encode));
4980 }
4982 void Assembler::incq(Register dst) {
4983 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4984 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
4985 int encode = prefixq_and_encode(dst->encoding());
4986 emit_int8((unsigned char)0xFF);
4987 emit_int8((unsigned char)(0xC0 | encode));
4988 }
4990 void Assembler::incq(Address dst) {
4991 // Don't use it directly. Use MacroAssembler::incrementq() instead.
4992 InstructionMark im(this);
4993 prefixq(dst);
4994 emit_int8((unsigned char)0xFF);
4995 emit_operand(rax, dst);
4996 }
4998 void Assembler::lea(Register dst, Address src) {
4999 leaq(dst, src);
5000 }
5002 void Assembler::leaq(Register dst, Address src) {
5003 InstructionMark im(this);
5004 prefixq(src, dst);
5005 emit_int8((unsigned char)0x8D);
5006 emit_operand(dst, src);
5007 }
5009 void Assembler::mov64(Register dst, int64_t imm64) {
5010 InstructionMark im(this);
5011 int encode = prefixq_and_encode(dst->encoding());
5012 emit_int8((unsigned char)(0xB8 | encode));
5013 emit_int64(imm64);
5014 }
5016 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5017 InstructionMark im(this);
5018 int encode = prefixq_and_encode(dst->encoding());
5019 emit_int8(0xB8 | encode);
5020 emit_data64(imm64, rspec);
5021 }
5023 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5024 InstructionMark im(this);
5025 int encode = prefix_and_encode(dst->encoding());
5026 emit_int8((unsigned char)(0xB8 | encode));
5027 emit_data((int)imm32, rspec, narrow_oop_operand);
5028 }
5030 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5031 InstructionMark im(this);
5032 prefix(dst);
5033 emit_int8((unsigned char)0xC7);
5034 emit_operand(rax, dst, 4);
5035 emit_data((int)imm32, rspec, narrow_oop_operand);
5036 }
5038 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5039 InstructionMark im(this);
5040 int encode = prefix_and_encode(src1->encoding());
5041 emit_int8((unsigned char)0x81);
5042 emit_int8((unsigned char)(0xF8 | encode));
5043 emit_data((int)imm32, rspec, narrow_oop_operand);
5044 }
5046 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5047 InstructionMark im(this);
5048 prefix(src1);
5049 emit_int8((unsigned char)0x81);
5050 emit_operand(rax, src1, 4);
5051 emit_data((int)imm32, rspec, narrow_oop_operand);
5052 }
5054 void Assembler::lzcntq(Register dst, Register src) {
5055 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5056 emit_int8((unsigned char)0xF3);
5057 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5058 emit_int8(0x0F);
5059 emit_int8((unsigned char)0xBD);
5060 emit_int8((unsigned char)(0xC0 | encode));
5061 }
5063 void Assembler::movdq(XMMRegister dst, Register src) {
5064 // table D-1 says MMX/SSE2
5065 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5066 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5067 emit_int8(0x6E);
5068 emit_int8((unsigned char)(0xC0 | encode));
5069 }
5071 void Assembler::movdq(Register dst, XMMRegister src) {
5072 // table D-1 says MMX/SSE2
5073 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5074 // swap src/dst to get correct prefix
5075 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5076 emit_int8(0x7E);
5077 emit_int8((unsigned char)(0xC0 | encode));
5078 }
5080 void Assembler::movq(Register dst, Register src) {
5081 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5082 emit_int8((unsigned char)0x8B);
5083 emit_int8((unsigned char)(0xC0 | encode));
5084 }
5086 void Assembler::movq(Register dst, Address src) {
5087 InstructionMark im(this);
5088 prefixq(src, dst);
5089 emit_int8((unsigned char)0x8B);
5090 emit_operand(dst, src);
5091 }
5093 void Assembler::movq(Address dst, Register src) {
5094 InstructionMark im(this);
5095 prefixq(dst, src);
5096 emit_int8((unsigned char)0x89);
5097 emit_operand(src, dst);
5098 }
5100 void Assembler::movsbq(Register dst, Address src) {
5101 InstructionMark im(this);
5102 prefixq(src, dst);
5103 emit_int8(0x0F);
5104 emit_int8((unsigned char)0xBE);
5105 emit_operand(dst, src);
5106 }
5108 void Assembler::movsbq(Register dst, Register src) {
5109 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5110 emit_int8(0x0F);
5111 emit_int8((unsigned char)0xBE);
5112 emit_int8((unsigned char)(0xC0 | encode));
5113 }
5115 void Assembler::movslq(Register dst, int32_t imm32) {
5116 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5117 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5118 // as a result we shouldn't use until tested at runtime...
5119 ShouldNotReachHere();
5120 InstructionMark im(this);
5121 int encode = prefixq_and_encode(dst->encoding());
5122 emit_int8((unsigned char)(0xC7 | encode));
5123 emit_int32(imm32);
5124 }
5126 void Assembler::movslq(Address dst, int32_t imm32) {
5127 assert(is_simm32(imm32), "lost bits");
5128 InstructionMark im(this);
5129 prefixq(dst);
5130 emit_int8((unsigned char)0xC7);
5131 emit_operand(rax, dst, 4);
5132 emit_int32(imm32);
5133 }
5135 void Assembler::movslq(Register dst, Address src) {
5136 InstructionMark im(this);
5137 prefixq(src, dst);
5138 emit_int8(0x63);
5139 emit_operand(dst, src);
5140 }
5142 void Assembler::movslq(Register dst, Register src) {
5143 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5144 emit_int8(0x63);
5145 emit_int8((unsigned char)(0xC0 | encode));
5146 }
5148 void Assembler::movswq(Register dst, Address src) {
5149 InstructionMark im(this);
5150 prefixq(src, dst);
5151 emit_int8(0x0F);
5152 emit_int8((unsigned char)0xBF);
5153 emit_operand(dst, src);
5154 }
5156 void Assembler::movswq(Register dst, Register src) {
5157 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5158 emit_int8((unsigned char)0x0F);
5159 emit_int8((unsigned char)0xBF);
5160 emit_int8((unsigned char)(0xC0 | encode));
5161 }
5163 void Assembler::movzbq(Register dst, Address src) {
5164 InstructionMark im(this);
5165 prefixq(src, dst);
5166 emit_int8((unsigned char)0x0F);
5167 emit_int8((unsigned char)0xB6);
5168 emit_operand(dst, src);
5169 }
5171 void Assembler::movzbq(Register dst, Register src) {
5172 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5173 emit_int8(0x0F);
5174 emit_int8((unsigned char)0xB6);
5175 emit_int8(0xC0 | encode);
5176 }
5178 void Assembler::movzwq(Register dst, Address src) {
5179 InstructionMark im(this);
5180 prefixq(src, dst);
5181 emit_int8((unsigned char)0x0F);
5182 emit_int8((unsigned char)0xB7);
5183 emit_operand(dst, src);
5184 }
5186 void Assembler::movzwq(Register dst, Register src) {
5187 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5188 emit_int8((unsigned char)0x0F);
5189 emit_int8((unsigned char)0xB7);
5190 emit_int8((unsigned char)(0xC0 | encode));
5191 }
5193 void Assembler::negq(Register dst) {
5194 int encode = prefixq_and_encode(dst->encoding());
5195 emit_int8((unsigned char)0xF7);
5196 emit_int8((unsigned char)(0xD8 | encode));
5197 }
5199 void Assembler::notq(Register dst) {
5200 int encode = prefixq_and_encode(dst->encoding());
5201 emit_int8((unsigned char)0xF7);
5202 emit_int8((unsigned char)(0xD0 | encode));
5203 }
5205 void Assembler::orq(Address dst, int32_t imm32) {
5206 InstructionMark im(this);
5207 prefixq(dst);
5208 emit_int8((unsigned char)0x81);
5209 emit_operand(rcx, dst, 4);
5210 emit_int32(imm32);
5211 }
5213 void Assembler::orq(Register dst, int32_t imm32) {
5214 (void) prefixq_and_encode(dst->encoding());
5215 emit_arith(0x81, 0xC8, dst, imm32);
5216 }
5218 void Assembler::orq(Register dst, Address src) {
5219 InstructionMark im(this);
5220 prefixq(src, dst);
5221 emit_int8(0x0B);
5222 emit_operand(dst, src);
5223 }
5225 void Assembler::orq(Register dst, Register src) {
5226 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5227 emit_arith(0x0B, 0xC0, dst, src);
5228 }
5230 void Assembler::popa() { // 64bit
5231 movq(r15, Address(rsp, 0));
5232 movq(r14, Address(rsp, wordSize));
5233 movq(r13, Address(rsp, 2 * wordSize));
5234 movq(r12, Address(rsp, 3 * wordSize));
5235 movq(r11, Address(rsp, 4 * wordSize));
5236 movq(r10, Address(rsp, 5 * wordSize));
5237 movq(r9, Address(rsp, 6 * wordSize));
5238 movq(r8, Address(rsp, 7 * wordSize));
5239 movq(rdi, Address(rsp, 8 * wordSize));
5240 movq(rsi, Address(rsp, 9 * wordSize));
5241 movq(rbp, Address(rsp, 10 * wordSize));
5242 // skip rsp
5243 movq(rbx, Address(rsp, 12 * wordSize));
5244 movq(rdx, Address(rsp, 13 * wordSize));
5245 movq(rcx, Address(rsp, 14 * wordSize));
5246 movq(rax, Address(rsp, 15 * wordSize));
5248 addq(rsp, 16 * wordSize);
5249 }
5251 void Assembler::popcntq(Register dst, Address src) {
5252 assert(VM_Version::supports_popcnt(), "must support");
5253 InstructionMark im(this);
5254 emit_int8((unsigned char)0xF3);
5255 prefixq(src, dst);
5256 emit_int8((unsigned char)0x0F);
5257 emit_int8((unsigned char)0xB8);
5258 emit_operand(dst, src);
5259 }
5261 void Assembler::popcntq(Register dst, Register src) {
5262 assert(VM_Version::supports_popcnt(), "must support");
5263 emit_int8((unsigned char)0xF3);
5264 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5265 emit_int8((unsigned char)0x0F);
5266 emit_int8((unsigned char)0xB8);
5267 emit_int8((unsigned char)(0xC0 | encode));
5268 }
5270 void Assembler::popq(Address dst) {
5271 InstructionMark im(this);
5272 prefixq(dst);
5273 emit_int8((unsigned char)0x8F);
5274 emit_operand(rax, dst);
5275 }
5277 void Assembler::pusha() { // 64bit
5278 // we have to store original rsp. ABI says that 128 bytes
5279 // below rsp are local scratch.
5280 movq(Address(rsp, -5 * wordSize), rsp);
5282 subq(rsp, 16 * wordSize);
5284 movq(Address(rsp, 15 * wordSize), rax);
5285 movq(Address(rsp, 14 * wordSize), rcx);
5286 movq(Address(rsp, 13 * wordSize), rdx);
5287 movq(Address(rsp, 12 * wordSize), rbx);
5288 // skip rsp
5289 movq(Address(rsp, 10 * wordSize), rbp);
5290 movq(Address(rsp, 9 * wordSize), rsi);
5291 movq(Address(rsp, 8 * wordSize), rdi);
5292 movq(Address(rsp, 7 * wordSize), r8);
5293 movq(Address(rsp, 6 * wordSize), r9);
5294 movq(Address(rsp, 5 * wordSize), r10);
5295 movq(Address(rsp, 4 * wordSize), r11);
5296 movq(Address(rsp, 3 * wordSize), r12);
5297 movq(Address(rsp, 2 * wordSize), r13);
5298 movq(Address(rsp, wordSize), r14);
5299 movq(Address(rsp, 0), r15);
5300 }
5302 void Assembler::pushq(Address src) {
5303 InstructionMark im(this);
5304 prefixq(src);
5305 emit_int8((unsigned char)0xFF);
5306 emit_operand(rsi, src);
5307 }
5309 void Assembler::rclq(Register dst, int imm8) {
5310 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5311 int encode = prefixq_and_encode(dst->encoding());
5312 if (imm8 == 1) {
5313 emit_int8((unsigned char)0xD1);
5314 emit_int8((unsigned char)(0xD0 | encode));
5315 } else {
5316 emit_int8((unsigned char)0xC1);
5317 emit_int8((unsigned char)(0xD0 | encode));
5318 emit_int8(imm8);
5319 }
5320 }
5321 void Assembler::sarq(Register dst, int imm8) {
5322 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5323 int encode = prefixq_and_encode(dst->encoding());
5324 if (imm8 == 1) {
5325 emit_int8((unsigned char)0xD1);
5326 emit_int8((unsigned char)(0xF8 | encode));
5327 } else {
5328 emit_int8((unsigned char)0xC1);
5329 emit_int8((unsigned char)(0xF8 | encode));
5330 emit_int8(imm8);
5331 }
5332 }
5334 void Assembler::sarq(Register dst) {
5335 int encode = prefixq_and_encode(dst->encoding());
5336 emit_int8((unsigned char)0xD3);
5337 emit_int8((unsigned char)(0xF8 | encode));
5338 }
5340 void Assembler::sbbq(Address dst, int32_t imm32) {
5341 InstructionMark im(this);
5342 prefixq(dst);
5343 emit_arith_operand(0x81, rbx, dst, imm32);
5344 }
5346 void Assembler::sbbq(Register dst, int32_t imm32) {
5347 (void) prefixq_and_encode(dst->encoding());
5348 emit_arith(0x81, 0xD8, dst, imm32);
5349 }
5351 void Assembler::sbbq(Register dst, Address src) {
5352 InstructionMark im(this);
5353 prefixq(src, dst);
5354 emit_int8(0x1B);
5355 emit_operand(dst, src);
5356 }
5358 void Assembler::sbbq(Register dst, Register src) {
5359 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5360 emit_arith(0x1B, 0xC0, dst, src);
5361 }
5363 void Assembler::shlq(Register dst, int imm8) {
5364 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5365 int encode = prefixq_and_encode(dst->encoding());
5366 if (imm8 == 1) {
5367 emit_int8((unsigned char)0xD1);
5368 emit_int8((unsigned char)(0xE0 | encode));
5369 } else {
5370 emit_int8((unsigned char)0xC1);
5371 emit_int8((unsigned char)(0xE0 | encode));
5372 emit_int8(imm8);
5373 }
5374 }
5376 void Assembler::shlq(Register dst) {
5377 int encode = prefixq_and_encode(dst->encoding());
5378 emit_int8((unsigned char)0xD3);
5379 emit_int8((unsigned char)(0xE0 | encode));
5380 }
5382 void Assembler::shrq(Register dst, int imm8) {
5383 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5384 int encode = prefixq_and_encode(dst->encoding());
5385 emit_int8((unsigned char)0xC1);
5386 emit_int8((unsigned char)(0xE8 | encode));
5387 emit_int8(imm8);
5388 }
5390 void Assembler::shrq(Register dst) {
5391 int encode = prefixq_and_encode(dst->encoding());
5392 emit_int8((unsigned char)0xD3);
5393 emit_int8(0xE8 | encode);
5394 }
5396 void Assembler::subq(Address dst, int32_t imm32) {
5397 InstructionMark im(this);
5398 prefixq(dst);
5399 emit_arith_operand(0x81, rbp, dst, imm32);
5400 }
5402 void Assembler::subq(Address dst, Register src) {
5403 InstructionMark im(this);
5404 prefixq(dst, src);
5405 emit_int8(0x29);
5406 emit_operand(src, dst);
5407 }
5409 void Assembler::subq(Register dst, int32_t imm32) {
5410 (void) prefixq_and_encode(dst->encoding());
5411 emit_arith(0x81, 0xE8, dst, imm32);
5412 }
5414 // Force generation of a 4 byte immediate value even if it fits into 8bit
5415 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5416 (void) prefixq_and_encode(dst->encoding());
5417 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5418 }
5420 void Assembler::subq(Register dst, Address src) {
5421 InstructionMark im(this);
5422 prefixq(src, dst);
5423 emit_int8(0x2B);
5424 emit_operand(dst, src);
5425 }
5427 void Assembler::subq(Register dst, Register src) {
5428 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5429 emit_arith(0x2B, 0xC0, dst, src);
5430 }
5432 void Assembler::testq(Register dst, int32_t imm32) {
5433 // not using emit_arith because test
5434 // doesn't support sign-extension of
5435 // 8bit operands
5436 int encode = dst->encoding();
5437 if (encode == 0) {
5438 prefix(REX_W);
5439 emit_int8((unsigned char)0xA9);
5440 } else {
5441 encode = prefixq_and_encode(encode);
5442 emit_int8((unsigned char)0xF7);
5443 emit_int8((unsigned char)(0xC0 | encode));
5444 }
5445 emit_int32(imm32);
5446 }
5448 void Assembler::testq(Register dst, Register src) {
5449 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5450 emit_arith(0x85, 0xC0, dst, src);
5451 }
5453 void Assembler::xaddq(Address dst, Register src) {
5454 InstructionMark im(this);
5455 prefixq(dst, src);
5456 emit_int8(0x0F);
5457 emit_int8((unsigned char)0xC1);
5458 emit_operand(src, dst);
5459 }
5461 void Assembler::xchgq(Register dst, Address src) {
5462 InstructionMark im(this);
5463 prefixq(src, dst);
5464 emit_int8((unsigned char)0x87);
5465 emit_operand(dst, src);
5466 }
5468 void Assembler::xchgq(Register dst, Register src) {
5469 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5470 emit_int8((unsigned char)0x87);
5471 emit_int8((unsigned char)(0xc0 | encode));
5472 }
5474 void Assembler::xorq(Register dst, Register src) {
5475 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5476 emit_arith(0x33, 0xC0, dst, src);
5477 }
5479 void Assembler::xorq(Register dst, Address src) {
5480 InstructionMark im(this);
5481 prefixq(src, dst);
5482 emit_int8(0x33);
5483 emit_operand(dst, src);
5484 }
5486 #endif // !LP64