src/cpu/mips/vm/c1_Runtime1_mips.cpp

Tue, 05 Mar 2019 17:00:17 +0800

author
aoqi
date
Tue, 05 Mar 2019 17:00:17 +0800
changeset 9459
814e9e335067
parent 9251
1ccc5a3b3671
child 9645
ac996ba07f9d
permissions
-rw-r--r--

#8573 Cleanup: x86 registers in comments; comment style; deadcode
Reviewed-by: zhaixiang

     1 /*
     2  * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
     3  * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
     4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
     5  *
     6  * This code is free software; you can redistribute it and/or modify it
     7  * under the terms of the GNU General Public License version 2 only, as
     8  * published by the Free Software Foundation.
     9  *
    10  * This code is distributed in the hope that it will be useful, but WITHOUT
    11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
    13  * version 2 for more details (a copy is included in the LICENSE file that
    14  * accompanied this code).
    15  *
    16  * You should have received a copy of the GNU General Public License version
    17  * 2 along with this work; if not, write to the Free Software Foundation,
    18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
    19  *
    20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
    21  * or visit www.oracle.com if you need additional information or have any
    22  * questions.
    23  *
    24  */
    26 #include "precompiled.hpp"
    27 #include "asm/assembler.hpp"
    28 #include "c1/c1_Defs.hpp"
    29 #include "c1/c1_MacroAssembler.hpp"
    30 #include "c1/c1_Runtime1.hpp"
    31 #include "interpreter/interpreter.hpp"
    32 #include "nativeInst_mips.hpp"
    33 #include "oops/compiledICHolder.hpp"
    34 #include "oops/oop.inline.hpp"
    35 #include "prims/jvmtiExport.hpp"
    36 #include "register_mips.hpp"
    37 #include "runtime/sharedRuntime.hpp"
    38 #include "runtime/signature.hpp"
    39 #include "runtime/vframeArray.hpp"
    40 #include "utilities/macros.hpp"
    41 #include "vmreg_mips.inline.hpp"
    42 #if INCLUDE_ALL_GCS
    43 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
    44 #endif
    47 // Implementation of StubAssembler
    48 // this method will preserve the stack space for arguments as indicated by args_size
    49 // for stack alignment consideration, you cannot call this with argument in stack.
    50 // if you need >3 arguments, you must implement this method yourself.
    51 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
    52   // setup registers
    53   const Register thread = TREG; // is callee-saved register (Visual C++ calling conventions)
    54   assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result,                            "registers must be different");
    55   assert(oop_result1 != thread && metadata_result != thread, "registers must be different");
    56   assert(args_size >= 0, "illegal args_size");
    57   bool align_stack = false;
    58 #ifdef _LP64
    59   // At a method handle call, the stack may not be properly aligned
    60   // when returning with an exception.
    61   align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
    62 #endif
    64   set_num_rt_args(1 + args_size);
    67   // push java thread (becomes first argument of C function)
    68   get_thread(thread);
    69   move(A0, thread);
    71   if(!align_stack) {
    72     set_last_Java_frame(thread, NOREG, FP, NULL);
    73   } else {
    74     address the_pc = pc();
    75     set_last_Java_frame(thread, NOREG, FP, the_pc);
    76     move(AT, -(StackAlignmentInBytes));
    77     andr(SP, SP, AT);
    78   }
    80   relocate(relocInfo::internal_pc_type);
    81   {
    82 #ifndef _LP64
    83     int save_pc = (int)pc() +  12 + NativeCall::return_address_offset;
    84     lui(AT, Assembler::split_high(save_pc));
    85     addiu(AT, AT, Assembler::split_low(save_pc));
    86 #else
    87     uintptr_t save_pc = (uintptr_t)pc() + NativeMovConstReg::instruction_size + 1 * BytesPerInstWord + NativeCall::return_address_offset_long;
    88     li48(AT, save_pc);
    89 #endif
    90   }
    91   st_ptr(AT, thread, in_bytes(JavaThread::last_Java_pc_offset()));
    93   // do the call
    94 #ifndef _LP64
    95   lui(T9, Assembler::split_high((int)entry));
    96   addiu(T9, T9, Assembler::split_low((int)entry));
    97 #else
    98   li48(T9, (intptr_t)entry);
    99 #endif
   100   jalr(T9);
   101   delayed()->nop();
   103   int call_offset = offset();
   105   // verify callee-saved register
   106 #ifdef ASSERT
   107   guarantee(thread != V0, "change this code");
   108   push(V0);
   109   {
   110     Label L;
   111     get_thread(V0);
   112     beq(thread, V0, L);
   113     delayed()->nop();
   114     int3();
   115     stop("StubAssembler::call_RT: TREG not callee saved?");
   116     bind(L);
   117   }
   118   super_pop(V0);
   119 #endif
   120   // discard thread and arguments
   121   ld_ptr(SP, thread, in_bytes(JavaThread::last_Java_sp_offset()));
   122   reset_last_Java_frame(thread, true);
   123   // check for pending exceptions
   124   {
   125     Label L;
   126     ld_ptr(AT, thread, in_bytes(Thread::pending_exception_offset()));
   127     beq(AT, R0, L);
   128     delayed()->nop();
   129     // exception pending => remove activation and forward to exception handler
   130     // make sure that the vm_results are cleared
   131     if (oop_result1->is_valid()) {
   132       st_ptr(R0, thread, in_bytes(JavaThread::vm_result_offset()));
   133     }
   134     if (metadata_result->is_valid()) {
   135       st_ptr(R0, thread, in_bytes(JavaThread::vm_result_2_offset()));
   136     }
   137     // the leave() in x86 just pops ebp and remains the return address on the top
   138     // of stack
   139     // the return address will be needed by forward_exception_entry()
   140     if (frame_size() == no_frame_size) {
   141       addiu(SP, FP, wordSize);
   142       ld_ptr(FP, SP, (-1) * wordSize);
   143       jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
   144       delayed()->nop();
   145     } else if (_stub_id == Runtime1::forward_exception_id) {
   146       should_not_reach_here();
   147     } else {
   148       jmp(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type);
   149       delayed()->nop();
   150     }
   151     bind(L);
   152   }
   153   // get oop results if there are any and reset the values in the thread
   154   if (oop_result1->is_valid()) {
   155     ld_ptr(oop_result1, thread, in_bytes(JavaThread::vm_result_offset()));
   156     st_ptr(R0, thread, in_bytes(JavaThread::vm_result_offset()));
   157     verify_oop(oop_result1);
   158   }
   159   if (metadata_result->is_valid()) {
   160     ld_ptr(metadata_result, thread, in_bytes(JavaThread::vm_result_2_offset()));
   161     st_ptr(R0, thread, in_bytes(JavaThread::vm_result_2_offset()));
   162     verify_oop(metadata_result);
   163   }
   164   return call_offset;
   165 }
   168 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
   169   if (arg1 != A1) move(A1, arg1);
   170   return call_RT(oop_result1, metadata_result, entry, 1);
   171 }
   174 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
   175   if (arg1!=A1) move(A1, arg1);
   176   if (arg2!=A2) move(A2, arg2); assert(arg2 != A1, "smashed argument");
   177   return call_RT(oop_result1, metadata_result, entry, 2);
   178 }
   181 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
   182   if (arg1!=A1) move(A1, arg1);
   183   if (arg2!=A2) move(A2, arg2); assert(arg2 != A1, "smashed argument");
   184   if (arg3!=A3) move(A3, arg3); assert(arg3 != A1 && arg3 != A2, "smashed argument");
   185   return call_RT(oop_result1, metadata_result, entry, 3);
   186 }
   189 // Implementation of StubFrame
   191 class StubFrame: public StackObj {
   192  private:
   193   StubAssembler* _sasm;
   195  public:
   196   StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
   197   void load_argument(int offset_in_words, Register reg);
   199   ~StubFrame();
   200 };
   203 #define __ _sasm->
   205 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
   206   _sasm = sasm;
   207   __ set_info(name, must_gc_arguments);
   208   __ enter();
   209 }
   212 //FIXME, I have no idea the frame architecture of mips
   213 // load parameters that were stored with LIR_Assembler::store_parameter
   214 // Note: offsets for store_parameter and load_argument must match
   215 void StubFrame::load_argument(int offset_in_words, Register reg) {
   216   //fp, + 0: link
   217   //    + 1: return address
   218   //    + 2: argument with offset 0
   219   //    + 3: argument with offset 1
   220   //    + 4: ...
   221   __ ld_ptr(reg, Address(FP, (offset_in_words + 2) * BytesPerWord));
   222 }
   225 StubFrame::~StubFrame() {
   226   __ leave();
   227   __ jr(RA);
   228   __ delayed()->nop();
   229 }
   231 #undef __
   234 // Implementation of Runtime1
   236 #define __ sasm->
   238 const int float_regs_as_doubles_size_in_words = 16;
   240 //FIXME,
   241 // Stack layout for saving/restoring  all the registers needed during a runtime
   242 // call (this includes deoptimization)
   243 // Note: note that users of this frame may well have arguments to some runtime
   244 // while these values are on the stack. These positions neglect those arguments
   245 // but the code in save_live_registers will take the argument count into
   246 // account.
   247 //
   248 #ifdef _LP64
   249   #define SLOT2(x) x,
   250   #define SLOT_PER_WORD 2
   251 #else
   252   #define SLOT2(x)
   253   #define SLOT_PER_WORD 1
   254 #endif // _LP64
   256 enum reg_save_layout {
   257 #ifndef _LP64
   258   T0_off = 0,
   259   S0_off = T0_off + SLOT_PER_WORD * 8,
   260 #else
   261   A4_off = 0,
   262   S0_off = A4_off + SLOT_PER_WORD * 8,
   263 #endif
   264   FP_off = S0_off + SLOT_PER_WORD * 8, SLOT2(FPH_off)
   265   T8_off, SLOT2(T8H_off)
   266   T9_off, SLOT2(T9H_off)
   267   SP_off, SLOT2(SPH_off)
   268   V0_off, SLOT2(V0H_off)
   269   V1_off, SLOT2(V1H_off)
   270   A0_off, SLOT2(A0H_off)
   271   A1_off, SLOT2(A1H_off)
   272   A2_off, SLOT2(A2H_off)
   273   A3_off, SLOT2(A3H_off)
   275   // Float registers
   276   // FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers
   277   F0_off, SLOT2( F0H_off)
   278   F1_off, SLOT2( F1H_off)
   279   F2_off, SLOT2( F2H_off)
   280   F3_off, SLOT2( F3H_off)
   281   F4_off, SLOT2( F4H_off)
   282   F5_off, SLOT2( F5H_off)
   283   F6_off, SLOT2( F6H_off)
   284   F7_off, SLOT2( F7H_off)
   285   F8_off, SLOT2( F8H_off)
   286   F9_off, SLOT2( F9H_off)
   287   F10_off, SLOT2( F10H_off)
   288   F11_off, SLOT2( F11H_off)
   289   F12_off, SLOT2( F12H_off)
   290   F13_off, SLOT2( F13H_off)
   291   F14_off, SLOT2( F14H_off)
   292   F15_off, SLOT2( F15H_off)
   293   F16_off, SLOT2( F16H_off)
   294   F17_off, SLOT2( F17H_off)
   295   F18_off, SLOT2( F18H_off)
   296   F19_off, SLOT2( F19H_off)
   298   GP_off, SLOT2( GPH_off)
   299   //temp_2_off,
   300   temp_1_off, SLOT2(temp_1H_off)
   301   saved_fp_off, SLOT2(saved_fpH_off)
   302   return_off, SLOT2(returnH_off)
   304   reg_save_frame_size,
   306   // illegal instruction handler
   307   continue_dest_off = temp_1_off,
   309   // deoptimization equates
   310   //deopt_type = temp_2_off,             // slot for type of deopt in progress
   311   ret_type = temp_1_off                // slot for return type
   312 };
   316 // Save off registers which might be killed by calls into the runtime.
   317 // Tries to smart of about FP registers.  In particular we separate
   318 // saving and describing the FPU registers for deoptimization since we
   319 // have to save the FPU registers twice if we describe them and on P4
   320 // saving FPU registers which don't contain anything appears
   321 // expensive.  The deopt blob is the only thing which needs to
   322 // describe FPU registers.  In all other cases it should be sufficient
   323 // to simply save their current value.
   324 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
   325                                 bool save_fpu_registers = true, bool describe_fpu_registers = false) {
   327   LP64_ONLY(num_rt_args = 0);
   328   LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
   329   int frame_size_in_slots = reg_save_frame_size + num_rt_args * wordSize / VMRegImpl::slots_per_word;   // args + thread
   330   sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word);
   332   // record saved value locations in an OopMap
   333   // locations are offsets from sp after runtime call; num_rt_args is number of arguments
   334   // in call, including thread
   335   OopMap* map = new OopMap(reg_save_frame_size, 0);
   337   map->set_callee_saved(VMRegImpl::stack2reg(V0_off + num_rt_args), V0->as_VMReg());
   338   map->set_callee_saved(VMRegImpl::stack2reg(V1_off + num_rt_args), V1->as_VMReg());
   339 #ifdef _LP64
   340   map->set_callee_saved(VMRegImpl::stack2reg(V0H_off + num_rt_args), V0->as_VMReg()->next());
   341   map->set_callee_saved(VMRegImpl::stack2reg(V1H_off + num_rt_args), V1->as_VMReg()->next());
   342 #endif
   344   int i = 0;
   345 #ifndef _LP64
   346   for (Register r = T0; r != T7->successor(); r = r->successor() ) {
   347     map->set_callee_saved(VMRegImpl::stack2reg(T0_off + num_rt_args + i++), r->as_VMReg());
   348   }
   349 #else
   350   for (Register r = A4; r != T3->successor(); r = r->successor() ) {
   351     map->set_callee_saved(VMRegImpl::stack2reg(A4_off + num_rt_args + i++), r->as_VMReg());
   352     map->set_callee_saved(VMRegImpl::stack2reg(A4_off + num_rt_args + i++), r->as_VMReg()->next());
   353   }
   354 #endif
   356   i = 0;
   357   for (Register r = S0; r != S7->successor(); r = r->successor() ) {
   358     map->set_callee_saved(VMRegImpl::stack2reg(S0_off + num_rt_args + i++), r->as_VMReg());
   359 #ifdef _LP64
   360     map->set_callee_saved(VMRegImpl::stack2reg(S0_off + num_rt_args + i++), r->as_VMReg()->next());
   361 #endif
   362   }
   364   map->set_callee_saved(VMRegImpl::stack2reg(FP_off + num_rt_args), FP->as_VMReg());
   365   map->set_callee_saved(VMRegImpl::stack2reg(GP_off + num_rt_args), GP->as_VMReg());
   366   map->set_callee_saved(VMRegImpl::stack2reg(T8_off + num_rt_args), T8->as_VMReg());
   367   map->set_callee_saved(VMRegImpl::stack2reg(T9_off + num_rt_args), T9->as_VMReg());
   368   map->set_callee_saved(VMRegImpl::stack2reg(A0_off + num_rt_args), A0->as_VMReg());
   369   map->set_callee_saved(VMRegImpl::stack2reg(A1_off + num_rt_args), A1->as_VMReg());
   370   map->set_callee_saved(VMRegImpl::stack2reg(A2_off + num_rt_args), A2->as_VMReg());
   371   map->set_callee_saved(VMRegImpl::stack2reg(A3_off + num_rt_args), A3->as_VMReg());
   373   map->set_callee_saved(VMRegImpl::stack2reg(F0_off + num_rt_args), F0->as_VMReg());
   374   map->set_callee_saved(VMRegImpl::stack2reg(F1_off + num_rt_args), F1->as_VMReg());
   375   map->set_callee_saved(VMRegImpl::stack2reg(F2_off + num_rt_args), F2->as_VMReg());
   376   map->set_callee_saved(VMRegImpl::stack2reg(F3_off + num_rt_args), F1->as_VMReg());
   377   map->set_callee_saved(VMRegImpl::stack2reg(F4_off + num_rt_args), F4->as_VMReg());
   378   map->set_callee_saved(VMRegImpl::stack2reg(F5_off + num_rt_args), F4->as_VMReg());
   379   map->set_callee_saved(VMRegImpl::stack2reg(F6_off + num_rt_args), F4->as_VMReg());
   380   map->set_callee_saved(VMRegImpl::stack2reg(F7_off + num_rt_args), F4->as_VMReg());
   381   map->set_callee_saved(VMRegImpl::stack2reg(F8_off + num_rt_args), F4->as_VMReg());
   382   map->set_callee_saved(VMRegImpl::stack2reg(F9_off + num_rt_args), F4->as_VMReg());
   383   map->set_callee_saved(VMRegImpl::stack2reg(F10_off + num_rt_args), F4->as_VMReg());
   384   map->set_callee_saved(VMRegImpl::stack2reg(F11_off + num_rt_args), F4->as_VMReg());
   385   map->set_callee_saved(VMRegImpl::stack2reg(F12_off + num_rt_args), F12->as_VMReg());
   386   map->set_callee_saved(VMRegImpl::stack2reg(F13_off + num_rt_args), F13->as_VMReg());
   387   map->set_callee_saved(VMRegImpl::stack2reg(F14_off + num_rt_args), F14->as_VMReg());
   388   map->set_callee_saved(VMRegImpl::stack2reg(F15_off + num_rt_args), F15->as_VMReg());
   389   map->set_callee_saved(VMRegImpl::stack2reg(F16_off + num_rt_args), F16->as_VMReg());
   390   map->set_callee_saved(VMRegImpl::stack2reg(F17_off + num_rt_args), F17->as_VMReg());
   391   map->set_callee_saved(VMRegImpl::stack2reg(F18_off + num_rt_args), F18->as_VMReg());
   392   map->set_callee_saved(VMRegImpl::stack2reg(F19_off + num_rt_args), F19->as_VMReg());
   394 #ifdef _LP64
   395   map->set_callee_saved(VMRegImpl::stack2reg(FPH_off + num_rt_args), FP->as_VMReg()->next());
   396   map->set_callee_saved(VMRegImpl::stack2reg(GPH_off + num_rt_args), GP->as_VMReg()->next());
   397   map->set_callee_saved(VMRegImpl::stack2reg(T8H_off + num_rt_args), T8->as_VMReg()->next());
   398   map->set_callee_saved(VMRegImpl::stack2reg(T9H_off + num_rt_args), T9->as_VMReg()->next());
   399   map->set_callee_saved(VMRegImpl::stack2reg(A0H_off + num_rt_args), A0->as_VMReg()->next());
   400   map->set_callee_saved(VMRegImpl::stack2reg(A1H_off + num_rt_args), A1->as_VMReg()->next());
   401   map->set_callee_saved(VMRegImpl::stack2reg(A2H_off + num_rt_args), A2->as_VMReg()->next());
   402   map->set_callee_saved(VMRegImpl::stack2reg(A3H_off + num_rt_args), A3->as_VMReg()->next());
   403 #endif
   404   return map;
   405 }
   407 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
   408                                    bool save_fpu_registers = true,
   409                                    bool describe_fpu_registers = false) {
   410   //const int reg_save_frame_size = return_off + 1 + num_rt_args;
   411   __ block_comment("save_live_registers");
   413   // save all register state - int, fpu
   414   __ addi(SP, SP, -(reg_save_frame_size / SLOT_PER_WORD - 2)* wordSize);
   416 #ifndef _LP64
   417   for (Register r = T0; r != T7->successor(); r = r->successor() ) {
   418     __ sw(r, SP, (r->encoding() - T0->encoding() + T0_off / SLOT_PER_WORD) * wordSize);
   419 #else
   420   for (Register r = A4; r != T3->successor(); r = r->successor() ) {
   421     __ sd(r, SP, (r->encoding() - A4->encoding() + A4_off / SLOT_PER_WORD) * wordSize);
   422 #endif
   423   }
   424   for (Register r = S0; r != S7->successor(); r = r->successor() ) {
   425     __ st_ptr(r, SP, (r->encoding() - S0->encoding() + S0_off / SLOT_PER_WORD) * wordSize);
   426   }
   427   __ st_ptr(FP, SP, FP_off * wordSize / SLOT_PER_WORD);
   428   __ st_ptr(GP, SP, GP_off * wordSize / SLOT_PER_WORD);
   429   __ st_ptr(T8, SP, T8_off * wordSize / SLOT_PER_WORD);
   430   __ st_ptr(T9, SP, T9_off * wordSize / SLOT_PER_WORD);
   431   __ st_ptr(A0, SP, A0_off * wordSize / SLOT_PER_WORD);
   432   __ st_ptr(A1, SP, A1_off * wordSize / SLOT_PER_WORD);
   433   __ st_ptr(A2, SP, A2_off * wordSize / SLOT_PER_WORD);
   434   __ st_ptr(A3, SP, A3_off * wordSize / SLOT_PER_WORD);
   435   __ st_ptr(V0, SP, V0_off * wordSize / SLOT_PER_WORD);
   436   __ st_ptr(V1, SP, V1_off * wordSize / SLOT_PER_WORD);
   438   __ sdc1(F0, SP, F0_off * wordSize / SLOT_PER_WORD);
   439   __ sdc1(F1, SP, F1_off * wordSize / SLOT_PER_WORD);
   440   __ sdc1(F2, SP, F2_off * wordSize / SLOT_PER_WORD);
   441   __ sdc1(F3, SP, F3_off * wordSize / SLOT_PER_WORD);
   442   __ sdc1(F4, SP, F4_off * wordSize / SLOT_PER_WORD);
   443   __ sdc1(F5, SP, F5_off * wordSize / SLOT_PER_WORD);
   444   __ sdc1(F6, SP, F6_off * wordSize / SLOT_PER_WORD);
   445   __ sdc1(F7, SP, F7_off * wordSize / SLOT_PER_WORD);
   446   __ sdc1(F8, SP, F8_off * wordSize / SLOT_PER_WORD);
   447   __ sdc1(F9, SP, F9_off * wordSize / SLOT_PER_WORD);
   448   __ sdc1(F10, SP, F10_off * wordSize / SLOT_PER_WORD);
   449   __ sdc1(F11, SP, F11_off * wordSize / SLOT_PER_WORD);
   450   __ sdc1(F12, SP, F12_off * wordSize / SLOT_PER_WORD);
   451   __ sdc1(F13, SP, F13_off * wordSize / SLOT_PER_WORD);
   452   __ sdc1(F14, SP, F14_off * wordSize / SLOT_PER_WORD);
   453   __ sdc1(F15, SP, F15_off * wordSize / SLOT_PER_WORD);
   454   __ sdc1(F16, SP, F16_off * wordSize / SLOT_PER_WORD);
   455   __ sdc1(F17, SP, F17_off * wordSize / SLOT_PER_WORD);
   456   __ sdc1(F18, SP, F18_off * wordSize / SLOT_PER_WORD);
   457   __ sdc1(F19, SP, F19_off * wordSize / SLOT_PER_WORD);
   459   return generate_oop_map(sasm, num_rt_args, save_fpu_registers, describe_fpu_registers);
   460 }
   462 static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) {
   463   //static void restore_live_registers(MacroAssembler* sasm) {
   464 #ifndef _LP64
   465   for (Register r = T0; r != T7->successor(); r = r->successor() ) {
   466     __ lw(r, SP, (r->encoding() - T0->encoding() + T0_off / SLOT_PER_WORD) * wordSize);
   467 #else
   468   for (Register r = A4; r != T3->successor(); r = r->successor() ) {
   469     __ ld(r, SP, (r->encoding() - A4->encoding() + A4_off / SLOT_PER_WORD) * wordSize);
   470 #endif
   471   }
   472   for (Register r = S0; r != S7->successor(); r = r->successor() ) {
   473     __ ld_ptr(r, SP, (r->encoding() - S0->encoding() + S0_off / SLOT_PER_WORD) * wordSize);
   474   }
   475   __ ld_ptr(FP, SP, FP_off * wordSize / SLOT_PER_WORD);
   476   __ ld_ptr(GP, SP, GP_off * wordSize / SLOT_PER_WORD);
   478   __ ld_ptr(T8, SP, T8_off * wordSize / SLOT_PER_WORD);
   479   __ ld_ptr(T9, SP, T9_off * wordSize / SLOT_PER_WORD);
   480   __ ld_ptr(A0, SP, A0_off * wordSize / SLOT_PER_WORD);
   481   __ ld_ptr(A1, SP, A1_off * wordSize / SLOT_PER_WORD);
   482   __ ld_ptr(A2, SP, A2_off * wordSize / SLOT_PER_WORD);
   483   __ ld_ptr(A3, SP, A3_off * wordSize / SLOT_PER_WORD);
   485   __ ld_ptr(V0, SP, V0_off * wordSize / SLOT_PER_WORD);
   486   __ ld_ptr(V1, SP, V1_off * wordSize / SLOT_PER_WORD);
   488   __ ldc1(F0, SP, F0_off * wordSize / SLOT_PER_WORD);
   489   __ ldc1(F1, SP, F1_off * wordSize / SLOT_PER_WORD);
   490   __ ldc1(F2, SP, F2_off * wordSize / SLOT_PER_WORD);
   491   __ ldc1(F3, SP, F3_off * wordSize / SLOT_PER_WORD);
   492   __ ldc1(F4, SP, F4_off * wordSize / SLOT_PER_WORD);
   493   __ ldc1(F5, SP, F5_off * wordSize / SLOT_PER_WORD);
   494   __ ldc1(F6, SP, F6_off * wordSize / SLOT_PER_WORD);
   495   __ ldc1(F7, SP, F7_off * wordSize / SLOT_PER_WORD);
   496   __ ldc1(F8, SP, F8_off * wordSize / SLOT_PER_WORD);
   497   __ ldc1(F9, SP, F9_off * wordSize / SLOT_PER_WORD);
   498   __ ldc1(F10, SP, F10_off * wordSize / SLOT_PER_WORD);
   499   __ ldc1(F11, SP, F11_off * wordSize / SLOT_PER_WORD);
   500   __ ldc1(F12, SP, F12_off * wordSize / SLOT_PER_WORD);
   501   __ ldc1(F13, SP, F13_off * wordSize / SLOT_PER_WORD);
   502   __ ldc1(F14, SP, F14_off * wordSize / SLOT_PER_WORD);
   503   __ ldc1(F15, SP, F15_off * wordSize / SLOT_PER_WORD);
   504   __ ldc1(F16, SP, F16_off * wordSize / SLOT_PER_WORD);
   505   __ ldc1(F17, SP, F17_off * wordSize / SLOT_PER_WORD);
   506   __ ldc1(F18, SP, F18_off * wordSize / SLOT_PER_WORD);
   507   __ ldc1(F19, SP, F19_off * wordSize / SLOT_PER_WORD);
   509   __ addiu(SP, SP, (reg_save_frame_size / SLOT_PER_WORD - 2) * wordSize);
   510 }
   512 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
   513   __ block_comment("restore_live_registers");
   514   restore_fpu(sasm, restore_fpu_registers);
   515 }
   517 static void restore_live_registers_except_V0(StubAssembler* sasm, bool restore_fpu_registers = true) {
   518   //static void restore_live_registers(MacroAssembler* sasm) {
   519   //FIXME , maybe V1 need to be saved too
   520   __ block_comment("restore_live_registers except V0");
   521 #ifndef _LP64
   522   for (Register r = T0; r != T7->successor(); r = r->successor() ) {
   523     __ lw(r, SP, (r->encoding() - T0->encoding() + T0_off / SLOT_PER_WORD) * wordSize);
   524 #else
   525   for (Register r = A4; r != T3->successor(); r = r->successor() ) {
   526     __ ld(r, SP, (r->encoding() - A4->encoding() + A4_off / SLOT_PER_WORD) * wordSize);
   527 #endif
   528   }
   529   for (Register r = S0; r != S7->successor(); r = r->successor() ) {
   530     __ ld_ptr(r, SP, (r->encoding() - S0->encoding() + S0_off / SLOT_PER_WORD) * wordSize);
   531   }
   532   __ ld_ptr(FP, SP, FP_off * wordSize / SLOT_PER_WORD);
   533   __ ld_ptr(GP, SP, GP_off * wordSize / SLOT_PER_WORD);
   535   __ ld_ptr(T8, SP, T8_off * wordSize / SLOT_PER_WORD);
   536   __ ld_ptr(T9, SP, T9_off * wordSize / SLOT_PER_WORD);
   537   __ ld_ptr(A0, SP, A0_off * wordSize / SLOT_PER_WORD);
   538   __ ld_ptr(A1, SP, A1_off * wordSize / SLOT_PER_WORD);
   539   __ ld_ptr(A2, SP, A2_off * wordSize / SLOT_PER_WORD);
   540   __ ld_ptr(A3, SP, A3_off * wordSize / SLOT_PER_WORD);
   542 #if 1
   543   __ ldc1(F0, SP, F0_off * wordSize / SLOT_PER_WORD);
   544   __ ldc1(F1, SP, F1_off * wordSize / SLOT_PER_WORD);
   545   __ ldc1(F2, SP, F2_off * wordSize / SLOT_PER_WORD);
   546   __ ldc1(F3, SP, F3_off * wordSize / SLOT_PER_WORD);
   547   __ ldc1(F4, SP, F4_off * wordSize / SLOT_PER_WORD);
   548   __ ldc1(F5, SP, F5_off * wordSize / SLOT_PER_WORD);
   549   __ ldc1(F6, SP, F6_off * wordSize / SLOT_PER_WORD);
   550   __ ldc1(F7, SP, F7_off * wordSize / SLOT_PER_WORD);
   551   __ ldc1(F8, SP, F8_off * wordSize / SLOT_PER_WORD);
   552   __ ldc1(F9, SP, F9_off * wordSize / SLOT_PER_WORD);
   553   __ ldc1(F10, SP, F10_off * wordSize / SLOT_PER_WORD);
   554   __ ldc1(F11, SP, F11_off * wordSize / SLOT_PER_WORD);
   555   __ ldc1(F12, SP, F12_off * wordSize / SLOT_PER_WORD);
   556   __ ldc1(F13, SP, F13_off * wordSize / SLOT_PER_WORD);
   557   __ ldc1(F14, SP, F14_off * wordSize / SLOT_PER_WORD);
   558   __ ldc1(F15, SP, F15_off * wordSize / SLOT_PER_WORD);
   559   __ ldc1(F16, SP, F16_off * wordSize / SLOT_PER_WORD);
   560   __ ldc1(F17, SP, F17_off * wordSize / SLOT_PER_WORD);
   561   __ ldc1(F18, SP, F18_off * wordSize / SLOT_PER_WORD);
   562   __ ldc1(F19, SP, F19_off * wordSize / SLOT_PER_WORD);
   563 #endif
   565   __ ld_ptr(V1, SP, V1_off * wordSize / SLOT_PER_WORD);
   567   __ addiu(SP, SP, (reg_save_frame_size / SLOT_PER_WORD - 2) * wordSize);
   568 }
   570 void Runtime1::initialize_pd() {
   571   // nothing to do
   572 }
   574 // target: the entry point of the method that creates and posts the exception oop
   575 // has_argument: true if the exception needs an argument (passed on stack because registers must be preserved)
   576 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
   577   // preserve all registers
   578   OopMap* oop_map = save_live_registers(sasm, 0);
   580   // now all registers are saved and can be used freely
   581   // verify that no old value is used accidentally
   582   //all reigster are saved , I think mips do not need this
   584   // registers used by this stub
   585   const Register temp_reg = T3;
   586   // load argument for exception that is passed as an argument into the stub
   587   if (has_argument) {
   588     __ ld_ptr(temp_reg, Address(FP, 2*BytesPerWord));
   589   }
   590   int call_offset;
   591   if (has_argument)
   592      call_offset = __ call_RT(noreg, noreg, target, temp_reg);
   593   else
   594      call_offset = __ call_RT(noreg, noreg, target);
   596   OopMapSet* oop_maps = new OopMapSet();
   597   oop_maps->add_gc_map(call_offset, oop_map);
   599   __ stop("should not reach here");
   601   return oop_maps;
   602 }
   604 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
   605   __ block_comment("generate_handle_exception");
   607   // incoming parameters
   608   const Register exception_oop = V0;
   609   const Register exception_pc = V1;
   610   // other registers used in this stub
   611   const Register thread = TREG;
   612 #ifndef OPT_THREAD
   613   __ get_thread(thread);
   614 #endif
   615   // Save registers, if required.
   616   OopMapSet* oop_maps = new OopMapSet();
   617   OopMap* oop_map = NULL;
   618   switch (id) {
   619   case forward_exception_id:
   620     // We're handling an exception in the context of a compiled frame.
   621     // The registers have been saved in the standard places.  Perform
   622     // an exception lookup in the caller and dispatch to the handler
   623     // if found.  Otherwise unwind and dispatch to the callers
   624     // exception handler.
   625     oop_map = generate_oop_map(sasm, 1 /*thread*/);
   627     // load and clear pending exception oop into V0
   628     __ ld_ptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
   629     __ st_ptr(R0, Address(thread, Thread::pending_exception_offset()));
   631     // load issuing PC (the return address for this stub) into V1
   632     __ ld_ptr(exception_pc, Address(FP, 1*BytesPerWord));
   634     // make sure that the vm_results are cleared (may be unnecessary)
   635     __ st_ptr(R0, Address(thread, JavaThread::vm_result_offset()));
   636     __ st_ptr(R0, Address(thread, JavaThread::vm_result_2_offset()));
   637     break;
   638   case handle_exception_nofpu_id:
   639   case handle_exception_id:
   640     // At this point all registers MAY be live.
   641     oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
   642     break;
   643   case handle_exception_from_callee_id: {
   644     // At this point all registers except exception oop (V0) and
   645     // exception pc (V1) are dead.
   646     const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/);
   647     oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
   648     sasm->set_frame_size(frame_size);
   649     break;
   650   }
   651   default:  ShouldNotReachHere();
   652   }
   654 #ifdef TIERED
   655   // C2 can leave the fpu stack dirty
   656   __ empty_FPU_stack();
   657 #endif // TIERED
   659   // verify that only V0 and V1 is valid at this time
   660   // verify that V0 contains a valid exception
   661   __ verify_not_null_oop(exception_oop);
   663   // load address of JavaThread object for thread-local data
   664   __ get_thread(thread);
   666 #ifdef ASSERT
   667   // check that fields in JavaThread for exception oop and issuing pc are
   668   // empty before writing to them
   669   Label oop_empty;
   670   __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_oop_offset())));
   671   __ beq(AT, R0, oop_empty);
   672   __ delayed()->nop();
   673   __ stop("exception oop already set");
   674   __ bind(oop_empty);
   676   Label pc_empty;
   677   __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_pc_offset())));
   678   __ beq(AT, R0, pc_empty);
   679   __ delayed()->nop();
   680   __ stop("exception pc already set");
   681   __ bind(pc_empty);
   682 #endif
   684   // save exception oop and issuing pc into JavaThread
   685   // (exception handler will load it from here)
   686   __ st_ptr(exception_oop, Address(thread, in_bytes(JavaThread::exception_oop_offset())));
   687   __ st_ptr(exception_pc, Address(thread, in_bytes(JavaThread::exception_pc_offset())));
   689   // patch throwing pc into return address (has bci & oop map)
   690   __ st_ptr(exception_pc, Address(FP, 1*BytesPerWord));
   692   // compute the exception handler.
   693   // the exception oop and the throwing pc are read from the fields in JavaThread
   694   __ block_comment(";; will call_RT exception_handler_for_pc");
   695   int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
   696   oop_maps->add_gc_map(call_offset, oop_map);
   697   __ block_comment(";; end of call_RT exception_handler_for_pc");
   699   // V0:  handler address or NULL if no handler exists
   700   //      will be the deopt blob if nmethod was deoptimized while we looked up
   701   //      handler regardless of whether handler existed in the nmethod.
   703   // only V0 is valid at this time, all other registers have been destroyed by the
   704   // runtime call
   706   // patch the return address -> the stub will directly return to the exception handler
   707   __ st_ptr(V0, Address(FP, 1 * BytesPerWord));
   709   switch (id) {
   710   case forward_exception_id:
   711   case handle_exception_nofpu_id:
   712   case handle_exception_id:
   713     // Restore the registers that were saved at the beginning.
   714     restore_live_registers(sasm, id != handle_exception_nofpu_id);
   715     break;
   716   case handle_exception_from_callee_id:
   717     // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
   718     // since we do a leave anyway.
   720     // Pop the return address since we are possibly changing SP (restoring from BP).
   721     __ move(SP, FP);
   722     __ pop(FP);
   723     __ pop(RA);
   724     __ jr(RA);  // jump to exception handler
   725     __ delayed()->nop();
   726     break;
   727    default:  ShouldNotReachHere();
   728   }
   730   return oop_maps;
   731 }
   737 void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
   738   // incoming parameters
   739   const Register exception_oop = V0;
   740   // callee-saved copy of exception_oop during runtime call
   741   const Register exception_oop_callee_saved = S0;
   742   // other registers used in this stub
   743   const Register exception_pc = V1;
   744   const Register handler_addr = T3;
   745   const Register thread = TREG;
   747 #ifdef ASSERT
   748   // check that fields in JavaThread for exception oop and issuing pc are empty
   749   __ get_thread(thread);
   750   Label oop_empty;
   751   __ ld_ptr(AT, thread, in_bytes(JavaThread::exception_oop_offset()));
   752   __ beq(AT, R0, oop_empty);
   753   __ delayed()->nop();
   754   __ stop("exception oop must be empty");
   755   __ bind(oop_empty);
   757   Label pc_empty;
   758   __ ld_ptr(AT, thread, in_bytes(JavaThread::exception_pc_offset()));
   759   __ beq(AT, R0, pc_empty);
   760   __ delayed()->nop();
   761   __ stop("exception pc must be empty");
   762   __ bind(pc_empty);
   763 #endif
   764   // clear the FPU stack in case any FPU results are left behind
   765   __ empty_FPU_stack();
   767   // save exception_oop in callee-saved register to preserve it during runtime calls
   768   __ verify_not_null_oop(exception_oop);
   769   __ move(exception_oop_callee_saved, exception_oop);
   771 #ifndef OPT_THREAD
   772   __ get_thread(thread);
   773 #endif
   774   // Get return address (is in RA after leave).
   776   __ move(exception_pc, RA);
   777   __ push(RA);
   779   // search the exception handler address of the caller (using the return address)
   780   __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
   781   // V0: exception handler address of the caller
   783   // move result of call into correct register
   784   __ move(handler_addr, V0);
   786   // Restore exception oop to V0 (required convention of exception handler).
   787   __ move(exception_oop, exception_oop_callee_saved);
   789   // verify that there is really a valid exception in V0
   790   __ verify_oop(exception_oop);
   792   // get throwing pc (= return address).
   793   // V1 has been destroyed by the call, so it must be set again
   794   // the pop is also necessary to simulate the effect of a ret(0)
   795   __ super_pop(exception_pc);
   797   // continue at exception handler (return address removed)
   798   // note: do *not* remove arguments when unwinding the
   799   //       activation since the caller assumes having
   800   //       all arguments on the stack when entering the
   801   //       runtime to determine the exception handler
   802   //       (GC happens at call site with arguments!)
   803   // V0: exception oop
   804   // V1: throwing pc
   805   // T3: exception handler
   806   __ jr(handler_addr);
   807   __ delayed()->nop();
   808 }
   810 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
   812   // use the maximum number of runtime-arguments here because it is difficult to
   813   // distinguish each RT-Call.
   814   // Note: This number affects also the RT-Call in generate_handle_exception because
   815   //       the oop-map is shared for all calls.
   817   DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
   818   assert(deopt_blob != NULL, "deoptimization blob must have been created");
   819   // assert(deopt_with_exception_entry_for_patch != NULL,
   820   // "deoptimization blob must have been created");
   822   //OopMap* oop_map = save_live_registers(sasm, num_rt_args);
   823   OopMap* oop_map = save_live_registers(sasm, 0);
   824   const Register thread = T8;
   825   // push java thread (becomes first argument of C function)
   826   __ get_thread(thread);
   827   __ move(A0, thread);
   831   // NOTE: this frame should be compiled frame, but at this point, the pc in frame-anchor
   832   // is contained in interpreter. It should be wrong, and should be cleared but is not.
   833   // even if we cleared the wrong pc in anchor, the default way to get caller pc in class frame
   834   // is not right. It depends on that the caller pc is stored in *(sp - 1) but it's not the case
   836   __ set_last_Java_frame(thread, NOREG, FP, NULL);
   837   NOT_LP64(__ addiu(SP, SP, (-1) * wordSize));
   838   __ move(AT, -(StackAlignmentInBytes));
   839   __ andr(SP, SP, AT);
   840   __ relocate(relocInfo::internal_pc_type);
   841   {
   842 #ifndef _LP64
   843     int save_pc = (int)__ pc() +  12 + NativeCall::return_address_offset;
   844     __ lui(AT, Assembler::split_high(save_pc));
   845     __ addiu(AT, AT, Assembler::split_low(save_pc));
   846 #else
   847     uintptr_t save_pc = (uintptr_t)__ pc() + NativeMovConstReg::instruction_size + 1 * BytesPerInstWord + NativeCall::return_address_offset_long;
   848     __ li48(AT, save_pc);
   849 #endif
   850   }
   851   __ st_ptr(AT, thread, in_bytes(JavaThread::last_Java_pc_offset()));
   853   // do the call
   854 #ifndef _LP64
   855   __ lui(T9, Assembler::split_high((int)target));
   856   __ addiu(T9, T9, Assembler::split_low((int)target));
   857 #else
   858   __ li48(T9, (intptr_t)target);
   859 #endif
   860   __ jalr(T9);
   861   __ delayed()->nop();
   862   OopMapSet*  oop_maps = new OopMapSet();
   863   oop_maps->add_gc_map(__ offset(),  oop_map);
   865   __ get_thread(thread);
   867   __ ld_ptr (SP, thread, in_bytes(JavaThread::last_Java_sp_offset()));
   868   __ reset_last_Java_frame(thread, true);
   869   // discard thread arg
   870   // check for pending exceptions
   871   {
   872     Label L, skip;
   873     //Label no_deopt;
   874     __ ld_ptr(AT, thread, in_bytes(Thread::pending_exception_offset()));
   875     __ beq(AT, R0, L);
   876     __ delayed()->nop();
   877     // exception pending => remove activation and forward to exception handler
   879     __ bne(V0, R0, skip);
   880     __ delayed()->nop();
   881     __ jmp(Runtime1::entry_for(Runtime1::forward_exception_id),
   882         relocInfo::runtime_call_type);
   883     __ delayed()->nop();
   884     __ bind(skip);
   886     // the deopt blob expects exceptions in the special fields of
   887     // JavaThread, so copy and clear pending exception.
   889     // load and clear pending exception
   890     __ ld_ptr(V0, Address(thread,in_bytes(Thread::pending_exception_offset())));
   891     __ st_ptr(R0, Address(thread, in_bytes(Thread::pending_exception_offset())));
   893     // check that there is really a valid exception
   894     __ verify_not_null_oop(V0);
   896     // load throwing pc: this is the return address of the stub
   897     __ ld_ptr(V1, Address(SP, return_off * BytesPerWord));
   900 #ifdef ASSERT
   901     // check that fields in JavaThread for exception oop and issuing pc are empty
   902     Label oop_empty;
   903     __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_oop_offset())));
   904     __ beq(AT,R0,oop_empty);
   905     __ delayed()->nop();
   906     __ stop("exception oop must be empty");
   907     __ bind(oop_empty);
   909     Label pc_empty;
   910     __ ld_ptr(AT, Address(thread, in_bytes(JavaThread::exception_pc_offset())));
   911     __ beq(AT,R0,pc_empty);
   912     __ delayed()->nop();
   913     __ stop("exception pc must be empty");
   914     __ bind(pc_empty);
   915 #endif
   917     // store exception oop and throwing pc to JavaThread
   918     __ st_ptr(V0,Address(thread, in_bytes(JavaThread::exception_oop_offset())));
   919     __ st_ptr(V1,Address(thread, in_bytes(JavaThread::exception_pc_offset())));
   921     restore_live_registers(sasm);
   923     __ leave();
   925     // Forward the exception directly to deopt blob. We can blow no
   926     // registers and must leave throwing pc on the stack.  A patch may
   927     // have values live in registers so the entry point with the
   928     // exception in tls.
   929     __ jmp(deopt_blob->unpack_with_exception_in_tls(), relocInfo::runtime_call_type);
   930     __ delayed()->nop();
   932     __ bind(L);
   933   }
   935   // Runtime will return true if the nmethod has been deoptimized during
   936   // the patching process. In that case we must do a deopt reexecute instead.
   938   Label reexecuteEntry, cont;
   940   __ beq(V0, R0, cont);                              // have we deoptimized?
   941   __ delayed()->nop();
   943   // Will reexecute. Proper return address is already on the stack we just restore
   944   // registers, pop all of our frame but the return address and jump to the deopt blob
   945   restore_live_registers(sasm);
   947   __ leave();
   948   __ jmp(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type);
   949   __ delayed()->nop();
   951   __ bind(cont);
   952   restore_live_registers(sasm);
   954   __ leave();
   955   __ jr(RA);
   956   __ delayed()->nop();
   958   return oop_maps;
   959 }
   962 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
   963   // for better readability
   964   const bool must_gc_arguments = true;
   965   const bool dont_gc_arguments = false;
   968   // default value; overwritten for some optimized stubs that are called
   969   // from methods that do not use the fpu
   970   bool save_fpu_registers = true;
   973   // stub code & info for the different stubs
   974   OopMapSet* oop_maps = NULL;
   976   switch (id) {
   977     case forward_exception_id:
   978       {
   979         oop_maps = generate_handle_exception(id, sasm);
   980         __ leave();
   981         __ jr(RA);
   982         __ delayed()->nop();
   983       }
   984       break;
   986     case new_instance_id:
   987     case fast_new_instance_id:
   988     case fast_new_instance_init_check_id:
   989       {
   990         Register klass = A4; // Incoming
   991         Register obj   = V0; // Result
   993         if (id == new_instance_id) {
   994           __ set_info("new_instance", dont_gc_arguments);
   995         } else if (id == fast_new_instance_id) {
   996           __ set_info("fast new_instance", dont_gc_arguments);
   997         } else {
   998           assert(id == fast_new_instance_init_check_id, "bad StubID");
   999           __ set_info("fast new_instance init check", dont_gc_arguments);
  1002         if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id)
  1003              && UseTLAB && FastTLABRefill) {
  1004           Label slow_path;
  1005           Register obj_size = T0;
  1006           Register t1       = T2;
  1007           Register t2       = T3;
  1008           assert_different_registers(klass, obj, obj_size, t1, t2);
  1009           if (id == fast_new_instance_init_check_id) {
  1010             // make sure the klass is initialized
  1011             __ ld_ptr(AT, Address(klass, in_bytes(InstanceKlass::init_state_offset())));
  1012             __ move(t1, InstanceKlass::fully_initialized);
  1013             __ bne(AT, t1, slow_path);
  1014             __ delayed()->nop();
  1016 #ifdef ASSERT
  1017           // assert object can be fast path allocated
  1019             Label ok, not_ok;
  1020             __ lw(obj_size, klass, in_bytes(Klass::layout_helper_offset()));
  1021             __ blez(obj_size, not_ok);
  1022             __ delayed()->nop();
  1023             __ andi(t1 , obj_size, Klass::_lh_instance_slow_path_bit);
  1024             __ beq(t1, R0, ok);
  1025             __ delayed()->nop();
  1026             __ bind(not_ok);
  1027             __ stop("assert(can be fast path allocated)");
  1028             __ should_not_reach_here();
  1029             __ bind(ok);
  1031 #endif // ASSERT
  1032           // if we got here then the TLAB allocation failed, so try
  1033           // refilling the TLAB or allocating directly from eden.
  1035           Label retry_tlab, try_eden;
  1036           __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy A4 (klass)
  1038           __ bind(retry_tlab);
  1040           // get the instance size
  1041           __ lw(obj_size, klass, in_bytes(Klass::layout_helper_offset()));
  1042           __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
  1043           __ initialize_object(obj, klass, obj_size, 0, t1, t2);
  1044           __ verify_oop(obj);
  1045           __ jr(RA);
  1046           __ delayed()->nop();
  1048 #ifndef OPT_THREAD
  1049           const Register thread = T8;
  1050           __ get_thread(thread);
  1051 #else
  1052           const Register thread = TREG;
  1053 #endif
  1055           __ bind(try_eden);
  1057           // get the instance size
  1058           __ lw(obj_size, klass, in_bytes(Klass::layout_helper_offset()));
  1059           __ eden_allocate(obj, obj_size, 0, t1, t2, slow_path);
  1060           __ incr_allocated_bytes(thread, obj_size, 0);
  1062           __ initialize_object(obj, klass, obj_size, 0, t1, t2);
  1063           __ verify_oop(obj);
  1064           __ jr(RA);
  1065           __ delayed()->nop();
  1067           __ bind(slow_path);
  1069         __ enter();
  1070         OopMap* map = save_live_registers(sasm, 0);
  1071         int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
  1072         oop_maps = new OopMapSet();
  1073         oop_maps->add_gc_map(call_offset, map);
  1074         restore_live_registers_except_V0(sasm);
  1075         __ verify_oop(obj);
  1076         __ leave();
  1077         __ jr(RA);
  1078         __ delayed()->nop();
  1080         // V0: new instance
  1082       break;
  1085 #ifdef TIERED
  1086 //FIXME, I hava no idea which register to use
  1087     case counter_overflow_id:
  1089 #ifndef _LP64
  1090         Register bci = T5;
  1091 #else
  1092         Register bci = A5;
  1093 #endif
  1094         Register method = AT;
  1095         __ enter();
  1096         OopMap* map = save_live_registers(sasm, 0);
  1097         // Retrieve bci
  1098         __ lw(bci, Address(FP, 2*BytesPerWord));
  1099         __ ld(method, Address(FP, 3*BytesPerWord));
  1100         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
  1101         oop_maps = new OopMapSet();
  1102         oop_maps->add_gc_map(call_offset, map);
  1103         restore_live_registers(sasm);
  1104         __ leave();
  1105         __ jr(RA);
  1106         __ delayed()->nop();
  1108       break;
  1109 #endif // TIERED
  1113     case new_type_array_id:
  1114     case new_object_array_id:
  1116         // i use T2 as length register, T4 as klass register, V0 as result register.
  1117         // MUST accord with NewTypeArrayStub::emit_code, NewObjectArrayStub::emit_code
  1118         Register length   = T2; // Incoming
  1119 #ifndef _LP64
  1120         Register klass    = T4; // Incoming
  1121 #else
  1122         Register klass    = A4; // Incoming
  1123 #endif
  1124         Register obj      = V0; // Result
  1126         if (id == new_type_array_id) {
  1127           __ set_info("new_type_array", dont_gc_arguments);
  1128         } else {
  1129           __ set_info("new_object_array", dont_gc_arguments);
  1132         if (UseTLAB && FastTLABRefill) {
  1133           Register arr_size = T0;
  1134           Register t1       = T1;
  1135           Register t2       = T3;
  1136           Label slow_path;
  1137           assert_different_registers(length, klass, obj, arr_size, t1, t2);
  1139           // check that array length is small enough for fast path
  1140           __ move(AT, C1_MacroAssembler::max_array_allocation_length);
  1141           __ sltu(AT, AT, length);
  1142           __ bne(AT, R0, slow_path);
  1143           __ delayed()->nop();
  1145           // if we got here then the TLAB allocation failed, so try
  1146           // refilling the TLAB or allocating directly from eden.
  1147           Label retry_tlab, try_eden;
  1148           //T0,T1,T5,T8 have changed!
  1149           __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves T2 & T4
  1151           __ bind(retry_tlab);
  1153           // get the allocation size: (length << (layout_helper & 0x1F)) + header_size
  1154           __ lw(t1, klass, in_bytes(Klass::layout_helper_offset()));
  1155           __ andi(AT, t1, 0x1f);
  1156           __ sllv(arr_size, length, AT);
  1157           __ srl(t1, t1, Klass::_lh_header_size_shift);
  1158           __ andi(t1, t1, Klass::_lh_header_size_mask);
  1159           __ add(arr_size, t1, arr_size);
  1160           __ addi(arr_size, arr_size, MinObjAlignmentInBytesMask);  // align up
  1161           __ move(AT, ~MinObjAlignmentInBytesMask);
  1162           __ andr(arr_size, arr_size, AT);
  1165           __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path);  // preserves arr_size
  1166           __ initialize_header(obj, klass, length,t1,t2);
  1167           __ lbu(t1, Address(klass, in_bytes(Klass::layout_helper_offset())
  1168                                     + (Klass::_lh_header_size_shift / BitsPerByte)));
  1169           assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
  1170           assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
  1171           __ andi(t1, t1, Klass::_lh_header_size_mask);
  1172           __ sub(arr_size, arr_size, t1);  // body length
  1173           __ add(t1, t1, obj);             // body start
  1174           __ initialize_body(t1, arr_size, 0, t2);
  1175           __ verify_oop(obj);
  1176           __ jr(RA);
  1177           __ delayed()->nop();
  1179 #ifndef OPT_THREAD
  1180           const Register thread = T8;
  1181           __ get_thread(thread);
  1182 #else
  1183           const Register thread = TREG;
  1184 #endif
  1186           __ bind(try_eden);
  1187           // get the allocation size: (length << (layout_helper & 0x1F)) + header_size
  1188           __ lw(t1, klass, in_bytes(Klass::layout_helper_offset()));
  1189           __ andi(AT, t1, 0x1f);
  1190           __ sllv(arr_size, length, AT);
  1191           __ srl(t1, t1, Klass::_lh_header_size_shift);
  1192           __ andi(t1, t1, Klass::_lh_header_size_mask);
  1193           __ add(arr_size, t1, arr_size);
  1194           __ addi(arr_size, arr_size, MinObjAlignmentInBytesMask);  // align up
  1195           __ move(AT, ~MinObjAlignmentInBytesMask);
  1196           __ andr(arr_size, arr_size, AT);
  1197           __ eden_allocate(obj, arr_size, 0, t1, t2, slow_path);  // preserves arr_size
  1198           __ incr_allocated_bytes(thread, arr_size, 0);
  1200           __ initialize_header(obj, klass, length,t1,t2);
  1201           __ lbu(t1, Address(klass, in_bytes(Klass::layout_helper_offset())
  1202                                     + (Klass::_lh_header_size_shift / BitsPerByte)));
  1203           __ andi(t1, t1, Klass::_lh_header_size_mask);
  1204           __ sub(arr_size, arr_size, t1);  // body length
  1205           __ add(t1, t1, obj);             // body start
  1207           __ initialize_body(t1, arr_size, 0, t2);
  1208           __ verify_oop(obj);
  1209           __ jr(RA);
  1210           __ delayed()->nop();
  1211           __ bind(slow_path);
  1215         __ enter();
  1216         OopMap* map = save_live_registers(sasm, 0);
  1217         int call_offset;
  1218         if (id == new_type_array_id) {
  1219           call_offset = __ call_RT(obj, noreg,
  1220                                     CAST_FROM_FN_PTR(address, new_type_array), klass, length);
  1221         } else {
  1222           call_offset = __ call_RT(obj, noreg,
  1223                                    CAST_FROM_FN_PTR(address, new_object_array), klass, length);
  1226         oop_maps = new OopMapSet();
  1227         oop_maps->add_gc_map(call_offset, map);
  1228         restore_live_registers_except_V0(sasm);
  1229         __ verify_oop(obj);
  1230         __ leave();
  1231         __ jr(RA);
  1232         __ delayed()->nop();
  1234       break;
  1236     case new_multi_array_id:
  1238         StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
  1239        //refer to c1_LIRGenerate_mips.cpp:do_NewmultiArray
  1240         // V0: klass
  1241         // T2: rank
  1242         // T0: address of 1st dimension
  1243         //__ call_RT(V0, noreg, CAST_FROM_FN_PTR(address, new_multi_array), A1, A2, A3);
  1244         //OopMap* map = save_live_registers(sasm, 4);
  1245         OopMap* map = save_live_registers(sasm, 0);
  1246         int call_offset = __ call_RT(V0, noreg, CAST_FROM_FN_PTR(address, new_multi_array),
  1247             V0,T2,T0);
  1248         oop_maps = new OopMapSet();
  1249         oop_maps->add_gc_map(call_offset, map);
  1250         //FIXME
  1251         restore_live_registers_except_V0(sasm);
  1252         // V0: new multi array
  1253         __ verify_oop(V0);
  1255       break;
  1258     case register_finalizer_id:
  1260         __ set_info("register_finalizer", dont_gc_arguments);
  1262         // The object is passed on the stack and we haven't pushed a
  1263         // frame yet so it's one work away from top of stack.
  1264         //reference to LIRGenerator::do_RegisterFinalizer, call_runtime
  1265         __ move(V0, A0);
  1266         __ verify_oop(V0);
  1267         // load the klass and check the has finalizer flag
  1268         Label register_finalizer;
  1269 #ifndef _LP64
  1270         Register t = T5;
  1271 #else
  1272         Register t = A5;
  1273 #endif
  1274         //__ ld_ptr(t, Address(V0, oopDesc::klass_offset_in_bytes()));
  1275         __ load_klass(t, V0);
  1276         __ lw(t, Address(t, Klass::access_flags_offset()));
  1277         __ move(AT, JVM_ACC_HAS_FINALIZER);
  1278         __ andr(AT, AT, t);
  1280         __ bne(AT, R0, register_finalizer);
  1281         __ delayed()->nop();
  1282         __ jr(RA);
  1283         __ delayed()->nop();
  1284         __ bind(register_finalizer);
  1285         __ enter();
  1286         OopMap* map = save_live_registers(sasm, 0 /*num_rt_args */);
  1288         int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
  1289               SharedRuntime::register_finalizer), V0);
  1290         oop_maps = new OopMapSet();
  1291         oop_maps->add_gc_map(call_offset, map);
  1293         // Now restore all the live registers
  1294         restore_live_registers(sasm);
  1296         __ leave();
  1297         __ jr(RA);
  1298         __ delayed()->nop();
  1300       break;
  1302 //  case range_check_failed_id:
  1303   case throw_range_check_failed_id:
  1305         StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
  1306         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
  1307               throw_range_check_exception),true);
  1309       break;
  1311       case throw_index_exception_id:
  1313         // i use A1 as the index register, for this will be the first argument, see call_RT
  1314         StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
  1315         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
  1316               throw_index_exception), true);
  1318       break;
  1320   case throw_div0_exception_id:
  1321       { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
  1322         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
  1323               throw_div0_exception), false);
  1325       break;
  1327   case throw_null_pointer_exception_id:
  1329         StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
  1330         oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
  1331               throw_null_pointer_exception),false);
  1333       break;
  1335   case handle_exception_nofpu_id:
  1336     save_fpu_registers = false;
  1337      // fall through
  1338   case handle_exception_id:
  1340       StubFrame f(sasm, "handle_exception", dont_gc_arguments);
  1341       //OopMap* oop_map = save_live_registers(sasm, 1, save_fpu_registers);
  1342       oop_maps = generate_handle_exception(id, sasm);
  1344     break;
  1345   case handle_exception_from_callee_id:
  1347       StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
  1348       oop_maps = generate_handle_exception(id, sasm);
  1350     break;
  1351   case unwind_exception_id:
  1353       __ set_info("unwind_exception", dont_gc_arguments);
  1354       generate_unwind_exception(sasm);
  1356     break;
  1359   case throw_array_store_exception_id:
  1361       StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
  1362       // tos + 0: link
  1363       //     + 1: return address
  1364       oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
  1365             throw_array_store_exception), true);
  1367     break;
  1369   case throw_class_cast_exception_id:
  1371       StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
  1372       oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address,
  1373             throw_class_cast_exception), true);
  1375     break;
  1377   case throw_incompatible_class_change_error_id:
  1379       StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments);
  1380       oop_maps = generate_exception_throw(sasm,
  1381             CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
  1383     break;
  1385   case slow_subtype_check_id:
  1387     //actually , We do not use it
  1388       // A0:klass_RInfo    sub
  1389       // A1:k->encoding() super
  1390       __ set_info("slow_subtype_check", dont_gc_arguments);
  1391       __ st_ptr(T0, SP, (-1) * wordSize);
  1392       __ st_ptr(T1, SP, (-2) * wordSize);
  1393       __ addiu(SP, SP, (-2) * wordSize);
  1395       Label miss;
  1396       __ check_klass_subtype_slow_path(A0, A1, T0, T1, NULL, &miss);
  1398       __ addiu(V0, R0, 1);
  1399       __ addiu(SP, SP, 2 * wordSize);
  1400       __ ld_ptr(T0, SP, (-1) * wordSize);
  1401       __ ld_ptr(T1, SP, (-2) * wordSize);
  1402       __ jr(RA);
  1403       __ delayed()->nop();
  1406       __ bind(miss);
  1407       __ move(V0, R0);
  1408       __ addiu(SP, SP, 2 * wordSize);
  1409       __ ld_ptr(T0, SP, (-1) * wordSize);
  1410       __ ld_ptr(T1, SP, (-2) * wordSize);
  1411       __ jr(RA);
  1412       __ delayed()->nop();
  1414     break;
  1416   case monitorenter_nofpu_id:
  1417     save_fpu_registers = false;// fall through
  1419   case monitorenter_id:
  1421       StubFrame f(sasm, "monitorenter", dont_gc_arguments);
  1422       OopMap* map = save_live_registers(sasm, 0, save_fpu_registers);
  1424       f.load_argument(1, V0); // V0: object
  1425 #ifndef _LP64
  1426       f.load_argument(0, T6); // T6: lock address
  1427       int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
  1428            monitorenter), V0, T6);
  1429 #else
  1430       f.load_argument(0, A6); // A6: lock address
  1431       int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
  1432            monitorenter), V0, A6);
  1433 #endif
  1435       oop_maps = new OopMapSet();
  1436       oop_maps->add_gc_map(call_offset, map);
  1437       restore_live_registers(sasm, save_fpu_registers);
  1439     break;
  1441   case monitorexit_nofpu_id:
  1442     save_fpu_registers = false;
  1443         // fall through
  1444   case monitorexit_id:
  1446       StubFrame f(sasm, "monitorexit", dont_gc_arguments);
  1447       OopMap* map = save_live_registers(sasm, 0, save_fpu_registers);
  1449 #ifndef _LP64
  1450       f.load_argument(0, T6); // T6: lock address
  1451 #else
  1452       f.load_argument(0, A6); // A6: lock address
  1453 #endif
  1454       // note: really a leaf routine but must setup last java sp
  1455       //       => use call_RT for now (speed can be improved by
  1456       //       doing last java sp setup manually)
  1457 #ifndef _LP64
  1458       int call_offset = __ call_RT(noreg, noreg,
  1459                                     CAST_FROM_FN_PTR(address, monitorexit), T6);
  1460 #else
  1461       int call_offset = __ call_RT(noreg, noreg,
  1462                                     CAST_FROM_FN_PTR(address, monitorexit), A6);
  1463 #endif
  1464       oop_maps = new OopMapSet();
  1465       oop_maps->add_gc_map(call_offset, map);
  1466       restore_live_registers(sasm, save_fpu_registers);
  1469     break;
  1470         //  case init_check_patching_id:
  1471   case access_field_patching_id:
  1473       StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
  1474       // we should set up register map
  1475       oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
  1478     break;
  1480   case load_klass_patching_id:
  1482       StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
  1483       // we should set up register map
  1484       oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address,
  1485             move_klass_patching));
  1487     break;
  1488   case load_mirror_patching_id:
  1490       StubFrame f(sasm, "load_mirror_patching" , dont_gc_arguments);
  1491       oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
  1493     break;
  1495   case load_appendix_patching_id:
  1497       StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
  1498       // we should set up register map
  1499       oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
  1501     break;
  1503   case dtrace_object_alloc_id:
  1505       // V0:object
  1506       StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
  1507       // we can't gc here so skip the oopmap but make sure that all
  1508       // the live registers get saved.
  1509       save_live_registers(sasm, 0);
  1511       __ push_reg(V0);
  1512       __ move(A0, V0);
  1513       __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc),
  1514           relocInfo::runtime_call_type);
  1515       __ delayed()->nop();
  1516       __ super_pop(V0);
  1518       restore_live_registers(sasm);
  1520     break;
  1522   case fpu2long_stub_id:
  1524       //FIXME, I hava no idea how to port this
  1525       //tty->print_cr("fpu2long_stub_id unimplemented yet!");
  1527     break;
  1529   case deoptimize_id:
  1531       StubFrame f(sasm, "deoptimize", dont_gc_arguments);
  1532       const int num_rt_args = 1;  // thread
  1533       OopMap* oop_map = save_live_registers(sasm, num_rt_args);
  1534       int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize));
  1535       oop_maps = new OopMapSet();
  1536       oop_maps->add_gc_map(call_offset, oop_map);
  1537       restore_live_registers(sasm);
  1538       DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
  1539       assert(deopt_blob != NULL, "deoptimization blob must have been created");
  1540       __ leave();
  1541       __ jmp(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type);
  1542       __ delayed()->nop();
  1544    break;
  1546   case predicate_failed_trap_id:
  1548       StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments);
  1550       OopMap* map = save_live_registers(sasm, 1);
  1552       int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
  1553       oop_maps = new OopMapSet();
  1554       oop_maps->add_gc_map(call_offset, map);
  1555       restore_live_registers(sasm);
  1556       __ leave();
  1557       DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
  1558       assert(deopt_blob != NULL, "deoptimization blob must have been created");
  1560       __ jmp(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type);
  1561       __ delayed()->nop();
  1563    break;
  1565   default:
  1567       StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
  1568       __ move(A1, (int)id);
  1569       __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), A1);
  1570       __ should_not_reach_here();
  1572     break;
  1574   return oop_maps;
  1577 #undef __
  1579 const char *Runtime1::pd_name_for_address(address entry) {
  1580   return "<unknown function>";

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