1.1 --- a/src/cpu/mips/vm/c1_Runtime1_mips.cpp Thu Feb 21 10:14:02 2019 +0800
1.2 +++ b/src/cpu/mips/vm/c1_Runtime1_mips.cpp Tue Mar 05 17:00:17 2019 +0800
1.3 @@ -1,6 +1,6 @@
1.4 /*
1.5 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
1.6 - * Copyright (c) 2015, 2018, Loongson Technology. All rights reserved.
1.7 + * Copyright (c) 2015, 2019, Loongson Technology. All rights reserved.
1.8 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
1.9 *
1.10 * This code is free software; you can redistribute it and/or modify it
1.11 @@ -49,7 +49,6 @@
1.12 // for stack alignment consideration, you cannot call this with argument in stack.
1.13 // if you need >3 arguments, you must implement this method yourself.
1.14 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
1.15 - // i use S7 for edi.
1.16 // setup registers
1.17 const Register thread = TREG; // is callee-saved register (Visual C++ calling conventions)
1.18 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different");
1.19 @@ -113,7 +112,7 @@
1.20 beq(thread, V0, L);
1.21 delayed()->nop();
1.22 int3();
1.23 - stop("StubAssembler::call_RT: edi not callee saved?");
1.24 + stop("StubAssembler::call_RT: TREG not callee saved?");
1.25 bind(L);
1.26 }
1.27 super_pop(V0);
1.28 @@ -214,7 +213,7 @@
1.29 // load parameters that were stored with LIR_Assembler::store_parameter
1.30 // Note: offsets for store_parameter and load_argument must match
1.31 void StubFrame::load_argument(int offset_in_words, Register reg) {
1.32 - //ebp + 0: link
1.33 + //fp, + 0: link
1.34 // + 1: return address
1.35 // + 2: argument with offset 0
1.36 // + 3: argument with offset 1
1.37 @@ -236,13 +235,6 @@
1.38
1.39 #define __ sasm->
1.40
1.41 -//static OopMap* save_live_registers(MacroAssembler* sasm, int num_rt_args);
1.42 -//static void restore_live_registers(MacroAssembler* sasm);
1.43 -//DeoptimizationBlob* SharedRuntime::_deopt_blob = NULL;
1.44 -/*
1.45 -const int fpu_stack_as_doubles_size_in_words = 16;
1.46 -const int fpu_stack_as_doubles_size = 64;
1.47 -*/
1.48 const int float_regs_as_doubles_size_in_words = 16;
1.49
1.50 //FIXME,
1.51 @@ -281,7 +273,7 @@
1.52 A3_off, SLOT2(A3H_off)
1.53
1.54 // Float registers
1.55 - /* FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers */
1.56 + // FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers
1.57 F0_off, SLOT2( F0H_off)
1.58 F1_off, SLOT2( F1H_off)
1.59 F2_off, SLOT2( F2H_off)
1.60 @@ -632,11 +624,11 @@
1.61 // exception handler.
1.62 oop_map = generate_oop_map(sasm, 1 /*thread*/);
1.63
1.64 - // load and clear pending exception oop into RAX
1.65 + // load and clear pending exception oop into V0
1.66 __ ld_ptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
1.67 __ st_ptr(R0, Address(thread, Thread::pending_exception_offset()));
1.68
1.69 - // load issuing PC (the return address for this stub) into rdx
1.70 + // load issuing PC (the return address for this stub) into V1
1.71 __ ld_ptr(exception_pc, Address(FP, 1*BytesPerWord));
1.72
1.73 // make sure that the vm_results are cleared (may be unnecessary)
1.74 @@ -649,8 +641,8 @@
1.75 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
1.76 break;
1.77 case handle_exception_from_callee_id: {
1.78 - // At this point all registers except exception oop (RAX) and
1.79 - // exception pc (RDX) are dead.
1.80 + // At this point all registers except exception oop (V0) and
1.81 + // exception pc (V1) are dead.
1.82 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/);
1.83 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
1.84 sasm->set_frame_size(frame_size);
1.85 @@ -752,9 +744,6 @@
1.86 const Register handler_addr = T3;
1.87 const Register thread = TREG;
1.88
1.89 - // verify that only eax is valid at this time
1.90 - // __ invalidate_registers(false, true, true, true, true, true);
1.91 -
1.92 #ifdef ASSERT
1.93 // check that fields in JavaThread for exception oop and issuing pc are empty
1.94 __ get_thread(thread);
1.95 @@ -791,8 +780,6 @@
1.96 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
1.97 // V0: exception handler address of the caller
1.98
1.99 - // only eax is valid at this time, all other registers have been destroyed by the call
1.100 -
1.101 // move result of call into correct register
1.102 __ move(handler_addr, V0);
1.103
1.104 @@ -820,11 +807,6 @@
1.105 __ delayed()->nop();
1.106 }
1.107
1.108 -
1.109 -
1.110 -
1.111 -//static address deopt_with_exception_entry_for_patch = NULL;
1.112 -
1.113 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
1.114
1.115 // use the maximum number of runtime-arguments here because it is difficult to
1.116 @@ -845,12 +827,12 @@
1.117 __ move(A0, thread);
1.118
1.119
1.120 -/*
1.121 - * NOTE: this frame should be compiled frame, but at this point, the pc in frame-anchor
1.122 - * is contained in interpreter. It should be wrong, and should be cleared but is not.
1.123 - * even if we cleared the wrong pc in anchor, the default way to get caller pc in class frame
1.124 - * is not right. It depends on that the caller pc is stored in *(sp - 1) but it's not the case
1.125 - */
1.126 +
1.127 + // NOTE: this frame should be compiled frame, but at this point, the pc in frame-anchor
1.128 + // is contained in interpreter. It should be wrong, and should be cleared but is not.
1.129 + // even if we cleared the wrong pc in anchor, the default way to get caller pc in class frame
1.130 + // is not right. It depends on that the caller pc is stored in *(sp - 1) but it's not the case
1.131 +
1.132 __ set_last_Java_frame(thread, NOREG, FP, NULL);
1.133 NOT_LP64(__ addiu(SP, SP, (-1) * wordSize));
1.134 __ move(AT, -(StackAlignmentInBytes));
1.135 @@ -1051,7 +1033,7 @@
1.136 // refilling the TLAB or allocating directly from eden.
1.137
1.138 Label retry_tlab, try_eden;
1.139 - __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy edx (klass)
1.140 + __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy A4 (klass)
1.141
1.142 __ bind(retry_tlab);
1.143
1.144 @@ -1113,7 +1095,7 @@
1.145 __ enter();
1.146 OopMap* map = save_live_registers(sasm, 0);
1.147 // Retrieve bci
1.148 - __ lw(bci, Address(FP, 2*BytesPerWord));// FIXME:wuhui.ebp==??
1.149 + __ lw(bci, Address(FP, 2*BytesPerWord));
1.150 __ ld(method, Address(FP, 3*BytesPerWord));
1.151 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
1.152 oop_maps = new OopMapSet();
1.153 @@ -1465,7 +1447,7 @@
1.154 OopMap* map = save_live_registers(sasm, 0, save_fpu_registers);
1.155
1.156 #ifndef _LP64
1.157 - f.load_argument(0, T6); // eax: lock address
1.158 + f.load_argument(0, T6); // T6: lock address
1.159 #else
1.160 f.load_argument(0, A6); // A6: lock address
1.161 #endif
1.162 @@ -1503,21 +1485,6 @@
1.163 move_klass_patching));
1.164 }
1.165 break;
1.166 -/* case jvmti_exception_throw_id:
1.167 - {
1.168 - // V0: exception oop
1.169 - // V1: exception pc
1.170 - StubFrame f(sasm, "jvmti_exception_throw", dont_gc_arguments);
1.171 - // Preserve all registers across this potentially blocking call
1.172 - const int num_rt_args = 2; // thread, exception oop
1.173 - //OopMap* map = save_live_registers(sasm, num_rt_args);
1.174 - OopMap* map = save_live_registers(sasm, 0);
1.175 - int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address,
1.176 - Runtime1::post_jvmti_exception_throw), V0);
1.177 - oop_maps = new OopMapSet();
1.178 - oop_maps->add_gc_map(call_offset, map);
1.179 - restore_live_registers(sasm);
1.180 - }*/
1.181 case load_mirror_patching_id:
1.182 {
1.183 StubFrame f(sasm, "load_mirror_patching" , dont_gc_arguments);
