Fri, 11 Mar 2011 22:34:57 -0800
7012648: move JSR 292 to package java.lang.invoke and adjust names
Summary: package and class renaming only; delete unused methods and classes
Reviewed-by: twisti
1 //
2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 // Macros to extract hi & lo halves from a long pair.
464 // G0 is not part of any long pair, so assert on that.
465 // Prevents accidentally using G1 instead of G0.
466 #define LONG_HI_REG(x) (x)
467 #define LONG_LO_REG(x) (x)
469 %}
471 source %{
472 #define __ _masm.
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
477 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
482 static Register reg_to_register_object(int register_encoding);
484 // Used by the DFA in dfa_sparc.cpp.
485 // Check for being able to use a V9 branch-on-register. Requires a
486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
487 // extended. Doesn't work following an integer ADD, for example, because of
488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
490 // replace them with zero, which could become sign-extension in a different OS
491 // release. There's no obvious reason why an interrupt will ever fill these
492 // bits with non-zero junk (the registers are reloaded with standard LD
493 // instructions which either zero-fill or sign-fill).
494 bool can_branch_register( Node *bol, Node *cmp ) {
495 if( !BranchOnRegister ) return false;
496 #ifdef _LP64
497 if( cmp->Opcode() == Op_CmpP )
498 return true; // No problems with pointer compares
499 #endif
500 if( cmp->Opcode() == Op_CmpL )
501 return true; // No problems with long compares
503 if( !SparcV9RegsHiBitsZero ) return false;
504 if( bol->as_Bool()->_test._test != BoolTest::ne &&
505 bol->as_Bool()->_test._test != BoolTest::eq )
506 return false;
508 // Check for comparing against a 'safe' value. Any operation which
509 // clears out the high word is safe. Thus, loads and certain shifts
510 // are safe, as are non-negative constants. Any operation which
511 // preserves zero bits in the high word is safe as long as each of its
512 // inputs are safe. Thus, phis and bitwise booleans are safe if their
513 // inputs are safe. At present, the only important case to recognize
514 // seems to be loads. Constants should fold away, and shifts &
515 // logicals can use the 'cc' forms.
516 Node *x = cmp->in(1);
517 if( x->is_Load() ) return true;
518 if( x->is_Phi() ) {
519 for( uint i = 1; i < x->req(); i++ )
520 if( !x->in(i)->is_Load() )
521 return false;
522 return true;
523 }
524 return false;
525 }
527 // ****************************************************************************
529 // REQUIRED FUNCTIONALITY
531 // !!!!! Special hack to get all type of calls to specify the byte offset
532 // from the start of the call to the point where the return address
533 // will point.
534 // The "return address" is the address of the call instruction, plus 8.
536 int MachCallStaticJavaNode::ret_addr_offset() {
537 int offset = NativeCall::instruction_size; // call; delay slot
538 if (_method_handle_invoke)
539 offset += 4; // restore SP
540 return offset;
541 }
543 int MachCallDynamicJavaNode::ret_addr_offset() {
544 int vtable_index = this->_vtable_index;
545 if (vtable_index < 0) {
546 // must be invalid_vtable_index, not nonvirtual_vtable_index
547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
548 return (NativeMovConstReg::instruction_size +
549 NativeCall::instruction_size); // sethi; setlo; call; delay slot
550 } else {
551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
554 int klass_load_size;
555 if (UseCompressedOops) {
556 assert(Universe::heap() != NULL, "java heap should be initialized");
557 if (Universe::narrow_oop_base() == NULL)
558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
559 else
560 klass_load_size = 3*BytesPerInstWord;
561 } else {
562 klass_load_size = 1*BytesPerInstWord;
563 }
564 if( Assembler::is_simm13(v_off) ) {
565 return klass_load_size +
566 (2*BytesPerInstWord + // ld_ptr, ld_ptr
567 NativeCall::instruction_size); // call; delay slot
568 } else {
569 return klass_load_size +
570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
571 NativeCall::instruction_size); // call; delay slot
572 }
573 }
574 }
576 int MachCallRuntimeNode::ret_addr_offset() {
577 #ifdef _LP64
578 if (MacroAssembler::is_far_target(entry_point())) {
579 return NativeFarCall::instruction_size;
580 } else {
581 return NativeCall::instruction_size;
582 }
583 #else
584 return NativeCall::instruction_size; // call; delay slot
585 #endif
586 }
588 // Indicate if the safepoint node needs the polling page as an input.
589 // Since Sparc does not have absolute addressing, it does.
590 bool SafePointNode::needs_polling_address_input() {
591 return true;
592 }
594 // emit an interrupt that is caught by the debugger (for debugging compiler)
595 void emit_break(CodeBuffer &cbuf) {
596 MacroAssembler _masm(&cbuf);
597 __ breakpoint_trap();
598 }
600 #ifndef PRODUCT
601 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
602 st->print("TA");
603 }
604 #endif
606 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
607 emit_break(cbuf);
608 }
610 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
611 return MachNode::size(ra_);
612 }
614 // Traceable jump
615 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
616 MacroAssembler _masm(&cbuf);
617 Register rdest = reg_to_register_object(jump_target);
618 __ JMP(rdest, 0);
619 __ delayed()->nop();
620 }
622 // Traceable jump and set exception pc
623 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
624 MacroAssembler _masm(&cbuf);
625 Register rdest = reg_to_register_object(jump_target);
626 __ JMP(rdest, 0);
627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
628 }
630 void emit_nop(CodeBuffer &cbuf) {
631 MacroAssembler _masm(&cbuf);
632 __ nop();
633 }
635 void emit_illtrap(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ illtrap(0);
638 }
641 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
642 assert(n->rule() != loadUB_rule, "");
644 intptr_t offset = 0;
645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
646 const Node* addr = n->get_base_and_disp(offset, adr_type);
647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
648 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
649 assert(addr->bottom_type()->isa_oopptr() == atype, "");
650 atype = atype->add_offset(offset);
651 assert(disp32 == offset, "wrong disp32");
652 return atype->_offset;
653 }
656 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
657 assert(n->rule() != loadUB_rule, "");
659 intptr_t offset = 0;
660 Node* addr = n->in(2);
661 assert(addr->bottom_type()->isa_oopptr() == atype, "");
662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
663 Node* a = addr->in(2/*AddPNode::Address*/);
664 Node* o = addr->in(3/*AddPNode::Offset*/);
665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
666 atype = a->bottom_type()->is_ptr()->add_offset(offset);
667 assert(atype->isa_oop_ptr(), "still an oop");
668 }
669 offset = atype->is_ptr()->_offset;
670 if (offset != Type::OffsetBot) offset += disp32;
671 return offset;
672 }
674 static inline jdouble replicate_immI(int con, int count, int width) {
675 // Load a constant replicated "count" times with width "width"
676 int bit_width = width * 8;
677 jlong elt_val = con;
678 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
679 jlong val = elt_val;
680 for (int i = 0; i < count - 1; i++) {
681 val <<= bit_width;
682 val |= elt_val;
683 }
684 jdouble dval = *((jdouble*) &val); // coerce to double type
685 return dval;
686 }
688 // Standard Sparc opcode form2 field breakdown
689 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
690 f0 &= (1<<19)-1; // Mask displacement to 19 bits
691 int op = (f30 << 30) |
692 (f29 << 29) |
693 (f25 << 25) |
694 (f22 << 22) |
695 (f20 << 20) |
696 (f19 << 19) |
697 (f0 << 0);
698 cbuf.insts()->emit_int32(op);
699 }
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
703 f0 >>= 10; // Drop 10 bits
704 f0 &= (1<<22)-1; // Mask displacement to 22 bits
705 int op = (f30 << 30) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f0 << 0);
709 cbuf.insts()->emit_int32(op);
710 }
712 // Standard Sparc opcode form3 field breakdown
713 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
714 int op = (f30 << 30) |
715 (f25 << 25) |
716 (f19 << 19) |
717 (f14 << 14) |
718 (f5 << 5) |
719 (f0 << 0);
720 cbuf.insts()->emit_int32(op);
721 }
723 // Standard Sparc opcode form3 field breakdown
724 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
725 simm13 &= (1<<13)-1; // Mask to 13 bits
726 int op = (f30 << 30) |
727 (f25 << 25) |
728 (f19 << 19) |
729 (f14 << 14) |
730 (1 << 13) | // bit to indicate immediate-mode
731 (simm13<<0);
732 cbuf.insts()->emit_int32(op);
733 }
735 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
736 simm10 &= (1<<10)-1; // Mask to 10 bits
737 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
738 }
740 #ifdef ASSERT
741 // Helper function for VerifyOops in emit_form3_mem_reg
742 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
743 warning("VerifyOops encountered unexpected instruction:");
744 n->dump(2);
745 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
746 }
747 #endif
750 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
751 int src1_enc, int disp32, int src2_enc, int dst_enc) {
753 #ifdef ASSERT
754 // The following code implements the +VerifyOops feature.
755 // It verifies oop values which are loaded into or stored out of
756 // the current method activation. +VerifyOops complements techniques
757 // like ScavengeALot, because it eagerly inspects oops in transit,
758 // as they enter or leave the stack, as opposed to ScavengeALot,
759 // which inspects oops "at rest", in the stack or heap, at safepoints.
760 // For this reason, +VerifyOops can sometimes detect bugs very close
761 // to their point of creation. It can also serve as a cross-check
762 // on the validity of oop maps, when used toegether with ScavengeALot.
764 // It would be good to verify oops at other points, especially
765 // when an oop is used as a base pointer for a load or store.
766 // This is presently difficult, because it is hard to know when
767 // a base address is biased or not. (If we had such information,
768 // it would be easy and useful to make a two-argument version of
769 // verify_oop which unbiases the base, and performs verification.)
771 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
772 bool is_verified_oop_base = false;
773 bool is_verified_oop_load = false;
774 bool is_verified_oop_store = false;
775 int tmp_enc = -1;
776 if (VerifyOops && src1_enc != R_SP_enc) {
777 // classify the op, mainly for an assert check
778 int st_op = 0, ld_op = 0;
779 switch (primary) {
780 case Assembler::stb_op3: st_op = Op_StoreB; break;
781 case Assembler::sth_op3: st_op = Op_StoreC; break;
782 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
783 case Assembler::stw_op3: st_op = Op_StoreI; break;
784 case Assembler::std_op3: st_op = Op_StoreL; break;
785 case Assembler::stf_op3: st_op = Op_StoreF; break;
786 case Assembler::stdf_op3: st_op = Op_StoreD; break;
788 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
789 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
790 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
791 case Assembler::ldx_op3: // may become LoadP or stay LoadI
792 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
793 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
794 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
795 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
796 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
797 case Assembler::ldub_op3: ld_op = Op_LoadB; break;
798 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
800 default: ShouldNotReachHere();
801 }
802 if (tertiary == REGP_OP) {
803 if (st_op == Op_StoreI) st_op = Op_StoreP;
804 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
805 else ShouldNotReachHere();
806 if (st_op) {
807 // a store
808 // inputs are (0:control, 1:memory, 2:address, 3:value)
809 Node* n2 = n->in(3);
810 if (n2 != NULL) {
811 const Type* t = n2->bottom_type();
812 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
813 }
814 } else {
815 // a load
816 const Type* t = n->bottom_type();
817 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
818 }
819 }
821 if (ld_op) {
822 // a Load
823 // inputs are (0:control, 1:memory, 2:address)
824 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
825 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
826 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
827 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
828 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
829 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
830 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
831 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
832 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
833 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
834 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
835 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
836 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
837 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) &&
839 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) &&
840 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) &&
841 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) &&
842 !(n->rule() == loadUB_rule)) {
843 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
844 }
845 } else if (st_op) {
846 // a Store
847 // inputs are (0:control, 1:memory, 2:address, 3:value)
848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
853 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) &&
854 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) &&
855 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) &&
856 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
857 verify_oops_warning(n, n->ideal_Opcode(), st_op);
858 }
859 }
861 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
862 Node* addr = n->in(2);
863 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
864 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
865 if (atype != NULL) {
866 intptr_t offset = get_offset_from_base(n, atype, disp32);
867 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
868 if (offset != offset_2) {
869 get_offset_from_base(n, atype, disp32);
870 get_offset_from_base_2(n, atype, disp32);
871 }
872 assert(offset == offset_2, "different offsets");
873 if (offset == disp32) {
874 // we now know that src1 is a true oop pointer
875 is_verified_oop_base = true;
876 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
877 if( primary == Assembler::ldd_op3 ) {
878 is_verified_oop_base = false; // Cannot 'ldd' into O7
879 } else {
880 tmp_enc = dst_enc;
881 dst_enc = R_O7_enc; // Load into O7; preserve source oop
882 assert(src1_enc != dst_enc, "");
883 }
884 }
885 }
886 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
887 || offset == oopDesc::mark_offset_in_bytes())) {
888 // loading the mark should not be allowed either, but
889 // we don't check this since it conflicts with InlineObjectHash
890 // usage of LoadINode to get the mark. We could keep the
891 // check if we create a new LoadMarkNode
892 // but do not verify the object before its header is initialized
893 ShouldNotReachHere();
894 }
895 }
896 }
897 }
898 }
899 #endif
901 uint instr;
902 instr = (Assembler::ldst_op << 30)
903 | (dst_enc << 25)
904 | (primary << 19)
905 | (src1_enc << 14);
907 uint index = src2_enc;
908 int disp = disp32;
910 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
911 disp += STACK_BIAS;
913 // We should have a compiler bailout here rather than a guarantee.
914 // Better yet would be some mechanism to handle variable-size matches correctly.
915 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
917 if( disp == 0 ) {
918 // use reg-reg form
919 // bit 13 is already zero
920 instr |= index;
921 } else {
922 // use reg-imm form
923 instr |= 0x00002000; // set bit 13 to one
924 instr |= disp & 0x1FFF;
925 }
927 cbuf.insts()->emit_int32(instr);
929 #ifdef ASSERT
930 {
931 MacroAssembler _masm(&cbuf);
932 if (is_verified_oop_base) {
933 __ verify_oop(reg_to_register_object(src1_enc));
934 }
935 if (is_verified_oop_store) {
936 __ verify_oop(reg_to_register_object(dst_enc));
937 }
938 if (tmp_enc != -1) {
939 __ mov(O7, reg_to_register_object(tmp_enc));
940 }
941 if (is_verified_oop_load) {
942 __ verify_oop(reg_to_register_object(dst_enc));
943 }
944 }
945 #endif
946 }
948 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
949 // The method which records debug information at every safepoint
950 // expects the call to be the first instruction in the snippet as
951 // it creates a PcDesc structure which tracks the offset of a call
952 // from the start of the codeBlob. This offset is computed as
953 // code_end() - code_begin() of the code which has been emitted
954 // so far.
955 // In this particular case we have skirted around the problem by
956 // putting the "mov" instruction in the delay slot but the problem
957 // may bite us again at some other point and a cleaner/generic
958 // solution using relocations would be needed.
959 MacroAssembler _masm(&cbuf);
960 __ set_inst_mark();
962 // We flush the current window just so that there is a valid stack copy
963 // the fact that the current window becomes active again instantly is
964 // not a problem there is nothing live in it.
966 #ifdef ASSERT
967 int startpos = __ offset();
968 #endif /* ASSERT */
970 __ call((address)entry_point, rtype);
972 if (preserve_g2) __ delayed()->mov(G2, L7);
973 else __ delayed()->nop();
975 if (preserve_g2) __ mov(L7, G2);
977 #ifdef ASSERT
978 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
979 #ifdef _LP64
980 // Trash argument dump slots.
981 __ set(0xb0b8ac0db0b8ac0d, G1);
982 __ mov(G1, G5);
983 __ stx(G1, SP, STACK_BIAS + 0x80);
984 __ stx(G1, SP, STACK_BIAS + 0x88);
985 __ stx(G1, SP, STACK_BIAS + 0x90);
986 __ stx(G1, SP, STACK_BIAS + 0x98);
987 __ stx(G1, SP, STACK_BIAS + 0xA0);
988 __ stx(G1, SP, STACK_BIAS + 0xA8);
989 #else // _LP64
990 // this is also a native call, so smash the first 7 stack locations,
991 // and the various registers
993 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
994 // while [SP+0x44..0x58] are the argument dump slots.
995 __ set((intptr_t)0xbaadf00d, G1);
996 __ mov(G1, G5);
997 __ sllx(G1, 32, G1);
998 __ or3(G1, G5, G1);
999 __ mov(G1, G5);
1000 __ stx(G1, SP, 0x40);
1001 __ stx(G1, SP, 0x48);
1002 __ stx(G1, SP, 0x50);
1003 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1004 #endif // _LP64
1005 }
1006 #endif /*ASSERT*/
1007 }
1009 //=============================================================================
1010 // REQUIRED FUNCTIONALITY for encoding
1011 void emit_lo(CodeBuffer &cbuf, int val) { }
1012 void emit_hi(CodeBuffer &cbuf, int val) { }
1015 //=============================================================================
1016 const bool Matcher::constant_table_absolute_addressing = false;
1017 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask;
1019 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1020 Compile* C = ra_->C;
1021 Compile::ConstantTable& constant_table = C->constant_table();
1022 MacroAssembler _masm(&cbuf);
1024 Register r = as_Register(ra_->get_encode(this));
1025 CodeSection* cs = __ code()->consts();
1026 int consts_size = cs->align_at_start(cs->size());
1028 if (UseRDPCForConstantTableBase) {
1029 // For the following RDPC logic to work correctly the consts
1030 // section must be allocated right before the insts section. This
1031 // assert checks for that. The layout and the SECT_* constants
1032 // are defined in src/share/vm/asm/codeBuffer.hpp.
1033 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1034 int offset = __ offset();
1035 int disp;
1037 // If the displacement from the current PC to the constant table
1038 // base fits into simm13 we set the constant table base to the
1039 // current PC.
1040 if (__ is_simm13(-(consts_size + offset))) {
1041 constant_table.set_table_base_offset(-(consts_size + offset));
1042 disp = 0;
1043 } else {
1044 // If the offset of the top constant (last entry in the table)
1045 // fits into simm13 we set the constant table base to the actual
1046 // table base.
1047 if (__ is_simm13(constant_table.top_offset())) {
1048 constant_table.set_table_base_offset(0);
1049 disp = consts_size + offset;
1050 } else {
1051 // Otherwise we set the constant table base in the middle of the
1052 // constant table.
1053 int half_consts_size = consts_size / 2;
1054 assert(half_consts_size * 2 == consts_size, "sanity");
1055 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement.
1056 disp = half_consts_size + offset;
1057 }
1058 }
1060 __ rdpc(r);
1062 if (disp != 0) {
1063 assert(r != O7, "need temporary");
1064 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1065 }
1066 }
1067 else {
1068 // Materialize the constant table base.
1069 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1070 address baseaddr = cs->start() + -(constant_table.table_base_offset());
1071 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1072 AddressLiteral base(baseaddr, rspec);
1073 __ set(base, r);
1074 }
1075 }
1077 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1078 if (UseRDPCForConstantTableBase) {
1079 // This is really the worst case but generally it's only 1 instruction.
1080 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1081 } else {
1082 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1083 }
1084 }
1086 #ifndef PRODUCT
1087 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1088 char reg[128];
1089 ra_->dump_register(this, reg);
1090 if (UseRDPCForConstantTableBase) {
1091 st->print("RDPC %s\t! constant table base", reg);
1092 } else {
1093 st->print("SET &constanttable,%s\t! constant table base", reg);
1094 }
1095 }
1096 #endif
1099 //=============================================================================
1101 #ifndef PRODUCT
1102 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1103 Compile* C = ra_->C;
1105 for (int i = 0; i < OptoPrologueNops; i++) {
1106 st->print_cr("NOP"); st->print("\t");
1107 }
1109 if( VerifyThread ) {
1110 st->print_cr("Verify_Thread"); st->print("\t");
1111 }
1113 size_t framesize = C->frame_slots() << LogBytesPerInt;
1115 // Calls to C2R adapters often do not accept exceptional returns.
1116 // We require that their callers must bang for them. But be careful, because
1117 // some VM calls (such as call site linkage) can use several kilobytes of
1118 // stack. But the stack safety zone should account for that.
1119 // See bugs 4446381, 4468289, 4497237.
1120 if (C->need_stack_bang(framesize)) {
1121 st->print_cr("! stack bang"); st->print("\t");
1122 }
1124 if (Assembler::is_simm13(-framesize)) {
1125 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1126 } else {
1127 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1128 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1129 st->print ("SAVE R_SP,R_G3,R_SP");
1130 }
1132 }
1133 #endif
1135 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1136 Compile* C = ra_->C;
1137 MacroAssembler _masm(&cbuf);
1139 for (int i = 0; i < OptoPrologueNops; i++) {
1140 __ nop();
1141 }
1143 __ verify_thread();
1145 size_t framesize = C->frame_slots() << LogBytesPerInt;
1146 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1147 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1149 // Calls to C2R adapters often do not accept exceptional returns.
1150 // We require that their callers must bang for them. But be careful, because
1151 // some VM calls (such as call site linkage) can use several kilobytes of
1152 // stack. But the stack safety zone should account for that.
1153 // See bugs 4446381, 4468289, 4497237.
1154 if (C->need_stack_bang(framesize)) {
1155 __ generate_stack_overflow_check(framesize);
1156 }
1158 if (Assembler::is_simm13(-framesize)) {
1159 __ save(SP, -framesize, SP);
1160 } else {
1161 __ sethi(-framesize & ~0x3ff, G3);
1162 __ add(G3, -framesize & 0x3ff, G3);
1163 __ save(SP, G3, SP);
1164 }
1165 C->set_frame_complete( __ offset() );
1166 }
1168 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1169 return MachNode::size(ra_);
1170 }
1172 int MachPrologNode::reloc() const {
1173 return 10; // a large enough number
1174 }
1176 //=============================================================================
1177 #ifndef PRODUCT
1178 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1179 Compile* C = ra_->C;
1181 if( do_polling() && ra_->C->is_method_compilation() ) {
1182 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1183 #ifdef _LP64
1184 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1185 #else
1186 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1187 #endif
1188 }
1190 if( do_polling() )
1191 st->print("RET\n\t");
1193 st->print("RESTORE");
1194 }
1195 #endif
1197 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1198 MacroAssembler _masm(&cbuf);
1199 Compile* C = ra_->C;
1201 __ verify_thread();
1203 // If this does safepoint polling, then do it here
1204 if( do_polling() && ra_->C->is_method_compilation() ) {
1205 AddressLiteral polling_page(os::get_polling_page());
1206 __ sethi(polling_page, L0);
1207 __ relocate(relocInfo::poll_return_type);
1208 __ ld_ptr( L0, 0, G0 );
1209 }
1211 // If this is a return, then stuff the restore in the delay slot
1212 if( do_polling() ) {
1213 __ ret();
1214 __ delayed()->restore();
1215 } else {
1216 __ restore();
1217 }
1218 }
1220 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1221 return MachNode::size(ra_);
1222 }
1224 int MachEpilogNode::reloc() const {
1225 return 16; // a large enough number
1226 }
1228 const Pipeline * MachEpilogNode::pipeline() const {
1229 return MachNode::pipeline_class();
1230 }
1232 int MachEpilogNode::safepoint_offset() const {
1233 assert( do_polling(), "no return for this epilog node");
1234 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1235 }
1237 //=============================================================================
1239 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1240 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1241 static enum RC rc_class( OptoReg::Name reg ) {
1242 if( !OptoReg::is_valid(reg) ) return rc_bad;
1243 if (OptoReg::is_stack(reg)) return rc_stack;
1244 VMReg r = OptoReg::as_VMReg(reg);
1245 if (r->is_Register()) return rc_int;
1246 assert(r->is_FloatRegister(), "must be");
1247 return rc_float;
1248 }
1250 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1251 if( cbuf ) {
1252 // Better yet would be some mechanism to handle variable-size matches correctly
1253 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1254 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1255 } else {
1256 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1257 }
1258 }
1259 #ifndef PRODUCT
1260 else if( !do_size ) {
1261 if( size != 0 ) st->print("\n\t");
1262 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1263 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1264 }
1265 #endif
1266 return size+4;
1267 }
1269 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1270 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1271 #ifndef PRODUCT
1272 else if( !do_size ) {
1273 if( size != 0 ) st->print("\n\t");
1274 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1275 }
1276 #endif
1277 return size+4;
1278 }
1280 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1281 PhaseRegAlloc *ra_,
1282 bool do_size,
1283 outputStream* st ) const {
1284 // Get registers to move
1285 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1286 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1287 OptoReg::Name dst_second = ra_->get_reg_second(this );
1288 OptoReg::Name dst_first = ra_->get_reg_first(this );
1290 enum RC src_second_rc = rc_class(src_second);
1291 enum RC src_first_rc = rc_class(src_first);
1292 enum RC dst_second_rc = rc_class(dst_second);
1293 enum RC dst_first_rc = rc_class(dst_first);
1295 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1297 // Generate spill code!
1298 int size = 0;
1300 if( src_first == dst_first && src_second == dst_second )
1301 return size; // Self copy, no move
1303 // --------------------------------------
1304 // Check for mem-mem move. Load into unused float registers and fall into
1305 // the float-store case.
1306 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1307 int offset = ra_->reg2offset(src_first);
1308 // Further check for aligned-adjacent pair, so we can use a double load
1309 if( (src_first&1)==0 && src_first+1 == src_second ) {
1310 src_second = OptoReg::Name(R_F31_num);
1311 src_second_rc = rc_float;
1312 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1313 } else {
1314 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1315 }
1316 src_first = OptoReg::Name(R_F30_num);
1317 src_first_rc = rc_float;
1318 }
1320 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1321 int offset = ra_->reg2offset(src_second);
1322 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1323 src_second = OptoReg::Name(R_F31_num);
1324 src_second_rc = rc_float;
1325 }
1327 // --------------------------------------
1328 // Check for float->int copy; requires a trip through memory
1329 if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
1330 int offset = frame::register_save_words*wordSize;
1331 if( cbuf ) {
1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1333 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1334 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1336 }
1337 #ifndef PRODUCT
1338 else if( !do_size ) {
1339 if( size != 0 ) st->print("\n\t");
1340 st->print( "SUB R_SP,16,R_SP\n");
1341 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1342 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1343 st->print("\tADD R_SP,16,R_SP\n");
1344 }
1345 #endif
1346 size += 16;
1347 }
1349 // --------------------------------------
1350 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1351 // In such cases, I have to do the big-endian swap. For aligned targets, the
1352 // hardware does the flop for me. Doubles are always aligned, so no problem
1353 // there. Misaligned sources only come from native-long-returns (handled
1354 // special below).
1355 #ifndef _LP64
1356 if( src_first_rc == rc_int && // source is already big-endian
1357 src_second_rc != rc_bad && // 64-bit move
1358 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1359 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1360 // Do the big-endian flop.
1361 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1362 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1363 }
1364 #endif
1366 // --------------------------------------
1367 // Check for integer reg-reg copy
1368 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1369 #ifndef _LP64
1370 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1371 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1372 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1373 // operand contains the least significant word of the 64-bit value and vice versa.
1374 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1375 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1376 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1377 if( cbuf ) {
1378 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1379 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1380 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1381 #ifndef PRODUCT
1382 } else if( !do_size ) {
1383 if( size != 0 ) st->print("\n\t");
1384 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1385 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1386 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1387 #endif
1388 }
1389 return size+12;
1390 }
1391 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1392 // returning a long value in I0/I1
1393 // a SpillCopy must be able to target a return instruction's reg_class
1394 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1395 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1396 // operand contains the least significant word of the 64-bit value and vice versa.
1397 OptoReg::Name tdest = dst_first;
1399 if (src_first == dst_first) {
1400 tdest = OptoReg::Name(R_O7_num);
1401 size += 4;
1402 }
1404 if( cbuf ) {
1405 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1406 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1407 // ShrL_reg_imm6
1408 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1409 // ShrR_reg_imm6 src, 0, dst
1410 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1411 if (tdest != dst_first) {
1412 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1413 }
1414 }
1415 #ifndef PRODUCT
1416 else if( !do_size ) {
1417 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1418 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1419 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1420 if (tdest != dst_first) {
1421 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1422 }
1423 }
1424 #endif // PRODUCT
1425 return size+8;
1426 }
1427 #endif // !_LP64
1428 // Else normal reg-reg copy
1429 assert( src_second != dst_first, "smashed second before evacuating it" );
1430 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1431 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1432 // This moves an aligned adjacent pair.
1433 // See if we are done.
1434 if( src_first+1 == src_second && dst_first+1 == dst_second )
1435 return size;
1436 }
1438 // Check for integer store
1439 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1440 int offset = ra_->reg2offset(dst_first);
1441 // Further check for aligned-adjacent pair, so we can use a double store
1442 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1443 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1444 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1445 }
1447 // Check for integer load
1448 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1449 int offset = ra_->reg2offset(src_first);
1450 // Further check for aligned-adjacent pair, so we can use a double load
1451 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1452 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1453 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1454 }
1456 // Check for float reg-reg copy
1457 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1458 // Further check for aligned-adjacent pair, so we can use a double move
1459 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1460 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1461 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1462 }
1464 // Check for float store
1465 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1466 int offset = ra_->reg2offset(dst_first);
1467 // Further check for aligned-adjacent pair, so we can use a double store
1468 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1469 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1470 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1471 }
1473 // Check for float load
1474 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1475 int offset = ra_->reg2offset(src_first);
1476 // Further check for aligned-adjacent pair, so we can use a double load
1477 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1478 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1479 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1480 }
1482 // --------------------------------------------------------------------
1483 // Check for hi bits still needing moving. Only happens for misaligned
1484 // arguments to native calls.
1485 if( src_second == dst_second )
1486 return size; // Self copy; no move
1487 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1489 #ifndef _LP64
1490 // In the LP64 build, all registers can be moved as aligned/adjacent
1491 // pairs, so there's never any need to move the high bits separately.
1492 // The 32-bit builds have to deal with the 32-bit ABI which can force
1493 // all sorts of silly alignment problems.
1495 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1496 // 32-bits of a 64-bit register, but are needed in low bits of another
1497 // register (else it's a hi-bits-to-hi-bits copy which should have
1498 // happened already as part of a 64-bit move)
1499 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1500 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1501 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1502 // Shift src_second down to dst_second's low bits.
1503 if( cbuf ) {
1504 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1505 #ifndef PRODUCT
1506 } else if( !do_size ) {
1507 if( size != 0 ) st->print("\n\t");
1508 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1509 #endif
1510 }
1511 return size+4;
1512 }
1514 // Check for high word integer store. Must down-shift the hi bits
1515 // into a temp register, then fall into the case of storing int bits.
1516 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1517 // Shift src_second down to dst_second's low bits.
1518 if( cbuf ) {
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1520 #ifndef PRODUCT
1521 } else if( !do_size ) {
1522 if( size != 0 ) st->print("\n\t");
1523 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1524 #endif
1525 }
1526 size+=4;
1527 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1528 }
1530 // Check for high word integer load
1531 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1532 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1534 // Check for high word integer store
1535 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1536 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1538 // Check for high word float store
1539 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1540 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1542 #endif // !_LP64
1544 Unimplemented();
1545 }
1547 #ifndef PRODUCT
1548 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1549 implementation( NULL, ra_, false, st );
1550 }
1551 #endif
1553 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1554 implementation( &cbuf, ra_, false, NULL );
1555 }
1557 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1558 return implementation( NULL, ra_, true, NULL );
1559 }
1561 //=============================================================================
1562 #ifndef PRODUCT
1563 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1564 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1565 }
1566 #endif
1568 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1569 MacroAssembler _masm(&cbuf);
1570 for(int i = 0; i < _count; i += 1) {
1571 __ nop();
1572 }
1573 }
1575 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1576 return 4 * _count;
1577 }
1580 //=============================================================================
1581 #ifndef PRODUCT
1582 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1583 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1584 int reg = ra_->get_reg_first(this);
1585 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1586 }
1587 #endif
1589 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1590 MacroAssembler _masm(&cbuf);
1591 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1592 int reg = ra_->get_encode(this);
1594 if (Assembler::is_simm13(offset)) {
1595 __ add(SP, offset, reg_to_register_object(reg));
1596 } else {
1597 __ set(offset, O7);
1598 __ add(SP, O7, reg_to_register_object(reg));
1599 }
1600 }
1602 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1603 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1604 assert(ra_ == ra_->C->regalloc(), "sanity");
1605 return ra_->C->scratch_emit_size(this);
1606 }
1608 //=============================================================================
1610 // emit call stub, compiled java to interpretor
1611 void emit_java_to_interp(CodeBuffer &cbuf ) {
1613 // Stub is fixed up when the corresponding call is converted from calling
1614 // compiled code to calling interpreted code.
1615 // set (empty), G5
1616 // jmp -1
1618 address mark = cbuf.insts_mark(); // get mark within main instrs section
1620 MacroAssembler _masm(&cbuf);
1622 address base =
1623 __ start_a_stub(Compile::MAX_stubs_size);
1624 if (base == NULL) return; // CodeBuffer::expand failed
1626 // static stub relocation stores the instruction address of the call
1627 __ relocate(static_stub_Relocation::spec(mark));
1629 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1631 __ set_inst_mark();
1632 AddressLiteral addrlit(-1);
1633 __ JUMP(addrlit, G3, 0);
1635 __ delayed()->nop();
1637 // Update current stubs pointer and restore code_end.
1638 __ end_a_stub();
1639 }
1641 // size of call stub, compiled java to interpretor
1642 uint size_java_to_interp() {
1643 // This doesn't need to be accurate but it must be larger or equal to
1644 // the real size of the stub.
1645 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1646 NativeJump::instruction_size + // sethi; jmp; nop
1647 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1648 }
1649 // relocation entries for call stub, compiled java to interpretor
1650 uint reloc_java_to_interp() {
1651 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1652 }
1655 //=============================================================================
1656 #ifndef PRODUCT
1657 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 st->print_cr("\nUEP:");
1659 #ifdef _LP64
1660 if (UseCompressedOops) {
1661 assert(Universe::heap() != NULL, "java heap should be initialized");
1662 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1663 st->print_cr("\tSLL R_G5,3,R_G5");
1664 if (Universe::narrow_oop_base() != NULL)
1665 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1666 } else {
1667 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1668 }
1669 st->print_cr("\tCMP R_G5,R_G3" );
1670 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1671 #else // _LP64
1672 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1673 st->print_cr("\tCMP R_G5,R_G3" );
1674 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1675 #endif // _LP64
1676 }
1677 #endif
1679 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1680 MacroAssembler _masm(&cbuf);
1681 Label L;
1682 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1683 Register temp_reg = G3;
1684 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1686 // Load klass from receiver
1687 __ load_klass(O0, temp_reg);
1688 // Compare against expected klass
1689 __ cmp(temp_reg, G5_ic_reg);
1690 // Branch to miss code, checks xcc or icc depending
1691 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1692 }
1694 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1695 return MachNode::size(ra_);
1696 }
1699 //=============================================================================
1701 uint size_exception_handler() {
1702 if (TraceJumps) {
1703 return (400); // just a guess
1704 }
1705 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1706 }
1708 uint size_deopt_handler() {
1709 if (TraceJumps) {
1710 return (400); // just a guess
1711 }
1712 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1713 }
1715 // Emit exception handler code.
1716 int emit_exception_handler(CodeBuffer& cbuf) {
1717 Register temp_reg = G3;
1718 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1719 MacroAssembler _masm(&cbuf);
1721 address base =
1722 __ start_a_stub(size_exception_handler());
1723 if (base == NULL) return 0; // CodeBuffer::expand failed
1725 int offset = __ offset();
1727 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1728 __ delayed()->nop();
1730 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1732 __ end_a_stub();
1734 return offset;
1735 }
1737 int emit_deopt_handler(CodeBuffer& cbuf) {
1738 // Can't use any of the current frame's registers as we may have deopted
1739 // at a poll and everything (including G3) can be live.
1740 Register temp_reg = L0;
1741 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1742 MacroAssembler _masm(&cbuf);
1744 address base =
1745 __ start_a_stub(size_deopt_handler());
1746 if (base == NULL) return 0; // CodeBuffer::expand failed
1748 int offset = __ offset();
1749 __ save_frame(0);
1750 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1751 __ delayed()->restore();
1753 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1755 __ end_a_stub();
1756 return offset;
1758 }
1760 // Given a register encoding, produce a Integer Register object
1761 static Register reg_to_register_object(int register_encoding) {
1762 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1763 return as_Register(register_encoding);
1764 }
1766 // Given a register encoding, produce a single-precision Float Register object
1767 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1768 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1769 return as_SingleFloatRegister(register_encoding);
1770 }
1772 // Given a register encoding, produce a double-precision Float Register object
1773 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1774 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1775 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1776 return as_DoubleFloatRegister(register_encoding);
1777 }
1779 const bool Matcher::match_rule_supported(int opcode) {
1780 if (!has_match_rule(opcode))
1781 return false;
1783 switch (opcode) {
1784 case Op_CountLeadingZerosI:
1785 case Op_CountLeadingZerosL:
1786 case Op_CountTrailingZerosI:
1787 case Op_CountTrailingZerosL:
1788 if (!UsePopCountInstruction)
1789 return false;
1790 break;
1791 }
1793 return true; // Per default match rules are supported.
1794 }
1796 int Matcher::regnum_to_fpu_offset(int regnum) {
1797 return regnum - 32; // The FP registers are in the second chunk
1798 }
1800 #ifdef ASSERT
1801 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1802 #endif
1804 // Vector width in bytes
1805 const uint Matcher::vector_width_in_bytes(void) {
1806 return 8;
1807 }
1809 // Vector ideal reg
1810 const uint Matcher::vector_ideal_reg(void) {
1811 return Op_RegD;
1812 }
1814 // USII supports fxtof through the whole range of number, USIII doesn't
1815 const bool Matcher::convL2FSupported(void) {
1816 return VM_Version::has_fast_fxtof();
1817 }
1819 // Is this branch offset short enough that a short branch can be used?
1820 //
1821 // NOTE: If the platform does not provide any short branch variants, then
1822 // this method should return false for offset 0.
1823 bool Matcher::is_short_branch_offset(int rule, int offset) {
1824 return false;
1825 }
1827 const bool Matcher::isSimpleConstant64(jlong value) {
1828 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1829 // Depends on optimizations in MacroAssembler::setx.
1830 int hi = (int)(value >> 32);
1831 int lo = (int)(value & ~0);
1832 return (hi == 0) || (hi == -1) || (lo == 0);
1833 }
1835 // No scaling for the parameter the ClearArray node.
1836 const bool Matcher::init_array_count_is_in_bytes = true;
1838 // Threshold size for cleararray.
1839 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1841 // Should the Matcher clone shifts on addressing modes, expecting them to
1842 // be subsumed into complex addressing expressions or compute them into
1843 // registers? True for Intel but false for most RISCs
1844 const bool Matcher::clone_shift_expressions = false;
1846 bool Matcher::narrow_oop_use_complex_address() {
1847 NOT_LP64(ShouldNotCallThis());
1848 assert(UseCompressedOops, "only for compressed oops code");
1849 return false;
1850 }
1852 // Is it better to copy float constants, or load them directly from memory?
1853 // Intel can load a float constant from a direct address, requiring no
1854 // extra registers. Most RISCs will have to materialize an address into a
1855 // register first, so they would do better to copy the constant from stack.
1856 const bool Matcher::rematerialize_float_constants = false;
1858 // If CPU can load and store mis-aligned doubles directly then no fixup is
1859 // needed. Else we split the double into 2 integer pieces and move it
1860 // piece-by-piece. Only happens when passing doubles into C code as the
1861 // Java calling convention forces doubles to be aligned.
1862 #ifdef _LP64
1863 const bool Matcher::misaligned_doubles_ok = true;
1864 #else
1865 const bool Matcher::misaligned_doubles_ok = false;
1866 #endif
1868 // No-op on SPARC.
1869 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1870 }
1872 // Advertise here if the CPU requires explicit rounding operations
1873 // to implement the UseStrictFP mode.
1874 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1876 // Are floats conerted to double when stored to stack during deoptimization?
1877 // Sparc does not handle callee-save floats.
1878 bool Matcher::float_in_double() { return false; }
1880 // Do ints take an entire long register or just half?
1881 // Note that we if-def off of _LP64.
1882 // The relevant question is how the int is callee-saved. In _LP64
1883 // the whole long is written but de-opt'ing will have to extract
1884 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1885 #ifdef _LP64
1886 const bool Matcher::int_in_long = true;
1887 #else
1888 const bool Matcher::int_in_long = false;
1889 #endif
1891 // Return whether or not this register is ever used as an argument. This
1892 // function is used on startup to build the trampoline stubs in generateOptoStub.
1893 // Registers not mentioned will be killed by the VM call in the trampoline, and
1894 // arguments in those registers not be available to the callee.
1895 bool Matcher::can_be_java_arg( int reg ) {
1896 // Standard sparc 6 args in registers
1897 if( reg == R_I0_num ||
1898 reg == R_I1_num ||
1899 reg == R_I2_num ||
1900 reg == R_I3_num ||
1901 reg == R_I4_num ||
1902 reg == R_I5_num ) return true;
1903 #ifdef _LP64
1904 // 64-bit builds can pass 64-bit pointers and longs in
1905 // the high I registers
1906 if( reg == R_I0H_num ||
1907 reg == R_I1H_num ||
1908 reg == R_I2H_num ||
1909 reg == R_I3H_num ||
1910 reg == R_I4H_num ||
1911 reg == R_I5H_num ) return true;
1913 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1914 return true;
1915 }
1917 #else
1918 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1919 // Longs cannot be passed in O regs, because O regs become I regs
1920 // after a 'save' and I regs get their high bits chopped off on
1921 // interrupt.
1922 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1923 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1924 #endif
1925 // A few float args in registers
1926 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1928 return false;
1929 }
1931 bool Matcher::is_spillable_arg( int reg ) {
1932 return can_be_java_arg(reg);
1933 }
1935 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1936 // Use hardware SDIVX instruction when it is
1937 // faster than a code which use multiply.
1938 return VM_Version::has_fast_idiv();
1939 }
1941 // Register for DIVI projection of divmodI
1942 RegMask Matcher::divI_proj_mask() {
1943 ShouldNotReachHere();
1944 return RegMask();
1945 }
1947 // Register for MODI projection of divmodI
1948 RegMask Matcher::modI_proj_mask() {
1949 ShouldNotReachHere();
1950 return RegMask();
1951 }
1953 // Register for DIVL projection of divmodL
1954 RegMask Matcher::divL_proj_mask() {
1955 ShouldNotReachHere();
1956 return RegMask();
1957 }
1959 // Register for MODL projection of divmodL
1960 RegMask Matcher::modL_proj_mask() {
1961 ShouldNotReachHere();
1962 return RegMask();
1963 }
1965 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1966 return L7_REGP_mask;
1967 }
1969 %}
1972 // The intptr_t operand types, defined by textual substitution.
1973 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
1974 #ifdef _LP64
1975 #define immX immL
1976 #define immX13 immL13
1977 #define immX13m7 immL13m7
1978 #define iRegX iRegL
1979 #define g1RegX g1RegL
1980 #else
1981 #define immX immI
1982 #define immX13 immI13
1983 #define immX13m7 immI13m7
1984 #define iRegX iRegI
1985 #define g1RegX g1RegI
1986 #endif
1988 //----------ENCODING BLOCK-----------------------------------------------------
1989 // This block specifies the encoding classes used by the compiler to output
1990 // byte streams. Encoding classes are parameterized macros used by
1991 // Machine Instruction Nodes in order to generate the bit encoding of the
1992 // instruction. Operands specify their base encoding interface with the
1993 // interface keyword. There are currently supported four interfaces,
1994 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1995 // operand to generate a function which returns its register number when
1996 // queried. CONST_INTER causes an operand to generate a function which
1997 // returns the value of the constant when queried. MEMORY_INTER causes an
1998 // operand to generate four functions which return the Base Register, the
1999 // Index Register, the Scale Value, and the Offset Value of the operand when
2000 // queried. COND_INTER causes an operand to generate six functions which
2001 // return the encoding code (ie - encoding bits for the instruction)
2002 // associated with each basic boolean condition for a conditional instruction.
2003 //
2004 // Instructions specify two basic values for encoding. Again, a function
2005 // is available to check if the constant displacement is an oop. They use the
2006 // ins_encode keyword to specify their encoding classes (which must be
2007 // a sequence of enc_class names, and their parameters, specified in
2008 // the encoding block), and they use the
2009 // opcode keyword to specify, in order, their primary, secondary, and
2010 // tertiary opcode. Only the opcode sections which a particular instruction
2011 // needs for encoding need to be specified.
2012 encode %{
2013 enc_class enc_untested %{
2014 #ifdef ASSERT
2015 MacroAssembler _masm(&cbuf);
2016 __ untested("encoding");
2017 #endif
2018 %}
2020 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2021 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2022 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2023 %}
2025 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2026 emit_form3_mem_reg(cbuf, this, $primary, -1,
2027 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2028 %}
2030 enc_class form3_mem_prefetch_read( memory mem ) %{
2031 emit_form3_mem_reg(cbuf, this, $primary, -1,
2032 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2033 %}
2035 enc_class form3_mem_prefetch_write( memory mem ) %{
2036 emit_form3_mem_reg(cbuf, this, $primary, -1,
2037 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2038 %}
2040 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2041 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2042 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2043 guarantee($mem$$index == R_G0_enc, "double index?");
2044 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2045 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2046 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2047 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2048 %}
2050 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2051 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" );
2052 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
2053 guarantee($mem$$index == R_G0_enc, "double index?");
2054 // Load long with 2 instructions
2055 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2056 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2057 %}
2059 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2060 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2061 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2062 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2063 %}
2065 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2066 // Encode a reg-reg copy. If it is useless, then empty encoding.
2067 if( $rs2$$reg != $rd$$reg )
2068 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2069 %}
2071 // Target lo half of long
2072 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2073 // Encode a reg-reg copy. If it is useless, then empty encoding.
2074 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2075 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2076 %}
2078 // Source lo half of long
2079 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2080 // Encode a reg-reg copy. If it is useless, then empty encoding.
2081 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2082 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2083 %}
2085 // Target hi half of long
2086 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2087 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2088 %}
2090 // Source lo half of long, and leave it sign extended.
2091 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2092 // Sign extend low half
2093 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2094 %}
2096 // Source hi half of long, and leave it sign extended.
2097 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2098 // Shift high half to low half
2099 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2100 %}
2102 // Source hi half of long
2103 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2104 // Encode a reg-reg copy. If it is useless, then empty encoding.
2105 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2106 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2107 %}
2109 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2110 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2111 %}
2113 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2114 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2115 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2116 %}
2118 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2119 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2120 // clear if nothing else is happening
2121 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2122 // blt,a,pn done
2123 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2124 // mov dst,-1 in delay slot
2125 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2126 %}
2128 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2129 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2130 %}
2132 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2133 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2134 %}
2136 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2137 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2138 %}
2140 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2141 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2142 %}
2144 enc_class move_return_pc_to_o1() %{
2145 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2146 %}
2148 #ifdef _LP64
2149 /* %%% merge with enc_to_bool */
2150 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2151 MacroAssembler _masm(&cbuf);
2153 Register src_reg = reg_to_register_object($src$$reg);
2154 Register dst_reg = reg_to_register_object($dst$$reg);
2155 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2156 %}
2157 #endif
2159 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2160 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2161 MacroAssembler _masm(&cbuf);
2163 Register p_reg = reg_to_register_object($p$$reg);
2164 Register q_reg = reg_to_register_object($q$$reg);
2165 Register y_reg = reg_to_register_object($y$$reg);
2166 Register tmp_reg = reg_to_register_object($tmp$$reg);
2168 __ subcc( p_reg, q_reg, p_reg );
2169 __ add ( p_reg, y_reg, tmp_reg );
2170 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2171 %}
2173 enc_class form_d2i_helper(regD src, regF dst) %{
2174 // fcmp %fcc0,$src,$src
2175 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2176 // branch %fcc0 not-nan, predict taken
2177 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2178 // fdtoi $src,$dst
2179 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2180 // fitos $dst,$dst (if nan)
2181 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2182 // clear $dst (if nan)
2183 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2184 // carry on here...
2185 %}
2187 enc_class form_d2l_helper(regD src, regD dst) %{
2188 // fcmp %fcc0,$src,$src check for NAN
2189 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2190 // branch %fcc0 not-nan, predict taken
2191 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2192 // fdtox $src,$dst convert in delay slot
2193 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2194 // fxtod $dst,$dst (if nan)
2195 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2196 // clear $dst (if nan)
2197 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2198 // carry on here...
2199 %}
2201 enc_class form_f2i_helper(regF src, regF dst) %{
2202 // fcmps %fcc0,$src,$src
2203 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2204 // branch %fcc0 not-nan, predict taken
2205 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2206 // fstoi $src,$dst
2207 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2208 // fitos $dst,$dst (if nan)
2209 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2210 // clear $dst (if nan)
2211 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2212 // carry on here...
2213 %}
2215 enc_class form_f2l_helper(regF src, regD dst) %{
2216 // fcmps %fcc0,$src,$src
2217 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2218 // branch %fcc0 not-nan, predict taken
2219 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2220 // fstox $src,$dst
2221 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2222 // fxtod $dst,$dst (if nan)
2223 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2224 // clear $dst (if nan)
2225 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2226 // carry on here...
2227 %}
2229 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2230 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2231 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2232 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2234 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2236 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2237 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2239 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2240 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2241 %}
2243 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2244 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2245 %}
2247 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2248 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2249 %}
2251 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2252 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2253 %}
2255 enc_class form3_convI2F(regF rs2, regF rd) %{
2256 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2257 %}
2259 // Encloding class for traceable jumps
2260 enc_class form_jmpl(g3RegP dest) %{
2261 emit_jmpl(cbuf, $dest$$reg);
2262 %}
2264 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2265 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2266 %}
2268 enc_class form2_nop() %{
2269 emit_nop(cbuf);
2270 %}
2272 enc_class form2_illtrap() %{
2273 emit_illtrap(cbuf);
2274 %}
2277 // Compare longs and convert into -1, 0, 1.
2278 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2279 // CMP $src1,$src2
2280 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2281 // blt,a,pn done
2282 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2283 // mov dst,-1 in delay slot
2284 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2285 // bgt,a,pn done
2286 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2287 // mov dst,1 in delay slot
2288 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2289 // CLR $dst
2290 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2291 %}
2293 enc_class enc_PartialSubtypeCheck() %{
2294 MacroAssembler _masm(&cbuf);
2295 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2296 __ delayed()->nop();
2297 %}
2299 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
2300 MacroAssembler _masm(&cbuf);
2301 Label &L = *($labl$$label);
2302 Assembler::Predict predict_taken =
2303 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2305 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
2306 __ delayed()->nop();
2307 %}
2309 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
2310 MacroAssembler _masm(&cbuf);
2311 Label &L = *($labl$$label);
2312 Assembler::Predict predict_taken =
2313 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2315 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
2316 __ delayed()->nop();
2317 %}
2319 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
2320 MacroAssembler _masm(&cbuf);
2321 Label &L = *($labl$$label);
2322 Assembler::Predict predict_taken =
2323 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2325 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
2326 __ delayed()->nop();
2327 %}
2329 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
2330 MacroAssembler _masm(&cbuf);
2331 Label &L = *($labl$$label);
2332 Assembler::Predict predict_taken =
2333 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2335 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
2336 __ delayed()->nop();
2337 %}
2339 enc_class enc_ba( Label labl ) %{
2340 MacroAssembler _masm(&cbuf);
2341 Label &L = *($labl$$label);
2342 __ ba(false, L);
2343 __ delayed()->nop();
2344 %}
2346 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
2347 MacroAssembler _masm(&cbuf);
2348 Label &L = *$labl$$label;
2349 Assembler::Predict predict_taken =
2350 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;
2352 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
2353 __ delayed()->nop();
2354 %}
2356 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2357 int op = (Assembler::arith_op << 30) |
2358 ($dst$$reg << 25) |
2359 (Assembler::movcc_op3 << 19) |
2360 (1 << 18) | // cc2 bit for 'icc'
2361 ($cmp$$cmpcode << 14) |
2362 (0 << 13) | // select register move
2363 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2364 ($src$$reg << 0);
2365 cbuf.insts()->emit_int32(op);
2366 %}
2368 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2369 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2370 int op = (Assembler::arith_op << 30) |
2371 ($dst$$reg << 25) |
2372 (Assembler::movcc_op3 << 19) |
2373 (1 << 18) | // cc2 bit for 'icc'
2374 ($cmp$$cmpcode << 14) |
2375 (1 << 13) | // select immediate move
2376 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2377 (simm11 << 0);
2378 cbuf.insts()->emit_int32(op);
2379 %}
2381 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2382 int op = (Assembler::arith_op << 30) |
2383 ($dst$$reg << 25) |
2384 (Assembler::movcc_op3 << 19) |
2385 (0 << 18) | // cc2 bit for 'fccX'
2386 ($cmp$$cmpcode << 14) |
2387 (0 << 13) | // select register move
2388 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2389 ($src$$reg << 0);
2390 cbuf.insts()->emit_int32(op);
2391 %}
2393 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2394 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2395 int op = (Assembler::arith_op << 30) |
2396 ($dst$$reg << 25) |
2397 (Assembler::movcc_op3 << 19) |
2398 (0 << 18) | // cc2 bit for 'fccX'
2399 ($cmp$$cmpcode << 14) |
2400 (1 << 13) | // select immediate move
2401 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2402 (simm11 << 0);
2403 cbuf.insts()->emit_int32(op);
2404 %}
2406 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2407 int op = (Assembler::arith_op << 30) |
2408 ($dst$$reg << 25) |
2409 (Assembler::fpop2_op3 << 19) |
2410 (0 << 18) |
2411 ($cmp$$cmpcode << 14) |
2412 (1 << 13) | // select register move
2413 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2414 ($primary << 5) | // select single, double or quad
2415 ($src$$reg << 0);
2416 cbuf.insts()->emit_int32(op);
2417 %}
2419 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2420 int op = (Assembler::arith_op << 30) |
2421 ($dst$$reg << 25) |
2422 (Assembler::fpop2_op3 << 19) |
2423 (0 << 18) |
2424 ($cmp$$cmpcode << 14) |
2425 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2426 ($primary << 5) | // select single, double or quad
2427 ($src$$reg << 0);
2428 cbuf.insts()->emit_int32(op);
2429 %}
2431 // Used by the MIN/MAX encodings. Same as a CMOV, but
2432 // the condition comes from opcode-field instead of an argument.
2433 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2434 int op = (Assembler::arith_op << 30) |
2435 ($dst$$reg << 25) |
2436 (Assembler::movcc_op3 << 19) |
2437 (1 << 18) | // cc2 bit for 'icc'
2438 ($primary << 14) |
2439 (0 << 13) | // select register move
2440 (0 << 11) | // cc1, cc0 bits for 'icc'
2441 ($src$$reg << 0);
2442 cbuf.insts()->emit_int32(op);
2443 %}
2445 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2446 int op = (Assembler::arith_op << 30) |
2447 ($dst$$reg << 25) |
2448 (Assembler::movcc_op3 << 19) |
2449 (6 << 16) | // cc2 bit for 'xcc'
2450 ($primary << 14) |
2451 (0 << 13) | // select register move
2452 (0 << 11) | // cc1, cc0 bits for 'icc'
2453 ($src$$reg << 0);
2454 cbuf.insts()->emit_int32(op);
2455 %}
2457 enc_class Set13( immI13 src, iRegI rd ) %{
2458 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2459 %}
2461 enc_class SetHi22( immI src, iRegI rd ) %{
2462 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2463 %}
2465 enc_class Set32( immI src, iRegI rd ) %{
2466 MacroAssembler _masm(&cbuf);
2467 __ set($src$$constant, reg_to_register_object($rd$$reg));
2468 %}
2470 enc_class call_epilog %{
2471 if( VerifyStackAtCalls ) {
2472 MacroAssembler _masm(&cbuf);
2473 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2474 Register temp_reg = G3;
2475 __ add(SP, framesize, temp_reg);
2476 __ cmp(temp_reg, FP);
2477 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2478 }
2479 %}
2481 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2482 // to G1 so the register allocator will not have to deal with the misaligned register
2483 // pair.
2484 enc_class adjust_long_from_native_call %{
2485 #ifndef _LP64
2486 if (returns_long()) {
2487 // sllx O0,32,O0
2488 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2489 // srl O1,0,O1
2490 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2491 // or O0,O1,G1
2492 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2493 }
2494 #endif
2495 %}
2497 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2498 // CALL directly to the runtime
2499 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2500 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2501 /*preserve_g2=*/true);
2502 %}
2504 enc_class preserve_SP %{
2505 MacroAssembler _masm(&cbuf);
2506 __ mov(SP, L7_mh_SP_save);
2507 %}
2509 enc_class restore_SP %{
2510 MacroAssembler _masm(&cbuf);
2511 __ mov(L7_mh_SP_save, SP);
2512 %}
2514 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2515 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2516 // who we intended to call.
2517 if ( !_method ) {
2518 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2519 } else if (_optimized_virtual) {
2520 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2521 } else {
2522 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2523 }
2524 if( _method ) { // Emit stub for static call
2525 emit_java_to_interp(cbuf);
2526 }
2527 %}
2529 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2530 MacroAssembler _masm(&cbuf);
2531 __ set_inst_mark();
2532 int vtable_index = this->_vtable_index;
2533 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2534 if (vtable_index < 0) {
2535 // must be invalid_vtable_index, not nonvirtual_vtable_index
2536 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2537 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2538 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2539 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2540 // !!!!!
2541 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2542 // emit_call_dynamic_prologue( cbuf );
2543 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2545 address virtual_call_oop_addr = __ inst_mark();
2546 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2547 // who we intended to call.
2548 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2549 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2550 } else {
2551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2552 // Just go thru the vtable
2553 // get receiver klass (receiver already checked for non-null)
2554 // If we end up going thru a c2i adapter interpreter expects method in G5
2555 int off = __ offset();
2556 __ load_klass(O0, G3_scratch);
2557 int klass_load_size;
2558 if (UseCompressedOops) {
2559 assert(Universe::heap() != NULL, "java heap should be initialized");
2560 if (Universe::narrow_oop_base() == NULL)
2561 klass_load_size = 2*BytesPerInstWord;
2562 else
2563 klass_load_size = 3*BytesPerInstWord;
2564 } else {
2565 klass_load_size = 1*BytesPerInstWord;
2566 }
2567 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2568 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2569 if( __ is_simm13(v_off) ) {
2570 __ ld_ptr(G3, v_off, G5_method);
2571 } else {
2572 // Generate 2 instructions
2573 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2574 __ or3(G5_method, v_off & 0x3ff, G5_method);
2575 // ld_ptr, set_hi, set
2576 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2577 "Unexpected instruction size(s)");
2578 __ ld_ptr(G3, G5_method, G5_method);
2579 }
2580 // NOTE: for vtable dispatches, the vtable entry will never be null.
2581 // However it may very well end up in handle_wrong_method if the
2582 // method is abstract for the particular class.
2583 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2584 // jump to target (either compiled code or c2iadapter)
2585 __ jmpl(G3_scratch, G0, O7);
2586 __ delayed()->nop();
2587 }
2588 %}
2590 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2591 MacroAssembler _masm(&cbuf);
2593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2594 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2595 // we might be calling a C2I adapter which needs it.
2597 assert(temp_reg != G5_ic_reg, "conflicting registers");
2598 // Load nmethod
2599 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2601 // CALL to compiled java, indirect the contents of G3
2602 __ set_inst_mark();
2603 __ callr(temp_reg, G0);
2604 __ delayed()->nop();
2605 %}
2607 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2608 MacroAssembler _masm(&cbuf);
2609 Register Rdividend = reg_to_register_object($src1$$reg);
2610 Register Rdivisor = reg_to_register_object($src2$$reg);
2611 Register Rresult = reg_to_register_object($dst$$reg);
2613 __ sra(Rdivisor, 0, Rdivisor);
2614 __ sra(Rdividend, 0, Rdividend);
2615 __ sdivx(Rdividend, Rdivisor, Rresult);
2616 %}
2618 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2619 MacroAssembler _masm(&cbuf);
2621 Register Rdividend = reg_to_register_object($src1$$reg);
2622 int divisor = $imm$$constant;
2623 Register Rresult = reg_to_register_object($dst$$reg);
2625 __ sra(Rdividend, 0, Rdividend);
2626 __ sdivx(Rdividend, divisor, Rresult);
2627 %}
2629 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2630 MacroAssembler _masm(&cbuf);
2631 Register Rsrc1 = reg_to_register_object($src1$$reg);
2632 Register Rsrc2 = reg_to_register_object($src2$$reg);
2633 Register Rdst = reg_to_register_object($dst$$reg);
2635 __ sra( Rsrc1, 0, Rsrc1 );
2636 __ sra( Rsrc2, 0, Rsrc2 );
2637 __ mulx( Rsrc1, Rsrc2, Rdst );
2638 __ srlx( Rdst, 32, Rdst );
2639 %}
2641 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2642 MacroAssembler _masm(&cbuf);
2643 Register Rdividend = reg_to_register_object($src1$$reg);
2644 Register Rdivisor = reg_to_register_object($src2$$reg);
2645 Register Rresult = reg_to_register_object($dst$$reg);
2646 Register Rscratch = reg_to_register_object($scratch$$reg);
2648 assert(Rdividend != Rscratch, "");
2649 assert(Rdivisor != Rscratch, "");
2651 __ sra(Rdividend, 0, Rdividend);
2652 __ sra(Rdivisor, 0, Rdivisor);
2653 __ sdivx(Rdividend, Rdivisor, Rscratch);
2654 __ mulx(Rscratch, Rdivisor, Rscratch);
2655 __ sub(Rdividend, Rscratch, Rresult);
2656 %}
2658 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2659 MacroAssembler _masm(&cbuf);
2661 Register Rdividend = reg_to_register_object($src1$$reg);
2662 int divisor = $imm$$constant;
2663 Register Rresult = reg_to_register_object($dst$$reg);
2664 Register Rscratch = reg_to_register_object($scratch$$reg);
2666 assert(Rdividend != Rscratch, "");
2668 __ sra(Rdividend, 0, Rdividend);
2669 __ sdivx(Rdividend, divisor, Rscratch);
2670 __ mulx(Rscratch, divisor, Rscratch);
2671 __ sub(Rdividend, Rscratch, Rresult);
2672 %}
2674 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2675 MacroAssembler _masm(&cbuf);
2677 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2678 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2680 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2681 %}
2683 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2684 MacroAssembler _masm(&cbuf);
2686 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2687 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2689 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2690 %}
2692 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2693 MacroAssembler _masm(&cbuf);
2695 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2696 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2698 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2699 %}
2701 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2702 MacroAssembler _masm(&cbuf);
2704 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2705 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2707 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2708 %}
2710 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2711 MacroAssembler _masm(&cbuf);
2713 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2714 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2716 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2717 %}
2719 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2720 MacroAssembler _masm(&cbuf);
2722 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2723 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2725 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2726 %}
2728 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2729 MacroAssembler _masm(&cbuf);
2731 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2732 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2734 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2735 %}
2737 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2738 MacroAssembler _masm(&cbuf);
2740 Register Roop = reg_to_register_object($oop$$reg);
2741 Register Rbox = reg_to_register_object($box$$reg);
2742 Register Rscratch = reg_to_register_object($scratch$$reg);
2743 Register Rmark = reg_to_register_object($scratch2$$reg);
2745 assert(Roop != Rscratch, "");
2746 assert(Roop != Rmark, "");
2747 assert(Rbox != Rscratch, "");
2748 assert(Rbox != Rmark, "");
2750 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2751 %}
2753 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2754 MacroAssembler _masm(&cbuf);
2756 Register Roop = reg_to_register_object($oop$$reg);
2757 Register Rbox = reg_to_register_object($box$$reg);
2758 Register Rscratch = reg_to_register_object($scratch$$reg);
2759 Register Rmark = reg_to_register_object($scratch2$$reg);
2761 assert(Roop != Rscratch, "");
2762 assert(Roop != Rmark, "");
2763 assert(Rbox != Rscratch, "");
2764 assert(Rbox != Rmark, "");
2766 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2767 %}
2769 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2770 MacroAssembler _masm(&cbuf);
2771 Register Rmem = reg_to_register_object($mem$$reg);
2772 Register Rold = reg_to_register_object($old$$reg);
2773 Register Rnew = reg_to_register_object($new$$reg);
2775 // casx_under_lock picks 1 of 3 encodings:
2776 // For 32-bit pointers you get a 32-bit CAS
2777 // For 64-bit pointers you get a 64-bit CASX
2778 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2779 __ cmp( Rold, Rnew );
2780 %}
2782 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2783 Register Rmem = reg_to_register_object($mem$$reg);
2784 Register Rold = reg_to_register_object($old$$reg);
2785 Register Rnew = reg_to_register_object($new$$reg);
2787 MacroAssembler _masm(&cbuf);
2788 __ mov(Rnew, O7);
2789 __ casx(Rmem, Rold, O7);
2790 __ cmp( Rold, O7 );
2791 %}
2793 // raw int cas, used for compareAndSwap
2794 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2795 Register Rmem = reg_to_register_object($mem$$reg);
2796 Register Rold = reg_to_register_object($old$$reg);
2797 Register Rnew = reg_to_register_object($new$$reg);
2799 MacroAssembler _masm(&cbuf);
2800 __ mov(Rnew, O7);
2801 __ cas(Rmem, Rold, O7);
2802 __ cmp( Rold, O7 );
2803 %}
2805 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2806 Register Rres = reg_to_register_object($res$$reg);
2808 MacroAssembler _masm(&cbuf);
2809 __ mov(1, Rres);
2810 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2811 %}
2813 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2814 Register Rres = reg_to_register_object($res$$reg);
2816 MacroAssembler _masm(&cbuf);
2817 __ mov(1, Rres);
2818 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2819 %}
2821 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2822 MacroAssembler _masm(&cbuf);
2823 Register Rdst = reg_to_register_object($dst$$reg);
2824 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2825 : reg_to_DoubleFloatRegister_object($src1$$reg);
2826 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2827 : reg_to_DoubleFloatRegister_object($src2$$reg);
2829 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2830 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2831 %}
2833 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
2834 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2835 MacroAssembler _masm(&cbuf);
2836 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2837 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2838 Register base_pointer_arg = reg_to_register_object($base$$reg);
2840 Label loop;
2841 __ mov(nof_bytes_arg, nof_bytes_tmp);
2843 // Loop and clear, walking backwards through the array.
2844 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2845 __ bind(loop);
2846 __ deccc(nof_bytes_tmp, 8);
2847 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
2848 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
2849 // %%%% this mini-loop must not cross a cache boundary!
2850 %}
2853 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2854 Label Ldone, Lloop;
2855 MacroAssembler _masm(&cbuf);
2857 Register str1_reg = reg_to_register_object($str1$$reg);
2858 Register str2_reg = reg_to_register_object($str2$$reg);
2859 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2860 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2861 Register result_reg = reg_to_register_object($result$$reg);
2863 assert(result_reg != str1_reg &&
2864 result_reg != str2_reg &&
2865 result_reg != cnt1_reg &&
2866 result_reg != cnt2_reg ,
2867 "need different registers");
2869 // Compute the minimum of the string lengths(str1_reg) and the
2870 // difference of the string lengths (stack)
2872 // See if the lengths are different, and calculate min in str1_reg.
2873 // Stash diff in O7 in case we need it for a tie-breaker.
2874 Label Lskip;
2875 __ subcc(cnt1_reg, cnt2_reg, O7);
2876 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2877 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2878 // cnt2 is shorter, so use its count:
2879 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2880 __ bind(Lskip);
2882 // reallocate cnt1_reg, cnt2_reg, result_reg
2883 // Note: limit_reg holds the string length pre-scaled by 2
2884 Register limit_reg = cnt1_reg;
2885 Register chr2_reg = cnt2_reg;
2886 Register chr1_reg = result_reg;
2887 // str{12} are the base pointers
2889 // Is the minimum length zero?
2890 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2891 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2892 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2894 // Load first characters
2895 __ lduh(str1_reg, 0, chr1_reg);
2896 __ lduh(str2_reg, 0, chr2_reg);
2898 // Compare first characters
2899 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2900 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2901 assert(chr1_reg == result_reg, "result must be pre-placed");
2902 __ delayed()->nop();
2904 {
2905 // Check after comparing first character to see if strings are equivalent
2906 Label LSkip2;
2907 // Check if the strings start at same location
2908 __ cmp(str1_reg, str2_reg);
2909 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2910 __ delayed()->nop();
2912 // Check if the length difference is zero (in O7)
2913 __ cmp(G0, O7);
2914 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2915 __ delayed()->mov(G0, result_reg); // result is zero
2917 // Strings might not be equal
2918 __ bind(LSkip2);
2919 }
2921 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2922 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2923 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2925 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2926 __ add(str1_reg, limit_reg, str1_reg);
2927 __ add(str2_reg, limit_reg, str2_reg);
2928 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2930 // Compare the rest of the characters
2931 __ lduh(str1_reg, limit_reg, chr1_reg);
2932 __ bind(Lloop);
2933 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2934 __ lduh(str2_reg, limit_reg, chr2_reg);
2935 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2936 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2937 assert(chr1_reg == result_reg, "result must be pre-placed");
2938 __ delayed()->inccc(limit_reg, sizeof(jchar));
2939 // annul LDUH if branch is not taken to prevent access past end of string
2940 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2941 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2943 // If strings are equal up to min length, return the length difference.
2944 __ mov(O7, result_reg);
2946 // Otherwise, return the difference between the first mismatched chars.
2947 __ bind(Ldone);
2948 %}
2950 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2951 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2952 MacroAssembler _masm(&cbuf);
2954 Register str1_reg = reg_to_register_object($str1$$reg);
2955 Register str2_reg = reg_to_register_object($str2$$reg);
2956 Register cnt_reg = reg_to_register_object($cnt$$reg);
2957 Register tmp1_reg = O7;
2958 Register result_reg = reg_to_register_object($result$$reg);
2960 assert(result_reg != str1_reg &&
2961 result_reg != str2_reg &&
2962 result_reg != cnt_reg &&
2963 result_reg != tmp1_reg ,
2964 "need different registers");
2966 __ cmp(str1_reg, str2_reg); //same char[] ?
2967 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2968 __ delayed()->add(G0, 1, result_reg);
2970 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone);
2971 __ delayed()->add(G0, 1, result_reg); // count == 0
2973 //rename registers
2974 Register limit_reg = cnt_reg;
2975 Register chr1_reg = result_reg;
2976 Register chr2_reg = tmp1_reg;
2978 //check for alignment and position the pointers to the ends
2979 __ or3(str1_reg, str2_reg, chr1_reg);
2980 __ andcc(chr1_reg, 0x3, chr1_reg);
2981 // notZero means at least one not 4-byte aligned.
2982 // We could optimize the case when both arrays are not aligned
2983 // but it is not frequent case and it requires additional checks.
2984 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2985 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2987 // Compare char[] arrays aligned to 4 bytes.
2988 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2989 chr1_reg, chr2_reg, Ldone);
2990 __ ba(false,Ldone);
2991 __ delayed()->add(G0, 1, result_reg);
2993 // char by char compare
2994 __ bind(Lchar);
2995 __ add(str1_reg, limit_reg, str1_reg);
2996 __ add(str2_reg, limit_reg, str2_reg);
2997 __ neg(limit_reg); //negate count
2999 __ lduh(str1_reg, limit_reg, chr1_reg);
3000 // Lchar_loop
3001 __ bind(Lchar_loop);
3002 __ lduh(str2_reg, limit_reg, chr2_reg);
3003 __ cmp(chr1_reg, chr2_reg);
3004 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3005 __ delayed()->mov(G0, result_reg); //not equal
3006 __ inccc(limit_reg, sizeof(jchar));
3007 // annul LDUH if branch is not taken to prevent access past end of string
3008 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3009 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3011 __ add(G0, 1, result_reg); //equal
3013 __ bind(Ldone);
3014 %}
3016 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3017 Label Lvector, Ldone, Lloop;
3018 MacroAssembler _masm(&cbuf);
3020 Register ary1_reg = reg_to_register_object($ary1$$reg);
3021 Register ary2_reg = reg_to_register_object($ary2$$reg);
3022 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3023 Register tmp2_reg = O7;
3024 Register result_reg = reg_to_register_object($result$$reg);
3026 int length_offset = arrayOopDesc::length_offset_in_bytes();
3027 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3029 // return true if the same array
3030 __ cmp(ary1_reg, ary2_reg);
3031 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3032 __ delayed()->add(G0, 1, result_reg); // equal
3034 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3035 __ delayed()->mov(G0, result_reg); // not equal
3037 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3038 __ delayed()->mov(G0, result_reg); // not equal
3040 //load the lengths of arrays
3041 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3042 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3044 // return false if the two arrays are not equal length
3045 __ cmp(tmp1_reg, tmp2_reg);
3046 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3047 __ delayed()->mov(G0, result_reg); // not equal
3049 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone);
3050 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3052 // load array addresses
3053 __ add(ary1_reg, base_offset, ary1_reg);
3054 __ add(ary2_reg, base_offset, ary2_reg);
3056 // renaming registers
3057 Register chr1_reg = result_reg; // for characters in ary1
3058 Register chr2_reg = tmp2_reg; // for characters in ary2
3059 Register limit_reg = tmp1_reg; // length
3061 // set byte count
3062 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3064 // Compare char[] arrays aligned to 4 bytes.
3065 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3066 chr1_reg, chr2_reg, Ldone);
3067 __ add(G0, 1, result_reg); // equals
3069 __ bind(Ldone);
3070 %}
3072 enc_class enc_rethrow() %{
3073 cbuf.set_insts_mark();
3074 Register temp_reg = G3;
3075 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3076 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3077 MacroAssembler _masm(&cbuf);
3078 #ifdef ASSERT
3079 __ save_frame(0);
3080 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3081 __ sethi(last_rethrow_addrlit, L1);
3082 Address addr(L1, last_rethrow_addrlit.low10());
3083 __ get_pc(L2);
3084 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3085 __ st_ptr(L2, addr);
3086 __ restore();
3087 #endif
3088 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3089 __ delayed()->nop();
3090 %}
3092 enc_class emit_mem_nop() %{
3093 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3094 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3095 %}
3097 enc_class emit_fadd_nop() %{
3098 // Generates the instruction FMOVS f31,f31
3099 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3100 %}
3102 enc_class emit_br_nop() %{
3103 // Generates the instruction BPN,PN .
3104 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3105 %}
3107 enc_class enc_membar_acquire %{
3108 MacroAssembler _masm(&cbuf);
3109 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3110 %}
3112 enc_class enc_membar_release %{
3113 MacroAssembler _masm(&cbuf);
3114 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3115 %}
3117 enc_class enc_membar_volatile %{
3118 MacroAssembler _masm(&cbuf);
3119 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3120 %}
3122 enc_class enc_repl8b( iRegI src, iRegL dst ) %{
3123 MacroAssembler _masm(&cbuf);
3124 Register src_reg = reg_to_register_object($src$$reg);
3125 Register dst_reg = reg_to_register_object($dst$$reg);
3126 __ sllx(src_reg, 56, dst_reg);
3127 __ srlx(dst_reg, 8, O7);
3128 __ or3 (dst_reg, O7, dst_reg);
3129 __ srlx(dst_reg, 16, O7);
3130 __ or3 (dst_reg, O7, dst_reg);
3131 __ srlx(dst_reg, 32, O7);
3132 __ or3 (dst_reg, O7, dst_reg);
3133 %}
3135 enc_class enc_repl4b( iRegI src, iRegL dst ) %{
3136 MacroAssembler _masm(&cbuf);
3137 Register src_reg = reg_to_register_object($src$$reg);
3138 Register dst_reg = reg_to_register_object($dst$$reg);
3139 __ sll(src_reg, 24, dst_reg);
3140 __ srl(dst_reg, 8, O7);
3141 __ or3(dst_reg, O7, dst_reg);
3142 __ srl(dst_reg, 16, O7);
3143 __ or3(dst_reg, O7, dst_reg);
3144 %}
3146 enc_class enc_repl4s( iRegI src, iRegL dst ) %{
3147 MacroAssembler _masm(&cbuf);
3148 Register src_reg = reg_to_register_object($src$$reg);
3149 Register dst_reg = reg_to_register_object($dst$$reg);
3150 __ sllx(src_reg, 48, dst_reg);
3151 __ srlx(dst_reg, 16, O7);
3152 __ or3 (dst_reg, O7, dst_reg);
3153 __ srlx(dst_reg, 32, O7);
3154 __ or3 (dst_reg, O7, dst_reg);
3155 %}
3157 enc_class enc_repl2i( iRegI src, iRegL dst ) %{
3158 MacroAssembler _masm(&cbuf);
3159 Register src_reg = reg_to_register_object($src$$reg);
3160 Register dst_reg = reg_to_register_object($dst$$reg);
3161 __ sllx(src_reg, 32, dst_reg);
3162 __ srlx(dst_reg, 32, O7);
3163 __ or3 (dst_reg, O7, dst_reg);
3164 %}
3166 %}
3168 //----------FRAME--------------------------------------------------------------
3169 // Definition of frame structure and management information.
3170 //
3171 // S T A C K L A Y O U T Allocators stack-slot number
3172 // | (to get allocators register number
3173 // G Owned by | | v add VMRegImpl::stack0)
3174 // r CALLER | |
3175 // o | +--------+ pad to even-align allocators stack-slot
3176 // w V | pad0 | numbers; owned by CALLER
3177 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3178 // h ^ | in | 5
3179 // | | args | 4 Holes in incoming args owned by SELF
3180 // | | | | 3
3181 // | | +--------+
3182 // V | | old out| Empty on Intel, window on Sparc
3183 // | old |preserve| Must be even aligned.
3184 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3185 // | | in | 3 area for Intel ret address
3186 // Owned by |preserve| Empty on Sparc.
3187 // SELF +--------+
3188 // | | pad2 | 2 pad to align old SP
3189 // | +--------+ 1
3190 // | | locks | 0
3191 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3192 // | | pad1 | 11 pad to align new SP
3193 // | +--------+
3194 // | | | 10
3195 // | | spills | 9 spills
3196 // V | | 8 (pad0 slot for callee)
3197 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3198 // ^ | out | 7
3199 // | | args | 6 Holes in outgoing args owned by CALLEE
3200 // Owned by +--------+
3201 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3202 // | new |preserve| Must be even-aligned.
3203 // | SP-+--------+----> Matcher::_new_SP, even aligned
3204 // | | |
3205 //
3206 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3207 // known from SELF's arguments and the Java calling convention.
3208 // Region 6-7 is determined per call site.
3209 // Note 2: If the calling convention leaves holes in the incoming argument
3210 // area, those holes are owned by SELF. Holes in the outgoing area
3211 // are owned by the CALLEE. Holes should not be nessecary in the
3212 // incoming area, as the Java calling convention is completely under
3213 // the control of the AD file. Doubles can be sorted and packed to
3214 // avoid holes. Holes in the outgoing arguments may be nessecary for
3215 // varargs C calling conventions.
3216 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3217 // even aligned with pad0 as needed.
3218 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3219 // region 6-11 is even aligned; it may be padded out more so that
3220 // the region from SP to FP meets the minimum stack alignment.
3222 frame %{
3223 // What direction does stack grow in (assumed to be same for native & Java)
3224 stack_direction(TOWARDS_LOW);
3226 // These two registers define part of the calling convention
3227 // between compiled code and the interpreter.
3228 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3229 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3231 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3232 cisc_spilling_operand_name(indOffset);
3234 // Number of stack slots consumed by a Monitor enter
3235 #ifdef _LP64
3236 sync_stack_slots(2);
3237 #else
3238 sync_stack_slots(1);
3239 #endif
3241 // Compiled code's Frame Pointer
3242 frame_pointer(R_SP);
3244 // Stack alignment requirement
3245 stack_alignment(StackAlignmentInBytes);
3246 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3247 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3249 // Number of stack slots between incoming argument block and the start of
3250 // a new frame. The PROLOG must add this many slots to the stack. The
3251 // EPILOG must remove this many slots.
3252 in_preserve_stack_slots(0);
3254 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3255 // for calls to C. Supports the var-args backing area for register parms.
3256 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3257 #ifdef _LP64
3258 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3259 varargs_C_out_slots_killed(12);
3260 #else
3261 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3262 varargs_C_out_slots_killed( 7);
3263 #endif
3265 // The after-PROLOG location of the return address. Location of
3266 // return address specifies a type (REG or STACK) and a number
3267 // representing the register number (i.e. - use a register name) or
3268 // stack slot.
3269 return_addr(REG R_I7); // Ret Addr is in register I7
3271 // Body of function which returns an OptoRegs array locating
3272 // arguments either in registers or in stack slots for calling
3273 // java
3274 calling_convention %{
3275 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3277 %}
3279 // Body of function which returns an OptoRegs array locating
3280 // arguments either in registers or in stack slots for callin
3281 // C.
3282 c_calling_convention %{
3283 // This is obviously always outgoing
3284 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3285 %}
3287 // Location of native (C/C++) and interpreter return values. This is specified to
3288 // be the same as Java. In the 32-bit VM, long values are actually returned from
3289 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3290 // to and from the register pairs is done by the appropriate call and epilog
3291 // opcodes. This simplifies the register allocator.
3292 c_return_value %{
3293 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3294 #ifdef _LP64
3295 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3296 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3297 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3298 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3299 #else // !_LP64
3300 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3301 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3302 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3303 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3304 #endif
3305 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3306 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3307 %}
3309 // Location of compiled Java return values. Same as C
3310 return_value %{
3311 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3312 #ifdef _LP64
3313 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3314 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3315 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3316 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3317 #else // !_LP64
3318 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3319 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3320 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3321 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3322 #endif
3323 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3324 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3325 %}
3327 %}
3330 //----------ATTRIBUTES---------------------------------------------------------
3331 //----------Operand Attributes-------------------------------------------------
3332 op_attrib op_cost(1); // Required cost attribute
3334 //----------Instruction Attributes---------------------------------------------
3335 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3336 ins_attrib ins_size(32); // Required size attribute (in bits)
3337 ins_attrib ins_pc_relative(0); // Required PC Relative flag
3338 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3339 // non-matching short branch variant of some
3340 // long branch?
3342 //----------OPERANDS-----------------------------------------------------------
3343 // Operand definitions must precede instruction definitions for correct parsing
3344 // in the ADLC because operands constitute user defined types which are used in
3345 // instruction definitions.
3347 //----------Simple Operands----------------------------------------------------
3348 // Immediate Operands
3349 // Integer Immediate: 32-bit
3350 operand immI() %{
3351 match(ConI);
3353 op_cost(0);
3354 // formats are generated automatically for constants and base registers
3355 format %{ %}
3356 interface(CONST_INTER);
3357 %}
3359 // Integer Immediate: 8-bit
3360 operand immI8() %{
3361 predicate(Assembler::is_simm(n->get_int(), 8));
3362 match(ConI);
3363 op_cost(0);
3364 format %{ %}
3365 interface(CONST_INTER);
3366 %}
3368 // Integer Immediate: 13-bit
3369 operand immI13() %{
3370 predicate(Assembler::is_simm13(n->get_int()));
3371 match(ConI);
3372 op_cost(0);
3374 format %{ %}
3375 interface(CONST_INTER);
3376 %}
3378 // Integer Immediate: 13-bit minus 7
3379 operand immI13m7() %{
3380 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3381 match(ConI);
3382 op_cost(0);
3384 format %{ %}
3385 interface(CONST_INTER);
3386 %}
3388 // Integer Immediate: 16-bit
3389 operand immI16() %{
3390 predicate(Assembler::is_simm(n->get_int(), 16));
3391 match(ConI);
3392 op_cost(0);
3393 format %{ %}
3394 interface(CONST_INTER);
3395 %}
3397 // Unsigned (positive) Integer Immediate: 13-bit
3398 operand immU13() %{
3399 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3400 match(ConI);
3401 op_cost(0);
3403 format %{ %}
3404 interface(CONST_INTER);
3405 %}
3407 // Integer Immediate: 6-bit
3408 operand immU6() %{
3409 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3410 match(ConI);
3411 op_cost(0);
3412 format %{ %}
3413 interface(CONST_INTER);
3414 %}
3416 // Integer Immediate: 11-bit
3417 operand immI11() %{
3418 predicate(Assembler::is_simm(n->get_int(),11));
3419 match(ConI);
3420 op_cost(0);
3421 format %{ %}
3422 interface(CONST_INTER);
3423 %}
3425 // Integer Immediate: 0-bit
3426 operand immI0() %{
3427 predicate(n->get_int() == 0);
3428 match(ConI);
3429 op_cost(0);
3431 format %{ %}
3432 interface(CONST_INTER);
3433 %}
3435 // Integer Immediate: the value 10
3436 operand immI10() %{
3437 predicate(n->get_int() == 10);
3438 match(ConI);
3439 op_cost(0);
3441 format %{ %}
3442 interface(CONST_INTER);
3443 %}
3445 // Integer Immediate: the values 0-31
3446 operand immU5() %{
3447 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3448 match(ConI);
3449 op_cost(0);
3451 format %{ %}
3452 interface(CONST_INTER);
3453 %}
3455 // Integer Immediate: the values 1-31
3456 operand immI_1_31() %{
3457 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3458 match(ConI);
3459 op_cost(0);
3461 format %{ %}
3462 interface(CONST_INTER);
3463 %}
3465 // Integer Immediate: the values 32-63
3466 operand immI_32_63() %{
3467 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3468 match(ConI);
3469 op_cost(0);
3471 format %{ %}
3472 interface(CONST_INTER);
3473 %}
3475 // Immediates for special shifts (sign extend)
3477 // Integer Immediate: the value 16
3478 operand immI_16() %{
3479 predicate(n->get_int() == 16);
3480 match(ConI);
3481 op_cost(0);
3483 format %{ %}
3484 interface(CONST_INTER);
3485 %}
3487 // Integer Immediate: the value 24
3488 operand immI_24() %{
3489 predicate(n->get_int() == 24);
3490 match(ConI);
3491 op_cost(0);
3493 format %{ %}
3494 interface(CONST_INTER);
3495 %}
3497 // Integer Immediate: the value 255
3498 operand immI_255() %{
3499 predicate( n->get_int() == 255 );
3500 match(ConI);
3501 op_cost(0);
3503 format %{ %}
3504 interface(CONST_INTER);
3505 %}
3507 // Integer Immediate: the value 65535
3508 operand immI_65535() %{
3509 predicate(n->get_int() == 65535);
3510 match(ConI);
3511 op_cost(0);
3513 format %{ %}
3514 interface(CONST_INTER);
3515 %}
3517 // Long Immediate: the value FF
3518 operand immL_FF() %{
3519 predicate( n->get_long() == 0xFFL );
3520 match(ConL);
3521 op_cost(0);
3523 format %{ %}
3524 interface(CONST_INTER);
3525 %}
3527 // Long Immediate: the value FFFF
3528 operand immL_FFFF() %{
3529 predicate( n->get_long() == 0xFFFFL );
3530 match(ConL);
3531 op_cost(0);
3533 format %{ %}
3534 interface(CONST_INTER);
3535 %}
3537 // Pointer Immediate: 32 or 64-bit
3538 operand immP() %{
3539 match(ConP);
3541 op_cost(5);
3542 // formats are generated automatically for constants and base registers
3543 format %{ %}
3544 interface(CONST_INTER);
3545 %}
3547 #ifdef _LP64
3548 // Pointer Immediate: 64-bit
3549 operand immP_set() %{
3550 predicate(!VM_Version::is_niagara_plus());
3551 match(ConP);
3553 op_cost(5);
3554 // formats are generated automatically for constants and base registers
3555 format %{ %}
3556 interface(CONST_INTER);
3557 %}
3559 // Pointer Immediate: 64-bit
3560 // From Niagara2 processors on a load should be better than materializing.
3561 operand immP_load() %{
3562 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3563 match(ConP);
3565 op_cost(5);
3566 // formats are generated automatically for constants and base registers
3567 format %{ %}
3568 interface(CONST_INTER);
3569 %}
3571 // Pointer Immediate: 64-bit
3572 operand immP_no_oop_cheap() %{
3573 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3574 match(ConP);
3576 op_cost(5);
3577 // formats are generated automatically for constants and base registers
3578 format %{ %}
3579 interface(CONST_INTER);
3580 %}
3581 #endif
3583 operand immP13() %{
3584 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3585 match(ConP);
3586 op_cost(0);
3588 format %{ %}
3589 interface(CONST_INTER);
3590 %}
3592 operand immP0() %{
3593 predicate(n->get_ptr() == 0);
3594 match(ConP);
3595 op_cost(0);
3597 format %{ %}
3598 interface(CONST_INTER);
3599 %}
3601 operand immP_poll() %{
3602 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3603 match(ConP);
3605 // formats are generated automatically for constants and base registers
3606 format %{ %}
3607 interface(CONST_INTER);
3608 %}
3610 // Pointer Immediate
3611 operand immN()
3612 %{
3613 match(ConN);
3615 op_cost(10);
3616 format %{ %}
3617 interface(CONST_INTER);
3618 %}
3620 // NULL Pointer Immediate
3621 operand immN0()
3622 %{
3623 predicate(n->get_narrowcon() == 0);
3624 match(ConN);
3626 op_cost(0);
3627 format %{ %}
3628 interface(CONST_INTER);
3629 %}
3631 operand immL() %{
3632 match(ConL);
3633 op_cost(40);
3634 // formats are generated automatically for constants and base registers
3635 format %{ %}
3636 interface(CONST_INTER);
3637 %}
3639 operand immL0() %{
3640 predicate(n->get_long() == 0L);
3641 match(ConL);
3642 op_cost(0);
3643 // formats are generated automatically for constants and base registers
3644 format %{ %}
3645 interface(CONST_INTER);
3646 %}
3648 // Long Immediate: 13-bit
3649 operand immL13() %{
3650 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3651 match(ConL);
3652 op_cost(0);
3654 format %{ %}
3655 interface(CONST_INTER);
3656 %}
3658 // Long Immediate: 13-bit minus 7
3659 operand immL13m7() %{
3660 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3661 match(ConL);
3662 op_cost(0);
3664 format %{ %}
3665 interface(CONST_INTER);
3666 %}
3668 // Long Immediate: low 32-bit mask
3669 operand immL_32bits() %{
3670 predicate(n->get_long() == 0xFFFFFFFFL);
3671 match(ConL);
3672 op_cost(0);
3674 format %{ %}
3675 interface(CONST_INTER);
3676 %}
3678 // Long Immediate: cheap (materialize in <= 3 instructions)
3679 operand immL_cheap() %{
3680 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3681 match(ConL);
3682 op_cost(0);
3684 format %{ %}
3685 interface(CONST_INTER);
3686 %}
3688 // Long Immediate: expensive (materialize in > 3 instructions)
3689 operand immL_expensive() %{
3690 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3691 match(ConL);
3692 op_cost(0);
3694 format %{ %}
3695 interface(CONST_INTER);
3696 %}
3698 // Double Immediate
3699 operand immD() %{
3700 match(ConD);
3702 op_cost(40);
3703 format %{ %}
3704 interface(CONST_INTER);
3705 %}
3707 operand immD0() %{
3708 #ifdef _LP64
3709 // on 64-bit architectures this comparision is faster
3710 predicate(jlong_cast(n->getd()) == 0);
3711 #else
3712 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3713 #endif
3714 match(ConD);
3716 op_cost(0);
3717 format %{ %}
3718 interface(CONST_INTER);
3719 %}
3721 // Float Immediate
3722 operand immF() %{
3723 match(ConF);
3725 op_cost(20);
3726 format %{ %}
3727 interface(CONST_INTER);
3728 %}
3730 // Float Immediate: 0
3731 operand immF0() %{
3732 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3733 match(ConF);
3735 op_cost(0);
3736 format %{ %}
3737 interface(CONST_INTER);
3738 %}
3740 // Integer Register Operands
3741 // Integer Register
3742 operand iRegI() %{
3743 constraint(ALLOC_IN_RC(int_reg));
3744 match(RegI);
3746 match(notemp_iRegI);
3747 match(g1RegI);
3748 match(o0RegI);
3749 match(iRegIsafe);
3751 format %{ %}
3752 interface(REG_INTER);
3753 %}
3755 operand notemp_iRegI() %{
3756 constraint(ALLOC_IN_RC(notemp_int_reg));
3757 match(RegI);
3759 match(o0RegI);
3761 format %{ %}
3762 interface(REG_INTER);
3763 %}
3765 operand o0RegI() %{
3766 constraint(ALLOC_IN_RC(o0_regI));
3767 match(iRegI);
3769 format %{ %}
3770 interface(REG_INTER);
3771 %}
3773 // Pointer Register
3774 operand iRegP() %{
3775 constraint(ALLOC_IN_RC(ptr_reg));
3776 match(RegP);
3778 match(lock_ptr_RegP);
3779 match(g1RegP);
3780 match(g2RegP);
3781 match(g3RegP);
3782 match(g4RegP);
3783 match(i0RegP);
3784 match(o0RegP);
3785 match(o1RegP);
3786 match(l7RegP);
3788 format %{ %}
3789 interface(REG_INTER);
3790 %}
3792 operand sp_ptr_RegP() %{
3793 constraint(ALLOC_IN_RC(sp_ptr_reg));
3794 match(RegP);
3795 match(iRegP);
3797 format %{ %}
3798 interface(REG_INTER);
3799 %}
3801 operand lock_ptr_RegP() %{
3802 constraint(ALLOC_IN_RC(lock_ptr_reg));
3803 match(RegP);
3804 match(i0RegP);
3805 match(o0RegP);
3806 match(o1RegP);
3807 match(l7RegP);
3809 format %{ %}
3810 interface(REG_INTER);
3811 %}
3813 operand g1RegP() %{
3814 constraint(ALLOC_IN_RC(g1_regP));
3815 match(iRegP);
3817 format %{ %}
3818 interface(REG_INTER);
3819 %}
3821 operand g2RegP() %{
3822 constraint(ALLOC_IN_RC(g2_regP));
3823 match(iRegP);
3825 format %{ %}
3826 interface(REG_INTER);
3827 %}
3829 operand g3RegP() %{
3830 constraint(ALLOC_IN_RC(g3_regP));
3831 match(iRegP);
3833 format %{ %}
3834 interface(REG_INTER);
3835 %}
3837 operand g1RegI() %{
3838 constraint(ALLOC_IN_RC(g1_regI));
3839 match(iRegI);
3841 format %{ %}
3842 interface(REG_INTER);
3843 %}
3845 operand g3RegI() %{
3846 constraint(ALLOC_IN_RC(g3_regI));
3847 match(iRegI);
3849 format %{ %}
3850 interface(REG_INTER);
3851 %}
3853 operand g4RegI() %{
3854 constraint(ALLOC_IN_RC(g4_regI));
3855 match(iRegI);
3857 format %{ %}
3858 interface(REG_INTER);
3859 %}
3861 operand g4RegP() %{
3862 constraint(ALLOC_IN_RC(g4_regP));
3863 match(iRegP);
3865 format %{ %}
3866 interface(REG_INTER);
3867 %}
3869 operand i0RegP() %{
3870 constraint(ALLOC_IN_RC(i0_regP));
3871 match(iRegP);
3873 format %{ %}
3874 interface(REG_INTER);
3875 %}
3877 operand o0RegP() %{
3878 constraint(ALLOC_IN_RC(o0_regP));
3879 match(iRegP);
3881 format %{ %}
3882 interface(REG_INTER);
3883 %}
3885 operand o1RegP() %{
3886 constraint(ALLOC_IN_RC(o1_regP));
3887 match(iRegP);
3889 format %{ %}
3890 interface(REG_INTER);
3891 %}
3893 operand o2RegP() %{
3894 constraint(ALLOC_IN_RC(o2_regP));
3895 match(iRegP);
3897 format %{ %}
3898 interface(REG_INTER);
3899 %}
3901 operand o7RegP() %{
3902 constraint(ALLOC_IN_RC(o7_regP));
3903 match(iRegP);
3905 format %{ %}
3906 interface(REG_INTER);
3907 %}
3909 operand l7RegP() %{
3910 constraint(ALLOC_IN_RC(l7_regP));
3911 match(iRegP);
3913 format %{ %}
3914 interface(REG_INTER);
3915 %}
3917 operand o7RegI() %{
3918 constraint(ALLOC_IN_RC(o7_regI));
3919 match(iRegI);
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3925 operand iRegN() %{
3926 constraint(ALLOC_IN_RC(int_reg));
3927 match(RegN);
3929 format %{ %}
3930 interface(REG_INTER);
3931 %}
3933 // Long Register
3934 operand iRegL() %{
3935 constraint(ALLOC_IN_RC(long_reg));
3936 match(RegL);
3938 format %{ %}
3939 interface(REG_INTER);
3940 %}
3942 operand o2RegL() %{
3943 constraint(ALLOC_IN_RC(o2_regL));
3944 match(iRegL);
3946 format %{ %}
3947 interface(REG_INTER);
3948 %}
3950 operand o7RegL() %{
3951 constraint(ALLOC_IN_RC(o7_regL));
3952 match(iRegL);
3954 format %{ %}
3955 interface(REG_INTER);
3956 %}
3958 operand g1RegL() %{
3959 constraint(ALLOC_IN_RC(g1_regL));
3960 match(iRegL);
3962 format %{ %}
3963 interface(REG_INTER);
3964 %}
3966 operand g3RegL() %{
3967 constraint(ALLOC_IN_RC(g3_regL));
3968 match(iRegL);
3970 format %{ %}
3971 interface(REG_INTER);
3972 %}
3974 // Int Register safe
3975 // This is 64bit safe
3976 operand iRegIsafe() %{
3977 constraint(ALLOC_IN_RC(long_reg));
3979 match(iRegI);
3981 format %{ %}
3982 interface(REG_INTER);
3983 %}
3985 // Condition Code Flag Register
3986 operand flagsReg() %{
3987 constraint(ALLOC_IN_RC(int_flags));
3988 match(RegFlags);
3990 format %{ "ccr" %} // both ICC and XCC
3991 interface(REG_INTER);
3992 %}
3994 // Condition Code Register, unsigned comparisons.
3995 operand flagsRegU() %{
3996 constraint(ALLOC_IN_RC(int_flags));
3997 match(RegFlags);
3999 format %{ "icc_U" %}
4000 interface(REG_INTER);
4001 %}
4003 // Condition Code Register, pointer comparisons.
4004 operand flagsRegP() %{
4005 constraint(ALLOC_IN_RC(int_flags));
4006 match(RegFlags);
4008 #ifdef _LP64
4009 format %{ "xcc_P" %}
4010 #else
4011 format %{ "icc_P" %}
4012 #endif
4013 interface(REG_INTER);
4014 %}
4016 // Condition Code Register, long comparisons.
4017 operand flagsRegL() %{
4018 constraint(ALLOC_IN_RC(int_flags));
4019 match(RegFlags);
4021 format %{ "xcc_L" %}
4022 interface(REG_INTER);
4023 %}
4025 // Condition Code Register, floating comparisons, unordered same as "less".
4026 operand flagsRegF() %{
4027 constraint(ALLOC_IN_RC(float_flags));
4028 match(RegFlags);
4029 match(flagsRegF0);
4031 format %{ %}
4032 interface(REG_INTER);
4033 %}
4035 operand flagsRegF0() %{
4036 constraint(ALLOC_IN_RC(float_flag0));
4037 match(RegFlags);
4039 format %{ %}
4040 interface(REG_INTER);
4041 %}
4044 // Condition Code Flag Register used by long compare
4045 operand flagsReg_long_LTGE() %{
4046 constraint(ALLOC_IN_RC(int_flags));
4047 match(RegFlags);
4048 format %{ "icc_LTGE" %}
4049 interface(REG_INTER);
4050 %}
4051 operand flagsReg_long_EQNE() %{
4052 constraint(ALLOC_IN_RC(int_flags));
4053 match(RegFlags);
4054 format %{ "icc_EQNE" %}
4055 interface(REG_INTER);
4056 %}
4057 operand flagsReg_long_LEGT() %{
4058 constraint(ALLOC_IN_RC(int_flags));
4059 match(RegFlags);
4060 format %{ "icc_LEGT" %}
4061 interface(REG_INTER);
4062 %}
4065 operand regD() %{
4066 constraint(ALLOC_IN_RC(dflt_reg));
4067 match(RegD);
4069 match(regD_low);
4071 format %{ %}
4072 interface(REG_INTER);
4073 %}
4075 operand regF() %{
4076 constraint(ALLOC_IN_RC(sflt_reg));
4077 match(RegF);
4079 format %{ %}
4080 interface(REG_INTER);
4081 %}
4083 operand regD_low() %{
4084 constraint(ALLOC_IN_RC(dflt_low_reg));
4085 match(regD);
4087 format %{ %}
4088 interface(REG_INTER);
4089 %}
4091 // Special Registers
4093 // Method Register
4094 operand inline_cache_regP(iRegP reg) %{
4095 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4096 match(reg);
4097 format %{ %}
4098 interface(REG_INTER);
4099 %}
4101 operand interpreter_method_oop_regP(iRegP reg) %{
4102 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4103 match(reg);
4104 format %{ %}
4105 interface(REG_INTER);
4106 %}
4109 //----------Complex Operands---------------------------------------------------
4110 // Indirect Memory Reference
4111 operand indirect(sp_ptr_RegP reg) %{
4112 constraint(ALLOC_IN_RC(sp_ptr_reg));
4113 match(reg);
4115 op_cost(100);
4116 format %{ "[$reg]" %}
4117 interface(MEMORY_INTER) %{
4118 base($reg);
4119 index(0x0);
4120 scale(0x0);
4121 disp(0x0);
4122 %}
4123 %}
4125 // Indirect with simm13 Offset
4126 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4127 constraint(ALLOC_IN_RC(sp_ptr_reg));
4128 match(AddP reg offset);
4130 op_cost(100);
4131 format %{ "[$reg + $offset]" %}
4132 interface(MEMORY_INTER) %{
4133 base($reg);
4134 index(0x0);
4135 scale(0x0);
4136 disp($offset);
4137 %}
4138 %}
4140 // Indirect with simm13 Offset minus 7
4141 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4142 constraint(ALLOC_IN_RC(sp_ptr_reg));
4143 match(AddP reg offset);
4145 op_cost(100);
4146 format %{ "[$reg + $offset]" %}
4147 interface(MEMORY_INTER) %{
4148 base($reg);
4149 index(0x0);
4150 scale(0x0);
4151 disp($offset);
4152 %}
4153 %}
4155 // Note: Intel has a swapped version also, like this:
4156 //operand indOffsetX(iRegI reg, immP offset) %{
4157 // constraint(ALLOC_IN_RC(int_reg));
4158 // match(AddP offset reg);
4159 //
4160 // op_cost(100);
4161 // format %{ "[$reg + $offset]" %}
4162 // interface(MEMORY_INTER) %{
4163 // base($reg);
4164 // index(0x0);
4165 // scale(0x0);
4166 // disp($offset);
4167 // %}
4168 //%}
4169 //// However, it doesn't make sense for SPARC, since
4170 // we have no particularly good way to embed oops in
4171 // single instructions.
4173 // Indirect with Register Index
4174 operand indIndex(iRegP addr, iRegX index) %{
4175 constraint(ALLOC_IN_RC(ptr_reg));
4176 match(AddP addr index);
4178 op_cost(100);
4179 format %{ "[$addr + $index]" %}
4180 interface(MEMORY_INTER) %{
4181 base($addr);
4182 index($index);
4183 scale(0x0);
4184 disp(0x0);
4185 %}
4186 %}
4188 //----------Special Memory Operands--------------------------------------------
4189 // Stack Slot Operand - This operand is used for loading and storing temporary
4190 // values on the stack where a match requires a value to
4191 // flow through memory.
4192 operand stackSlotI(sRegI reg) %{
4193 constraint(ALLOC_IN_RC(stack_slots));
4194 op_cost(100);
4195 //match(RegI);
4196 format %{ "[$reg]" %}
4197 interface(MEMORY_INTER) %{
4198 base(0xE); // R_SP
4199 index(0x0);
4200 scale(0x0);
4201 disp($reg); // Stack Offset
4202 %}
4203 %}
4205 operand stackSlotP(sRegP reg) %{
4206 constraint(ALLOC_IN_RC(stack_slots));
4207 op_cost(100);
4208 //match(RegP);
4209 format %{ "[$reg]" %}
4210 interface(MEMORY_INTER) %{
4211 base(0xE); // R_SP
4212 index(0x0);
4213 scale(0x0);
4214 disp($reg); // Stack Offset
4215 %}
4216 %}
4218 operand stackSlotF(sRegF reg) %{
4219 constraint(ALLOC_IN_RC(stack_slots));
4220 op_cost(100);
4221 //match(RegF);
4222 format %{ "[$reg]" %}
4223 interface(MEMORY_INTER) %{
4224 base(0xE); // R_SP
4225 index(0x0);
4226 scale(0x0);
4227 disp($reg); // Stack Offset
4228 %}
4229 %}
4230 operand stackSlotD(sRegD reg) %{
4231 constraint(ALLOC_IN_RC(stack_slots));
4232 op_cost(100);
4233 //match(RegD);
4234 format %{ "[$reg]" %}
4235 interface(MEMORY_INTER) %{
4236 base(0xE); // R_SP
4237 index(0x0);
4238 scale(0x0);
4239 disp($reg); // Stack Offset
4240 %}
4241 %}
4242 operand stackSlotL(sRegL reg) %{
4243 constraint(ALLOC_IN_RC(stack_slots));
4244 op_cost(100);
4245 //match(RegL);
4246 format %{ "[$reg]" %}
4247 interface(MEMORY_INTER) %{
4248 base(0xE); // R_SP
4249 index(0x0);
4250 scale(0x0);
4251 disp($reg); // Stack Offset
4252 %}
4253 %}
4255 // Operands for expressing Control Flow
4256 // NOTE: Label is a predefined operand which should not be redefined in
4257 // the AD file. It is generically handled within the ADLC.
4259 //----------Conditional Branch Operands----------------------------------------
4260 // Comparison Op - This is the operation of the comparison, and is limited to
4261 // the following set of codes:
4262 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4263 //
4264 // Other attributes of the comparison, such as unsignedness, are specified
4265 // by the comparison instruction that sets a condition code flags register.
4266 // That result is represented by a flags operand whose subtype is appropriate
4267 // to the unsignedness (etc.) of the comparison.
4268 //
4269 // Later, the instruction which matches both the Comparison Op (a Bool) and
4270 // the flags (produced by the Cmp) specifies the coding of the comparison op
4271 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4273 operand cmpOp() %{
4274 match(Bool);
4276 format %{ "" %}
4277 interface(COND_INTER) %{
4278 equal(0x1);
4279 not_equal(0x9);
4280 less(0x3);
4281 greater_equal(0xB);
4282 less_equal(0x2);
4283 greater(0xA);
4284 %}
4285 %}
4287 // Comparison Op, unsigned
4288 operand cmpOpU() %{
4289 match(Bool);
4291 format %{ "u" %}
4292 interface(COND_INTER) %{
4293 equal(0x1);
4294 not_equal(0x9);
4295 less(0x5);
4296 greater_equal(0xD);
4297 less_equal(0x4);
4298 greater(0xC);
4299 %}
4300 %}
4302 // Comparison Op, pointer (same as unsigned)
4303 operand cmpOpP() %{
4304 match(Bool);
4306 format %{ "p" %}
4307 interface(COND_INTER) %{
4308 equal(0x1);
4309 not_equal(0x9);
4310 less(0x5);
4311 greater_equal(0xD);
4312 less_equal(0x4);
4313 greater(0xC);
4314 %}
4315 %}
4317 // Comparison Op, branch-register encoding
4318 operand cmpOp_reg() %{
4319 match(Bool);
4321 format %{ "" %}
4322 interface(COND_INTER) %{
4323 equal (0x1);
4324 not_equal (0x5);
4325 less (0x3);
4326 greater_equal(0x7);
4327 less_equal (0x2);
4328 greater (0x6);
4329 %}
4330 %}
4332 // Comparison Code, floating, unordered same as less
4333 operand cmpOpF() %{
4334 match(Bool);
4336 format %{ "fl" %}
4337 interface(COND_INTER) %{
4338 equal(0x9);
4339 not_equal(0x1);
4340 less(0x3);
4341 greater_equal(0xB);
4342 less_equal(0xE);
4343 greater(0x6);
4344 %}
4345 %}
4347 // Used by long compare
4348 operand cmpOp_commute() %{
4349 match(Bool);
4351 format %{ "" %}
4352 interface(COND_INTER) %{
4353 equal(0x1);
4354 not_equal(0x9);
4355 less(0xA);
4356 greater_equal(0x2);
4357 less_equal(0xB);
4358 greater(0x3);
4359 %}
4360 %}
4362 //----------OPERAND CLASSES----------------------------------------------------
4363 // Operand Classes are groups of operands that are used to simplify
4364 // instruction definitions by not requiring the AD writer to specify separate
4365 // instructions for every form of operand when the instruction accepts
4366 // multiple operand types with the same basic encoding and format. The classic
4367 // case of this is memory operands.
4368 opclass memory( indirect, indOffset13, indIndex );
4369 opclass indIndexMemory( indIndex );
4371 //----------PIPELINE-----------------------------------------------------------
4372 pipeline %{
4374 //----------ATTRIBUTES---------------------------------------------------------
4375 attributes %{
4376 fixed_size_instructions; // Fixed size instructions
4377 branch_has_delay_slot; // Branch has delay slot following
4378 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4379 instruction_unit_size = 4; // An instruction is 4 bytes long
4380 instruction_fetch_unit_size = 16; // The processor fetches one line
4381 instruction_fetch_units = 1; // of 16 bytes
4383 // List of nop instructions
4384 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4385 %}
4387 //----------RESOURCES----------------------------------------------------------
4388 // Resources are the functional units available to the machine
4389 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4391 //----------PIPELINE DESCRIPTION-----------------------------------------------
4392 // Pipeline Description specifies the stages in the machine's pipeline
4394 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4396 //----------PIPELINE CLASSES---------------------------------------------------
4397 // Pipeline Classes describe the stages in which input and output are
4398 // referenced by the hardware pipeline.
4400 // Integer ALU reg-reg operation
4401 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4402 single_instruction;
4403 dst : E(write);
4404 src1 : R(read);
4405 src2 : R(read);
4406 IALU : R;
4407 %}
4409 // Integer ALU reg-reg long operation
4410 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4411 instruction_count(2);
4412 dst : E(write);
4413 src1 : R(read);
4414 src2 : R(read);
4415 IALU : R;
4416 IALU : R;
4417 %}
4419 // Integer ALU reg-reg long dependent operation
4420 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4421 instruction_count(1); multiple_bundles;
4422 dst : E(write);
4423 src1 : R(read);
4424 src2 : R(read);
4425 cr : E(write);
4426 IALU : R(2);
4427 %}
4429 // Integer ALU reg-imm operaion
4430 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4431 single_instruction;
4432 dst : E(write);
4433 src1 : R(read);
4434 IALU : R;
4435 %}
4437 // Integer ALU reg-reg operation with condition code
4438 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4439 single_instruction;
4440 dst : E(write);
4441 cr : E(write);
4442 src1 : R(read);
4443 src2 : R(read);
4444 IALU : R;
4445 %}
4447 // Integer ALU reg-imm operation with condition code
4448 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4449 single_instruction;
4450 dst : E(write);
4451 cr : E(write);
4452 src1 : R(read);
4453 IALU : R;
4454 %}
4456 // Integer ALU zero-reg operation
4457 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4458 single_instruction;
4459 dst : E(write);
4460 src2 : R(read);
4461 IALU : R;
4462 %}
4464 // Integer ALU zero-reg operation with condition code only
4465 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4466 single_instruction;
4467 cr : E(write);
4468 src : R(read);
4469 IALU : R;
4470 %}
4472 // Integer ALU reg-reg operation with condition code only
4473 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4474 single_instruction;
4475 cr : E(write);
4476 src1 : R(read);
4477 src2 : R(read);
4478 IALU : R;
4479 %}
4481 // Integer ALU reg-imm operation with condition code only
4482 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4483 single_instruction;
4484 cr : E(write);
4485 src1 : R(read);
4486 IALU : R;
4487 %}
4489 // Integer ALU reg-reg-zero operation with condition code only
4490 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4491 single_instruction;
4492 cr : E(write);
4493 src1 : R(read);
4494 src2 : R(read);
4495 IALU : R;
4496 %}
4498 // Integer ALU reg-imm-zero operation with condition code only
4499 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4500 single_instruction;
4501 cr : E(write);
4502 src1 : R(read);
4503 IALU : R;
4504 %}
4506 // Integer ALU reg-reg operation with condition code, src1 modified
4507 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4508 single_instruction;
4509 cr : E(write);
4510 src1 : E(write);
4511 src1 : R(read);
4512 src2 : R(read);
4513 IALU : R;
4514 %}
4516 // Integer ALU reg-imm operation with condition code, src1 modified
4517 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4518 single_instruction;
4519 cr : E(write);
4520 src1 : E(write);
4521 src1 : R(read);
4522 IALU : R;
4523 %}
4525 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4526 multiple_bundles;
4527 dst : E(write)+4;
4528 cr : E(write);
4529 src1 : R(read);
4530 src2 : R(read);
4531 IALU : R(3);
4532 BR : R(2);
4533 %}
4535 // Integer ALU operation
4536 pipe_class ialu_none(iRegI dst) %{
4537 single_instruction;
4538 dst : E(write);
4539 IALU : R;
4540 %}
4542 // Integer ALU reg operation
4543 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4544 single_instruction; may_have_no_code;
4545 dst : E(write);
4546 src : R(read);
4547 IALU : R;
4548 %}
4550 // Integer ALU reg conditional operation
4551 // This instruction has a 1 cycle stall, and cannot execute
4552 // in the same cycle as the instruction setting the condition
4553 // code. We kludge this by pretending to read the condition code
4554 // 1 cycle earlier, and by marking the functional units as busy
4555 // for 2 cycles with the result available 1 cycle later than
4556 // is really the case.
4557 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4558 single_instruction;
4559 op2_out : C(write);
4560 op1 : R(read);
4561 cr : R(read); // This is really E, with a 1 cycle stall
4562 BR : R(2);
4563 MS : R(2);
4564 %}
4566 #ifdef _LP64
4567 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4568 instruction_count(1); multiple_bundles;
4569 dst : C(write)+1;
4570 src : R(read)+1;
4571 IALU : R(1);
4572 BR : E(2);
4573 MS : E(2);
4574 %}
4575 #endif
4577 // Integer ALU reg operation
4578 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4579 single_instruction; may_have_no_code;
4580 dst : E(write);
4581 src : R(read);
4582 IALU : R;
4583 %}
4584 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4585 single_instruction; may_have_no_code;
4586 dst : E(write);
4587 src : R(read);
4588 IALU : R;
4589 %}
4591 // Two integer ALU reg operations
4592 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4593 instruction_count(2);
4594 dst : E(write);
4595 src : R(read);
4596 A0 : R;
4597 A1 : R;
4598 %}
4600 // Two integer ALU reg operations
4601 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4602 instruction_count(2); may_have_no_code;
4603 dst : E(write);
4604 src : R(read);
4605 A0 : R;
4606 A1 : R;
4607 %}
4609 // Integer ALU imm operation
4610 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4611 single_instruction;
4612 dst : E(write);
4613 IALU : R;
4614 %}
4616 // Integer ALU reg-reg with carry operation
4617 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4618 single_instruction;
4619 dst : E(write);
4620 src1 : R(read);
4621 src2 : R(read);
4622 IALU : R;
4623 %}
4625 // Integer ALU cc operation
4626 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4627 single_instruction;
4628 dst : E(write);
4629 cc : R(read);
4630 IALU : R;
4631 %}
4633 // Integer ALU cc / second IALU operation
4634 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4635 instruction_count(1); multiple_bundles;
4636 dst : E(write)+1;
4637 src : R(read);
4638 IALU : R;
4639 %}
4641 // Integer ALU cc / second IALU operation
4642 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4643 instruction_count(1); multiple_bundles;
4644 dst : E(write)+1;
4645 p : R(read);
4646 q : R(read);
4647 IALU : R;
4648 %}
4650 // Integer ALU hi-lo-reg operation
4651 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4652 instruction_count(1); multiple_bundles;
4653 dst : E(write)+1;
4654 IALU : R(2);
4655 %}
4657 // Float ALU hi-lo-reg operation (with temp)
4658 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4659 instruction_count(1); multiple_bundles;
4660 dst : E(write)+1;
4661 IALU : R(2);
4662 %}
4664 // Long Constant
4665 pipe_class loadConL( iRegL dst, immL src ) %{
4666 instruction_count(2); multiple_bundles;
4667 dst : E(write)+1;
4668 IALU : R(2);
4669 IALU : R(2);
4670 %}
4672 // Pointer Constant
4673 pipe_class loadConP( iRegP dst, immP src ) %{
4674 instruction_count(0); multiple_bundles;
4675 fixed_latency(6);
4676 %}
4678 // Polling Address
4679 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4680 #ifdef _LP64
4681 instruction_count(0); multiple_bundles;
4682 fixed_latency(6);
4683 #else
4684 dst : E(write);
4685 IALU : R;
4686 #endif
4687 %}
4689 // Long Constant small
4690 pipe_class loadConLlo( iRegL dst, immL src ) %{
4691 instruction_count(2);
4692 dst : E(write);
4693 IALU : R;
4694 IALU : R;
4695 %}
4697 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4698 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4699 instruction_count(1); multiple_bundles;
4700 src : R(read);
4701 dst : M(write)+1;
4702 IALU : R;
4703 MS : E;
4704 %}
4706 // Integer ALU nop operation
4707 pipe_class ialu_nop() %{
4708 single_instruction;
4709 IALU : R;
4710 %}
4712 // Integer ALU nop operation
4713 pipe_class ialu_nop_A0() %{
4714 single_instruction;
4715 A0 : R;
4716 %}
4718 // Integer ALU nop operation
4719 pipe_class ialu_nop_A1() %{
4720 single_instruction;
4721 A1 : R;
4722 %}
4724 // Integer Multiply reg-reg operation
4725 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4726 single_instruction;
4727 dst : E(write);
4728 src1 : R(read);
4729 src2 : R(read);
4730 MS : R(5);
4731 %}
4733 // Integer Multiply reg-imm operation
4734 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4735 single_instruction;
4736 dst : E(write);
4737 src1 : R(read);
4738 MS : R(5);
4739 %}
4741 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4742 single_instruction;
4743 dst : E(write)+4;
4744 src1 : R(read);
4745 src2 : R(read);
4746 MS : R(6);
4747 %}
4749 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4750 single_instruction;
4751 dst : E(write)+4;
4752 src1 : R(read);
4753 MS : R(6);
4754 %}
4756 // Integer Divide reg-reg
4757 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4758 instruction_count(1); multiple_bundles;
4759 dst : E(write);
4760 temp : E(write);
4761 src1 : R(read);
4762 src2 : R(read);
4763 temp : R(read);
4764 MS : R(38);
4765 %}
4767 // Integer Divide reg-imm
4768 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4769 instruction_count(1); multiple_bundles;
4770 dst : E(write);
4771 temp : E(write);
4772 src1 : R(read);
4773 temp : R(read);
4774 MS : R(38);
4775 %}
4777 // Long Divide
4778 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4779 dst : E(write)+71;
4780 src1 : R(read);
4781 src2 : R(read)+1;
4782 MS : R(70);
4783 %}
4785 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4786 dst : E(write)+71;
4787 src1 : R(read);
4788 MS : R(70);
4789 %}
4791 // Floating Point Add Float
4792 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4793 single_instruction;
4794 dst : X(write);
4795 src1 : E(read);
4796 src2 : E(read);
4797 FA : R;
4798 %}
4800 // Floating Point Add Double
4801 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4802 single_instruction;
4803 dst : X(write);
4804 src1 : E(read);
4805 src2 : E(read);
4806 FA : R;
4807 %}
4809 // Floating Point Conditional Move based on integer flags
4810 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4811 single_instruction;
4812 dst : X(write);
4813 src : E(read);
4814 cr : R(read);
4815 FA : R(2);
4816 BR : R(2);
4817 %}
4819 // Floating Point Conditional Move based on integer flags
4820 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4821 single_instruction;
4822 dst : X(write);
4823 src : E(read);
4824 cr : R(read);
4825 FA : R(2);
4826 BR : R(2);
4827 %}
4829 // Floating Point Multiply Float
4830 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4831 single_instruction;
4832 dst : X(write);
4833 src1 : E(read);
4834 src2 : E(read);
4835 FM : R;
4836 %}
4838 // Floating Point Multiply Double
4839 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4840 single_instruction;
4841 dst : X(write);
4842 src1 : E(read);
4843 src2 : E(read);
4844 FM : R;
4845 %}
4847 // Floating Point Divide Float
4848 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4849 single_instruction;
4850 dst : X(write);
4851 src1 : E(read);
4852 src2 : E(read);
4853 FM : R;
4854 FDIV : C(14);
4855 %}
4857 // Floating Point Divide Double
4858 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4859 single_instruction;
4860 dst : X(write);
4861 src1 : E(read);
4862 src2 : E(read);
4863 FM : R;
4864 FDIV : C(17);
4865 %}
4867 // Floating Point Move/Negate/Abs Float
4868 pipe_class faddF_reg(regF dst, regF src) %{
4869 single_instruction;
4870 dst : W(write);
4871 src : E(read);
4872 FA : R(1);
4873 %}
4875 // Floating Point Move/Negate/Abs Double
4876 pipe_class faddD_reg(regD dst, regD src) %{
4877 single_instruction;
4878 dst : W(write);
4879 src : E(read);
4880 FA : R;
4881 %}
4883 // Floating Point Convert F->D
4884 pipe_class fcvtF2D(regD dst, regF src) %{
4885 single_instruction;
4886 dst : X(write);
4887 src : E(read);
4888 FA : R;
4889 %}
4891 // Floating Point Convert I->D
4892 pipe_class fcvtI2D(regD dst, regF src) %{
4893 single_instruction;
4894 dst : X(write);
4895 src : E(read);
4896 FA : R;
4897 %}
4899 // Floating Point Convert LHi->D
4900 pipe_class fcvtLHi2D(regD dst, regD src) %{
4901 single_instruction;
4902 dst : X(write);
4903 src : E(read);
4904 FA : R;
4905 %}
4907 // Floating Point Convert L->D
4908 pipe_class fcvtL2D(regD dst, regF src) %{
4909 single_instruction;
4910 dst : X(write);
4911 src : E(read);
4912 FA : R;
4913 %}
4915 // Floating Point Convert L->F
4916 pipe_class fcvtL2F(regD dst, regF src) %{
4917 single_instruction;
4918 dst : X(write);
4919 src : E(read);
4920 FA : R;
4921 %}
4923 // Floating Point Convert D->F
4924 pipe_class fcvtD2F(regD dst, regF src) %{
4925 single_instruction;
4926 dst : X(write);
4927 src : E(read);
4928 FA : R;
4929 %}
4931 // Floating Point Convert I->L
4932 pipe_class fcvtI2L(regD dst, regF src) %{
4933 single_instruction;
4934 dst : X(write);
4935 src : E(read);
4936 FA : R;
4937 %}
4939 // Floating Point Convert D->F
4940 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4941 instruction_count(1); multiple_bundles;
4942 dst : X(write)+6;
4943 src : E(read);
4944 FA : R;
4945 %}
4947 // Floating Point Convert D->L
4948 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4949 instruction_count(1); multiple_bundles;
4950 dst : X(write)+6;
4951 src : E(read);
4952 FA : R;
4953 %}
4955 // Floating Point Convert F->I
4956 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4957 instruction_count(1); multiple_bundles;
4958 dst : X(write)+6;
4959 src : E(read);
4960 FA : R;
4961 %}
4963 // Floating Point Convert F->L
4964 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4965 instruction_count(1); multiple_bundles;
4966 dst : X(write)+6;
4967 src : E(read);
4968 FA : R;
4969 %}
4971 // Floating Point Convert I->F
4972 pipe_class fcvtI2F(regF dst, regF src) %{
4973 single_instruction;
4974 dst : X(write);
4975 src : E(read);
4976 FA : R;
4977 %}
4979 // Floating Point Compare
4980 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4981 single_instruction;
4982 cr : X(write);
4983 src1 : E(read);
4984 src2 : E(read);
4985 FA : R;
4986 %}
4988 // Floating Point Compare
4989 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4990 single_instruction;
4991 cr : X(write);
4992 src1 : E(read);
4993 src2 : E(read);
4994 FA : R;
4995 %}
4997 // Floating Add Nop
4998 pipe_class fadd_nop() %{
4999 single_instruction;
5000 FA : R;
5001 %}
5003 // Integer Store to Memory
5004 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5005 single_instruction;
5006 mem : R(read);
5007 src : C(read);
5008 MS : R;
5009 %}
5011 // Integer Store to Memory
5012 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5013 single_instruction;
5014 mem : R(read);
5015 src : C(read);
5016 MS : R;
5017 %}
5019 // Integer Store Zero to Memory
5020 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5021 single_instruction;
5022 mem : R(read);
5023 MS : R;
5024 %}
5026 // Special Stack Slot Store
5027 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5028 single_instruction;
5029 stkSlot : R(read);
5030 src : C(read);
5031 MS : R;
5032 %}
5034 // Special Stack Slot Store
5035 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5036 instruction_count(2); multiple_bundles;
5037 stkSlot : R(read);
5038 src : C(read);
5039 MS : R(2);
5040 %}
5042 // Float Store
5043 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5044 single_instruction;
5045 mem : R(read);
5046 src : C(read);
5047 MS : R;
5048 %}
5050 // Float Store
5051 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5052 single_instruction;
5053 mem : R(read);
5054 MS : R;
5055 %}
5057 // Double Store
5058 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5059 instruction_count(1);
5060 mem : R(read);
5061 src : C(read);
5062 MS : R;
5063 %}
5065 // Double Store
5066 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5067 single_instruction;
5068 mem : R(read);
5069 MS : R;
5070 %}
5072 // Special Stack Slot Float Store
5073 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5074 single_instruction;
5075 stkSlot : R(read);
5076 src : C(read);
5077 MS : R;
5078 %}
5080 // Special Stack Slot Double Store
5081 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5082 single_instruction;
5083 stkSlot : R(read);
5084 src : C(read);
5085 MS : R;
5086 %}
5088 // Integer Load (when sign bit propagation not needed)
5089 pipe_class iload_mem(iRegI dst, memory mem) %{
5090 single_instruction;
5091 mem : R(read);
5092 dst : C(write);
5093 MS : R;
5094 %}
5096 // Integer Load from stack operand
5097 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5098 single_instruction;
5099 mem : R(read);
5100 dst : C(write);
5101 MS : R;
5102 %}
5104 // Integer Load (when sign bit propagation or masking is needed)
5105 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5106 single_instruction;
5107 mem : R(read);
5108 dst : M(write);
5109 MS : R;
5110 %}
5112 // Float Load
5113 pipe_class floadF_mem(regF dst, memory mem) %{
5114 single_instruction;
5115 mem : R(read);
5116 dst : M(write);
5117 MS : R;
5118 %}
5120 // Float Load
5121 pipe_class floadD_mem(regD dst, memory mem) %{
5122 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5123 mem : R(read);
5124 dst : M(write);
5125 MS : R;
5126 %}
5128 // Float Load
5129 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5130 single_instruction;
5131 stkSlot : R(read);
5132 dst : M(write);
5133 MS : R;
5134 %}
5136 // Float Load
5137 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5138 single_instruction;
5139 stkSlot : R(read);
5140 dst : M(write);
5141 MS : R;
5142 %}
5144 // Memory Nop
5145 pipe_class mem_nop() %{
5146 single_instruction;
5147 MS : R;
5148 %}
5150 pipe_class sethi(iRegP dst, immI src) %{
5151 single_instruction;
5152 dst : E(write);
5153 IALU : R;
5154 %}
5156 pipe_class loadPollP(iRegP poll) %{
5157 single_instruction;
5158 poll : R(read);
5159 MS : R;
5160 %}
5162 pipe_class br(Universe br, label labl) %{
5163 single_instruction_with_delay_slot;
5164 BR : R;
5165 %}
5167 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5168 single_instruction_with_delay_slot;
5169 cr : E(read);
5170 BR : R;
5171 %}
5173 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5174 single_instruction_with_delay_slot;
5175 op1 : E(read);
5176 BR : R;
5177 MS : R;
5178 %}
5180 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5181 single_instruction_with_delay_slot;
5182 cr : E(read);
5183 BR : R;
5184 %}
5186 pipe_class br_nop() %{
5187 single_instruction;
5188 BR : R;
5189 %}
5191 pipe_class simple_call(method meth) %{
5192 instruction_count(2); multiple_bundles; force_serialization;
5193 fixed_latency(100);
5194 BR : R(1);
5195 MS : R(1);
5196 A0 : R(1);
5197 %}
5199 pipe_class compiled_call(method meth) %{
5200 instruction_count(1); multiple_bundles; force_serialization;
5201 fixed_latency(100);
5202 MS : R(1);
5203 %}
5205 pipe_class call(method meth) %{
5206 instruction_count(0); multiple_bundles; force_serialization;
5207 fixed_latency(100);
5208 %}
5210 pipe_class tail_call(Universe ignore, label labl) %{
5211 single_instruction; has_delay_slot;
5212 fixed_latency(100);
5213 BR : R(1);
5214 MS : R(1);
5215 %}
5217 pipe_class ret(Universe ignore) %{
5218 single_instruction; has_delay_slot;
5219 BR : R(1);
5220 MS : R(1);
5221 %}
5223 pipe_class ret_poll(g3RegP poll) %{
5224 instruction_count(3); has_delay_slot;
5225 poll : E(read);
5226 MS : R;
5227 %}
5229 // The real do-nothing guy
5230 pipe_class empty( ) %{
5231 instruction_count(0);
5232 %}
5234 pipe_class long_memory_op() %{
5235 instruction_count(0); multiple_bundles; force_serialization;
5236 fixed_latency(25);
5237 MS : R(1);
5238 %}
5240 // Check-cast
5241 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5242 array : R(read);
5243 match : R(read);
5244 IALU : R(2);
5245 BR : R(2);
5246 MS : R;
5247 %}
5249 // Convert FPU flags into +1,0,-1
5250 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5251 src1 : E(read);
5252 src2 : E(read);
5253 dst : E(write);
5254 FA : R;
5255 MS : R(2);
5256 BR : R(2);
5257 %}
5259 // Compare for p < q, and conditionally add y
5260 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5261 p : E(read);
5262 q : E(read);
5263 y : E(read);
5264 IALU : R(3)
5265 %}
5267 // Perform a compare, then move conditionally in a branch delay slot.
5268 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5269 src2 : E(read);
5270 srcdst : E(read);
5271 IALU : R;
5272 BR : R;
5273 %}
5275 // Define the class for the Nop node
5276 define %{
5277 MachNop = ialu_nop;
5278 %}
5280 %}
5282 //----------INSTRUCTIONS-------------------------------------------------------
5284 //------------Special Stack Slot instructions - no match rules-----------------
5285 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5286 // No match rule to avoid chain rule match.
5287 effect(DEF dst, USE src);
5288 ins_cost(MEMORY_REF_COST);
5289 size(4);
5290 format %{ "LDF $src,$dst\t! stkI to regF" %}
5291 opcode(Assembler::ldf_op3);
5292 ins_encode(simple_form3_mem_reg(src, dst));
5293 ins_pipe(floadF_stk);
5294 %}
5296 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5297 // No match rule to avoid chain rule match.
5298 effect(DEF dst, USE src);
5299 ins_cost(MEMORY_REF_COST);
5300 size(4);
5301 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5302 opcode(Assembler::lddf_op3);
5303 ins_encode(simple_form3_mem_reg(src, dst));
5304 ins_pipe(floadD_stk);
5305 %}
5307 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5308 // No match rule to avoid chain rule match.
5309 effect(DEF dst, USE src);
5310 ins_cost(MEMORY_REF_COST);
5311 size(4);
5312 format %{ "STF $src,$dst\t! regF to stkI" %}
5313 opcode(Assembler::stf_op3);
5314 ins_encode(simple_form3_mem_reg(dst, src));
5315 ins_pipe(fstoreF_stk_reg);
5316 %}
5318 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5319 // No match rule to avoid chain rule match.
5320 effect(DEF dst, USE src);
5321 ins_cost(MEMORY_REF_COST);
5322 size(4);
5323 format %{ "STDF $src,$dst\t! regD to stkL" %}
5324 opcode(Assembler::stdf_op3);
5325 ins_encode(simple_form3_mem_reg(dst, src));
5326 ins_pipe(fstoreD_stk_reg);
5327 %}
5329 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5330 effect(DEF dst, USE src);
5331 ins_cost(MEMORY_REF_COST*2);
5332 size(8);
5333 format %{ "STW $src,$dst.hi\t! long\n\t"
5334 "STW R_G0,$dst.lo" %}
5335 opcode(Assembler::stw_op3);
5336 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5337 ins_pipe(lstoreI_stk_reg);
5338 %}
5340 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5341 // No match rule to avoid chain rule match.
5342 effect(DEF dst, USE src);
5343 ins_cost(MEMORY_REF_COST);
5344 size(4);
5345 format %{ "STX $src,$dst\t! regL to stkD" %}
5346 opcode(Assembler::stx_op3);
5347 ins_encode(simple_form3_mem_reg( dst, src ) );
5348 ins_pipe(istore_stk_reg);
5349 %}
5351 //---------- Chain stack slots between similar types --------
5353 // Load integer from stack slot
5354 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5355 match(Set dst src);
5356 ins_cost(MEMORY_REF_COST);
5358 size(4);
5359 format %{ "LDUW $src,$dst\t!stk" %}
5360 opcode(Assembler::lduw_op3);
5361 ins_encode(simple_form3_mem_reg( src, dst ) );
5362 ins_pipe(iload_mem);
5363 %}
5365 // Store integer to stack slot
5366 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5367 match(Set dst src);
5368 ins_cost(MEMORY_REF_COST);
5370 size(4);
5371 format %{ "STW $src,$dst\t!stk" %}
5372 opcode(Assembler::stw_op3);
5373 ins_encode(simple_form3_mem_reg( dst, src ) );
5374 ins_pipe(istore_mem_reg);
5375 %}
5377 // Load long from stack slot
5378 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5379 match(Set dst src);
5381 ins_cost(MEMORY_REF_COST);
5382 size(4);
5383 format %{ "LDX $src,$dst\t! long" %}
5384 opcode(Assembler::ldx_op3);
5385 ins_encode(simple_form3_mem_reg( src, dst ) );
5386 ins_pipe(iload_mem);
5387 %}
5389 // Store long to stack slot
5390 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5391 match(Set dst src);
5393 ins_cost(MEMORY_REF_COST);
5394 size(4);
5395 format %{ "STX $src,$dst\t! long" %}
5396 opcode(Assembler::stx_op3);
5397 ins_encode(simple_form3_mem_reg( dst, src ) );
5398 ins_pipe(istore_mem_reg);
5399 %}
5401 #ifdef _LP64
5402 // Load pointer from stack slot, 64-bit encoding
5403 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5404 match(Set dst src);
5405 ins_cost(MEMORY_REF_COST);
5406 size(4);
5407 format %{ "LDX $src,$dst\t!ptr" %}
5408 opcode(Assembler::ldx_op3);
5409 ins_encode(simple_form3_mem_reg( src, dst ) );
5410 ins_pipe(iload_mem);
5411 %}
5413 // Store pointer to stack slot
5414 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5415 match(Set dst src);
5416 ins_cost(MEMORY_REF_COST);
5417 size(4);
5418 format %{ "STX $src,$dst\t!ptr" %}
5419 opcode(Assembler::stx_op3);
5420 ins_encode(simple_form3_mem_reg( dst, src ) );
5421 ins_pipe(istore_mem_reg);
5422 %}
5423 #else // _LP64
5424 // Load pointer from stack slot, 32-bit encoding
5425 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5426 match(Set dst src);
5427 ins_cost(MEMORY_REF_COST);
5428 format %{ "LDUW $src,$dst\t!ptr" %}
5429 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5430 ins_encode(simple_form3_mem_reg( src, dst ) );
5431 ins_pipe(iload_mem);
5432 %}
5434 // Store pointer to stack slot
5435 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5436 match(Set dst src);
5437 ins_cost(MEMORY_REF_COST);
5438 format %{ "STW $src,$dst\t!ptr" %}
5439 opcode(Assembler::stw_op3, Assembler::ldst_op);
5440 ins_encode(simple_form3_mem_reg( dst, src ) );
5441 ins_pipe(istore_mem_reg);
5442 %}
5443 #endif // _LP64
5445 //------------Special Nop instructions for bundling - no match rules-----------
5446 // Nop using the A0 functional unit
5447 instruct Nop_A0() %{
5448 ins_cost(0);
5450 format %{ "NOP ! Alu Pipeline" %}
5451 opcode(Assembler::or_op3, Assembler::arith_op);
5452 ins_encode( form2_nop() );
5453 ins_pipe(ialu_nop_A0);
5454 %}
5456 // Nop using the A1 functional unit
5457 instruct Nop_A1( ) %{
5458 ins_cost(0);
5460 format %{ "NOP ! Alu Pipeline" %}
5461 opcode(Assembler::or_op3, Assembler::arith_op);
5462 ins_encode( form2_nop() );
5463 ins_pipe(ialu_nop_A1);
5464 %}
5466 // Nop using the memory functional unit
5467 instruct Nop_MS( ) %{
5468 ins_cost(0);
5470 format %{ "NOP ! Memory Pipeline" %}
5471 ins_encode( emit_mem_nop );
5472 ins_pipe(mem_nop);
5473 %}
5475 // Nop using the floating add functional unit
5476 instruct Nop_FA( ) %{
5477 ins_cost(0);
5479 format %{ "NOP ! Floating Add Pipeline" %}
5480 ins_encode( emit_fadd_nop );
5481 ins_pipe(fadd_nop);
5482 %}
5484 // Nop using the branch functional unit
5485 instruct Nop_BR( ) %{
5486 ins_cost(0);
5488 format %{ "NOP ! Branch Pipeline" %}
5489 ins_encode( emit_br_nop );
5490 ins_pipe(br_nop);
5491 %}
5493 //----------Load/Store/Move Instructions---------------------------------------
5494 //----------Load Instructions--------------------------------------------------
5495 // Load Byte (8bit signed)
5496 instruct loadB(iRegI dst, memory mem) %{
5497 match(Set dst (LoadB mem));
5498 ins_cost(MEMORY_REF_COST);
5500 size(4);
5501 format %{ "LDSB $mem,$dst\t! byte" %}
5502 ins_encode %{
5503 __ ldsb($mem$$Address, $dst$$Register);
5504 %}
5505 ins_pipe(iload_mask_mem);
5506 %}
5508 // Load Byte (8bit signed) into a Long Register
5509 instruct loadB2L(iRegL dst, memory mem) %{
5510 match(Set dst (ConvI2L (LoadB mem)));
5511 ins_cost(MEMORY_REF_COST);
5513 size(4);
5514 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5515 ins_encode %{
5516 __ ldsb($mem$$Address, $dst$$Register);
5517 %}
5518 ins_pipe(iload_mask_mem);
5519 %}
5521 // Load Unsigned Byte (8bit UNsigned) into an int reg
5522 instruct loadUB(iRegI dst, memory mem) %{
5523 match(Set dst (LoadUB mem));
5524 ins_cost(MEMORY_REF_COST);
5526 size(4);
5527 format %{ "LDUB $mem,$dst\t! ubyte" %}
5528 ins_encode %{
5529 __ ldub($mem$$Address, $dst$$Register);
5530 %}
5531 ins_pipe(iload_mem);
5532 %}
5534 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5535 instruct loadUB2L(iRegL dst, memory mem) %{
5536 match(Set dst (ConvI2L (LoadUB mem)));
5537 ins_cost(MEMORY_REF_COST);
5539 size(4);
5540 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5541 ins_encode %{
5542 __ ldub($mem$$Address, $dst$$Register);
5543 %}
5544 ins_pipe(iload_mem);
5545 %}
5547 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5548 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5549 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5550 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5552 size(2*4);
5553 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5554 "AND $dst,$mask,$dst" %}
5555 ins_encode %{
5556 __ ldub($mem$$Address, $dst$$Register);
5557 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5558 %}
5559 ins_pipe(iload_mem);
5560 %}
5562 // Load Short (16bit signed)
5563 instruct loadS(iRegI dst, memory mem) %{
5564 match(Set dst (LoadS mem));
5565 ins_cost(MEMORY_REF_COST);
5567 size(4);
5568 format %{ "LDSH $mem,$dst\t! short" %}
5569 ins_encode %{
5570 __ ldsh($mem$$Address, $dst$$Register);
5571 %}
5572 ins_pipe(iload_mask_mem);
5573 %}
5575 // Load Short (16 bit signed) to Byte (8 bit signed)
5576 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5577 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5578 ins_cost(MEMORY_REF_COST);
5580 size(4);
5582 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5583 ins_encode %{
5584 __ ldsb($mem$$Address, $dst$$Register, 1);
5585 %}
5586 ins_pipe(iload_mask_mem);
5587 %}
5589 // Load Short (16bit signed) into a Long Register
5590 instruct loadS2L(iRegL dst, memory mem) %{
5591 match(Set dst (ConvI2L (LoadS mem)));
5592 ins_cost(MEMORY_REF_COST);
5594 size(4);
5595 format %{ "LDSH $mem,$dst\t! short -> long" %}
5596 ins_encode %{
5597 __ ldsh($mem$$Address, $dst$$Register);
5598 %}
5599 ins_pipe(iload_mask_mem);
5600 %}
5602 // Load Unsigned Short/Char (16bit UNsigned)
5603 instruct loadUS(iRegI dst, memory mem) %{
5604 match(Set dst (LoadUS mem));
5605 ins_cost(MEMORY_REF_COST);
5607 size(4);
5608 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5609 ins_encode %{
5610 __ lduh($mem$$Address, $dst$$Register);
5611 %}
5612 ins_pipe(iload_mem);
5613 %}
5615 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5616 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5617 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5618 ins_cost(MEMORY_REF_COST);
5620 size(4);
5621 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5622 ins_encode %{
5623 __ ldsb($mem$$Address, $dst$$Register, 1);
5624 %}
5625 ins_pipe(iload_mask_mem);
5626 %}
5628 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5629 instruct loadUS2L(iRegL dst, memory mem) %{
5630 match(Set dst (ConvI2L (LoadUS mem)));
5631 ins_cost(MEMORY_REF_COST);
5633 size(4);
5634 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5635 ins_encode %{
5636 __ lduh($mem$$Address, $dst$$Register);
5637 %}
5638 ins_pipe(iload_mem);
5639 %}
5641 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5642 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5643 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5644 ins_cost(MEMORY_REF_COST);
5646 size(4);
5647 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5648 ins_encode %{
5649 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5650 %}
5651 ins_pipe(iload_mem);
5652 %}
5654 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5655 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5656 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5657 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5659 size(2*4);
5660 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5661 "AND $dst,$mask,$dst" %}
5662 ins_encode %{
5663 Register Rdst = $dst$$Register;
5664 __ lduh($mem$$Address, Rdst);
5665 __ and3(Rdst, $mask$$constant, Rdst);
5666 %}
5667 ins_pipe(iload_mem);
5668 %}
5670 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5671 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5672 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5673 effect(TEMP dst, TEMP tmp);
5674 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5676 size((3+1)*4); // set may use two instructions.
5677 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5678 "SET $mask,$tmp\n\t"
5679 "AND $dst,$tmp,$dst" %}
5680 ins_encode %{
5681 Register Rdst = $dst$$Register;
5682 Register Rtmp = $tmp$$Register;
5683 __ lduh($mem$$Address, Rdst);
5684 __ set($mask$$constant, Rtmp);
5685 __ and3(Rdst, Rtmp, Rdst);
5686 %}
5687 ins_pipe(iload_mem);
5688 %}
5690 // Load Integer
5691 instruct loadI(iRegI dst, memory mem) %{
5692 match(Set dst (LoadI mem));
5693 ins_cost(MEMORY_REF_COST);
5695 size(4);
5696 format %{ "LDUW $mem,$dst\t! int" %}
5697 ins_encode %{
5698 __ lduw($mem$$Address, $dst$$Register);
5699 %}
5700 ins_pipe(iload_mem);
5701 %}
5703 // Load Integer to Byte (8 bit signed)
5704 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5705 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5706 ins_cost(MEMORY_REF_COST);
5708 size(4);
5710 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5711 ins_encode %{
5712 __ ldsb($mem$$Address, $dst$$Register, 3);
5713 %}
5714 ins_pipe(iload_mask_mem);
5715 %}
5717 // Load Integer to Unsigned Byte (8 bit UNsigned)
5718 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5719 match(Set dst (AndI (LoadI mem) mask));
5720 ins_cost(MEMORY_REF_COST);
5722 size(4);
5724 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5725 ins_encode %{
5726 __ ldub($mem$$Address, $dst$$Register, 3);
5727 %}
5728 ins_pipe(iload_mask_mem);
5729 %}
5731 // Load Integer to Short (16 bit signed)
5732 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5733 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5734 ins_cost(MEMORY_REF_COST);
5736 size(4);
5738 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5739 ins_encode %{
5740 __ ldsh($mem$$Address, $dst$$Register, 2);
5741 %}
5742 ins_pipe(iload_mask_mem);
5743 %}
5745 // Load Integer to Unsigned Short (16 bit UNsigned)
5746 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5747 match(Set dst (AndI (LoadI mem) mask));
5748 ins_cost(MEMORY_REF_COST);
5750 size(4);
5752 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5753 ins_encode %{
5754 __ lduh($mem$$Address, $dst$$Register, 2);
5755 %}
5756 ins_pipe(iload_mask_mem);
5757 %}
5759 // Load Integer into a Long Register
5760 instruct loadI2L(iRegL dst, memory mem) %{
5761 match(Set dst (ConvI2L (LoadI mem)));
5762 ins_cost(MEMORY_REF_COST);
5764 size(4);
5765 format %{ "LDSW $mem,$dst\t! int -> long" %}
5766 ins_encode %{
5767 __ ldsw($mem$$Address, $dst$$Register);
5768 %}
5769 ins_pipe(iload_mask_mem);
5770 %}
5772 // Load Integer with mask 0xFF into a Long Register
5773 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5774 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5775 ins_cost(MEMORY_REF_COST);
5777 size(4);
5778 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5779 ins_encode %{
5780 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5781 %}
5782 ins_pipe(iload_mem);
5783 %}
5785 // Load Integer with mask 0xFFFF into a Long Register
5786 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5787 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5788 ins_cost(MEMORY_REF_COST);
5790 size(4);
5791 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5792 ins_encode %{
5793 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5794 %}
5795 ins_pipe(iload_mem);
5796 %}
5798 // Load Integer with a 13-bit mask into a Long Register
5799 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5800 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5801 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5803 size(2*4);
5804 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5805 "AND $dst,$mask,$dst" %}
5806 ins_encode %{
5807 Register Rdst = $dst$$Register;
5808 __ lduw($mem$$Address, Rdst);
5809 __ and3(Rdst, $mask$$constant, Rdst);
5810 %}
5811 ins_pipe(iload_mem);
5812 %}
5814 // Load Integer with a 32-bit mask into a Long Register
5815 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5816 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5817 effect(TEMP dst, TEMP tmp);
5818 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5820 size((3+1)*4); // set may use two instructions.
5821 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5822 "SET $mask,$tmp\n\t"
5823 "AND $dst,$tmp,$dst" %}
5824 ins_encode %{
5825 Register Rdst = $dst$$Register;
5826 Register Rtmp = $tmp$$Register;
5827 __ lduw($mem$$Address, Rdst);
5828 __ set($mask$$constant, Rtmp);
5829 __ and3(Rdst, Rtmp, Rdst);
5830 %}
5831 ins_pipe(iload_mem);
5832 %}
5834 // Load Unsigned Integer into a Long Register
5835 instruct loadUI2L(iRegL dst, memory mem) %{
5836 match(Set dst (LoadUI2L mem));
5837 ins_cost(MEMORY_REF_COST);
5839 size(4);
5840 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5841 ins_encode %{
5842 __ lduw($mem$$Address, $dst$$Register);
5843 %}
5844 ins_pipe(iload_mem);
5845 %}
5847 // Load Long - aligned
5848 instruct loadL(iRegL dst, memory mem ) %{
5849 match(Set dst (LoadL mem));
5850 ins_cost(MEMORY_REF_COST);
5852 size(4);
5853 format %{ "LDX $mem,$dst\t! long" %}
5854 ins_encode %{
5855 __ ldx($mem$$Address, $dst$$Register);
5856 %}
5857 ins_pipe(iload_mem);
5858 %}
5860 // Load Long - UNaligned
5861 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5862 match(Set dst (LoadL_unaligned mem));
5863 effect(KILL tmp);
5864 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5865 size(16);
5866 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5867 "\tLDUW $mem ,$dst\n"
5868 "\tSLLX #32, $dst, $dst\n"
5869 "\tOR $dst, R_O7, $dst" %}
5870 opcode(Assembler::lduw_op3);
5871 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5872 ins_pipe(iload_mem);
5873 %}
5875 // Load Aligned Packed Byte into a Double Register
5876 instruct loadA8B(regD dst, memory mem) %{
5877 match(Set dst (Load8B mem));
5878 ins_cost(MEMORY_REF_COST);
5879 size(4);
5880 format %{ "LDDF $mem,$dst\t! packed8B" %}
5881 opcode(Assembler::lddf_op3);
5882 ins_encode(simple_form3_mem_reg( mem, dst ) );
5883 ins_pipe(floadD_mem);
5884 %}
5886 // Load Aligned Packed Char into a Double Register
5887 instruct loadA4C(regD dst, memory mem) %{
5888 match(Set dst (Load4C mem));
5889 ins_cost(MEMORY_REF_COST);
5890 size(4);
5891 format %{ "LDDF $mem,$dst\t! packed4C" %}
5892 opcode(Assembler::lddf_op3);
5893 ins_encode(simple_form3_mem_reg( mem, dst ) );
5894 ins_pipe(floadD_mem);
5895 %}
5897 // Load Aligned Packed Short into a Double Register
5898 instruct loadA4S(regD dst, memory mem) %{
5899 match(Set dst (Load4S mem));
5900 ins_cost(MEMORY_REF_COST);
5901 size(4);
5902 format %{ "LDDF $mem,$dst\t! packed4S" %}
5903 opcode(Assembler::lddf_op3);
5904 ins_encode(simple_form3_mem_reg( mem, dst ) );
5905 ins_pipe(floadD_mem);
5906 %}
5908 // Load Aligned Packed Int into a Double Register
5909 instruct loadA2I(regD dst, memory mem) %{
5910 match(Set dst (Load2I mem));
5911 ins_cost(MEMORY_REF_COST);
5912 size(4);
5913 format %{ "LDDF $mem,$dst\t! packed2I" %}
5914 opcode(Assembler::lddf_op3);
5915 ins_encode(simple_form3_mem_reg( mem, dst ) );
5916 ins_pipe(floadD_mem);
5917 %}
5919 // Load Range
5920 instruct loadRange(iRegI dst, memory mem) %{
5921 match(Set dst (LoadRange mem));
5922 ins_cost(MEMORY_REF_COST);
5924 size(4);
5925 format %{ "LDUW $mem,$dst\t! range" %}
5926 opcode(Assembler::lduw_op3);
5927 ins_encode(simple_form3_mem_reg( mem, dst ) );
5928 ins_pipe(iload_mem);
5929 %}
5931 // Load Integer into %f register (for fitos/fitod)
5932 instruct loadI_freg(regF dst, memory mem) %{
5933 match(Set dst (LoadI mem));
5934 ins_cost(MEMORY_REF_COST);
5935 size(4);
5937 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5938 opcode(Assembler::ldf_op3);
5939 ins_encode(simple_form3_mem_reg( mem, dst ) );
5940 ins_pipe(floadF_mem);
5941 %}
5943 // Load Pointer
5944 instruct loadP(iRegP dst, memory mem) %{
5945 match(Set dst (LoadP mem));
5946 ins_cost(MEMORY_REF_COST);
5947 size(4);
5949 #ifndef _LP64
5950 format %{ "LDUW $mem,$dst\t! ptr" %}
5951 ins_encode %{
5952 __ lduw($mem$$Address, $dst$$Register);
5953 %}
5954 #else
5955 format %{ "LDX $mem,$dst\t! ptr" %}
5956 ins_encode %{
5957 __ ldx($mem$$Address, $dst$$Register);
5958 %}
5959 #endif
5960 ins_pipe(iload_mem);
5961 %}
5963 // Load Compressed Pointer
5964 instruct loadN(iRegN dst, memory mem) %{
5965 match(Set dst (LoadN mem));
5966 ins_cost(MEMORY_REF_COST);
5967 size(4);
5969 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5970 ins_encode %{
5971 __ lduw($mem$$Address, $dst$$Register);
5972 %}
5973 ins_pipe(iload_mem);
5974 %}
5976 // Load Klass Pointer
5977 instruct loadKlass(iRegP dst, memory mem) %{
5978 match(Set dst (LoadKlass mem));
5979 ins_cost(MEMORY_REF_COST);
5980 size(4);
5982 #ifndef _LP64
5983 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5984 ins_encode %{
5985 __ lduw($mem$$Address, $dst$$Register);
5986 %}
5987 #else
5988 format %{ "LDX $mem,$dst\t! klass ptr" %}
5989 ins_encode %{
5990 __ ldx($mem$$Address, $dst$$Register);
5991 %}
5992 #endif
5993 ins_pipe(iload_mem);
5994 %}
5996 // Load narrow Klass Pointer
5997 instruct loadNKlass(iRegN dst, memory mem) %{
5998 match(Set dst (LoadNKlass mem));
5999 ins_cost(MEMORY_REF_COST);
6000 size(4);
6002 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6003 ins_encode %{
6004 __ lduw($mem$$Address, $dst$$Register);
6005 %}
6006 ins_pipe(iload_mem);
6007 %}
6009 // Load Double
6010 instruct loadD(regD dst, memory mem) %{
6011 match(Set dst (LoadD mem));
6012 ins_cost(MEMORY_REF_COST);
6014 size(4);
6015 format %{ "LDDF $mem,$dst" %}
6016 opcode(Assembler::lddf_op3);
6017 ins_encode(simple_form3_mem_reg( mem, dst ) );
6018 ins_pipe(floadD_mem);
6019 %}
6021 // Load Double - UNaligned
6022 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6023 match(Set dst (LoadD_unaligned mem));
6024 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6025 size(8);
6026 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6027 "\tLDF $mem+4,$dst.lo\t!" %}
6028 opcode(Assembler::ldf_op3);
6029 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6030 ins_pipe(iload_mem);
6031 %}
6033 // Load Float
6034 instruct loadF(regF dst, memory mem) %{
6035 match(Set dst (LoadF mem));
6036 ins_cost(MEMORY_REF_COST);
6038 size(4);
6039 format %{ "LDF $mem,$dst" %}
6040 opcode(Assembler::ldf_op3);
6041 ins_encode(simple_form3_mem_reg( mem, dst ) );
6042 ins_pipe(floadF_mem);
6043 %}
6045 // Load Constant
6046 instruct loadConI( iRegI dst, immI src ) %{
6047 match(Set dst src);
6048 ins_cost(DEFAULT_COST * 3/2);
6049 format %{ "SET $src,$dst" %}
6050 ins_encode( Set32(src, dst) );
6051 ins_pipe(ialu_hi_lo_reg);
6052 %}
6054 instruct loadConI13( iRegI dst, immI13 src ) %{
6055 match(Set dst src);
6057 size(4);
6058 format %{ "MOV $src,$dst" %}
6059 ins_encode( Set13( src, dst ) );
6060 ins_pipe(ialu_imm);
6061 %}
6063 #ifndef _LP64
6064 instruct loadConP(iRegP dst, immP con) %{
6065 match(Set dst con);
6066 ins_cost(DEFAULT_COST * 3/2);
6067 format %{ "SET $con,$dst\t!ptr" %}
6068 ins_encode %{
6069 // [RGV] This next line should be generated from ADLC
6070 if (_opnds[1]->constant_is_oop()) {
6071 intptr_t val = $con$$constant;
6072 __ set_oop_constant((jobject) val, $dst$$Register);
6073 } else { // non-oop pointers, e.g. card mark base, heap top
6074 __ set($con$$constant, $dst$$Register);
6075 }
6076 %}
6077 ins_pipe(loadConP);
6078 %}
6079 #else
6080 instruct loadConP_set(iRegP dst, immP_set con) %{
6081 match(Set dst con);
6082 ins_cost(DEFAULT_COST * 3/2);
6083 format %{ "SET $con,$dst\t! ptr" %}
6084 ins_encode %{
6085 // [RGV] This next line should be generated from ADLC
6086 if (_opnds[1]->constant_is_oop()) {
6087 intptr_t val = $con$$constant;
6088 __ set_oop_constant((jobject) val, $dst$$Register);
6089 } else { // non-oop pointers, e.g. card mark base, heap top
6090 __ set($con$$constant, $dst$$Register);
6091 }
6092 %}
6093 ins_pipe(loadConP);
6094 %}
6096 instruct loadConP_load(iRegP dst, immP_load con) %{
6097 match(Set dst con);
6098 ins_cost(MEMORY_REF_COST);
6099 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6100 ins_encode %{
6101 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6102 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6103 %}
6104 ins_pipe(loadConP);
6105 %}
6107 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6108 match(Set dst con);
6109 ins_cost(DEFAULT_COST * 3/2);
6110 format %{ "SET $con,$dst\t! non-oop ptr" %}
6111 ins_encode %{
6112 __ set($con$$constant, $dst$$Register);
6113 %}
6114 ins_pipe(loadConP);
6115 %}
6116 #endif // _LP64
6118 instruct loadConP0(iRegP dst, immP0 src) %{
6119 match(Set dst src);
6121 size(4);
6122 format %{ "CLR $dst\t!ptr" %}
6123 ins_encode %{
6124 __ clr($dst$$Register);
6125 %}
6126 ins_pipe(ialu_imm);
6127 %}
6129 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6130 match(Set dst src);
6131 ins_cost(DEFAULT_COST);
6132 format %{ "SET $src,$dst\t!ptr" %}
6133 ins_encode %{
6134 AddressLiteral polling_page(os::get_polling_page());
6135 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6136 %}
6137 ins_pipe(loadConP_poll);
6138 %}
6140 instruct loadConN0(iRegN dst, immN0 src) %{
6141 match(Set dst src);
6143 size(4);
6144 format %{ "CLR $dst\t! compressed NULL ptr" %}
6145 ins_encode %{
6146 __ clr($dst$$Register);
6147 %}
6148 ins_pipe(ialu_imm);
6149 %}
6151 instruct loadConN(iRegN dst, immN src) %{
6152 match(Set dst src);
6153 ins_cost(DEFAULT_COST * 3/2);
6154 format %{ "SET $src,$dst\t! compressed ptr" %}
6155 ins_encode %{
6156 Register dst = $dst$$Register;
6157 __ set_narrow_oop((jobject)$src$$constant, dst);
6158 %}
6159 ins_pipe(ialu_hi_lo_reg);
6160 %}
6162 // Materialize long value (predicated by immL_cheap).
6163 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6164 match(Set dst con);
6165 effect(KILL tmp);
6166 ins_cost(DEFAULT_COST * 3);
6167 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6168 ins_encode %{
6169 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6170 %}
6171 ins_pipe(loadConL);
6172 %}
6174 // Load long value from constant table (predicated by immL_expensive).
6175 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6176 match(Set dst con);
6177 ins_cost(MEMORY_REF_COST);
6178 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6179 ins_encode %{
6180 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6181 __ ldx($constanttablebase, con_offset, $dst$$Register);
6182 %}
6183 ins_pipe(loadConL);
6184 %}
6186 instruct loadConL0( iRegL dst, immL0 src ) %{
6187 match(Set dst src);
6188 ins_cost(DEFAULT_COST);
6189 size(4);
6190 format %{ "CLR $dst\t! long" %}
6191 ins_encode( Set13( src, dst ) );
6192 ins_pipe(ialu_imm);
6193 %}
6195 instruct loadConL13( iRegL dst, immL13 src ) %{
6196 match(Set dst src);
6197 ins_cost(DEFAULT_COST * 2);
6199 size(4);
6200 format %{ "MOV $src,$dst\t! long" %}
6201 ins_encode( Set13( src, dst ) );
6202 ins_pipe(ialu_imm);
6203 %}
6205 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6206 match(Set dst con);
6207 effect(KILL tmp);
6208 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6209 ins_encode %{
6210 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6211 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6212 %}
6213 ins_pipe(loadConFD);
6214 %}
6216 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6217 match(Set dst con);
6218 effect(KILL tmp);
6219 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6220 ins_encode %{
6221 // XXX This is a quick fix for 6833573.
6222 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6223 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6224 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6225 %}
6226 ins_pipe(loadConFD);
6227 %}
6229 // Prefetch instructions.
6230 // Must be safe to execute with invalid address (cannot fault).
6232 instruct prefetchr( memory mem ) %{
6233 match( PrefetchRead mem );
6234 ins_cost(MEMORY_REF_COST);
6236 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6237 opcode(Assembler::prefetch_op3);
6238 ins_encode( form3_mem_prefetch_read( mem ) );
6239 ins_pipe(iload_mem);
6240 %}
6242 instruct prefetchw( memory mem ) %{
6243 predicate(AllocatePrefetchStyle != 3 );
6244 match( PrefetchWrite mem );
6245 ins_cost(MEMORY_REF_COST);
6247 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6248 opcode(Assembler::prefetch_op3);
6249 ins_encode( form3_mem_prefetch_write( mem ) );
6250 ins_pipe(iload_mem);
6251 %}
6253 // Use BIS instruction to prefetch.
6254 instruct prefetchw_bis( memory mem ) %{
6255 predicate(AllocatePrefetchStyle == 3);
6256 match( PrefetchWrite mem );
6257 ins_cost(MEMORY_REF_COST);
6259 format %{ "STXA G0,$mem\t! // Block initializing store" %}
6260 ins_encode %{
6261 Register base = as_Register($mem$$base);
6262 int disp = $mem$$disp;
6263 if (disp != 0) {
6264 __ add(base, AllocatePrefetchStepSize, base);
6265 }
6266 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P);
6267 %}
6268 ins_pipe(istore_mem_reg);
6269 %}
6271 //----------Store Instructions-------------------------------------------------
6272 // Store Byte
6273 instruct storeB(memory mem, iRegI src) %{
6274 match(Set mem (StoreB mem src));
6275 ins_cost(MEMORY_REF_COST);
6277 size(4);
6278 format %{ "STB $src,$mem\t! byte" %}
6279 opcode(Assembler::stb_op3);
6280 ins_encode(simple_form3_mem_reg( mem, src ) );
6281 ins_pipe(istore_mem_reg);
6282 %}
6284 instruct storeB0(memory mem, immI0 src) %{
6285 match(Set mem (StoreB mem src));
6286 ins_cost(MEMORY_REF_COST);
6288 size(4);
6289 format %{ "STB $src,$mem\t! byte" %}
6290 opcode(Assembler::stb_op3);
6291 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6292 ins_pipe(istore_mem_zero);
6293 %}
6295 instruct storeCM0(memory mem, immI0 src) %{
6296 match(Set mem (StoreCM mem src));
6297 ins_cost(MEMORY_REF_COST);
6299 size(4);
6300 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6301 opcode(Assembler::stb_op3);
6302 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6303 ins_pipe(istore_mem_zero);
6304 %}
6306 // Store Char/Short
6307 instruct storeC(memory mem, iRegI src) %{
6308 match(Set mem (StoreC mem src));
6309 ins_cost(MEMORY_REF_COST);
6311 size(4);
6312 format %{ "STH $src,$mem\t! short" %}
6313 opcode(Assembler::sth_op3);
6314 ins_encode(simple_form3_mem_reg( mem, src ) );
6315 ins_pipe(istore_mem_reg);
6316 %}
6318 instruct storeC0(memory mem, immI0 src) %{
6319 match(Set mem (StoreC mem src));
6320 ins_cost(MEMORY_REF_COST);
6322 size(4);
6323 format %{ "STH $src,$mem\t! short" %}
6324 opcode(Assembler::sth_op3);
6325 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6326 ins_pipe(istore_mem_zero);
6327 %}
6329 // Store Integer
6330 instruct storeI(memory mem, iRegI src) %{
6331 match(Set mem (StoreI mem src));
6332 ins_cost(MEMORY_REF_COST);
6334 size(4);
6335 format %{ "STW $src,$mem" %}
6336 opcode(Assembler::stw_op3);
6337 ins_encode(simple_form3_mem_reg( mem, src ) );
6338 ins_pipe(istore_mem_reg);
6339 %}
6341 // Store Long
6342 instruct storeL(memory mem, iRegL src) %{
6343 match(Set mem (StoreL mem src));
6344 ins_cost(MEMORY_REF_COST);
6345 size(4);
6346 format %{ "STX $src,$mem\t! long" %}
6347 opcode(Assembler::stx_op3);
6348 ins_encode(simple_form3_mem_reg( mem, src ) );
6349 ins_pipe(istore_mem_reg);
6350 %}
6352 instruct storeI0(memory mem, immI0 src) %{
6353 match(Set mem (StoreI mem src));
6354 ins_cost(MEMORY_REF_COST);
6356 size(4);
6357 format %{ "STW $src,$mem" %}
6358 opcode(Assembler::stw_op3);
6359 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6360 ins_pipe(istore_mem_zero);
6361 %}
6363 instruct storeL0(memory mem, immL0 src) %{
6364 match(Set mem (StoreL mem src));
6365 ins_cost(MEMORY_REF_COST);
6367 size(4);
6368 format %{ "STX $src,$mem" %}
6369 opcode(Assembler::stx_op3);
6370 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6371 ins_pipe(istore_mem_zero);
6372 %}
6374 // Store Integer from float register (used after fstoi)
6375 instruct storeI_Freg(memory mem, regF src) %{
6376 match(Set mem (StoreI mem src));
6377 ins_cost(MEMORY_REF_COST);
6379 size(4);
6380 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6381 opcode(Assembler::stf_op3);
6382 ins_encode(simple_form3_mem_reg( mem, src ) );
6383 ins_pipe(fstoreF_mem_reg);
6384 %}
6386 // Store Pointer
6387 instruct storeP(memory dst, sp_ptr_RegP src) %{
6388 match(Set dst (StoreP dst src));
6389 ins_cost(MEMORY_REF_COST);
6390 size(4);
6392 #ifndef _LP64
6393 format %{ "STW $src,$dst\t! ptr" %}
6394 opcode(Assembler::stw_op3, 0, REGP_OP);
6395 #else
6396 format %{ "STX $src,$dst\t! ptr" %}
6397 opcode(Assembler::stx_op3, 0, REGP_OP);
6398 #endif
6399 ins_encode( form3_mem_reg( dst, src ) );
6400 ins_pipe(istore_mem_spORreg);
6401 %}
6403 instruct storeP0(memory dst, immP0 src) %{
6404 match(Set dst (StoreP dst src));
6405 ins_cost(MEMORY_REF_COST);
6406 size(4);
6408 #ifndef _LP64
6409 format %{ "STW $src,$dst\t! ptr" %}
6410 opcode(Assembler::stw_op3, 0, REGP_OP);
6411 #else
6412 format %{ "STX $src,$dst\t! ptr" %}
6413 opcode(Assembler::stx_op3, 0, REGP_OP);
6414 #endif
6415 ins_encode( form3_mem_reg( dst, R_G0 ) );
6416 ins_pipe(istore_mem_zero);
6417 %}
6419 // Store Compressed Pointer
6420 instruct storeN(memory dst, iRegN src) %{
6421 match(Set dst (StoreN dst src));
6422 ins_cost(MEMORY_REF_COST);
6423 size(4);
6425 format %{ "STW $src,$dst\t! compressed ptr" %}
6426 ins_encode %{
6427 Register base = as_Register($dst$$base);
6428 Register index = as_Register($dst$$index);
6429 Register src = $src$$Register;
6430 if (index != G0) {
6431 __ stw(src, base, index);
6432 } else {
6433 __ stw(src, base, $dst$$disp);
6434 }
6435 %}
6436 ins_pipe(istore_mem_spORreg);
6437 %}
6439 instruct storeN0(memory dst, immN0 src) %{
6440 match(Set dst (StoreN dst src));
6441 ins_cost(MEMORY_REF_COST);
6442 size(4);
6444 format %{ "STW $src,$dst\t! compressed ptr" %}
6445 ins_encode %{
6446 Register base = as_Register($dst$$base);
6447 Register index = as_Register($dst$$index);
6448 if (index != G0) {
6449 __ stw(0, base, index);
6450 } else {
6451 __ stw(0, base, $dst$$disp);
6452 }
6453 %}
6454 ins_pipe(istore_mem_zero);
6455 %}
6457 // Store Double
6458 instruct storeD( memory mem, regD src) %{
6459 match(Set mem (StoreD mem src));
6460 ins_cost(MEMORY_REF_COST);
6462 size(4);
6463 format %{ "STDF $src,$mem" %}
6464 opcode(Assembler::stdf_op3);
6465 ins_encode(simple_form3_mem_reg( mem, src ) );
6466 ins_pipe(fstoreD_mem_reg);
6467 %}
6469 instruct storeD0( memory mem, immD0 src) %{
6470 match(Set mem (StoreD mem src));
6471 ins_cost(MEMORY_REF_COST);
6473 size(4);
6474 format %{ "STX $src,$mem" %}
6475 opcode(Assembler::stx_op3);
6476 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6477 ins_pipe(fstoreD_mem_zero);
6478 %}
6480 // Store Float
6481 instruct storeF( memory mem, regF src) %{
6482 match(Set mem (StoreF mem src));
6483 ins_cost(MEMORY_REF_COST);
6485 size(4);
6486 format %{ "STF $src,$mem" %}
6487 opcode(Assembler::stf_op3);
6488 ins_encode(simple_form3_mem_reg( mem, src ) );
6489 ins_pipe(fstoreF_mem_reg);
6490 %}
6492 instruct storeF0( memory mem, immF0 src) %{
6493 match(Set mem (StoreF mem src));
6494 ins_cost(MEMORY_REF_COST);
6496 size(4);
6497 format %{ "STW $src,$mem\t! storeF0" %}
6498 opcode(Assembler::stw_op3);
6499 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6500 ins_pipe(fstoreF_mem_zero);
6501 %}
6503 // Store Aligned Packed Bytes in Double register to memory
6504 instruct storeA8B(memory mem, regD src) %{
6505 match(Set mem (Store8B mem src));
6506 ins_cost(MEMORY_REF_COST);
6507 size(4);
6508 format %{ "STDF $src,$mem\t! packed8B" %}
6509 opcode(Assembler::stdf_op3);
6510 ins_encode(simple_form3_mem_reg( mem, src ) );
6511 ins_pipe(fstoreD_mem_reg);
6512 %}
6514 // Convert oop pointer into compressed form
6515 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6516 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6517 match(Set dst (EncodeP src));
6518 format %{ "encode_heap_oop $src, $dst" %}
6519 ins_encode %{
6520 __ encode_heap_oop($src$$Register, $dst$$Register);
6521 %}
6522 ins_pipe(ialu_reg);
6523 %}
6525 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6526 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6527 match(Set dst (EncodeP src));
6528 format %{ "encode_heap_oop_not_null $src, $dst" %}
6529 ins_encode %{
6530 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6531 %}
6532 ins_pipe(ialu_reg);
6533 %}
6535 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6536 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6537 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6538 match(Set dst (DecodeN src));
6539 format %{ "decode_heap_oop $src, $dst" %}
6540 ins_encode %{
6541 __ decode_heap_oop($src$$Register, $dst$$Register);
6542 %}
6543 ins_pipe(ialu_reg);
6544 %}
6546 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6547 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6548 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6549 match(Set dst (DecodeN src));
6550 format %{ "decode_heap_oop_not_null $src, $dst" %}
6551 ins_encode %{
6552 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6553 %}
6554 ins_pipe(ialu_reg);
6555 %}
6558 // Store Zero into Aligned Packed Bytes
6559 instruct storeA8B0(memory mem, immI0 zero) %{
6560 match(Set mem (Store8B mem zero));
6561 ins_cost(MEMORY_REF_COST);
6562 size(4);
6563 format %{ "STX $zero,$mem\t! packed8B" %}
6564 opcode(Assembler::stx_op3);
6565 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6566 ins_pipe(fstoreD_mem_zero);
6567 %}
6569 // Store Aligned Packed Chars/Shorts in Double register to memory
6570 instruct storeA4C(memory mem, regD src) %{
6571 match(Set mem (Store4C mem src));
6572 ins_cost(MEMORY_REF_COST);
6573 size(4);
6574 format %{ "STDF $src,$mem\t! packed4C" %}
6575 opcode(Assembler::stdf_op3);
6576 ins_encode(simple_form3_mem_reg( mem, src ) );
6577 ins_pipe(fstoreD_mem_reg);
6578 %}
6580 // Store Zero into Aligned Packed Chars/Shorts
6581 instruct storeA4C0(memory mem, immI0 zero) %{
6582 match(Set mem (Store4C mem (Replicate4C zero)));
6583 ins_cost(MEMORY_REF_COST);
6584 size(4);
6585 format %{ "STX $zero,$mem\t! packed4C" %}
6586 opcode(Assembler::stx_op3);
6587 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6588 ins_pipe(fstoreD_mem_zero);
6589 %}
6591 // Store Aligned Packed Ints in Double register to memory
6592 instruct storeA2I(memory mem, regD src) %{
6593 match(Set mem (Store2I mem src));
6594 ins_cost(MEMORY_REF_COST);
6595 size(4);
6596 format %{ "STDF $src,$mem\t! packed2I" %}
6597 opcode(Assembler::stdf_op3);
6598 ins_encode(simple_form3_mem_reg( mem, src ) );
6599 ins_pipe(fstoreD_mem_reg);
6600 %}
6602 // Store Zero into Aligned Packed Ints
6603 instruct storeA2I0(memory mem, immI0 zero) %{
6604 match(Set mem (Store2I mem zero));
6605 ins_cost(MEMORY_REF_COST);
6606 size(4);
6607 format %{ "STX $zero,$mem\t! packed2I" %}
6608 opcode(Assembler::stx_op3);
6609 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6610 ins_pipe(fstoreD_mem_zero);
6611 %}
6614 //----------MemBar Instructions-----------------------------------------------
6615 // Memory barrier flavors
6617 instruct membar_acquire() %{
6618 match(MemBarAcquire);
6619 ins_cost(4*MEMORY_REF_COST);
6621 size(0);
6622 format %{ "MEMBAR-acquire" %}
6623 ins_encode( enc_membar_acquire );
6624 ins_pipe(long_memory_op);
6625 %}
6627 instruct membar_acquire_lock() %{
6628 match(MemBarAcquire);
6629 predicate(Matcher::prior_fast_lock(n));
6630 ins_cost(0);
6632 size(0);
6633 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6634 ins_encode( );
6635 ins_pipe(empty);
6636 %}
6638 instruct membar_release() %{
6639 match(MemBarRelease);
6640 ins_cost(4*MEMORY_REF_COST);
6642 size(0);
6643 format %{ "MEMBAR-release" %}
6644 ins_encode( enc_membar_release );
6645 ins_pipe(long_memory_op);
6646 %}
6648 instruct membar_release_lock() %{
6649 match(MemBarRelease);
6650 predicate(Matcher::post_fast_unlock(n));
6651 ins_cost(0);
6653 size(0);
6654 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6655 ins_encode( );
6656 ins_pipe(empty);
6657 %}
6659 instruct membar_volatile() %{
6660 match(MemBarVolatile);
6661 ins_cost(4*MEMORY_REF_COST);
6663 size(4);
6664 format %{ "MEMBAR-volatile" %}
6665 ins_encode( enc_membar_volatile );
6666 ins_pipe(long_memory_op);
6667 %}
6669 instruct unnecessary_membar_volatile() %{
6670 match(MemBarVolatile);
6671 predicate(Matcher::post_store_load_barrier(n));
6672 ins_cost(0);
6674 size(0);
6675 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6676 ins_encode( );
6677 ins_pipe(empty);
6678 %}
6680 //----------Register Move Instructions-----------------------------------------
6681 instruct roundDouble_nop(regD dst) %{
6682 match(Set dst (RoundDouble dst));
6683 ins_cost(0);
6684 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6685 ins_encode( );
6686 ins_pipe(empty);
6687 %}
6690 instruct roundFloat_nop(regF dst) %{
6691 match(Set dst (RoundFloat dst));
6692 ins_cost(0);
6693 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6694 ins_encode( );
6695 ins_pipe(empty);
6696 %}
6699 // Cast Index to Pointer for unsafe natives
6700 instruct castX2P(iRegX src, iRegP dst) %{
6701 match(Set dst (CastX2P src));
6703 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6704 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6705 ins_pipe(ialu_reg);
6706 %}
6708 // Cast Pointer to Index for unsafe natives
6709 instruct castP2X(iRegP src, iRegX dst) %{
6710 match(Set dst (CastP2X src));
6712 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6713 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6714 ins_pipe(ialu_reg);
6715 %}
6717 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6718 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6719 match(Set stkSlot src); // chain rule
6720 ins_cost(MEMORY_REF_COST);
6721 format %{ "STDF $src,$stkSlot\t!stk" %}
6722 opcode(Assembler::stdf_op3);
6723 ins_encode(simple_form3_mem_reg(stkSlot, src));
6724 ins_pipe(fstoreD_stk_reg);
6725 %}
6727 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6728 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6729 match(Set dst stkSlot); // chain rule
6730 ins_cost(MEMORY_REF_COST);
6731 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6732 opcode(Assembler::lddf_op3);
6733 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6734 ins_pipe(floadD_stk);
6735 %}
6737 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6738 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6739 match(Set stkSlot src); // chain rule
6740 ins_cost(MEMORY_REF_COST);
6741 format %{ "STF $src,$stkSlot\t!stk" %}
6742 opcode(Assembler::stf_op3);
6743 ins_encode(simple_form3_mem_reg(stkSlot, src));
6744 ins_pipe(fstoreF_stk_reg);
6745 %}
6747 //----------Conditional Move---------------------------------------------------
6748 // Conditional move
6749 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6750 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6751 ins_cost(150);
6752 format %{ "MOV$cmp $pcc,$src,$dst" %}
6753 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6754 ins_pipe(ialu_reg);
6755 %}
6757 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6758 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6759 ins_cost(140);
6760 format %{ "MOV$cmp $pcc,$src,$dst" %}
6761 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6762 ins_pipe(ialu_imm);
6763 %}
6765 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6766 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6767 ins_cost(150);
6768 size(4);
6769 format %{ "MOV$cmp $icc,$src,$dst" %}
6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6771 ins_pipe(ialu_reg);
6772 %}
6774 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6775 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6776 ins_cost(140);
6777 size(4);
6778 format %{ "MOV$cmp $icc,$src,$dst" %}
6779 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6780 ins_pipe(ialu_imm);
6781 %}
6783 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6784 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6785 ins_cost(150);
6786 size(4);
6787 format %{ "MOV$cmp $icc,$src,$dst" %}
6788 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6789 ins_pipe(ialu_reg);
6790 %}
6792 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6793 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6794 ins_cost(140);
6795 size(4);
6796 format %{ "MOV$cmp $icc,$src,$dst" %}
6797 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6798 ins_pipe(ialu_imm);
6799 %}
6801 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6802 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6803 ins_cost(150);
6804 size(4);
6805 format %{ "MOV$cmp $fcc,$src,$dst" %}
6806 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6807 ins_pipe(ialu_reg);
6808 %}
6810 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6811 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6812 ins_cost(140);
6813 size(4);
6814 format %{ "MOV$cmp $fcc,$src,$dst" %}
6815 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6816 ins_pipe(ialu_imm);
6817 %}
6819 // Conditional move for RegN. Only cmov(reg,reg).
6820 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6821 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6822 ins_cost(150);
6823 format %{ "MOV$cmp $pcc,$src,$dst" %}
6824 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6825 ins_pipe(ialu_reg);
6826 %}
6828 // This instruction also works with CmpN so we don't need cmovNN_reg.
6829 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6830 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6831 ins_cost(150);
6832 size(4);
6833 format %{ "MOV$cmp $icc,$src,$dst" %}
6834 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6835 ins_pipe(ialu_reg);
6836 %}
6838 // This instruction also works with CmpN so we don't need cmovNN_reg.
6839 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6840 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6841 ins_cost(150);
6842 size(4);
6843 format %{ "MOV$cmp $icc,$src,$dst" %}
6844 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6845 ins_pipe(ialu_reg);
6846 %}
6848 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6849 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6850 ins_cost(150);
6851 size(4);
6852 format %{ "MOV$cmp $fcc,$src,$dst" %}
6853 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6854 ins_pipe(ialu_reg);
6855 %}
6857 // Conditional move
6858 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6859 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6860 ins_cost(150);
6861 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6862 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6863 ins_pipe(ialu_reg);
6864 %}
6866 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6867 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6868 ins_cost(140);
6869 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6870 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6871 ins_pipe(ialu_imm);
6872 %}
6874 // This instruction also works with CmpN so we don't need cmovPN_reg.
6875 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6876 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6877 ins_cost(150);
6879 size(4);
6880 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6881 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6882 ins_pipe(ialu_reg);
6883 %}
6885 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6886 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6887 ins_cost(150);
6889 size(4);
6890 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6891 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6892 ins_pipe(ialu_reg);
6893 %}
6895 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6896 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6897 ins_cost(140);
6899 size(4);
6900 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6901 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6902 ins_pipe(ialu_imm);
6903 %}
6905 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6906 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6907 ins_cost(140);
6909 size(4);
6910 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6911 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6912 ins_pipe(ialu_imm);
6913 %}
6915 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6916 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6917 ins_cost(150);
6918 size(4);
6919 format %{ "MOV$cmp $fcc,$src,$dst" %}
6920 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6921 ins_pipe(ialu_imm);
6922 %}
6924 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6925 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6926 ins_cost(140);
6927 size(4);
6928 format %{ "MOV$cmp $fcc,$src,$dst" %}
6929 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6930 ins_pipe(ialu_imm);
6931 %}
6933 // Conditional move
6934 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6935 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6936 ins_cost(150);
6937 opcode(0x101);
6938 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6939 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6940 ins_pipe(int_conditional_float_move);
6941 %}
6943 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6944 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6945 ins_cost(150);
6947 size(4);
6948 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6949 opcode(0x101);
6950 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6951 ins_pipe(int_conditional_float_move);
6952 %}
6954 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6955 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6956 ins_cost(150);
6958 size(4);
6959 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6960 opcode(0x101);
6961 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6962 ins_pipe(int_conditional_float_move);
6963 %}
6965 // Conditional move,
6966 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6967 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6968 ins_cost(150);
6969 size(4);
6970 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6971 opcode(0x1);
6972 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6973 ins_pipe(int_conditional_double_move);
6974 %}
6976 // Conditional move
6977 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6978 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6979 ins_cost(150);
6980 size(4);
6981 opcode(0x102);
6982 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6983 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6984 ins_pipe(int_conditional_double_move);
6985 %}
6987 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6988 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6989 ins_cost(150);
6991 size(4);
6992 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6993 opcode(0x102);
6994 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6995 ins_pipe(int_conditional_double_move);
6996 %}
6998 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6999 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7000 ins_cost(150);
7002 size(4);
7003 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7004 opcode(0x102);
7005 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7006 ins_pipe(int_conditional_double_move);
7007 %}
7009 // Conditional move,
7010 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7011 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7012 ins_cost(150);
7013 size(4);
7014 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7015 opcode(0x2);
7016 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7017 ins_pipe(int_conditional_double_move);
7018 %}
7020 // Conditional move
7021 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7022 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7023 ins_cost(150);
7024 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7025 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7026 ins_pipe(ialu_reg);
7027 %}
7029 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7030 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7031 ins_cost(140);
7032 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7033 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7034 ins_pipe(ialu_imm);
7035 %}
7037 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7038 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7039 ins_cost(150);
7041 size(4);
7042 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7043 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7044 ins_pipe(ialu_reg);
7045 %}
7048 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7049 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7050 ins_cost(150);
7052 size(4);
7053 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7054 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7055 ins_pipe(ialu_reg);
7056 %}
7059 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7060 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7061 ins_cost(150);
7063 size(4);
7064 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7065 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7066 ins_pipe(ialu_reg);
7067 %}
7071 //----------OS and Locking Instructions----------------------------------------
7073 // This name is KNOWN by the ADLC and cannot be changed.
7074 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7075 // for this guy.
7076 instruct tlsLoadP(g2RegP dst) %{
7077 match(Set dst (ThreadLocal));
7079 size(0);
7080 ins_cost(0);
7081 format %{ "# TLS is in G2" %}
7082 ins_encode( /*empty encoding*/ );
7083 ins_pipe(ialu_none);
7084 %}
7086 instruct checkCastPP( iRegP dst ) %{
7087 match(Set dst (CheckCastPP dst));
7089 size(0);
7090 format %{ "# checkcastPP of $dst" %}
7091 ins_encode( /*empty encoding*/ );
7092 ins_pipe(empty);
7093 %}
7096 instruct castPP( iRegP dst ) %{
7097 match(Set dst (CastPP dst));
7098 format %{ "# castPP of $dst" %}
7099 ins_encode( /*empty encoding*/ );
7100 ins_pipe(empty);
7101 %}
7103 instruct castII( iRegI dst ) %{
7104 match(Set dst (CastII dst));
7105 format %{ "# castII of $dst" %}
7106 ins_encode( /*empty encoding*/ );
7107 ins_cost(0);
7108 ins_pipe(empty);
7109 %}
7111 //----------Arithmetic Instructions--------------------------------------------
7112 // Addition Instructions
7113 // Register Addition
7114 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7115 match(Set dst (AddI src1 src2));
7117 size(4);
7118 format %{ "ADD $src1,$src2,$dst" %}
7119 ins_encode %{
7120 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7121 %}
7122 ins_pipe(ialu_reg_reg);
7123 %}
7125 // Immediate Addition
7126 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7127 match(Set dst (AddI src1 src2));
7129 size(4);
7130 format %{ "ADD $src1,$src2,$dst" %}
7131 opcode(Assembler::add_op3, Assembler::arith_op);
7132 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7133 ins_pipe(ialu_reg_imm);
7134 %}
7136 // Pointer Register Addition
7137 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7138 match(Set dst (AddP src1 src2));
7140 size(4);
7141 format %{ "ADD $src1,$src2,$dst" %}
7142 opcode(Assembler::add_op3, Assembler::arith_op);
7143 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7144 ins_pipe(ialu_reg_reg);
7145 %}
7147 // Pointer Immediate Addition
7148 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7149 match(Set dst (AddP src1 src2));
7151 size(4);
7152 format %{ "ADD $src1,$src2,$dst" %}
7153 opcode(Assembler::add_op3, Assembler::arith_op);
7154 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7155 ins_pipe(ialu_reg_imm);
7156 %}
7158 // Long Addition
7159 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7160 match(Set dst (AddL src1 src2));
7162 size(4);
7163 format %{ "ADD $src1,$src2,$dst\t! long" %}
7164 opcode(Assembler::add_op3, Assembler::arith_op);
7165 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7166 ins_pipe(ialu_reg_reg);
7167 %}
7169 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7170 match(Set dst (AddL src1 con));
7172 size(4);
7173 format %{ "ADD $src1,$con,$dst" %}
7174 opcode(Assembler::add_op3, Assembler::arith_op);
7175 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7176 ins_pipe(ialu_reg_imm);
7177 %}
7179 //----------Conditional_store--------------------------------------------------
7180 // Conditional-store of the updated heap-top.
7181 // Used during allocation of the shared heap.
7182 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7184 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7185 instruct loadPLocked(iRegP dst, memory mem) %{
7186 match(Set dst (LoadPLocked mem));
7187 ins_cost(MEMORY_REF_COST);
7189 #ifndef _LP64
7190 size(4);
7191 format %{ "LDUW $mem,$dst\t! ptr" %}
7192 opcode(Assembler::lduw_op3, 0, REGP_OP);
7193 #else
7194 format %{ "LDX $mem,$dst\t! ptr" %}
7195 opcode(Assembler::ldx_op3, 0, REGP_OP);
7196 #endif
7197 ins_encode( form3_mem_reg( mem, dst ) );
7198 ins_pipe(iload_mem);
7199 %}
7201 // LoadL-locked. Same as a regular long load when used with a compare-swap
7202 instruct loadLLocked(iRegL dst, memory mem) %{
7203 match(Set dst (LoadLLocked mem));
7204 ins_cost(MEMORY_REF_COST);
7205 size(4);
7206 format %{ "LDX $mem,$dst\t! long" %}
7207 opcode(Assembler::ldx_op3);
7208 ins_encode(simple_form3_mem_reg( mem, dst ) );
7209 ins_pipe(iload_mem);
7210 %}
7212 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7213 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7214 effect( KILL newval );
7215 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7216 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7217 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7218 ins_pipe( long_memory_op );
7219 %}
7221 // Conditional-store of an int value.
7222 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7223 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7224 effect( KILL newval );
7225 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7226 "CMP $oldval,$newval\t\t! See if we made progress" %}
7227 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7228 ins_pipe( long_memory_op );
7229 %}
7231 // Conditional-store of a long value.
7232 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7233 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7234 effect( KILL newval );
7235 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7236 "CMP $oldval,$newval\t\t! See if we made progress" %}
7237 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7238 ins_pipe( long_memory_op );
7239 %}
7241 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7243 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7244 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7245 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7246 format %{
7247 "MOV $newval,O7\n\t"
7248 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7249 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7250 "MOV 1,$res\n\t"
7251 "MOVne xcc,R_G0,$res"
7252 %}
7253 ins_encode( enc_casx(mem_ptr, oldval, newval),
7254 enc_lflags_ne_to_boolean(res) );
7255 ins_pipe( long_memory_op );
7256 %}
7259 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7260 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7261 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7262 format %{
7263 "MOV $newval,O7\n\t"
7264 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7265 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7266 "MOV 1,$res\n\t"
7267 "MOVne icc,R_G0,$res"
7268 %}
7269 ins_encode( enc_casi(mem_ptr, oldval, newval),
7270 enc_iflags_ne_to_boolean(res) );
7271 ins_pipe( long_memory_op );
7272 %}
7274 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7275 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7276 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7277 format %{
7278 "MOV $newval,O7\n\t"
7279 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7280 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7281 "MOV 1,$res\n\t"
7282 "MOVne xcc,R_G0,$res"
7283 %}
7284 #ifdef _LP64
7285 ins_encode( enc_casx(mem_ptr, oldval, newval),
7286 enc_lflags_ne_to_boolean(res) );
7287 #else
7288 ins_encode( enc_casi(mem_ptr, oldval, newval),
7289 enc_iflags_ne_to_boolean(res) );
7290 #endif
7291 ins_pipe( long_memory_op );
7292 %}
7294 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7295 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7296 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7297 format %{
7298 "MOV $newval,O7\n\t"
7299 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7300 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7301 "MOV 1,$res\n\t"
7302 "MOVne icc,R_G0,$res"
7303 %}
7304 ins_encode( enc_casi(mem_ptr, oldval, newval),
7305 enc_iflags_ne_to_boolean(res) );
7306 ins_pipe( long_memory_op );
7307 %}
7309 //---------------------
7310 // Subtraction Instructions
7311 // Register Subtraction
7312 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7313 match(Set dst (SubI src1 src2));
7315 size(4);
7316 format %{ "SUB $src1,$src2,$dst" %}
7317 opcode(Assembler::sub_op3, Assembler::arith_op);
7318 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7319 ins_pipe(ialu_reg_reg);
7320 %}
7322 // Immediate Subtraction
7323 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7324 match(Set dst (SubI src1 src2));
7326 size(4);
7327 format %{ "SUB $src1,$src2,$dst" %}
7328 opcode(Assembler::sub_op3, Assembler::arith_op);
7329 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7330 ins_pipe(ialu_reg_imm);
7331 %}
7333 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7334 match(Set dst (SubI zero src2));
7336 size(4);
7337 format %{ "NEG $src2,$dst" %}
7338 opcode(Assembler::sub_op3, Assembler::arith_op);
7339 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7340 ins_pipe(ialu_zero_reg);
7341 %}
7343 // Long subtraction
7344 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7345 match(Set dst (SubL src1 src2));
7347 size(4);
7348 format %{ "SUB $src1,$src2,$dst\t! long" %}
7349 opcode(Assembler::sub_op3, Assembler::arith_op);
7350 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7351 ins_pipe(ialu_reg_reg);
7352 %}
7354 // Immediate Subtraction
7355 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7356 match(Set dst (SubL src1 con));
7358 size(4);
7359 format %{ "SUB $src1,$con,$dst\t! long" %}
7360 opcode(Assembler::sub_op3, Assembler::arith_op);
7361 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7362 ins_pipe(ialu_reg_imm);
7363 %}
7365 // Long negation
7366 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7367 match(Set dst (SubL zero src2));
7369 size(4);
7370 format %{ "NEG $src2,$dst\t! long" %}
7371 opcode(Assembler::sub_op3, Assembler::arith_op);
7372 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7373 ins_pipe(ialu_zero_reg);
7374 %}
7376 // Multiplication Instructions
7377 // Integer Multiplication
7378 // Register Multiplication
7379 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7380 match(Set dst (MulI src1 src2));
7382 size(4);
7383 format %{ "MULX $src1,$src2,$dst" %}
7384 opcode(Assembler::mulx_op3, Assembler::arith_op);
7385 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7386 ins_pipe(imul_reg_reg);
7387 %}
7389 // Immediate Multiplication
7390 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7391 match(Set dst (MulI src1 src2));
7393 size(4);
7394 format %{ "MULX $src1,$src2,$dst" %}
7395 opcode(Assembler::mulx_op3, Assembler::arith_op);
7396 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7397 ins_pipe(imul_reg_imm);
7398 %}
7400 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7401 match(Set dst (MulL src1 src2));
7402 ins_cost(DEFAULT_COST * 5);
7403 size(4);
7404 format %{ "MULX $src1,$src2,$dst\t! long" %}
7405 opcode(Assembler::mulx_op3, Assembler::arith_op);
7406 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7407 ins_pipe(mulL_reg_reg);
7408 %}
7410 // Immediate Multiplication
7411 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7412 match(Set dst (MulL src1 src2));
7413 ins_cost(DEFAULT_COST * 5);
7414 size(4);
7415 format %{ "MULX $src1,$src2,$dst" %}
7416 opcode(Assembler::mulx_op3, Assembler::arith_op);
7417 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7418 ins_pipe(mulL_reg_imm);
7419 %}
7421 // Integer Division
7422 // Register Division
7423 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7424 match(Set dst (DivI src1 src2));
7425 ins_cost((2+71)*DEFAULT_COST);
7427 format %{ "SRA $src2,0,$src2\n\t"
7428 "SRA $src1,0,$src1\n\t"
7429 "SDIVX $src1,$src2,$dst" %}
7430 ins_encode( idiv_reg( src1, src2, dst ) );
7431 ins_pipe(sdiv_reg_reg);
7432 %}
7434 // Immediate Division
7435 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7436 match(Set dst (DivI src1 src2));
7437 ins_cost((2+71)*DEFAULT_COST);
7439 format %{ "SRA $src1,0,$src1\n\t"
7440 "SDIVX $src1,$src2,$dst" %}
7441 ins_encode( idiv_imm( src1, src2, dst ) );
7442 ins_pipe(sdiv_reg_imm);
7443 %}
7445 //----------Div-By-10-Expansion------------------------------------------------
7446 // Extract hi bits of a 32x32->64 bit multiply.
7447 // Expand rule only, not matched
7448 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7449 effect( DEF dst, USE src1, USE src2 );
7450 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7451 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7452 ins_encode( enc_mul_hi(dst,src1,src2));
7453 ins_pipe(sdiv_reg_reg);
7454 %}
7456 // Magic constant, reciprocal of 10
7457 instruct loadConI_x66666667(iRegIsafe dst) %{
7458 effect( DEF dst );
7460 size(8);
7461 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7462 ins_encode( Set32(0x66666667, dst) );
7463 ins_pipe(ialu_hi_lo_reg);
7464 %}
7466 // Register Shift Right Arithmetic Long by 32-63
7467 instruct sra_31( iRegI dst, iRegI src ) %{
7468 effect( DEF dst, USE src );
7469 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7470 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7471 ins_pipe(ialu_reg_reg);
7472 %}
7474 // Arithmetic Shift Right by 8-bit immediate
7475 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7476 effect( DEF dst, USE src );
7477 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7478 opcode(Assembler::sra_op3, Assembler::arith_op);
7479 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7480 ins_pipe(ialu_reg_imm);
7481 %}
7483 // Integer DIV with 10
7484 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7485 match(Set dst (DivI src div));
7486 ins_cost((6+6)*DEFAULT_COST);
7487 expand %{
7488 iRegIsafe tmp1; // Killed temps;
7489 iRegIsafe tmp2; // Killed temps;
7490 iRegI tmp3; // Killed temps;
7491 iRegI tmp4; // Killed temps;
7492 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7493 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7494 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7495 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7496 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7497 %}
7498 %}
7500 // Register Long Division
7501 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7502 match(Set dst (DivL src1 src2));
7503 ins_cost(DEFAULT_COST*71);
7504 size(4);
7505 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7506 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7507 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7508 ins_pipe(divL_reg_reg);
7509 %}
7511 // Register Long Division
7512 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7513 match(Set dst (DivL src1 src2));
7514 ins_cost(DEFAULT_COST*71);
7515 size(4);
7516 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7517 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7518 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7519 ins_pipe(divL_reg_imm);
7520 %}
7522 // Integer Remainder
7523 // Register Remainder
7524 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7525 match(Set dst (ModI src1 src2));
7526 effect( KILL ccr, KILL temp);
7528 format %{ "SREM $src1,$src2,$dst" %}
7529 ins_encode( irem_reg(src1, src2, dst, temp) );
7530 ins_pipe(sdiv_reg_reg);
7531 %}
7533 // Immediate Remainder
7534 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7535 match(Set dst (ModI src1 src2));
7536 effect( KILL ccr, KILL temp);
7538 format %{ "SREM $src1,$src2,$dst" %}
7539 ins_encode( irem_imm(src1, src2, dst, temp) );
7540 ins_pipe(sdiv_reg_imm);
7541 %}
7543 // Register Long Remainder
7544 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7545 effect(DEF dst, USE src1, USE src2);
7546 size(4);
7547 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7548 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7549 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7550 ins_pipe(divL_reg_reg);
7551 %}
7553 // Register Long Division
7554 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7555 effect(DEF dst, USE src1, USE src2);
7556 size(4);
7557 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7558 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7559 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7560 ins_pipe(divL_reg_imm);
7561 %}
7563 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7564 effect(DEF dst, USE src1, USE src2);
7565 size(4);
7566 format %{ "MULX $src1,$src2,$dst\t! long" %}
7567 opcode(Assembler::mulx_op3, Assembler::arith_op);
7568 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7569 ins_pipe(mulL_reg_reg);
7570 %}
7572 // Immediate Multiplication
7573 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7574 effect(DEF dst, USE src1, USE src2);
7575 size(4);
7576 format %{ "MULX $src1,$src2,$dst" %}
7577 opcode(Assembler::mulx_op3, Assembler::arith_op);
7578 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7579 ins_pipe(mulL_reg_imm);
7580 %}
7582 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7583 effect(DEF dst, USE src1, USE src2);
7584 size(4);
7585 format %{ "SUB $src1,$src2,$dst\t! long" %}
7586 opcode(Assembler::sub_op3, Assembler::arith_op);
7587 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7588 ins_pipe(ialu_reg_reg);
7589 %}
7591 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7592 effect(DEF dst, USE src1, USE src2);
7593 size(4);
7594 format %{ "SUB $src1,$src2,$dst\t! long" %}
7595 opcode(Assembler::sub_op3, Assembler::arith_op);
7596 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7597 ins_pipe(ialu_reg_reg);
7598 %}
7600 // Register Long Remainder
7601 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7602 match(Set dst (ModL src1 src2));
7603 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7604 expand %{
7605 iRegL tmp1;
7606 iRegL tmp2;
7607 divL_reg_reg_1(tmp1, src1, src2);
7608 mulL_reg_reg_1(tmp2, tmp1, src2);
7609 subL_reg_reg_1(dst, src1, tmp2);
7610 %}
7611 %}
7613 // Register Long Remainder
7614 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7615 match(Set dst (ModL src1 src2));
7616 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7617 expand %{
7618 iRegL tmp1;
7619 iRegL tmp2;
7620 divL_reg_imm13_1(tmp1, src1, src2);
7621 mulL_reg_imm13_1(tmp2, tmp1, src2);
7622 subL_reg_reg_2 (dst, src1, tmp2);
7623 %}
7624 %}
7626 // Integer Shift Instructions
7627 // Register Shift Left
7628 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7629 match(Set dst (LShiftI src1 src2));
7631 size(4);
7632 format %{ "SLL $src1,$src2,$dst" %}
7633 opcode(Assembler::sll_op3, Assembler::arith_op);
7634 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7635 ins_pipe(ialu_reg_reg);
7636 %}
7638 // Register Shift Left Immediate
7639 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7640 match(Set dst (LShiftI src1 src2));
7642 size(4);
7643 format %{ "SLL $src1,$src2,$dst" %}
7644 opcode(Assembler::sll_op3, Assembler::arith_op);
7645 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7646 ins_pipe(ialu_reg_imm);
7647 %}
7649 // Register Shift Left
7650 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7651 match(Set dst (LShiftL src1 src2));
7653 size(4);
7654 format %{ "SLLX $src1,$src2,$dst" %}
7655 opcode(Assembler::sllx_op3, Assembler::arith_op);
7656 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7657 ins_pipe(ialu_reg_reg);
7658 %}
7660 // Register Shift Left Immediate
7661 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7662 match(Set dst (LShiftL src1 src2));
7664 size(4);
7665 format %{ "SLLX $src1,$src2,$dst" %}
7666 opcode(Assembler::sllx_op3, Assembler::arith_op);
7667 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7668 ins_pipe(ialu_reg_imm);
7669 %}
7671 // Register Arithmetic Shift Right
7672 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7673 match(Set dst (RShiftI src1 src2));
7674 size(4);
7675 format %{ "SRA $src1,$src2,$dst" %}
7676 opcode(Assembler::sra_op3, Assembler::arith_op);
7677 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7678 ins_pipe(ialu_reg_reg);
7679 %}
7681 // Register Arithmetic Shift Right Immediate
7682 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7683 match(Set dst (RShiftI src1 src2));
7685 size(4);
7686 format %{ "SRA $src1,$src2,$dst" %}
7687 opcode(Assembler::sra_op3, Assembler::arith_op);
7688 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7689 ins_pipe(ialu_reg_imm);
7690 %}
7692 // Register Shift Right Arithmatic Long
7693 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7694 match(Set dst (RShiftL src1 src2));
7696 size(4);
7697 format %{ "SRAX $src1,$src2,$dst" %}
7698 opcode(Assembler::srax_op3, Assembler::arith_op);
7699 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7700 ins_pipe(ialu_reg_reg);
7701 %}
7703 // Register Shift Left Immediate
7704 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7705 match(Set dst (RShiftL src1 src2));
7707 size(4);
7708 format %{ "SRAX $src1,$src2,$dst" %}
7709 opcode(Assembler::srax_op3, Assembler::arith_op);
7710 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7711 ins_pipe(ialu_reg_imm);
7712 %}
7714 // Register Shift Right
7715 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7716 match(Set dst (URShiftI src1 src2));
7718 size(4);
7719 format %{ "SRL $src1,$src2,$dst" %}
7720 opcode(Assembler::srl_op3, Assembler::arith_op);
7721 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7722 ins_pipe(ialu_reg_reg);
7723 %}
7725 // Register Shift Right Immediate
7726 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7727 match(Set dst (URShiftI src1 src2));
7729 size(4);
7730 format %{ "SRL $src1,$src2,$dst" %}
7731 opcode(Assembler::srl_op3, Assembler::arith_op);
7732 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7733 ins_pipe(ialu_reg_imm);
7734 %}
7736 // Register Shift Right
7737 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7738 match(Set dst (URShiftL src1 src2));
7740 size(4);
7741 format %{ "SRLX $src1,$src2,$dst" %}
7742 opcode(Assembler::srlx_op3, Assembler::arith_op);
7743 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7744 ins_pipe(ialu_reg_reg);
7745 %}
7747 // Register Shift Right Immediate
7748 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7749 match(Set dst (URShiftL src1 src2));
7751 size(4);
7752 format %{ "SRLX $src1,$src2,$dst" %}
7753 opcode(Assembler::srlx_op3, Assembler::arith_op);
7754 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7755 ins_pipe(ialu_reg_imm);
7756 %}
7758 // Register Shift Right Immediate with a CastP2X
7759 #ifdef _LP64
7760 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7761 match(Set dst (URShiftL (CastP2X src1) src2));
7762 size(4);
7763 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7764 opcode(Assembler::srlx_op3, Assembler::arith_op);
7765 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7766 ins_pipe(ialu_reg_imm);
7767 %}
7768 #else
7769 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7770 match(Set dst (URShiftI (CastP2X src1) src2));
7771 size(4);
7772 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7773 opcode(Assembler::srl_op3, Assembler::arith_op);
7774 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7775 ins_pipe(ialu_reg_imm);
7776 %}
7777 #endif
7780 //----------Floating Point Arithmetic Instructions-----------------------------
7782 // Add float single precision
7783 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7784 match(Set dst (AddF src1 src2));
7786 size(4);
7787 format %{ "FADDS $src1,$src2,$dst" %}
7788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7789 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7790 ins_pipe(faddF_reg_reg);
7791 %}
7793 // Add float double precision
7794 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7795 match(Set dst (AddD src1 src2));
7797 size(4);
7798 format %{ "FADDD $src1,$src2,$dst" %}
7799 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7800 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7801 ins_pipe(faddD_reg_reg);
7802 %}
7804 // Sub float single precision
7805 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7806 match(Set dst (SubF src1 src2));
7808 size(4);
7809 format %{ "FSUBS $src1,$src2,$dst" %}
7810 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7811 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7812 ins_pipe(faddF_reg_reg);
7813 %}
7815 // Sub float double precision
7816 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7817 match(Set dst (SubD src1 src2));
7819 size(4);
7820 format %{ "FSUBD $src1,$src2,$dst" %}
7821 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7822 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7823 ins_pipe(faddD_reg_reg);
7824 %}
7826 // Mul float single precision
7827 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7828 match(Set dst (MulF src1 src2));
7830 size(4);
7831 format %{ "FMULS $src1,$src2,$dst" %}
7832 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7833 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7834 ins_pipe(fmulF_reg_reg);
7835 %}
7837 // Mul float double precision
7838 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7839 match(Set dst (MulD src1 src2));
7841 size(4);
7842 format %{ "FMULD $src1,$src2,$dst" %}
7843 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7844 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7845 ins_pipe(fmulD_reg_reg);
7846 %}
7848 // Div float single precision
7849 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7850 match(Set dst (DivF src1 src2));
7852 size(4);
7853 format %{ "FDIVS $src1,$src2,$dst" %}
7854 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7855 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7856 ins_pipe(fdivF_reg_reg);
7857 %}
7859 // Div float double precision
7860 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7861 match(Set dst (DivD src1 src2));
7863 size(4);
7864 format %{ "FDIVD $src1,$src2,$dst" %}
7865 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7866 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7867 ins_pipe(fdivD_reg_reg);
7868 %}
7870 // Absolute float double precision
7871 instruct absD_reg(regD dst, regD src) %{
7872 match(Set dst (AbsD src));
7874 format %{ "FABSd $src,$dst" %}
7875 ins_encode(fabsd(dst, src));
7876 ins_pipe(faddD_reg);
7877 %}
7879 // Absolute float single precision
7880 instruct absF_reg(regF dst, regF src) %{
7881 match(Set dst (AbsF src));
7883 format %{ "FABSs $src,$dst" %}
7884 ins_encode(fabss(dst, src));
7885 ins_pipe(faddF_reg);
7886 %}
7888 instruct negF_reg(regF dst, regF src) %{
7889 match(Set dst (NegF src));
7891 size(4);
7892 format %{ "FNEGs $src,$dst" %}
7893 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7894 ins_encode(form3_opf_rs2F_rdF(src, dst));
7895 ins_pipe(faddF_reg);
7896 %}
7898 instruct negD_reg(regD dst, regD src) %{
7899 match(Set dst (NegD src));
7901 format %{ "FNEGd $src,$dst" %}
7902 ins_encode(fnegd(dst, src));
7903 ins_pipe(faddD_reg);
7904 %}
7906 // Sqrt float double precision
7907 instruct sqrtF_reg_reg(regF dst, regF src) %{
7908 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7910 size(4);
7911 format %{ "FSQRTS $src,$dst" %}
7912 ins_encode(fsqrts(dst, src));
7913 ins_pipe(fdivF_reg_reg);
7914 %}
7916 // Sqrt float double precision
7917 instruct sqrtD_reg_reg(regD dst, regD src) %{
7918 match(Set dst (SqrtD src));
7920 size(4);
7921 format %{ "FSQRTD $src,$dst" %}
7922 ins_encode(fsqrtd(dst, src));
7923 ins_pipe(fdivD_reg_reg);
7924 %}
7926 //----------Logical Instructions-----------------------------------------------
7927 // And Instructions
7928 // Register And
7929 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7930 match(Set dst (AndI src1 src2));
7932 size(4);
7933 format %{ "AND $src1,$src2,$dst" %}
7934 opcode(Assembler::and_op3, Assembler::arith_op);
7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7936 ins_pipe(ialu_reg_reg);
7937 %}
7939 // Immediate And
7940 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7941 match(Set dst (AndI src1 src2));
7943 size(4);
7944 format %{ "AND $src1,$src2,$dst" %}
7945 opcode(Assembler::and_op3, Assembler::arith_op);
7946 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7947 ins_pipe(ialu_reg_imm);
7948 %}
7950 // Register And Long
7951 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7952 match(Set dst (AndL src1 src2));
7954 ins_cost(DEFAULT_COST);
7955 size(4);
7956 format %{ "AND $src1,$src2,$dst\t! long" %}
7957 opcode(Assembler::and_op3, Assembler::arith_op);
7958 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7959 ins_pipe(ialu_reg_reg);
7960 %}
7962 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7963 match(Set dst (AndL src1 con));
7965 ins_cost(DEFAULT_COST);
7966 size(4);
7967 format %{ "AND $src1,$con,$dst\t! long" %}
7968 opcode(Assembler::and_op3, Assembler::arith_op);
7969 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7970 ins_pipe(ialu_reg_imm);
7971 %}
7973 // Or Instructions
7974 // Register Or
7975 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7976 match(Set dst (OrI src1 src2));
7978 size(4);
7979 format %{ "OR $src1,$src2,$dst" %}
7980 opcode(Assembler::or_op3, Assembler::arith_op);
7981 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7982 ins_pipe(ialu_reg_reg);
7983 %}
7985 // Immediate Or
7986 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7987 match(Set dst (OrI src1 src2));
7989 size(4);
7990 format %{ "OR $src1,$src2,$dst" %}
7991 opcode(Assembler::or_op3, Assembler::arith_op);
7992 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7993 ins_pipe(ialu_reg_imm);
7994 %}
7996 // Register Or Long
7997 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7998 match(Set dst (OrL src1 src2));
8000 ins_cost(DEFAULT_COST);
8001 size(4);
8002 format %{ "OR $src1,$src2,$dst\t! long" %}
8003 opcode(Assembler::or_op3, Assembler::arith_op);
8004 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8005 ins_pipe(ialu_reg_reg);
8006 %}
8008 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8009 match(Set dst (OrL src1 con));
8010 ins_cost(DEFAULT_COST*2);
8012 ins_cost(DEFAULT_COST);
8013 size(4);
8014 format %{ "OR $src1,$con,$dst\t! long" %}
8015 opcode(Assembler::or_op3, Assembler::arith_op);
8016 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8017 ins_pipe(ialu_reg_imm);
8018 %}
8020 #ifndef _LP64
8022 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8023 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8024 match(Set dst (OrI src1 (CastP2X src2)));
8026 size(4);
8027 format %{ "OR $src1,$src2,$dst" %}
8028 opcode(Assembler::or_op3, Assembler::arith_op);
8029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8030 ins_pipe(ialu_reg_reg);
8031 %}
8033 #else
8035 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8036 match(Set dst (OrL src1 (CastP2X src2)));
8038 ins_cost(DEFAULT_COST);
8039 size(4);
8040 format %{ "OR $src1,$src2,$dst\t! long" %}
8041 opcode(Assembler::or_op3, Assembler::arith_op);
8042 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8043 ins_pipe(ialu_reg_reg);
8044 %}
8046 #endif
8048 // Xor Instructions
8049 // Register Xor
8050 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8051 match(Set dst (XorI src1 src2));
8053 size(4);
8054 format %{ "XOR $src1,$src2,$dst" %}
8055 opcode(Assembler::xor_op3, Assembler::arith_op);
8056 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8057 ins_pipe(ialu_reg_reg);
8058 %}
8060 // Immediate Xor
8061 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8062 match(Set dst (XorI src1 src2));
8064 size(4);
8065 format %{ "XOR $src1,$src2,$dst" %}
8066 opcode(Assembler::xor_op3, Assembler::arith_op);
8067 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8068 ins_pipe(ialu_reg_imm);
8069 %}
8071 // Register Xor Long
8072 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8073 match(Set dst (XorL src1 src2));
8075 ins_cost(DEFAULT_COST);
8076 size(4);
8077 format %{ "XOR $src1,$src2,$dst\t! long" %}
8078 opcode(Assembler::xor_op3, Assembler::arith_op);
8079 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8080 ins_pipe(ialu_reg_reg);
8081 %}
8083 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8084 match(Set dst (XorL src1 con));
8086 ins_cost(DEFAULT_COST);
8087 size(4);
8088 format %{ "XOR $src1,$con,$dst\t! long" %}
8089 opcode(Assembler::xor_op3, Assembler::arith_op);
8090 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8091 ins_pipe(ialu_reg_imm);
8092 %}
8094 //----------Convert to Boolean-------------------------------------------------
8095 // Nice hack for 32-bit tests but doesn't work for
8096 // 64-bit pointers.
8097 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8098 match(Set dst (Conv2B src));
8099 effect( KILL ccr );
8100 ins_cost(DEFAULT_COST*2);
8101 format %{ "CMP R_G0,$src\n\t"
8102 "ADDX R_G0,0,$dst" %}
8103 ins_encode( enc_to_bool( src, dst ) );
8104 ins_pipe(ialu_reg_ialu);
8105 %}
8107 #ifndef _LP64
8108 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8109 match(Set dst (Conv2B src));
8110 effect( KILL ccr );
8111 ins_cost(DEFAULT_COST*2);
8112 format %{ "CMP R_G0,$src\n\t"
8113 "ADDX R_G0,0,$dst" %}
8114 ins_encode( enc_to_bool( src, dst ) );
8115 ins_pipe(ialu_reg_ialu);
8116 %}
8117 #else
8118 instruct convP2B( iRegI dst, iRegP src ) %{
8119 match(Set dst (Conv2B src));
8120 ins_cost(DEFAULT_COST*2);
8121 format %{ "MOV $src,$dst\n\t"
8122 "MOVRNZ $src,1,$dst" %}
8123 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8124 ins_pipe(ialu_clr_and_mover);
8125 %}
8126 #endif
8128 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8129 match(Set dst (CmpLTMask src zero));
8130 effect(KILL ccr);
8131 size(4);
8132 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8133 ins_encode %{
8134 __ sra($src$$Register, 31, $dst$$Register);
8135 %}
8136 ins_pipe(ialu_reg_imm);
8137 %}
8139 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8140 match(Set dst (CmpLTMask p q));
8141 effect( KILL ccr );
8142 ins_cost(DEFAULT_COST*4);
8143 format %{ "CMP $p,$q\n\t"
8144 "MOV #0,$dst\n\t"
8145 "BLT,a .+8\n\t"
8146 "MOV #-1,$dst" %}
8147 ins_encode( enc_ltmask(p,q,dst) );
8148 ins_pipe(ialu_reg_reg_ialu);
8149 %}
8151 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8152 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8153 effect(KILL ccr, TEMP tmp);
8154 ins_cost(DEFAULT_COST*3);
8156 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8157 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8158 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8159 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8160 ins_pipe( cadd_cmpltmask );
8161 %}
8163 //----------Arithmetic Conversion Instructions---------------------------------
8164 // The conversions operations are all Alpha sorted. Please keep it that way!
8166 instruct convD2F_reg(regF dst, regD src) %{
8167 match(Set dst (ConvD2F src));
8168 size(4);
8169 format %{ "FDTOS $src,$dst" %}
8170 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8171 ins_encode(form3_opf_rs2D_rdF(src, dst));
8172 ins_pipe(fcvtD2F);
8173 %}
8176 // Convert a double to an int in a float register.
8177 // If the double is a NAN, stuff a zero in instead.
8178 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8179 effect(DEF dst, USE src, KILL fcc0);
8180 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8181 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8182 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8183 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8184 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8185 "skip:" %}
8186 ins_encode(form_d2i_helper(src,dst));
8187 ins_pipe(fcvtD2I);
8188 %}
8190 instruct convD2I_reg(stackSlotI dst, regD src) %{
8191 match(Set dst (ConvD2I src));
8192 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8193 expand %{
8194 regF tmp;
8195 convD2I_helper(tmp, src);
8196 regF_to_stkI(dst, tmp);
8197 %}
8198 %}
8200 // Convert a double to a long in a double register.
8201 // If the double is a NAN, stuff a zero in instead.
8202 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8203 effect(DEF dst, USE src, KILL fcc0);
8204 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8205 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8206 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8207 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8208 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8209 "skip:" %}
8210 ins_encode(form_d2l_helper(src,dst));
8211 ins_pipe(fcvtD2L);
8212 %}
8215 // Double to Long conversion
8216 instruct convD2L_reg(stackSlotL dst, regD src) %{
8217 match(Set dst (ConvD2L src));
8218 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8219 expand %{
8220 regD tmp;
8221 convD2L_helper(tmp, src);
8222 regD_to_stkL(dst, tmp);
8223 %}
8224 %}
8227 instruct convF2D_reg(regD dst, regF src) %{
8228 match(Set dst (ConvF2D src));
8229 format %{ "FSTOD $src,$dst" %}
8230 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8231 ins_encode(form3_opf_rs2F_rdD(src, dst));
8232 ins_pipe(fcvtF2D);
8233 %}
8236 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8237 effect(DEF dst, USE src, KILL fcc0);
8238 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8239 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8240 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8241 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8242 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8243 "skip:" %}
8244 ins_encode(form_f2i_helper(src,dst));
8245 ins_pipe(fcvtF2I);
8246 %}
8248 instruct convF2I_reg(stackSlotI dst, regF src) %{
8249 match(Set dst (ConvF2I src));
8250 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8251 expand %{
8252 regF tmp;
8253 convF2I_helper(tmp, src);
8254 regF_to_stkI(dst, tmp);
8255 %}
8256 %}
8259 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8260 effect(DEF dst, USE src, KILL fcc0);
8261 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8262 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8263 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8264 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8265 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8266 "skip:" %}
8267 ins_encode(form_f2l_helper(src,dst));
8268 ins_pipe(fcvtF2L);
8269 %}
8271 // Float to Long conversion
8272 instruct convF2L_reg(stackSlotL dst, regF src) %{
8273 match(Set dst (ConvF2L src));
8274 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8275 expand %{
8276 regD tmp;
8277 convF2L_helper(tmp, src);
8278 regD_to_stkL(dst, tmp);
8279 %}
8280 %}
8283 instruct convI2D_helper(regD dst, regF tmp) %{
8284 effect(USE tmp, DEF dst);
8285 format %{ "FITOD $tmp,$dst" %}
8286 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8287 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8288 ins_pipe(fcvtI2D);
8289 %}
8291 instruct convI2D_reg(stackSlotI src, regD dst) %{
8292 match(Set dst (ConvI2D src));
8293 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8294 expand %{
8295 regF tmp;
8296 stkI_to_regF( tmp, src);
8297 convI2D_helper( dst, tmp);
8298 %}
8299 %}
8301 instruct convI2D_mem( regD_low dst, memory mem ) %{
8302 match(Set dst (ConvI2D (LoadI mem)));
8303 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8304 size(8);
8305 format %{ "LDF $mem,$dst\n\t"
8306 "FITOD $dst,$dst" %}
8307 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8308 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8309 ins_pipe(floadF_mem);
8310 %}
8313 instruct convI2F_helper(regF dst, regF tmp) %{
8314 effect(DEF dst, USE tmp);
8315 format %{ "FITOS $tmp,$dst" %}
8316 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8317 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8318 ins_pipe(fcvtI2F);
8319 %}
8321 instruct convI2F_reg( regF dst, stackSlotI src ) %{
8322 match(Set dst (ConvI2F src));
8323 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8324 expand %{
8325 regF tmp;
8326 stkI_to_regF(tmp,src);
8327 convI2F_helper(dst, tmp);
8328 %}
8329 %}
8331 instruct convI2F_mem( regF dst, memory mem ) %{
8332 match(Set dst (ConvI2F (LoadI mem)));
8333 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8334 size(8);
8335 format %{ "LDF $mem,$dst\n\t"
8336 "FITOS $dst,$dst" %}
8337 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8338 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8339 ins_pipe(floadF_mem);
8340 %}
8343 instruct convI2L_reg(iRegL dst, iRegI src) %{
8344 match(Set dst (ConvI2L src));
8345 size(4);
8346 format %{ "SRA $src,0,$dst\t! int->long" %}
8347 opcode(Assembler::sra_op3, Assembler::arith_op);
8348 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8349 ins_pipe(ialu_reg_reg);
8350 %}
8352 // Zero-extend convert int to long
8353 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8354 match(Set dst (AndL (ConvI2L src) mask) );
8355 size(4);
8356 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8357 opcode(Assembler::srl_op3, Assembler::arith_op);
8358 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8359 ins_pipe(ialu_reg_reg);
8360 %}
8362 // Zero-extend long
8363 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8364 match(Set dst (AndL src mask) );
8365 size(4);
8366 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8367 opcode(Assembler::srl_op3, Assembler::arith_op);
8368 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8369 ins_pipe(ialu_reg_reg);
8370 %}
8372 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8373 match(Set dst (MoveF2I src));
8374 effect(DEF dst, USE src);
8375 ins_cost(MEMORY_REF_COST);
8377 size(4);
8378 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8379 opcode(Assembler::lduw_op3);
8380 ins_encode(simple_form3_mem_reg( src, dst ) );
8381 ins_pipe(iload_mem);
8382 %}
8384 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8385 match(Set dst (MoveI2F src));
8386 effect(DEF dst, USE src);
8387 ins_cost(MEMORY_REF_COST);
8389 size(4);
8390 format %{ "LDF $src,$dst\t! MoveI2F" %}
8391 opcode(Assembler::ldf_op3);
8392 ins_encode(simple_form3_mem_reg(src, dst));
8393 ins_pipe(floadF_stk);
8394 %}
8396 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8397 match(Set dst (MoveD2L src));
8398 effect(DEF dst, USE src);
8399 ins_cost(MEMORY_REF_COST);
8401 size(4);
8402 format %{ "LDX $src,$dst\t! MoveD2L" %}
8403 opcode(Assembler::ldx_op3);
8404 ins_encode(simple_form3_mem_reg( src, dst ) );
8405 ins_pipe(iload_mem);
8406 %}
8408 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8409 match(Set dst (MoveL2D src));
8410 effect(DEF dst, USE src);
8411 ins_cost(MEMORY_REF_COST);
8413 size(4);
8414 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8415 opcode(Assembler::lddf_op3);
8416 ins_encode(simple_form3_mem_reg(src, dst));
8417 ins_pipe(floadD_stk);
8418 %}
8420 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8421 match(Set dst (MoveF2I src));
8422 effect(DEF dst, USE src);
8423 ins_cost(MEMORY_REF_COST);
8425 size(4);
8426 format %{ "STF $src,$dst\t!MoveF2I" %}
8427 opcode(Assembler::stf_op3);
8428 ins_encode(simple_form3_mem_reg(dst, src));
8429 ins_pipe(fstoreF_stk_reg);
8430 %}
8432 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8433 match(Set dst (MoveI2F src));
8434 effect(DEF dst, USE src);
8435 ins_cost(MEMORY_REF_COST);
8437 size(4);
8438 format %{ "STW $src,$dst\t!MoveI2F" %}
8439 opcode(Assembler::stw_op3);
8440 ins_encode(simple_form3_mem_reg( dst, src ) );
8441 ins_pipe(istore_mem_reg);
8442 %}
8444 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8445 match(Set dst (MoveD2L src));
8446 effect(DEF dst, USE src);
8447 ins_cost(MEMORY_REF_COST);
8449 size(4);
8450 format %{ "STDF $src,$dst\t!MoveD2L" %}
8451 opcode(Assembler::stdf_op3);
8452 ins_encode(simple_form3_mem_reg(dst, src));
8453 ins_pipe(fstoreD_stk_reg);
8454 %}
8456 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8457 match(Set dst (MoveL2D src));
8458 effect(DEF dst, USE src);
8459 ins_cost(MEMORY_REF_COST);
8461 size(4);
8462 format %{ "STX $src,$dst\t!MoveL2D" %}
8463 opcode(Assembler::stx_op3);
8464 ins_encode(simple_form3_mem_reg( dst, src ) );
8465 ins_pipe(istore_mem_reg);
8466 %}
8469 //-----------
8470 // Long to Double conversion using V8 opcodes.
8471 // Still useful because cheetah traps and becomes
8472 // amazingly slow for some common numbers.
8474 // Magic constant, 0x43300000
8475 instruct loadConI_x43300000(iRegI dst) %{
8476 effect(DEF dst);
8477 size(4);
8478 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8479 ins_encode(SetHi22(0x43300000, dst));
8480 ins_pipe(ialu_none);
8481 %}
8483 // Magic constant, 0x41f00000
8484 instruct loadConI_x41f00000(iRegI dst) %{
8485 effect(DEF dst);
8486 size(4);
8487 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8488 ins_encode(SetHi22(0x41f00000, dst));
8489 ins_pipe(ialu_none);
8490 %}
8492 // Construct a double from two float halves
8493 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8494 effect(DEF dst, USE src1, USE src2);
8495 size(8);
8496 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8497 "FMOVS $src2.lo,$dst.lo" %}
8498 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8499 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8500 ins_pipe(faddD_reg_reg);
8501 %}
8503 // Convert integer in high half of a double register (in the lower half of
8504 // the double register file) to double
8505 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8506 effect(DEF dst, USE src);
8507 size(4);
8508 format %{ "FITOD $src,$dst" %}
8509 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8510 ins_encode(form3_opf_rs2D_rdD(src, dst));
8511 ins_pipe(fcvtLHi2D);
8512 %}
8514 // Add float double precision
8515 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8516 effect(DEF dst, USE src1, USE src2);
8517 size(4);
8518 format %{ "FADDD $src1,$src2,$dst" %}
8519 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8520 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8521 ins_pipe(faddD_reg_reg);
8522 %}
8524 // Sub float double precision
8525 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8526 effect(DEF dst, USE src1, USE src2);
8527 size(4);
8528 format %{ "FSUBD $src1,$src2,$dst" %}
8529 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8530 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8531 ins_pipe(faddD_reg_reg);
8532 %}
8534 // Mul float double precision
8535 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8536 effect(DEF dst, USE src1, USE src2);
8537 size(4);
8538 format %{ "FMULD $src1,$src2,$dst" %}
8539 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8540 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8541 ins_pipe(fmulD_reg_reg);
8542 %}
8544 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8545 match(Set dst (ConvL2D src));
8546 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8548 expand %{
8549 regD_low tmpsrc;
8550 iRegI ix43300000;
8551 iRegI ix41f00000;
8552 stackSlotL lx43300000;
8553 stackSlotL lx41f00000;
8554 regD_low dx43300000;
8555 regD dx41f00000;
8556 regD tmp1;
8557 regD_low tmp2;
8558 regD tmp3;
8559 regD tmp4;
8561 stkL_to_regD(tmpsrc, src);
8563 loadConI_x43300000(ix43300000);
8564 loadConI_x41f00000(ix41f00000);
8565 regI_to_stkLHi(lx43300000, ix43300000);
8566 regI_to_stkLHi(lx41f00000, ix41f00000);
8567 stkL_to_regD(dx43300000, lx43300000);
8568 stkL_to_regD(dx41f00000, lx41f00000);
8570 convI2D_regDHi_regD(tmp1, tmpsrc);
8571 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8572 subD_regD_regD(tmp3, tmp2, dx43300000);
8573 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8574 addD_regD_regD(dst, tmp3, tmp4);
8575 %}
8576 %}
8578 // Long to Double conversion using fast fxtof
8579 instruct convL2D_helper(regD dst, regD tmp) %{
8580 effect(DEF dst, USE tmp);
8581 size(4);
8582 format %{ "FXTOD $tmp,$dst" %}
8583 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8584 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8585 ins_pipe(fcvtL2D);
8586 %}
8588 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
8589 predicate(VM_Version::has_fast_fxtof());
8590 match(Set dst (ConvL2D src));
8591 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8592 expand %{
8593 regD tmp;
8594 stkL_to_regD(tmp, src);
8595 convL2D_helper(dst, tmp);
8596 %}
8597 %}
8599 //-----------
8600 // Long to Float conversion using V8 opcodes.
8601 // Still useful because cheetah traps and becomes
8602 // amazingly slow for some common numbers.
8604 // Long to Float conversion using fast fxtof
8605 instruct convL2F_helper(regF dst, regD tmp) %{
8606 effect(DEF dst, USE tmp);
8607 size(4);
8608 format %{ "FXTOS $tmp,$dst" %}
8609 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8610 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8611 ins_pipe(fcvtL2F);
8612 %}
8614 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
8615 match(Set dst (ConvL2F src));
8616 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8617 expand %{
8618 regD tmp;
8619 stkL_to_regD(tmp, src);
8620 convL2F_helper(dst, tmp);
8621 %}
8622 %}
8623 //-----------
8625 instruct convL2I_reg(iRegI dst, iRegL src) %{
8626 match(Set dst (ConvL2I src));
8627 #ifndef _LP64
8628 format %{ "MOV $src.lo,$dst\t! long->int" %}
8629 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8630 ins_pipe(ialu_move_reg_I_to_L);
8631 #else
8632 size(4);
8633 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8634 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8635 ins_pipe(ialu_reg);
8636 #endif
8637 %}
8639 // Register Shift Right Immediate
8640 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8641 match(Set dst (ConvL2I (RShiftL src cnt)));
8643 size(4);
8644 format %{ "SRAX $src,$cnt,$dst" %}
8645 opcode(Assembler::srax_op3, Assembler::arith_op);
8646 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8647 ins_pipe(ialu_reg_imm);
8648 %}
8650 // Replicate scalar to packed byte values in Double register
8651 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
8652 effect(DEF dst, USE src);
8653 format %{ "SLLX $src,56,$dst\n\t"
8654 "SRLX $dst, 8,O7\n\t"
8655 "OR $dst,O7,$dst\n\t"
8656 "SRLX $dst,16,O7\n\t"
8657 "OR $dst,O7,$dst\n\t"
8658 "SRLX $dst,32,O7\n\t"
8659 "OR $dst,O7,$dst\t! replicate8B" %}
8660 ins_encode( enc_repl8b(src, dst));
8661 ins_pipe(ialu_reg);
8662 %}
8664 // Replicate scalar to packed byte values in Double register
8665 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
8666 match(Set dst (Replicate8B src));
8667 expand %{
8668 iRegL tmp;
8669 Repl8B_reg_helper(tmp, src);
8670 regL_to_stkD(dst, tmp);
8671 %}
8672 %}
8674 // Replicate scalar constant to packed byte values in Double register
8675 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
8676 match(Set dst (Replicate8B con));
8677 effect(KILL tmp);
8678 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
8679 ins_encode %{
8680 // XXX This is a quick fix for 6833573.
8681 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
8682 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
8683 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8684 %}
8685 ins_pipe(loadConFD);
8686 %}
8688 // Replicate scalar to packed char values into stack slot
8689 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
8690 effect(DEF dst, USE src);
8691 format %{ "SLLX $src,48,$dst\n\t"
8692 "SRLX $dst,16,O7\n\t"
8693 "OR $dst,O7,$dst\n\t"
8694 "SRLX $dst,32,O7\n\t"
8695 "OR $dst,O7,$dst\t! replicate4C" %}
8696 ins_encode( enc_repl4s(src, dst) );
8697 ins_pipe(ialu_reg);
8698 %}
8700 // Replicate scalar to packed char values into stack slot
8701 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
8702 match(Set dst (Replicate4C src));
8703 expand %{
8704 iRegL tmp;
8705 Repl4C_reg_helper(tmp, src);
8706 regL_to_stkD(dst, tmp);
8707 %}
8708 %}
8710 // Replicate scalar constant to packed char values in Double register
8711 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{
8712 match(Set dst (Replicate4C con));
8713 effect(KILL tmp);
8714 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %}
8715 ins_encode %{
8716 // XXX This is a quick fix for 6833573.
8717 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8718 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8719 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8720 %}
8721 ins_pipe(loadConFD);
8722 %}
8724 // Replicate scalar to packed short values into stack slot
8725 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
8726 effect(DEF dst, USE src);
8727 format %{ "SLLX $src,48,$dst\n\t"
8728 "SRLX $dst,16,O7\n\t"
8729 "OR $dst,O7,$dst\n\t"
8730 "SRLX $dst,32,O7\n\t"
8731 "OR $dst,O7,$dst\t! replicate4S" %}
8732 ins_encode( enc_repl4s(src, dst) );
8733 ins_pipe(ialu_reg);
8734 %}
8736 // Replicate scalar to packed short values into stack slot
8737 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
8738 match(Set dst (Replicate4S src));
8739 expand %{
8740 iRegL tmp;
8741 Repl4S_reg_helper(tmp, src);
8742 regL_to_stkD(dst, tmp);
8743 %}
8744 %}
8746 // Replicate scalar constant to packed short values in Double register
8747 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
8748 match(Set dst (Replicate4S con));
8749 effect(KILL tmp);
8750 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
8751 ins_encode %{
8752 // XXX This is a quick fix for 6833573.
8753 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
8754 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
8755 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8756 %}
8757 ins_pipe(loadConFD);
8758 %}
8760 // Replicate scalar to packed int values in Double register
8761 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
8762 effect(DEF dst, USE src);
8763 format %{ "SLLX $src,32,$dst\n\t"
8764 "SRLX $dst,32,O7\n\t"
8765 "OR $dst,O7,$dst\t! replicate2I" %}
8766 ins_encode( enc_repl2i(src, dst));
8767 ins_pipe(ialu_reg);
8768 %}
8770 // Replicate scalar to packed int values in Double register
8771 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
8772 match(Set dst (Replicate2I src));
8773 expand %{
8774 iRegL tmp;
8775 Repl2I_reg_helper(tmp, src);
8776 regL_to_stkD(dst, tmp);
8777 %}
8778 %}
8780 // Replicate scalar zero constant to packed int values in Double register
8781 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
8782 match(Set dst (Replicate2I con));
8783 effect(KILL tmp);
8784 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
8785 ins_encode %{
8786 // XXX This is a quick fix for 6833573.
8787 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
8788 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
8789 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
8790 %}
8791 ins_pipe(loadConFD);
8792 %}
8794 //----------Control Flow Instructions------------------------------------------
8795 // Compare Instructions
8796 // Compare Integers
8797 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8798 match(Set icc (CmpI op1 op2));
8799 effect( DEF icc, USE op1, USE op2 );
8801 size(4);
8802 format %{ "CMP $op1,$op2" %}
8803 opcode(Assembler::subcc_op3, Assembler::arith_op);
8804 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8805 ins_pipe(ialu_cconly_reg_reg);
8806 %}
8808 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8809 match(Set icc (CmpU op1 op2));
8811 size(4);
8812 format %{ "CMP $op1,$op2\t! unsigned" %}
8813 opcode(Assembler::subcc_op3, Assembler::arith_op);
8814 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8815 ins_pipe(ialu_cconly_reg_reg);
8816 %}
8818 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8819 match(Set icc (CmpI op1 op2));
8820 effect( DEF icc, USE op1 );
8822 size(4);
8823 format %{ "CMP $op1,$op2" %}
8824 opcode(Assembler::subcc_op3, Assembler::arith_op);
8825 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8826 ins_pipe(ialu_cconly_reg_imm);
8827 %}
8829 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8830 match(Set icc (CmpI (AndI op1 op2) zero));
8832 size(4);
8833 format %{ "BTST $op2,$op1" %}
8834 opcode(Assembler::andcc_op3, Assembler::arith_op);
8835 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8836 ins_pipe(ialu_cconly_reg_reg_zero);
8837 %}
8839 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8840 match(Set icc (CmpI (AndI op1 op2) zero));
8842 size(4);
8843 format %{ "BTST $op2,$op1" %}
8844 opcode(Assembler::andcc_op3, Assembler::arith_op);
8845 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8846 ins_pipe(ialu_cconly_reg_imm_zero);
8847 %}
8849 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8850 match(Set xcc (CmpL op1 op2));
8851 effect( DEF xcc, USE op1, USE op2 );
8853 size(4);
8854 format %{ "CMP $op1,$op2\t\t! long" %}
8855 opcode(Assembler::subcc_op3, Assembler::arith_op);
8856 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8857 ins_pipe(ialu_cconly_reg_reg);
8858 %}
8860 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8861 match(Set xcc (CmpL op1 con));
8862 effect( DEF xcc, USE op1, USE con );
8864 size(4);
8865 format %{ "CMP $op1,$con\t\t! long" %}
8866 opcode(Assembler::subcc_op3, Assembler::arith_op);
8867 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8868 ins_pipe(ialu_cconly_reg_reg);
8869 %}
8871 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8872 match(Set xcc (CmpL (AndL op1 op2) zero));
8873 effect( DEF xcc, USE op1, USE op2 );
8875 size(4);
8876 format %{ "BTST $op1,$op2\t\t! long" %}
8877 opcode(Assembler::andcc_op3, Assembler::arith_op);
8878 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8879 ins_pipe(ialu_cconly_reg_reg);
8880 %}
8882 // useful for checking the alignment of a pointer:
8883 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8884 match(Set xcc (CmpL (AndL op1 con) zero));
8885 effect( DEF xcc, USE op1, USE con );
8887 size(4);
8888 format %{ "BTST $op1,$con\t\t! long" %}
8889 opcode(Assembler::andcc_op3, Assembler::arith_op);
8890 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8891 ins_pipe(ialu_cconly_reg_reg);
8892 %}
8894 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8895 match(Set icc (CmpU op1 op2));
8897 size(4);
8898 format %{ "CMP $op1,$op2\t! unsigned" %}
8899 opcode(Assembler::subcc_op3, Assembler::arith_op);
8900 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8901 ins_pipe(ialu_cconly_reg_imm);
8902 %}
8904 // Compare Pointers
8905 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8906 match(Set pcc (CmpP op1 op2));
8908 size(4);
8909 format %{ "CMP $op1,$op2\t! ptr" %}
8910 opcode(Assembler::subcc_op3, Assembler::arith_op);
8911 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8912 ins_pipe(ialu_cconly_reg_reg);
8913 %}
8915 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8916 match(Set pcc (CmpP op1 op2));
8918 size(4);
8919 format %{ "CMP $op1,$op2\t! ptr" %}
8920 opcode(Assembler::subcc_op3, Assembler::arith_op);
8921 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8922 ins_pipe(ialu_cconly_reg_imm);
8923 %}
8925 // Compare Narrow oops
8926 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8927 match(Set icc (CmpN op1 op2));
8929 size(4);
8930 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8931 opcode(Assembler::subcc_op3, Assembler::arith_op);
8932 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8933 ins_pipe(ialu_cconly_reg_reg);
8934 %}
8936 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8937 match(Set icc (CmpN op1 op2));
8939 size(4);
8940 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8941 opcode(Assembler::subcc_op3, Assembler::arith_op);
8942 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8943 ins_pipe(ialu_cconly_reg_imm);
8944 %}
8946 //----------Max and Min--------------------------------------------------------
8947 // Min Instructions
8948 // Conditional move for min
8949 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8950 effect( USE_DEF op2, USE op1, USE icc );
8952 size(4);
8953 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8954 opcode(Assembler::less);
8955 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8956 ins_pipe(ialu_reg_flags);
8957 %}
8959 // Min Register with Register.
8960 instruct minI_eReg(iRegI op1, iRegI op2) %{
8961 match(Set op2 (MinI op1 op2));
8962 ins_cost(DEFAULT_COST*2);
8963 expand %{
8964 flagsReg icc;
8965 compI_iReg(icc,op1,op2);
8966 cmovI_reg_lt(op2,op1,icc);
8967 %}
8968 %}
8970 // Max Instructions
8971 // Conditional move for max
8972 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8973 effect( USE_DEF op2, USE op1, USE icc );
8974 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8975 opcode(Assembler::greater);
8976 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8977 ins_pipe(ialu_reg_flags);
8978 %}
8980 // Max Register with Register
8981 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8982 match(Set op2 (MaxI op1 op2));
8983 ins_cost(DEFAULT_COST*2);
8984 expand %{
8985 flagsReg icc;
8986 compI_iReg(icc,op1,op2);
8987 cmovI_reg_gt(op2,op1,icc);
8988 %}
8989 %}
8992 //----------Float Compares----------------------------------------------------
8993 // Compare floating, generate condition code
8994 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8995 match(Set fcc (CmpF src1 src2));
8997 size(4);
8998 format %{ "FCMPs $fcc,$src1,$src2" %}
8999 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9000 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9001 ins_pipe(faddF_fcc_reg_reg_zero);
9002 %}
9004 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9005 match(Set fcc (CmpD src1 src2));
9007 size(4);
9008 format %{ "FCMPd $fcc,$src1,$src2" %}
9009 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9010 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9011 ins_pipe(faddD_fcc_reg_reg_zero);
9012 %}
9015 // Compare floating, generate -1,0,1
9016 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9017 match(Set dst (CmpF3 src1 src2));
9018 effect(KILL fcc0);
9019 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9020 format %{ "fcmpl $dst,$src1,$src2" %}
9021 // Primary = float
9022 opcode( true );
9023 ins_encode( floating_cmp( dst, src1, src2 ) );
9024 ins_pipe( floating_cmp );
9025 %}
9027 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9028 match(Set dst (CmpD3 src1 src2));
9029 effect(KILL fcc0);
9030 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9031 format %{ "dcmpl $dst,$src1,$src2" %}
9032 // Primary = double (not float)
9033 opcode( false );
9034 ins_encode( floating_cmp( dst, src1, src2 ) );
9035 ins_pipe( floating_cmp );
9036 %}
9038 //----------Branches---------------------------------------------------------
9039 // Jump
9040 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9041 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9042 match(Jump switch_val);
9044 ins_cost(350);
9046 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9047 "LD [O7 + $switch_val], O7\n\t"
9048 "JUMP O7"
9049 %}
9050 ins_encode %{
9051 // Calculate table address into a register.
9052 Register table_reg;
9053 Register label_reg = O7;
9054 if (constant_offset() == 0) {
9055 table_reg = $constanttablebase;
9056 } else {
9057 table_reg = O7;
9058 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9059 __ add($constanttablebase, con_offset, table_reg);
9060 }
9062 // Jump to base address + switch value
9063 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9064 __ jmp(label_reg, G0);
9065 __ delayed()->nop();
9066 %}
9067 ins_pc_relative(1);
9068 ins_pipe(ialu_reg_reg);
9069 %}
9071 // Direct Branch. Use V8 version with longer range.
9072 instruct branch(label labl) %{
9073 match(Goto);
9074 effect(USE labl);
9076 size(8);
9077 ins_cost(BRANCH_COST);
9078 format %{ "BA $labl" %}
9079 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
9080 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
9081 ins_encode( enc_ba( labl ) );
9082 ins_pc_relative(1);
9083 ins_pipe(br);
9084 %}
9086 // Conditional Direct Branch
9087 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9088 match(If cmp icc);
9089 effect(USE labl);
9091 size(8);
9092 ins_cost(BRANCH_COST);
9093 format %{ "BP$cmp $icc,$labl" %}
9094 // Prim = bits 24-22, Secnd = bits 31-30
9095 ins_encode( enc_bp( labl, cmp, icc ) );
9096 ins_pc_relative(1);
9097 ins_pipe(br_cc);
9098 %}
9100 // Branch-on-register tests all 64 bits. We assume that values
9101 // in 64-bit registers always remains zero or sign extended
9102 // unless our code munges the high bits. Interrupts can chop
9103 // the high order bits to zero or sign at any time.
9104 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9105 match(If cmp (CmpI op1 zero));
9106 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9107 effect(USE labl);
9109 size(8);
9110 ins_cost(BRANCH_COST);
9111 format %{ "BR$cmp $op1,$labl" %}
9112 ins_encode( enc_bpr( labl, cmp, op1 ) );
9113 ins_pc_relative(1);
9114 ins_pipe(br_reg);
9115 %}
9117 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9118 match(If cmp (CmpP op1 null));
9119 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9120 effect(USE labl);
9122 size(8);
9123 ins_cost(BRANCH_COST);
9124 format %{ "BR$cmp $op1,$labl" %}
9125 ins_encode( enc_bpr( labl, cmp, op1 ) );
9126 ins_pc_relative(1);
9127 ins_pipe(br_reg);
9128 %}
9130 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9131 match(If cmp (CmpL op1 zero));
9132 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9133 effect(USE labl);
9135 size(8);
9136 ins_cost(BRANCH_COST);
9137 format %{ "BR$cmp $op1,$labl" %}
9138 ins_encode( enc_bpr( labl, cmp, op1 ) );
9139 ins_pc_relative(1);
9140 ins_pipe(br_reg);
9141 %}
9143 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9144 match(If cmp icc);
9145 effect(USE labl);
9147 format %{ "BP$cmp $icc,$labl" %}
9148 // Prim = bits 24-22, Secnd = bits 31-30
9149 ins_encode( enc_bp( labl, cmp, icc ) );
9150 ins_pc_relative(1);
9151 ins_pipe(br_cc);
9152 %}
9154 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9155 match(If cmp pcc);
9156 effect(USE labl);
9158 size(8);
9159 ins_cost(BRANCH_COST);
9160 format %{ "BP$cmp $pcc,$labl" %}
9161 // Prim = bits 24-22, Secnd = bits 31-30
9162 ins_encode( enc_bpx( labl, cmp, pcc ) );
9163 ins_pc_relative(1);
9164 ins_pipe(br_cc);
9165 %}
9167 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9168 match(If cmp fcc);
9169 effect(USE labl);
9171 size(8);
9172 ins_cost(BRANCH_COST);
9173 format %{ "FBP$cmp $fcc,$labl" %}
9174 // Prim = bits 24-22, Secnd = bits 31-30
9175 ins_encode( enc_fbp( labl, cmp, fcc ) );
9176 ins_pc_relative(1);
9177 ins_pipe(br_fcc);
9178 %}
9180 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9181 match(CountedLoopEnd cmp icc);
9182 effect(USE labl);
9184 size(8);
9185 ins_cost(BRANCH_COST);
9186 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9187 // Prim = bits 24-22, Secnd = bits 31-30
9188 ins_encode( enc_bp( labl, cmp, icc ) );
9189 ins_pc_relative(1);
9190 ins_pipe(br_cc);
9191 %}
9193 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9194 match(CountedLoopEnd cmp icc);
9195 effect(USE labl);
9197 size(8);
9198 ins_cost(BRANCH_COST);
9199 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9200 // Prim = bits 24-22, Secnd = bits 31-30
9201 ins_encode( enc_bp( labl, cmp, icc ) );
9202 ins_pc_relative(1);
9203 ins_pipe(br_cc);
9204 %}
9206 // ============================================================================
9207 // Long Compare
9208 //
9209 // Currently we hold longs in 2 registers. Comparing such values efficiently
9210 // is tricky. The flavor of compare used depends on whether we are testing
9211 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9212 // The GE test is the negated LT test. The LE test can be had by commuting
9213 // the operands (yielding a GE test) and then negating; negate again for the
9214 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9215 // NE test is negated from that.
9217 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9218 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9219 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9220 // are collapsed internally in the ADLC's dfa-gen code. The match for
9221 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9222 // foo match ends up with the wrong leaf. One fix is to not match both
9223 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9224 // both forms beat the trinary form of long-compare and both are very useful
9225 // on Intel which has so few registers.
9227 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9228 match(If cmp xcc);
9229 effect(USE labl);
9231 size(8);
9232 ins_cost(BRANCH_COST);
9233 format %{ "BP$cmp $xcc,$labl" %}
9234 // Prim = bits 24-22, Secnd = bits 31-30
9235 ins_encode( enc_bpl( labl, cmp, xcc ) );
9236 ins_pc_relative(1);
9237 ins_pipe(br_cc);
9238 %}
9240 // Manifest a CmpL3 result in an integer register. Very painful.
9241 // This is the test to avoid.
9242 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9243 match(Set dst (CmpL3 src1 src2) );
9244 effect( KILL ccr );
9245 ins_cost(6*DEFAULT_COST);
9246 size(24);
9247 format %{ "CMP $src1,$src2\t\t! long\n"
9248 "\tBLT,a,pn done\n"
9249 "\tMOV -1,$dst\t! delay slot\n"
9250 "\tBGT,a,pn done\n"
9251 "\tMOV 1,$dst\t! delay slot\n"
9252 "\tCLR $dst\n"
9253 "done:" %}
9254 ins_encode( cmpl_flag(src1,src2,dst) );
9255 ins_pipe(cmpL_reg);
9256 %}
9258 // Conditional move
9259 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9260 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9261 ins_cost(150);
9262 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9263 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9264 ins_pipe(ialu_reg);
9265 %}
9267 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9268 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9269 ins_cost(140);
9270 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9271 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9272 ins_pipe(ialu_imm);
9273 %}
9275 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9276 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9277 ins_cost(150);
9278 format %{ "MOV$cmp $xcc,$src,$dst" %}
9279 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9280 ins_pipe(ialu_reg);
9281 %}
9283 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9284 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9285 ins_cost(140);
9286 format %{ "MOV$cmp $xcc,$src,$dst" %}
9287 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9288 ins_pipe(ialu_imm);
9289 %}
9291 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9292 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9293 ins_cost(150);
9294 format %{ "MOV$cmp $xcc,$src,$dst" %}
9295 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9296 ins_pipe(ialu_reg);
9297 %}
9299 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9300 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9301 ins_cost(150);
9302 format %{ "MOV$cmp $xcc,$src,$dst" %}
9303 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9304 ins_pipe(ialu_reg);
9305 %}
9307 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9308 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9309 ins_cost(140);
9310 format %{ "MOV$cmp $xcc,$src,$dst" %}
9311 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9312 ins_pipe(ialu_imm);
9313 %}
9315 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9316 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9317 ins_cost(150);
9318 opcode(0x101);
9319 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9320 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9321 ins_pipe(int_conditional_float_move);
9322 %}
9324 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9325 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9326 ins_cost(150);
9327 opcode(0x102);
9328 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9329 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9330 ins_pipe(int_conditional_float_move);
9331 %}
9333 // ============================================================================
9334 // Safepoint Instruction
9335 instruct safePoint_poll(iRegP poll) %{
9336 match(SafePoint poll);
9337 effect(USE poll);
9339 size(4);
9340 #ifdef _LP64
9341 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9342 #else
9343 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9344 #endif
9345 ins_encode %{
9346 __ relocate(relocInfo::poll_type);
9347 __ ld_ptr($poll$$Register, 0, G0);
9348 %}
9349 ins_pipe(loadPollP);
9350 %}
9352 // ============================================================================
9353 // Call Instructions
9354 // Call Java Static Instruction
9355 instruct CallStaticJavaDirect( method meth ) %{
9356 match(CallStaticJava);
9357 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9358 effect(USE meth);
9360 size(8);
9361 ins_cost(CALL_COST);
9362 format %{ "CALL,static ; NOP ==> " %}
9363 ins_encode( Java_Static_Call( meth ), call_epilog );
9364 ins_pc_relative(1);
9365 ins_pipe(simple_call);
9366 %}
9368 // Call Java Static Instruction (method handle version)
9369 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9370 match(CallStaticJava);
9371 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9372 effect(USE meth, KILL l7_mh_SP_save);
9374 size(8);
9375 ins_cost(CALL_COST);
9376 format %{ "CALL,static/MethodHandle" %}
9377 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9378 ins_pc_relative(1);
9379 ins_pipe(simple_call);
9380 %}
9382 // Call Java Dynamic Instruction
9383 instruct CallDynamicJavaDirect( method meth ) %{
9384 match(CallDynamicJava);
9385 effect(USE meth);
9387 ins_cost(CALL_COST);
9388 format %{ "SET (empty),R_G5\n\t"
9389 "CALL,dynamic ; NOP ==> " %}
9390 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9391 ins_pc_relative(1);
9392 ins_pipe(call);
9393 %}
9395 // Call Runtime Instruction
9396 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9397 match(CallRuntime);
9398 effect(USE meth, KILL l7);
9399 ins_cost(CALL_COST);
9400 format %{ "CALL,runtime" %}
9401 ins_encode( Java_To_Runtime( meth ),
9402 call_epilog, adjust_long_from_native_call );
9403 ins_pc_relative(1);
9404 ins_pipe(simple_call);
9405 %}
9407 // Call runtime without safepoint - same as CallRuntime
9408 instruct CallLeafDirect(method meth, l7RegP l7) %{
9409 match(CallLeaf);
9410 effect(USE meth, KILL l7);
9411 ins_cost(CALL_COST);
9412 format %{ "CALL,runtime leaf" %}
9413 ins_encode( Java_To_Runtime( meth ),
9414 call_epilog,
9415 adjust_long_from_native_call );
9416 ins_pc_relative(1);
9417 ins_pipe(simple_call);
9418 %}
9420 // Call runtime without safepoint - same as CallLeaf
9421 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9422 match(CallLeafNoFP);
9423 effect(USE meth, KILL l7);
9424 ins_cost(CALL_COST);
9425 format %{ "CALL,runtime leaf nofp" %}
9426 ins_encode( Java_To_Runtime( meth ),
9427 call_epilog,
9428 adjust_long_from_native_call );
9429 ins_pc_relative(1);
9430 ins_pipe(simple_call);
9431 %}
9433 // Tail Call; Jump from runtime stub to Java code.
9434 // Also known as an 'interprocedural jump'.
9435 // Target of jump will eventually return to caller.
9436 // TailJump below removes the return address.
9437 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9438 match(TailCall jump_target method_oop );
9440 ins_cost(CALL_COST);
9441 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9442 ins_encode(form_jmpl(jump_target));
9443 ins_pipe(tail_call);
9444 %}
9447 // Return Instruction
9448 instruct Ret() %{
9449 match(Return);
9451 // The epilogue node did the ret already.
9452 size(0);
9453 format %{ "! return" %}
9454 ins_encode();
9455 ins_pipe(empty);
9456 %}
9459 // Tail Jump; remove the return address; jump to target.
9460 // TailCall above leaves the return address around.
9461 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9462 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9463 // "restore" before this instruction (in Epilogue), we need to materialize it
9464 // in %i0.
9465 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9466 match( TailJump jump_target ex_oop );
9467 ins_cost(CALL_COST);
9468 format %{ "! discard R_O7\n\t"
9469 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9470 ins_encode(form_jmpl_set_exception_pc(jump_target));
9471 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9472 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9473 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9474 ins_pipe(tail_call);
9475 %}
9477 // Create exception oop: created by stack-crawling runtime code.
9478 // Created exception is now available to this handler, and is setup
9479 // just prior to jumping to this handler. No code emitted.
9480 instruct CreateException( o0RegP ex_oop )
9481 %{
9482 match(Set ex_oop (CreateEx));
9483 ins_cost(0);
9485 size(0);
9486 // use the following format syntax
9487 format %{ "! exception oop is in R_O0; no code emitted" %}
9488 ins_encode();
9489 ins_pipe(empty);
9490 %}
9493 // Rethrow exception:
9494 // The exception oop will come in the first argument position.
9495 // Then JUMP (not call) to the rethrow stub code.
9496 instruct RethrowException()
9497 %{
9498 match(Rethrow);
9499 ins_cost(CALL_COST);
9501 // use the following format syntax
9502 format %{ "Jmp rethrow_stub" %}
9503 ins_encode(enc_rethrow);
9504 ins_pipe(tail_call);
9505 %}
9508 // Die now
9509 instruct ShouldNotReachHere( )
9510 %{
9511 match(Halt);
9512 ins_cost(CALL_COST);
9514 size(4);
9515 // Use the following format syntax
9516 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9517 ins_encode( form2_illtrap() );
9518 ins_pipe(tail_call);
9519 %}
9521 // ============================================================================
9522 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9523 // array for an instance of the superklass. Set a hidden internal cache on a
9524 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9525 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9526 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9527 match(Set index (PartialSubtypeCheck sub super));
9528 effect( KILL pcc, KILL o7 );
9529 ins_cost(DEFAULT_COST*10);
9530 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9531 ins_encode( enc_PartialSubtypeCheck() );
9532 ins_pipe(partial_subtype_check_pipe);
9533 %}
9535 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9536 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9537 effect( KILL idx, KILL o7 );
9538 ins_cost(DEFAULT_COST*10);
9539 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9540 ins_encode( enc_PartialSubtypeCheck() );
9541 ins_pipe(partial_subtype_check_pipe);
9542 %}
9545 // ============================================================================
9546 // inlined locking and unlocking
9548 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9549 match(Set pcc (FastLock object box));
9551 effect(KILL scratch, TEMP scratch2);
9552 ins_cost(100);
9554 size(4*112); // conservative overestimation ...
9555 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9556 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9557 ins_pipe(long_memory_op);
9558 %}
9561 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
9562 match(Set pcc (FastUnlock object box));
9563 effect(KILL scratch, TEMP scratch2);
9564 ins_cost(100);
9566 size(4*120); // conservative overestimation ...
9567 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
9568 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9569 ins_pipe(long_memory_op);
9570 %}
9572 // Count and Base registers are fixed because the allocator cannot
9573 // kill unknown registers. The encodings are generic.
9574 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9575 match(Set dummy (ClearArray cnt base));
9576 effect(TEMP temp, KILL ccr);
9577 ins_cost(300);
9578 format %{ "MOV $cnt,$temp\n"
9579 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9580 " BRge loop\t\t! Clearing loop\n"
9581 " STX G0,[$base+$temp]\t! delay slot" %}
9582 ins_encode( enc_Clear_Array(cnt, base, temp) );
9583 ins_pipe(long_memory_op);
9584 %}
9586 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
9587 o7RegI tmp, flagsReg ccr) %{
9588 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
9589 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
9590 ins_cost(300);
9591 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
9592 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
9593 ins_pipe(long_memory_op);
9594 %}
9596 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
9597 o7RegI tmp, flagsReg ccr) %{
9598 match(Set result (StrEquals (Binary str1 str2) cnt));
9599 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
9600 ins_cost(300);
9601 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
9602 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
9603 ins_pipe(long_memory_op);
9604 %}
9606 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
9607 o7RegI tmp2, flagsReg ccr) %{
9608 match(Set result (AryEq ary1 ary2));
9609 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
9610 ins_cost(300);
9611 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
9612 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
9613 ins_pipe(long_memory_op);
9614 %}
9617 //---------- Zeros Count Instructions ------------------------------------------
9619 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
9620 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9621 match(Set dst (CountLeadingZerosI src));
9622 effect(TEMP dst, TEMP tmp, KILL cr);
9624 // x |= (x >> 1);
9625 // x |= (x >> 2);
9626 // x |= (x >> 4);
9627 // x |= (x >> 8);
9628 // x |= (x >> 16);
9629 // return (WORDBITS - popc(x));
9630 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
9631 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
9632 "OR $dst,$tmp,$dst\n\t"
9633 "SRL $dst,2,$tmp\n\t"
9634 "OR $dst,$tmp,$dst\n\t"
9635 "SRL $dst,4,$tmp\n\t"
9636 "OR $dst,$tmp,$dst\n\t"
9637 "SRL $dst,8,$tmp\n\t"
9638 "OR $dst,$tmp,$dst\n\t"
9639 "SRL $dst,16,$tmp\n\t"
9640 "OR $dst,$tmp,$dst\n\t"
9641 "POPC $dst,$dst\n\t"
9642 "MOV 32,$tmp\n\t"
9643 "SUB $tmp,$dst,$dst" %}
9644 ins_encode %{
9645 Register Rdst = $dst$$Register;
9646 Register Rsrc = $src$$Register;
9647 Register Rtmp = $tmp$$Register;
9648 __ srl(Rsrc, 1, Rtmp);
9649 __ srl(Rsrc, 0, Rdst);
9650 __ or3(Rdst, Rtmp, Rdst);
9651 __ srl(Rdst, 2, Rtmp);
9652 __ or3(Rdst, Rtmp, Rdst);
9653 __ srl(Rdst, 4, Rtmp);
9654 __ or3(Rdst, Rtmp, Rdst);
9655 __ srl(Rdst, 8, Rtmp);
9656 __ or3(Rdst, Rtmp, Rdst);
9657 __ srl(Rdst, 16, Rtmp);
9658 __ or3(Rdst, Rtmp, Rdst);
9659 __ popc(Rdst, Rdst);
9660 __ mov(BitsPerInt, Rtmp);
9661 __ sub(Rtmp, Rdst, Rdst);
9662 %}
9663 ins_pipe(ialu_reg);
9664 %}
9666 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
9667 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9668 match(Set dst (CountLeadingZerosL src));
9669 effect(TEMP dst, TEMP tmp, KILL cr);
9671 // x |= (x >> 1);
9672 // x |= (x >> 2);
9673 // x |= (x >> 4);
9674 // x |= (x >> 8);
9675 // x |= (x >> 16);
9676 // x |= (x >> 32);
9677 // return (WORDBITS - popc(x));
9678 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
9679 "OR $src,$tmp,$dst\n\t"
9680 "SRLX $dst,2,$tmp\n\t"
9681 "OR $dst,$tmp,$dst\n\t"
9682 "SRLX $dst,4,$tmp\n\t"
9683 "OR $dst,$tmp,$dst\n\t"
9684 "SRLX $dst,8,$tmp\n\t"
9685 "OR $dst,$tmp,$dst\n\t"
9686 "SRLX $dst,16,$tmp\n\t"
9687 "OR $dst,$tmp,$dst\n\t"
9688 "SRLX $dst,32,$tmp\n\t"
9689 "OR $dst,$tmp,$dst\n\t"
9690 "POPC $dst,$dst\n\t"
9691 "MOV 64,$tmp\n\t"
9692 "SUB $tmp,$dst,$dst" %}
9693 ins_encode %{
9694 Register Rdst = $dst$$Register;
9695 Register Rsrc = $src$$Register;
9696 Register Rtmp = $tmp$$Register;
9697 __ srlx(Rsrc, 1, Rtmp);
9698 __ or3( Rsrc, Rtmp, Rdst);
9699 __ srlx(Rdst, 2, Rtmp);
9700 __ or3( Rdst, Rtmp, Rdst);
9701 __ srlx(Rdst, 4, Rtmp);
9702 __ or3( Rdst, Rtmp, Rdst);
9703 __ srlx(Rdst, 8, Rtmp);
9704 __ or3( Rdst, Rtmp, Rdst);
9705 __ srlx(Rdst, 16, Rtmp);
9706 __ or3( Rdst, Rtmp, Rdst);
9707 __ srlx(Rdst, 32, Rtmp);
9708 __ or3( Rdst, Rtmp, Rdst);
9709 __ popc(Rdst, Rdst);
9710 __ mov(BitsPerLong, Rtmp);
9711 __ sub(Rtmp, Rdst, Rdst);
9712 %}
9713 ins_pipe(ialu_reg);
9714 %}
9716 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
9717 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9718 match(Set dst (CountTrailingZerosI src));
9719 effect(TEMP dst, KILL cr);
9721 // return popc(~x & (x - 1));
9722 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
9723 "ANDN $dst,$src,$dst\n\t"
9724 "SRL $dst,R_G0,$dst\n\t"
9725 "POPC $dst,$dst" %}
9726 ins_encode %{
9727 Register Rdst = $dst$$Register;
9728 Register Rsrc = $src$$Register;
9729 __ sub(Rsrc, 1, Rdst);
9730 __ andn(Rdst, Rsrc, Rdst);
9731 __ srl(Rdst, G0, Rdst);
9732 __ popc(Rdst, Rdst);
9733 %}
9734 ins_pipe(ialu_reg);
9735 %}
9737 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
9738 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
9739 match(Set dst (CountTrailingZerosL src));
9740 effect(TEMP dst, KILL cr);
9742 // return popc(~x & (x - 1));
9743 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
9744 "ANDN $dst,$src,$dst\n\t"
9745 "POPC $dst,$dst" %}
9746 ins_encode %{
9747 Register Rdst = $dst$$Register;
9748 Register Rsrc = $src$$Register;
9749 __ sub(Rsrc, 1, Rdst);
9750 __ andn(Rdst, Rsrc, Rdst);
9751 __ popc(Rdst, Rdst);
9752 %}
9753 ins_pipe(ialu_reg);
9754 %}
9757 //---------- Population Count Instructions -------------------------------------
9759 instruct popCountI(iRegI dst, iRegI src) %{
9760 predicate(UsePopCountInstruction);
9761 match(Set dst (PopCountI src));
9763 format %{ "POPC $src, $dst" %}
9764 ins_encode %{
9765 __ popc($src$$Register, $dst$$Register);
9766 %}
9767 ins_pipe(ialu_reg);
9768 %}
9770 // Note: Long.bitCount(long) returns an int.
9771 instruct popCountL(iRegI dst, iRegL src) %{
9772 predicate(UsePopCountInstruction);
9773 match(Set dst (PopCountL src));
9775 format %{ "POPC $src, $dst" %}
9776 ins_encode %{
9777 __ popc($src$$Register, $dst$$Register);
9778 %}
9779 ins_pipe(ialu_reg);
9780 %}
9783 // ============================================================================
9784 //------------Bytes reverse--------------------------------------------------
9786 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
9787 match(Set dst (ReverseBytesI src));
9789 // Op cost is artificially doubled to make sure that load or store
9790 // instructions are preferred over this one which requires a spill
9791 // onto a stack slot.
9792 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9793 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9795 ins_encode %{
9796 __ set($src$$disp + STACK_BIAS, O7);
9797 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9798 %}
9799 ins_pipe( iload_mem );
9800 %}
9802 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
9803 match(Set dst (ReverseBytesL src));
9805 // Op cost is artificially doubled to make sure that load or store
9806 // instructions are preferred over this one which requires a spill
9807 // onto a stack slot.
9808 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9809 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9811 ins_encode %{
9812 __ set($src$$disp + STACK_BIAS, O7);
9813 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9814 %}
9815 ins_pipe( iload_mem );
9816 %}
9818 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
9819 match(Set dst (ReverseBytesUS src));
9821 // Op cost is artificially doubled to make sure that load or store
9822 // instructions are preferred over this one which requires a spill
9823 // onto a stack slot.
9824 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9825 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
9827 ins_encode %{
9828 // the value was spilled as an int so bias the load
9829 __ set($src$$disp + STACK_BIAS + 2, O7);
9830 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9831 %}
9832 ins_pipe( iload_mem );
9833 %}
9835 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
9836 match(Set dst (ReverseBytesS src));
9838 // Op cost is artificially doubled to make sure that load or store
9839 // instructions are preferred over this one which requires a spill
9840 // onto a stack slot.
9841 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
9842 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
9844 ins_encode %{
9845 // the value was spilled as an int so bias the load
9846 __ set($src$$disp + STACK_BIAS + 2, O7);
9847 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9848 %}
9849 ins_pipe( iload_mem );
9850 %}
9852 // Load Integer reversed byte order
9853 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
9854 match(Set dst (ReverseBytesI (LoadI src)));
9856 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
9857 size(4);
9858 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
9860 ins_encode %{
9861 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9862 %}
9863 ins_pipe(iload_mem);
9864 %}
9866 // Load Long - aligned and reversed
9867 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
9868 match(Set dst (ReverseBytesL (LoadL src)));
9870 ins_cost(MEMORY_REF_COST);
9871 size(4);
9872 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
9874 ins_encode %{
9875 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9876 %}
9877 ins_pipe(iload_mem);
9878 %}
9880 // Load unsigned short / char reversed byte order
9881 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
9882 match(Set dst (ReverseBytesUS (LoadUS src)));
9884 ins_cost(MEMORY_REF_COST);
9885 size(4);
9886 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
9888 ins_encode %{
9889 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9890 %}
9891 ins_pipe(iload_mem);
9892 %}
9894 // Load short reversed byte order
9895 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
9896 match(Set dst (ReverseBytesS (LoadS src)));
9898 ins_cost(MEMORY_REF_COST);
9899 size(4);
9900 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
9902 ins_encode %{
9903 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
9904 %}
9905 ins_pipe(iload_mem);
9906 %}
9908 // Store Integer reversed byte order
9909 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
9910 match(Set dst (StoreI dst (ReverseBytesI src)));
9912 ins_cost(MEMORY_REF_COST);
9913 size(4);
9914 format %{ "STWA $src, $dst\t!asi=primary_little" %}
9916 ins_encode %{
9917 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9918 %}
9919 ins_pipe(istore_mem_reg);
9920 %}
9922 // Store Long reversed byte order
9923 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
9924 match(Set dst (StoreL dst (ReverseBytesL src)));
9926 ins_cost(MEMORY_REF_COST);
9927 size(4);
9928 format %{ "STXA $src, $dst\t!asi=primary_little" %}
9930 ins_encode %{
9931 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9932 %}
9933 ins_pipe(istore_mem_reg);
9934 %}
9936 // Store unsighed short/char reversed byte order
9937 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
9938 match(Set dst (StoreC dst (ReverseBytesUS src)));
9940 ins_cost(MEMORY_REF_COST);
9941 size(4);
9942 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9944 ins_encode %{
9945 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9946 %}
9947 ins_pipe(istore_mem_reg);
9948 %}
9950 // Store short reversed byte order
9951 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
9952 match(Set dst (StoreC dst (ReverseBytesS src)));
9954 ins_cost(MEMORY_REF_COST);
9955 size(4);
9956 format %{ "STHA $src, $dst\t!asi=primary_little" %}
9958 ins_encode %{
9959 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
9960 %}
9961 ins_pipe(istore_mem_reg);
9962 %}
9964 //----------PEEPHOLE RULES-----------------------------------------------------
9965 // These must follow all instruction definitions as they use the names
9966 // defined in the instructions definitions.
9967 //
9968 // peepmatch ( root_instr_name [preceding_instruction]* );
9969 //
9970 // peepconstraint %{
9971 // (instruction_number.operand_name relational_op instruction_number.operand_name
9972 // [, ...] );
9973 // // instruction numbers are zero-based using left to right order in peepmatch
9974 //
9975 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
9976 // // provide an instruction_number.operand_name for each operand that appears
9977 // // in the replacement instruction's match rule
9978 //
9979 // ---------VM FLAGS---------------------------------------------------------
9980 //
9981 // All peephole optimizations can be turned off using -XX:-OptoPeephole
9982 //
9983 // Each peephole rule is given an identifying number starting with zero and
9984 // increasing by one in the order seen by the parser. An individual peephole
9985 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
9986 // on the command-line.
9987 //
9988 // ---------CURRENT LIMITATIONS----------------------------------------------
9989 //
9990 // Only match adjacent instructions in same basic block
9991 // Only equality constraints
9992 // Only constraints between operands, not (0.dest_reg == EAX_enc)
9993 // Only one replacement instruction
9994 //
9995 // ---------EXAMPLE----------------------------------------------------------
9996 //
9997 // // pertinent parts of existing instructions in architecture description
9998 // instruct movI(eRegI dst, eRegI src) %{
9999 // match(Set dst (CopyI src));
10000 // %}
10001 //
10002 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10003 // match(Set dst (AddI dst src));
10004 // effect(KILL cr);
10005 // %}
10006 //
10007 // // Change (inc mov) to lea
10008 // peephole %{
10009 // // increment preceeded by register-register move
10010 // peepmatch ( incI_eReg movI );
10011 // // require that the destination register of the increment
10012 // // match the destination register of the move
10013 // peepconstraint ( 0.dst == 1.dst );
10014 // // construct a replacement instruction that sets
10015 // // the destination to ( move's source register + one )
10016 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10017 // %}
10018 //
10020 // // Change load of spilled value to only a spill
10021 // instruct storeI(memory mem, eRegI src) %{
10022 // match(Set mem (StoreI mem src));
10023 // %}
10024 //
10025 // instruct loadI(eRegI dst, memory mem) %{
10026 // match(Set dst (LoadI mem));
10027 // %}
10028 //
10029 // peephole %{
10030 // peepmatch ( loadI storeI );
10031 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10032 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10033 // %}
10035 //----------SMARTSPILL RULES---------------------------------------------------
10036 // These must follow all instruction definitions as they use the names
10037 // defined in the instructions definitions.
10038 //
10039 // SPARC will probably not have any of these rules due to RISC instruction set.
10041 //----------PIPELINE-----------------------------------------------------------
10042 // Rules which define the behavior of the target architectures pipeline.