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src/cpu/x86/vm/c1_LIRAssembler_x86.cpp@7eca5de9e0b6
src/cpu/x86/vm/c1_LIRAssembler_x86.cpp
Thu, 20 Sep 2012 16:49:17 +0200
- author
- roland
- date
- Thu, 20 Sep 2012 16:49:17 +0200
- changeset 4106
- 7eca5de9e0b6
- parent 4051
- 8a02ca5e5576
- child 4142
- d8ce2825b193
- child 4159
- 8e47bac5643a
- permissions
- -rw-r--r--
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
Summary: use shorter instruction sequences for atomic add and atomic exchange when possible.
Reviewed-by: kvn, jrose
1 /*
2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc_interface/collectedHeap.hpp"
35 #include "memory/barrierSet.hpp"
36 #include "memory/cardTableModRefBS.hpp"
37 #include "nativeInst_x86.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/sharedRuntime.hpp"
42 // These masks are used to provide 128-bit aligned bitmasks to the XMM
43 // instructions, to allow sign-masking or sign-bit flipping. They allow
44 // fast versions of NegF/NegD and AbsF/AbsD.
46 // Note: 'double' and 'long long' have 32-bits alignment on x86.
47 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
48 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
49 // of 128-bits operands for SSE instructions.
50 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
51 // Store the value to a 128-bits operand.
52 operand[0] = lo;
53 operand[1] = hi;
54 return operand;
55 }
57 // Buffer for 128-bits masks used by SSE instructions.
58 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
60 // Static initialization during VM startup.
61 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
62 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
63 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
64 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
68 NEEDS_CLEANUP // remove this definitions ?
69 const Register IC_Klass = rax; // where the IC klass is cached
70 const Register SYNC_header = rax; // synchronization header
71 const Register SHIFT_count = rcx; // where count for shift operations must be
73 #define __ _masm->
76 static void select_different_registers(Register preserve,
77 Register extra,
78 Register &tmp1,
79 Register &tmp2) {
80 if (tmp1 == preserve) {
81 assert_different_registers(tmp1, tmp2, extra);
82 tmp1 = extra;
83 } else if (tmp2 == preserve) {
84 assert_different_registers(tmp1, tmp2, extra);
85 tmp2 = extra;
86 }
87 assert_different_registers(preserve, tmp1, tmp2);
88 }
92 static void select_different_registers(Register preserve,
93 Register extra,
94 Register &tmp1,
95 Register &tmp2,
96 Register &tmp3) {
97 if (tmp1 == preserve) {
98 assert_different_registers(tmp1, tmp2, tmp3, extra);
99 tmp1 = extra;
100 } else if (tmp2 == preserve) {
101 assert_different_registers(tmp1, tmp2, tmp3, extra);
102 tmp2 = extra;
103 } else if (tmp3 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp3 = extra;
106 }
107 assert_different_registers(preserve, tmp1, tmp2, tmp3);
108 }
112 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
113 if (opr->is_constant()) {
114 LIR_Const* constant = opr->as_constant_ptr();
115 switch (constant->type()) {
116 case T_INT: {
117 return true;
118 }
120 default:
121 return false;
122 }
123 }
124 return false;
125 }
128 LIR_Opr LIR_Assembler::receiverOpr() {
129 return FrameMap::receiver_opr;
130 }
132 LIR_Opr LIR_Assembler::osrBufferPointer() {
133 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
134 }
136 //--------------fpu register translations-----------------------
139 address LIR_Assembler::float_constant(float f) {
140 address const_addr = __ float_constant(f);
141 if (const_addr == NULL) {
142 bailout("const section overflow");
143 return __ code()->consts()->start();
144 } else {
145 return const_addr;
146 }
147 }
150 address LIR_Assembler::double_constant(double d) {
151 address const_addr = __ double_constant(d);
152 if (const_addr == NULL) {
153 bailout("const section overflow");
154 return __ code()->consts()->start();
155 } else {
156 return const_addr;
157 }
158 }
161 void LIR_Assembler::set_24bit_FPU() {
162 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
163 }
165 void LIR_Assembler::reset_FPU() {
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
167 }
169 void LIR_Assembler::fpop() {
170 __ fpop();
171 }
173 void LIR_Assembler::fxch(int i) {
174 __ fxch(i);
175 }
177 void LIR_Assembler::fld(int i) {
178 __ fld_s(i);
179 }
181 void LIR_Assembler::ffree(int i) {
182 __ ffree(i);
183 }
185 void LIR_Assembler::breakpoint() {
186 __ int3();
187 }
189 void LIR_Assembler::push(LIR_Opr opr) {
190 if (opr->is_single_cpu()) {
191 __ push_reg(opr->as_register());
192 } else if (opr->is_double_cpu()) {
193 NOT_LP64(__ push_reg(opr->as_register_hi()));
194 __ push_reg(opr->as_register_lo());
195 } else if (opr->is_stack()) {
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
197 } else if (opr->is_constant()) {
198 LIR_Const* const_opr = opr->as_constant_ptr();
199 if (const_opr->type() == T_OBJECT) {
200 __ push_oop(const_opr->as_jobject());
201 } else if (const_opr->type() == T_INT) {
202 __ push_jint(const_opr->as_jint());
203 } else {
204 ShouldNotReachHere();
205 }
207 } else {
208 ShouldNotReachHere();
209 }
210 }
212 void LIR_Assembler::pop(LIR_Opr opr) {
213 if (opr->is_single_cpu()) {
214 __ pop_reg(opr->as_register());
215 } else {
216 ShouldNotReachHere();
217 }
218 }
220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
221 return addr->base()->is_illegal() && addr->index()->is_illegal();
222 }
224 //-------------------------------------------
226 Address LIR_Assembler::as_Address(LIR_Address* addr) {
227 return as_Address(addr, rscratch1);
228 }
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
231 if (addr->base()->is_illegal()) {
232 assert(addr->index()->is_illegal(), "must be illegal too");
233 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
234 if (! __ reachable(laddr)) {
235 __ movptr(tmp, laddr.addr());
236 Address res(tmp, 0);
237 return res;
238 } else {
239 return __ as_Address(laddr);
240 }
241 }
243 Register base = addr->base()->as_pointer_register();
245 if (addr->index()->is_illegal()) {
246 return Address( base, addr->disp());
247 } else if (addr->index()->is_cpu_register()) {
248 Register index = addr->index()->as_pointer_register();
249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
250 } else if (addr->index()->is_constant()) {
251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
252 assert(Assembler::is_simm32(addr_offset), "must be");
254 return Address(base, addr_offset);
255 } else {
256 Unimplemented();
257 return Address();
258 }
259 }
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
263 Address base = as_Address(addr);
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
265 }
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
269 return as_Address(addr);
270 }
273 void LIR_Assembler::osr_entry() {
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
276 ValueStack* entry_state = osr_entry->state();
277 int number_of_locks = entry_state->locks_size();
279 // we jump here if osr happens with the interpreter
280 // state set up to continue at the beginning of the
281 // loop that triggered osr - in particular, we have
282 // the following registers setup:
283 //
284 // rcx: osr buffer
285 //
287 // build frame
288 ciMethod* m = compilation()->method();
289 __ build_frame(initial_frame_size_in_bytes());
291 // OSR buffer is
292 //
293 // locals[nlocals-1..0]
294 // monitors[0..number_of_locks]
295 //
296 // locals is a direct copy of the interpreter frame so in the osr buffer
297 // so first slot in the local array is the last local from the interpreter
298 // and last slot is local[0] (receiver) from the interpreter
299 //
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
302 // in the interpreter frame (the method lock if a sync method)
304 // Initialize monitors in the compiled activation.
305 // rcx: pointer to osr buffer
306 //
307 // All other registers are dead at this point and the locals will be
308 // copied into place by code emitted in the IR.
310 Register OSR_buf = osrBufferPointer()->as_pointer_register();
311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
312 int monitor_offset = BytesPerWord * method()->max_locals() +
313 (2 * BytesPerWord) * (number_of_locks - 1);
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
315 // the OSR buffer using 2 word entries: first the lock and then
316 // the oop.
317 for (int i = 0; i < number_of_locks; i++) {
318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
319 #ifdef ASSERT
320 // verify the interpreter's monitor has a non-null object
321 {
322 Label L;
323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
324 __ jcc(Assembler::notZero, L);
325 __ stop("locked object is NULL");
326 __ bind(L);
327 }
328 #endif
329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
332 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
333 }
334 }
335 }
338 // inline cache check; done before the frame is built.
339 int LIR_Assembler::check_icache() {
340 Register receiver = FrameMap::receiver_opr->as_register();
341 Register ic_klass = IC_Klass;
342 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
343 const bool do_post_padding = VerifyOops || UseCompressedOops;
344 if (!do_post_padding) {
345 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
346 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
347 __ nop();
348 }
349 }
350 int offset = __ offset();
351 __ inline_cache_check(receiver, IC_Klass);
352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
353 if (do_post_padding) {
354 // force alignment after the cache check.
355 // It's been verified to be aligned if !VerifyOops
356 __ align(CodeEntryAlignment);
357 }
358 return offset;
359 }
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
363 jobject o = NULL;
364 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_mirror_id);
365 __ movoop(reg, o);
366 patching_epilog(patch, lir_patch_normal, reg, info);
367 }
369 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
370 Metadata* o = NULL;
371 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
372 __ mov_metadata(reg, o);
373 patching_epilog(patch, lir_patch_normal, reg, info);
374 }
376 // This specifies the rsp decrement needed to build the frame
377 int LIR_Assembler::initial_frame_size_in_bytes() {
378 // if rounding, must let FrameMap know!
380 // The frame_map records size in slots (32bit word)
382 // subtract two words to account for return address and link
383 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
384 }
387 int LIR_Assembler::emit_exception_handler() {
388 // if the last instruction is a call (typically to do a throw which
389 // is coming at the end after block reordering) the return address
390 // must still point into the code area in order to avoid assertion
391 // failures when searching for the corresponding bci => add a nop
392 // (was bug 5/14/1999 - gri)
393 __ nop();
395 // generate code for exception handler
396 address handler_base = __ start_a_stub(exception_handler_size);
397 if (handler_base == NULL) {
398 // not enough space left for the handler
399 bailout("exception handler overflow");
400 return -1;
401 }
403 int offset = code_offset();
405 // the exception oop and pc are in rax, and rdx
406 // no other registers need to be preserved, so invalidate them
407 __ invalidate_registers(false, true, true, false, true, true);
409 // check that there is really an exception
410 __ verify_not_null_oop(rax);
412 // search an exception handler (rax: exception oop, rdx: throwing pc)
413 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
414 __ should_not_reach_here();
415 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
416 __ end_a_stub();
418 return offset;
419 }
422 // Emit the code to remove the frame from the stack in the exception
423 // unwind path.
424 int LIR_Assembler::emit_unwind_handler() {
425 #ifndef PRODUCT
426 if (CommentedAssembly) {
427 _masm->block_comment("Unwind handler");
428 }
429 #endif
431 int offset = code_offset();
433 // Fetch the exception from TLS and clear out exception related thread state
434 __ get_thread(rsi);
435 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset()));
436 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
437 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
439 __ bind(_unwind_handler_entry);
440 __ verify_not_null_oop(rax);
441 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
442 __ mov(rsi, rax); // Preserve the exception
443 }
445 // Preform needed unlocking
446 MonitorExitStub* stub = NULL;
447 if (method()->is_synchronized()) {
448 monitor_address(0, FrameMap::rax_opr);
449 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
450 __ unlock_object(rdi, rbx, rax, *stub->entry());
451 __ bind(*stub->continuation());
452 }
454 if (compilation()->env()->dtrace_method_probes()) {
455 __ get_thread(rax);
456 __ movptr(Address(rsp, 0), rax);
457 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
458 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
459 }
461 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
462 __ mov(rax, rsi); // Restore the exception
463 }
465 // remove the activation and dispatch to the unwind handler
466 __ remove_frame(initial_frame_size_in_bytes());
467 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
469 // Emit the slow path assembly
470 if (stub != NULL) {
471 stub->emit_code(this);
472 }
474 return offset;
475 }
478 int LIR_Assembler::emit_deopt_handler() {
479 // if the last instruction is a call (typically to do a throw which
480 // is coming at the end after block reordering) the return address
481 // must still point into the code area in order to avoid assertion
482 // failures when searching for the corresponding bci => add a nop
483 // (was bug 5/14/1999 - gri)
484 __ nop();
486 // generate code for exception handler
487 address handler_base = __ start_a_stub(deopt_handler_size);
488 if (handler_base == NULL) {
489 // not enough space left for the handler
490 bailout("deopt handler overflow");
491 return -1;
492 }
494 int offset = code_offset();
495 InternalAddress here(__ pc());
497 __ pushptr(here.addr());
498 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
499 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
500 __ end_a_stub();
502 return offset;
503 }
506 // This is the fast version of java.lang.String.compare; it has not
507 // OSR-entry and therefore, we generate a slow version for OSR's
508 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
509 __ movptr (rbx, rcx); // receiver is in rcx
510 __ movptr (rax, arg1->as_register());
512 // Get addresses of first characters from both Strings
513 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
514 if (java_lang_String::has_offset_field()) {
515 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
516 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
517 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
518 } else {
519 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
520 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
521 }
523 // rbx, may be NULL
524 add_debug_info_for_null_check_here(info);
525 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
526 if (java_lang_String::has_offset_field()) {
527 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
528 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
529 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
530 } else {
531 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
532 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
533 }
535 // compute minimum length (in rax) and difference of lengths (on top of stack)
536 __ mov (rcx, rbx);
537 __ subptr(rbx, rax); // subtract lengths
538 __ push (rbx); // result
539 __ cmov (Assembler::lessEqual, rax, rcx);
541 // is minimum length 0?
542 Label noLoop, haveResult;
543 __ testptr (rax, rax);
544 __ jcc (Assembler::zero, noLoop);
546 // compare first characters
547 __ load_unsigned_short(rcx, Address(rdi, 0));
548 __ load_unsigned_short(rbx, Address(rsi, 0));
549 __ subl(rcx, rbx);
550 __ jcc(Assembler::notZero, haveResult);
551 // starting loop
552 __ decrement(rax); // we already tested index: skip one
553 __ jcc(Assembler::zero, noLoop);
555 // set rsi.edi to the end of the arrays (arrays have same length)
556 // negate the index
558 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
559 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
560 __ negptr(rax);
562 // compare the strings in a loop
564 Label loop;
565 __ align(wordSize);
566 __ bind(loop);
567 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
568 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
569 __ subl(rcx, rbx);
570 __ jcc(Assembler::notZero, haveResult);
571 __ increment(rax);
572 __ jcc(Assembler::notZero, loop);
574 // strings are equal up to min length
576 __ bind(noLoop);
577 __ pop(rax);
578 return_op(LIR_OprFact::illegalOpr);
580 __ bind(haveResult);
581 // leave instruction is going to discard the TOS value
582 __ mov (rax, rcx); // result of call is in rax,
583 }
586 void LIR_Assembler::return_op(LIR_Opr result) {
587 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
588 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
589 assert(result->fpu() == 0, "result must already be on TOS");
590 }
592 // Pop the stack before the safepoint code
593 __ remove_frame(initial_frame_size_in_bytes());
595 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
597 // Note: we do not need to round double result; float result has the right precision
598 // the poll sets the condition code, but no data registers
599 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
600 relocInfo::poll_return_type);
602 if (Assembler::is_polling_page_far()) {
603 __ lea(rscratch1, polling_page);
604 __ relocate(relocInfo::poll_return_type);
605 __ testl(rax, Address(rscratch1, 0));
606 } else {
607 __ testl(rax, polling_page);
608 }
609 __ ret(0);
610 }
613 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
614 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()),
615 relocInfo::poll_type);
616 guarantee(info != NULL, "Shouldn't be NULL");
617 int offset = __ offset();
618 if (Assembler::is_polling_page_far()) {
619 __ lea(rscratch1, polling_page);
620 offset = __ offset();
621 add_debug_info_for_branch(info);
622 __ testl(rax, Address(rscratch1, 0));
623 } else {
624 add_debug_info_for_branch(info);
625 __ testl(rax, polling_page);
626 }
627 return offset;
628 }
631 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
632 if (from_reg != to_reg) __ mov(to_reg, from_reg);
633 }
635 void LIR_Assembler::swap_reg(Register a, Register b) {
636 __ xchgptr(a, b);
637 }
640 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
641 assert(src->is_constant(), "should not call otherwise");
642 assert(dest->is_register(), "should not call otherwise");
643 LIR_Const* c = src->as_constant_ptr();
645 switch (c->type()) {
646 case T_INT: {
647 assert(patch_code == lir_patch_none, "no patching handled here");
648 __ movl(dest->as_register(), c->as_jint());
649 break;
650 }
652 case T_ADDRESS: {
653 assert(patch_code == lir_patch_none, "no patching handled here");
654 __ movptr(dest->as_register(), c->as_jint());
655 break;
656 }
658 case T_LONG: {
659 assert(patch_code == lir_patch_none, "no patching handled here");
660 #ifdef _LP64
661 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
662 #else
663 __ movptr(dest->as_register_lo(), c->as_jint_lo());
664 __ movptr(dest->as_register_hi(), c->as_jint_hi());
665 #endif // _LP64
666 break;
667 }
669 case T_OBJECT: {
670 if (patch_code != lir_patch_none) {
671 jobject2reg_with_patching(dest->as_register(), info);
672 } else {
673 __ movoop(dest->as_register(), c->as_jobject());
674 }
675 break;
676 }
678 case T_METADATA: {
679 if (patch_code != lir_patch_none) {
680 klass2reg_with_patching(dest->as_register(), info);
681 } else {
682 __ mov_metadata(dest->as_register(), c->as_metadata());
683 }
684 break;
685 }
687 case T_FLOAT: {
688 if (dest->is_single_xmm()) {
689 if (c->is_zero_float()) {
690 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
691 } else {
692 __ movflt(dest->as_xmm_float_reg(),
693 InternalAddress(float_constant(c->as_jfloat())));
694 }
695 } else {
696 assert(dest->is_single_fpu(), "must be");
697 assert(dest->fpu_regnr() == 0, "dest must be TOS");
698 if (c->is_zero_float()) {
699 __ fldz();
700 } else if (c->is_one_float()) {
701 __ fld1();
702 } else {
703 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
704 }
705 }
706 break;
707 }
709 case T_DOUBLE: {
710 if (dest->is_double_xmm()) {
711 if (c->is_zero_double()) {
712 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
713 } else {
714 __ movdbl(dest->as_xmm_double_reg(),
715 InternalAddress(double_constant(c->as_jdouble())));
716 }
717 } else {
718 assert(dest->is_double_fpu(), "must be");
719 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
720 if (c->is_zero_double()) {
721 __ fldz();
722 } else if (c->is_one_double()) {
723 __ fld1();
724 } else {
725 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
726 }
727 }
728 break;
729 }
731 default:
732 ShouldNotReachHere();
733 }
734 }
736 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
737 assert(src->is_constant(), "should not call otherwise");
738 assert(dest->is_stack(), "should not call otherwise");
739 LIR_Const* c = src->as_constant_ptr();
741 switch (c->type()) {
742 case T_INT: // fall through
743 case T_FLOAT:
744 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
745 break;
747 case T_ADDRESS:
748 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
749 break;
751 case T_OBJECT:
752 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
753 break;
755 case T_LONG: // fall through
756 case T_DOUBLE:
757 #ifdef _LP64
758 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
759 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
760 #else
761 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
762 lo_word_offset_in_bytes), c->as_jint_lo_bits());
763 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
764 hi_word_offset_in_bytes), c->as_jint_hi_bits());
765 #endif // _LP64
766 break;
768 default:
769 ShouldNotReachHere();
770 }
771 }
773 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
774 assert(src->is_constant(), "should not call otherwise");
775 assert(dest->is_address(), "should not call otherwise");
776 LIR_Const* c = src->as_constant_ptr();
777 LIR_Address* addr = dest->as_address_ptr();
779 int null_check_here = code_offset();
780 switch (type) {
781 case T_INT: // fall through
782 case T_FLOAT:
783 __ movl(as_Address(addr), c->as_jint_bits());
784 break;
786 case T_ADDRESS:
787 __ movptr(as_Address(addr), c->as_jint_bits());
788 break;
790 case T_OBJECT: // fall through
791 case T_ARRAY:
792 if (c->as_jobject() == NULL) {
793 if (UseCompressedOops && !wide) {
794 __ movl(as_Address(addr), (int32_t)NULL_WORD);
795 } else {
796 __ movptr(as_Address(addr), NULL_WORD);
797 }
798 } else {
799 if (is_literal_address(addr)) {
800 ShouldNotReachHere();
801 __ movoop(as_Address(addr, noreg), c->as_jobject());
802 } else {
803 #ifdef _LP64
804 __ movoop(rscratch1, c->as_jobject());
805 if (UseCompressedOops && !wide) {
806 __ encode_heap_oop(rscratch1);
807 null_check_here = code_offset();
808 __ movl(as_Address_lo(addr), rscratch1);
809 } else {
810 null_check_here = code_offset();
811 __ movptr(as_Address_lo(addr), rscratch1);
812 }
813 #else
814 __ movoop(as_Address(addr), c->as_jobject());
815 #endif
816 }
817 }
818 break;
820 case T_LONG: // fall through
821 case T_DOUBLE:
822 #ifdef _LP64
823 if (is_literal_address(addr)) {
824 ShouldNotReachHere();
825 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
826 } else {
827 __ movptr(r10, (intptr_t)c->as_jlong_bits());
828 null_check_here = code_offset();
829 __ movptr(as_Address_lo(addr), r10);
830 }
831 #else
832 // Always reachable in 32bit so this doesn't produce useless move literal
833 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
834 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
835 #endif // _LP64
836 break;
838 case T_BOOLEAN: // fall through
839 case T_BYTE:
840 __ movb(as_Address(addr), c->as_jint() & 0xFF);
841 break;
843 case T_CHAR: // fall through
844 case T_SHORT:
845 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
846 break;
848 default:
849 ShouldNotReachHere();
850 };
852 if (info != NULL) {
853 add_debug_info_for_null_check(null_check_here, info);
854 }
855 }
858 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
859 assert(src->is_register(), "should not call otherwise");
860 assert(dest->is_register(), "should not call otherwise");
862 // move between cpu-registers
863 if (dest->is_single_cpu()) {
864 #ifdef _LP64
865 if (src->type() == T_LONG) {
866 // Can do LONG -> OBJECT
867 move_regs(src->as_register_lo(), dest->as_register());
868 return;
869 }
870 #endif
871 assert(src->is_single_cpu(), "must match");
872 if (src->type() == T_OBJECT) {
873 __ verify_oop(src->as_register());
874 }
875 move_regs(src->as_register(), dest->as_register());
877 } else if (dest->is_double_cpu()) {
878 #ifdef _LP64
879 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
880 // Surprising to me but we can see move of a long to t_object
881 __ verify_oop(src->as_register());
882 move_regs(src->as_register(), dest->as_register_lo());
883 return;
884 }
885 #endif
886 assert(src->is_double_cpu(), "must match");
887 Register f_lo = src->as_register_lo();
888 Register f_hi = src->as_register_hi();
889 Register t_lo = dest->as_register_lo();
890 Register t_hi = dest->as_register_hi();
891 #ifdef _LP64
892 assert(f_hi == f_lo, "must be same");
893 assert(t_hi == t_lo, "must be same");
894 move_regs(f_lo, t_lo);
895 #else
896 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
899 if (f_lo == t_hi && f_hi == t_lo) {
900 swap_reg(f_lo, f_hi);
901 } else if (f_hi == t_lo) {
902 assert(f_lo != t_hi, "overwriting register");
903 move_regs(f_hi, t_hi);
904 move_regs(f_lo, t_lo);
905 } else {
906 assert(f_hi != t_lo, "overwriting register");
907 move_regs(f_lo, t_lo);
908 move_regs(f_hi, t_hi);
909 }
910 #endif // LP64
912 // special moves from fpu-register to xmm-register
913 // necessary for method results
914 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
915 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
916 __ fld_s(Address(rsp, 0));
917 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
918 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
919 __ fld_d(Address(rsp, 0));
920 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
921 __ fstp_s(Address(rsp, 0));
922 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
923 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
924 __ fstp_d(Address(rsp, 0));
925 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
927 // move between xmm-registers
928 } else if (dest->is_single_xmm()) {
929 assert(src->is_single_xmm(), "must match");
930 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
931 } else if (dest->is_double_xmm()) {
932 assert(src->is_double_xmm(), "must match");
933 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
935 // move between fpu-registers (no instruction necessary because of fpu-stack)
936 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
937 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
938 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
939 } else {
940 ShouldNotReachHere();
941 }
942 }
944 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
945 assert(src->is_register(), "should not call otherwise");
946 assert(dest->is_stack(), "should not call otherwise");
948 if (src->is_single_cpu()) {
949 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
950 if (type == T_OBJECT || type == T_ARRAY) {
951 __ verify_oop(src->as_register());
952 __ movptr (dst, src->as_register());
953 } else if (type == T_METADATA) {
954 __ movptr (dst, src->as_register());
955 } else {
956 __ movl (dst, src->as_register());
957 }
959 } else if (src->is_double_cpu()) {
960 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
961 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
962 __ movptr (dstLO, src->as_register_lo());
963 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
965 } else if (src->is_single_xmm()) {
966 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
967 __ movflt(dst_addr, src->as_xmm_float_reg());
969 } else if (src->is_double_xmm()) {
970 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
971 __ movdbl(dst_addr, src->as_xmm_double_reg());
973 } else if (src->is_single_fpu()) {
974 assert(src->fpu_regnr() == 0, "argument must be on TOS");
975 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
976 if (pop_fpu_stack) __ fstp_s (dst_addr);
977 else __ fst_s (dst_addr);
979 } else if (src->is_double_fpu()) {
980 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
981 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
982 if (pop_fpu_stack) __ fstp_d (dst_addr);
983 else __ fst_d (dst_addr);
985 } else {
986 ShouldNotReachHere();
987 }
988 }
991 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
992 LIR_Address* to_addr = dest->as_address_ptr();
993 PatchingStub* patch = NULL;
994 Register compressed_src = rscratch1;
996 if (type == T_ARRAY || type == T_OBJECT) {
997 __ verify_oop(src->as_register());
998 #ifdef _LP64
999 if (UseCompressedOops && !wide) {
1000 __ movptr(compressed_src, src->as_register());
1001 __ encode_heap_oop(compressed_src);
1002 }
1003 #endif
1004 }
1006 if (patch_code != lir_patch_none) {
1007 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1008 Address toa = as_Address(to_addr);
1009 assert(toa.disp() != 0, "must have");
1010 }
1012 int null_check_here = code_offset();
1013 switch (type) {
1014 case T_FLOAT: {
1015 if (src->is_single_xmm()) {
1016 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1017 } else {
1018 assert(src->is_single_fpu(), "must be");
1019 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1020 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1021 else __ fst_s (as_Address(to_addr));
1022 }
1023 break;
1024 }
1026 case T_DOUBLE: {
1027 if (src->is_double_xmm()) {
1028 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1029 } else {
1030 assert(src->is_double_fpu(), "must be");
1031 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1032 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1033 else __ fst_d (as_Address(to_addr));
1034 }
1035 break;
1036 }
1038 case T_ARRAY: // fall through
1039 case T_OBJECT: // fall through
1040 if (UseCompressedOops && !wide) {
1041 __ movl(as_Address(to_addr), compressed_src);
1042 } else {
1043 __ movptr(as_Address(to_addr), src->as_register());
1044 }
1045 break;
1046 case T_METADATA:
1047 // We get here to store a method pointer to the stack to pass to
1048 // a dtrace runtime call. This can't work on 64 bit with
1049 // compressed klass ptrs: T_METADATA can be a compressed klass
1050 // ptr or a 64 bit method pointer.
1051 LP64_ONLY(ShouldNotReachHere());
1052 __ movptr(as_Address(to_addr), src->as_register());
1053 break;
1054 case T_ADDRESS:
1055 __ movptr(as_Address(to_addr), src->as_register());
1056 break;
1057 case T_INT:
1058 __ movl(as_Address(to_addr), src->as_register());
1059 break;
1061 case T_LONG: {
1062 Register from_lo = src->as_register_lo();
1063 Register from_hi = src->as_register_hi();
1064 #ifdef _LP64
1065 __ movptr(as_Address_lo(to_addr), from_lo);
1066 #else
1067 Register base = to_addr->base()->as_register();
1068 Register index = noreg;
1069 if (to_addr->index()->is_register()) {
1070 index = to_addr->index()->as_register();
1071 }
1072 if (base == from_lo || index == from_lo) {
1073 assert(base != from_hi, "can't be");
1074 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1075 __ movl(as_Address_hi(to_addr), from_hi);
1076 if (patch != NULL) {
1077 patching_epilog(patch, lir_patch_high, base, info);
1078 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1079 patch_code = lir_patch_low;
1080 }
1081 __ movl(as_Address_lo(to_addr), from_lo);
1082 } else {
1083 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1084 __ movl(as_Address_lo(to_addr), from_lo);
1085 if (patch != NULL) {
1086 patching_epilog(patch, lir_patch_low, base, info);
1087 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1088 patch_code = lir_patch_high;
1089 }
1090 __ movl(as_Address_hi(to_addr), from_hi);
1091 }
1092 #endif // _LP64
1093 break;
1094 }
1096 case T_BYTE: // fall through
1097 case T_BOOLEAN: {
1098 Register src_reg = src->as_register();
1099 Address dst_addr = as_Address(to_addr);
1100 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1101 __ movb(dst_addr, src_reg);
1102 break;
1103 }
1105 case T_CHAR: // fall through
1106 case T_SHORT:
1107 __ movw(as_Address(to_addr), src->as_register());
1108 break;
1110 default:
1111 ShouldNotReachHere();
1112 }
1113 if (info != NULL) {
1114 add_debug_info_for_null_check(null_check_here, info);
1115 }
1117 if (patch_code != lir_patch_none) {
1118 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1119 }
1120 }
1123 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1124 assert(src->is_stack(), "should not call otherwise");
1125 assert(dest->is_register(), "should not call otherwise");
1127 if (dest->is_single_cpu()) {
1128 if (type == T_ARRAY || type == T_OBJECT) {
1129 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1130 __ verify_oop(dest->as_register());
1131 } else if (type == T_METADATA) {
1132 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1133 } else {
1134 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1135 }
1137 } else if (dest->is_double_cpu()) {
1138 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1139 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1140 __ movptr(dest->as_register_lo(), src_addr_LO);
1141 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1143 } else if (dest->is_single_xmm()) {
1144 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1145 __ movflt(dest->as_xmm_float_reg(), src_addr);
1147 } else if (dest->is_double_xmm()) {
1148 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1149 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1151 } else if (dest->is_single_fpu()) {
1152 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1153 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1154 __ fld_s(src_addr);
1156 } else if (dest->is_double_fpu()) {
1157 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1158 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1159 __ fld_d(src_addr);
1161 } else {
1162 ShouldNotReachHere();
1163 }
1164 }
1167 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1168 if (src->is_single_stack()) {
1169 if (type == T_OBJECT || type == T_ARRAY) {
1170 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1171 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1172 } else {
1173 #ifndef _LP64
1174 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1175 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1176 #else
1177 //no pushl on 64bits
1178 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1179 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1180 #endif
1181 }
1183 } else if (src->is_double_stack()) {
1184 #ifdef _LP64
1185 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1186 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1187 #else
1188 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1189 // push and pop the part at src + wordSize, adding wordSize for the previous push
1190 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1191 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1192 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1193 #endif // _LP64
1195 } else {
1196 ShouldNotReachHere();
1197 }
1198 }
1201 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1202 assert(src->is_address(), "should not call otherwise");
1203 assert(dest->is_register(), "should not call otherwise");
1205 LIR_Address* addr = src->as_address_ptr();
1206 Address from_addr = as_Address(addr);
1208 switch (type) {
1209 case T_BOOLEAN: // fall through
1210 case T_BYTE: // fall through
1211 case T_CHAR: // fall through
1212 case T_SHORT:
1213 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1214 // on pre P6 processors we may get partial register stalls
1215 // so blow away the value of to_rinfo before loading a
1216 // partial word into it. Do it here so that it precedes
1217 // the potential patch point below.
1218 __ xorptr(dest->as_register(), dest->as_register());
1219 }
1220 break;
1221 }
1223 PatchingStub* patch = NULL;
1224 if (patch_code != lir_patch_none) {
1225 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1226 assert(from_addr.disp() != 0, "must have");
1227 }
1228 if (info != NULL) {
1229 add_debug_info_for_null_check_here(info);
1230 }
1232 switch (type) {
1233 case T_FLOAT: {
1234 if (dest->is_single_xmm()) {
1235 __ movflt(dest->as_xmm_float_reg(), from_addr);
1236 } else {
1237 assert(dest->is_single_fpu(), "must be");
1238 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1239 __ fld_s(from_addr);
1240 }
1241 break;
1242 }
1244 case T_DOUBLE: {
1245 if (dest->is_double_xmm()) {
1246 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1247 } else {
1248 assert(dest->is_double_fpu(), "must be");
1249 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1250 __ fld_d(from_addr);
1251 }
1252 break;
1253 }
1255 case T_OBJECT: // fall through
1256 case T_ARRAY: // fall through
1257 if (UseCompressedOops && !wide) {
1258 __ movl(dest->as_register(), from_addr);
1259 } else {
1260 __ movptr(dest->as_register(), from_addr);
1261 }
1262 break;
1264 case T_ADDRESS:
1265 __ movptr(dest->as_register(), from_addr);
1266 break;
1267 case T_INT:
1268 __ movl(dest->as_register(), from_addr);
1269 break;
1271 case T_LONG: {
1272 Register to_lo = dest->as_register_lo();
1273 Register to_hi = dest->as_register_hi();
1274 #ifdef _LP64
1275 __ movptr(to_lo, as_Address_lo(addr));
1276 #else
1277 Register base = addr->base()->as_register();
1278 Register index = noreg;
1279 if (addr->index()->is_register()) {
1280 index = addr->index()->as_register();
1281 }
1282 if ((base == to_lo && index == to_hi) ||
1283 (base == to_hi && index == to_lo)) {
1284 // addresses with 2 registers are only formed as a result of
1285 // array access so this code will never have to deal with
1286 // patches or null checks.
1287 assert(info == NULL && patch == NULL, "must be");
1288 __ lea(to_hi, as_Address(addr));
1289 __ movl(to_lo, Address(to_hi, 0));
1290 __ movl(to_hi, Address(to_hi, BytesPerWord));
1291 } else if (base == to_lo || index == to_lo) {
1292 assert(base != to_hi, "can't be");
1293 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1294 __ movl(to_hi, as_Address_hi(addr));
1295 if (patch != NULL) {
1296 patching_epilog(patch, lir_patch_high, base, info);
1297 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1298 patch_code = lir_patch_low;
1299 }
1300 __ movl(to_lo, as_Address_lo(addr));
1301 } else {
1302 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1303 __ movl(to_lo, as_Address_lo(addr));
1304 if (patch != NULL) {
1305 patching_epilog(patch, lir_patch_low, base, info);
1306 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1307 patch_code = lir_patch_high;
1308 }
1309 __ movl(to_hi, as_Address_hi(addr));
1310 }
1311 #endif // _LP64
1312 break;
1313 }
1315 case T_BOOLEAN: // fall through
1316 case T_BYTE: {
1317 Register dest_reg = dest->as_register();
1318 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1319 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1320 __ movsbl(dest_reg, from_addr);
1321 } else {
1322 __ movb(dest_reg, from_addr);
1323 __ shll(dest_reg, 24);
1324 __ sarl(dest_reg, 24);
1325 }
1326 break;
1327 }
1329 case T_CHAR: {
1330 Register dest_reg = dest->as_register();
1331 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1332 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1333 __ movzwl(dest_reg, from_addr);
1334 } else {
1335 __ movw(dest_reg, from_addr);
1336 }
1337 break;
1338 }
1340 case T_SHORT: {
1341 Register dest_reg = dest->as_register();
1342 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1343 __ movswl(dest_reg, from_addr);
1344 } else {
1345 __ movw(dest_reg, from_addr);
1346 __ shll(dest_reg, 16);
1347 __ sarl(dest_reg, 16);
1348 }
1349 break;
1350 }
1352 default:
1353 ShouldNotReachHere();
1354 }
1356 if (patch != NULL) {
1357 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1358 }
1360 if (type == T_ARRAY || type == T_OBJECT) {
1361 #ifdef _LP64
1362 if (UseCompressedOops && !wide) {
1363 __ decode_heap_oop(dest->as_register());
1364 }
1365 #endif
1366 __ verify_oop(dest->as_register());
1367 }
1368 }
1371 void LIR_Assembler::prefetchr(LIR_Opr src) {
1372 LIR_Address* addr = src->as_address_ptr();
1373 Address from_addr = as_Address(addr);
1375 if (VM_Version::supports_sse()) {
1376 switch (ReadPrefetchInstr) {
1377 case 0:
1378 __ prefetchnta(from_addr); break;
1379 case 1:
1380 __ prefetcht0(from_addr); break;
1381 case 2:
1382 __ prefetcht2(from_addr); break;
1383 default:
1384 ShouldNotReachHere(); break;
1385 }
1386 } else if (VM_Version::supports_3dnow_prefetch()) {
1387 __ prefetchr(from_addr);
1388 }
1389 }
1392 void LIR_Assembler::prefetchw(LIR_Opr src) {
1393 LIR_Address* addr = src->as_address_ptr();
1394 Address from_addr = as_Address(addr);
1396 if (VM_Version::supports_sse()) {
1397 switch (AllocatePrefetchInstr) {
1398 case 0:
1399 __ prefetchnta(from_addr); break;
1400 case 1:
1401 __ prefetcht0(from_addr); break;
1402 case 2:
1403 __ prefetcht2(from_addr); break;
1404 case 3:
1405 __ prefetchw(from_addr); break;
1406 default:
1407 ShouldNotReachHere(); break;
1408 }
1409 } else if (VM_Version::supports_3dnow_prefetch()) {
1410 __ prefetchw(from_addr);
1411 }
1412 }
1415 NEEDS_CLEANUP; // This could be static?
1416 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1417 int elem_size = type2aelembytes(type);
1418 switch (elem_size) {
1419 case 1: return Address::times_1;
1420 case 2: return Address::times_2;
1421 case 4: return Address::times_4;
1422 case 8: return Address::times_8;
1423 }
1424 ShouldNotReachHere();
1425 return Address::no_scale;
1426 }
1429 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1430 switch (op->code()) {
1431 case lir_idiv:
1432 case lir_irem:
1433 arithmetic_idiv(op->code(),
1434 op->in_opr1(),
1435 op->in_opr2(),
1436 op->in_opr3(),
1437 op->result_opr(),
1438 op->info());
1439 break;
1440 default: ShouldNotReachHere(); break;
1441 }
1442 }
1444 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1445 #ifdef ASSERT
1446 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1447 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1448 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1449 #endif
1451 if (op->cond() == lir_cond_always) {
1452 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1453 __ jmp (*(op->label()));
1454 } else {
1455 Assembler::Condition acond = Assembler::zero;
1456 if (op->code() == lir_cond_float_branch) {
1457 assert(op->ublock() != NULL, "must have unordered successor");
1458 __ jcc(Assembler::parity, *(op->ublock()->label()));
1459 switch(op->cond()) {
1460 case lir_cond_equal: acond = Assembler::equal; break;
1461 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1462 case lir_cond_less: acond = Assembler::below; break;
1463 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1464 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1465 case lir_cond_greater: acond = Assembler::above; break;
1466 default: ShouldNotReachHere();
1467 }
1468 } else {
1469 switch (op->cond()) {
1470 case lir_cond_equal: acond = Assembler::equal; break;
1471 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1472 case lir_cond_less: acond = Assembler::less; break;
1473 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1474 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1475 case lir_cond_greater: acond = Assembler::greater; break;
1476 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1477 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1478 default: ShouldNotReachHere();
1479 }
1480 }
1481 __ jcc(acond,*(op->label()));
1482 }
1483 }
1485 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1486 LIR_Opr src = op->in_opr();
1487 LIR_Opr dest = op->result_opr();
1489 switch (op->bytecode()) {
1490 case Bytecodes::_i2l:
1491 #ifdef _LP64
1492 __ movl2ptr(dest->as_register_lo(), src->as_register());
1493 #else
1494 move_regs(src->as_register(), dest->as_register_lo());
1495 move_regs(src->as_register(), dest->as_register_hi());
1496 __ sarl(dest->as_register_hi(), 31);
1497 #endif // LP64
1498 break;
1500 case Bytecodes::_l2i:
1501 #ifdef _LP64
1502 __ movl(dest->as_register(), src->as_register_lo());
1503 #else
1504 move_regs(src->as_register_lo(), dest->as_register());
1505 #endif
1506 break;
1508 case Bytecodes::_i2b:
1509 move_regs(src->as_register(), dest->as_register());
1510 __ sign_extend_byte(dest->as_register());
1511 break;
1513 case Bytecodes::_i2c:
1514 move_regs(src->as_register(), dest->as_register());
1515 __ andl(dest->as_register(), 0xFFFF);
1516 break;
1518 case Bytecodes::_i2s:
1519 move_regs(src->as_register(), dest->as_register());
1520 __ sign_extend_short(dest->as_register());
1521 break;
1524 case Bytecodes::_f2d:
1525 case Bytecodes::_d2f:
1526 if (dest->is_single_xmm()) {
1527 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1528 } else if (dest->is_double_xmm()) {
1529 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1530 } else {
1531 assert(src->fpu() == dest->fpu(), "register must be equal");
1532 // do nothing (float result is rounded later through spilling)
1533 }
1534 break;
1536 case Bytecodes::_i2f:
1537 case Bytecodes::_i2d:
1538 if (dest->is_single_xmm()) {
1539 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1540 } else if (dest->is_double_xmm()) {
1541 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1542 } else {
1543 assert(dest->fpu() == 0, "result must be on TOS");
1544 __ movl(Address(rsp, 0), src->as_register());
1545 __ fild_s(Address(rsp, 0));
1546 }
1547 break;
1549 case Bytecodes::_f2i:
1550 case Bytecodes::_d2i:
1551 if (src->is_single_xmm()) {
1552 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1553 } else if (src->is_double_xmm()) {
1554 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1555 } else {
1556 assert(src->fpu() == 0, "input must be on TOS");
1557 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1558 __ fist_s(Address(rsp, 0));
1559 __ movl(dest->as_register(), Address(rsp, 0));
1560 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1561 }
1563 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1564 assert(op->stub() != NULL, "stub required");
1565 __ cmpl(dest->as_register(), 0x80000000);
1566 __ jcc(Assembler::equal, *op->stub()->entry());
1567 __ bind(*op->stub()->continuation());
1568 break;
1570 case Bytecodes::_l2f:
1571 case Bytecodes::_l2d:
1572 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1573 assert(dest->fpu() == 0, "result must be on TOS");
1575 __ movptr(Address(rsp, 0), src->as_register_lo());
1576 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1577 __ fild_d(Address(rsp, 0));
1578 // float result is rounded later through spilling
1579 break;
1581 case Bytecodes::_f2l:
1582 case Bytecodes::_d2l:
1583 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1584 assert(src->fpu() == 0, "input must be on TOS");
1585 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1587 // instruction sequence too long to inline it here
1588 {
1589 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1590 }
1591 break;
1593 default: ShouldNotReachHere();
1594 }
1595 }
1597 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1598 if (op->init_check()) {
1599 __ cmpb(Address(op->klass()->as_register(),
1600 InstanceKlass::init_state_offset()),
1601 InstanceKlass::fully_initialized);
1602 add_debug_info_for_null_check_here(op->stub()->info());
1603 __ jcc(Assembler::notEqual, *op->stub()->entry());
1604 }
1605 __ allocate_object(op->obj()->as_register(),
1606 op->tmp1()->as_register(),
1607 op->tmp2()->as_register(),
1608 op->header_size(),
1609 op->object_size(),
1610 op->klass()->as_register(),
1611 *op->stub()->entry());
1612 __ bind(*op->stub()->continuation());
1613 }
1615 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1616 Register len = op->len()->as_register();
1617 LP64_ONLY( __ movslq(len, len); )
1619 if (UseSlowPath ||
1620 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1621 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1622 __ jmp(*op->stub()->entry());
1623 } else {
1624 Register tmp1 = op->tmp1()->as_register();
1625 Register tmp2 = op->tmp2()->as_register();
1626 Register tmp3 = op->tmp3()->as_register();
1627 if (len == tmp1) {
1628 tmp1 = tmp3;
1629 } else if (len == tmp2) {
1630 tmp2 = tmp3;
1631 } else if (len == tmp3) {
1632 // everything is ok
1633 } else {
1634 __ mov(tmp3, len);
1635 }
1636 __ allocate_array(op->obj()->as_register(),
1637 len,
1638 tmp1,
1639 tmp2,
1640 arrayOopDesc::header_size(op->type()),
1641 array_element_size(op->type()),
1642 op->klass()->as_register(),
1643 *op->stub()->entry());
1644 }
1645 __ bind(*op->stub()->continuation());
1646 }
1648 void LIR_Assembler::type_profile_helper(Register mdo,
1649 ciMethodData *md, ciProfileData *data,
1650 Register recv, Label* update_done) {
1651 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1652 Label next_test;
1653 // See if the receiver is receiver[n].
1654 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1655 __ jccb(Assembler::notEqual, next_test);
1656 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1657 __ addptr(data_addr, DataLayout::counter_increment);
1658 __ jmp(*update_done);
1659 __ bind(next_test);
1660 }
1662 // Didn't find receiver; find next empty slot and fill it in
1663 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1664 Label next_test;
1665 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1666 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1667 __ jccb(Assembler::notEqual, next_test);
1668 __ movptr(recv_addr, recv);
1669 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1670 __ jmp(*update_done);
1671 __ bind(next_test);
1672 }
1673 }
1675 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1676 // we always need a stub for the failure case.
1677 CodeStub* stub = op->stub();
1678 Register obj = op->object()->as_register();
1679 Register k_RInfo = op->tmp1()->as_register();
1680 Register klass_RInfo = op->tmp2()->as_register();
1681 Register dst = op->result_opr()->as_register();
1682 ciKlass* k = op->klass();
1683 Register Rtmp1 = noreg;
1685 // check if it needs to be profiled
1686 ciMethodData* md;
1687 ciProfileData* data;
1689 if (op->should_profile()) {
1690 ciMethod* method = op->profiled_method();
1691 assert(method != NULL, "Should have method");
1692 int bci = op->profiled_bci();
1693 md = method->method_data_or_null();
1694 assert(md != NULL, "Sanity");
1695 data = md->bci_to_data(bci);
1696 assert(data != NULL, "need data for type check");
1697 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1698 }
1699 Label profile_cast_success, profile_cast_failure;
1700 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1701 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1703 if (obj == k_RInfo) {
1704 k_RInfo = dst;
1705 } else if (obj == klass_RInfo) {
1706 klass_RInfo = dst;
1707 }
1708 if (k->is_loaded() && !UseCompressedOops) {
1709 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1710 } else {
1711 Rtmp1 = op->tmp3()->as_register();
1712 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1713 }
1715 assert_different_registers(obj, k_RInfo, klass_RInfo);
1716 if (!k->is_loaded()) {
1717 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1718 } else {
1719 #ifdef _LP64
1720 __ mov_metadata(k_RInfo, k->constant_encoding());
1721 #endif // _LP64
1722 }
1723 assert(obj != k_RInfo, "must be different");
1725 __ cmpptr(obj, (int32_t)NULL_WORD);
1726 if (op->should_profile()) {
1727 Label not_null;
1728 __ jccb(Assembler::notEqual, not_null);
1729 // Object is null; update MDO and exit
1730 Register mdo = klass_RInfo;
1731 __ mov_metadata(mdo, md->constant_encoding());
1732 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1733 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1734 __ orl(data_addr, header_bits);
1735 __ jmp(*obj_is_null);
1736 __ bind(not_null);
1737 } else {
1738 __ jcc(Assembler::equal, *obj_is_null);
1739 }
1740 __ verify_oop(obj);
1742 if (op->fast_check()) {
1743 // get object class
1744 // not a safepoint as obj null check happens earlier
1745 #ifdef _LP64
1746 if (UseCompressedKlassPointers) {
1747 __ load_klass(Rtmp1, obj);
1748 __ cmpptr(k_RInfo, Rtmp1);
1749 } else {
1750 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1751 }
1752 #else
1753 if (k->is_loaded()) {
1754 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1755 } else {
1756 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1757 }
1758 #endif
1759 __ jcc(Assembler::notEqual, *failure_target);
1760 // successful cast, fall through to profile or jump
1761 } else {
1762 // get object class
1763 // not a safepoint as obj null check happens earlier
1764 __ load_klass(klass_RInfo, obj);
1765 if (k->is_loaded()) {
1766 // See if we get an immediate positive hit
1767 #ifdef _LP64
1768 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1769 #else
1770 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1771 #endif // _LP64
1772 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1773 __ jcc(Assembler::notEqual, *failure_target);
1774 // successful cast, fall through to profile or jump
1775 } else {
1776 // See if we get an immediate positive hit
1777 __ jcc(Assembler::equal, *success_target);
1778 // check for self
1779 #ifdef _LP64
1780 __ cmpptr(klass_RInfo, k_RInfo);
1781 #else
1782 __ cmpklass(klass_RInfo, k->constant_encoding());
1783 #endif // _LP64
1784 __ jcc(Assembler::equal, *success_target);
1786 __ push(klass_RInfo);
1787 #ifdef _LP64
1788 __ push(k_RInfo);
1789 #else
1790 __ pushklass(k->constant_encoding());
1791 #endif // _LP64
1792 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1793 __ pop(klass_RInfo);
1794 __ pop(klass_RInfo);
1795 // result is a boolean
1796 __ cmpl(klass_RInfo, 0);
1797 __ jcc(Assembler::equal, *failure_target);
1798 // successful cast, fall through to profile or jump
1799 }
1800 } else {
1801 // perform the fast part of the checking logic
1802 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1803 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1804 __ push(klass_RInfo);
1805 __ push(k_RInfo);
1806 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1807 __ pop(klass_RInfo);
1808 __ pop(k_RInfo);
1809 // result is a boolean
1810 __ cmpl(k_RInfo, 0);
1811 __ jcc(Assembler::equal, *failure_target);
1812 // successful cast, fall through to profile or jump
1813 }
1814 }
1815 if (op->should_profile()) {
1816 Register mdo = klass_RInfo, recv = k_RInfo;
1817 __ bind(profile_cast_success);
1818 __ mov_metadata(mdo, md->constant_encoding());
1819 __ load_klass(recv, obj);
1820 Label update_done;
1821 type_profile_helper(mdo, md, data, recv, success);
1822 __ jmp(*success);
1824 __ bind(profile_cast_failure);
1825 __ mov_metadata(mdo, md->constant_encoding());
1826 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1827 __ subptr(counter_addr, DataLayout::counter_increment);
1828 __ jmp(*failure);
1829 }
1830 __ jmp(*success);
1831 }
1834 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1835 LIR_Code code = op->code();
1836 if (code == lir_store_check) {
1837 Register value = op->object()->as_register();
1838 Register array = op->array()->as_register();
1839 Register k_RInfo = op->tmp1()->as_register();
1840 Register klass_RInfo = op->tmp2()->as_register();
1841 Register Rtmp1 = op->tmp3()->as_register();
1843 CodeStub* stub = op->stub();
1845 // check if it needs to be profiled
1846 ciMethodData* md;
1847 ciProfileData* data;
1849 if (op->should_profile()) {
1850 ciMethod* method = op->profiled_method();
1851 assert(method != NULL, "Should have method");
1852 int bci = op->profiled_bci();
1853 md = method->method_data_or_null();
1854 assert(md != NULL, "Sanity");
1855 data = md->bci_to_data(bci);
1856 assert(data != NULL, "need data for type check");
1857 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1858 }
1859 Label profile_cast_success, profile_cast_failure, done;
1860 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1861 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1863 __ cmpptr(value, (int32_t)NULL_WORD);
1864 if (op->should_profile()) {
1865 Label not_null;
1866 __ jccb(Assembler::notEqual, not_null);
1867 // Object is null; update MDO and exit
1868 Register mdo = klass_RInfo;
1869 __ mov_metadata(mdo, md->constant_encoding());
1870 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1871 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1872 __ orl(data_addr, header_bits);
1873 __ jmp(done);
1874 __ bind(not_null);
1875 } else {
1876 __ jcc(Assembler::equal, done);
1877 }
1879 add_debug_info_for_null_check_here(op->info_for_exception());
1880 __ load_klass(k_RInfo, array);
1881 __ load_klass(klass_RInfo, value);
1883 // get instance klass (it's already uncompressed)
1884 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset()));
1885 // perform the fast part of the checking logic
1886 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1887 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1888 __ push(klass_RInfo);
1889 __ push(k_RInfo);
1890 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1891 __ pop(klass_RInfo);
1892 __ pop(k_RInfo);
1893 // result is a boolean
1894 __ cmpl(k_RInfo, 0);
1895 __ jcc(Assembler::equal, *failure_target);
1896 // fall through to the success case
1898 if (op->should_profile()) {
1899 Register mdo = klass_RInfo, recv = k_RInfo;
1900 __ bind(profile_cast_success);
1901 __ mov_metadata(mdo, md->constant_encoding());
1902 __ load_klass(recv, value);
1903 Label update_done;
1904 type_profile_helper(mdo, md, data, recv, &done);
1905 __ jmpb(done);
1907 __ bind(profile_cast_failure);
1908 __ mov_metadata(mdo, md->constant_encoding());
1909 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1910 __ subptr(counter_addr, DataLayout::counter_increment);
1911 __ jmp(*stub->entry());
1912 }
1914 __ bind(done);
1915 } else
1916 if (code == lir_checkcast) {
1917 Register obj = op->object()->as_register();
1918 Register dst = op->result_opr()->as_register();
1919 Label success;
1920 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1921 __ bind(success);
1922 if (dst != obj) {
1923 __ mov(dst, obj);
1924 }
1925 } else
1926 if (code == lir_instanceof) {
1927 Register obj = op->object()->as_register();
1928 Register dst = op->result_opr()->as_register();
1929 Label success, failure, done;
1930 emit_typecheck_helper(op, &success, &failure, &failure);
1931 __ bind(failure);
1932 __ xorptr(dst, dst);
1933 __ jmpb(done);
1934 __ bind(success);
1935 __ movptr(dst, 1);
1936 __ bind(done);
1937 } else {
1938 ShouldNotReachHere();
1939 }
1941 }
1944 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1945 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1946 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1947 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1948 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1949 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1950 Register addr = op->addr()->as_register();
1951 if (os::is_MP()) {
1952 __ lock();
1953 }
1954 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1956 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1957 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1958 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1959 Register newval = op->new_value()->as_register();
1960 Register cmpval = op->cmp_value()->as_register();
1961 assert(cmpval == rax, "wrong register");
1962 assert(newval != NULL, "new val must be register");
1963 assert(cmpval != newval, "cmp and new values must be in different registers");
1964 assert(cmpval != addr, "cmp and addr must be in different registers");
1965 assert(newval != addr, "new value and addr must be in different registers");
1967 if ( op->code() == lir_cas_obj) {
1968 #ifdef _LP64
1969 if (UseCompressedOops) {
1970 __ encode_heap_oop(cmpval);
1971 __ mov(rscratch1, newval);
1972 __ encode_heap_oop(rscratch1);
1973 if (os::is_MP()) {
1974 __ lock();
1975 }
1976 // cmpval (rax) is implicitly used by this instruction
1977 __ cmpxchgl(rscratch1, Address(addr, 0));
1978 } else
1979 #endif
1980 {
1981 if (os::is_MP()) {
1982 __ lock();
1983 }
1984 __ cmpxchgptr(newval, Address(addr, 0));
1985 }
1986 } else {
1987 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1988 if (os::is_MP()) {
1989 __ lock();
1990 }
1991 __ cmpxchgl(newval, Address(addr, 0));
1992 }
1993 #ifdef _LP64
1994 } else if (op->code() == lir_cas_long) {
1995 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1996 Register newval = op->new_value()->as_register_lo();
1997 Register cmpval = op->cmp_value()->as_register_lo();
1998 assert(cmpval == rax, "wrong register");
1999 assert(newval != NULL, "new val must be register");
2000 assert(cmpval != newval, "cmp and new values must be in different registers");
2001 assert(cmpval != addr, "cmp and addr must be in different registers");
2002 assert(newval != addr, "new value and addr must be in different registers");
2003 if (os::is_MP()) {
2004 __ lock();
2005 }
2006 __ cmpxchgq(newval, Address(addr, 0));
2007 #endif // _LP64
2008 } else {
2009 Unimplemented();
2010 }
2011 }
2013 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2014 Assembler::Condition acond, ncond;
2015 switch (condition) {
2016 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2017 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2018 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2019 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2020 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2021 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2022 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2023 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2024 default: ShouldNotReachHere();
2025 }
2027 if (opr1->is_cpu_register()) {
2028 reg2reg(opr1, result);
2029 } else if (opr1->is_stack()) {
2030 stack2reg(opr1, result, result->type());
2031 } else if (opr1->is_constant()) {
2032 const2reg(opr1, result, lir_patch_none, NULL);
2033 } else {
2034 ShouldNotReachHere();
2035 }
2037 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2038 // optimized version that does not require a branch
2039 if (opr2->is_single_cpu()) {
2040 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2041 __ cmov(ncond, result->as_register(), opr2->as_register());
2042 } else if (opr2->is_double_cpu()) {
2043 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2044 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2045 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2046 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2047 } else if (opr2->is_single_stack()) {
2048 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2049 } else if (opr2->is_double_stack()) {
2050 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2051 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2052 } else {
2053 ShouldNotReachHere();
2054 }
2056 } else {
2057 Label skip;
2058 __ jcc (acond, skip);
2059 if (opr2->is_cpu_register()) {
2060 reg2reg(opr2, result);
2061 } else if (opr2->is_stack()) {
2062 stack2reg(opr2, result, result->type());
2063 } else if (opr2->is_constant()) {
2064 const2reg(opr2, result, lir_patch_none, NULL);
2065 } else {
2066 ShouldNotReachHere();
2067 }
2068 __ bind(skip);
2069 }
2070 }
2073 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2074 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2076 if (left->is_single_cpu()) {
2077 assert(left == dest, "left and dest must be equal");
2078 Register lreg = left->as_register();
2080 if (right->is_single_cpu()) {
2081 // cpu register - cpu register
2082 Register rreg = right->as_register();
2083 switch (code) {
2084 case lir_add: __ addl (lreg, rreg); break;
2085 case lir_sub: __ subl (lreg, rreg); break;
2086 case lir_mul: __ imull(lreg, rreg); break;
2087 default: ShouldNotReachHere();
2088 }
2090 } else if (right->is_stack()) {
2091 // cpu register - stack
2092 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2093 switch (code) {
2094 case lir_add: __ addl(lreg, raddr); break;
2095 case lir_sub: __ subl(lreg, raddr); break;
2096 default: ShouldNotReachHere();
2097 }
2099 } else if (right->is_constant()) {
2100 // cpu register - constant
2101 jint c = right->as_constant_ptr()->as_jint();
2102 switch (code) {
2103 case lir_add: {
2104 __ incrementl(lreg, c);
2105 break;
2106 }
2107 case lir_sub: {
2108 __ decrementl(lreg, c);
2109 break;
2110 }
2111 default: ShouldNotReachHere();
2112 }
2114 } else {
2115 ShouldNotReachHere();
2116 }
2118 } else if (left->is_double_cpu()) {
2119 assert(left == dest, "left and dest must be equal");
2120 Register lreg_lo = left->as_register_lo();
2121 Register lreg_hi = left->as_register_hi();
2123 if (right->is_double_cpu()) {
2124 // cpu register - cpu register
2125 Register rreg_lo = right->as_register_lo();
2126 Register rreg_hi = right->as_register_hi();
2127 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2128 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2129 switch (code) {
2130 case lir_add:
2131 __ addptr(lreg_lo, rreg_lo);
2132 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2133 break;
2134 case lir_sub:
2135 __ subptr(lreg_lo, rreg_lo);
2136 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2137 break;
2138 case lir_mul:
2139 #ifdef _LP64
2140 __ imulq(lreg_lo, rreg_lo);
2141 #else
2142 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2143 __ imull(lreg_hi, rreg_lo);
2144 __ imull(rreg_hi, lreg_lo);
2145 __ addl (rreg_hi, lreg_hi);
2146 __ mull (rreg_lo);
2147 __ addl (lreg_hi, rreg_hi);
2148 #endif // _LP64
2149 break;
2150 default:
2151 ShouldNotReachHere();
2152 }
2154 } else if (right->is_constant()) {
2155 // cpu register - constant
2156 #ifdef _LP64
2157 jlong c = right->as_constant_ptr()->as_jlong_bits();
2158 __ movptr(r10, (intptr_t) c);
2159 switch (code) {
2160 case lir_add:
2161 __ addptr(lreg_lo, r10);
2162 break;
2163 case lir_sub:
2164 __ subptr(lreg_lo, r10);
2165 break;
2166 default:
2167 ShouldNotReachHere();
2168 }
2169 #else
2170 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2171 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2172 switch (code) {
2173 case lir_add:
2174 __ addptr(lreg_lo, c_lo);
2175 __ adcl(lreg_hi, c_hi);
2176 break;
2177 case lir_sub:
2178 __ subptr(lreg_lo, c_lo);
2179 __ sbbl(lreg_hi, c_hi);
2180 break;
2181 default:
2182 ShouldNotReachHere();
2183 }
2184 #endif // _LP64
2186 } else {
2187 ShouldNotReachHere();
2188 }
2190 } else if (left->is_single_xmm()) {
2191 assert(left == dest, "left and dest must be equal");
2192 XMMRegister lreg = left->as_xmm_float_reg();
2194 if (right->is_single_xmm()) {
2195 XMMRegister rreg = right->as_xmm_float_reg();
2196 switch (code) {
2197 case lir_add: __ addss(lreg, rreg); break;
2198 case lir_sub: __ subss(lreg, rreg); break;
2199 case lir_mul_strictfp: // fall through
2200 case lir_mul: __ mulss(lreg, rreg); break;
2201 case lir_div_strictfp: // fall through
2202 case lir_div: __ divss(lreg, rreg); break;
2203 default: ShouldNotReachHere();
2204 }
2205 } else {
2206 Address raddr;
2207 if (right->is_single_stack()) {
2208 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2209 } else if (right->is_constant()) {
2210 // hack for now
2211 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2212 } else {
2213 ShouldNotReachHere();
2214 }
2215 switch (code) {
2216 case lir_add: __ addss(lreg, raddr); break;
2217 case lir_sub: __ subss(lreg, raddr); break;
2218 case lir_mul_strictfp: // fall through
2219 case lir_mul: __ mulss(lreg, raddr); break;
2220 case lir_div_strictfp: // fall through
2221 case lir_div: __ divss(lreg, raddr); break;
2222 default: ShouldNotReachHere();
2223 }
2224 }
2226 } else if (left->is_double_xmm()) {
2227 assert(left == dest, "left and dest must be equal");
2229 XMMRegister lreg = left->as_xmm_double_reg();
2230 if (right->is_double_xmm()) {
2231 XMMRegister rreg = right->as_xmm_double_reg();
2232 switch (code) {
2233 case lir_add: __ addsd(lreg, rreg); break;
2234 case lir_sub: __ subsd(lreg, rreg); break;
2235 case lir_mul_strictfp: // fall through
2236 case lir_mul: __ mulsd(lreg, rreg); break;
2237 case lir_div_strictfp: // fall through
2238 case lir_div: __ divsd(lreg, rreg); break;
2239 default: ShouldNotReachHere();
2240 }
2241 } else {
2242 Address raddr;
2243 if (right->is_double_stack()) {
2244 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2245 } else if (right->is_constant()) {
2246 // hack for now
2247 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2248 } else {
2249 ShouldNotReachHere();
2250 }
2251 switch (code) {
2252 case lir_add: __ addsd(lreg, raddr); break;
2253 case lir_sub: __ subsd(lreg, raddr); break;
2254 case lir_mul_strictfp: // fall through
2255 case lir_mul: __ mulsd(lreg, raddr); break;
2256 case lir_div_strictfp: // fall through
2257 case lir_div: __ divsd(lreg, raddr); break;
2258 default: ShouldNotReachHere();
2259 }
2260 }
2262 } else if (left->is_single_fpu()) {
2263 assert(dest->is_single_fpu(), "fpu stack allocation required");
2265 if (right->is_single_fpu()) {
2266 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2268 } else {
2269 assert(left->fpu_regnr() == 0, "left must be on TOS");
2270 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2272 Address raddr;
2273 if (right->is_single_stack()) {
2274 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2275 } else if (right->is_constant()) {
2276 address const_addr = float_constant(right->as_jfloat());
2277 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2278 // hack for now
2279 raddr = __ as_Address(InternalAddress(const_addr));
2280 } else {
2281 ShouldNotReachHere();
2282 }
2284 switch (code) {
2285 case lir_add: __ fadd_s(raddr); break;
2286 case lir_sub: __ fsub_s(raddr); break;
2287 case lir_mul_strictfp: // fall through
2288 case lir_mul: __ fmul_s(raddr); break;
2289 case lir_div_strictfp: // fall through
2290 case lir_div: __ fdiv_s(raddr); break;
2291 default: ShouldNotReachHere();
2292 }
2293 }
2295 } else if (left->is_double_fpu()) {
2296 assert(dest->is_double_fpu(), "fpu stack allocation required");
2298 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2299 // Double values require special handling for strictfp mul/div on x86
2300 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2301 __ fmulp(left->fpu_regnrLo() + 1);
2302 }
2304 if (right->is_double_fpu()) {
2305 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2307 } else {
2308 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2309 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2311 Address raddr;
2312 if (right->is_double_stack()) {
2313 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2314 } else if (right->is_constant()) {
2315 // hack for now
2316 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2317 } else {
2318 ShouldNotReachHere();
2319 }
2321 switch (code) {
2322 case lir_add: __ fadd_d(raddr); break;
2323 case lir_sub: __ fsub_d(raddr); break;
2324 case lir_mul_strictfp: // fall through
2325 case lir_mul: __ fmul_d(raddr); break;
2326 case lir_div_strictfp: // fall through
2327 case lir_div: __ fdiv_d(raddr); break;
2328 default: ShouldNotReachHere();
2329 }
2330 }
2332 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2333 // Double values require special handling for strictfp mul/div on x86
2334 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2335 __ fmulp(dest->fpu_regnrLo() + 1);
2336 }
2338 } else if (left->is_single_stack() || left->is_address()) {
2339 assert(left == dest, "left and dest must be equal");
2341 Address laddr;
2342 if (left->is_single_stack()) {
2343 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2344 } else if (left->is_address()) {
2345 laddr = as_Address(left->as_address_ptr());
2346 } else {
2347 ShouldNotReachHere();
2348 }
2350 if (right->is_single_cpu()) {
2351 Register rreg = right->as_register();
2352 switch (code) {
2353 case lir_add: __ addl(laddr, rreg); break;
2354 case lir_sub: __ subl(laddr, rreg); break;
2355 default: ShouldNotReachHere();
2356 }
2357 } else if (right->is_constant()) {
2358 jint c = right->as_constant_ptr()->as_jint();
2359 switch (code) {
2360 case lir_add: {
2361 __ incrementl(laddr, c);
2362 break;
2363 }
2364 case lir_sub: {
2365 __ decrementl(laddr, c);
2366 break;
2367 }
2368 default: ShouldNotReachHere();
2369 }
2370 } else {
2371 ShouldNotReachHere();
2372 }
2374 } else {
2375 ShouldNotReachHere();
2376 }
2377 }
2379 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2380 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2381 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2382 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2384 bool left_is_tos = (left_index == 0);
2385 bool dest_is_tos = (dest_index == 0);
2386 int non_tos_index = (left_is_tos ? right_index : left_index);
2388 switch (code) {
2389 case lir_add:
2390 if (pop_fpu_stack) __ faddp(non_tos_index);
2391 else if (dest_is_tos) __ fadd (non_tos_index);
2392 else __ fadda(non_tos_index);
2393 break;
2395 case lir_sub:
2396 if (left_is_tos) {
2397 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2398 else if (dest_is_tos) __ fsub (non_tos_index);
2399 else __ fsubra(non_tos_index);
2400 } else {
2401 if (pop_fpu_stack) __ fsubp (non_tos_index);
2402 else if (dest_is_tos) __ fsubr (non_tos_index);
2403 else __ fsuba (non_tos_index);
2404 }
2405 break;
2407 case lir_mul_strictfp: // fall through
2408 case lir_mul:
2409 if (pop_fpu_stack) __ fmulp(non_tos_index);
2410 else if (dest_is_tos) __ fmul (non_tos_index);
2411 else __ fmula(non_tos_index);
2412 break;
2414 case lir_div_strictfp: // fall through
2415 case lir_div:
2416 if (left_is_tos) {
2417 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2418 else if (dest_is_tos) __ fdiv (non_tos_index);
2419 else __ fdivra(non_tos_index);
2420 } else {
2421 if (pop_fpu_stack) __ fdivp (non_tos_index);
2422 else if (dest_is_tos) __ fdivr (non_tos_index);
2423 else __ fdiva (non_tos_index);
2424 }
2425 break;
2427 case lir_rem:
2428 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2429 __ fremr(noreg);
2430 break;
2432 default:
2433 ShouldNotReachHere();
2434 }
2435 }
2438 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2439 if (value->is_double_xmm()) {
2440 switch(code) {
2441 case lir_abs :
2442 {
2443 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2444 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2445 }
2446 __ andpd(dest->as_xmm_double_reg(),
2447 ExternalAddress((address)double_signmask_pool));
2448 }
2449 break;
2451 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2452 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2453 default : ShouldNotReachHere();
2454 }
2456 } else if (value->is_double_fpu()) {
2457 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2458 switch(code) {
2459 case lir_log : __ flog() ; break;
2460 case lir_log10 : __ flog10() ; break;
2461 case lir_abs : __ fabs() ; break;
2462 case lir_sqrt : __ fsqrt(); break;
2463 case lir_sin :
2464 // Should consider not saving rbx, if not necessary
2465 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2466 break;
2467 case lir_cos :
2468 // Should consider not saving rbx, if not necessary
2469 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2470 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2471 break;
2472 case lir_tan :
2473 // Should consider not saving rbx, if not necessary
2474 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2475 break;
2476 case lir_exp :
2477 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2478 break;
2479 case lir_pow :
2480 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2481 break;
2482 default : ShouldNotReachHere();
2483 }
2484 } else {
2485 Unimplemented();
2486 }
2487 }
2489 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2490 // assert(left->destroys_register(), "check");
2491 if (left->is_single_cpu()) {
2492 Register reg = left->as_register();
2493 if (right->is_constant()) {
2494 int val = right->as_constant_ptr()->as_jint();
2495 switch (code) {
2496 case lir_logic_and: __ andl (reg, val); break;
2497 case lir_logic_or: __ orl (reg, val); break;
2498 case lir_logic_xor: __ xorl (reg, val); break;
2499 default: ShouldNotReachHere();
2500 }
2501 } else if (right->is_stack()) {
2502 // added support for stack operands
2503 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2504 switch (code) {
2505 case lir_logic_and: __ andl (reg, raddr); break;
2506 case lir_logic_or: __ orl (reg, raddr); break;
2507 case lir_logic_xor: __ xorl (reg, raddr); break;
2508 default: ShouldNotReachHere();
2509 }
2510 } else {
2511 Register rright = right->as_register();
2512 switch (code) {
2513 case lir_logic_and: __ andptr (reg, rright); break;
2514 case lir_logic_or : __ orptr (reg, rright); break;
2515 case lir_logic_xor: __ xorptr (reg, rright); break;
2516 default: ShouldNotReachHere();
2517 }
2518 }
2519 move_regs(reg, dst->as_register());
2520 } else {
2521 Register l_lo = left->as_register_lo();
2522 Register l_hi = left->as_register_hi();
2523 if (right->is_constant()) {
2524 #ifdef _LP64
2525 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2526 switch (code) {
2527 case lir_logic_and:
2528 __ andq(l_lo, rscratch1);
2529 break;
2530 case lir_logic_or:
2531 __ orq(l_lo, rscratch1);
2532 break;
2533 case lir_logic_xor:
2534 __ xorq(l_lo, rscratch1);
2535 break;
2536 default: ShouldNotReachHere();
2537 }
2538 #else
2539 int r_lo = right->as_constant_ptr()->as_jint_lo();
2540 int r_hi = right->as_constant_ptr()->as_jint_hi();
2541 switch (code) {
2542 case lir_logic_and:
2543 __ andl(l_lo, r_lo);
2544 __ andl(l_hi, r_hi);
2545 break;
2546 case lir_logic_or:
2547 __ orl(l_lo, r_lo);
2548 __ orl(l_hi, r_hi);
2549 break;
2550 case lir_logic_xor:
2551 __ xorl(l_lo, r_lo);
2552 __ xorl(l_hi, r_hi);
2553 break;
2554 default: ShouldNotReachHere();
2555 }
2556 #endif // _LP64
2557 } else {
2558 #ifdef _LP64
2559 Register r_lo;
2560 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2561 r_lo = right->as_register();
2562 } else {
2563 r_lo = right->as_register_lo();
2564 }
2565 #else
2566 Register r_lo = right->as_register_lo();
2567 Register r_hi = right->as_register_hi();
2568 assert(l_lo != r_hi, "overwriting registers");
2569 #endif
2570 switch (code) {
2571 case lir_logic_and:
2572 __ andptr(l_lo, r_lo);
2573 NOT_LP64(__ andptr(l_hi, r_hi);)
2574 break;
2575 case lir_logic_or:
2576 __ orptr(l_lo, r_lo);
2577 NOT_LP64(__ orptr(l_hi, r_hi);)
2578 break;
2579 case lir_logic_xor:
2580 __ xorptr(l_lo, r_lo);
2581 NOT_LP64(__ xorptr(l_hi, r_hi);)
2582 break;
2583 default: ShouldNotReachHere();
2584 }
2585 }
2587 Register dst_lo = dst->as_register_lo();
2588 Register dst_hi = dst->as_register_hi();
2590 #ifdef _LP64
2591 move_regs(l_lo, dst_lo);
2592 #else
2593 if (dst_lo == l_hi) {
2594 assert(dst_hi != l_lo, "overwriting registers");
2595 move_regs(l_hi, dst_hi);
2596 move_regs(l_lo, dst_lo);
2597 } else {
2598 assert(dst_lo != l_hi, "overwriting registers");
2599 move_regs(l_lo, dst_lo);
2600 move_regs(l_hi, dst_hi);
2601 }
2602 #endif // _LP64
2603 }
2604 }
2607 // we assume that rax, and rdx can be overwritten
2608 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2610 assert(left->is_single_cpu(), "left must be register");
2611 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2612 assert(result->is_single_cpu(), "result must be register");
2614 // assert(left->destroys_register(), "check");
2615 // assert(right->destroys_register(), "check");
2617 Register lreg = left->as_register();
2618 Register dreg = result->as_register();
2620 if (right->is_constant()) {
2621 int divisor = right->as_constant_ptr()->as_jint();
2622 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2623 if (code == lir_idiv) {
2624 assert(lreg == rax, "must be rax,");
2625 assert(temp->as_register() == rdx, "tmp register must be rdx");
2626 __ cdql(); // sign extend into rdx:rax
2627 if (divisor == 2) {
2628 __ subl(lreg, rdx);
2629 } else {
2630 __ andl(rdx, divisor - 1);
2631 __ addl(lreg, rdx);
2632 }
2633 __ sarl(lreg, log2_intptr(divisor));
2634 move_regs(lreg, dreg);
2635 } else if (code == lir_irem) {
2636 Label done;
2637 __ mov(dreg, lreg);
2638 __ andl(dreg, 0x80000000 | (divisor - 1));
2639 __ jcc(Assembler::positive, done);
2640 __ decrement(dreg);
2641 __ orl(dreg, ~(divisor - 1));
2642 __ increment(dreg);
2643 __ bind(done);
2644 } else {
2645 ShouldNotReachHere();
2646 }
2647 } else {
2648 Register rreg = right->as_register();
2649 assert(lreg == rax, "left register must be rax,");
2650 assert(rreg != rdx, "right register must not be rdx");
2651 assert(temp->as_register() == rdx, "tmp register must be rdx");
2653 move_regs(lreg, rax);
2655 int idivl_offset = __ corrected_idivl(rreg);
2656 add_debug_info_for_div0(idivl_offset, info);
2657 if (code == lir_irem) {
2658 move_regs(rdx, dreg); // result is in rdx
2659 } else {
2660 move_regs(rax, dreg);
2661 }
2662 }
2663 }
2666 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2667 if (opr1->is_single_cpu()) {
2668 Register reg1 = opr1->as_register();
2669 if (opr2->is_single_cpu()) {
2670 // cpu register - cpu register
2671 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2672 __ cmpptr(reg1, opr2->as_register());
2673 } else {
2674 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2675 __ cmpl(reg1, opr2->as_register());
2676 }
2677 } else if (opr2->is_stack()) {
2678 // cpu register - stack
2679 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2680 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2681 } else {
2682 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2683 }
2684 } else if (opr2->is_constant()) {
2685 // cpu register - constant
2686 LIR_Const* c = opr2->as_constant_ptr();
2687 if (c->type() == T_INT) {
2688 __ cmpl(reg1, c->as_jint());
2689 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2690 // In 64bit oops are single register
2691 jobject o = c->as_jobject();
2692 if (o == NULL) {
2693 __ cmpptr(reg1, (int32_t)NULL_WORD);
2694 } else {
2695 #ifdef _LP64
2696 __ movoop(rscratch1, o);
2697 __ cmpptr(reg1, rscratch1);
2698 #else
2699 __ cmpoop(reg1, c->as_jobject());
2700 #endif // _LP64
2701 }
2702 } else {
2703 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2704 }
2705 // cpu register - address
2706 } else if (opr2->is_address()) {
2707 if (op->info() != NULL) {
2708 add_debug_info_for_null_check_here(op->info());
2709 }
2710 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2711 } else {
2712 ShouldNotReachHere();
2713 }
2715 } else if(opr1->is_double_cpu()) {
2716 Register xlo = opr1->as_register_lo();
2717 Register xhi = opr1->as_register_hi();
2718 if (opr2->is_double_cpu()) {
2719 #ifdef _LP64
2720 __ cmpptr(xlo, opr2->as_register_lo());
2721 #else
2722 // cpu register - cpu register
2723 Register ylo = opr2->as_register_lo();
2724 Register yhi = opr2->as_register_hi();
2725 __ subl(xlo, ylo);
2726 __ sbbl(xhi, yhi);
2727 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2728 __ orl(xhi, xlo);
2729 }
2730 #endif // _LP64
2731 } else if (opr2->is_constant()) {
2732 // cpu register - constant 0
2733 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2734 #ifdef _LP64
2735 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2736 #else
2737 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2738 __ orl(xhi, xlo);
2739 #endif // _LP64
2740 } else {
2741 ShouldNotReachHere();
2742 }
2744 } else if (opr1->is_single_xmm()) {
2745 XMMRegister reg1 = opr1->as_xmm_float_reg();
2746 if (opr2->is_single_xmm()) {
2747 // xmm register - xmm register
2748 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2749 } else if (opr2->is_stack()) {
2750 // xmm register - stack
2751 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2752 } else if (opr2->is_constant()) {
2753 // xmm register - constant
2754 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2755 } else if (opr2->is_address()) {
2756 // xmm register - address
2757 if (op->info() != NULL) {
2758 add_debug_info_for_null_check_here(op->info());
2759 }
2760 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2761 } else {
2762 ShouldNotReachHere();
2763 }
2765 } else if (opr1->is_double_xmm()) {
2766 XMMRegister reg1 = opr1->as_xmm_double_reg();
2767 if (opr2->is_double_xmm()) {
2768 // xmm register - xmm register
2769 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2770 } else if (opr2->is_stack()) {
2771 // xmm register - stack
2772 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2773 } else if (opr2->is_constant()) {
2774 // xmm register - constant
2775 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2776 } else if (opr2->is_address()) {
2777 // xmm register - address
2778 if (op->info() != NULL) {
2779 add_debug_info_for_null_check_here(op->info());
2780 }
2781 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2782 } else {
2783 ShouldNotReachHere();
2784 }
2786 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2787 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2788 assert(opr2->is_fpu_register(), "both must be registers");
2789 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2791 } else if (opr1->is_address() && opr2->is_constant()) {
2792 LIR_Const* c = opr2->as_constant_ptr();
2793 #ifdef _LP64
2794 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2795 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2796 __ movoop(rscratch1, c->as_jobject());
2797 }
2798 #endif // LP64
2799 if (op->info() != NULL) {
2800 add_debug_info_for_null_check_here(op->info());
2801 }
2802 // special case: address - constant
2803 LIR_Address* addr = opr1->as_address_ptr();
2804 if (c->type() == T_INT) {
2805 __ cmpl(as_Address(addr), c->as_jint());
2806 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2807 #ifdef _LP64
2808 // %%% Make this explode if addr isn't reachable until we figure out a
2809 // better strategy by giving noreg as the temp for as_Address
2810 __ cmpptr(rscratch1, as_Address(addr, noreg));
2811 #else
2812 __ cmpoop(as_Address(addr), c->as_jobject());
2813 #endif // _LP64
2814 } else {
2815 ShouldNotReachHere();
2816 }
2818 } else {
2819 ShouldNotReachHere();
2820 }
2821 }
2823 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2824 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2825 if (left->is_single_xmm()) {
2826 assert(right->is_single_xmm(), "must match");
2827 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2828 } else if (left->is_double_xmm()) {
2829 assert(right->is_double_xmm(), "must match");
2830 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2832 } else {
2833 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2834 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2836 assert(left->fpu() == 0, "left must be on TOS");
2837 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2838 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2839 }
2840 } else {
2841 assert(code == lir_cmp_l2i, "check");
2842 #ifdef _LP64
2843 Label done;
2844 Register dest = dst->as_register();
2845 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2846 __ movl(dest, -1);
2847 __ jccb(Assembler::less, done);
2848 __ set_byte_if_not_zero(dest);
2849 __ movzbl(dest, dest);
2850 __ bind(done);
2851 #else
2852 __ lcmp2int(left->as_register_hi(),
2853 left->as_register_lo(),
2854 right->as_register_hi(),
2855 right->as_register_lo());
2856 move_regs(left->as_register_hi(), dst->as_register());
2857 #endif // _LP64
2858 }
2859 }
2862 void LIR_Assembler::align_call(LIR_Code code) {
2863 if (os::is_MP()) {
2864 // make sure that the displacement word of the call ends up word aligned
2865 int offset = __ offset();
2866 switch (code) {
2867 case lir_static_call:
2868 case lir_optvirtual_call:
2869 case lir_dynamic_call:
2870 offset += NativeCall::displacement_offset;
2871 break;
2872 case lir_icvirtual_call:
2873 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2874 break;
2875 case lir_virtual_call: // currently, sparc-specific for niagara
2876 default: ShouldNotReachHere();
2877 }
2878 while (offset++ % BytesPerWord != 0) {
2879 __ nop();
2880 }
2881 }
2882 }
2885 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2886 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2887 "must be aligned");
2888 __ call(AddressLiteral(op->addr(), rtype));
2889 add_call_info(code_offset(), op->info());
2890 }
2893 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2894 __ ic_call(op->addr());
2895 add_call_info(code_offset(), op->info());
2896 assert(!os::is_MP() ||
2897 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2898 "must be aligned");
2899 }
2902 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2903 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2904 ShouldNotReachHere();
2905 }
2908 void LIR_Assembler::emit_static_call_stub() {
2909 address call_pc = __ pc();
2910 address stub = __ start_a_stub(call_stub_size);
2911 if (stub == NULL) {
2912 bailout("static call stub overflow");
2913 return;
2914 }
2916 int start = __ offset();
2917 if (os::is_MP()) {
2918 // make sure that the displacement word of the call ends up word aligned
2919 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2920 while (offset++ % BytesPerWord != 0) {
2921 __ nop();
2922 }
2923 }
2924 __ relocate(static_stub_Relocation::spec(call_pc));
2925 __ mov_metadata(rbx, (Metadata*)NULL);
2926 // must be set to -1 at code generation time
2927 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2928 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2929 __ jump(RuntimeAddress(__ pc()));
2931 assert(__ offset() - start <= call_stub_size, "stub too big");
2932 __ end_a_stub();
2933 }
2936 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2937 assert(exceptionOop->as_register() == rax, "must match");
2938 assert(exceptionPC->as_register() == rdx, "must match");
2940 // exception object is not added to oop map by LinearScan
2941 // (LinearScan assumes that no oops are in fixed registers)
2942 info->add_register_oop(exceptionOop);
2943 Runtime1::StubID unwind_id;
2945 // get current pc information
2946 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2947 int pc_for_athrow_offset = __ offset();
2948 InternalAddress pc_for_athrow(__ pc());
2949 __ lea(exceptionPC->as_register(), pc_for_athrow);
2950 add_call_info(pc_for_athrow_offset, info); // for exception handler
2952 __ verify_not_null_oop(rax);
2953 // search an exception handler (rax: exception oop, rdx: throwing pc)
2954 if (compilation()->has_fpu_code()) {
2955 unwind_id = Runtime1::handle_exception_id;
2956 } else {
2957 unwind_id = Runtime1::handle_exception_nofpu_id;
2958 }
2959 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2961 // enough room for two byte trap
2962 __ nop();
2963 }
2966 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2967 assert(exceptionOop->as_register() == rax, "must match");
2969 __ jmp(_unwind_handler_entry);
2970 }
2973 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2975 // optimized version for linear scan:
2976 // * count must be already in ECX (guaranteed by LinearScan)
2977 // * left and dest must be equal
2978 // * tmp must be unused
2979 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2980 assert(left == dest, "left and dest must be equal");
2981 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2983 if (left->is_single_cpu()) {
2984 Register value = left->as_register();
2985 assert(value != SHIFT_count, "left cannot be ECX");
2987 switch (code) {
2988 case lir_shl: __ shll(value); break;
2989 case lir_shr: __ sarl(value); break;
2990 case lir_ushr: __ shrl(value); break;
2991 default: ShouldNotReachHere();
2992 }
2993 } else if (left->is_double_cpu()) {
2994 Register lo = left->as_register_lo();
2995 Register hi = left->as_register_hi();
2996 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2997 #ifdef _LP64
2998 switch (code) {
2999 case lir_shl: __ shlptr(lo); break;
3000 case lir_shr: __ sarptr(lo); break;
3001 case lir_ushr: __ shrptr(lo); break;
3002 default: ShouldNotReachHere();
3003 }
3004 #else
3006 switch (code) {
3007 case lir_shl: __ lshl(hi, lo); break;
3008 case lir_shr: __ lshr(hi, lo, true); break;
3009 case lir_ushr: __ lshr(hi, lo, false); break;
3010 default: ShouldNotReachHere();
3011 }
3012 #endif // LP64
3013 } else {
3014 ShouldNotReachHere();
3015 }
3016 }
3019 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3020 if (dest->is_single_cpu()) {
3021 // first move left into dest so that left is not destroyed by the shift
3022 Register value = dest->as_register();
3023 count = count & 0x1F; // Java spec
3025 move_regs(left->as_register(), value);
3026 switch (code) {
3027 case lir_shl: __ shll(value, count); break;
3028 case lir_shr: __ sarl(value, count); break;
3029 case lir_ushr: __ shrl(value, count); break;
3030 default: ShouldNotReachHere();
3031 }
3032 } else if (dest->is_double_cpu()) {
3033 #ifndef _LP64
3034 Unimplemented();
3035 #else
3036 // first move left into dest so that left is not destroyed by the shift
3037 Register value = dest->as_register_lo();
3038 count = count & 0x1F; // Java spec
3040 move_regs(left->as_register_lo(), value);
3041 switch (code) {
3042 case lir_shl: __ shlptr(value, count); break;
3043 case lir_shr: __ sarptr(value, count); break;
3044 case lir_ushr: __ shrptr(value, count); break;
3045 default: ShouldNotReachHere();
3046 }
3047 #endif // _LP64
3048 } else {
3049 ShouldNotReachHere();
3050 }
3051 }
3054 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3055 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3056 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3057 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3058 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3059 }
3062 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3063 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3064 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3065 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3066 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3067 }
3070 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3071 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3072 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3073 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3074 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3075 }
3078 // This code replaces a call to arraycopy; no exception may
3079 // be thrown in this code, they must be thrown in the System.arraycopy
3080 // activation frame; we could save some checks if this would not be the case
3081 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3082 ciArrayKlass* default_type = op->expected_type();
3083 Register src = op->src()->as_register();
3084 Register dst = op->dst()->as_register();
3085 Register src_pos = op->src_pos()->as_register();
3086 Register dst_pos = op->dst_pos()->as_register();
3087 Register length = op->length()->as_register();
3088 Register tmp = op->tmp()->as_register();
3090 CodeStub* stub = op->stub();
3091 int flags = op->flags();
3092 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3093 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3095 // if we don't know anything, just go through the generic arraycopy
3096 if (default_type == NULL) {
3097 Label done;
3098 // save outgoing arguments on stack in case call to System.arraycopy is needed
3099 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3100 // for interpreter calling conventions. Now we have to do it in new style conventions.
3101 // For the moment until C1 gets the new register allocator I just force all the
3102 // args to the right place (except the register args) and then on the back side
3103 // reload the register args properly if we go slow path. Yuck
3105 // These are proper for the calling convention
3106 store_parameter(length, 2);
3107 store_parameter(dst_pos, 1);
3108 store_parameter(dst, 0);
3110 // these are just temporary placements until we need to reload
3111 store_parameter(src_pos, 3);
3112 store_parameter(src, 4);
3113 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3115 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3117 address copyfunc_addr = StubRoutines::generic_arraycopy();
3119 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3120 #ifdef _LP64
3121 // The arguments are in java calling convention so we can trivially shift them to C
3122 // convention
3123 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3124 __ mov(c_rarg0, j_rarg0);
3125 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3126 __ mov(c_rarg1, j_rarg1);
3127 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3128 __ mov(c_rarg2, j_rarg2);
3129 assert_different_registers(c_rarg3, j_rarg4);
3130 __ mov(c_rarg3, j_rarg3);
3131 #ifdef _WIN64
3132 // Allocate abi space for args but be sure to keep stack aligned
3133 __ subptr(rsp, 6*wordSize);
3134 store_parameter(j_rarg4, 4);
3135 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3136 __ call(RuntimeAddress(C_entry));
3137 } else {
3138 #ifndef PRODUCT
3139 if (PrintC1Statistics) {
3140 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3141 }
3142 #endif
3143 __ call(RuntimeAddress(copyfunc_addr));
3144 }
3145 __ addptr(rsp, 6*wordSize);
3146 #else
3147 __ mov(c_rarg4, j_rarg4);
3148 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3149 __ call(RuntimeAddress(C_entry));
3150 } else {
3151 #ifndef PRODUCT
3152 if (PrintC1Statistics) {
3153 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3154 }
3155 #endif
3156 __ call(RuntimeAddress(copyfunc_addr));
3157 }
3158 #endif // _WIN64
3159 #else
3160 __ push(length);
3161 __ push(dst_pos);
3162 __ push(dst);
3163 __ push(src_pos);
3164 __ push(src);
3166 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3167 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3168 } else {
3169 #ifndef PRODUCT
3170 if (PrintC1Statistics) {
3171 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3172 }
3173 #endif
3174 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3175 }
3177 #endif // _LP64
3179 __ cmpl(rax, 0);
3180 __ jcc(Assembler::equal, *stub->continuation());
3182 if (copyfunc_addr != NULL) {
3183 __ mov(tmp, rax);
3184 __ xorl(tmp, -1);
3185 }
3187 // Reload values from the stack so they are where the stub
3188 // expects them.
3189 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3190 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3191 __ movptr (length, Address(rsp, 2*BytesPerWord));
3192 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3193 __ movptr (src, Address(rsp, 4*BytesPerWord));
3195 if (copyfunc_addr != NULL) {
3196 __ subl(length, tmp);
3197 __ addl(src_pos, tmp);
3198 __ addl(dst_pos, tmp);
3199 }
3200 __ jmp(*stub->entry());
3202 __ bind(*stub->continuation());
3203 return;
3204 }
3206 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3208 int elem_size = type2aelembytes(basic_type);
3209 int shift_amount;
3210 Address::ScaleFactor scale;
3212 switch (elem_size) {
3213 case 1 :
3214 shift_amount = 0;
3215 scale = Address::times_1;
3216 break;
3217 case 2 :
3218 shift_amount = 1;
3219 scale = Address::times_2;
3220 break;
3221 case 4 :
3222 shift_amount = 2;
3223 scale = Address::times_4;
3224 break;
3225 case 8 :
3226 shift_amount = 3;
3227 scale = Address::times_8;
3228 break;
3229 default:
3230 ShouldNotReachHere();
3231 }
3233 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3234 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3235 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3236 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3238 // length and pos's are all sign extended at this point on 64bit
3240 // test for NULL
3241 if (flags & LIR_OpArrayCopy::src_null_check) {
3242 __ testptr(src, src);
3243 __ jcc(Assembler::zero, *stub->entry());
3244 }
3245 if (flags & LIR_OpArrayCopy::dst_null_check) {
3246 __ testptr(dst, dst);
3247 __ jcc(Assembler::zero, *stub->entry());
3248 }
3250 // check if negative
3251 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3252 __ testl(src_pos, src_pos);
3253 __ jcc(Assembler::less, *stub->entry());
3254 }
3255 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3256 __ testl(dst_pos, dst_pos);
3257 __ jcc(Assembler::less, *stub->entry());
3258 }
3260 if (flags & LIR_OpArrayCopy::src_range_check) {
3261 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3262 __ cmpl(tmp, src_length_addr);
3263 __ jcc(Assembler::above, *stub->entry());
3264 }
3265 if (flags & LIR_OpArrayCopy::dst_range_check) {
3266 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3267 __ cmpl(tmp, dst_length_addr);
3268 __ jcc(Assembler::above, *stub->entry());
3269 }
3271 if (flags & LIR_OpArrayCopy::length_positive_check) {
3272 __ testl(length, length);
3273 __ jcc(Assembler::less, *stub->entry());
3274 __ jcc(Assembler::zero, *stub->continuation());
3275 }
3277 #ifdef _LP64
3278 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3279 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3280 #endif
3282 if (flags & LIR_OpArrayCopy::type_check) {
3283 // We don't know the array types are compatible
3284 if (basic_type != T_OBJECT) {
3285 // Simple test for basic type arrays
3286 if (UseCompressedKlassPointers) {
3287 __ movl(tmp, src_klass_addr);
3288 __ cmpl(tmp, dst_klass_addr);
3289 } else {
3290 __ movptr(tmp, src_klass_addr);
3291 __ cmpptr(tmp, dst_klass_addr);
3292 }
3293 __ jcc(Assembler::notEqual, *stub->entry());
3294 } else {
3295 // For object arrays, if src is a sub class of dst then we can
3296 // safely do the copy.
3297 Label cont, slow;
3299 __ push(src);
3300 __ push(dst);
3302 __ load_klass(src, src);
3303 __ load_klass(dst, dst);
3305 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3307 __ push(src);
3308 __ push(dst);
3309 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3310 __ pop(dst);
3311 __ pop(src);
3313 __ cmpl(src, 0);
3314 __ jcc(Assembler::notEqual, cont);
3316 __ bind(slow);
3317 __ pop(dst);
3318 __ pop(src);
3320 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3321 if (copyfunc_addr != NULL) { // use stub if available
3322 // src is not a sub class of dst so we have to do a
3323 // per-element check.
3325 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3326 if ((flags & mask) != mask) {
3327 // Check that at least both of them object arrays.
3328 assert(flags & mask, "one of the two should be known to be an object array");
3330 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3331 __ load_klass(tmp, src);
3332 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3333 __ load_klass(tmp, dst);
3334 }
3335 int lh_offset = in_bytes(Klass::layout_helper_offset());
3336 Address klass_lh_addr(tmp, lh_offset);
3337 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3338 __ cmpl(klass_lh_addr, objArray_lh);
3339 __ jcc(Assembler::notEqual, *stub->entry());
3340 }
3342 // Spill because stubs can use any register they like and it's
3343 // easier to restore just those that we care about.
3344 store_parameter(dst, 0);
3345 store_parameter(dst_pos, 1);
3346 store_parameter(length, 2);
3347 store_parameter(src_pos, 3);
3348 store_parameter(src, 4);
3350 #ifndef _LP64
3351 __ movptr(tmp, dst_klass_addr);
3352 __ movptr(tmp, Address(tmp, objArrayKlass::element_klass_offset()));
3353 __ push(tmp);
3354 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3355 __ push(tmp);
3356 __ push(length);
3357 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3358 __ push(tmp);
3359 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3360 __ push(tmp);
3362 __ call_VM_leaf(copyfunc_addr, 5);
3363 #else
3364 __ movl2ptr(length, length); //higher 32bits must be null
3366 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3367 assert_different_registers(c_rarg0, dst, dst_pos, length);
3368 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3369 assert_different_registers(c_rarg1, dst, length);
3371 __ mov(c_rarg2, length);
3372 assert_different_registers(c_rarg2, dst);
3374 #ifdef _WIN64
3375 // Allocate abi space for args but be sure to keep stack aligned
3376 __ subptr(rsp, 6*wordSize);
3377 __ load_klass(c_rarg3, dst);
3378 __ movptr(c_rarg3, Address(c_rarg3, objArrayKlass::element_klass_offset()));
3379 store_parameter(c_rarg3, 4);
3380 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3381 __ call(RuntimeAddress(copyfunc_addr));
3382 __ addptr(rsp, 6*wordSize);
3383 #else
3384 __ load_klass(c_rarg4, dst);
3385 __ movptr(c_rarg4, Address(c_rarg4, objArrayKlass::element_klass_offset()));
3386 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3387 __ call(RuntimeAddress(copyfunc_addr));
3388 #endif
3390 #endif
3392 #ifndef PRODUCT
3393 if (PrintC1Statistics) {
3394 Label failed;
3395 __ testl(rax, rax);
3396 __ jcc(Assembler::notZero, failed);
3397 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3398 __ bind(failed);
3399 }
3400 #endif
3402 __ testl(rax, rax);
3403 __ jcc(Assembler::zero, *stub->continuation());
3405 #ifndef PRODUCT
3406 if (PrintC1Statistics) {
3407 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3408 }
3409 #endif
3411 __ mov(tmp, rax);
3413 __ xorl(tmp, -1);
3415 // Restore previously spilled arguments
3416 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3417 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3418 __ movptr (length, Address(rsp, 2*BytesPerWord));
3419 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3420 __ movptr (src, Address(rsp, 4*BytesPerWord));
3423 __ subl(length, tmp);
3424 __ addl(src_pos, tmp);
3425 __ addl(dst_pos, tmp);
3426 }
3428 __ jmp(*stub->entry());
3430 __ bind(cont);
3431 __ pop(dst);
3432 __ pop(src);
3433 }
3434 }
3436 #ifdef ASSERT
3437 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3438 // Sanity check the known type with the incoming class. For the
3439 // primitive case the types must match exactly with src.klass and
3440 // dst.klass each exactly matching the default type. For the
3441 // object array case, if no type check is needed then either the
3442 // dst type is exactly the expected type and the src type is a
3443 // subtype which we can't check or src is the same array as dst
3444 // but not necessarily exactly of type default_type.
3445 Label known_ok, halt;
3446 __ mov_metadata(tmp, default_type->constant_encoding());
3447 #ifdef _LP64
3448 if (UseCompressedKlassPointers) {
3449 __ encode_heap_oop(tmp);
3450 }
3451 #endif
3453 if (basic_type != T_OBJECT) {
3455 if (UseCompressedKlassPointers) __ cmpl(tmp, dst_klass_addr);
3456 else __ cmpptr(tmp, dst_klass_addr);
3457 __ jcc(Assembler::notEqual, halt);
3458 if (UseCompressedKlassPointers) __ cmpl(tmp, src_klass_addr);
3459 else __ cmpptr(tmp, src_klass_addr);
3460 __ jcc(Assembler::equal, known_ok);
3461 } else {
3462 if (UseCompressedKlassPointers) __ cmpl(tmp, dst_klass_addr);
3463 else __ cmpptr(tmp, dst_klass_addr);
3464 __ jcc(Assembler::equal, known_ok);
3465 __ cmpptr(src, dst);
3466 __ jcc(Assembler::equal, known_ok);
3467 }
3468 __ bind(halt);
3469 __ stop("incorrect type information in arraycopy");
3470 __ bind(known_ok);
3471 }
3472 #endif
3474 #ifndef PRODUCT
3475 if (PrintC1Statistics) {
3476 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3477 }
3478 #endif
3480 #ifdef _LP64
3481 assert_different_registers(c_rarg0, dst, dst_pos, length);
3482 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3483 assert_different_registers(c_rarg1, length);
3484 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3485 __ mov(c_rarg2, length);
3487 #else
3488 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3489 store_parameter(tmp, 0);
3490 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3491 store_parameter(tmp, 1);
3492 store_parameter(length, 2);
3493 #endif // _LP64
3495 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3496 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3497 const char *name;
3498 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3499 __ call_VM_leaf(entry, 0);
3501 __ bind(*stub->continuation());
3502 }
3505 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3506 Register obj = op->obj_opr()->as_register(); // may not be an oop
3507 Register hdr = op->hdr_opr()->as_register();
3508 Register lock = op->lock_opr()->as_register();
3509 if (!UseFastLocking) {
3510 __ jmp(*op->stub()->entry());
3511 } else if (op->code() == lir_lock) {
3512 Register scratch = noreg;
3513 if (UseBiasedLocking) {
3514 scratch = op->scratch_opr()->as_register();
3515 }
3516 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3517 // add debug info for NullPointerException only if one is possible
3518 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3519 if (op->info() != NULL) {
3520 add_debug_info_for_null_check(null_check_offset, op->info());
3521 }
3522 // done
3523 } else if (op->code() == lir_unlock) {
3524 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3525 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3526 } else {
3527 Unimplemented();
3528 }
3529 __ bind(*op->stub()->continuation());
3530 }
3533 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3534 ciMethod* method = op->profiled_method();
3535 int bci = op->profiled_bci();
3536 ciMethod* callee = op->profiled_callee();
3538 // Update counter for all call types
3539 ciMethodData* md = method->method_data_or_null();
3540 assert(md != NULL, "Sanity");
3541 ciProfileData* data = md->bci_to_data(bci);
3542 assert(data->is_CounterData(), "need CounterData for calls");
3543 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3544 Register mdo = op->mdo()->as_register();
3545 __ mov_metadata(mdo, md->constant_encoding());
3546 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3547 Bytecodes::Code bc = method->java_code_at_bci(bci);
3548 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3549 // Perform additional virtual call profiling for invokevirtual and
3550 // invokeinterface bytecodes
3551 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3552 !callee_is_static && // required for optimized MH invokes
3553 C1ProfileVirtualCalls) {
3554 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3555 Register recv = op->recv()->as_register();
3556 assert_different_registers(mdo, recv);
3557 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3558 ciKlass* known_klass = op->known_holder();
3559 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3560 // We know the type that will be seen at this call site; we can
3561 // statically update the MethodData* rather than needing to do
3562 // dynamic tests on the receiver type
3564 // NOTE: we should probably put a lock around this search to
3565 // avoid collisions by concurrent compilations
3566 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3567 uint i;
3568 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3569 ciKlass* receiver = vc_data->receiver(i);
3570 if (known_klass->equals(receiver)) {
3571 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3572 __ addptr(data_addr, DataLayout::counter_increment);
3573 return;
3574 }
3575 }
3577 // Receiver type not found in profile data; select an empty slot
3579 // Note that this is less efficient than it should be because it
3580 // always does a write to the receiver part of the
3581 // VirtualCallData rather than just the first time
3582 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3583 ciKlass* receiver = vc_data->receiver(i);
3584 if (receiver == NULL) {
3585 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3586 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3587 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3588 __ addptr(data_addr, DataLayout::counter_increment);
3589 return;
3590 }
3591 }
3592 } else {
3593 __ load_klass(recv, recv);
3594 Label update_done;
3595 type_profile_helper(mdo, md, data, recv, &update_done);
3596 // Receiver did not match any saved receiver and there is no empty row for it.
3597 // Increment total counter to indicate polymorphic case.
3598 __ addptr(counter_addr, DataLayout::counter_increment);
3600 __ bind(update_done);
3601 }
3602 } else {
3603 // Static call
3604 __ addptr(counter_addr, DataLayout::counter_increment);
3605 }
3606 }
3608 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3609 Unimplemented();
3610 }
3613 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3614 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3615 }
3618 void LIR_Assembler::align_backward_branch_target() {
3619 __ align(BytesPerWord);
3620 }
3623 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3624 if (left->is_single_cpu()) {
3625 __ negl(left->as_register());
3626 move_regs(left->as_register(), dest->as_register());
3628 } else if (left->is_double_cpu()) {
3629 Register lo = left->as_register_lo();
3630 #ifdef _LP64
3631 Register dst = dest->as_register_lo();
3632 __ movptr(dst, lo);
3633 __ negptr(dst);
3634 #else
3635 Register hi = left->as_register_hi();
3636 __ lneg(hi, lo);
3637 if (dest->as_register_lo() == hi) {
3638 assert(dest->as_register_hi() != lo, "destroying register");
3639 move_regs(hi, dest->as_register_hi());
3640 move_regs(lo, dest->as_register_lo());
3641 } else {
3642 move_regs(lo, dest->as_register_lo());
3643 move_regs(hi, dest->as_register_hi());
3644 }
3645 #endif // _LP64
3647 } else if (dest->is_single_xmm()) {
3648 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3649 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3650 }
3651 __ xorps(dest->as_xmm_float_reg(),
3652 ExternalAddress((address)float_signflip_pool));
3654 } else if (dest->is_double_xmm()) {
3655 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3656 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3657 }
3658 __ xorpd(dest->as_xmm_double_reg(),
3659 ExternalAddress((address)double_signflip_pool));
3661 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3662 assert(left->fpu() == 0, "arg must be on TOS");
3663 assert(dest->fpu() == 0, "dest must be TOS");
3664 __ fchs();
3666 } else {
3667 ShouldNotReachHere();
3668 }
3669 }
3672 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3673 assert(addr->is_address() && dest->is_register(), "check");
3674 Register reg;
3675 reg = dest->as_pointer_register();
3676 __ lea(reg, as_Address(addr->as_address_ptr()));
3677 }
3681 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3682 assert(!tmp->is_valid(), "don't need temporary");
3683 __ call(RuntimeAddress(dest));
3684 if (info != NULL) {
3685 add_call_info_here(info);
3686 }
3687 }
3690 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3691 assert(type == T_LONG, "only for volatile long fields");
3693 if (info != NULL) {
3694 add_debug_info_for_null_check_here(info);
3695 }
3697 if (src->is_double_xmm()) {
3698 if (dest->is_double_cpu()) {
3699 #ifdef _LP64
3700 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3701 #else
3702 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3703 __ psrlq(src->as_xmm_double_reg(), 32);
3704 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3705 #endif // _LP64
3706 } else if (dest->is_double_stack()) {
3707 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3708 } else if (dest->is_address()) {
3709 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3710 } else {
3711 ShouldNotReachHere();
3712 }
3714 } else if (dest->is_double_xmm()) {
3715 if (src->is_double_stack()) {
3716 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3717 } else if (src->is_address()) {
3718 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3719 } else {
3720 ShouldNotReachHere();
3721 }
3723 } else if (src->is_double_fpu()) {
3724 assert(src->fpu_regnrLo() == 0, "must be TOS");
3725 if (dest->is_double_stack()) {
3726 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3727 } else if (dest->is_address()) {
3728 __ fistp_d(as_Address(dest->as_address_ptr()));
3729 } else {
3730 ShouldNotReachHere();
3731 }
3733 } else if (dest->is_double_fpu()) {
3734 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3735 if (src->is_double_stack()) {
3736 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3737 } else if (src->is_address()) {
3738 __ fild_d(as_Address(src->as_address_ptr()));
3739 } else {
3740 ShouldNotReachHere();
3741 }
3742 } else {
3743 ShouldNotReachHere();
3744 }
3745 }
3748 void LIR_Assembler::membar() {
3749 // QQQ sparc TSO uses this,
3750 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3751 }
3753 void LIR_Assembler::membar_acquire() {
3754 // No x86 machines currently require load fences
3755 // __ load_fence();
3756 }
3758 void LIR_Assembler::membar_release() {
3759 // No x86 machines currently require store fences
3760 // __ store_fence();
3761 }
3763 void LIR_Assembler::membar_loadload() {
3764 // no-op
3765 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3766 }
3768 void LIR_Assembler::membar_storestore() {
3769 // no-op
3770 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3771 }
3773 void LIR_Assembler::membar_loadstore() {
3774 // no-op
3775 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3776 }
3778 void LIR_Assembler::membar_storeload() {
3779 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3780 }
3782 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3783 assert(result_reg->is_register(), "check");
3784 #ifdef _LP64
3785 // __ get_thread(result_reg->as_register_lo());
3786 __ mov(result_reg->as_register(), r15_thread);
3787 #else
3788 __ get_thread(result_reg->as_register());
3789 #endif // _LP64
3790 }
3793 void LIR_Assembler::peephole(LIR_List*) {
3794 // do nothing for now
3795 }
3797 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3798 assert(data == dest, "xchg/xadd uses only 2 operands");
3800 if (data->type() == T_INT) {
3801 if (code == lir_xadd) {
3802 if (os::is_MP()) {
3803 __ lock();
3804 }
3805 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3806 } else {
3807 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3808 }
3809 } else if (data->is_oop()) {
3810 assert (code == lir_xchg, "xadd for oops");
3811 Register obj = data->as_register();
3812 #ifdef _LP64
3813 if (UseCompressedOops) {
3814 __ encode_heap_oop(obj);
3815 __ xchgl(obj, as_Address(src->as_address_ptr()));
3816 __ decode_heap_oop(obj);
3817 } else {
3818 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3819 }
3820 #else
3821 __ xchgl(obj, as_Address(src->as_address_ptr()));
3822 #endif
3823 } else if (data->type() == T_LONG) {
3824 #ifdef _LP64
3825 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3826 if (code == lir_xadd) {
3827 if (os::is_MP()) {
3828 __ lock();
3829 }
3830 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3831 } else {
3832 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3833 }
3834 #else
3835 ShouldNotReachHere();
3836 #endif
3837 } else {
3838 ShouldNotReachHere();
3839 }
3840 }
3842 #undef __
