3792 |
3792 |
3793 void LIR_Assembler::peephole(LIR_List*) { |
3793 void LIR_Assembler::peephole(LIR_List*) { |
3794 // do nothing for now |
3794 // do nothing for now |
3795 } |
3795 } |
3796 |
3796 |
|
3797 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { |
|
3798 assert(data == dest, "xchg/xadd uses only 2 operands"); |
|
3799 |
|
3800 if (data->type() == T_INT) { |
|
3801 if (code == lir_xadd) { |
|
3802 if (os::is_MP()) { |
|
3803 __ lock(); |
|
3804 } |
|
3805 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); |
|
3806 } else { |
|
3807 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); |
|
3808 } |
|
3809 } else if (data->is_oop()) { |
|
3810 assert (code == lir_xchg, "xadd for oops"); |
|
3811 Register obj = data->as_register(); |
|
3812 #ifdef _LP64 |
|
3813 if (UseCompressedOops) { |
|
3814 __ encode_heap_oop(obj); |
|
3815 __ xchgl(obj, as_Address(src->as_address_ptr())); |
|
3816 __ decode_heap_oop(obj); |
|
3817 } else { |
|
3818 __ xchgptr(obj, as_Address(src->as_address_ptr())); |
|
3819 } |
|
3820 #else |
|
3821 __ xchgl(obj, as_Address(src->as_address_ptr())); |
|
3822 #endif |
|
3823 } else if (data->type() == T_LONG) { |
|
3824 #ifdef _LP64 |
|
3825 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); |
|
3826 if (code == lir_xadd) { |
|
3827 if (os::is_MP()) { |
|
3828 __ lock(); |
|
3829 } |
|
3830 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); |
|
3831 } else { |
|
3832 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); |
|
3833 } |
|
3834 #else |
|
3835 ShouldNotReachHere(); |
|
3836 #endif |
|
3837 } else { |
|
3838 ShouldNotReachHere(); |
|
3839 } |
|
3840 } |
3797 |
3841 |
3798 #undef __ |
3842 #undef __ |