Fri, 12 Feb 2010 15:27:36 -0800
Merge
1 /*
2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
25 # include "incls/_precompiled.incl"
26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl"
28 #define __ _masm->
31 //------------------------------------------------------------
34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
35 if (opr->is_constant()) {
36 LIR_Const* constant = opr->as_constant_ptr();
37 switch (constant->type()) {
38 case T_INT: {
39 jint value = constant->as_jint();
40 return Assembler::is_simm13(value);
41 }
43 default:
44 return false;
45 }
46 }
47 return false;
48 }
51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) {
52 switch (op->code()) {
53 case lir_null_check:
54 return true;
57 case lir_add:
58 case lir_ushr:
59 case lir_shr:
60 case lir_shl:
61 // integer shifts and adds are always one instruction
62 return op->result_opr()->is_single_cpu();
65 case lir_move: {
66 LIR_Op1* op1 = op->as_Op1();
67 LIR_Opr src = op1->in_opr();
68 LIR_Opr dst = op1->result_opr();
70 if (src == dst) {
71 NEEDS_CLEANUP;
72 // this works around a problem where moves with the same src and dst
73 // end up in the delay slot and then the assembler swallows the mov
74 // since it has no effect and then it complains because the delay slot
75 // is empty. returning false stops the optimizer from putting this in
76 // the delay slot
77 return false;
78 }
80 // don't put moves involving oops into the delay slot since the VerifyOops code
81 // will make it much larger than a single instruction.
82 if (VerifyOops) {
83 return false;
84 }
86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
88 return false;
89 }
91 if (dst->is_register()) {
92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
93 return !PatchALot;
94 } else if (src->is_single_stack()) {
95 return true;
96 }
97 }
99 if (src->is_register()) {
100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
101 return !PatchALot;
102 } else if (dst->is_single_stack()) {
103 return true;
104 }
105 }
107 if (dst->is_register() &&
108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
110 return true;
111 }
113 return false;
114 }
116 default:
117 return false;
118 }
119 ShouldNotReachHere();
120 }
123 LIR_Opr LIR_Assembler::receiverOpr() {
124 return FrameMap::O0_oop_opr;
125 }
128 LIR_Opr LIR_Assembler::incomingReceiverOpr() {
129 return FrameMap::I0_oop_opr;
130 }
133 LIR_Opr LIR_Assembler::osrBufferPointer() {
134 return FrameMap::I0_opr;
135 }
138 int LIR_Assembler::initial_frame_size_in_bytes() {
139 return in_bytes(frame_map()->framesize_in_bytes());
140 }
143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
144 // we fetch the class of the receiver (O0) and compare it with the cached class.
145 // If they do not match we jump to slow case.
146 int LIR_Assembler::check_icache() {
147 int offset = __ offset();
148 __ inline_cache_check(O0, G5_inline_cache_reg);
149 return offset;
150 }
153 void LIR_Assembler::osr_entry() {
154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
155 //
156 // 1. Create a new compiled activation.
157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty
158 // at the osr_bci; it is not initialized.
159 // 3. Jump to the continuation address in compiled code to resume execution.
161 // OSR entry point
162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
163 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
164 ValueStack* entry_state = osr_entry->end()->state();
165 int number_of_locks = entry_state->locks_size();
167 // Create a frame for the compiled activation.
168 __ build_frame(initial_frame_size_in_bytes());
170 // OSR buffer is
171 //
172 // locals[nlocals-1..0]
173 // monitors[number_of_locks-1..0]
174 //
175 // locals is a direct copy of the interpreter frame so in the osr buffer
176 // so first slot in the local array is the last local from the interpreter
177 // and last slot is local[0] (receiver) from the interpreter
178 //
179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
181 // in the interpreter frame (the method lock if a sync method)
183 // Initialize monitors in the compiled activation.
184 // I0: pointer to osr buffer
185 //
186 // All other registers are dead at this point and the locals will be
187 // copied into place by code emitted in the IR.
189 Register OSR_buf = osrBufferPointer()->as_register();
190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
191 int monitor_offset = BytesPerWord * method()->max_locals() +
192 (2 * BytesPerWord) * (number_of_locks - 1);
193 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
194 // the OSR buffer using 2 word entries: first the lock and then
195 // the oop.
196 for (int i = 0; i < number_of_locks; i++) {
197 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
198 #ifdef ASSERT
199 // verify the interpreter's monitor has a non-null object
200 {
201 Label L;
202 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
203 __ cmp(G0, O7);
204 __ br(Assembler::notEqual, false, Assembler::pt, L);
205 __ delayed()->nop();
206 __ stop("locked object is NULL");
207 __ bind(L);
208 }
209 #endif // ASSERT
210 // Copy the lock field into the compiled activation.
211 __ ld_ptr(OSR_buf, slot_offset + 0, O7);
212 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
213 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
214 __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
215 }
216 }
217 }
220 // Optimized Library calls
221 // This is the fast version of java.lang.String.compare; it has not
222 // OSR-entry and therefore, we generate a slow version for OSR's
223 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
224 Register str0 = left->as_register();
225 Register str1 = right->as_register();
227 Label Ldone;
229 Register result = dst->as_register();
230 {
231 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
232 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
233 // Also, get string0.count-string1.count in o7 and get the condition code set
234 // Note: some instructions have been hoisted for better instruction scheduling
236 Register tmp0 = L0;
237 Register tmp1 = L1;
238 Register tmp2 = L2;
240 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
241 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
242 int count_offset = java_lang_String:: count_offset_in_bytes();
244 __ ld_ptr(str0, value_offset, tmp0);
245 __ ld(str0, offset_offset, tmp2);
246 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
247 __ ld(str0, count_offset, str0);
248 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
250 // str1 may be null
251 add_debug_info_for_null_check_here(info);
253 __ ld_ptr(str1, value_offset, tmp1);
254 __ add(tmp0, tmp2, tmp0);
256 __ ld(str1, offset_offset, tmp2);
257 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
258 __ ld(str1, count_offset, str1);
259 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
260 __ subcc(str0, str1, O7);
261 __ add(tmp1, tmp2, tmp1);
262 }
264 {
265 // Compute the minimum of the string lengths, scale it and store it in limit
266 Register count0 = I0;
267 Register count1 = I1;
268 Register limit = L3;
270 Label Lskip;
271 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
272 __ br(Assembler::greater, true, Assembler::pt, Lskip);
273 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
274 __ bind(Lskip);
276 // If either string is empty (or both of them) the result is the difference in lengths
277 __ cmp(limit, 0);
278 __ br(Assembler::equal, true, Assembler::pn, Ldone);
279 __ delayed()->mov(O7, result); // result is difference in lengths
280 }
282 {
283 // Neither string is empty
284 Label Lloop;
286 Register base0 = L0;
287 Register base1 = L1;
288 Register chr0 = I0;
289 Register chr1 = I1;
290 Register limit = L3;
292 // Shift base0 and base1 to the end of the arrays, negate limit
293 __ add(base0, limit, base0);
294 __ add(base1, limit, base1);
295 __ neg(limit); // limit = -min{string0.count, strin1.count}
297 __ lduh(base0, limit, chr0);
298 __ bind(Lloop);
299 __ lduh(base1, limit, chr1);
300 __ subcc(chr0, chr1, chr0);
301 __ br(Assembler::notZero, false, Assembler::pn, Ldone);
302 assert(chr0 == result, "result must be pre-placed");
303 __ delayed()->inccc(limit, sizeof(jchar));
304 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
305 __ delayed()->lduh(base0, limit, chr0);
306 }
308 // If strings are equal up to min length, return the length difference.
309 __ mov(O7, result);
311 // Otherwise, return the difference between the first mismatched chars.
312 __ bind(Ldone);
313 }
316 // --------------------------------------------------------------------------------------------
318 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
319 if (!GenerateSynchronizationCode) return;
321 Register obj_reg = obj_opr->as_register();
322 Register lock_reg = lock_opr->as_register();
324 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
325 Register reg = mon_addr.base();
326 int offset = mon_addr.disp();
327 // compute pointer to BasicLock
328 if (mon_addr.is_simm13()) {
329 __ add(reg, offset, lock_reg);
330 }
331 else {
332 __ set(offset, lock_reg);
333 __ add(reg, lock_reg, lock_reg);
334 }
335 // unlock object
336 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
337 // _slow_case_stubs->append(slow_case);
338 // temporary fix: must be created after exceptionhandler, therefore as call stub
339 _slow_case_stubs->append(slow_case);
340 if (UseFastLocking) {
341 // try inlined fast unlocking first, revert to slow locking if it fails
342 // note: lock_reg points to the displaced header since the displaced header offset is 0!
343 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
344 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
345 } else {
346 // always do slow unlocking
347 // note: the slow unlocking code could be inlined here, however if we use
348 // slow unlocking, speed doesn't matter anyway and this solution is
349 // simpler and requires less duplicated code - additionally, the
350 // slow unlocking code is the same in either case which simplifies
351 // debugging
352 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
353 __ delayed()->nop();
354 }
355 // done
356 __ bind(*slow_case->continuation());
357 }
360 int LIR_Assembler::emit_exception_handler() {
361 // if the last instruction is a call (typically to do a throw which
362 // is coming at the end after block reordering) the return address
363 // must still point into the code area in order to avoid assertion
364 // failures when searching for the corresponding bci => add a nop
365 // (was bug 5/14/1999 - gri)
366 __ nop();
368 // generate code for exception handler
369 ciMethod* method = compilation()->method();
371 address handler_base = __ start_a_stub(exception_handler_size);
373 if (handler_base == NULL) {
374 // not enough space left for the handler
375 bailout("exception handler overflow");
376 return -1;
377 }
379 int offset = code_offset();
381 if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_on_exceptions()) {
382 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
383 __ delayed()->nop();
384 }
386 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
387 __ delayed()->nop();
388 debug_only(__ stop("should have gone to the caller");)
389 assert(code_offset() - offset <= exception_handler_size, "overflow");
390 __ end_a_stub();
392 return offset;
393 }
396 int LIR_Assembler::emit_deopt_handler() {
397 // if the last instruction is a call (typically to do a throw which
398 // is coming at the end after block reordering) the return address
399 // must still point into the code area in order to avoid assertion
400 // failures when searching for the corresponding bci => add a nop
401 // (was bug 5/14/1999 - gri)
402 __ nop();
404 // generate code for deopt handler
405 ciMethod* method = compilation()->method();
406 address handler_base = __ start_a_stub(deopt_handler_size);
407 if (handler_base == NULL) {
408 // not enough space left for the handler
409 bailout("deopt handler overflow");
410 return -1;
411 }
413 int offset = code_offset();
414 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
415 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
416 __ delayed()->nop();
417 assert(code_offset() - offset <= deopt_handler_size, "overflow");
418 debug_only(__ stop("should have gone to the caller");)
419 __ end_a_stub();
421 return offset;
422 }
425 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
426 if (o == NULL) {
427 __ set(NULL_WORD, reg);
428 } else {
429 int oop_index = __ oop_recorder()->find_index(o);
430 RelocationHolder rspec = oop_Relocation::spec(oop_index);
431 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
432 }
433 }
436 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
437 // Allocate a new index in oop table to hold the oop once it's been patched
438 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
439 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
441 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
442 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
443 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
444 // NULL will be dynamically patched later and the patched value may be large. We must
445 // therefore generate the sethi/add as a placeholders
446 __ patchable_set(addrlit, reg);
448 patching_epilog(patch, lir_patch_normal, reg, info);
449 }
452 void LIR_Assembler::emit_op3(LIR_Op3* op) {
453 Register Rdividend = op->in_opr1()->as_register();
454 Register Rdivisor = noreg;
455 Register Rscratch = op->in_opr3()->as_register();
456 Register Rresult = op->result_opr()->as_register();
457 int divisor = -1;
459 if (op->in_opr2()->is_register()) {
460 Rdivisor = op->in_opr2()->as_register();
461 } else {
462 divisor = op->in_opr2()->as_constant_ptr()->as_jint();
463 assert(Assembler::is_simm13(divisor), "can only handle simm13");
464 }
466 assert(Rdividend != Rscratch, "");
467 assert(Rdivisor != Rscratch, "");
468 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
470 if (Rdivisor == noreg && is_power_of_2(divisor)) {
471 // convert division by a power of two into some shifts and logical operations
472 if (op->code() == lir_idiv) {
473 if (divisor == 2) {
474 __ srl(Rdividend, 31, Rscratch);
475 } else {
476 __ sra(Rdividend, 31, Rscratch);
477 __ and3(Rscratch, divisor - 1, Rscratch);
478 }
479 __ add(Rdividend, Rscratch, Rscratch);
480 __ sra(Rscratch, log2_intptr(divisor), Rresult);
481 return;
482 } else {
483 if (divisor == 2) {
484 __ srl(Rdividend, 31, Rscratch);
485 } else {
486 __ sra(Rdividend, 31, Rscratch);
487 __ and3(Rscratch, divisor - 1,Rscratch);
488 }
489 __ add(Rdividend, Rscratch, Rscratch);
490 __ andn(Rscratch, divisor - 1,Rscratch);
491 __ sub(Rdividend, Rscratch, Rresult);
492 return;
493 }
494 }
496 __ sra(Rdividend, 31, Rscratch);
497 __ wry(Rscratch);
498 if (!VM_Version::v9_instructions_work()) {
499 // v9 doesn't require these nops
500 __ nop();
501 __ nop();
502 __ nop();
503 __ nop();
504 }
506 add_debug_info_for_div0_here(op->info());
508 if (Rdivisor != noreg) {
509 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
510 } else {
511 assert(Assembler::is_simm13(divisor), "can only handle simm13");
512 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
513 }
515 Label skip;
516 __ br(Assembler::overflowSet, true, Assembler::pn, skip);
517 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
518 __ bind(skip);
520 if (op->code() == lir_irem) {
521 if (Rdivisor != noreg) {
522 __ smul(Rscratch, Rdivisor, Rscratch);
523 } else {
524 __ smul(Rscratch, divisor, Rscratch);
525 }
526 __ sub(Rdividend, Rscratch, Rresult);
527 }
528 }
531 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
532 #ifdef ASSERT
533 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
534 if (op->block() != NULL) _branch_target_blocks.append(op->block());
535 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
536 #endif
537 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
539 if (op->cond() == lir_cond_always) {
540 __ br(Assembler::always, false, Assembler::pt, *(op->label()));
541 } else if (op->code() == lir_cond_float_branch) {
542 assert(op->ublock() != NULL, "must have unordered successor");
543 bool is_unordered = (op->ublock() == op->block());
544 Assembler::Condition acond;
545 switch (op->cond()) {
546 case lir_cond_equal: acond = Assembler::f_equal; break;
547 case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
548 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
549 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
550 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
551 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
552 default : ShouldNotReachHere();
553 };
555 if (!VM_Version::v9_instructions_work()) {
556 __ nop();
557 }
558 __ fb( acond, false, Assembler::pn, *(op->label()));
559 } else {
560 assert (op->code() == lir_branch, "just checking");
562 Assembler::Condition acond;
563 switch (op->cond()) {
564 case lir_cond_equal: acond = Assembler::equal; break;
565 case lir_cond_notEqual: acond = Assembler::notEqual; break;
566 case lir_cond_less: acond = Assembler::less; break;
567 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
568 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
569 case lir_cond_greater: acond = Assembler::greater; break;
570 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
571 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
572 default: ShouldNotReachHere();
573 };
575 // sparc has different condition codes for testing 32-bit
576 // vs. 64-bit values. We could always test xcc is we could
577 // guarantee that 32-bit loads always sign extended but that isn't
578 // true and since sign extension isn't free, it would impose a
579 // slight cost.
580 #ifdef _LP64
581 if (op->type() == T_INT) {
582 __ br(acond, false, Assembler::pn, *(op->label()));
583 } else
584 #endif
585 __ brx(acond, false, Assembler::pn, *(op->label()));
586 }
587 // The peephole pass fills the delay slot
588 }
591 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
592 Bytecodes::Code code = op->bytecode();
593 LIR_Opr dst = op->result_opr();
595 switch(code) {
596 case Bytecodes::_i2l: {
597 Register rlo = dst->as_register_lo();
598 Register rhi = dst->as_register_hi();
599 Register rval = op->in_opr()->as_register();
600 #ifdef _LP64
601 __ sra(rval, 0, rlo);
602 #else
603 __ mov(rval, rlo);
604 __ sra(rval, BitsPerInt-1, rhi);
605 #endif
606 break;
607 }
608 case Bytecodes::_i2d:
609 case Bytecodes::_i2f: {
610 bool is_double = (code == Bytecodes::_i2d);
611 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
612 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
613 FloatRegister rsrc = op->in_opr()->as_float_reg();
614 if (rsrc != rdst) {
615 __ fmov(FloatRegisterImpl::S, rsrc, rdst);
616 }
617 __ fitof(w, rdst, rdst);
618 break;
619 }
620 case Bytecodes::_f2i:{
621 FloatRegister rsrc = op->in_opr()->as_float_reg();
622 Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
623 Label L;
624 // result must be 0 if value is NaN; test by comparing value to itself
625 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
626 if (!VM_Version::v9_instructions_work()) {
627 __ nop();
628 }
629 __ fb(Assembler::f_unordered, true, Assembler::pn, L);
630 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
631 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
632 // move integer result from float register to int register
633 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
634 __ bind (L);
635 break;
636 }
637 case Bytecodes::_l2i: {
638 Register rlo = op->in_opr()->as_register_lo();
639 Register rhi = op->in_opr()->as_register_hi();
640 Register rdst = dst->as_register();
641 #ifdef _LP64
642 __ sra(rlo, 0, rdst);
643 #else
644 __ mov(rlo, rdst);
645 #endif
646 break;
647 }
648 case Bytecodes::_d2f:
649 case Bytecodes::_f2d: {
650 bool is_double = (code == Bytecodes::_f2d);
651 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
652 LIR_Opr val = op->in_opr();
653 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
654 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
655 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
656 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
657 __ ftof(vw, dw, rval, rdst);
658 break;
659 }
660 case Bytecodes::_i2s:
661 case Bytecodes::_i2b: {
662 Register rval = op->in_opr()->as_register();
663 Register rdst = dst->as_register();
664 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
665 __ sll (rval, shift, rdst);
666 __ sra (rdst, shift, rdst);
667 break;
668 }
669 case Bytecodes::_i2c: {
670 Register rval = op->in_opr()->as_register();
671 Register rdst = dst->as_register();
672 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
673 __ sll (rval, shift, rdst);
674 __ srl (rdst, shift, rdst);
675 break;
676 }
678 default: ShouldNotReachHere();
679 }
680 }
683 void LIR_Assembler::align_call(LIR_Code) {
684 // do nothing since all instructions are word aligned on sparc
685 }
688 void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) {
689 __ call(entry, rtype);
690 // the peephole pass fills the delay slot
691 }
694 void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) {
695 RelocationHolder rspec = virtual_call_Relocation::spec(pc());
696 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
697 __ relocate(rspec);
698 __ call(entry, relocInfo::none);
699 // the peephole pass fills the delay slot
700 }
703 void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
704 add_debug_info_for_null_check_here(info);
705 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
706 if (__ is_simm13(vtable_offset) ) {
707 __ ld_ptr(G3_scratch, vtable_offset, G5_method);
708 } else {
709 // This will generate 2 instructions
710 __ set(vtable_offset, G5_method);
711 // ld_ptr, set_hi, set
712 __ ld_ptr(G3_scratch, G5_method, G5_method);
713 }
714 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
715 __ callr(G3_scratch, G0);
716 // the peephole pass fills the delay slot
717 }
720 // load with 32-bit displacement
721 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
722 int load_offset = code_offset();
723 if (Assembler::is_simm13(disp)) {
724 if (info != NULL) add_debug_info_for_null_check_here(info);
725 switch(ld_type) {
726 case T_BOOLEAN: // fall through
727 case T_BYTE : __ ldsb(s, disp, d); break;
728 case T_CHAR : __ lduh(s, disp, d); break;
729 case T_SHORT : __ ldsh(s, disp, d); break;
730 case T_INT : __ ld(s, disp, d); break;
731 case T_ADDRESS:// fall through
732 case T_ARRAY : // fall through
733 case T_OBJECT: __ ld_ptr(s, disp, d); break;
734 default : ShouldNotReachHere();
735 }
736 } else {
737 __ set(disp, O7);
738 if (info != NULL) add_debug_info_for_null_check_here(info);
739 load_offset = code_offset();
740 switch(ld_type) {
741 case T_BOOLEAN: // fall through
742 case T_BYTE : __ ldsb(s, O7, d); break;
743 case T_CHAR : __ lduh(s, O7, d); break;
744 case T_SHORT : __ ldsh(s, O7, d); break;
745 case T_INT : __ ld(s, O7, d); break;
746 case T_ADDRESS:// fall through
747 case T_ARRAY : // fall through
748 case T_OBJECT: __ ld_ptr(s, O7, d); break;
749 default : ShouldNotReachHere();
750 }
751 }
752 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
753 return load_offset;
754 }
757 // store with 32-bit displacement
758 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
759 if (Assembler::is_simm13(offset)) {
760 if (info != NULL) add_debug_info_for_null_check_here(info);
761 switch (type) {
762 case T_BOOLEAN: // fall through
763 case T_BYTE : __ stb(value, base, offset); break;
764 case T_CHAR : __ sth(value, base, offset); break;
765 case T_SHORT : __ sth(value, base, offset); break;
766 case T_INT : __ stw(value, base, offset); break;
767 case T_ADDRESS:// fall through
768 case T_ARRAY : // fall through
769 case T_OBJECT: __ st_ptr(value, base, offset); break;
770 default : ShouldNotReachHere();
771 }
772 } else {
773 __ set(offset, O7);
774 if (info != NULL) add_debug_info_for_null_check_here(info);
775 switch (type) {
776 case T_BOOLEAN: // fall through
777 case T_BYTE : __ stb(value, base, O7); break;
778 case T_CHAR : __ sth(value, base, O7); break;
779 case T_SHORT : __ sth(value, base, O7); break;
780 case T_INT : __ stw(value, base, O7); break;
781 case T_ADDRESS:// fall through
782 case T_ARRAY : //fall through
783 case T_OBJECT: __ st_ptr(value, base, O7); break;
784 default : ShouldNotReachHere();
785 }
786 }
787 // Note: Do the store before verification as the code might be patched!
788 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
789 }
792 // load float with 32-bit displacement
793 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
794 FloatRegisterImpl::Width w;
795 switch(ld_type) {
796 case T_FLOAT : w = FloatRegisterImpl::S; break;
797 case T_DOUBLE: w = FloatRegisterImpl::D; break;
798 default : ShouldNotReachHere();
799 }
801 if (Assembler::is_simm13(disp)) {
802 if (info != NULL) add_debug_info_for_null_check_here(info);
803 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
804 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
805 __ ldf(FloatRegisterImpl::S, s, disp , d);
806 } else {
807 __ ldf(w, s, disp, d);
808 }
809 } else {
810 __ set(disp, O7);
811 if (info != NULL) add_debug_info_for_null_check_here(info);
812 __ ldf(w, s, O7, d);
813 }
814 }
817 // store float with 32-bit displacement
818 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
819 FloatRegisterImpl::Width w;
820 switch(type) {
821 case T_FLOAT : w = FloatRegisterImpl::S; break;
822 case T_DOUBLE: w = FloatRegisterImpl::D; break;
823 default : ShouldNotReachHere();
824 }
826 if (Assembler::is_simm13(offset)) {
827 if (info != NULL) add_debug_info_for_null_check_here(info);
828 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
829 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
830 __ stf(FloatRegisterImpl::S, value , base, offset);
831 } else {
832 __ stf(w, value, base, offset);
833 }
834 } else {
835 __ set(offset, O7);
836 if (info != NULL) add_debug_info_for_null_check_here(info);
837 __ stf(w, value, O7, base);
838 }
839 }
842 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
843 int store_offset;
844 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
845 assert(!unaligned, "can't handle this");
846 // for offsets larger than a simm13 we setup the offset in O7
847 __ set(offset, O7);
848 store_offset = store(from_reg, base, O7, type);
849 } else {
850 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
851 store_offset = code_offset();
852 switch (type) {
853 case T_BOOLEAN: // fall through
854 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
855 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
856 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
857 case T_INT : __ stw(from_reg->as_register(), base, offset); break;
858 case T_LONG :
859 #ifdef _LP64
860 if (unaligned || PatchALot) {
861 __ srax(from_reg->as_register_lo(), 32, O7);
862 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
863 __ stw(O7, base, offset + hi_word_offset_in_bytes);
864 } else {
865 __ stx(from_reg->as_register_lo(), base, offset);
866 }
867 #else
868 assert(Assembler::is_simm13(offset + 4), "must be");
869 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
870 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
871 #endif
872 break;
873 case T_ADDRESS:// fall through
874 case T_ARRAY : // fall through
875 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
876 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
877 case T_DOUBLE:
878 {
879 FloatRegister reg = from_reg->as_double_reg();
880 // split unaligned stores
881 if (unaligned || PatchALot) {
882 assert(Assembler::is_simm13(offset + 4), "must be");
883 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
884 __ stf(FloatRegisterImpl::S, reg, base, offset);
885 } else {
886 __ stf(FloatRegisterImpl::D, reg, base, offset);
887 }
888 break;
889 }
890 default : ShouldNotReachHere();
891 }
892 }
893 return store_offset;
894 }
897 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
898 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
899 int store_offset = code_offset();
900 switch (type) {
901 case T_BOOLEAN: // fall through
902 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
903 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
904 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
905 case T_INT : __ stw(from_reg->as_register(), base, disp); break;
906 case T_LONG :
907 #ifdef _LP64
908 __ stx(from_reg->as_register_lo(), base, disp);
909 #else
910 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
911 __ std(from_reg->as_register_hi(), base, disp);
912 #endif
913 break;
914 case T_ADDRESS:// fall through
915 case T_ARRAY : // fall through
916 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
917 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
918 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
919 default : ShouldNotReachHere();
920 }
921 return store_offset;
922 }
925 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
926 int load_offset;
927 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
928 assert(base != O7, "destroying register");
929 assert(!unaligned, "can't handle this");
930 // for offsets larger than a simm13 we setup the offset in O7
931 __ set(offset, O7);
932 load_offset = load(base, O7, to_reg, type);
933 } else {
934 load_offset = code_offset();
935 switch(type) {
936 case T_BOOLEAN: // fall through
937 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
938 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
939 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
940 case T_INT : __ ld(base, offset, to_reg->as_register()); break;
941 case T_LONG :
942 if (!unaligned) {
943 #ifdef _LP64
944 __ ldx(base, offset, to_reg->as_register_lo());
945 #else
946 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
947 "must be sequential");
948 __ ldd(base, offset, to_reg->as_register_hi());
949 #endif
950 } else {
951 #ifdef _LP64
952 assert(base != to_reg->as_register_lo(), "can't handle this");
953 assert(O7 != to_reg->as_register_lo(), "can't handle this");
954 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
955 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
956 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
957 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
958 #else
959 if (base == to_reg->as_register_lo()) {
960 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
961 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
962 } else {
963 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
964 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
965 }
966 #endif
967 }
968 break;
969 case T_ADDRESS:// fall through
970 case T_ARRAY : // fall through
971 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
972 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
973 case T_DOUBLE:
974 {
975 FloatRegister reg = to_reg->as_double_reg();
976 // split unaligned loads
977 if (unaligned || PatchALot) {
978 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
979 __ ldf(FloatRegisterImpl::S, base, offset, reg);
980 } else {
981 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
982 }
983 break;
984 }
985 default : ShouldNotReachHere();
986 }
987 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
988 }
989 return load_offset;
990 }
993 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
994 int load_offset = code_offset();
995 switch(type) {
996 case T_BOOLEAN: // fall through
997 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
998 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
999 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
1000 case T_INT : __ ld(base, disp, to_reg->as_register()); break;
1001 case T_ADDRESS:// fall through
1002 case T_ARRAY : // fall through
1003 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
1004 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
1005 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
1006 case T_LONG :
1007 #ifdef _LP64
1008 __ ldx(base, disp, to_reg->as_register_lo());
1009 #else
1010 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
1011 "must be sequential");
1012 __ ldd(base, disp, to_reg->as_register_hi());
1013 #endif
1014 break;
1015 default : ShouldNotReachHere();
1016 }
1017 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
1018 return load_offset;
1019 }
1022 // load/store with an Address
1023 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1024 load(a.base(), a.disp() + offset, d, ld_type, info);
1025 }
1028 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1029 store(value, dest.base(), dest.disp() + offset, type, info);
1030 }
1033 // loadf/storef with an Address
1034 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
1035 load(a.base(), a.disp() + offset, d, ld_type, info);
1036 }
1039 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
1040 store(value, dest.base(), dest.disp() + offset, type, info);
1041 }
1044 // load/store with an Address
1045 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
1046 load(as_Address(a), d, ld_type, info);
1047 }
1050 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1051 store(value, as_Address(dest), type, info);
1052 }
1055 // loadf/storef with an Address
1056 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
1057 load(as_Address(a), d, ld_type, info);
1058 }
1061 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
1062 store(value, as_Address(dest), type, info);
1063 }
1066 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
1067 LIR_Const* c = src->as_constant_ptr();
1068 switch (c->type()) {
1069 case T_INT:
1070 case T_FLOAT: {
1071 Register src_reg = O7;
1072 int value = c->as_jint_bits();
1073 if (value == 0) {
1074 src_reg = G0;
1075 } else {
1076 __ set(value, O7);
1077 }
1078 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1079 __ stw(src_reg, addr.base(), addr.disp());
1080 break;
1081 }
1082 case T_OBJECT: {
1083 Register src_reg = O7;
1084 jobject2reg(c->as_jobject(), src_reg);
1085 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
1086 __ st_ptr(src_reg, addr.base(), addr.disp());
1087 break;
1088 }
1089 case T_LONG:
1090 case T_DOUBLE: {
1091 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
1093 Register tmp = O7;
1094 int value_lo = c->as_jint_lo_bits();
1095 if (value_lo == 0) {
1096 tmp = G0;
1097 } else {
1098 __ set(value_lo, O7);
1099 }
1100 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
1101 int value_hi = c->as_jint_hi_bits();
1102 if (value_hi == 0) {
1103 tmp = G0;
1104 } else {
1105 __ set(value_hi, O7);
1106 }
1107 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
1108 break;
1109 }
1110 default:
1111 Unimplemented();
1112 }
1113 }
1116 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
1117 LIR_Const* c = src->as_constant_ptr();
1118 LIR_Address* addr = dest->as_address_ptr();
1119 Register base = addr->base()->as_pointer_register();
1121 if (info != NULL) {
1122 add_debug_info_for_null_check_here(info);
1123 }
1124 switch (c->type()) {
1125 case T_INT:
1126 case T_FLOAT: {
1127 LIR_Opr tmp = FrameMap::O7_opr;
1128 int value = c->as_jint_bits();
1129 if (value == 0) {
1130 tmp = FrameMap::G0_opr;
1131 } else if (Assembler::is_simm13(value)) {
1132 __ set(value, O7);
1133 }
1134 if (addr->index()->is_valid()) {
1135 assert(addr->disp() == 0, "must be zero");
1136 store(tmp, base, addr->index()->as_pointer_register(), type);
1137 } else {
1138 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1139 store(tmp, base, addr->disp(), type);
1140 }
1141 break;
1142 }
1143 case T_LONG:
1144 case T_DOUBLE: {
1145 assert(!addr->index()->is_valid(), "can't handle reg reg address here");
1146 assert(Assembler::is_simm13(addr->disp()) &&
1147 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
1149 Register tmp = O7;
1150 int value_lo = c->as_jint_lo_bits();
1151 if (value_lo == 0) {
1152 tmp = G0;
1153 } else {
1154 __ set(value_lo, O7);
1155 }
1156 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
1157 int value_hi = c->as_jint_hi_bits();
1158 if (value_hi == 0) {
1159 tmp = G0;
1160 } else {
1161 __ set(value_hi, O7);
1162 }
1163 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
1164 break;
1165 }
1166 case T_OBJECT: {
1167 jobject obj = c->as_jobject();
1168 LIR_Opr tmp;
1169 if (obj == NULL) {
1170 tmp = FrameMap::G0_opr;
1171 } else {
1172 tmp = FrameMap::O7_opr;
1173 jobject2reg(c->as_jobject(), O7);
1174 }
1175 // handle either reg+reg or reg+disp address
1176 if (addr->index()->is_valid()) {
1177 assert(addr->disp() == 0, "must be zero");
1178 store(tmp, base, addr->index()->as_pointer_register(), type);
1179 } else {
1180 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
1181 store(tmp, base, addr->disp(), type);
1182 }
1184 break;
1185 }
1186 default:
1187 Unimplemented();
1188 }
1189 }
1192 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
1193 LIR_Const* c = src->as_constant_ptr();
1194 LIR_Opr to_reg = dest;
1196 switch (c->type()) {
1197 case T_INT:
1198 {
1199 jint con = c->as_jint();
1200 if (to_reg->is_single_cpu()) {
1201 assert(patch_code == lir_patch_none, "no patching handled here");
1202 __ set(con, to_reg->as_register());
1203 } else {
1204 ShouldNotReachHere();
1205 assert(to_reg->is_single_fpu(), "wrong register kind");
1207 __ set(con, O7);
1208 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
1209 __ st(O7, temp_slot);
1210 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
1211 }
1212 }
1213 break;
1215 case T_LONG:
1216 {
1217 jlong con = c->as_jlong();
1219 if (to_reg->is_double_cpu()) {
1220 #ifdef _LP64
1221 __ set(con, to_reg->as_register_lo());
1222 #else
1223 __ set(low(con), to_reg->as_register_lo());
1224 __ set(high(con), to_reg->as_register_hi());
1225 #endif
1226 #ifdef _LP64
1227 } else if (to_reg->is_single_cpu()) {
1228 __ set(con, to_reg->as_register());
1229 #endif
1230 } else {
1231 ShouldNotReachHere();
1232 assert(to_reg->is_double_fpu(), "wrong register kind");
1233 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
1234 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
1235 __ set(low(con), O7);
1236 __ st(O7, temp_slot_lo);
1237 __ set(high(con), O7);
1238 __ st(O7, temp_slot_hi);
1239 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
1240 }
1241 }
1242 break;
1244 case T_OBJECT:
1245 {
1246 if (patch_code == lir_patch_none) {
1247 jobject2reg(c->as_jobject(), to_reg->as_register());
1248 } else {
1249 jobject2reg_with_patching(to_reg->as_register(), info);
1250 }
1251 }
1252 break;
1254 case T_FLOAT:
1255 {
1256 address const_addr = __ float_constant(c->as_jfloat());
1257 if (const_addr == NULL) {
1258 bailout("const section overflow");
1259 break;
1260 }
1261 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1262 AddressLiteral const_addrlit(const_addr, rspec);
1263 if (to_reg->is_single_fpu()) {
1264 __ patchable_sethi(const_addrlit, O7);
1265 __ relocate(rspec);
1266 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
1268 } else {
1269 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1271 __ set(const_addrlit, O7);
1272 load(O7, 0, to_reg->as_register(), T_INT);
1273 }
1274 }
1275 break;
1277 case T_DOUBLE:
1278 {
1279 address const_addr = __ double_constant(c->as_jdouble());
1280 if (const_addr == NULL) {
1281 bailout("const section overflow");
1282 break;
1283 }
1284 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1286 if (to_reg->is_double_fpu()) {
1287 AddressLiteral const_addrlit(const_addr, rspec);
1288 __ patchable_sethi(const_addrlit, O7);
1289 __ relocate(rspec);
1290 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
1291 } else {
1292 assert(to_reg->is_double_cpu(), "Must be a long register.");
1293 #ifdef _LP64
1294 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
1295 #else
1296 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
1297 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
1298 #endif
1299 }
1301 }
1302 break;
1304 default:
1305 ShouldNotReachHere();
1306 }
1307 }
1309 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1310 Register reg = addr->base()->as_register();
1311 return Address(reg, addr->disp());
1312 }
1315 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1316 switch (type) {
1317 case T_INT:
1318 case T_FLOAT: {
1319 Register tmp = O7;
1320 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1321 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1322 __ lduw(from.base(), from.disp(), tmp);
1323 __ stw(tmp, to.base(), to.disp());
1324 break;
1325 }
1326 case T_OBJECT: {
1327 Register tmp = O7;
1328 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1329 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1330 __ ld_ptr(from.base(), from.disp(), tmp);
1331 __ st_ptr(tmp, to.base(), to.disp());
1332 break;
1333 }
1334 case T_LONG:
1335 case T_DOUBLE: {
1336 Register tmp = O7;
1337 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1338 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1339 __ lduw(from.base(), from.disp(), tmp);
1340 __ stw(tmp, to.base(), to.disp());
1341 __ lduw(from.base(), from.disp() + 4, tmp);
1342 __ stw(tmp, to.base(), to.disp() + 4);
1343 break;
1344 }
1346 default:
1347 ShouldNotReachHere();
1348 }
1349 }
1352 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1353 Address base = as_Address(addr);
1354 return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
1355 }
1358 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1359 Address base = as_Address(addr);
1360 return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
1361 }
1364 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1365 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
1367 LIR_Address* addr = src_opr->as_address_ptr();
1368 LIR_Opr to_reg = dest;
1370 Register src = addr->base()->as_pointer_register();
1371 Register disp_reg = noreg;
1372 int disp_value = addr->disp();
1373 bool needs_patching = (patch_code != lir_patch_none);
1375 if (addr->base()->type() == T_OBJECT) {
1376 __ verify_oop(src);
1377 }
1379 PatchingStub* patch = NULL;
1380 if (needs_patching) {
1381 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1382 assert(!to_reg->is_double_cpu() ||
1383 patch_code == lir_patch_none ||
1384 patch_code == lir_patch_normal, "patching doesn't match register");
1385 }
1387 if (addr->index()->is_illegal()) {
1388 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1389 if (needs_patching) {
1390 __ patchable_set(0, O7);
1391 } else {
1392 __ set(disp_value, O7);
1393 }
1394 disp_reg = O7;
1395 }
1396 } else if (unaligned || PatchALot) {
1397 __ add(src, addr->index()->as_register(), O7);
1398 src = O7;
1399 } else {
1400 disp_reg = addr->index()->as_pointer_register();
1401 assert(disp_value == 0, "can't handle 3 operand addresses");
1402 }
1404 // remember the offset of the load. The patching_epilog must be done
1405 // before the call to add_debug_info, otherwise the PcDescs don't get
1406 // entered in increasing order.
1407 int offset = code_offset();
1409 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1410 if (disp_reg == noreg) {
1411 offset = load(src, disp_value, to_reg, type, unaligned);
1412 } else {
1413 assert(!unaligned, "can't handle this");
1414 offset = load(src, disp_reg, to_reg, type);
1415 }
1417 if (patch != NULL) {
1418 patching_epilog(patch, patch_code, src, info);
1419 }
1421 if (info != NULL) add_debug_info_for_null_check(offset, info);
1422 }
1425 void LIR_Assembler::prefetchr(LIR_Opr src) {
1426 LIR_Address* addr = src->as_address_ptr();
1427 Address from_addr = as_Address(addr);
1429 if (VM_Version::has_v9()) {
1430 __ prefetch(from_addr, Assembler::severalReads);
1431 }
1432 }
1435 void LIR_Assembler::prefetchw(LIR_Opr src) {
1436 LIR_Address* addr = src->as_address_ptr();
1437 Address from_addr = as_Address(addr);
1439 if (VM_Version::has_v9()) {
1440 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
1441 }
1442 }
1445 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1446 Address addr;
1447 if (src->is_single_word()) {
1448 addr = frame_map()->address_for_slot(src->single_stack_ix());
1449 } else if (src->is_double_word()) {
1450 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1451 }
1453 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1454 load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
1455 }
1458 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1459 Address addr;
1460 if (dest->is_single_word()) {
1461 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1462 } else if (dest->is_double_word()) {
1463 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1464 }
1465 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1466 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
1467 }
1470 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1471 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1472 if (from_reg->is_double_fpu()) {
1473 // double to double moves
1474 assert(to_reg->is_double_fpu(), "should match");
1475 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
1476 } else {
1477 // float to float moves
1478 assert(to_reg->is_single_fpu(), "should match");
1479 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
1480 }
1481 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1482 if (from_reg->is_double_cpu()) {
1483 #ifdef _LP64
1484 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
1485 #else
1486 assert(to_reg->is_double_cpu() &&
1487 from_reg->as_register_hi() != to_reg->as_register_lo() &&
1488 from_reg->as_register_lo() != to_reg->as_register_hi(),
1489 "should both be long and not overlap");
1490 // long to long moves
1491 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
1492 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
1493 #endif
1494 #ifdef _LP64
1495 } else if (to_reg->is_double_cpu()) {
1496 // int to int moves
1497 __ mov(from_reg->as_register(), to_reg->as_register_lo());
1498 #endif
1499 } else {
1500 // int to int moves
1501 __ mov(from_reg->as_register(), to_reg->as_register());
1502 }
1503 } else {
1504 ShouldNotReachHere();
1505 }
1506 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1507 __ verify_oop(to_reg->as_register());
1508 }
1509 }
1512 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1513 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1514 bool unaligned) {
1515 LIR_Address* addr = dest->as_address_ptr();
1517 Register src = addr->base()->as_pointer_register();
1518 Register disp_reg = noreg;
1519 int disp_value = addr->disp();
1520 bool needs_patching = (patch_code != lir_patch_none);
1522 if (addr->base()->is_oop_register()) {
1523 __ verify_oop(src);
1524 }
1526 PatchingStub* patch = NULL;
1527 if (needs_patching) {
1528 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1529 assert(!from_reg->is_double_cpu() ||
1530 patch_code == lir_patch_none ||
1531 patch_code == lir_patch_normal, "patching doesn't match register");
1532 }
1534 if (addr->index()->is_illegal()) {
1535 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
1536 if (needs_patching) {
1537 __ patchable_set(0, O7);
1538 } else {
1539 __ set(disp_value, O7);
1540 }
1541 disp_reg = O7;
1542 }
1543 } else if (unaligned || PatchALot) {
1544 __ add(src, addr->index()->as_register(), O7);
1545 src = O7;
1546 } else {
1547 disp_reg = addr->index()->as_pointer_register();
1548 assert(disp_value == 0, "can't handle 3 operand addresses");
1549 }
1551 // remember the offset of the store. The patching_epilog must be done
1552 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1553 // entered in increasing order.
1554 int offset;
1556 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
1557 if (disp_reg == noreg) {
1558 offset = store(from_reg, src, disp_value, type, unaligned);
1559 } else {
1560 assert(!unaligned, "can't handle this");
1561 offset = store(from_reg, src, disp_reg, type);
1562 }
1564 if (patch != NULL) {
1565 patching_epilog(patch, patch_code, src, info);
1566 }
1568 if (info != NULL) add_debug_info_for_null_check(offset, info);
1569 }
1572 void LIR_Assembler::return_op(LIR_Opr result) {
1573 // the poll may need a register so just pick one that isn't the return register
1574 #ifdef TIERED
1575 if (result->type_field() == LIR_OprDesc::long_type) {
1576 // Must move the result to G1
1577 // Must leave proper result in O0,O1 and G1 (TIERED only)
1578 __ sllx(I0, 32, G1); // Shift bits into high G1
1579 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
1580 __ or3 (I1, G1, G1); // OR 64 bits into G1
1581 }
1582 #endif // TIERED
1583 __ set((intptr_t)os::get_polling_page(), L0);
1584 __ relocate(relocInfo::poll_return_type);
1585 __ ld_ptr(L0, 0, G0);
1586 __ ret();
1587 __ delayed()->restore();
1588 }
1591 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1592 __ set((intptr_t)os::get_polling_page(), tmp->as_register());
1593 if (info != NULL) {
1594 add_debug_info_for_branch(info);
1595 } else {
1596 __ relocate(relocInfo::poll_type);
1597 }
1599 int offset = __ offset();
1600 __ ld_ptr(tmp->as_register(), 0, G0);
1602 return offset;
1603 }
1606 void LIR_Assembler::emit_static_call_stub() {
1607 address call_pc = __ pc();
1608 address stub = __ start_a_stub(call_stub_size);
1609 if (stub == NULL) {
1610 bailout("static call stub overflow");
1611 return;
1612 }
1614 int start = __ offset();
1615 __ relocate(static_stub_Relocation::spec(call_pc));
1617 __ set_oop(NULL, G5);
1618 // must be set to -1 at code generation time
1619 AddressLiteral addrlit(-1);
1620 __ jump_to(addrlit, G3);
1621 __ delayed()->nop();
1623 assert(__ offset() - start <= call_stub_size, "stub too big");
1624 __ end_a_stub();
1625 }
1628 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1629 if (opr1->is_single_fpu()) {
1630 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
1631 } else if (opr1->is_double_fpu()) {
1632 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
1633 } else if (opr1->is_single_cpu()) {
1634 if (opr2->is_constant()) {
1635 switch (opr2->as_constant_ptr()->type()) {
1636 case T_INT:
1637 { jint con = opr2->as_constant_ptr()->as_jint();
1638 if (Assembler::is_simm13(con)) {
1639 __ cmp(opr1->as_register(), con);
1640 } else {
1641 __ set(con, O7);
1642 __ cmp(opr1->as_register(), O7);
1643 }
1644 }
1645 break;
1647 case T_OBJECT:
1648 // there are only equal/notequal comparisions on objects
1649 { jobject con = opr2->as_constant_ptr()->as_jobject();
1650 if (con == NULL) {
1651 __ cmp(opr1->as_register(), 0);
1652 } else {
1653 jobject2reg(con, O7);
1654 __ cmp(opr1->as_register(), O7);
1655 }
1656 }
1657 break;
1659 default:
1660 ShouldNotReachHere();
1661 break;
1662 }
1663 } else {
1664 if (opr2->is_address()) {
1665 LIR_Address * addr = opr2->as_address_ptr();
1666 BasicType type = addr->type();
1667 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1668 else __ ld(as_Address(addr), O7);
1669 __ cmp(opr1->as_register(), O7);
1670 } else {
1671 __ cmp(opr1->as_register(), opr2->as_register());
1672 }
1673 }
1674 } else if (opr1->is_double_cpu()) {
1675 Register xlo = opr1->as_register_lo();
1676 Register xhi = opr1->as_register_hi();
1677 if (opr2->is_constant() && opr2->as_jlong() == 0) {
1678 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
1679 #ifdef _LP64
1680 __ orcc(xhi, G0, G0);
1681 #else
1682 __ orcc(xhi, xlo, G0);
1683 #endif
1684 } else if (opr2->is_register()) {
1685 Register ylo = opr2->as_register_lo();
1686 Register yhi = opr2->as_register_hi();
1687 #ifdef _LP64
1688 __ cmp(xlo, ylo);
1689 #else
1690 __ subcc(xlo, ylo, xlo);
1691 __ subccc(xhi, yhi, xhi);
1692 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1693 __ orcc(xhi, xlo, G0);
1694 }
1695 #endif
1696 } else {
1697 ShouldNotReachHere();
1698 }
1699 } else if (opr1->is_address()) {
1700 LIR_Address * addr = opr1->as_address_ptr();
1701 BasicType type = addr->type();
1702 assert (opr2->is_constant(), "Checking");
1703 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
1704 else __ ld(as_Address(addr), O7);
1705 __ cmp(O7, opr2->as_constant_ptr()->as_jint());
1706 } else {
1707 ShouldNotReachHere();
1708 }
1709 }
1712 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1713 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1714 bool is_unordered_less = (code == lir_ucmp_fd2i);
1715 if (left->is_single_fpu()) {
1716 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1717 } else if (left->is_double_fpu()) {
1718 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1719 } else {
1720 ShouldNotReachHere();
1721 }
1722 } else if (code == lir_cmp_l2i) {
1723 __ lcmp(left->as_register_hi(), left->as_register_lo(),
1724 right->as_register_hi(), right->as_register_lo(),
1725 dst->as_register());
1726 } else {
1727 ShouldNotReachHere();
1728 }
1729 }
1732 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
1734 Assembler::Condition acond;
1735 switch (condition) {
1736 case lir_cond_equal: acond = Assembler::equal; break;
1737 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1738 case lir_cond_less: acond = Assembler::less; break;
1739 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1740 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
1741 case lir_cond_greater: acond = Assembler::greater; break;
1742 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
1743 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
1744 default: ShouldNotReachHere();
1745 };
1747 if (opr1->is_constant() && opr1->type() == T_INT) {
1748 Register dest = result->as_register();
1749 // load up first part of constant before branch
1750 // and do the rest in the delay slot.
1751 if (!Assembler::is_simm13(opr1->as_jint())) {
1752 __ sethi(opr1->as_jint(), dest);
1753 }
1754 } else if (opr1->is_constant()) {
1755 const2reg(opr1, result, lir_patch_none, NULL);
1756 } else if (opr1->is_register()) {
1757 reg2reg(opr1, result);
1758 } else if (opr1->is_stack()) {
1759 stack2reg(opr1, result, result->type());
1760 } else {
1761 ShouldNotReachHere();
1762 }
1763 Label skip;
1764 __ br(acond, false, Assembler::pt, skip);
1765 if (opr1->is_constant() && opr1->type() == T_INT) {
1766 Register dest = result->as_register();
1767 if (Assembler::is_simm13(opr1->as_jint())) {
1768 __ delayed()->or3(G0, opr1->as_jint(), dest);
1769 } else {
1770 // the sethi has been done above, so just put in the low 10 bits
1771 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
1772 }
1773 } else {
1774 // can't do anything useful in the delay slot
1775 __ delayed()->nop();
1776 }
1777 if (opr2->is_constant()) {
1778 const2reg(opr2, result, lir_patch_none, NULL);
1779 } else if (opr2->is_register()) {
1780 reg2reg(opr2, result);
1781 } else if (opr2->is_stack()) {
1782 stack2reg(opr2, result, result->type());
1783 } else {
1784 ShouldNotReachHere();
1785 }
1786 __ bind(skip);
1787 }
1790 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1791 assert(info == NULL, "unused on this code path");
1792 assert(left->is_register(), "wrong items state");
1793 assert(dest->is_register(), "wrong items state");
1795 if (right->is_register()) {
1796 if (dest->is_float_kind()) {
1798 FloatRegister lreg, rreg, res;
1799 FloatRegisterImpl::Width w;
1800 if (right->is_single_fpu()) {
1801 w = FloatRegisterImpl::S;
1802 lreg = left->as_float_reg();
1803 rreg = right->as_float_reg();
1804 res = dest->as_float_reg();
1805 } else {
1806 w = FloatRegisterImpl::D;
1807 lreg = left->as_double_reg();
1808 rreg = right->as_double_reg();
1809 res = dest->as_double_reg();
1810 }
1812 switch (code) {
1813 case lir_add: __ fadd(w, lreg, rreg, res); break;
1814 case lir_sub: __ fsub(w, lreg, rreg, res); break;
1815 case lir_mul: // fall through
1816 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
1817 case lir_div: // fall through
1818 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
1819 default: ShouldNotReachHere();
1820 }
1822 } else if (dest->is_double_cpu()) {
1823 #ifdef _LP64
1824 Register dst_lo = dest->as_register_lo();
1825 Register op1_lo = left->as_pointer_register();
1826 Register op2_lo = right->as_pointer_register();
1828 switch (code) {
1829 case lir_add:
1830 __ add(op1_lo, op2_lo, dst_lo);
1831 break;
1833 case lir_sub:
1834 __ sub(op1_lo, op2_lo, dst_lo);
1835 break;
1837 default: ShouldNotReachHere();
1838 }
1839 #else
1840 Register op1_lo = left->as_register_lo();
1841 Register op1_hi = left->as_register_hi();
1842 Register op2_lo = right->as_register_lo();
1843 Register op2_hi = right->as_register_hi();
1844 Register dst_lo = dest->as_register_lo();
1845 Register dst_hi = dest->as_register_hi();
1847 switch (code) {
1848 case lir_add:
1849 __ addcc(op1_lo, op2_lo, dst_lo);
1850 __ addc (op1_hi, op2_hi, dst_hi);
1851 break;
1853 case lir_sub:
1854 __ subcc(op1_lo, op2_lo, dst_lo);
1855 __ subc (op1_hi, op2_hi, dst_hi);
1856 break;
1858 default: ShouldNotReachHere();
1859 }
1860 #endif
1861 } else {
1862 assert (right->is_single_cpu(), "Just Checking");
1864 Register lreg = left->as_register();
1865 Register res = dest->as_register();
1866 Register rreg = right->as_register();
1867 switch (code) {
1868 case lir_add: __ add (lreg, rreg, res); break;
1869 case lir_sub: __ sub (lreg, rreg, res); break;
1870 case lir_mul: __ mult (lreg, rreg, res); break;
1871 default: ShouldNotReachHere();
1872 }
1873 }
1874 } else {
1875 assert (right->is_constant(), "must be constant");
1877 if (dest->is_single_cpu()) {
1878 Register lreg = left->as_register();
1879 Register res = dest->as_register();
1880 int simm13 = right->as_constant_ptr()->as_jint();
1882 switch (code) {
1883 case lir_add: __ add (lreg, simm13, res); break;
1884 case lir_sub: __ sub (lreg, simm13, res); break;
1885 case lir_mul: __ mult (lreg, simm13, res); break;
1886 default: ShouldNotReachHere();
1887 }
1888 } else {
1889 Register lreg = left->as_pointer_register();
1890 Register res = dest->as_register_lo();
1891 long con = right->as_constant_ptr()->as_jlong();
1892 assert(Assembler::is_simm13(con), "must be simm13");
1894 switch (code) {
1895 case lir_add: __ add (lreg, (int)con, res); break;
1896 case lir_sub: __ sub (lreg, (int)con, res); break;
1897 case lir_mul: __ mult (lreg, (int)con, res); break;
1898 default: ShouldNotReachHere();
1899 }
1900 }
1901 }
1902 }
1905 void LIR_Assembler::fpop() {
1906 // do nothing
1907 }
1910 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1911 switch (code) {
1912 case lir_sin:
1913 case lir_tan:
1914 case lir_cos: {
1915 assert(thread->is_valid(), "preserve the thread object for performance reasons");
1916 assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
1917 break;
1918 }
1919 case lir_sqrt: {
1920 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1921 FloatRegister src_reg = value->as_double_reg();
1922 FloatRegister dst_reg = dest->as_double_reg();
1923 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
1924 break;
1925 }
1926 case lir_abs: {
1927 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1928 FloatRegister src_reg = value->as_double_reg();
1929 FloatRegister dst_reg = dest->as_double_reg();
1930 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
1931 break;
1932 }
1933 default: {
1934 ShouldNotReachHere();
1935 break;
1936 }
1937 }
1938 }
1941 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1942 if (right->is_constant()) {
1943 if (dest->is_single_cpu()) {
1944 int simm13 = right->as_constant_ptr()->as_jint();
1945 switch (code) {
1946 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
1947 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
1948 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
1949 default: ShouldNotReachHere();
1950 }
1951 } else {
1952 long c = right->as_constant_ptr()->as_jlong();
1953 assert(c == (int)c && Assembler::is_simm13(c), "out of range");
1954 int simm13 = (int)c;
1955 switch (code) {
1956 case lir_logic_and:
1957 #ifndef _LP64
1958 __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
1959 #endif
1960 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
1961 break;
1963 case lir_logic_or:
1964 #ifndef _LP64
1965 __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
1966 #endif
1967 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
1968 break;
1970 case lir_logic_xor:
1971 #ifndef _LP64
1972 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
1973 #endif
1974 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
1975 break;
1977 default: ShouldNotReachHere();
1978 }
1979 }
1980 } else {
1981 assert(right->is_register(), "right should be in register");
1983 if (dest->is_single_cpu()) {
1984 switch (code) {
1985 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
1986 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
1987 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
1988 default: ShouldNotReachHere();
1989 }
1990 } else {
1991 #ifdef _LP64
1992 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1993 left->as_register_lo();
1994 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1995 right->as_register_lo();
1997 switch (code) {
1998 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
1999 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
2000 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
2001 default: ShouldNotReachHere();
2002 }
2003 #else
2004 switch (code) {
2005 case lir_logic_and:
2006 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2007 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2008 break;
2010 case lir_logic_or:
2011 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2012 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2013 break;
2015 case lir_logic_xor:
2016 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
2017 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
2018 break;
2020 default: ShouldNotReachHere();
2021 }
2022 #endif
2023 }
2024 }
2025 }
2028 int LIR_Assembler::shift_amount(BasicType t) {
2029 int elem_size = type2aelembytes(t);
2030 switch (elem_size) {
2031 case 1 : return 0;
2032 case 2 : return 1;
2033 case 4 : return 2;
2034 case 8 : return 3;
2035 }
2036 ShouldNotReachHere();
2037 return -1;
2038 }
2041 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) {
2042 assert(exceptionOop->as_register() == Oexception, "should match");
2043 assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match");
2045 info->add_register_oop(exceptionOop);
2047 if (unwind) {
2048 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
2049 __ delayed()->nop();
2050 } else {
2051 // reuse the debug info from the safepoint poll for the throw op itself
2052 address pc_for_athrow = __ pc();
2053 int pc_for_athrow_offset = __ offset();
2054 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
2055 __ set(pc_for_athrow, Oissuing_pc, rspec);
2056 add_call_info(pc_for_athrow_offset, info); // for exception handler
2058 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
2059 __ delayed()->nop();
2060 }
2061 }
2064 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2065 Register src = op->src()->as_register();
2066 Register dst = op->dst()->as_register();
2067 Register src_pos = op->src_pos()->as_register();
2068 Register dst_pos = op->dst_pos()->as_register();
2069 Register length = op->length()->as_register();
2070 Register tmp = op->tmp()->as_register();
2071 Register tmp2 = O7;
2073 int flags = op->flags();
2074 ciArrayKlass* default_type = op->expected_type();
2075 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2076 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2078 // set up the arraycopy stub information
2079 ArrayCopyStub* stub = op->stub();
2081 // always do stub if no type information is available. it's ok if
2082 // the known type isn't loaded since the code sanity checks
2083 // in debug mode and the type isn't required when we know the exact type
2084 // also check that the type is an array type.
2085 // We also, for now, always call the stub if the barrier set requires a
2086 // write_ref_pre barrier (which the stub does, but none of the optimized
2087 // cases currently does).
2088 if (op->expected_type() == NULL ||
2089 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
2090 __ mov(src, O0);
2091 __ mov(src_pos, O1);
2092 __ mov(dst, O2);
2093 __ mov(dst_pos, O3);
2094 __ mov(length, O4);
2095 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
2097 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
2098 __ delayed()->nop();
2099 __ bind(*stub->continuation());
2100 return;
2101 }
2103 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
2105 // make sure src and dst are non-null and load array length
2106 if (flags & LIR_OpArrayCopy::src_null_check) {
2107 __ tst(src);
2108 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2109 __ delayed()->nop();
2110 }
2112 if (flags & LIR_OpArrayCopy::dst_null_check) {
2113 __ tst(dst);
2114 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2115 __ delayed()->nop();
2116 }
2118 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2119 // test src_pos register
2120 __ tst(src_pos);
2121 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2122 __ delayed()->nop();
2123 }
2125 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2126 // test dst_pos register
2127 __ tst(dst_pos);
2128 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2129 __ delayed()->nop();
2130 }
2132 if (flags & LIR_OpArrayCopy::length_positive_check) {
2133 // make sure length isn't negative
2134 __ tst(length);
2135 __ br(Assembler::less, false, Assembler::pn, *stub->entry());
2136 __ delayed()->nop();
2137 }
2139 if (flags & LIR_OpArrayCopy::src_range_check) {
2140 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
2141 __ add(length, src_pos, tmp);
2142 __ cmp(tmp2, tmp);
2143 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2144 __ delayed()->nop();
2145 }
2147 if (flags & LIR_OpArrayCopy::dst_range_check) {
2148 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
2149 __ add(length, dst_pos, tmp);
2150 __ cmp(tmp2, tmp);
2151 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
2152 __ delayed()->nop();
2153 }
2155 if (flags & LIR_OpArrayCopy::type_check) {
2156 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
2157 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2158 __ cmp(tmp, tmp2);
2159 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2160 __ delayed()->nop();
2161 }
2163 #ifdef ASSERT
2164 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2165 // Sanity check the known type with the incoming class. For the
2166 // primitive case the types must match exactly with src.klass and
2167 // dst.klass each exactly matching the default type. For the
2168 // object array case, if no type check is needed then either the
2169 // dst type is exactly the expected type and the src type is a
2170 // subtype which we can't check or src is the same array as dst
2171 // but not necessarily exactly of type default_type.
2172 Label known_ok, halt;
2173 jobject2reg(op->expected_type()->constant_encoding(), tmp);
2174 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
2175 if (basic_type != T_OBJECT) {
2176 __ cmp(tmp, tmp2);
2177 __ br(Assembler::notEqual, false, Assembler::pn, halt);
2178 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
2179 __ cmp(tmp, tmp2);
2180 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2181 __ delayed()->nop();
2182 } else {
2183 __ cmp(tmp, tmp2);
2184 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2185 __ delayed()->cmp(src, dst);
2186 __ br(Assembler::equal, false, Assembler::pn, known_ok);
2187 __ delayed()->nop();
2188 }
2189 __ bind(halt);
2190 __ stop("incorrect type information in arraycopy");
2191 __ bind(known_ok);
2192 }
2193 #endif
2195 int shift = shift_amount(basic_type);
2197 Register src_ptr = O0;
2198 Register dst_ptr = O1;
2199 Register len = O2;
2201 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
2202 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
2203 if (shift == 0) {
2204 __ add(src_ptr, src_pos, src_ptr);
2205 } else {
2206 __ sll(src_pos, shift, tmp);
2207 __ add(src_ptr, tmp, src_ptr);
2208 }
2210 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
2211 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
2212 if (shift == 0) {
2213 __ add(dst_ptr, dst_pos, dst_ptr);
2214 } else {
2215 __ sll(dst_pos, shift, tmp);
2216 __ add(dst_ptr, tmp, dst_ptr);
2217 }
2219 if (basic_type != T_OBJECT) {
2220 if (shift == 0) {
2221 __ mov(length, len);
2222 } else {
2223 __ sll(length, shift, len);
2224 }
2225 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
2226 } else {
2227 // oop_arraycopy takes a length in number of elements, so don't scale it.
2228 __ mov(length, len);
2229 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
2230 }
2232 __ bind(*stub->continuation());
2233 }
2236 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2237 if (dest->is_single_cpu()) {
2238 #ifdef _LP64
2239 if (left->type() == T_OBJECT) {
2240 switch (code) {
2241 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
2242 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
2243 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2244 default: ShouldNotReachHere();
2245 }
2246 } else
2247 #endif
2248 switch (code) {
2249 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
2250 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
2251 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
2252 default: ShouldNotReachHere();
2253 }
2254 } else {
2255 #ifdef _LP64
2256 switch (code) {
2257 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2258 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2259 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
2260 default: ShouldNotReachHere();
2261 }
2262 #else
2263 switch (code) {
2264 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2265 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2266 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
2267 default: ShouldNotReachHere();
2268 }
2269 #endif
2270 }
2271 }
2274 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2275 #ifdef _LP64
2276 if (left->type() == T_OBJECT) {
2277 count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
2278 Register l = left->as_register();
2279 Register d = dest->as_register_lo();
2280 switch (code) {
2281 case lir_shl: __ sllx (l, count, d); break;
2282 case lir_shr: __ srax (l, count, d); break;
2283 case lir_ushr: __ srlx (l, count, d); break;
2284 default: ShouldNotReachHere();
2285 }
2286 return;
2287 }
2288 #endif
2290 if (dest->is_single_cpu()) {
2291 count = count & 0x1F; // Java spec
2292 switch (code) {
2293 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
2294 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
2295 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
2296 default: ShouldNotReachHere();
2297 }
2298 } else if (dest->is_double_cpu()) {
2299 count = count & 63; // Java spec
2300 switch (code) {
2301 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2302 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2303 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
2304 default: ShouldNotReachHere();
2305 }
2306 } else {
2307 ShouldNotReachHere();
2308 }
2309 }
2312 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2313 assert(op->tmp1()->as_register() == G1 &&
2314 op->tmp2()->as_register() == G3 &&
2315 op->tmp3()->as_register() == G4 &&
2316 op->obj()->as_register() == O0 &&
2317 op->klass()->as_register() == G5, "must be");
2318 if (op->init_check()) {
2319 __ ld(op->klass()->as_register(),
2320 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
2321 op->tmp1()->as_register());
2322 add_debug_info_for_null_check_here(op->stub()->info());
2323 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
2324 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
2325 __ delayed()->nop();
2326 }
2327 __ allocate_object(op->obj()->as_register(),
2328 op->tmp1()->as_register(),
2329 op->tmp2()->as_register(),
2330 op->tmp3()->as_register(),
2331 op->header_size(),
2332 op->object_size(),
2333 op->klass()->as_register(),
2334 *op->stub()->entry());
2335 __ bind(*op->stub()->continuation());
2336 __ verify_oop(op->obj()->as_register());
2337 }
2340 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2341 assert(op->tmp1()->as_register() == G1 &&
2342 op->tmp2()->as_register() == G3 &&
2343 op->tmp3()->as_register() == G4 &&
2344 op->tmp4()->as_register() == O1 &&
2345 op->klass()->as_register() == G5, "must be");
2346 if (UseSlowPath ||
2347 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2348 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2349 __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry());
2350 __ delayed()->nop();
2351 } else {
2352 __ allocate_array(op->obj()->as_register(),
2353 op->len()->as_register(),
2354 op->tmp1()->as_register(),
2355 op->tmp2()->as_register(),
2356 op->tmp3()->as_register(),
2357 arrayOopDesc::header_size(op->type()),
2358 type2aelembytes(op->type()),
2359 op->klass()->as_register(),
2360 *op->stub()->entry());
2361 }
2362 __ bind(*op->stub()->continuation());
2363 }
2366 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2367 LIR_Code code = op->code();
2368 if (code == lir_store_check) {
2369 Register value = op->object()->as_register();
2370 Register array = op->array()->as_register();
2371 Register k_RInfo = op->tmp1()->as_register();
2372 Register klass_RInfo = op->tmp2()->as_register();
2373 Register Rtmp1 = op->tmp3()->as_register();
2375 __ verify_oop(value);
2377 CodeStub* stub = op->stub();
2378 Label done;
2379 __ cmp(value, 0);
2380 __ br(Assembler::equal, false, Assembler::pn, done);
2381 __ delayed()->nop();
2382 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
2383 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2385 // get instance klass
2386 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
2387 // perform the fast part of the checking logic
2388 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL);
2390 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2391 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2392 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2393 __ delayed()->nop();
2394 __ cmp(G3, 0);
2395 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2396 __ delayed()->nop();
2397 __ bind(done);
2398 } else if (op->code() == lir_checkcast) {
2399 // we always need a stub for the failure case.
2400 CodeStub* stub = op->stub();
2401 Register obj = op->object()->as_register();
2402 Register k_RInfo = op->tmp1()->as_register();
2403 Register klass_RInfo = op->tmp2()->as_register();
2404 Register dst = op->result_opr()->as_register();
2405 Register Rtmp1 = op->tmp3()->as_register();
2406 ciKlass* k = op->klass();
2408 if (obj == k_RInfo) {
2409 k_RInfo = klass_RInfo;
2410 klass_RInfo = obj;
2411 }
2412 if (op->profiled_method() != NULL) {
2413 ciMethod* method = op->profiled_method();
2414 int bci = op->profiled_bci();
2416 // We need two temporaries to perform this operation on SPARC,
2417 // so to keep things simple we perform a redundant test here
2418 Label profile_done;
2419 __ cmp(obj, 0);
2420 __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
2421 __ delayed()->nop();
2422 // Object is null; update methodDataOop
2423 ciMethodData* md = method->method_data();
2424 if (md == NULL) {
2425 bailout("out of memory building methodDataOop");
2426 return;
2427 }
2428 ciProfileData* data = md->bci_to_data(bci);
2429 assert(data != NULL, "need data for checkcast");
2430 assert(data->is_BitData(), "need BitData for checkcast");
2431 Register mdo = k_RInfo;
2432 Register data_val = Rtmp1;
2433 jobject2reg(md->constant_encoding(), mdo);
2435 int mdo_offset_bias = 0;
2436 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2437 // The offset is large so bias the mdo by the base of the slot so
2438 // that the ld can use simm13s to reference the slots of the data
2439 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2440 __ set(mdo_offset_bias, data_val);
2441 __ add(mdo, data_val, mdo);
2442 }
2445 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
2446 __ ldub(flags_addr, data_val);
2447 __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
2448 __ stb(data_val, flags_addr);
2449 __ bind(profile_done);
2450 }
2452 Label done;
2453 // patching may screw with our temporaries on sparc,
2454 // so let's do it before loading the class
2455 if (k->is_loaded()) {
2456 jobject2reg(k->constant_encoding(), k_RInfo);
2457 } else {
2458 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2459 }
2460 assert(obj != k_RInfo, "must be different");
2461 __ cmp(obj, 0);
2462 __ br(Assembler::equal, false, Assembler::pn, done);
2463 __ delayed()->nop();
2465 // get object class
2466 // not a safepoint as obj null check happens earlier
2467 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2468 if (op->fast_check()) {
2469 assert_different_registers(klass_RInfo, k_RInfo);
2470 __ cmp(k_RInfo, klass_RInfo);
2471 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
2472 __ delayed()->nop();
2473 __ bind(done);
2474 } else {
2475 bool need_slow_path = true;
2476 if (k->is_loaded()) {
2477 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2478 need_slow_path = false;
2479 // perform the fast part of the checking logic
2480 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
2481 (need_slow_path ? &done : NULL),
2482 stub->entry(), NULL,
2483 RegisterOrConstant(k->super_check_offset()));
2484 } else {
2485 // perform the fast part of the checking logic
2486 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7,
2487 &done, stub->entry(), NULL);
2488 }
2489 if (need_slow_path) {
2490 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2491 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2492 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2493 __ delayed()->nop();
2494 __ cmp(G3, 0);
2495 __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
2496 __ delayed()->nop();
2497 }
2498 __ bind(done);
2499 }
2500 __ mov(obj, dst);
2501 } else if (code == lir_instanceof) {
2502 Register obj = op->object()->as_register();
2503 Register k_RInfo = op->tmp1()->as_register();
2504 Register klass_RInfo = op->tmp2()->as_register();
2505 Register dst = op->result_opr()->as_register();
2506 Register Rtmp1 = op->tmp3()->as_register();
2507 ciKlass* k = op->klass();
2509 Label done;
2510 if (obj == k_RInfo) {
2511 k_RInfo = klass_RInfo;
2512 klass_RInfo = obj;
2513 }
2514 // patching may screw with our temporaries on sparc,
2515 // so let's do it before loading the class
2516 if (k->is_loaded()) {
2517 jobject2reg(k->constant_encoding(), k_RInfo);
2518 } else {
2519 jobject2reg_with_patching(k_RInfo, op->info_for_patch());
2520 }
2521 assert(obj != k_RInfo, "must be different");
2522 __ cmp(obj, 0);
2523 __ br(Assembler::equal, true, Assembler::pn, done);
2524 __ delayed()->set(0, dst);
2526 // get object class
2527 // not a safepoint as obj null check happens earlier
2528 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
2529 if (op->fast_check()) {
2530 __ cmp(k_RInfo, klass_RInfo);
2531 __ br(Assembler::equal, true, Assembler::pt, done);
2532 __ delayed()->set(1, dst);
2533 __ set(0, dst);
2534 __ bind(done);
2535 } else {
2536 bool need_slow_path = true;
2537 if (k->is_loaded()) {
2538 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
2539 need_slow_path = false;
2540 // perform the fast part of the checking logic
2541 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg,
2542 (need_slow_path ? &done : NULL),
2543 (need_slow_path ? &done : NULL), NULL,
2544 RegisterOrConstant(k->super_check_offset()),
2545 dst);
2546 } else {
2547 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
2548 // perform the fast part of the checking logic
2549 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst,
2550 &done, &done, NULL,
2551 RegisterOrConstant(-1),
2552 dst);
2553 }
2554 if (need_slow_path) {
2555 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
2556 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
2557 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
2558 __ delayed()->nop();
2559 __ mov(G3, dst);
2560 }
2561 __ bind(done);
2562 }
2563 } else {
2564 ShouldNotReachHere();
2565 }
2567 }
2570 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2571 if (op->code() == lir_cas_long) {
2572 assert(VM_Version::supports_cx8(), "wrong machine");
2573 Register addr = op->addr()->as_pointer_register();
2574 Register cmp_value_lo = op->cmp_value()->as_register_lo();
2575 Register cmp_value_hi = op->cmp_value()->as_register_hi();
2576 Register new_value_lo = op->new_value()->as_register_lo();
2577 Register new_value_hi = op->new_value()->as_register_hi();
2578 Register t1 = op->tmp1()->as_register();
2579 Register t2 = op->tmp2()->as_register();
2580 #ifdef _LP64
2581 __ mov(cmp_value_lo, t1);
2582 __ mov(new_value_lo, t2);
2583 #else
2584 // move high and low halves of long values into single registers
2585 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
2586 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
2587 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
2588 __ sllx(new_value_hi, 32, t2);
2589 __ srl(new_value_lo, 0, new_value_lo);
2590 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
2591 #endif
2592 // perform the compare and swap operation
2593 __ casx(addr, t1, t2);
2594 // generate condition code - if the swap succeeded, t2 ("new value" reg) was
2595 // overwritten with the original value in "addr" and will be equal to t1.
2596 __ cmp(t1, t2);
2598 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2599 Register addr = op->addr()->as_pointer_register();
2600 Register cmp_value = op->cmp_value()->as_register();
2601 Register new_value = op->new_value()->as_register();
2602 Register t1 = op->tmp1()->as_register();
2603 Register t2 = op->tmp2()->as_register();
2604 __ mov(cmp_value, t1);
2605 __ mov(new_value, t2);
2606 #ifdef _LP64
2607 if (op->code() == lir_cas_obj) {
2608 __ casx(addr, t1, t2);
2609 } else
2610 #endif
2611 {
2612 __ cas(addr, t1, t2);
2613 }
2614 __ cmp(t1, t2);
2615 } else {
2616 Unimplemented();
2617 }
2618 }
2620 void LIR_Assembler::set_24bit_FPU() {
2621 Unimplemented();
2622 }
2625 void LIR_Assembler::reset_FPU() {
2626 Unimplemented();
2627 }
2630 void LIR_Assembler::breakpoint() {
2631 __ breakpoint_trap();
2632 }
2635 void LIR_Assembler::push(LIR_Opr opr) {
2636 Unimplemented();
2637 }
2640 void LIR_Assembler::pop(LIR_Opr opr) {
2641 Unimplemented();
2642 }
2645 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2646 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2647 Register dst = dst_opr->as_register();
2648 Register reg = mon_addr.base();
2649 int offset = mon_addr.disp();
2650 // compute pointer to BasicLock
2651 if (mon_addr.is_simm13()) {
2652 __ add(reg, offset, dst);
2653 } else {
2654 __ set(offset, dst);
2655 __ add(dst, reg, dst);
2656 }
2657 }
2660 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2661 Register obj = op->obj_opr()->as_register();
2662 Register hdr = op->hdr_opr()->as_register();
2663 Register lock = op->lock_opr()->as_register();
2665 // obj may not be an oop
2666 if (op->code() == lir_lock) {
2667 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2668 if (UseFastLocking) {
2669 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2670 // add debug info for NullPointerException only if one is possible
2671 if (op->info() != NULL) {
2672 add_debug_info_for_null_check_here(op->info());
2673 }
2674 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2675 } else {
2676 // always do slow locking
2677 // note: the slow locking code could be inlined here, however if we use
2678 // slow locking, speed doesn't matter anyway and this solution is
2679 // simpler and requires less duplicated code - additionally, the
2680 // slow locking code is the same in either case which simplifies
2681 // debugging
2682 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2683 __ delayed()->nop();
2684 }
2685 } else {
2686 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2687 if (UseFastLocking) {
2688 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2689 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2690 } else {
2691 // always do slow unlocking
2692 // note: the slow unlocking code could be inlined here, however if we use
2693 // slow unlocking, speed doesn't matter anyway and this solution is
2694 // simpler and requires less duplicated code - additionally, the
2695 // slow unlocking code is the same in either case which simplifies
2696 // debugging
2697 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
2698 __ delayed()->nop();
2699 }
2700 }
2701 __ bind(*op->stub()->continuation());
2702 }
2705 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2706 ciMethod* method = op->profiled_method();
2707 int bci = op->profiled_bci();
2709 // Update counter for all call types
2710 ciMethodData* md = method->method_data();
2711 if (md == NULL) {
2712 bailout("out of memory building methodDataOop");
2713 return;
2714 }
2715 ciProfileData* data = md->bci_to_data(bci);
2716 assert(data->is_CounterData(), "need CounterData for calls");
2717 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2718 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2719 Register mdo = op->mdo()->as_register();
2720 Register tmp1 = op->tmp1()->as_register();
2721 jobject2reg(md->constant_encoding(), mdo);
2722 int mdo_offset_bias = 0;
2723 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2724 data->size_in_bytes())) {
2725 // The offset is large so bias the mdo by the base of the slot so
2726 // that the ld can use simm13s to reference the slots of the data
2727 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2728 __ set(mdo_offset_bias, O7);
2729 __ add(mdo, O7, mdo);
2730 }
2732 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2733 Bytecodes::Code bc = method->java_code_at_bci(bci);
2734 // Perform additional virtual call profiling for invokevirtual and
2735 // invokeinterface bytecodes
2736 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2737 Tier1ProfileVirtualCalls) {
2738 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2739 Register recv = op->recv()->as_register();
2740 assert_different_registers(mdo, tmp1, recv);
2741 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2742 ciKlass* known_klass = op->known_holder();
2743 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
2744 // We know the type that will be seen at this call site; we can
2745 // statically update the methodDataOop rather than needing to do
2746 // dynamic tests on the receiver type
2748 // NOTE: we should probably put a lock around this search to
2749 // avoid collisions by concurrent compilations
2750 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2751 uint i;
2752 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2753 ciKlass* receiver = vc_data->receiver(i);
2754 if (known_klass->equals(receiver)) {
2755 Address data_addr(mdo, md->byte_offset_of_slot(data,
2756 VirtualCallData::receiver_count_offset(i)) -
2757 mdo_offset_bias);
2758 __ lduw(data_addr, tmp1);
2759 __ add(tmp1, DataLayout::counter_increment, tmp1);
2760 __ stw(tmp1, data_addr);
2761 return;
2762 }
2763 }
2765 // Receiver type not found in profile data; select an empty slot
2767 // Note that this is less efficient than it should be because it
2768 // always does a write to the receiver part of the
2769 // VirtualCallData rather than just the first time
2770 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2771 ciKlass* receiver = vc_data->receiver(i);
2772 if (receiver == NULL) {
2773 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2774 mdo_offset_bias);
2775 jobject2reg(known_klass->constant_encoding(), tmp1);
2776 __ st_ptr(tmp1, recv_addr);
2777 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2778 mdo_offset_bias);
2779 __ lduw(data_addr, tmp1);
2780 __ add(tmp1, DataLayout::counter_increment, tmp1);
2781 __ stw(tmp1, data_addr);
2782 return;
2783 }
2784 }
2785 } else {
2786 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
2787 Label update_done;
2788 uint i;
2789 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2790 Label next_test;
2791 // See if the receiver is receiver[n].
2792 Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2793 mdo_offset_bias);
2794 __ ld_ptr(receiver_addr, tmp1);
2795 __ verify_oop(tmp1);
2796 __ cmp(recv, tmp1);
2797 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2798 __ delayed()->nop();
2799 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2800 mdo_offset_bias);
2801 __ lduw(data_addr, tmp1);
2802 __ add(tmp1, DataLayout::counter_increment, tmp1);
2803 __ stw(tmp1, data_addr);
2804 __ br(Assembler::always, false, Assembler::pt, update_done);
2805 __ delayed()->nop();
2806 __ bind(next_test);
2807 }
2809 // Didn't find receiver; find next empty slot and fill it in
2810 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2811 Label next_test;
2812 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2813 mdo_offset_bias);
2814 load(recv_addr, tmp1, T_OBJECT);
2815 __ tst(tmp1);
2816 __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
2817 __ delayed()->nop();
2818 __ st_ptr(recv, recv_addr);
2819 __ set(DataLayout::counter_increment, tmp1);
2820 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2821 mdo_offset_bias);
2822 __ br(Assembler::always, false, Assembler::pt, update_done);
2823 __ delayed()->nop();
2824 __ bind(next_test);
2825 }
2826 // Receiver did not match any saved receiver and there is no empty row for it.
2827 // Increment total counter to indicate polymorphic case.
2828 __ lduw(counter_addr, tmp1);
2829 __ add(tmp1, DataLayout::counter_increment, tmp1);
2830 __ stw(tmp1, counter_addr);
2832 __ bind(update_done);
2833 }
2834 } else {
2835 // Static call
2836 __ lduw(counter_addr, tmp1);
2837 __ add(tmp1, DataLayout::counter_increment, tmp1);
2838 __ stw(tmp1, counter_addr);
2839 }
2840 }
2843 void LIR_Assembler::align_backward_branch_target() {
2844 __ align(16);
2845 }
2848 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2849 // make sure we are expecting a delay
2850 // this has the side effect of clearing the delay state
2851 // so we can use _masm instead of _masm->delayed() to do the
2852 // code generation.
2853 __ delayed();
2855 // make sure we only emit one instruction
2856 int offset = code_offset();
2857 op->delay_op()->emit_code(this);
2858 #ifdef ASSERT
2859 if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
2860 op->delay_op()->print();
2861 }
2862 assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
2863 "only one instruction can go in a delay slot");
2864 #endif
2866 // we may also be emitting the call info for the instruction
2867 // which we are the delay slot of.
2868 CodeEmitInfo * call_info = op->call_info();
2869 if (call_info) {
2870 add_call_info(code_offset(), call_info);
2871 }
2873 if (VerifyStackAtCalls) {
2874 _masm->sub(FP, SP, O7);
2875 _masm->cmp(O7, initial_frame_size_in_bytes());
2876 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
2877 }
2878 }
2881 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2882 assert(left->is_register(), "can only handle registers");
2884 if (left->is_single_cpu()) {
2885 __ neg(left->as_register(), dest->as_register());
2886 } else if (left->is_single_fpu()) {
2887 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
2888 } else if (left->is_double_fpu()) {
2889 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
2890 } else {
2891 assert (left->is_double_cpu(), "Must be a long");
2892 Register Rlow = left->as_register_lo();
2893 Register Rhi = left->as_register_hi();
2894 #ifdef _LP64
2895 __ sub(G0, Rlow, dest->as_register_lo());
2896 #else
2897 __ subcc(G0, Rlow, dest->as_register_lo());
2898 __ subc (G0, Rhi, dest->as_register_hi());
2899 #endif
2900 }
2901 }
2904 void LIR_Assembler::fxch(int i) {
2905 Unimplemented();
2906 }
2908 void LIR_Assembler::fld(int i) {
2909 Unimplemented();
2910 }
2912 void LIR_Assembler::ffree(int i) {
2913 Unimplemented();
2914 }
2916 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2917 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2919 // if tmp is invalid, then the function being called doesn't destroy the thread
2920 if (tmp->is_valid()) {
2921 __ save_thread(tmp->as_register());
2922 }
2923 __ call(dest, relocInfo::runtime_call_type);
2924 __ delayed()->nop();
2925 if (info != NULL) {
2926 add_call_info_here(info);
2927 }
2928 if (tmp->is_valid()) {
2929 __ restore_thread(tmp->as_register());
2930 }
2932 #ifdef ASSERT
2933 __ verify_thread();
2934 #endif // ASSERT
2935 }
2938 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2939 #ifdef _LP64
2940 ShouldNotReachHere();
2941 #endif
2943 NEEDS_CLEANUP;
2944 if (type == T_LONG) {
2945 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
2947 // (extended to allow indexed as well as constant displaced for JSR-166)
2948 Register idx = noreg; // contains either constant offset or index
2950 int disp = mem_addr->disp();
2951 if (mem_addr->index() == LIR_OprFact::illegalOpr) {
2952 if (!Assembler::is_simm13(disp)) {
2953 idx = O7;
2954 __ set(disp, idx);
2955 }
2956 } else {
2957 assert(disp == 0, "not both indexed and disp");
2958 idx = mem_addr->index()->as_register();
2959 }
2961 int null_check_offset = -1;
2963 Register base = mem_addr->base()->as_register();
2964 if (src->is_register() && dest->is_address()) {
2965 // G4 is high half, G5 is low half
2966 if (VM_Version::v9_instructions_work()) {
2967 // clear the top bits of G5, and scale up G4
2968 __ srl (src->as_register_lo(), 0, G5);
2969 __ sllx(src->as_register_hi(), 32, G4);
2970 // combine the two halves into the 64 bits of G4
2971 __ or3(G4, G5, G4);
2972 null_check_offset = __ offset();
2973 if (idx == noreg) {
2974 __ stx(G4, base, disp);
2975 } else {
2976 __ stx(G4, base, idx);
2977 }
2978 } else {
2979 __ mov (src->as_register_hi(), G4);
2980 __ mov (src->as_register_lo(), G5);
2981 null_check_offset = __ offset();
2982 if (idx == noreg) {
2983 __ std(G4, base, disp);
2984 } else {
2985 __ std(G4, base, idx);
2986 }
2987 }
2988 } else if (src->is_address() && dest->is_register()) {
2989 null_check_offset = __ offset();
2990 if (VM_Version::v9_instructions_work()) {
2991 if (idx == noreg) {
2992 __ ldx(base, disp, G5);
2993 } else {
2994 __ ldx(base, idx, G5);
2995 }
2996 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
2997 __ mov (G5, dest->as_register_lo()); // copy low half into lo
2998 } else {
2999 if (idx == noreg) {
3000 __ ldd(base, disp, G4);
3001 } else {
3002 __ ldd(base, idx, G4);
3003 }
3004 // G4 is high half, G5 is low half
3005 __ mov (G4, dest->as_register_hi());
3006 __ mov (G5, dest->as_register_lo());
3007 }
3008 } else {
3009 Unimplemented();
3010 }
3011 if (info != NULL) {
3012 add_debug_info_for_null_check(null_check_offset, info);
3013 }
3015 } else {
3016 // use normal move for all other volatiles since they don't need
3017 // special handling to remain atomic.
3018 move_op(src, dest, type, lir_patch_none, info, false, false);
3019 }
3020 }
3022 void LIR_Assembler::membar() {
3023 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
3024 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3025 }
3027 void LIR_Assembler::membar_acquire() {
3028 // no-op on TSO
3029 }
3031 void LIR_Assembler::membar_release() {
3032 // no-op on TSO
3033 }
3035 // Macro to Pack two sequential registers containing 32 bit values
3036 // into a single 64 bit register.
3037 // rs and rs->successor() are packed into rd
3038 // rd and rs may be the same register.
3039 // Note: rs and rs->successor() are destroyed.
3040 void LIR_Assembler::pack64( Register rs, Register rd ) {
3041 __ sllx(rs, 32, rs);
3042 __ srl(rs->successor(), 0, rs->successor());
3043 __ or3(rs, rs->successor(), rd);
3044 }
3046 // Macro to unpack a 64 bit value in a register into
3047 // two sequential registers.
3048 // rd is unpacked into rd and rd->successor()
3049 void LIR_Assembler::unpack64( Register rd ) {
3050 __ mov(rd, rd->successor());
3051 __ srax(rd, 32, rd);
3052 __ sra(rd->successor(), 0, rd->successor());
3053 }
3056 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
3057 LIR_Address* addr = addr_opr->as_address_ptr();
3058 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
3059 __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
3060 }
3063 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3064 assert(result_reg->is_register(), "check");
3065 __ mov(G2_thread, result_reg->as_register());
3066 }
3069 void LIR_Assembler::peephole(LIR_List* lir) {
3070 LIR_OpList* inst = lir->instructions_list();
3071 for (int i = 0; i < inst->length(); i++) {
3072 LIR_Op* op = inst->at(i);
3073 switch (op->code()) {
3074 case lir_cond_float_branch:
3075 case lir_branch: {
3076 LIR_OpBranch* branch = op->as_OpBranch();
3077 assert(branch->info() == NULL, "shouldn't be state on branches anymore");
3078 LIR_Op* delay_op = NULL;
3079 // we'd like to be able to pull following instructions into
3080 // this slot but we don't know enough to do it safely yet so
3081 // only optimize block to block control flow.
3082 if (LIRFillDelaySlots && branch->block()) {
3083 LIR_Op* prev = inst->at(i - 1);
3084 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
3085 // swap previous instruction into delay slot
3086 inst->at_put(i - 1, op);
3087 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3088 #ifndef PRODUCT
3089 if (LIRTracePeephole) {
3090 tty->print_cr("delayed");
3091 inst->at(i - 1)->print();
3092 inst->at(i)->print();
3093 }
3094 #endif
3095 continue;
3096 }
3097 }
3099 if (!delay_op) {
3100 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
3101 }
3102 inst->insert_before(i + 1, delay_op);
3103 break;
3104 }
3105 case lir_static_call:
3106 case lir_virtual_call:
3107 case lir_icvirtual_call:
3108 case lir_optvirtual_call: {
3109 LIR_Op* delay_op = NULL;
3110 LIR_Op* prev = inst->at(i - 1);
3111 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
3112 (op->code() != lir_virtual_call ||
3113 !prev->result_opr()->is_single_cpu() ||
3114 prev->result_opr()->as_register() != O0) &&
3115 LIR_Assembler::is_single_instruction(prev)) {
3116 // Only moves without info can be put into the delay slot.
3117 // Also don't allow the setup of the receiver in the delay
3118 // slot for vtable calls.
3119 inst->at_put(i - 1, op);
3120 inst->at_put(i, new LIR_OpDelay(prev, op->info()));
3121 #ifndef PRODUCT
3122 if (LIRTracePeephole) {
3123 tty->print_cr("delayed");
3124 inst->at(i - 1)->print();
3125 inst->at(i)->print();
3126 }
3127 #endif
3128 continue;
3129 }
3131 if (!delay_op) {
3132 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
3133 inst->insert_before(i + 1, delay_op);
3134 }
3135 break;
3136 }
3137 }
3138 }
3139 }
3144 #undef __