Tue, 25 Feb 2014 15:11:18 -0800
Merge
1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
25 // SPARC Architecture Description File
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
463 extern bool use_block_zeroing(Node* count);
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
471 %}
473 source %{
474 #define __ _masm.
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
532 // ****************************************************************************
534 // REQUIRED FUNCTIONALITY
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedClassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
563 } else {
564 klass_load_size = 1*BytesPerInstWord;
565 }
566 if (Assembler::is_simm13(v_off)) {
567 return klass_load_size +
568 (2*BytesPerInstWord + // ld_ptr, ld_ptr
569 NativeCall::instruction_size); // call; delay slot
570 } else {
571 return klass_load_size +
572 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
573 NativeCall::instruction_size); // call; delay slot
574 }
575 }
576 }
578 int MachCallRuntimeNode::ret_addr_offset() {
579 #ifdef _LP64
580 if (MacroAssembler::is_far_target(entry_point())) {
581 return NativeFarCall::instruction_size;
582 } else {
583 return NativeCall::instruction_size;
584 }
585 #else
586 return NativeCall::instruction_size; // call; delay slot
587 #endif
588 }
590 // Indicate if the safepoint node needs the polling page as an input.
591 // Since Sparc does not have absolute addressing, it does.
592 bool SafePointNode::needs_polling_address_input() {
593 return true;
594 }
596 // emit an interrupt that is caught by the debugger (for debugging compiler)
597 void emit_break(CodeBuffer &cbuf) {
598 MacroAssembler _masm(&cbuf);
599 __ breakpoint_trap();
600 }
602 #ifndef PRODUCT
603 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
604 st->print("TA");
605 }
606 #endif
608 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
609 emit_break(cbuf);
610 }
612 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
613 return MachNode::size(ra_);
614 }
616 // Traceable jump
617 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
618 MacroAssembler _masm(&cbuf);
619 Register rdest = reg_to_register_object(jump_target);
620 __ JMP(rdest, 0);
621 __ delayed()->nop();
622 }
624 // Traceable jump and set exception pc
625 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
626 MacroAssembler _masm(&cbuf);
627 Register rdest = reg_to_register_object(jump_target);
628 __ JMP(rdest, 0);
629 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
630 }
632 void emit_nop(CodeBuffer &cbuf) {
633 MacroAssembler _masm(&cbuf);
634 __ nop();
635 }
637 void emit_illtrap(CodeBuffer &cbuf) {
638 MacroAssembler _masm(&cbuf);
639 __ illtrap(0);
640 }
643 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
644 assert(n->rule() != loadUB_rule, "");
646 intptr_t offset = 0;
647 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
648 const Node* addr = n->get_base_and_disp(offset, adr_type);
649 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
650 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
651 assert(addr->bottom_type()->isa_oopptr() == atype, "");
652 atype = atype->add_offset(offset);
653 assert(disp32 == offset, "wrong disp32");
654 return atype->_offset;
655 }
658 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
659 assert(n->rule() != loadUB_rule, "");
661 intptr_t offset = 0;
662 Node* addr = n->in(2);
663 assert(addr->bottom_type()->isa_oopptr() == atype, "");
664 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
665 Node* a = addr->in(2/*AddPNode::Address*/);
666 Node* o = addr->in(3/*AddPNode::Offset*/);
667 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
668 atype = a->bottom_type()->is_ptr()->add_offset(offset);
669 assert(atype->isa_oop_ptr(), "still an oop");
670 }
671 offset = atype->is_ptr()->_offset;
672 if (offset != Type::OffsetBot) offset += disp32;
673 return offset;
674 }
676 static inline jdouble replicate_immI(int con, int count, int width) {
677 // Load a constant replicated "count" times with width "width"
678 assert(count*width == 8 && width <= 4, "sanity");
679 int bit_width = width * 8;
680 jlong val = con;
681 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
682 for (int i = 0; i < count - 1; i++) {
683 val |= (val << bit_width);
684 }
685 jdouble dval = *((jdouble*) &val); // coerce to double type
686 return dval;
687 }
689 static inline jdouble replicate_immF(float con) {
690 // Replicate float con 2 times and pack into vector.
691 int val = *((int*)&con);
692 jlong lval = val;
693 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
694 jdouble dval = *((jdouble*) &lval); // coerce to double type
695 return dval;
696 }
698 // Standard Sparc opcode form2 field breakdown
699 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
700 f0 &= (1<<19)-1; // Mask displacement to 19 bits
701 int op = (f30 << 30) |
702 (f29 << 29) |
703 (f25 << 25) |
704 (f22 << 22) |
705 (f20 << 20) |
706 (f19 << 19) |
707 (f0 << 0);
708 cbuf.insts()->emit_int32(op);
709 }
711 // Standard Sparc opcode form2 field breakdown
712 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
713 f0 >>= 10; // Drop 10 bits
714 f0 &= (1<<22)-1; // Mask displacement to 22 bits
715 int op = (f30 << 30) |
716 (f25 << 25) |
717 (f22 << 22) |
718 (f0 << 0);
719 cbuf.insts()->emit_int32(op);
720 }
722 // Standard Sparc opcode form3 field breakdown
723 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
724 int op = (f30 << 30) |
725 (f25 << 25) |
726 (f19 << 19) |
727 (f14 << 14) |
728 (f5 << 5) |
729 (f0 << 0);
730 cbuf.insts()->emit_int32(op);
731 }
733 // Standard Sparc opcode form3 field breakdown
734 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
735 simm13 &= (1<<13)-1; // Mask to 13 bits
736 int op = (f30 << 30) |
737 (f25 << 25) |
738 (f19 << 19) |
739 (f14 << 14) |
740 (1 << 13) | // bit to indicate immediate-mode
741 (simm13<<0);
742 cbuf.insts()->emit_int32(op);
743 }
745 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
746 simm10 &= (1<<10)-1; // Mask to 10 bits
747 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
748 }
750 #ifdef ASSERT
751 // Helper function for VerifyOops in emit_form3_mem_reg
752 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
753 warning("VerifyOops encountered unexpected instruction:");
754 n->dump(2);
755 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
756 }
757 #endif
760 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
761 int src1_enc, int disp32, int src2_enc, int dst_enc) {
763 #ifdef ASSERT
764 // The following code implements the +VerifyOops feature.
765 // It verifies oop values which are loaded into or stored out of
766 // the current method activation. +VerifyOops complements techniques
767 // like ScavengeALot, because it eagerly inspects oops in transit,
768 // as they enter or leave the stack, as opposed to ScavengeALot,
769 // which inspects oops "at rest", in the stack or heap, at safepoints.
770 // For this reason, +VerifyOops can sometimes detect bugs very close
771 // to their point of creation. It can also serve as a cross-check
772 // on the validity of oop maps, when used toegether with ScavengeALot.
774 // It would be good to verify oops at other points, especially
775 // when an oop is used as a base pointer for a load or store.
776 // This is presently difficult, because it is hard to know when
777 // a base address is biased or not. (If we had such information,
778 // it would be easy and useful to make a two-argument version of
779 // verify_oop which unbiases the base, and performs verification.)
781 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
782 bool is_verified_oop_base = false;
783 bool is_verified_oop_load = false;
784 bool is_verified_oop_store = false;
785 int tmp_enc = -1;
786 if (VerifyOops && src1_enc != R_SP_enc) {
787 // classify the op, mainly for an assert check
788 int st_op = 0, ld_op = 0;
789 switch (primary) {
790 case Assembler::stb_op3: st_op = Op_StoreB; break;
791 case Assembler::sth_op3: st_op = Op_StoreC; break;
792 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
793 case Assembler::stw_op3: st_op = Op_StoreI; break;
794 case Assembler::std_op3: st_op = Op_StoreL; break;
795 case Assembler::stf_op3: st_op = Op_StoreF; break;
796 case Assembler::stdf_op3: st_op = Op_StoreD; break;
798 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
799 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
800 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
801 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
802 case Assembler::ldx_op3: // may become LoadP or stay LoadI
803 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
804 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
805 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
806 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
807 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
808 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
810 default: ShouldNotReachHere();
811 }
812 if (tertiary == REGP_OP) {
813 if (st_op == Op_StoreI) st_op = Op_StoreP;
814 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
815 else ShouldNotReachHere();
816 if (st_op) {
817 // a store
818 // inputs are (0:control, 1:memory, 2:address, 3:value)
819 Node* n2 = n->in(3);
820 if (n2 != NULL) {
821 const Type* t = n2->bottom_type();
822 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
823 }
824 } else {
825 // a load
826 const Type* t = n->bottom_type();
827 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
828 }
829 }
831 if (ld_op) {
832 // a Load
833 // inputs are (0:control, 1:memory, 2:address)
834 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
835 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
836 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
837 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
838 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
839 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
840 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
843 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
844 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
845 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
846 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
847 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
848 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
849 !(n->rule() == loadUB_rule)) {
850 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
851 }
852 } else if (st_op) {
853 // a Store
854 // inputs are (0:control, 1:memory, 2:address, 3:value)
855 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
856 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
857 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
858 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
859 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
860 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
861 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
862 verify_oops_warning(n, n->ideal_Opcode(), st_op);
863 }
864 }
866 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
867 Node* addr = n->in(2);
868 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
869 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
870 if (atype != NULL) {
871 intptr_t offset = get_offset_from_base(n, atype, disp32);
872 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
873 if (offset != offset_2) {
874 get_offset_from_base(n, atype, disp32);
875 get_offset_from_base_2(n, atype, disp32);
876 }
877 assert(offset == offset_2, "different offsets");
878 if (offset == disp32) {
879 // we now know that src1 is a true oop pointer
880 is_verified_oop_base = true;
881 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
882 if( primary == Assembler::ldd_op3 ) {
883 is_verified_oop_base = false; // Cannot 'ldd' into O7
884 } else {
885 tmp_enc = dst_enc;
886 dst_enc = R_O7_enc; // Load into O7; preserve source oop
887 assert(src1_enc != dst_enc, "");
888 }
889 }
890 }
891 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
892 || offset == oopDesc::mark_offset_in_bytes())) {
893 // loading the mark should not be allowed either, but
894 // we don't check this since it conflicts with InlineObjectHash
895 // usage of LoadINode to get the mark. We could keep the
896 // check if we create a new LoadMarkNode
897 // but do not verify the object before its header is initialized
898 ShouldNotReachHere();
899 }
900 }
901 }
902 }
903 }
904 #endif
906 uint instr;
907 instr = (Assembler::ldst_op << 30)
908 | (dst_enc << 25)
909 | (primary << 19)
910 | (src1_enc << 14);
912 uint index = src2_enc;
913 int disp = disp32;
915 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
916 disp += STACK_BIAS;
917 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
918 if (!Assembler::is_simm13(disp)) {
919 ra->C->record_method_not_compilable("unable to handle large constant offsets");
920 return;
921 }
922 }
924 // We should have a compiler bailout here rather than a guarantee.
925 // Better yet would be some mechanism to handle variable-size matches correctly.
926 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
928 if( disp == 0 ) {
929 // use reg-reg form
930 // bit 13 is already zero
931 instr |= index;
932 } else {
933 // use reg-imm form
934 instr |= 0x00002000; // set bit 13 to one
935 instr |= disp & 0x1FFF;
936 }
938 cbuf.insts()->emit_int32(instr);
940 #ifdef ASSERT
941 {
942 MacroAssembler _masm(&cbuf);
943 if (is_verified_oop_base) {
944 __ verify_oop(reg_to_register_object(src1_enc));
945 }
946 if (is_verified_oop_store) {
947 __ verify_oop(reg_to_register_object(dst_enc));
948 }
949 if (tmp_enc != -1) {
950 __ mov(O7, reg_to_register_object(tmp_enc));
951 }
952 if (is_verified_oop_load) {
953 __ verify_oop(reg_to_register_object(dst_enc));
954 }
955 }
956 #endif
957 }
959 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
960 // The method which records debug information at every safepoint
961 // expects the call to be the first instruction in the snippet as
962 // it creates a PcDesc structure which tracks the offset of a call
963 // from the start of the codeBlob. This offset is computed as
964 // code_end() - code_begin() of the code which has been emitted
965 // so far.
966 // In this particular case we have skirted around the problem by
967 // putting the "mov" instruction in the delay slot but the problem
968 // may bite us again at some other point and a cleaner/generic
969 // solution using relocations would be needed.
970 MacroAssembler _masm(&cbuf);
971 __ set_inst_mark();
973 // We flush the current window just so that there is a valid stack copy
974 // the fact that the current window becomes active again instantly is
975 // not a problem there is nothing live in it.
977 #ifdef ASSERT
978 int startpos = __ offset();
979 #endif /* ASSERT */
981 __ call((address)entry_point, rtype);
983 if (preserve_g2) __ delayed()->mov(G2, L7);
984 else __ delayed()->nop();
986 if (preserve_g2) __ mov(L7, G2);
988 #ifdef ASSERT
989 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
990 #ifdef _LP64
991 // Trash argument dump slots.
992 __ set(0xb0b8ac0db0b8ac0d, G1);
993 __ mov(G1, G5);
994 __ stx(G1, SP, STACK_BIAS + 0x80);
995 __ stx(G1, SP, STACK_BIAS + 0x88);
996 __ stx(G1, SP, STACK_BIAS + 0x90);
997 __ stx(G1, SP, STACK_BIAS + 0x98);
998 __ stx(G1, SP, STACK_BIAS + 0xA0);
999 __ stx(G1, SP, STACK_BIAS + 0xA8);
1000 #else // _LP64
1001 // this is also a native call, so smash the first 7 stack locations,
1002 // and the various registers
1004 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1005 // while [SP+0x44..0x58] are the argument dump slots.
1006 __ set((intptr_t)0xbaadf00d, G1);
1007 __ mov(G1, G5);
1008 __ sllx(G1, 32, G1);
1009 __ or3(G1, G5, G1);
1010 __ mov(G1, G5);
1011 __ stx(G1, SP, 0x40);
1012 __ stx(G1, SP, 0x48);
1013 __ stx(G1, SP, 0x50);
1014 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1015 #endif // _LP64
1016 }
1017 #endif /*ASSERT*/
1018 }
1020 //=============================================================================
1021 // REQUIRED FUNCTIONALITY for encoding
1022 void emit_lo(CodeBuffer &cbuf, int val) { }
1023 void emit_hi(CodeBuffer &cbuf, int val) { }
1026 //=============================================================================
1027 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1029 int Compile::ConstantTable::calculate_table_base_offset() const {
1030 if (UseRDPCForConstantTableBase) {
1031 // The table base offset might be less but then it fits into
1032 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1033 return Assembler::min_simm13();
1034 } else {
1035 int offset = -(size() / 2);
1036 if (!Assembler::is_simm13(offset)) {
1037 offset = Assembler::min_simm13();
1038 }
1039 return offset;
1040 }
1041 }
1043 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1044 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1045 ShouldNotReachHere();
1046 }
1048 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1049 Compile* C = ra_->C;
1050 Compile::ConstantTable& constant_table = C->constant_table();
1051 MacroAssembler _masm(&cbuf);
1053 Register r = as_Register(ra_->get_encode(this));
1054 CodeSection* consts_section = __ code()->consts();
1055 int consts_size = consts_section->align_at_start(consts_section->size());
1056 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1058 if (UseRDPCForConstantTableBase) {
1059 // For the following RDPC logic to work correctly the consts
1060 // section must be allocated right before the insts section. This
1061 // assert checks for that. The layout and the SECT_* constants
1062 // are defined in src/share/vm/asm/codeBuffer.hpp.
1063 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1064 int insts_offset = __ offset();
1066 // Layout:
1067 //
1068 // |----------- consts section ------------|----------- insts section -----------...
1069 // |------ constant table -----|- padding -|------------------x----
1070 // \ current PC (RDPC instruction)
1071 // |<------------- consts_size ----------->|<- insts_offset ->|
1072 // \ table base
1073 // The table base offset is later added to the load displacement
1074 // so it has to be negative.
1075 int table_base_offset = -(consts_size + insts_offset);
1076 int disp;
1078 // If the displacement from the current PC to the constant table
1079 // base fits into simm13 we set the constant table base to the
1080 // current PC.
1081 if (Assembler::is_simm13(table_base_offset)) {
1082 constant_table.set_table_base_offset(table_base_offset);
1083 disp = 0;
1084 } else {
1085 // Otherwise we set the constant table base offset to the
1086 // maximum negative displacement of load instructions to keep
1087 // the disp as small as possible:
1088 //
1089 // |<------------- consts_size ----------->|<- insts_offset ->|
1090 // |<--------- min_simm13 --------->|<-------- disp --------->|
1091 // \ table base
1092 table_base_offset = Assembler::min_simm13();
1093 constant_table.set_table_base_offset(table_base_offset);
1094 disp = (consts_size + insts_offset) + table_base_offset;
1095 }
1097 __ rdpc(r);
1099 if (disp != 0) {
1100 assert(r != O7, "need temporary");
1101 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1102 }
1103 }
1104 else {
1105 // Materialize the constant table base.
1106 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1107 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1108 AddressLiteral base(baseaddr, rspec);
1109 __ set(base, r);
1110 }
1111 }
1113 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1114 if (UseRDPCForConstantTableBase) {
1115 // This is really the worst case but generally it's only 1 instruction.
1116 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1117 } else {
1118 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1119 }
1120 }
1122 #ifndef PRODUCT
1123 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1124 char reg[128];
1125 ra_->dump_register(this, reg);
1126 if (UseRDPCForConstantTableBase) {
1127 st->print("RDPC %s\t! constant table base", reg);
1128 } else {
1129 st->print("SET &constanttable,%s\t! constant table base", reg);
1130 }
1131 }
1132 #endif
1135 //=============================================================================
1137 #ifndef PRODUCT
1138 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1139 Compile* C = ra_->C;
1141 for (int i = 0; i < OptoPrologueNops; i++) {
1142 st->print_cr("NOP"); st->print("\t");
1143 }
1145 if( VerifyThread ) {
1146 st->print_cr("Verify_Thread"); st->print("\t");
1147 }
1149 size_t framesize = C->frame_slots() << LogBytesPerInt;
1151 // Calls to C2R adapters often do not accept exceptional returns.
1152 // We require that their callers must bang for them. But be careful, because
1153 // some VM calls (such as call site linkage) can use several kilobytes of
1154 // stack. But the stack safety zone should account for that.
1155 // See bugs 4446381, 4468289, 4497237.
1156 if (C->need_stack_bang(framesize)) {
1157 st->print_cr("! stack bang"); st->print("\t");
1158 }
1160 if (Assembler::is_simm13(-framesize)) {
1161 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1162 } else {
1163 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1164 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1165 st->print ("SAVE R_SP,R_G3,R_SP");
1166 }
1168 }
1169 #endif
1171 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1172 Compile* C = ra_->C;
1173 MacroAssembler _masm(&cbuf);
1175 for (int i = 0; i < OptoPrologueNops; i++) {
1176 __ nop();
1177 }
1179 __ verify_thread();
1181 size_t framesize = C->frame_slots() << LogBytesPerInt;
1182 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1183 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1185 // Calls to C2R adapters often do not accept exceptional returns.
1186 // We require that their callers must bang for them. But be careful, because
1187 // some VM calls (such as call site linkage) can use several kilobytes of
1188 // stack. But the stack safety zone should account for that.
1189 // See bugs 4446381, 4468289, 4497237.
1190 if (C->need_stack_bang(framesize)) {
1191 __ generate_stack_overflow_check(framesize);
1192 }
1194 if (Assembler::is_simm13(-framesize)) {
1195 __ save(SP, -framesize, SP);
1196 } else {
1197 __ sethi(-framesize & ~0x3ff, G3);
1198 __ add(G3, -framesize & 0x3ff, G3);
1199 __ save(SP, G3, SP);
1200 }
1201 C->set_frame_complete( __ offset() );
1203 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1204 // NOTE: We set the table base offset here because users might be
1205 // emitted before MachConstantBaseNode.
1206 Compile::ConstantTable& constant_table = C->constant_table();
1207 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1208 }
1209 }
1211 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1212 return MachNode::size(ra_);
1213 }
1215 int MachPrologNode::reloc() const {
1216 return 10; // a large enough number
1217 }
1219 //=============================================================================
1220 #ifndef PRODUCT
1221 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1222 Compile* C = ra_->C;
1224 if( do_polling() && ra_->C->is_method_compilation() ) {
1225 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1226 #ifdef _LP64
1227 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1228 #else
1229 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1230 #endif
1231 }
1233 if( do_polling() )
1234 st->print("RET\n\t");
1236 st->print("RESTORE");
1237 }
1238 #endif
1240 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1241 MacroAssembler _masm(&cbuf);
1242 Compile* C = ra_->C;
1244 __ verify_thread();
1246 // If this does safepoint polling, then do it here
1247 if( do_polling() && ra_->C->is_method_compilation() ) {
1248 AddressLiteral polling_page(os::get_polling_page());
1249 __ sethi(polling_page, L0);
1250 __ relocate(relocInfo::poll_return_type);
1251 __ ld_ptr( L0, 0, G0 );
1252 }
1254 // If this is a return, then stuff the restore in the delay slot
1255 if( do_polling() ) {
1256 __ ret();
1257 __ delayed()->restore();
1258 } else {
1259 __ restore();
1260 }
1261 }
1263 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1264 return MachNode::size(ra_);
1265 }
1267 int MachEpilogNode::reloc() const {
1268 return 16; // a large enough number
1269 }
1271 const Pipeline * MachEpilogNode::pipeline() const {
1272 return MachNode::pipeline_class();
1273 }
1275 int MachEpilogNode::safepoint_offset() const {
1276 assert( do_polling(), "no return for this epilog node");
1277 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1278 }
1280 //=============================================================================
1282 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1283 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1284 static enum RC rc_class( OptoReg::Name reg ) {
1285 if( !OptoReg::is_valid(reg) ) return rc_bad;
1286 if (OptoReg::is_stack(reg)) return rc_stack;
1287 VMReg r = OptoReg::as_VMReg(reg);
1288 if (r->is_Register()) return rc_int;
1289 assert(r->is_FloatRegister(), "must be");
1290 return rc_float;
1291 }
1293 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1294 if (cbuf) {
1295 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1296 }
1297 #ifndef PRODUCT
1298 else if (!do_size) {
1299 if (size != 0) st->print("\n\t");
1300 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1301 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1302 }
1303 #endif
1304 return size+4;
1305 }
1307 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1308 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1309 #ifndef PRODUCT
1310 else if( !do_size ) {
1311 if( size != 0 ) st->print("\n\t");
1312 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1313 }
1314 #endif
1315 return size+4;
1316 }
1318 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1319 PhaseRegAlloc *ra_,
1320 bool do_size,
1321 outputStream* st ) const {
1322 // Get registers to move
1323 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1324 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1325 OptoReg::Name dst_second = ra_->get_reg_second(this );
1326 OptoReg::Name dst_first = ra_->get_reg_first(this );
1328 enum RC src_second_rc = rc_class(src_second);
1329 enum RC src_first_rc = rc_class(src_first);
1330 enum RC dst_second_rc = rc_class(dst_second);
1331 enum RC dst_first_rc = rc_class(dst_first);
1333 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1335 // Generate spill code!
1336 int size = 0;
1338 if( src_first == dst_first && src_second == dst_second )
1339 return size; // Self copy, no move
1341 // --------------------------------------
1342 // Check for mem-mem move. Load into unused float registers and fall into
1343 // the float-store case.
1344 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1345 int offset = ra_->reg2offset(src_first);
1346 // Further check for aligned-adjacent pair, so we can use a double load
1347 if( (src_first&1)==0 && src_first+1 == src_second ) {
1348 src_second = OptoReg::Name(R_F31_num);
1349 src_second_rc = rc_float;
1350 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1351 } else {
1352 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1353 }
1354 src_first = OptoReg::Name(R_F30_num);
1355 src_first_rc = rc_float;
1356 }
1358 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1359 int offset = ra_->reg2offset(src_second);
1360 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1361 src_second = OptoReg::Name(R_F31_num);
1362 src_second_rc = rc_float;
1363 }
1365 // --------------------------------------
1366 // Check for float->int copy; requires a trip through memory
1367 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1368 int offset = frame::register_save_words*wordSize;
1369 if (cbuf) {
1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1371 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1372 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1373 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1374 }
1375 #ifndef PRODUCT
1376 else if (!do_size) {
1377 if (size != 0) st->print("\n\t");
1378 st->print( "SUB R_SP,16,R_SP\n");
1379 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1380 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1381 st->print("\tADD R_SP,16,R_SP\n");
1382 }
1383 #endif
1384 size += 16;
1385 }
1387 // Check for float->int copy on T4
1388 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1389 // Further check for aligned-adjacent pair, so we can use a double move
1390 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1391 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1392 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1393 }
1394 // Check for int->float copy on T4
1395 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1396 // Further check for aligned-adjacent pair, so we can use a double move
1397 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1398 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1399 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1400 }
1402 // --------------------------------------
1403 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1404 // In such cases, I have to do the big-endian swap. For aligned targets, the
1405 // hardware does the flop for me. Doubles are always aligned, so no problem
1406 // there. Misaligned sources only come from native-long-returns (handled
1407 // special below).
1408 #ifndef _LP64
1409 if( src_first_rc == rc_int && // source is already big-endian
1410 src_second_rc != rc_bad && // 64-bit move
1411 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1412 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1413 // Do the big-endian flop.
1414 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1415 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1416 }
1417 #endif
1419 // --------------------------------------
1420 // Check for integer reg-reg copy
1421 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1422 #ifndef _LP64
1423 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1424 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1425 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1426 // operand contains the least significant word of the 64-bit value and vice versa.
1427 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1428 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1429 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1430 if( cbuf ) {
1431 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1432 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1433 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1434 #ifndef PRODUCT
1435 } else if( !do_size ) {
1436 if( size != 0 ) st->print("\n\t");
1437 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1438 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1439 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1440 #endif
1441 }
1442 return size+12;
1443 }
1444 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1445 // returning a long value in I0/I1
1446 // a SpillCopy must be able to target a return instruction's reg_class
1447 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1448 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1449 // operand contains the least significant word of the 64-bit value and vice versa.
1450 OptoReg::Name tdest = dst_first;
1452 if (src_first == dst_first) {
1453 tdest = OptoReg::Name(R_O7_num);
1454 size += 4;
1455 }
1457 if( cbuf ) {
1458 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1459 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1460 // ShrL_reg_imm6
1461 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1462 // ShrR_reg_imm6 src, 0, dst
1463 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1464 if (tdest != dst_first) {
1465 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1466 }
1467 }
1468 #ifndef PRODUCT
1469 else if( !do_size ) {
1470 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1471 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1472 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1473 if (tdest != dst_first) {
1474 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1475 }
1476 }
1477 #endif // PRODUCT
1478 return size+8;
1479 }
1480 #endif // !_LP64
1481 // Else normal reg-reg copy
1482 assert( src_second != dst_first, "smashed second before evacuating it" );
1483 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1484 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1485 // This moves an aligned adjacent pair.
1486 // See if we are done.
1487 if( src_first+1 == src_second && dst_first+1 == dst_second )
1488 return size;
1489 }
1491 // Check for integer store
1492 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1493 int offset = ra_->reg2offset(dst_first);
1494 // Further check for aligned-adjacent pair, so we can use a double store
1495 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1496 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1497 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1498 }
1500 // Check for integer load
1501 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1502 int offset = ra_->reg2offset(src_first);
1503 // Further check for aligned-adjacent pair, so we can use a double load
1504 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1505 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1506 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1507 }
1509 // Check for float reg-reg copy
1510 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1511 // Further check for aligned-adjacent pair, so we can use a double move
1512 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1513 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1514 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1515 }
1517 // Check for float store
1518 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1519 int offset = ra_->reg2offset(dst_first);
1520 // Further check for aligned-adjacent pair, so we can use a double store
1521 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1522 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1523 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1524 }
1526 // Check for float load
1527 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1528 int offset = ra_->reg2offset(src_first);
1529 // Further check for aligned-adjacent pair, so we can use a double load
1530 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1531 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1532 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1533 }
1535 // --------------------------------------------------------------------
1536 // Check for hi bits still needing moving. Only happens for misaligned
1537 // arguments to native calls.
1538 if( src_second == dst_second )
1539 return size; // Self copy; no move
1540 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1542 #ifndef _LP64
1543 // In the LP64 build, all registers can be moved as aligned/adjacent
1544 // pairs, so there's never any need to move the high bits separately.
1545 // The 32-bit builds have to deal with the 32-bit ABI which can force
1546 // all sorts of silly alignment problems.
1548 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1549 // 32-bits of a 64-bit register, but are needed in low bits of another
1550 // register (else it's a hi-bits-to-hi-bits copy which should have
1551 // happened already as part of a 64-bit move)
1552 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1553 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1554 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1555 // Shift src_second down to dst_second's low bits.
1556 if( cbuf ) {
1557 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1558 #ifndef PRODUCT
1559 } else if( !do_size ) {
1560 if( size != 0 ) st->print("\n\t");
1561 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1562 #endif
1563 }
1564 return size+4;
1565 }
1567 // Check for high word integer store. Must down-shift the hi bits
1568 // into a temp register, then fall into the case of storing int bits.
1569 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1570 // Shift src_second down to dst_second's low bits.
1571 if( cbuf ) {
1572 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1573 #ifndef PRODUCT
1574 } else if( !do_size ) {
1575 if( size != 0 ) st->print("\n\t");
1576 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1577 #endif
1578 }
1579 size+=4;
1580 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1581 }
1583 // Check for high word integer load
1584 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1585 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1587 // Check for high word integer store
1588 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1589 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1591 // Check for high word float store
1592 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1593 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1595 #endif // !_LP64
1597 Unimplemented();
1598 }
1600 #ifndef PRODUCT
1601 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1602 implementation( NULL, ra_, false, st );
1603 }
1604 #endif
1606 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1607 implementation( &cbuf, ra_, false, NULL );
1608 }
1610 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1611 return implementation( NULL, ra_, true, NULL );
1612 }
1614 //=============================================================================
1615 #ifndef PRODUCT
1616 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1617 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1618 }
1619 #endif
1621 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1622 MacroAssembler _masm(&cbuf);
1623 for(int i = 0; i < _count; i += 1) {
1624 __ nop();
1625 }
1626 }
1628 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1629 return 4 * _count;
1630 }
1633 //=============================================================================
1634 #ifndef PRODUCT
1635 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1636 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1637 int reg = ra_->get_reg_first(this);
1638 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1639 }
1640 #endif
1642 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1643 MacroAssembler _masm(&cbuf);
1644 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1645 int reg = ra_->get_encode(this);
1647 if (Assembler::is_simm13(offset)) {
1648 __ add(SP, offset, reg_to_register_object(reg));
1649 } else {
1650 __ set(offset, O7);
1651 __ add(SP, O7, reg_to_register_object(reg));
1652 }
1653 }
1655 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1656 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1657 assert(ra_ == ra_->C->regalloc(), "sanity");
1658 return ra_->C->scratch_emit_size(this);
1659 }
1661 //=============================================================================
1662 #ifndef PRODUCT
1663 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1664 st->print_cr("\nUEP:");
1665 #ifdef _LP64
1666 if (UseCompressedClassPointers) {
1667 assert(Universe::heap() != NULL, "java heap should be initialized");
1668 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1669 if (Universe::narrow_klass_base() != 0) {
1670 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1671 if (Universe::narrow_klass_shift() != 0) {
1672 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1673 }
1674 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1675 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1676 } else {
1677 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1678 }
1679 } else {
1680 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1681 }
1682 st->print_cr("\tCMP R_G5,R_G3" );
1683 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1684 #else // _LP64
1685 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1686 st->print_cr("\tCMP R_G5,R_G3" );
1687 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1688 #endif // _LP64
1689 }
1690 #endif
1692 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1693 MacroAssembler _masm(&cbuf);
1694 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1695 Register temp_reg = G3;
1696 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1698 // Load klass from receiver
1699 __ load_klass(O0, temp_reg);
1700 // Compare against expected klass
1701 __ cmp(temp_reg, G5_ic_reg);
1702 // Branch to miss code, checks xcc or icc depending
1703 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1704 }
1706 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1707 return MachNode::size(ra_);
1708 }
1711 //=============================================================================
1713 uint size_exception_handler() {
1714 if (TraceJumps) {
1715 return (400); // just a guess
1716 }
1717 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1718 }
1720 uint size_deopt_handler() {
1721 if (TraceJumps) {
1722 return (400); // just a guess
1723 }
1724 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1725 }
1727 // Emit exception handler code.
1728 int emit_exception_handler(CodeBuffer& cbuf) {
1729 Register temp_reg = G3;
1730 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1731 MacroAssembler _masm(&cbuf);
1733 address base =
1734 __ start_a_stub(size_exception_handler());
1735 if (base == NULL) return 0; // CodeBuffer::expand failed
1737 int offset = __ offset();
1739 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1740 __ delayed()->nop();
1742 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1744 __ end_a_stub();
1746 return offset;
1747 }
1749 int emit_deopt_handler(CodeBuffer& cbuf) {
1750 // Can't use any of the current frame's registers as we may have deopted
1751 // at a poll and everything (including G3) can be live.
1752 Register temp_reg = L0;
1753 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1754 MacroAssembler _masm(&cbuf);
1756 address base =
1757 __ start_a_stub(size_deopt_handler());
1758 if (base == NULL) return 0; // CodeBuffer::expand failed
1760 int offset = __ offset();
1761 __ save_frame(0);
1762 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1763 __ delayed()->restore();
1765 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1767 __ end_a_stub();
1768 return offset;
1770 }
1772 // Given a register encoding, produce a Integer Register object
1773 static Register reg_to_register_object(int register_encoding) {
1774 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1775 return as_Register(register_encoding);
1776 }
1778 // Given a register encoding, produce a single-precision Float Register object
1779 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1780 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1781 return as_SingleFloatRegister(register_encoding);
1782 }
1784 // Given a register encoding, produce a double-precision Float Register object
1785 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1786 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1787 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1788 return as_DoubleFloatRegister(register_encoding);
1789 }
1791 const bool Matcher::match_rule_supported(int opcode) {
1792 if (!has_match_rule(opcode))
1793 return false;
1795 switch (opcode) {
1796 case Op_CountLeadingZerosI:
1797 case Op_CountLeadingZerosL:
1798 case Op_CountTrailingZerosI:
1799 case Op_CountTrailingZerosL:
1800 case Op_PopCountI:
1801 case Op_PopCountL:
1802 if (!UsePopCountInstruction)
1803 return false;
1804 case Op_CompareAndSwapL:
1805 #ifdef _LP64
1806 case Op_CompareAndSwapP:
1807 #endif
1808 if (!VM_Version::supports_cx8())
1809 return false;
1810 break;
1811 }
1813 return true; // Per default match rules are supported.
1814 }
1816 int Matcher::regnum_to_fpu_offset(int regnum) {
1817 return regnum - 32; // The FP registers are in the second chunk
1818 }
1820 #ifdef ASSERT
1821 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1822 #endif
1824 // Vector width in bytes
1825 const int Matcher::vector_width_in_bytes(BasicType bt) {
1826 assert(MaxVectorSize == 8, "");
1827 return 8;
1828 }
1830 // Vector ideal reg
1831 const int Matcher::vector_ideal_reg(int size) {
1832 assert(MaxVectorSize == 8, "");
1833 return Op_RegD;
1834 }
1836 const int Matcher::vector_shift_count_ideal_reg(int size) {
1837 fatal("vector shift is not supported");
1838 return Node::NotAMachineReg;
1839 }
1841 // Limits on vector size (number of elements) loaded into vector.
1842 const int Matcher::max_vector_size(const BasicType bt) {
1843 assert(is_java_primitive(bt), "only primitive type vectors");
1844 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1845 }
1847 const int Matcher::min_vector_size(const BasicType bt) {
1848 return max_vector_size(bt); // Same as max.
1849 }
1851 // SPARC doesn't support misaligned vectors store/load.
1852 const bool Matcher::misaligned_vectors_ok() {
1853 return false;
1854 }
1856 // Current (2013) SPARC platforms need to read original key
1857 // to construct decryption expanded key
1858 const bool Matcher::pass_original_key_for_aes() {
1859 return true;
1860 }
1862 // USII supports fxtof through the whole range of number, USIII doesn't
1863 const bool Matcher::convL2FSupported(void) {
1864 return VM_Version::has_fast_fxtof();
1865 }
1867 // Is this branch offset short enough that a short branch can be used?
1868 //
1869 // NOTE: If the platform does not provide any short branch variants, then
1870 // this method should return false for offset 0.
1871 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1872 // The passed offset is relative to address of the branch.
1873 // Don't need to adjust the offset.
1874 return UseCBCond && Assembler::is_simm12(offset);
1875 }
1877 const bool Matcher::isSimpleConstant64(jlong value) {
1878 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1879 // Depends on optimizations in MacroAssembler::setx.
1880 int hi = (int)(value >> 32);
1881 int lo = (int)(value & ~0);
1882 return (hi == 0) || (hi == -1) || (lo == 0);
1883 }
1885 // No scaling for the parameter the ClearArray node.
1886 const bool Matcher::init_array_count_is_in_bytes = true;
1888 // Threshold size for cleararray.
1889 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1891 // No additional cost for CMOVL.
1892 const int Matcher::long_cmove_cost() { return 0; }
1894 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1895 const int Matcher::float_cmove_cost() {
1896 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1897 }
1899 // Does the CPU require late expand (see block.cpp for description of late expand)?
1900 const bool Matcher::require_postalloc_expand = false;
1902 // Should the Matcher clone shifts on addressing modes, expecting them to
1903 // be subsumed into complex addressing expressions or compute them into
1904 // registers? True for Intel but false for most RISCs
1905 const bool Matcher::clone_shift_expressions = false;
1907 // Do we need to mask the count passed to shift instructions or does
1908 // the cpu only look at the lower 5/6 bits anyway?
1909 const bool Matcher::need_masked_shift_count = false;
1911 bool Matcher::narrow_oop_use_complex_address() {
1912 NOT_LP64(ShouldNotCallThis());
1913 assert(UseCompressedOops, "only for compressed oops code");
1914 return false;
1915 }
1917 bool Matcher::narrow_klass_use_complex_address() {
1918 NOT_LP64(ShouldNotCallThis());
1919 assert(UseCompressedClassPointers, "only for compressed klass code");
1920 return false;
1921 }
1923 // Is it better to copy float constants, or load them directly from memory?
1924 // Intel can load a float constant from a direct address, requiring no
1925 // extra registers. Most RISCs will have to materialize an address into a
1926 // register first, so they would do better to copy the constant from stack.
1927 const bool Matcher::rematerialize_float_constants = false;
1929 // If CPU can load and store mis-aligned doubles directly then no fixup is
1930 // needed. Else we split the double into 2 integer pieces and move it
1931 // piece-by-piece. Only happens when passing doubles into C code as the
1932 // Java calling convention forces doubles to be aligned.
1933 #ifdef _LP64
1934 const bool Matcher::misaligned_doubles_ok = true;
1935 #else
1936 const bool Matcher::misaligned_doubles_ok = false;
1937 #endif
1939 // No-op on SPARC.
1940 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1941 }
1943 // Advertise here if the CPU requires explicit rounding operations
1944 // to implement the UseStrictFP mode.
1945 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1947 // Are floats conerted to double when stored to stack during deoptimization?
1948 // Sparc does not handle callee-save floats.
1949 bool Matcher::float_in_double() { return false; }
1951 // Do ints take an entire long register or just half?
1952 // Note that we if-def off of _LP64.
1953 // The relevant question is how the int is callee-saved. In _LP64
1954 // the whole long is written but de-opt'ing will have to extract
1955 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1956 #ifdef _LP64
1957 const bool Matcher::int_in_long = true;
1958 #else
1959 const bool Matcher::int_in_long = false;
1960 #endif
1962 // Return whether or not this register is ever used as an argument. This
1963 // function is used on startup to build the trampoline stubs in generateOptoStub.
1964 // Registers not mentioned will be killed by the VM call in the trampoline, and
1965 // arguments in those registers not be available to the callee.
1966 bool Matcher::can_be_java_arg( int reg ) {
1967 // Standard sparc 6 args in registers
1968 if( reg == R_I0_num ||
1969 reg == R_I1_num ||
1970 reg == R_I2_num ||
1971 reg == R_I3_num ||
1972 reg == R_I4_num ||
1973 reg == R_I5_num ) return true;
1974 #ifdef _LP64
1975 // 64-bit builds can pass 64-bit pointers and longs in
1976 // the high I registers
1977 if( reg == R_I0H_num ||
1978 reg == R_I1H_num ||
1979 reg == R_I2H_num ||
1980 reg == R_I3H_num ||
1981 reg == R_I4H_num ||
1982 reg == R_I5H_num ) return true;
1984 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1985 return true;
1986 }
1988 #else
1989 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1990 // Longs cannot be passed in O regs, because O regs become I regs
1991 // after a 'save' and I regs get their high bits chopped off on
1992 // interrupt.
1993 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1994 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1995 #endif
1996 // A few float args in registers
1997 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1999 return false;
2000 }
2002 bool Matcher::is_spillable_arg( int reg ) {
2003 return can_be_java_arg(reg);
2004 }
2006 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2007 // Use hardware SDIVX instruction when it is
2008 // faster than a code which use multiply.
2009 return VM_Version::has_fast_idiv();
2010 }
2012 // Register for DIVI projection of divmodI
2013 RegMask Matcher::divI_proj_mask() {
2014 ShouldNotReachHere();
2015 return RegMask();
2016 }
2018 // Register for MODI projection of divmodI
2019 RegMask Matcher::modI_proj_mask() {
2020 ShouldNotReachHere();
2021 return RegMask();
2022 }
2024 // Register for DIVL projection of divmodL
2025 RegMask Matcher::divL_proj_mask() {
2026 ShouldNotReachHere();
2027 return RegMask();
2028 }
2030 // Register for MODL projection of divmodL
2031 RegMask Matcher::modL_proj_mask() {
2032 ShouldNotReachHere();
2033 return RegMask();
2034 }
2036 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2037 return L7_REGP_mask();
2038 }
2040 const RegMask Matcher::mathExactI_result_proj_mask() {
2041 return G1_REGI_mask();
2042 }
2044 const RegMask Matcher::mathExactL_result_proj_mask() {
2045 return G1_REGL_mask();
2046 }
2048 const RegMask Matcher::mathExactI_flags_proj_mask() {
2049 return INT_FLAGS_mask();
2050 }
2053 %}
2056 // The intptr_t operand types, defined by textual substitution.
2057 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2058 #ifdef _LP64
2059 #define immX immL
2060 #define immX13 immL13
2061 #define immX13m7 immL13m7
2062 #define iRegX iRegL
2063 #define g1RegX g1RegL
2064 #else
2065 #define immX immI
2066 #define immX13 immI13
2067 #define immX13m7 immI13m7
2068 #define iRegX iRegI
2069 #define g1RegX g1RegI
2070 #endif
2072 //----------ENCODING BLOCK-----------------------------------------------------
2073 // This block specifies the encoding classes used by the compiler to output
2074 // byte streams. Encoding classes are parameterized macros used by
2075 // Machine Instruction Nodes in order to generate the bit encoding of the
2076 // instruction. Operands specify their base encoding interface with the
2077 // interface keyword. There are currently supported four interfaces,
2078 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2079 // operand to generate a function which returns its register number when
2080 // queried. CONST_INTER causes an operand to generate a function which
2081 // returns the value of the constant when queried. MEMORY_INTER causes an
2082 // operand to generate four functions which return the Base Register, the
2083 // Index Register, the Scale Value, and the Offset Value of the operand when
2084 // queried. COND_INTER causes an operand to generate six functions which
2085 // return the encoding code (ie - encoding bits for the instruction)
2086 // associated with each basic boolean condition for a conditional instruction.
2087 //
2088 // Instructions specify two basic values for encoding. Again, a function
2089 // is available to check if the constant displacement is an oop. They use the
2090 // ins_encode keyword to specify their encoding classes (which must be
2091 // a sequence of enc_class names, and their parameters, specified in
2092 // the encoding block), and they use the
2093 // opcode keyword to specify, in order, their primary, secondary, and
2094 // tertiary opcode. Only the opcode sections which a particular instruction
2095 // needs for encoding need to be specified.
2096 encode %{
2097 enc_class enc_untested %{
2098 #ifdef ASSERT
2099 MacroAssembler _masm(&cbuf);
2100 __ untested("encoding");
2101 #endif
2102 %}
2104 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2105 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2106 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2107 %}
2109 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2110 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2111 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2112 %}
2114 enc_class form3_mem_prefetch_read( memory mem ) %{
2115 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2116 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2117 %}
2119 enc_class form3_mem_prefetch_write( memory mem ) %{
2120 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2121 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2122 %}
2124 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2125 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2126 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2127 guarantee($mem$$index == R_G0_enc, "double index?");
2128 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2129 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2130 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2131 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2132 %}
2134 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2135 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2136 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2137 guarantee($mem$$index == R_G0_enc, "double index?");
2138 // Load long with 2 instructions
2139 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2140 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2141 %}
2143 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2144 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2145 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2146 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2147 %}
2149 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2150 // Encode a reg-reg copy. If it is useless, then empty encoding.
2151 if( $rs2$$reg != $rd$$reg )
2152 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2153 %}
2155 // Target lo half of long
2156 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2157 // Encode a reg-reg copy. If it is useless, then empty encoding.
2158 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2159 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2160 %}
2162 // Source lo half of long
2163 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2164 // Encode a reg-reg copy. If it is useless, then empty encoding.
2165 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2166 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2167 %}
2169 // Target hi half of long
2170 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2171 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2172 %}
2174 // Source lo half of long, and leave it sign extended.
2175 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2176 // Sign extend low half
2177 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2178 %}
2180 // Source hi half of long, and leave it sign extended.
2181 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2182 // Shift high half to low half
2183 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2184 %}
2186 // Source hi half of long
2187 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2188 // Encode a reg-reg copy. If it is useless, then empty encoding.
2189 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2190 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2191 %}
2193 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2194 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2195 %}
2197 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2198 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2199 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2200 %}
2202 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2203 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2204 // clear if nothing else is happening
2205 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2206 // blt,a,pn done
2207 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2208 // mov dst,-1 in delay slot
2209 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2210 %}
2212 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2213 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2214 %}
2216 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2217 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2218 %}
2220 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2221 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2222 %}
2224 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2225 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2226 %}
2228 enc_class move_return_pc_to_o1() %{
2229 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2230 %}
2232 #ifdef _LP64
2233 /* %%% merge with enc_to_bool */
2234 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2235 MacroAssembler _masm(&cbuf);
2237 Register src_reg = reg_to_register_object($src$$reg);
2238 Register dst_reg = reg_to_register_object($dst$$reg);
2239 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2240 %}
2241 #endif
2243 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2244 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2245 MacroAssembler _masm(&cbuf);
2247 Register p_reg = reg_to_register_object($p$$reg);
2248 Register q_reg = reg_to_register_object($q$$reg);
2249 Register y_reg = reg_to_register_object($y$$reg);
2250 Register tmp_reg = reg_to_register_object($tmp$$reg);
2252 __ subcc( p_reg, q_reg, p_reg );
2253 __ add ( p_reg, y_reg, tmp_reg );
2254 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2255 %}
2257 enc_class form_d2i_helper(regD src, regF dst) %{
2258 // fcmp %fcc0,$src,$src
2259 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2260 // branch %fcc0 not-nan, predict taken
2261 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2262 // fdtoi $src,$dst
2263 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2264 // fitos $dst,$dst (if nan)
2265 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2266 // clear $dst (if nan)
2267 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2268 // carry on here...
2269 %}
2271 enc_class form_d2l_helper(regD src, regD dst) %{
2272 // fcmp %fcc0,$src,$src check for NAN
2273 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2274 // branch %fcc0 not-nan, predict taken
2275 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2276 // fdtox $src,$dst convert in delay slot
2277 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2278 // fxtod $dst,$dst (if nan)
2279 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2280 // clear $dst (if nan)
2281 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2282 // carry on here...
2283 %}
2285 enc_class form_f2i_helper(regF src, regF dst) %{
2286 // fcmps %fcc0,$src,$src
2287 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2288 // branch %fcc0 not-nan, predict taken
2289 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2290 // fstoi $src,$dst
2291 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2292 // fitos $dst,$dst (if nan)
2293 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2294 // clear $dst (if nan)
2295 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2296 // carry on here...
2297 %}
2299 enc_class form_f2l_helper(regF src, regD dst) %{
2300 // fcmps %fcc0,$src,$src
2301 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2302 // branch %fcc0 not-nan, predict taken
2303 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2304 // fstox $src,$dst
2305 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2306 // fxtod $dst,$dst (if nan)
2307 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2308 // clear $dst (if nan)
2309 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2310 // carry on here...
2311 %}
2313 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2314 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2315 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2316 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2318 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2320 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2321 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2323 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2324 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2325 %}
2327 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2328 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2329 %}
2331 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2332 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2333 %}
2335 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2336 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2337 %}
2339 enc_class form3_convI2F(regF rs2, regF rd) %{
2340 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2341 %}
2343 // Encloding class for traceable jumps
2344 enc_class form_jmpl(g3RegP dest) %{
2345 emit_jmpl(cbuf, $dest$$reg);
2346 %}
2348 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2349 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2350 %}
2352 enc_class form2_nop() %{
2353 emit_nop(cbuf);
2354 %}
2356 enc_class form2_illtrap() %{
2357 emit_illtrap(cbuf);
2358 %}
2361 // Compare longs and convert into -1, 0, 1.
2362 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2363 // CMP $src1,$src2
2364 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2365 // blt,a,pn done
2366 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2367 // mov dst,-1 in delay slot
2368 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2369 // bgt,a,pn done
2370 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2371 // mov dst,1 in delay slot
2372 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2373 // CLR $dst
2374 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2375 %}
2377 enc_class enc_PartialSubtypeCheck() %{
2378 MacroAssembler _masm(&cbuf);
2379 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2380 __ delayed()->nop();
2381 %}
2383 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2384 MacroAssembler _masm(&cbuf);
2385 Label* L = $labl$$label;
2386 Assembler::Predict predict_taken =
2387 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2389 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2390 __ delayed()->nop();
2391 %}
2393 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2394 MacroAssembler _masm(&cbuf);
2395 Label* L = $labl$$label;
2396 Assembler::Predict predict_taken =
2397 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2399 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2400 __ delayed()->nop();
2401 %}
2403 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2404 int op = (Assembler::arith_op << 30) |
2405 ($dst$$reg << 25) |
2406 (Assembler::movcc_op3 << 19) |
2407 (1 << 18) | // cc2 bit for 'icc'
2408 ($cmp$$cmpcode << 14) |
2409 (0 << 13) | // select register move
2410 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2411 ($src$$reg << 0);
2412 cbuf.insts()->emit_int32(op);
2413 %}
2415 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2416 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2417 int op = (Assembler::arith_op << 30) |
2418 ($dst$$reg << 25) |
2419 (Assembler::movcc_op3 << 19) |
2420 (1 << 18) | // cc2 bit for 'icc'
2421 ($cmp$$cmpcode << 14) |
2422 (1 << 13) | // select immediate move
2423 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2424 (simm11 << 0);
2425 cbuf.insts()->emit_int32(op);
2426 %}
2428 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2429 int op = (Assembler::arith_op << 30) |
2430 ($dst$$reg << 25) |
2431 (Assembler::movcc_op3 << 19) |
2432 (0 << 18) | // cc2 bit for 'fccX'
2433 ($cmp$$cmpcode << 14) |
2434 (0 << 13) | // select register move
2435 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2436 ($src$$reg << 0);
2437 cbuf.insts()->emit_int32(op);
2438 %}
2440 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2441 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2442 int op = (Assembler::arith_op << 30) |
2443 ($dst$$reg << 25) |
2444 (Assembler::movcc_op3 << 19) |
2445 (0 << 18) | // cc2 bit for 'fccX'
2446 ($cmp$$cmpcode << 14) |
2447 (1 << 13) | // select immediate move
2448 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2449 (simm11 << 0);
2450 cbuf.insts()->emit_int32(op);
2451 %}
2453 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2454 int op = (Assembler::arith_op << 30) |
2455 ($dst$$reg << 25) |
2456 (Assembler::fpop2_op3 << 19) |
2457 (0 << 18) |
2458 ($cmp$$cmpcode << 14) |
2459 (1 << 13) | // select register move
2460 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2461 ($primary << 5) | // select single, double or quad
2462 ($src$$reg << 0);
2463 cbuf.insts()->emit_int32(op);
2464 %}
2466 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2467 int op = (Assembler::arith_op << 30) |
2468 ($dst$$reg << 25) |
2469 (Assembler::fpop2_op3 << 19) |
2470 (0 << 18) |
2471 ($cmp$$cmpcode << 14) |
2472 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2473 ($primary << 5) | // select single, double or quad
2474 ($src$$reg << 0);
2475 cbuf.insts()->emit_int32(op);
2476 %}
2478 // Used by the MIN/MAX encodings. Same as a CMOV, but
2479 // the condition comes from opcode-field instead of an argument.
2480 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2481 int op = (Assembler::arith_op << 30) |
2482 ($dst$$reg << 25) |
2483 (Assembler::movcc_op3 << 19) |
2484 (1 << 18) | // cc2 bit for 'icc'
2485 ($primary << 14) |
2486 (0 << 13) | // select register move
2487 (0 << 11) | // cc1, cc0 bits for 'icc'
2488 ($src$$reg << 0);
2489 cbuf.insts()->emit_int32(op);
2490 %}
2492 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2493 int op = (Assembler::arith_op << 30) |
2494 ($dst$$reg << 25) |
2495 (Assembler::movcc_op3 << 19) |
2496 (6 << 16) | // cc2 bit for 'xcc'
2497 ($primary << 14) |
2498 (0 << 13) | // select register move
2499 (0 << 11) | // cc1, cc0 bits for 'icc'
2500 ($src$$reg << 0);
2501 cbuf.insts()->emit_int32(op);
2502 %}
2504 enc_class Set13( immI13 src, iRegI rd ) %{
2505 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2506 %}
2508 enc_class SetHi22( immI src, iRegI rd ) %{
2509 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2510 %}
2512 enc_class Set32( immI src, iRegI rd ) %{
2513 MacroAssembler _masm(&cbuf);
2514 __ set($src$$constant, reg_to_register_object($rd$$reg));
2515 %}
2517 enc_class call_epilog %{
2518 if( VerifyStackAtCalls ) {
2519 MacroAssembler _masm(&cbuf);
2520 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2521 Register temp_reg = G3;
2522 __ add(SP, framesize, temp_reg);
2523 __ cmp(temp_reg, FP);
2524 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2525 }
2526 %}
2528 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2529 // to G1 so the register allocator will not have to deal with the misaligned register
2530 // pair.
2531 enc_class adjust_long_from_native_call %{
2532 #ifndef _LP64
2533 if (returns_long()) {
2534 // sllx O0,32,O0
2535 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2536 // srl O1,0,O1
2537 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2538 // or O0,O1,G1
2539 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2540 }
2541 #endif
2542 %}
2544 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2545 // CALL directly to the runtime
2546 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2547 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2548 /*preserve_g2=*/true);
2549 %}
2551 enc_class preserve_SP %{
2552 MacroAssembler _masm(&cbuf);
2553 __ mov(SP, L7_mh_SP_save);
2554 %}
2556 enc_class restore_SP %{
2557 MacroAssembler _masm(&cbuf);
2558 __ mov(L7_mh_SP_save, SP);
2559 %}
2561 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2562 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2563 // who we intended to call.
2564 if (!_method) {
2565 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2566 } else if (_optimized_virtual) {
2567 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2568 } else {
2569 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2570 }
2571 if (_method) { // Emit stub for static call.
2572 CompiledStaticCall::emit_to_interp_stub(cbuf);
2573 }
2574 %}
2576 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2577 MacroAssembler _masm(&cbuf);
2578 __ set_inst_mark();
2579 int vtable_index = this->_vtable_index;
2580 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2581 if (vtable_index < 0) {
2582 // must be invalid_vtable_index, not nonvirtual_vtable_index
2583 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2584 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2585 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2586 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2587 __ ic_call((address)$meth$$method);
2588 } else {
2589 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2590 // Just go thru the vtable
2591 // get receiver klass (receiver already checked for non-null)
2592 // If we end up going thru a c2i adapter interpreter expects method in G5
2593 int off = __ offset();
2594 __ load_klass(O0, G3_scratch);
2595 int klass_load_size;
2596 if (UseCompressedClassPointers) {
2597 assert(Universe::heap() != NULL, "java heap should be initialized");
2598 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2599 } else {
2600 klass_load_size = 1*BytesPerInstWord;
2601 }
2602 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2603 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2604 if (Assembler::is_simm13(v_off)) {
2605 __ ld_ptr(G3, v_off, G5_method);
2606 } else {
2607 // Generate 2 instructions
2608 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2609 __ or3(G5_method, v_off & 0x3ff, G5_method);
2610 // ld_ptr, set_hi, set
2611 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2612 "Unexpected instruction size(s)");
2613 __ ld_ptr(G3, G5_method, G5_method);
2614 }
2615 // NOTE: for vtable dispatches, the vtable entry will never be null.
2616 // However it may very well end up in handle_wrong_method if the
2617 // method is abstract for the particular class.
2618 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2619 // jump to target (either compiled code or c2iadapter)
2620 __ jmpl(G3_scratch, G0, O7);
2621 __ delayed()->nop();
2622 }
2623 %}
2625 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2626 MacroAssembler _masm(&cbuf);
2628 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2629 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2630 // we might be calling a C2I adapter which needs it.
2632 assert(temp_reg != G5_ic_reg, "conflicting registers");
2633 // Load nmethod
2634 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2636 // CALL to compiled java, indirect the contents of G3
2637 __ set_inst_mark();
2638 __ callr(temp_reg, G0);
2639 __ delayed()->nop();
2640 %}
2642 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2643 MacroAssembler _masm(&cbuf);
2644 Register Rdividend = reg_to_register_object($src1$$reg);
2645 Register Rdivisor = reg_to_register_object($src2$$reg);
2646 Register Rresult = reg_to_register_object($dst$$reg);
2648 __ sra(Rdivisor, 0, Rdivisor);
2649 __ sra(Rdividend, 0, Rdividend);
2650 __ sdivx(Rdividend, Rdivisor, Rresult);
2651 %}
2653 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2654 MacroAssembler _masm(&cbuf);
2656 Register Rdividend = reg_to_register_object($src1$$reg);
2657 int divisor = $imm$$constant;
2658 Register Rresult = reg_to_register_object($dst$$reg);
2660 __ sra(Rdividend, 0, Rdividend);
2661 __ sdivx(Rdividend, divisor, Rresult);
2662 %}
2664 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2665 MacroAssembler _masm(&cbuf);
2666 Register Rsrc1 = reg_to_register_object($src1$$reg);
2667 Register Rsrc2 = reg_to_register_object($src2$$reg);
2668 Register Rdst = reg_to_register_object($dst$$reg);
2670 __ sra( Rsrc1, 0, Rsrc1 );
2671 __ sra( Rsrc2, 0, Rsrc2 );
2672 __ mulx( Rsrc1, Rsrc2, Rdst );
2673 __ srlx( Rdst, 32, Rdst );
2674 %}
2676 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2677 MacroAssembler _masm(&cbuf);
2678 Register Rdividend = reg_to_register_object($src1$$reg);
2679 Register Rdivisor = reg_to_register_object($src2$$reg);
2680 Register Rresult = reg_to_register_object($dst$$reg);
2681 Register Rscratch = reg_to_register_object($scratch$$reg);
2683 assert(Rdividend != Rscratch, "");
2684 assert(Rdivisor != Rscratch, "");
2686 __ sra(Rdividend, 0, Rdividend);
2687 __ sra(Rdivisor, 0, Rdivisor);
2688 __ sdivx(Rdividend, Rdivisor, Rscratch);
2689 __ mulx(Rscratch, Rdivisor, Rscratch);
2690 __ sub(Rdividend, Rscratch, Rresult);
2691 %}
2693 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2694 MacroAssembler _masm(&cbuf);
2696 Register Rdividend = reg_to_register_object($src1$$reg);
2697 int divisor = $imm$$constant;
2698 Register Rresult = reg_to_register_object($dst$$reg);
2699 Register Rscratch = reg_to_register_object($scratch$$reg);
2701 assert(Rdividend != Rscratch, "");
2703 __ sra(Rdividend, 0, Rdividend);
2704 __ sdivx(Rdividend, divisor, Rscratch);
2705 __ mulx(Rscratch, divisor, Rscratch);
2706 __ sub(Rdividend, Rscratch, Rresult);
2707 %}
2709 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2710 MacroAssembler _masm(&cbuf);
2712 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2713 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2715 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2716 %}
2718 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2719 MacroAssembler _masm(&cbuf);
2721 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2722 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2724 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2725 %}
2727 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2728 MacroAssembler _masm(&cbuf);
2730 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2731 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2733 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2734 %}
2736 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2737 MacroAssembler _masm(&cbuf);
2739 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2740 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2742 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2743 %}
2745 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2746 MacroAssembler _masm(&cbuf);
2748 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2749 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2751 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2752 %}
2754 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2755 MacroAssembler _masm(&cbuf);
2757 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2758 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2760 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2761 %}
2763 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2764 MacroAssembler _masm(&cbuf);
2766 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2767 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2769 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2770 %}
2772 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2773 MacroAssembler _masm(&cbuf);
2775 Register Roop = reg_to_register_object($oop$$reg);
2776 Register Rbox = reg_to_register_object($box$$reg);
2777 Register Rscratch = reg_to_register_object($scratch$$reg);
2778 Register Rmark = reg_to_register_object($scratch2$$reg);
2780 assert(Roop != Rscratch, "");
2781 assert(Roop != Rmark, "");
2782 assert(Rbox != Rscratch, "");
2783 assert(Rbox != Rmark, "");
2785 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2786 %}
2788 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2789 MacroAssembler _masm(&cbuf);
2791 Register Roop = reg_to_register_object($oop$$reg);
2792 Register Rbox = reg_to_register_object($box$$reg);
2793 Register Rscratch = reg_to_register_object($scratch$$reg);
2794 Register Rmark = reg_to_register_object($scratch2$$reg);
2796 assert(Roop != Rscratch, "");
2797 assert(Roop != Rmark, "");
2798 assert(Rbox != Rscratch, "");
2799 assert(Rbox != Rmark, "");
2801 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2802 %}
2804 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2805 MacroAssembler _masm(&cbuf);
2806 Register Rmem = reg_to_register_object($mem$$reg);
2807 Register Rold = reg_to_register_object($old$$reg);
2808 Register Rnew = reg_to_register_object($new$$reg);
2810 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2811 __ cmp( Rold, Rnew );
2812 %}
2814 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2815 Register Rmem = reg_to_register_object($mem$$reg);
2816 Register Rold = reg_to_register_object($old$$reg);
2817 Register Rnew = reg_to_register_object($new$$reg);
2819 MacroAssembler _masm(&cbuf);
2820 __ mov(Rnew, O7);
2821 __ casx(Rmem, Rold, O7);
2822 __ cmp( Rold, O7 );
2823 %}
2825 // raw int cas, used for compareAndSwap
2826 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2827 Register Rmem = reg_to_register_object($mem$$reg);
2828 Register Rold = reg_to_register_object($old$$reg);
2829 Register Rnew = reg_to_register_object($new$$reg);
2831 MacroAssembler _masm(&cbuf);
2832 __ mov(Rnew, O7);
2833 __ cas(Rmem, Rold, O7);
2834 __ cmp( Rold, O7 );
2835 %}
2837 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2838 Register Rres = reg_to_register_object($res$$reg);
2840 MacroAssembler _masm(&cbuf);
2841 __ mov(1, Rres);
2842 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2843 %}
2845 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2846 Register Rres = reg_to_register_object($res$$reg);
2848 MacroAssembler _masm(&cbuf);
2849 __ mov(1, Rres);
2850 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2851 %}
2853 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2854 MacroAssembler _masm(&cbuf);
2855 Register Rdst = reg_to_register_object($dst$$reg);
2856 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2857 : reg_to_DoubleFloatRegister_object($src1$$reg);
2858 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2859 : reg_to_DoubleFloatRegister_object($src2$$reg);
2861 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2862 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2863 %}
2866 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2867 Label Ldone, Lloop;
2868 MacroAssembler _masm(&cbuf);
2870 Register str1_reg = reg_to_register_object($str1$$reg);
2871 Register str2_reg = reg_to_register_object($str2$$reg);
2872 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2873 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2874 Register result_reg = reg_to_register_object($result$$reg);
2876 assert(result_reg != str1_reg &&
2877 result_reg != str2_reg &&
2878 result_reg != cnt1_reg &&
2879 result_reg != cnt2_reg ,
2880 "need different registers");
2882 // Compute the minimum of the string lengths(str1_reg) and the
2883 // difference of the string lengths (stack)
2885 // See if the lengths are different, and calculate min in str1_reg.
2886 // Stash diff in O7 in case we need it for a tie-breaker.
2887 Label Lskip;
2888 __ subcc(cnt1_reg, cnt2_reg, O7);
2889 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2890 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2891 // cnt2 is shorter, so use its count:
2892 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2893 __ bind(Lskip);
2895 // reallocate cnt1_reg, cnt2_reg, result_reg
2896 // Note: limit_reg holds the string length pre-scaled by 2
2897 Register limit_reg = cnt1_reg;
2898 Register chr2_reg = cnt2_reg;
2899 Register chr1_reg = result_reg;
2900 // str{12} are the base pointers
2902 // Is the minimum length zero?
2903 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2904 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2905 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2907 // Load first characters
2908 __ lduh(str1_reg, 0, chr1_reg);
2909 __ lduh(str2_reg, 0, chr2_reg);
2911 // Compare first characters
2912 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2913 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2914 assert(chr1_reg == result_reg, "result must be pre-placed");
2915 __ delayed()->nop();
2917 {
2918 // Check after comparing first character to see if strings are equivalent
2919 Label LSkip2;
2920 // Check if the strings start at same location
2921 __ cmp(str1_reg, str2_reg);
2922 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2923 __ delayed()->nop();
2925 // Check if the length difference is zero (in O7)
2926 __ cmp(G0, O7);
2927 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2928 __ delayed()->mov(G0, result_reg); // result is zero
2930 // Strings might not be equal
2931 __ bind(LSkip2);
2932 }
2934 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2935 __ signx(limit_reg);
2937 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2938 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2939 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2941 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2942 __ add(str1_reg, limit_reg, str1_reg);
2943 __ add(str2_reg, limit_reg, str2_reg);
2944 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2946 // Compare the rest of the characters
2947 __ lduh(str1_reg, limit_reg, chr1_reg);
2948 __ bind(Lloop);
2949 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2950 __ lduh(str2_reg, limit_reg, chr2_reg);
2951 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2952 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2953 assert(chr1_reg == result_reg, "result must be pre-placed");
2954 __ delayed()->inccc(limit_reg, sizeof(jchar));
2955 // annul LDUH if branch is not taken to prevent access past end of string
2956 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2957 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2959 // If strings are equal up to min length, return the length difference.
2960 __ mov(O7, result_reg);
2962 // Otherwise, return the difference between the first mismatched chars.
2963 __ bind(Ldone);
2964 %}
2966 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2967 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2968 MacroAssembler _masm(&cbuf);
2970 Register str1_reg = reg_to_register_object($str1$$reg);
2971 Register str2_reg = reg_to_register_object($str2$$reg);
2972 Register cnt_reg = reg_to_register_object($cnt$$reg);
2973 Register tmp1_reg = O7;
2974 Register result_reg = reg_to_register_object($result$$reg);
2976 assert(result_reg != str1_reg &&
2977 result_reg != str2_reg &&
2978 result_reg != cnt_reg &&
2979 result_reg != tmp1_reg ,
2980 "need different registers");
2982 __ cmp(str1_reg, str2_reg); //same char[] ?
2983 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2984 __ delayed()->add(G0, 1, result_reg);
2986 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2987 __ delayed()->add(G0, 1, result_reg); // count == 0
2989 //rename registers
2990 Register limit_reg = cnt_reg;
2991 Register chr1_reg = result_reg;
2992 Register chr2_reg = tmp1_reg;
2994 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2995 __ signx(limit_reg);
2997 //check for alignment and position the pointers to the ends
2998 __ or3(str1_reg, str2_reg, chr1_reg);
2999 __ andcc(chr1_reg, 0x3, chr1_reg);
3000 // notZero means at least one not 4-byte aligned.
3001 // We could optimize the case when both arrays are not aligned
3002 // but it is not frequent case and it requires additional checks.
3003 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3004 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3006 // Compare char[] arrays aligned to 4 bytes.
3007 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3008 chr1_reg, chr2_reg, Ldone);
3009 __ ba(Ldone);
3010 __ delayed()->add(G0, 1, result_reg);
3012 // char by char compare
3013 __ bind(Lchar);
3014 __ add(str1_reg, limit_reg, str1_reg);
3015 __ add(str2_reg, limit_reg, str2_reg);
3016 __ neg(limit_reg); //negate count
3018 __ lduh(str1_reg, limit_reg, chr1_reg);
3019 // Lchar_loop
3020 __ bind(Lchar_loop);
3021 __ lduh(str2_reg, limit_reg, chr2_reg);
3022 __ cmp(chr1_reg, chr2_reg);
3023 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3024 __ delayed()->mov(G0, result_reg); //not equal
3025 __ inccc(limit_reg, sizeof(jchar));
3026 // annul LDUH if branch is not taken to prevent access past end of string
3027 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3028 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3030 __ add(G0, 1, result_reg); //equal
3032 __ bind(Ldone);
3033 %}
3035 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3036 Label Lvector, Ldone, Lloop;
3037 MacroAssembler _masm(&cbuf);
3039 Register ary1_reg = reg_to_register_object($ary1$$reg);
3040 Register ary2_reg = reg_to_register_object($ary2$$reg);
3041 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3042 Register tmp2_reg = O7;
3043 Register result_reg = reg_to_register_object($result$$reg);
3045 int length_offset = arrayOopDesc::length_offset_in_bytes();
3046 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3048 // return true if the same array
3049 __ cmp(ary1_reg, ary2_reg);
3050 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3051 __ delayed()->add(G0, 1, result_reg); // equal
3053 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3054 __ delayed()->mov(G0, result_reg); // not equal
3056 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3057 __ delayed()->mov(G0, result_reg); // not equal
3059 //load the lengths of arrays
3060 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3061 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3063 // return false if the two arrays are not equal length
3064 __ cmp(tmp1_reg, tmp2_reg);
3065 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3066 __ delayed()->mov(G0, result_reg); // not equal
3068 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3069 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3071 // load array addresses
3072 __ add(ary1_reg, base_offset, ary1_reg);
3073 __ add(ary2_reg, base_offset, ary2_reg);
3075 // renaming registers
3076 Register chr1_reg = result_reg; // for characters in ary1
3077 Register chr2_reg = tmp2_reg; // for characters in ary2
3078 Register limit_reg = tmp1_reg; // length
3080 // set byte count
3081 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3083 // Compare char[] arrays aligned to 4 bytes.
3084 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3085 chr1_reg, chr2_reg, Ldone);
3086 __ add(G0, 1, result_reg); // equals
3088 __ bind(Ldone);
3089 %}
3091 enc_class enc_rethrow() %{
3092 cbuf.set_insts_mark();
3093 Register temp_reg = G3;
3094 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3095 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3096 MacroAssembler _masm(&cbuf);
3097 #ifdef ASSERT
3098 __ save_frame(0);
3099 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3100 __ sethi(last_rethrow_addrlit, L1);
3101 Address addr(L1, last_rethrow_addrlit.low10());
3102 __ rdpc(L2);
3103 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3104 __ st_ptr(L2, addr);
3105 __ restore();
3106 #endif
3107 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3108 __ delayed()->nop();
3109 %}
3111 enc_class emit_mem_nop() %{
3112 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3113 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3114 %}
3116 enc_class emit_fadd_nop() %{
3117 // Generates the instruction FMOVS f31,f31
3118 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3119 %}
3121 enc_class emit_br_nop() %{
3122 // Generates the instruction BPN,PN .
3123 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3124 %}
3126 enc_class enc_membar_acquire %{
3127 MacroAssembler _masm(&cbuf);
3128 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3129 %}
3131 enc_class enc_membar_release %{
3132 MacroAssembler _masm(&cbuf);
3133 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3134 %}
3136 enc_class enc_membar_volatile %{
3137 MacroAssembler _masm(&cbuf);
3138 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3139 %}
3141 %}
3143 //----------FRAME--------------------------------------------------------------
3144 // Definition of frame structure and management information.
3145 //
3146 // S T A C K L A Y O U T Allocators stack-slot number
3147 // | (to get allocators register number
3148 // G Owned by | | v add VMRegImpl::stack0)
3149 // r CALLER | |
3150 // o | +--------+ pad to even-align allocators stack-slot
3151 // w V | pad0 | numbers; owned by CALLER
3152 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3153 // h ^ | in | 5
3154 // | | args | 4 Holes in incoming args owned by SELF
3155 // | | | | 3
3156 // | | +--------+
3157 // V | | old out| Empty on Intel, window on Sparc
3158 // | old |preserve| Must be even aligned.
3159 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3160 // | | in | 3 area for Intel ret address
3161 // Owned by |preserve| Empty on Sparc.
3162 // SELF +--------+
3163 // | | pad2 | 2 pad to align old SP
3164 // | +--------+ 1
3165 // | | locks | 0
3166 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3167 // | | pad1 | 11 pad to align new SP
3168 // | +--------+
3169 // | | | 10
3170 // | | spills | 9 spills
3171 // V | | 8 (pad0 slot for callee)
3172 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3173 // ^ | out | 7
3174 // | | args | 6 Holes in outgoing args owned by CALLEE
3175 // Owned by +--------+
3176 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3177 // | new |preserve| Must be even-aligned.
3178 // | SP-+--------+----> Matcher::_new_SP, even aligned
3179 // | | |
3180 //
3181 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3182 // known from SELF's arguments and the Java calling convention.
3183 // Region 6-7 is determined per call site.
3184 // Note 2: If the calling convention leaves holes in the incoming argument
3185 // area, those holes are owned by SELF. Holes in the outgoing area
3186 // are owned by the CALLEE. Holes should not be nessecary in the
3187 // incoming area, as the Java calling convention is completely under
3188 // the control of the AD file. Doubles can be sorted and packed to
3189 // avoid holes. Holes in the outgoing arguments may be nessecary for
3190 // varargs C calling conventions.
3191 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3192 // even aligned with pad0 as needed.
3193 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3194 // region 6-11 is even aligned; it may be padded out more so that
3195 // the region from SP to FP meets the minimum stack alignment.
3197 frame %{
3198 // What direction does stack grow in (assumed to be same for native & Java)
3199 stack_direction(TOWARDS_LOW);
3201 // These two registers define part of the calling convention
3202 // between compiled code and the interpreter.
3203 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3204 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3206 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3207 cisc_spilling_operand_name(indOffset);
3209 // Number of stack slots consumed by a Monitor enter
3210 #ifdef _LP64
3211 sync_stack_slots(2);
3212 #else
3213 sync_stack_slots(1);
3214 #endif
3216 // Compiled code's Frame Pointer
3217 frame_pointer(R_SP);
3219 // Stack alignment requirement
3220 stack_alignment(StackAlignmentInBytes);
3221 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3222 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3224 // Number of stack slots between incoming argument block and the start of
3225 // a new frame. The PROLOG must add this many slots to the stack. The
3226 // EPILOG must remove this many slots.
3227 in_preserve_stack_slots(0);
3229 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3230 // for calls to C. Supports the var-args backing area for register parms.
3231 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3232 #ifdef _LP64
3233 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3234 varargs_C_out_slots_killed(12);
3235 #else
3236 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3237 varargs_C_out_slots_killed( 7);
3238 #endif
3240 // The after-PROLOG location of the return address. Location of
3241 // return address specifies a type (REG or STACK) and a number
3242 // representing the register number (i.e. - use a register name) or
3243 // stack slot.
3244 return_addr(REG R_I7); // Ret Addr is in register I7
3246 // Body of function which returns an OptoRegs array locating
3247 // arguments either in registers or in stack slots for calling
3248 // java
3249 calling_convention %{
3250 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3252 %}
3254 // Body of function which returns an OptoRegs array locating
3255 // arguments either in registers or in stack slots for callin
3256 // C.
3257 c_calling_convention %{
3258 // This is obviously always outgoing
3259 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3260 %}
3262 // Location of native (C/C++) and interpreter return values. This is specified to
3263 // be the same as Java. In the 32-bit VM, long values are actually returned from
3264 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3265 // to and from the register pairs is done by the appropriate call and epilog
3266 // opcodes. This simplifies the register allocator.
3267 c_return_value %{
3268 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3269 #ifdef _LP64
3270 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3271 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3272 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3273 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3274 #else // !_LP64
3275 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3276 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3277 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3278 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3279 #endif
3280 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3281 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3282 %}
3284 // Location of compiled Java return values. Same as C
3285 return_value %{
3286 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3287 #ifdef _LP64
3288 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3289 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3290 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3291 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3292 #else // !_LP64
3293 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3294 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3295 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3296 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3297 #endif
3298 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3299 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3300 %}
3302 %}
3305 //----------ATTRIBUTES---------------------------------------------------------
3306 //----------Operand Attributes-------------------------------------------------
3307 op_attrib op_cost(1); // Required cost attribute
3309 //----------Instruction Attributes---------------------------------------------
3310 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3311 ins_attrib ins_size(32); // Required size attribute (in bits)
3312 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3313 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3314 // non-matching short branch variant of some
3315 // long branch?
3317 //----------OPERANDS-----------------------------------------------------------
3318 // Operand definitions must precede instruction definitions for correct parsing
3319 // in the ADLC because operands constitute user defined types which are used in
3320 // instruction definitions.
3322 //----------Simple Operands----------------------------------------------------
3323 // Immediate Operands
3324 // Integer Immediate: 32-bit
3325 operand immI() %{
3326 match(ConI);
3328 op_cost(0);
3329 // formats are generated automatically for constants and base registers
3330 format %{ %}
3331 interface(CONST_INTER);
3332 %}
3334 // Integer Immediate: 8-bit
3335 operand immI8() %{
3336 predicate(Assembler::is_simm8(n->get_int()));
3337 match(ConI);
3338 op_cost(0);
3339 format %{ %}
3340 interface(CONST_INTER);
3341 %}
3343 // Integer Immediate: 13-bit
3344 operand immI13() %{
3345 predicate(Assembler::is_simm13(n->get_int()));
3346 match(ConI);
3347 op_cost(0);
3349 format %{ %}
3350 interface(CONST_INTER);
3351 %}
3353 // Integer Immediate: 13-bit minus 7
3354 operand immI13m7() %{
3355 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3356 match(ConI);
3357 op_cost(0);
3359 format %{ %}
3360 interface(CONST_INTER);
3361 %}
3363 // Integer Immediate: 16-bit
3364 operand immI16() %{
3365 predicate(Assembler::is_simm16(n->get_int()));
3366 match(ConI);
3367 op_cost(0);
3368 format %{ %}
3369 interface(CONST_INTER);
3370 %}
3372 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3373 operand immU12() %{
3374 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3375 match(ConI);
3376 op_cost(0);
3378 format %{ %}
3379 interface(CONST_INTER);
3380 %}
3382 // Integer Immediate: 6-bit
3383 operand immU6() %{
3384 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3385 match(ConI);
3386 op_cost(0);
3387 format %{ %}
3388 interface(CONST_INTER);
3389 %}
3391 // Integer Immediate: 11-bit
3392 operand immI11() %{
3393 predicate(Assembler::is_simm11(n->get_int()));
3394 match(ConI);
3395 op_cost(0);
3396 format %{ %}
3397 interface(CONST_INTER);
3398 %}
3400 // Integer Immediate: 5-bit
3401 operand immI5() %{
3402 predicate(Assembler::is_simm5(n->get_int()));
3403 match(ConI);
3404 op_cost(0);
3405 format %{ %}
3406 interface(CONST_INTER);
3407 %}
3409 // Int Immediate non-negative
3410 operand immU31()
3411 %{
3412 predicate(n->get_int() >= 0);
3413 match(ConI);
3415 op_cost(0);
3416 format %{ %}
3417 interface(CONST_INTER);
3418 %}
3420 // Integer Immediate: 0-bit
3421 operand immI0() %{
3422 predicate(n->get_int() == 0);
3423 match(ConI);
3424 op_cost(0);
3426 format %{ %}
3427 interface(CONST_INTER);
3428 %}
3430 // Integer Immediate: the value 10
3431 operand immI10() %{
3432 predicate(n->get_int() == 10);
3433 match(ConI);
3434 op_cost(0);
3436 format %{ %}
3437 interface(CONST_INTER);
3438 %}
3440 // Integer Immediate: the values 0-31
3441 operand immU5() %{
3442 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3443 match(ConI);
3444 op_cost(0);
3446 format %{ %}
3447 interface(CONST_INTER);
3448 %}
3450 // Integer Immediate: the values 1-31
3451 operand immI_1_31() %{
3452 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3453 match(ConI);
3454 op_cost(0);
3456 format %{ %}
3457 interface(CONST_INTER);
3458 %}
3460 // Integer Immediate: the values 32-63
3461 operand immI_32_63() %{
3462 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3463 match(ConI);
3464 op_cost(0);
3466 format %{ %}
3467 interface(CONST_INTER);
3468 %}
3470 // Immediates for special shifts (sign extend)
3472 // Integer Immediate: the value 16
3473 operand immI_16() %{
3474 predicate(n->get_int() == 16);
3475 match(ConI);
3476 op_cost(0);
3478 format %{ %}
3479 interface(CONST_INTER);
3480 %}
3482 // Integer Immediate: the value 24
3483 operand immI_24() %{
3484 predicate(n->get_int() == 24);
3485 match(ConI);
3486 op_cost(0);
3488 format %{ %}
3489 interface(CONST_INTER);
3490 %}
3492 // Integer Immediate: the value 255
3493 operand immI_255() %{
3494 predicate( n->get_int() == 255 );
3495 match(ConI);
3496 op_cost(0);
3498 format %{ %}
3499 interface(CONST_INTER);
3500 %}
3502 // Integer Immediate: the value 65535
3503 operand immI_65535() %{
3504 predicate(n->get_int() == 65535);
3505 match(ConI);
3506 op_cost(0);
3508 format %{ %}
3509 interface(CONST_INTER);
3510 %}
3512 // Long Immediate: the value FF
3513 operand immL_FF() %{
3514 predicate( n->get_long() == 0xFFL );
3515 match(ConL);
3516 op_cost(0);
3518 format %{ %}
3519 interface(CONST_INTER);
3520 %}
3522 // Long Immediate: the value FFFF
3523 operand immL_FFFF() %{
3524 predicate( n->get_long() == 0xFFFFL );
3525 match(ConL);
3526 op_cost(0);
3528 format %{ %}
3529 interface(CONST_INTER);
3530 %}
3532 // Pointer Immediate: 32 or 64-bit
3533 operand immP() %{
3534 match(ConP);
3536 op_cost(5);
3537 // formats are generated automatically for constants and base registers
3538 format %{ %}
3539 interface(CONST_INTER);
3540 %}
3542 #ifdef _LP64
3543 // Pointer Immediate: 64-bit
3544 operand immP_set() %{
3545 predicate(!VM_Version::is_niagara_plus());
3546 match(ConP);
3548 op_cost(5);
3549 // formats are generated automatically for constants and base registers
3550 format %{ %}
3551 interface(CONST_INTER);
3552 %}
3554 // Pointer Immediate: 64-bit
3555 // From Niagara2 processors on a load should be better than materializing.
3556 operand immP_load() %{
3557 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3558 match(ConP);
3560 op_cost(5);
3561 // formats are generated automatically for constants and base registers
3562 format %{ %}
3563 interface(CONST_INTER);
3564 %}
3566 // Pointer Immediate: 64-bit
3567 operand immP_no_oop_cheap() %{
3568 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3569 match(ConP);
3571 op_cost(5);
3572 // formats are generated automatically for constants and base registers
3573 format %{ %}
3574 interface(CONST_INTER);
3575 %}
3576 #endif
3578 operand immP13() %{
3579 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3580 match(ConP);
3581 op_cost(0);
3583 format %{ %}
3584 interface(CONST_INTER);
3585 %}
3587 operand immP0() %{
3588 predicate(n->get_ptr() == 0);
3589 match(ConP);
3590 op_cost(0);
3592 format %{ %}
3593 interface(CONST_INTER);
3594 %}
3596 operand immP_poll() %{
3597 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3598 match(ConP);
3600 // formats are generated automatically for constants and base registers
3601 format %{ %}
3602 interface(CONST_INTER);
3603 %}
3605 // Pointer Immediate
3606 operand immN()
3607 %{
3608 match(ConN);
3610 op_cost(10);
3611 format %{ %}
3612 interface(CONST_INTER);
3613 %}
3615 operand immNKlass()
3616 %{
3617 match(ConNKlass);
3619 op_cost(10);
3620 format %{ %}
3621 interface(CONST_INTER);
3622 %}
3624 // NULL Pointer Immediate
3625 operand immN0()
3626 %{
3627 predicate(n->get_narrowcon() == 0);
3628 match(ConN);
3630 op_cost(0);
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3635 operand immL() %{
3636 match(ConL);
3637 op_cost(40);
3638 // formats are generated automatically for constants and base registers
3639 format %{ %}
3640 interface(CONST_INTER);
3641 %}
3643 operand immL0() %{
3644 predicate(n->get_long() == 0L);
3645 match(ConL);
3646 op_cost(0);
3647 // formats are generated automatically for constants and base registers
3648 format %{ %}
3649 interface(CONST_INTER);
3650 %}
3652 // Integer Immediate: 5-bit
3653 operand immL5() %{
3654 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3655 match(ConL);
3656 op_cost(0);
3657 format %{ %}
3658 interface(CONST_INTER);
3659 %}
3661 // Long Immediate: 13-bit
3662 operand immL13() %{
3663 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3664 match(ConL);
3665 op_cost(0);
3667 format %{ %}
3668 interface(CONST_INTER);
3669 %}
3671 // Long Immediate: 13-bit minus 7
3672 operand immL13m7() %{
3673 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3674 match(ConL);
3675 op_cost(0);
3677 format %{ %}
3678 interface(CONST_INTER);
3679 %}
3681 // Long Immediate: low 32-bit mask
3682 operand immL_32bits() %{
3683 predicate(n->get_long() == 0xFFFFFFFFL);
3684 match(ConL);
3685 op_cost(0);
3687 format %{ %}
3688 interface(CONST_INTER);
3689 %}
3691 // Long Immediate: cheap (materialize in <= 3 instructions)
3692 operand immL_cheap() %{
3693 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3694 match(ConL);
3695 op_cost(0);
3697 format %{ %}
3698 interface(CONST_INTER);
3699 %}
3701 // Long Immediate: expensive (materialize in > 3 instructions)
3702 operand immL_expensive() %{
3703 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3704 match(ConL);
3705 op_cost(0);
3707 format %{ %}
3708 interface(CONST_INTER);
3709 %}
3711 // Double Immediate
3712 operand immD() %{
3713 match(ConD);
3715 op_cost(40);
3716 format %{ %}
3717 interface(CONST_INTER);
3718 %}
3720 operand immD0() %{
3721 #ifdef _LP64
3722 // on 64-bit architectures this comparision is faster
3723 predicate(jlong_cast(n->getd()) == 0);
3724 #else
3725 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3726 #endif
3727 match(ConD);
3729 op_cost(0);
3730 format %{ %}
3731 interface(CONST_INTER);
3732 %}
3734 // Float Immediate
3735 operand immF() %{
3736 match(ConF);
3738 op_cost(20);
3739 format %{ %}
3740 interface(CONST_INTER);
3741 %}
3743 // Float Immediate: 0
3744 operand immF0() %{
3745 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3746 match(ConF);
3748 op_cost(0);
3749 format %{ %}
3750 interface(CONST_INTER);
3751 %}
3753 // Integer Register Operands
3754 // Integer Register
3755 operand iRegI() %{
3756 constraint(ALLOC_IN_RC(int_reg));
3757 match(RegI);
3759 match(notemp_iRegI);
3760 match(g1RegI);
3761 match(o0RegI);
3762 match(iRegIsafe);
3764 format %{ %}
3765 interface(REG_INTER);
3766 %}
3768 operand notemp_iRegI() %{
3769 constraint(ALLOC_IN_RC(notemp_int_reg));
3770 match(RegI);
3772 match(o0RegI);
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3778 operand o0RegI() %{
3779 constraint(ALLOC_IN_RC(o0_regI));
3780 match(iRegI);
3782 format %{ %}
3783 interface(REG_INTER);
3784 %}
3786 // Pointer Register
3787 operand iRegP() %{
3788 constraint(ALLOC_IN_RC(ptr_reg));
3789 match(RegP);
3791 match(lock_ptr_RegP);
3792 match(g1RegP);
3793 match(g2RegP);
3794 match(g3RegP);
3795 match(g4RegP);
3796 match(i0RegP);
3797 match(o0RegP);
3798 match(o1RegP);
3799 match(l7RegP);
3801 format %{ %}
3802 interface(REG_INTER);
3803 %}
3805 operand sp_ptr_RegP() %{
3806 constraint(ALLOC_IN_RC(sp_ptr_reg));
3807 match(RegP);
3808 match(iRegP);
3810 format %{ %}
3811 interface(REG_INTER);
3812 %}
3814 operand lock_ptr_RegP() %{
3815 constraint(ALLOC_IN_RC(lock_ptr_reg));
3816 match(RegP);
3817 match(i0RegP);
3818 match(o0RegP);
3819 match(o1RegP);
3820 match(l7RegP);
3822 format %{ %}
3823 interface(REG_INTER);
3824 %}
3826 operand g1RegP() %{
3827 constraint(ALLOC_IN_RC(g1_regP));
3828 match(iRegP);
3830 format %{ %}
3831 interface(REG_INTER);
3832 %}
3834 operand g2RegP() %{
3835 constraint(ALLOC_IN_RC(g2_regP));
3836 match(iRegP);
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3842 operand g3RegP() %{
3843 constraint(ALLOC_IN_RC(g3_regP));
3844 match(iRegP);
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3850 operand g1RegI() %{
3851 constraint(ALLOC_IN_RC(g1_regI));
3852 match(iRegI);
3854 format %{ %}
3855 interface(REG_INTER);
3856 %}
3858 operand g3RegI() %{
3859 constraint(ALLOC_IN_RC(g3_regI));
3860 match(iRegI);
3862 format %{ %}
3863 interface(REG_INTER);
3864 %}
3866 operand g4RegI() %{
3867 constraint(ALLOC_IN_RC(g4_regI));
3868 match(iRegI);
3870 format %{ %}
3871 interface(REG_INTER);
3872 %}
3874 operand g4RegP() %{
3875 constraint(ALLOC_IN_RC(g4_regP));
3876 match(iRegP);
3878 format %{ %}
3879 interface(REG_INTER);
3880 %}
3882 operand i0RegP() %{
3883 constraint(ALLOC_IN_RC(i0_regP));
3884 match(iRegP);
3886 format %{ %}
3887 interface(REG_INTER);
3888 %}
3890 operand o0RegP() %{
3891 constraint(ALLOC_IN_RC(o0_regP));
3892 match(iRegP);
3894 format %{ %}
3895 interface(REG_INTER);
3896 %}
3898 operand o1RegP() %{
3899 constraint(ALLOC_IN_RC(o1_regP));
3900 match(iRegP);
3902 format %{ %}
3903 interface(REG_INTER);
3904 %}
3906 operand o2RegP() %{
3907 constraint(ALLOC_IN_RC(o2_regP));
3908 match(iRegP);
3910 format %{ %}
3911 interface(REG_INTER);
3912 %}
3914 operand o7RegP() %{
3915 constraint(ALLOC_IN_RC(o7_regP));
3916 match(iRegP);
3918 format %{ %}
3919 interface(REG_INTER);
3920 %}
3922 operand l7RegP() %{
3923 constraint(ALLOC_IN_RC(l7_regP));
3924 match(iRegP);
3926 format %{ %}
3927 interface(REG_INTER);
3928 %}
3930 operand o7RegI() %{
3931 constraint(ALLOC_IN_RC(o7_regI));
3932 match(iRegI);
3934 format %{ %}
3935 interface(REG_INTER);
3936 %}
3938 operand iRegN() %{
3939 constraint(ALLOC_IN_RC(int_reg));
3940 match(RegN);
3942 format %{ %}
3943 interface(REG_INTER);
3944 %}
3946 // Long Register
3947 operand iRegL() %{
3948 constraint(ALLOC_IN_RC(long_reg));
3949 match(RegL);
3951 format %{ %}
3952 interface(REG_INTER);
3953 %}
3955 operand o2RegL() %{
3956 constraint(ALLOC_IN_RC(o2_regL));
3957 match(iRegL);
3959 format %{ %}
3960 interface(REG_INTER);
3961 %}
3963 operand o7RegL() %{
3964 constraint(ALLOC_IN_RC(o7_regL));
3965 match(iRegL);
3967 format %{ %}
3968 interface(REG_INTER);
3969 %}
3971 operand g1RegL() %{
3972 constraint(ALLOC_IN_RC(g1_regL));
3973 match(iRegL);
3975 format %{ %}
3976 interface(REG_INTER);
3977 %}
3979 operand g3RegL() %{
3980 constraint(ALLOC_IN_RC(g3_regL));
3981 match(iRegL);
3983 format %{ %}
3984 interface(REG_INTER);
3985 %}
3987 // Int Register safe
3988 // This is 64bit safe
3989 operand iRegIsafe() %{
3990 constraint(ALLOC_IN_RC(long_reg));
3992 match(iRegI);
3994 format %{ %}
3995 interface(REG_INTER);
3996 %}
3998 // Condition Code Flag Register
3999 operand flagsReg() %{
4000 constraint(ALLOC_IN_RC(int_flags));
4001 match(RegFlags);
4003 format %{ "ccr" %} // both ICC and XCC
4004 interface(REG_INTER);
4005 %}
4007 // Condition Code Register, unsigned comparisons.
4008 operand flagsRegU() %{
4009 constraint(ALLOC_IN_RC(int_flags));
4010 match(RegFlags);
4012 format %{ "icc_U" %}
4013 interface(REG_INTER);
4014 %}
4016 // Condition Code Register, pointer comparisons.
4017 operand flagsRegP() %{
4018 constraint(ALLOC_IN_RC(int_flags));
4019 match(RegFlags);
4021 #ifdef _LP64
4022 format %{ "xcc_P" %}
4023 #else
4024 format %{ "icc_P" %}
4025 #endif
4026 interface(REG_INTER);
4027 %}
4029 // Condition Code Register, long comparisons.
4030 operand flagsRegL() %{
4031 constraint(ALLOC_IN_RC(int_flags));
4032 match(RegFlags);
4034 format %{ "xcc_L" %}
4035 interface(REG_INTER);
4036 %}
4038 // Condition Code Register, floating comparisons, unordered same as "less".
4039 operand flagsRegF() %{
4040 constraint(ALLOC_IN_RC(float_flags));
4041 match(RegFlags);
4042 match(flagsRegF0);
4044 format %{ %}
4045 interface(REG_INTER);
4046 %}
4048 operand flagsRegF0() %{
4049 constraint(ALLOC_IN_RC(float_flag0));
4050 match(RegFlags);
4052 format %{ %}
4053 interface(REG_INTER);
4054 %}
4057 // Condition Code Flag Register used by long compare
4058 operand flagsReg_long_LTGE() %{
4059 constraint(ALLOC_IN_RC(int_flags));
4060 match(RegFlags);
4061 format %{ "icc_LTGE" %}
4062 interface(REG_INTER);
4063 %}
4064 operand flagsReg_long_EQNE() %{
4065 constraint(ALLOC_IN_RC(int_flags));
4066 match(RegFlags);
4067 format %{ "icc_EQNE" %}
4068 interface(REG_INTER);
4069 %}
4070 operand flagsReg_long_LEGT() %{
4071 constraint(ALLOC_IN_RC(int_flags));
4072 match(RegFlags);
4073 format %{ "icc_LEGT" %}
4074 interface(REG_INTER);
4075 %}
4078 operand regD() %{
4079 constraint(ALLOC_IN_RC(dflt_reg));
4080 match(RegD);
4082 match(regD_low);
4084 format %{ %}
4085 interface(REG_INTER);
4086 %}
4088 operand regF() %{
4089 constraint(ALLOC_IN_RC(sflt_reg));
4090 match(RegF);
4092 format %{ %}
4093 interface(REG_INTER);
4094 %}
4096 operand regD_low() %{
4097 constraint(ALLOC_IN_RC(dflt_low_reg));
4098 match(regD);
4100 format %{ %}
4101 interface(REG_INTER);
4102 %}
4104 // Special Registers
4106 // Method Register
4107 operand inline_cache_regP(iRegP reg) %{
4108 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4109 match(reg);
4110 format %{ %}
4111 interface(REG_INTER);
4112 %}
4114 operand interpreter_method_oop_regP(iRegP reg) %{
4115 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4116 match(reg);
4117 format %{ %}
4118 interface(REG_INTER);
4119 %}
4122 //----------Complex Operands---------------------------------------------------
4123 // Indirect Memory Reference
4124 operand indirect(sp_ptr_RegP reg) %{
4125 constraint(ALLOC_IN_RC(sp_ptr_reg));
4126 match(reg);
4128 op_cost(100);
4129 format %{ "[$reg]" %}
4130 interface(MEMORY_INTER) %{
4131 base($reg);
4132 index(0x0);
4133 scale(0x0);
4134 disp(0x0);
4135 %}
4136 %}
4138 // Indirect with simm13 Offset
4139 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4140 constraint(ALLOC_IN_RC(sp_ptr_reg));
4141 match(AddP reg offset);
4143 op_cost(100);
4144 format %{ "[$reg + $offset]" %}
4145 interface(MEMORY_INTER) %{
4146 base($reg);
4147 index(0x0);
4148 scale(0x0);
4149 disp($offset);
4150 %}
4151 %}
4153 // Indirect with simm13 Offset minus 7
4154 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4155 constraint(ALLOC_IN_RC(sp_ptr_reg));
4156 match(AddP reg offset);
4158 op_cost(100);
4159 format %{ "[$reg + $offset]" %}
4160 interface(MEMORY_INTER) %{
4161 base($reg);
4162 index(0x0);
4163 scale(0x0);
4164 disp($offset);
4165 %}
4166 %}
4168 // Note: Intel has a swapped version also, like this:
4169 //operand indOffsetX(iRegI reg, immP offset) %{
4170 // constraint(ALLOC_IN_RC(int_reg));
4171 // match(AddP offset reg);
4172 //
4173 // op_cost(100);
4174 // format %{ "[$reg + $offset]" %}
4175 // interface(MEMORY_INTER) %{
4176 // base($reg);
4177 // index(0x0);
4178 // scale(0x0);
4179 // disp($offset);
4180 // %}
4181 //%}
4182 //// However, it doesn't make sense for SPARC, since
4183 // we have no particularly good way to embed oops in
4184 // single instructions.
4186 // Indirect with Register Index
4187 operand indIndex(iRegP addr, iRegX index) %{
4188 constraint(ALLOC_IN_RC(ptr_reg));
4189 match(AddP addr index);
4191 op_cost(100);
4192 format %{ "[$addr + $index]" %}
4193 interface(MEMORY_INTER) %{
4194 base($addr);
4195 index($index);
4196 scale(0x0);
4197 disp(0x0);
4198 %}
4199 %}
4201 //----------Special Memory Operands--------------------------------------------
4202 // Stack Slot Operand - This operand is used for loading and storing temporary
4203 // values on the stack where a match requires a value to
4204 // flow through memory.
4205 operand stackSlotI(sRegI reg) %{
4206 constraint(ALLOC_IN_RC(stack_slots));
4207 op_cost(100);
4208 //match(RegI);
4209 format %{ "[$reg]" %}
4210 interface(MEMORY_INTER) %{
4211 base(0xE); // R_SP
4212 index(0x0);
4213 scale(0x0);
4214 disp($reg); // Stack Offset
4215 %}
4216 %}
4218 operand stackSlotP(sRegP reg) %{
4219 constraint(ALLOC_IN_RC(stack_slots));
4220 op_cost(100);
4221 //match(RegP);
4222 format %{ "[$reg]" %}
4223 interface(MEMORY_INTER) %{
4224 base(0xE); // R_SP
4225 index(0x0);
4226 scale(0x0);
4227 disp($reg); // Stack Offset
4228 %}
4229 %}
4231 operand stackSlotF(sRegF reg) %{
4232 constraint(ALLOC_IN_RC(stack_slots));
4233 op_cost(100);
4234 //match(RegF);
4235 format %{ "[$reg]" %}
4236 interface(MEMORY_INTER) %{
4237 base(0xE); // R_SP
4238 index(0x0);
4239 scale(0x0);
4240 disp($reg); // Stack Offset
4241 %}
4242 %}
4243 operand stackSlotD(sRegD reg) %{
4244 constraint(ALLOC_IN_RC(stack_slots));
4245 op_cost(100);
4246 //match(RegD);
4247 format %{ "[$reg]" %}
4248 interface(MEMORY_INTER) %{
4249 base(0xE); // R_SP
4250 index(0x0);
4251 scale(0x0);
4252 disp($reg); // Stack Offset
4253 %}
4254 %}
4255 operand stackSlotL(sRegL reg) %{
4256 constraint(ALLOC_IN_RC(stack_slots));
4257 op_cost(100);
4258 //match(RegL);
4259 format %{ "[$reg]" %}
4260 interface(MEMORY_INTER) %{
4261 base(0xE); // R_SP
4262 index(0x0);
4263 scale(0x0);
4264 disp($reg); // Stack Offset
4265 %}
4266 %}
4268 // Operands for expressing Control Flow
4269 // NOTE: Label is a predefined operand which should not be redefined in
4270 // the AD file. It is generically handled within the ADLC.
4272 //----------Conditional Branch Operands----------------------------------------
4273 // Comparison Op - This is the operation of the comparison, and is limited to
4274 // the following set of codes:
4275 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4276 //
4277 // Other attributes of the comparison, such as unsignedness, are specified
4278 // by the comparison instruction that sets a condition code flags register.
4279 // That result is represented by a flags operand whose subtype is appropriate
4280 // to the unsignedness (etc.) of the comparison.
4281 //
4282 // Later, the instruction which matches both the Comparison Op (a Bool) and
4283 // the flags (produced by the Cmp) specifies the coding of the comparison op
4284 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4286 operand cmpOp() %{
4287 match(Bool);
4289 format %{ "" %}
4290 interface(COND_INTER) %{
4291 equal(0x1);
4292 not_equal(0x9);
4293 less(0x3);
4294 greater_equal(0xB);
4295 less_equal(0x2);
4296 greater(0xA);
4297 overflow(0x7);
4298 no_overflow(0xF);
4299 %}
4300 %}
4302 // Comparison Op, unsigned
4303 operand cmpOpU() %{
4304 match(Bool);
4305 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4306 n->as_Bool()->_test._test != BoolTest::no_overflow);
4308 format %{ "u" %}
4309 interface(COND_INTER) %{
4310 equal(0x1);
4311 not_equal(0x9);
4312 less(0x5);
4313 greater_equal(0xD);
4314 less_equal(0x4);
4315 greater(0xC);
4316 overflow(0x7);
4317 no_overflow(0xF);
4318 %}
4319 %}
4321 // Comparison Op, pointer (same as unsigned)
4322 operand cmpOpP() %{
4323 match(Bool);
4324 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4325 n->as_Bool()->_test._test != BoolTest::no_overflow);
4327 format %{ "p" %}
4328 interface(COND_INTER) %{
4329 equal(0x1);
4330 not_equal(0x9);
4331 less(0x5);
4332 greater_equal(0xD);
4333 less_equal(0x4);
4334 greater(0xC);
4335 overflow(0x7);
4336 no_overflow(0xF);
4337 %}
4338 %}
4340 // Comparison Op, branch-register encoding
4341 operand cmpOp_reg() %{
4342 match(Bool);
4343 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4344 n->as_Bool()->_test._test != BoolTest::no_overflow);
4346 format %{ "" %}
4347 interface(COND_INTER) %{
4348 equal (0x1);
4349 not_equal (0x5);
4350 less (0x3);
4351 greater_equal(0x7);
4352 less_equal (0x2);
4353 greater (0x6);
4354 overflow(0x7); // not supported
4355 no_overflow(0xF); // not supported
4356 %}
4357 %}
4359 // Comparison Code, floating, unordered same as less
4360 operand cmpOpF() %{
4361 match(Bool);
4362 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4363 n->as_Bool()->_test._test != BoolTest::no_overflow);
4365 format %{ "fl" %}
4366 interface(COND_INTER) %{
4367 equal(0x9);
4368 not_equal(0x1);
4369 less(0x3);
4370 greater_equal(0xB);
4371 less_equal(0xE);
4372 greater(0x6);
4374 overflow(0x7); // not supported
4375 no_overflow(0xF); // not supported
4376 %}
4377 %}
4379 // Used by long compare
4380 operand cmpOp_commute() %{
4381 match(Bool);
4382 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4383 n->as_Bool()->_test._test != BoolTest::no_overflow);
4385 format %{ "" %}
4386 interface(COND_INTER) %{
4387 equal(0x1);
4388 not_equal(0x9);
4389 less(0xA);
4390 greater_equal(0x2);
4391 less_equal(0xB);
4392 greater(0x3);
4393 overflow(0x7);
4394 no_overflow(0xF);
4395 %}
4396 %}
4398 //----------OPERAND CLASSES----------------------------------------------------
4399 // Operand Classes are groups of operands that are used to simplify
4400 // instruction definitions by not requiring the AD writer to specify separate
4401 // instructions for every form of operand when the instruction accepts
4402 // multiple operand types with the same basic encoding and format. The classic
4403 // case of this is memory operands.
4404 opclass memory( indirect, indOffset13, indIndex );
4405 opclass indIndexMemory( indIndex );
4407 //----------PIPELINE-----------------------------------------------------------
4408 pipeline %{
4410 //----------ATTRIBUTES---------------------------------------------------------
4411 attributes %{
4412 fixed_size_instructions; // Fixed size instructions
4413 branch_has_delay_slot; // Branch has delay slot following
4414 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4415 instruction_unit_size = 4; // An instruction is 4 bytes long
4416 instruction_fetch_unit_size = 16; // The processor fetches one line
4417 instruction_fetch_units = 1; // of 16 bytes
4419 // List of nop instructions
4420 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4421 %}
4423 //----------RESOURCES----------------------------------------------------------
4424 // Resources are the functional units available to the machine
4425 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4427 //----------PIPELINE DESCRIPTION-----------------------------------------------
4428 // Pipeline Description specifies the stages in the machine's pipeline
4430 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4432 //----------PIPELINE CLASSES---------------------------------------------------
4433 // Pipeline Classes describe the stages in which input and output are
4434 // referenced by the hardware pipeline.
4436 // Integer ALU reg-reg operation
4437 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4438 single_instruction;
4439 dst : E(write);
4440 src1 : R(read);
4441 src2 : R(read);
4442 IALU : R;
4443 %}
4445 // Integer ALU reg-reg long operation
4446 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4447 instruction_count(2);
4448 dst : E(write);
4449 src1 : R(read);
4450 src2 : R(read);
4451 IALU : R;
4452 IALU : R;
4453 %}
4455 // Integer ALU reg-reg long dependent operation
4456 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4457 instruction_count(1); multiple_bundles;
4458 dst : E(write);
4459 src1 : R(read);
4460 src2 : R(read);
4461 cr : E(write);
4462 IALU : R(2);
4463 %}
4465 // Integer ALU reg-imm operaion
4466 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4467 single_instruction;
4468 dst : E(write);
4469 src1 : R(read);
4470 IALU : R;
4471 %}
4473 // Integer ALU reg-reg operation with condition code
4474 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4475 single_instruction;
4476 dst : E(write);
4477 cr : E(write);
4478 src1 : R(read);
4479 src2 : R(read);
4480 IALU : R;
4481 %}
4483 // Integer ALU reg-imm operation with condition code
4484 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4485 single_instruction;
4486 dst : E(write);
4487 cr : E(write);
4488 src1 : R(read);
4489 IALU : R;
4490 %}
4492 // Integer ALU zero-reg operation
4493 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4494 single_instruction;
4495 dst : E(write);
4496 src2 : R(read);
4497 IALU : R;
4498 %}
4500 // Integer ALU zero-reg operation with condition code only
4501 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4502 single_instruction;
4503 cr : E(write);
4504 src : R(read);
4505 IALU : R;
4506 %}
4508 // Integer ALU reg-reg operation with condition code only
4509 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4510 single_instruction;
4511 cr : E(write);
4512 src1 : R(read);
4513 src2 : R(read);
4514 IALU : R;
4515 %}
4517 // Integer ALU reg-imm operation with condition code only
4518 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4519 single_instruction;
4520 cr : E(write);
4521 src1 : R(read);
4522 IALU : R;
4523 %}
4525 // Integer ALU reg-reg-zero operation with condition code only
4526 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4527 single_instruction;
4528 cr : E(write);
4529 src1 : R(read);
4530 src2 : R(read);
4531 IALU : R;
4532 %}
4534 // Integer ALU reg-imm-zero operation with condition code only
4535 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4536 single_instruction;
4537 cr : E(write);
4538 src1 : R(read);
4539 IALU : R;
4540 %}
4542 // Integer ALU reg-reg operation with condition code, src1 modified
4543 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4544 single_instruction;
4545 cr : E(write);
4546 src1 : E(write);
4547 src1 : R(read);
4548 src2 : R(read);
4549 IALU : R;
4550 %}
4552 // Integer ALU reg-imm operation with condition code, src1 modified
4553 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4554 single_instruction;
4555 cr : E(write);
4556 src1 : E(write);
4557 src1 : R(read);
4558 IALU : R;
4559 %}
4561 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4562 multiple_bundles;
4563 dst : E(write)+4;
4564 cr : E(write);
4565 src1 : R(read);
4566 src2 : R(read);
4567 IALU : R(3);
4568 BR : R(2);
4569 %}
4571 // Integer ALU operation
4572 pipe_class ialu_none(iRegI dst) %{
4573 single_instruction;
4574 dst : E(write);
4575 IALU : R;
4576 %}
4578 // Integer ALU reg operation
4579 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4580 single_instruction; may_have_no_code;
4581 dst : E(write);
4582 src : R(read);
4583 IALU : R;
4584 %}
4586 // Integer ALU reg conditional operation
4587 // This instruction has a 1 cycle stall, and cannot execute
4588 // in the same cycle as the instruction setting the condition
4589 // code. We kludge this by pretending to read the condition code
4590 // 1 cycle earlier, and by marking the functional units as busy
4591 // for 2 cycles with the result available 1 cycle later than
4592 // is really the case.
4593 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4594 single_instruction;
4595 op2_out : C(write);
4596 op1 : R(read);
4597 cr : R(read); // This is really E, with a 1 cycle stall
4598 BR : R(2);
4599 MS : R(2);
4600 %}
4602 #ifdef _LP64
4603 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4604 instruction_count(1); multiple_bundles;
4605 dst : C(write)+1;
4606 src : R(read)+1;
4607 IALU : R(1);
4608 BR : E(2);
4609 MS : E(2);
4610 %}
4611 #endif
4613 // Integer ALU reg operation
4614 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4615 single_instruction; may_have_no_code;
4616 dst : E(write);
4617 src : R(read);
4618 IALU : R;
4619 %}
4620 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4621 single_instruction; may_have_no_code;
4622 dst : E(write);
4623 src : R(read);
4624 IALU : R;
4625 %}
4627 // Two integer ALU reg operations
4628 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4629 instruction_count(2);
4630 dst : E(write);
4631 src : R(read);
4632 A0 : R;
4633 A1 : R;
4634 %}
4636 // Two integer ALU reg operations
4637 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4638 instruction_count(2); may_have_no_code;
4639 dst : E(write);
4640 src : R(read);
4641 A0 : R;
4642 A1 : R;
4643 %}
4645 // Integer ALU imm operation
4646 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4647 single_instruction;
4648 dst : E(write);
4649 IALU : R;
4650 %}
4652 // Integer ALU reg-reg with carry operation
4653 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4654 single_instruction;
4655 dst : E(write);
4656 src1 : R(read);
4657 src2 : R(read);
4658 IALU : R;
4659 %}
4661 // Integer ALU cc operation
4662 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4663 single_instruction;
4664 dst : E(write);
4665 cc : R(read);
4666 IALU : R;
4667 %}
4669 // Integer ALU cc / second IALU operation
4670 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4671 instruction_count(1); multiple_bundles;
4672 dst : E(write)+1;
4673 src : R(read);
4674 IALU : R;
4675 %}
4677 // Integer ALU cc / second IALU operation
4678 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4679 instruction_count(1); multiple_bundles;
4680 dst : E(write)+1;
4681 p : R(read);
4682 q : R(read);
4683 IALU : R;
4684 %}
4686 // Integer ALU hi-lo-reg operation
4687 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4688 instruction_count(1); multiple_bundles;
4689 dst : E(write)+1;
4690 IALU : R(2);
4691 %}
4693 // Float ALU hi-lo-reg operation (with temp)
4694 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4695 instruction_count(1); multiple_bundles;
4696 dst : E(write)+1;
4697 IALU : R(2);
4698 %}
4700 // Long Constant
4701 pipe_class loadConL( iRegL dst, immL src ) %{
4702 instruction_count(2); multiple_bundles;
4703 dst : E(write)+1;
4704 IALU : R(2);
4705 IALU : R(2);
4706 %}
4708 // Pointer Constant
4709 pipe_class loadConP( iRegP dst, immP src ) %{
4710 instruction_count(0); multiple_bundles;
4711 fixed_latency(6);
4712 %}
4714 // Polling Address
4715 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4716 #ifdef _LP64
4717 instruction_count(0); multiple_bundles;
4718 fixed_latency(6);
4719 #else
4720 dst : E(write);
4721 IALU : R;
4722 #endif
4723 %}
4725 // Long Constant small
4726 pipe_class loadConLlo( iRegL dst, immL src ) %{
4727 instruction_count(2);
4728 dst : E(write);
4729 IALU : R;
4730 IALU : R;
4731 %}
4733 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4734 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4735 instruction_count(1); multiple_bundles;
4736 src : R(read);
4737 dst : M(write)+1;
4738 IALU : R;
4739 MS : E;
4740 %}
4742 // Integer ALU nop operation
4743 pipe_class ialu_nop() %{
4744 single_instruction;
4745 IALU : R;
4746 %}
4748 // Integer ALU nop operation
4749 pipe_class ialu_nop_A0() %{
4750 single_instruction;
4751 A0 : R;
4752 %}
4754 // Integer ALU nop operation
4755 pipe_class ialu_nop_A1() %{
4756 single_instruction;
4757 A1 : R;
4758 %}
4760 // Integer Multiply reg-reg operation
4761 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4762 single_instruction;
4763 dst : E(write);
4764 src1 : R(read);
4765 src2 : R(read);
4766 MS : R(5);
4767 %}
4769 // Integer Multiply reg-imm operation
4770 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4771 single_instruction;
4772 dst : E(write);
4773 src1 : R(read);
4774 MS : R(5);
4775 %}
4777 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4778 single_instruction;
4779 dst : E(write)+4;
4780 src1 : R(read);
4781 src2 : R(read);
4782 MS : R(6);
4783 %}
4785 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4786 single_instruction;
4787 dst : E(write)+4;
4788 src1 : R(read);
4789 MS : R(6);
4790 %}
4792 // Integer Divide reg-reg
4793 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4794 instruction_count(1); multiple_bundles;
4795 dst : E(write);
4796 temp : E(write);
4797 src1 : R(read);
4798 src2 : R(read);
4799 temp : R(read);
4800 MS : R(38);
4801 %}
4803 // Integer Divide reg-imm
4804 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4805 instruction_count(1); multiple_bundles;
4806 dst : E(write);
4807 temp : E(write);
4808 src1 : R(read);
4809 temp : R(read);
4810 MS : R(38);
4811 %}
4813 // Long Divide
4814 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4815 dst : E(write)+71;
4816 src1 : R(read);
4817 src2 : R(read)+1;
4818 MS : R(70);
4819 %}
4821 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4822 dst : E(write)+71;
4823 src1 : R(read);
4824 MS : R(70);
4825 %}
4827 // Floating Point Add Float
4828 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4829 single_instruction;
4830 dst : X(write);
4831 src1 : E(read);
4832 src2 : E(read);
4833 FA : R;
4834 %}
4836 // Floating Point Add Double
4837 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4838 single_instruction;
4839 dst : X(write);
4840 src1 : E(read);
4841 src2 : E(read);
4842 FA : R;
4843 %}
4845 // Floating Point Conditional Move based on integer flags
4846 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4847 single_instruction;
4848 dst : X(write);
4849 src : E(read);
4850 cr : R(read);
4851 FA : R(2);
4852 BR : R(2);
4853 %}
4855 // Floating Point Conditional Move based on integer flags
4856 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4857 single_instruction;
4858 dst : X(write);
4859 src : E(read);
4860 cr : R(read);
4861 FA : R(2);
4862 BR : R(2);
4863 %}
4865 // Floating Point Multiply Float
4866 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4867 single_instruction;
4868 dst : X(write);
4869 src1 : E(read);
4870 src2 : E(read);
4871 FM : R;
4872 %}
4874 // Floating Point Multiply Double
4875 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4876 single_instruction;
4877 dst : X(write);
4878 src1 : E(read);
4879 src2 : E(read);
4880 FM : R;
4881 %}
4883 // Floating Point Divide Float
4884 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4885 single_instruction;
4886 dst : X(write);
4887 src1 : E(read);
4888 src2 : E(read);
4889 FM : R;
4890 FDIV : C(14);
4891 %}
4893 // Floating Point Divide Double
4894 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4895 single_instruction;
4896 dst : X(write);
4897 src1 : E(read);
4898 src2 : E(read);
4899 FM : R;
4900 FDIV : C(17);
4901 %}
4903 // Floating Point Move/Negate/Abs Float
4904 pipe_class faddF_reg(regF dst, regF src) %{
4905 single_instruction;
4906 dst : W(write);
4907 src : E(read);
4908 FA : R(1);
4909 %}
4911 // Floating Point Move/Negate/Abs Double
4912 pipe_class faddD_reg(regD dst, regD src) %{
4913 single_instruction;
4914 dst : W(write);
4915 src : E(read);
4916 FA : R;
4917 %}
4919 // Floating Point Convert F->D
4920 pipe_class fcvtF2D(regD dst, regF src) %{
4921 single_instruction;
4922 dst : X(write);
4923 src : E(read);
4924 FA : R;
4925 %}
4927 // Floating Point Convert I->D
4928 pipe_class fcvtI2D(regD dst, regF src) %{
4929 single_instruction;
4930 dst : X(write);
4931 src : E(read);
4932 FA : R;
4933 %}
4935 // Floating Point Convert LHi->D
4936 pipe_class fcvtLHi2D(regD dst, regD src) %{
4937 single_instruction;
4938 dst : X(write);
4939 src : E(read);
4940 FA : R;
4941 %}
4943 // Floating Point Convert L->D
4944 pipe_class fcvtL2D(regD dst, regF src) %{
4945 single_instruction;
4946 dst : X(write);
4947 src : E(read);
4948 FA : R;
4949 %}
4951 // Floating Point Convert L->F
4952 pipe_class fcvtL2F(regD dst, regF src) %{
4953 single_instruction;
4954 dst : X(write);
4955 src : E(read);
4956 FA : R;
4957 %}
4959 // Floating Point Convert D->F
4960 pipe_class fcvtD2F(regD dst, regF src) %{
4961 single_instruction;
4962 dst : X(write);
4963 src : E(read);
4964 FA : R;
4965 %}
4967 // Floating Point Convert I->L
4968 pipe_class fcvtI2L(regD dst, regF src) %{
4969 single_instruction;
4970 dst : X(write);
4971 src : E(read);
4972 FA : R;
4973 %}
4975 // Floating Point Convert D->F
4976 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4977 instruction_count(1); multiple_bundles;
4978 dst : X(write)+6;
4979 src : E(read);
4980 FA : R;
4981 %}
4983 // Floating Point Convert D->L
4984 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4985 instruction_count(1); multiple_bundles;
4986 dst : X(write)+6;
4987 src : E(read);
4988 FA : R;
4989 %}
4991 // Floating Point Convert F->I
4992 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4993 instruction_count(1); multiple_bundles;
4994 dst : X(write)+6;
4995 src : E(read);
4996 FA : R;
4997 %}
4999 // Floating Point Convert F->L
5000 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
5001 instruction_count(1); multiple_bundles;
5002 dst : X(write)+6;
5003 src : E(read);
5004 FA : R;
5005 %}
5007 // Floating Point Convert I->F
5008 pipe_class fcvtI2F(regF dst, regF src) %{
5009 single_instruction;
5010 dst : X(write);
5011 src : E(read);
5012 FA : R;
5013 %}
5015 // Floating Point Compare
5016 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5017 single_instruction;
5018 cr : X(write);
5019 src1 : E(read);
5020 src2 : E(read);
5021 FA : R;
5022 %}
5024 // Floating Point Compare
5025 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5026 single_instruction;
5027 cr : X(write);
5028 src1 : E(read);
5029 src2 : E(read);
5030 FA : R;
5031 %}
5033 // Floating Add Nop
5034 pipe_class fadd_nop() %{
5035 single_instruction;
5036 FA : R;
5037 %}
5039 // Integer Store to Memory
5040 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5041 single_instruction;
5042 mem : R(read);
5043 src : C(read);
5044 MS : R;
5045 %}
5047 // Integer Store to Memory
5048 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5049 single_instruction;
5050 mem : R(read);
5051 src : C(read);
5052 MS : R;
5053 %}
5055 // Integer Store Zero to Memory
5056 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5057 single_instruction;
5058 mem : R(read);
5059 MS : R;
5060 %}
5062 // Special Stack Slot Store
5063 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5064 single_instruction;
5065 stkSlot : R(read);
5066 src : C(read);
5067 MS : R;
5068 %}
5070 // Special Stack Slot Store
5071 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5072 instruction_count(2); multiple_bundles;
5073 stkSlot : R(read);
5074 src : C(read);
5075 MS : R(2);
5076 %}
5078 // Float Store
5079 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5080 single_instruction;
5081 mem : R(read);
5082 src : C(read);
5083 MS : R;
5084 %}
5086 // Float Store
5087 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5088 single_instruction;
5089 mem : R(read);
5090 MS : R;
5091 %}
5093 // Double Store
5094 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5095 instruction_count(1);
5096 mem : R(read);
5097 src : C(read);
5098 MS : R;
5099 %}
5101 // Double Store
5102 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5103 single_instruction;
5104 mem : R(read);
5105 MS : R;
5106 %}
5108 // Special Stack Slot Float Store
5109 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5110 single_instruction;
5111 stkSlot : R(read);
5112 src : C(read);
5113 MS : R;
5114 %}
5116 // Special Stack Slot Double Store
5117 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5118 single_instruction;
5119 stkSlot : R(read);
5120 src : C(read);
5121 MS : R;
5122 %}
5124 // Integer Load (when sign bit propagation not needed)
5125 pipe_class iload_mem(iRegI dst, memory mem) %{
5126 single_instruction;
5127 mem : R(read);
5128 dst : C(write);
5129 MS : R;
5130 %}
5132 // Integer Load from stack operand
5133 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5134 single_instruction;
5135 mem : R(read);
5136 dst : C(write);
5137 MS : R;
5138 %}
5140 // Integer Load (when sign bit propagation or masking is needed)
5141 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5142 single_instruction;
5143 mem : R(read);
5144 dst : M(write);
5145 MS : R;
5146 %}
5148 // Float Load
5149 pipe_class floadF_mem(regF dst, memory mem) %{
5150 single_instruction;
5151 mem : R(read);
5152 dst : M(write);
5153 MS : R;
5154 %}
5156 // Float Load
5157 pipe_class floadD_mem(regD dst, memory mem) %{
5158 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5159 mem : R(read);
5160 dst : M(write);
5161 MS : R;
5162 %}
5164 // Float Load
5165 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5166 single_instruction;
5167 stkSlot : R(read);
5168 dst : M(write);
5169 MS : R;
5170 %}
5172 // Float Load
5173 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5174 single_instruction;
5175 stkSlot : R(read);
5176 dst : M(write);
5177 MS : R;
5178 %}
5180 // Memory Nop
5181 pipe_class mem_nop() %{
5182 single_instruction;
5183 MS : R;
5184 %}
5186 pipe_class sethi(iRegP dst, immI src) %{
5187 single_instruction;
5188 dst : E(write);
5189 IALU : R;
5190 %}
5192 pipe_class loadPollP(iRegP poll) %{
5193 single_instruction;
5194 poll : R(read);
5195 MS : R;
5196 %}
5198 pipe_class br(Universe br, label labl) %{
5199 single_instruction_with_delay_slot;
5200 BR : R;
5201 %}
5203 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5204 single_instruction_with_delay_slot;
5205 cr : E(read);
5206 BR : R;
5207 %}
5209 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5210 single_instruction_with_delay_slot;
5211 op1 : E(read);
5212 BR : R;
5213 MS : R;
5214 %}
5216 // Compare and branch
5217 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5218 instruction_count(2); has_delay_slot;
5219 cr : E(write);
5220 src1 : R(read);
5221 src2 : R(read);
5222 IALU : R;
5223 BR : R;
5224 %}
5226 // Compare and branch
5227 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5228 instruction_count(2); has_delay_slot;
5229 cr : E(write);
5230 src1 : R(read);
5231 IALU : R;
5232 BR : R;
5233 %}
5235 // Compare and branch using cbcond
5236 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5237 single_instruction;
5238 src1 : E(read);
5239 src2 : E(read);
5240 IALU : R;
5241 BR : R;
5242 %}
5244 // Compare and branch using cbcond
5245 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5246 single_instruction;
5247 src1 : E(read);
5248 IALU : R;
5249 BR : R;
5250 %}
5252 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5253 single_instruction_with_delay_slot;
5254 cr : E(read);
5255 BR : R;
5256 %}
5258 pipe_class br_nop() %{
5259 single_instruction;
5260 BR : R;
5261 %}
5263 pipe_class simple_call(method meth) %{
5264 instruction_count(2); multiple_bundles; force_serialization;
5265 fixed_latency(100);
5266 BR : R(1);
5267 MS : R(1);
5268 A0 : R(1);
5269 %}
5271 pipe_class compiled_call(method meth) %{
5272 instruction_count(1); multiple_bundles; force_serialization;
5273 fixed_latency(100);
5274 MS : R(1);
5275 %}
5277 pipe_class call(method meth) %{
5278 instruction_count(0); multiple_bundles; force_serialization;
5279 fixed_latency(100);
5280 %}
5282 pipe_class tail_call(Universe ignore, label labl) %{
5283 single_instruction; has_delay_slot;
5284 fixed_latency(100);
5285 BR : R(1);
5286 MS : R(1);
5287 %}
5289 pipe_class ret(Universe ignore) %{
5290 single_instruction; has_delay_slot;
5291 BR : R(1);
5292 MS : R(1);
5293 %}
5295 pipe_class ret_poll(g3RegP poll) %{
5296 instruction_count(3); has_delay_slot;
5297 poll : E(read);
5298 MS : R;
5299 %}
5301 // The real do-nothing guy
5302 pipe_class empty( ) %{
5303 instruction_count(0);
5304 %}
5306 pipe_class long_memory_op() %{
5307 instruction_count(0); multiple_bundles; force_serialization;
5308 fixed_latency(25);
5309 MS : R(1);
5310 %}
5312 // Check-cast
5313 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5314 array : R(read);
5315 match : R(read);
5316 IALU : R(2);
5317 BR : R(2);
5318 MS : R;
5319 %}
5321 // Convert FPU flags into +1,0,-1
5322 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5323 src1 : E(read);
5324 src2 : E(read);
5325 dst : E(write);
5326 FA : R;
5327 MS : R(2);
5328 BR : R(2);
5329 %}
5331 // Compare for p < q, and conditionally add y
5332 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5333 p : E(read);
5334 q : E(read);
5335 y : E(read);
5336 IALU : R(3)
5337 %}
5339 // Perform a compare, then move conditionally in a branch delay slot.
5340 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5341 src2 : E(read);
5342 srcdst : E(read);
5343 IALU : R;
5344 BR : R;
5345 %}
5347 // Define the class for the Nop node
5348 define %{
5349 MachNop = ialu_nop;
5350 %}
5352 %}
5354 //----------INSTRUCTIONS-------------------------------------------------------
5356 //------------Special Stack Slot instructions - no match rules-----------------
5357 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5358 // No match rule to avoid chain rule match.
5359 effect(DEF dst, USE src);
5360 ins_cost(MEMORY_REF_COST);
5361 size(4);
5362 format %{ "LDF $src,$dst\t! stkI to regF" %}
5363 opcode(Assembler::ldf_op3);
5364 ins_encode(simple_form3_mem_reg(src, dst));
5365 ins_pipe(floadF_stk);
5366 %}
5368 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5369 // No match rule to avoid chain rule match.
5370 effect(DEF dst, USE src);
5371 ins_cost(MEMORY_REF_COST);
5372 size(4);
5373 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5374 opcode(Assembler::lddf_op3);
5375 ins_encode(simple_form3_mem_reg(src, dst));
5376 ins_pipe(floadD_stk);
5377 %}
5379 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5380 // No match rule to avoid chain rule match.
5381 effect(DEF dst, USE src);
5382 ins_cost(MEMORY_REF_COST);
5383 size(4);
5384 format %{ "STF $src,$dst\t! regF to stkI" %}
5385 opcode(Assembler::stf_op3);
5386 ins_encode(simple_form3_mem_reg(dst, src));
5387 ins_pipe(fstoreF_stk_reg);
5388 %}
5390 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5391 // No match rule to avoid chain rule match.
5392 effect(DEF dst, USE src);
5393 ins_cost(MEMORY_REF_COST);
5394 size(4);
5395 format %{ "STDF $src,$dst\t! regD to stkL" %}
5396 opcode(Assembler::stdf_op3);
5397 ins_encode(simple_form3_mem_reg(dst, src));
5398 ins_pipe(fstoreD_stk_reg);
5399 %}
5401 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5402 effect(DEF dst, USE src);
5403 ins_cost(MEMORY_REF_COST*2);
5404 size(8);
5405 format %{ "STW $src,$dst.hi\t! long\n\t"
5406 "STW R_G0,$dst.lo" %}
5407 opcode(Assembler::stw_op3);
5408 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5409 ins_pipe(lstoreI_stk_reg);
5410 %}
5412 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5413 // No match rule to avoid chain rule match.
5414 effect(DEF dst, USE src);
5415 ins_cost(MEMORY_REF_COST);
5416 size(4);
5417 format %{ "STX $src,$dst\t! regL to stkD" %}
5418 opcode(Assembler::stx_op3);
5419 ins_encode(simple_form3_mem_reg( dst, src ) );
5420 ins_pipe(istore_stk_reg);
5421 %}
5423 //---------- Chain stack slots between similar types --------
5425 // Load integer from stack slot
5426 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5427 match(Set dst src);
5428 ins_cost(MEMORY_REF_COST);
5430 size(4);
5431 format %{ "LDUW $src,$dst\t!stk" %}
5432 opcode(Assembler::lduw_op3);
5433 ins_encode(simple_form3_mem_reg( src, dst ) );
5434 ins_pipe(iload_mem);
5435 %}
5437 // Store integer to stack slot
5438 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5439 match(Set dst src);
5440 ins_cost(MEMORY_REF_COST);
5442 size(4);
5443 format %{ "STW $src,$dst\t!stk" %}
5444 opcode(Assembler::stw_op3);
5445 ins_encode(simple_form3_mem_reg( dst, src ) );
5446 ins_pipe(istore_mem_reg);
5447 %}
5449 // Load long from stack slot
5450 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5451 match(Set dst src);
5453 ins_cost(MEMORY_REF_COST);
5454 size(4);
5455 format %{ "LDX $src,$dst\t! long" %}
5456 opcode(Assembler::ldx_op3);
5457 ins_encode(simple_form3_mem_reg( src, dst ) );
5458 ins_pipe(iload_mem);
5459 %}
5461 // Store long to stack slot
5462 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5463 match(Set dst src);
5465 ins_cost(MEMORY_REF_COST);
5466 size(4);
5467 format %{ "STX $src,$dst\t! long" %}
5468 opcode(Assembler::stx_op3);
5469 ins_encode(simple_form3_mem_reg( dst, src ) );
5470 ins_pipe(istore_mem_reg);
5471 %}
5473 #ifdef _LP64
5474 // Load pointer from stack slot, 64-bit encoding
5475 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5476 match(Set dst src);
5477 ins_cost(MEMORY_REF_COST);
5478 size(4);
5479 format %{ "LDX $src,$dst\t!ptr" %}
5480 opcode(Assembler::ldx_op3);
5481 ins_encode(simple_form3_mem_reg( src, dst ) );
5482 ins_pipe(iload_mem);
5483 %}
5485 // Store pointer to stack slot
5486 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5487 match(Set dst src);
5488 ins_cost(MEMORY_REF_COST);
5489 size(4);
5490 format %{ "STX $src,$dst\t!ptr" %}
5491 opcode(Assembler::stx_op3);
5492 ins_encode(simple_form3_mem_reg( dst, src ) );
5493 ins_pipe(istore_mem_reg);
5494 %}
5495 #else // _LP64
5496 // Load pointer from stack slot, 32-bit encoding
5497 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5498 match(Set dst src);
5499 ins_cost(MEMORY_REF_COST);
5500 format %{ "LDUW $src,$dst\t!ptr" %}
5501 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5502 ins_encode(simple_form3_mem_reg( src, dst ) );
5503 ins_pipe(iload_mem);
5504 %}
5506 // Store pointer to stack slot
5507 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5508 match(Set dst src);
5509 ins_cost(MEMORY_REF_COST);
5510 format %{ "STW $src,$dst\t!ptr" %}
5511 opcode(Assembler::stw_op3, Assembler::ldst_op);
5512 ins_encode(simple_form3_mem_reg( dst, src ) );
5513 ins_pipe(istore_mem_reg);
5514 %}
5515 #endif // _LP64
5517 //------------Special Nop instructions for bundling - no match rules-----------
5518 // Nop using the A0 functional unit
5519 instruct Nop_A0() %{
5520 ins_cost(0);
5522 format %{ "NOP ! Alu Pipeline" %}
5523 opcode(Assembler::or_op3, Assembler::arith_op);
5524 ins_encode( form2_nop() );
5525 ins_pipe(ialu_nop_A0);
5526 %}
5528 // Nop using the A1 functional unit
5529 instruct Nop_A1( ) %{
5530 ins_cost(0);
5532 format %{ "NOP ! Alu Pipeline" %}
5533 opcode(Assembler::or_op3, Assembler::arith_op);
5534 ins_encode( form2_nop() );
5535 ins_pipe(ialu_nop_A1);
5536 %}
5538 // Nop using the memory functional unit
5539 instruct Nop_MS( ) %{
5540 ins_cost(0);
5542 format %{ "NOP ! Memory Pipeline" %}
5543 ins_encode( emit_mem_nop );
5544 ins_pipe(mem_nop);
5545 %}
5547 // Nop using the floating add functional unit
5548 instruct Nop_FA( ) %{
5549 ins_cost(0);
5551 format %{ "NOP ! Floating Add Pipeline" %}
5552 ins_encode( emit_fadd_nop );
5553 ins_pipe(fadd_nop);
5554 %}
5556 // Nop using the branch functional unit
5557 instruct Nop_BR( ) %{
5558 ins_cost(0);
5560 format %{ "NOP ! Branch Pipeline" %}
5561 ins_encode( emit_br_nop );
5562 ins_pipe(br_nop);
5563 %}
5565 //----------Load/Store/Move Instructions---------------------------------------
5566 //----------Load Instructions--------------------------------------------------
5567 // Load Byte (8bit signed)
5568 instruct loadB(iRegI dst, memory mem) %{
5569 match(Set dst (LoadB mem));
5570 ins_cost(MEMORY_REF_COST);
5572 size(4);
5573 format %{ "LDSB $mem,$dst\t! byte" %}
5574 ins_encode %{
5575 __ ldsb($mem$$Address, $dst$$Register);
5576 %}
5577 ins_pipe(iload_mask_mem);
5578 %}
5580 // Load Byte (8bit signed) into a Long Register
5581 instruct loadB2L(iRegL dst, memory mem) %{
5582 match(Set dst (ConvI2L (LoadB mem)));
5583 ins_cost(MEMORY_REF_COST);
5585 size(4);
5586 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5587 ins_encode %{
5588 __ ldsb($mem$$Address, $dst$$Register);
5589 %}
5590 ins_pipe(iload_mask_mem);
5591 %}
5593 // Load Unsigned Byte (8bit UNsigned) into an int reg
5594 instruct loadUB(iRegI dst, memory mem) %{
5595 match(Set dst (LoadUB mem));
5596 ins_cost(MEMORY_REF_COST);
5598 size(4);
5599 format %{ "LDUB $mem,$dst\t! ubyte" %}
5600 ins_encode %{
5601 __ ldub($mem$$Address, $dst$$Register);
5602 %}
5603 ins_pipe(iload_mem);
5604 %}
5606 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5607 instruct loadUB2L(iRegL dst, memory mem) %{
5608 match(Set dst (ConvI2L (LoadUB mem)));
5609 ins_cost(MEMORY_REF_COST);
5611 size(4);
5612 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5613 ins_encode %{
5614 __ ldub($mem$$Address, $dst$$Register);
5615 %}
5616 ins_pipe(iload_mem);
5617 %}
5619 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5620 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5621 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5622 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5624 size(2*4);
5625 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5626 "AND $dst,$mask,$dst" %}
5627 ins_encode %{
5628 __ ldub($mem$$Address, $dst$$Register);
5629 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5630 %}
5631 ins_pipe(iload_mem);
5632 %}
5634 // Load Short (16bit signed)
5635 instruct loadS(iRegI dst, memory mem) %{
5636 match(Set dst (LoadS mem));
5637 ins_cost(MEMORY_REF_COST);
5639 size(4);
5640 format %{ "LDSH $mem,$dst\t! short" %}
5641 ins_encode %{
5642 __ ldsh($mem$$Address, $dst$$Register);
5643 %}
5644 ins_pipe(iload_mask_mem);
5645 %}
5647 // Load Short (16 bit signed) to Byte (8 bit signed)
5648 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5649 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5650 ins_cost(MEMORY_REF_COST);
5652 size(4);
5654 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5655 ins_encode %{
5656 __ ldsb($mem$$Address, $dst$$Register, 1);
5657 %}
5658 ins_pipe(iload_mask_mem);
5659 %}
5661 // Load Short (16bit signed) into a Long Register
5662 instruct loadS2L(iRegL dst, memory mem) %{
5663 match(Set dst (ConvI2L (LoadS mem)));
5664 ins_cost(MEMORY_REF_COST);
5666 size(4);
5667 format %{ "LDSH $mem,$dst\t! short -> long" %}
5668 ins_encode %{
5669 __ ldsh($mem$$Address, $dst$$Register);
5670 %}
5671 ins_pipe(iload_mask_mem);
5672 %}
5674 // Load Unsigned Short/Char (16bit UNsigned)
5675 instruct loadUS(iRegI dst, memory mem) %{
5676 match(Set dst (LoadUS mem));
5677 ins_cost(MEMORY_REF_COST);
5679 size(4);
5680 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5681 ins_encode %{
5682 __ lduh($mem$$Address, $dst$$Register);
5683 %}
5684 ins_pipe(iload_mem);
5685 %}
5687 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5688 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5689 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5690 ins_cost(MEMORY_REF_COST);
5692 size(4);
5693 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5694 ins_encode %{
5695 __ ldsb($mem$$Address, $dst$$Register, 1);
5696 %}
5697 ins_pipe(iload_mask_mem);
5698 %}
5700 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5701 instruct loadUS2L(iRegL dst, memory mem) %{
5702 match(Set dst (ConvI2L (LoadUS mem)));
5703 ins_cost(MEMORY_REF_COST);
5705 size(4);
5706 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5707 ins_encode %{
5708 __ lduh($mem$$Address, $dst$$Register);
5709 %}
5710 ins_pipe(iload_mem);
5711 %}
5713 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5714 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5715 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5716 ins_cost(MEMORY_REF_COST);
5718 size(4);
5719 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5720 ins_encode %{
5721 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5722 %}
5723 ins_pipe(iload_mem);
5724 %}
5726 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5727 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5728 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5729 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5731 size(2*4);
5732 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5733 "AND $dst,$mask,$dst" %}
5734 ins_encode %{
5735 Register Rdst = $dst$$Register;
5736 __ lduh($mem$$Address, Rdst);
5737 __ and3(Rdst, $mask$$constant, Rdst);
5738 %}
5739 ins_pipe(iload_mem);
5740 %}
5742 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5743 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5744 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5745 effect(TEMP dst, TEMP tmp);
5746 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5748 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5749 "SET $mask,$tmp\n\t"
5750 "AND $dst,$tmp,$dst" %}
5751 ins_encode %{
5752 Register Rdst = $dst$$Register;
5753 Register Rtmp = $tmp$$Register;
5754 __ lduh($mem$$Address, Rdst);
5755 __ set($mask$$constant, Rtmp);
5756 __ and3(Rdst, Rtmp, Rdst);
5757 %}
5758 ins_pipe(iload_mem);
5759 %}
5761 // Load Integer
5762 instruct loadI(iRegI dst, memory mem) %{
5763 match(Set dst (LoadI mem));
5764 ins_cost(MEMORY_REF_COST);
5766 size(4);
5767 format %{ "LDUW $mem,$dst\t! int" %}
5768 ins_encode %{
5769 __ lduw($mem$$Address, $dst$$Register);
5770 %}
5771 ins_pipe(iload_mem);
5772 %}
5774 // Load Integer to Byte (8 bit signed)
5775 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5776 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5777 ins_cost(MEMORY_REF_COST);
5779 size(4);
5781 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5782 ins_encode %{
5783 __ ldsb($mem$$Address, $dst$$Register, 3);
5784 %}
5785 ins_pipe(iload_mask_mem);
5786 %}
5788 // Load Integer to Unsigned Byte (8 bit UNsigned)
5789 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5790 match(Set dst (AndI (LoadI mem) mask));
5791 ins_cost(MEMORY_REF_COST);
5793 size(4);
5795 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5796 ins_encode %{
5797 __ ldub($mem$$Address, $dst$$Register, 3);
5798 %}
5799 ins_pipe(iload_mask_mem);
5800 %}
5802 // Load Integer to Short (16 bit signed)
5803 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5804 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5805 ins_cost(MEMORY_REF_COST);
5807 size(4);
5809 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5810 ins_encode %{
5811 __ ldsh($mem$$Address, $dst$$Register, 2);
5812 %}
5813 ins_pipe(iload_mask_mem);
5814 %}
5816 // Load Integer to Unsigned Short (16 bit UNsigned)
5817 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5818 match(Set dst (AndI (LoadI mem) mask));
5819 ins_cost(MEMORY_REF_COST);
5821 size(4);
5823 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5824 ins_encode %{
5825 __ lduh($mem$$Address, $dst$$Register, 2);
5826 %}
5827 ins_pipe(iload_mask_mem);
5828 %}
5830 // Load Integer into a Long Register
5831 instruct loadI2L(iRegL dst, memory mem) %{
5832 match(Set dst (ConvI2L (LoadI mem)));
5833 ins_cost(MEMORY_REF_COST);
5835 size(4);
5836 format %{ "LDSW $mem,$dst\t! int -> long" %}
5837 ins_encode %{
5838 __ ldsw($mem$$Address, $dst$$Register);
5839 %}
5840 ins_pipe(iload_mask_mem);
5841 %}
5843 // Load Integer with mask 0xFF into a Long Register
5844 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5845 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5846 ins_cost(MEMORY_REF_COST);
5848 size(4);
5849 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5850 ins_encode %{
5851 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5852 %}
5853 ins_pipe(iload_mem);
5854 %}
5856 // Load Integer with mask 0xFFFF into a Long Register
5857 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5858 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5859 ins_cost(MEMORY_REF_COST);
5861 size(4);
5862 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5863 ins_encode %{
5864 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5865 %}
5866 ins_pipe(iload_mem);
5867 %}
5869 // Load Integer with a 12-bit mask into a Long Register
5870 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5871 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5872 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5874 size(2*4);
5875 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5876 "AND $dst,$mask,$dst" %}
5877 ins_encode %{
5878 Register Rdst = $dst$$Register;
5879 __ lduw($mem$$Address, Rdst);
5880 __ and3(Rdst, $mask$$constant, Rdst);
5881 %}
5882 ins_pipe(iload_mem);
5883 %}
5885 // Load Integer with a 31-bit mask into a Long Register
5886 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5887 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5888 effect(TEMP dst, TEMP tmp);
5889 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5891 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5892 "SET $mask,$tmp\n\t"
5893 "AND $dst,$tmp,$dst" %}
5894 ins_encode %{
5895 Register Rdst = $dst$$Register;
5896 Register Rtmp = $tmp$$Register;
5897 __ lduw($mem$$Address, Rdst);
5898 __ set($mask$$constant, Rtmp);
5899 __ and3(Rdst, Rtmp, Rdst);
5900 %}
5901 ins_pipe(iload_mem);
5902 %}
5904 // Load Unsigned Integer into a Long Register
5905 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5906 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5907 ins_cost(MEMORY_REF_COST);
5909 size(4);
5910 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5911 ins_encode %{
5912 __ lduw($mem$$Address, $dst$$Register);
5913 %}
5914 ins_pipe(iload_mem);
5915 %}
5917 // Load Long - aligned
5918 instruct loadL(iRegL dst, memory mem ) %{
5919 match(Set dst (LoadL mem));
5920 ins_cost(MEMORY_REF_COST);
5922 size(4);
5923 format %{ "LDX $mem,$dst\t! long" %}
5924 ins_encode %{
5925 __ ldx($mem$$Address, $dst$$Register);
5926 %}
5927 ins_pipe(iload_mem);
5928 %}
5930 // Load Long - UNaligned
5931 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5932 match(Set dst (LoadL_unaligned mem));
5933 effect(KILL tmp);
5934 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5935 size(16);
5936 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5937 "\tLDUW $mem ,$dst\n"
5938 "\tSLLX #32, $dst, $dst\n"
5939 "\tOR $dst, R_O7, $dst" %}
5940 opcode(Assembler::lduw_op3);
5941 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5942 ins_pipe(iload_mem);
5943 %}
5945 // Load Range
5946 instruct loadRange(iRegI dst, memory mem) %{
5947 match(Set dst (LoadRange mem));
5948 ins_cost(MEMORY_REF_COST);
5950 size(4);
5951 format %{ "LDUW $mem,$dst\t! range" %}
5952 opcode(Assembler::lduw_op3);
5953 ins_encode(simple_form3_mem_reg( mem, dst ) );
5954 ins_pipe(iload_mem);
5955 %}
5957 // Load Integer into %f register (for fitos/fitod)
5958 instruct loadI_freg(regF dst, memory mem) %{
5959 match(Set dst (LoadI mem));
5960 ins_cost(MEMORY_REF_COST);
5961 size(4);
5963 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5964 opcode(Assembler::ldf_op3);
5965 ins_encode(simple_form3_mem_reg( mem, dst ) );
5966 ins_pipe(floadF_mem);
5967 %}
5969 // Load Pointer
5970 instruct loadP(iRegP dst, memory mem) %{
5971 match(Set dst (LoadP mem));
5972 ins_cost(MEMORY_REF_COST);
5973 size(4);
5975 #ifndef _LP64
5976 format %{ "LDUW $mem,$dst\t! ptr" %}
5977 ins_encode %{
5978 __ lduw($mem$$Address, $dst$$Register);
5979 %}
5980 #else
5981 format %{ "LDX $mem,$dst\t! ptr" %}
5982 ins_encode %{
5983 __ ldx($mem$$Address, $dst$$Register);
5984 %}
5985 #endif
5986 ins_pipe(iload_mem);
5987 %}
5989 // Load Compressed Pointer
5990 instruct loadN(iRegN dst, memory mem) %{
5991 match(Set dst (LoadN mem));
5992 ins_cost(MEMORY_REF_COST);
5993 size(4);
5995 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5996 ins_encode %{
5997 __ lduw($mem$$Address, $dst$$Register);
5998 %}
5999 ins_pipe(iload_mem);
6000 %}
6002 // Load Klass Pointer
6003 instruct loadKlass(iRegP dst, memory mem) %{
6004 match(Set dst (LoadKlass mem));
6005 ins_cost(MEMORY_REF_COST);
6006 size(4);
6008 #ifndef _LP64
6009 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6010 ins_encode %{
6011 __ lduw($mem$$Address, $dst$$Register);
6012 %}
6013 #else
6014 format %{ "LDX $mem,$dst\t! klass ptr" %}
6015 ins_encode %{
6016 __ ldx($mem$$Address, $dst$$Register);
6017 %}
6018 #endif
6019 ins_pipe(iload_mem);
6020 %}
6022 // Load narrow Klass Pointer
6023 instruct loadNKlass(iRegN dst, memory mem) %{
6024 match(Set dst (LoadNKlass mem));
6025 ins_cost(MEMORY_REF_COST);
6026 size(4);
6028 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6029 ins_encode %{
6030 __ lduw($mem$$Address, $dst$$Register);
6031 %}
6032 ins_pipe(iload_mem);
6033 %}
6035 // Load Double
6036 instruct loadD(regD dst, memory mem) %{
6037 match(Set dst (LoadD mem));
6038 ins_cost(MEMORY_REF_COST);
6040 size(4);
6041 format %{ "LDDF $mem,$dst" %}
6042 opcode(Assembler::lddf_op3);
6043 ins_encode(simple_form3_mem_reg( mem, dst ) );
6044 ins_pipe(floadD_mem);
6045 %}
6047 // Load Double - UNaligned
6048 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6049 match(Set dst (LoadD_unaligned mem));
6050 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6051 size(8);
6052 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6053 "\tLDF $mem+4,$dst.lo\t!" %}
6054 opcode(Assembler::ldf_op3);
6055 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6056 ins_pipe(iload_mem);
6057 %}
6059 // Load Float
6060 instruct loadF(regF dst, memory mem) %{
6061 match(Set dst (LoadF mem));
6062 ins_cost(MEMORY_REF_COST);
6064 size(4);
6065 format %{ "LDF $mem,$dst" %}
6066 opcode(Assembler::ldf_op3);
6067 ins_encode(simple_form3_mem_reg( mem, dst ) );
6068 ins_pipe(floadF_mem);
6069 %}
6071 // Load Constant
6072 instruct loadConI( iRegI dst, immI src ) %{
6073 match(Set dst src);
6074 ins_cost(DEFAULT_COST * 3/2);
6075 format %{ "SET $src,$dst" %}
6076 ins_encode( Set32(src, dst) );
6077 ins_pipe(ialu_hi_lo_reg);
6078 %}
6080 instruct loadConI13( iRegI dst, immI13 src ) %{
6081 match(Set dst src);
6083 size(4);
6084 format %{ "MOV $src,$dst" %}
6085 ins_encode( Set13( src, dst ) );
6086 ins_pipe(ialu_imm);
6087 %}
6089 #ifndef _LP64
6090 instruct loadConP(iRegP dst, immP con) %{
6091 match(Set dst con);
6092 ins_cost(DEFAULT_COST * 3/2);
6093 format %{ "SET $con,$dst\t!ptr" %}
6094 ins_encode %{
6095 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6096 intptr_t val = $con$$constant;
6097 if (constant_reloc == relocInfo::oop_type) {
6098 __ set_oop_constant((jobject) val, $dst$$Register);
6099 } else if (constant_reloc == relocInfo::metadata_type) {
6100 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6101 } else { // non-oop pointers, e.g. card mark base, heap top
6102 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6103 __ set(val, $dst$$Register);
6104 }
6105 %}
6106 ins_pipe(loadConP);
6107 %}
6108 #else
6109 instruct loadConP_set(iRegP dst, immP_set con) %{
6110 match(Set dst con);
6111 ins_cost(DEFAULT_COST * 3/2);
6112 format %{ "SET $con,$dst\t! ptr" %}
6113 ins_encode %{
6114 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6115 intptr_t val = $con$$constant;
6116 if (constant_reloc == relocInfo::oop_type) {
6117 __ set_oop_constant((jobject) val, $dst$$Register);
6118 } else if (constant_reloc == relocInfo::metadata_type) {
6119 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6120 } else { // non-oop pointers, e.g. card mark base, heap top
6121 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6122 __ set(val, $dst$$Register);
6123 }
6124 %}
6125 ins_pipe(loadConP);
6126 %}
6128 instruct loadConP_load(iRegP dst, immP_load con) %{
6129 match(Set dst con);
6130 ins_cost(MEMORY_REF_COST);
6131 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6132 ins_encode %{
6133 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6134 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6135 %}
6136 ins_pipe(loadConP);
6137 %}
6139 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6140 match(Set dst con);
6141 ins_cost(DEFAULT_COST * 3/2);
6142 format %{ "SET $con,$dst\t! non-oop ptr" %}
6143 ins_encode %{
6144 __ set($con$$constant, $dst$$Register);
6145 %}
6146 ins_pipe(loadConP);
6147 %}
6148 #endif // _LP64
6150 instruct loadConP0(iRegP dst, immP0 src) %{
6151 match(Set dst src);
6153 size(4);
6154 format %{ "CLR $dst\t!ptr" %}
6155 ins_encode %{
6156 __ clr($dst$$Register);
6157 %}
6158 ins_pipe(ialu_imm);
6159 %}
6161 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6162 match(Set dst src);
6163 ins_cost(DEFAULT_COST);
6164 format %{ "SET $src,$dst\t!ptr" %}
6165 ins_encode %{
6166 AddressLiteral polling_page(os::get_polling_page());
6167 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6168 %}
6169 ins_pipe(loadConP_poll);
6170 %}
6172 instruct loadConN0(iRegN dst, immN0 src) %{
6173 match(Set dst src);
6175 size(4);
6176 format %{ "CLR $dst\t! compressed NULL ptr" %}
6177 ins_encode %{
6178 __ clr($dst$$Register);
6179 %}
6180 ins_pipe(ialu_imm);
6181 %}
6183 instruct loadConN(iRegN dst, immN src) %{
6184 match(Set dst src);
6185 ins_cost(DEFAULT_COST * 3/2);
6186 format %{ "SET $src,$dst\t! compressed ptr" %}
6187 ins_encode %{
6188 Register dst = $dst$$Register;
6189 __ set_narrow_oop((jobject)$src$$constant, dst);
6190 %}
6191 ins_pipe(ialu_hi_lo_reg);
6192 %}
6194 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6195 match(Set dst src);
6196 ins_cost(DEFAULT_COST * 3/2);
6197 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6198 ins_encode %{
6199 Register dst = $dst$$Register;
6200 __ set_narrow_klass((Klass*)$src$$constant, dst);
6201 %}
6202 ins_pipe(ialu_hi_lo_reg);
6203 %}
6205 // Materialize long value (predicated by immL_cheap).
6206 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6207 match(Set dst con);
6208 effect(KILL tmp);
6209 ins_cost(DEFAULT_COST * 3);
6210 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6211 ins_encode %{
6212 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6213 %}
6214 ins_pipe(loadConL);
6215 %}
6217 // Load long value from constant table (predicated by immL_expensive).
6218 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6219 match(Set dst con);
6220 ins_cost(MEMORY_REF_COST);
6221 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6222 ins_encode %{
6223 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6224 __ ldx($constanttablebase, con_offset, $dst$$Register);
6225 %}
6226 ins_pipe(loadConL);
6227 %}
6229 instruct loadConL0( iRegL dst, immL0 src ) %{
6230 match(Set dst src);
6231 ins_cost(DEFAULT_COST);
6232 size(4);
6233 format %{ "CLR $dst\t! long" %}
6234 ins_encode( Set13( src, dst ) );
6235 ins_pipe(ialu_imm);
6236 %}
6238 instruct loadConL13( iRegL dst, immL13 src ) %{
6239 match(Set dst src);
6240 ins_cost(DEFAULT_COST * 2);
6242 size(4);
6243 format %{ "MOV $src,$dst\t! long" %}
6244 ins_encode( Set13( src, dst ) );
6245 ins_pipe(ialu_imm);
6246 %}
6248 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6249 match(Set dst con);
6250 effect(KILL tmp);
6251 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6252 ins_encode %{
6253 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6254 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6255 %}
6256 ins_pipe(loadConFD);
6257 %}
6259 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6260 match(Set dst con);
6261 effect(KILL tmp);
6262 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6263 ins_encode %{
6264 // XXX This is a quick fix for 6833573.
6265 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6266 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6267 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6268 %}
6269 ins_pipe(loadConFD);
6270 %}
6272 // Prefetch instructions.
6273 // Must be safe to execute with invalid address (cannot fault).
6275 instruct prefetchr( memory mem ) %{
6276 match( PrefetchRead mem );
6277 ins_cost(MEMORY_REF_COST);
6278 size(4);
6280 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6281 opcode(Assembler::prefetch_op3);
6282 ins_encode( form3_mem_prefetch_read( mem ) );
6283 ins_pipe(iload_mem);
6284 %}
6286 instruct prefetchw( memory mem ) %{
6287 match( PrefetchWrite mem );
6288 ins_cost(MEMORY_REF_COST);
6289 size(4);
6291 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6292 opcode(Assembler::prefetch_op3);
6293 ins_encode( form3_mem_prefetch_write( mem ) );
6294 ins_pipe(iload_mem);
6295 %}
6297 // Prefetch instructions for allocation.
6299 instruct prefetchAlloc( memory mem ) %{
6300 predicate(AllocatePrefetchInstr == 0);
6301 match( PrefetchAllocation mem );
6302 ins_cost(MEMORY_REF_COST);
6303 size(4);
6305 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6306 opcode(Assembler::prefetch_op3);
6307 ins_encode( form3_mem_prefetch_write( mem ) );
6308 ins_pipe(iload_mem);
6309 %}
6311 // Use BIS instruction to prefetch for allocation.
6312 // Could fault, need space at the end of TLAB.
6313 instruct prefetchAlloc_bis( iRegP dst ) %{
6314 predicate(AllocatePrefetchInstr == 1);
6315 match( PrefetchAllocation dst );
6316 ins_cost(MEMORY_REF_COST);
6317 size(4);
6319 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6320 ins_encode %{
6321 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6322 %}
6323 ins_pipe(istore_mem_reg);
6324 %}
6326 // Next code is used for finding next cache line address to prefetch.
6327 #ifndef _LP64
6328 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6329 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6330 ins_cost(DEFAULT_COST);
6331 size(4);
6333 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6334 ins_encode %{
6335 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6336 %}
6337 ins_pipe(ialu_reg_imm);
6338 %}
6339 #else
6340 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6341 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6342 ins_cost(DEFAULT_COST);
6343 size(4);
6345 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6346 ins_encode %{
6347 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6348 %}
6349 ins_pipe(ialu_reg_imm);
6350 %}
6351 #endif
6353 //----------Store Instructions-------------------------------------------------
6354 // Store Byte
6355 instruct storeB(memory mem, iRegI src) %{
6356 match(Set mem (StoreB mem src));
6357 ins_cost(MEMORY_REF_COST);
6359 size(4);
6360 format %{ "STB $src,$mem\t! byte" %}
6361 opcode(Assembler::stb_op3);
6362 ins_encode(simple_form3_mem_reg( mem, src ) );
6363 ins_pipe(istore_mem_reg);
6364 %}
6366 instruct storeB0(memory mem, immI0 src) %{
6367 match(Set mem (StoreB mem src));
6368 ins_cost(MEMORY_REF_COST);
6370 size(4);
6371 format %{ "STB $src,$mem\t! byte" %}
6372 opcode(Assembler::stb_op3);
6373 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6374 ins_pipe(istore_mem_zero);
6375 %}
6377 instruct storeCM0(memory mem, immI0 src) %{
6378 match(Set mem (StoreCM mem src));
6379 ins_cost(MEMORY_REF_COST);
6381 size(4);
6382 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6383 opcode(Assembler::stb_op3);
6384 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6385 ins_pipe(istore_mem_zero);
6386 %}
6388 // Store Char/Short
6389 instruct storeC(memory mem, iRegI src) %{
6390 match(Set mem (StoreC mem src));
6391 ins_cost(MEMORY_REF_COST);
6393 size(4);
6394 format %{ "STH $src,$mem\t! short" %}
6395 opcode(Assembler::sth_op3);
6396 ins_encode(simple_form3_mem_reg( mem, src ) );
6397 ins_pipe(istore_mem_reg);
6398 %}
6400 instruct storeC0(memory mem, immI0 src) %{
6401 match(Set mem (StoreC mem src));
6402 ins_cost(MEMORY_REF_COST);
6404 size(4);
6405 format %{ "STH $src,$mem\t! short" %}
6406 opcode(Assembler::sth_op3);
6407 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6408 ins_pipe(istore_mem_zero);
6409 %}
6411 // Store Integer
6412 instruct storeI(memory mem, iRegI src) %{
6413 match(Set mem (StoreI mem src));
6414 ins_cost(MEMORY_REF_COST);
6416 size(4);
6417 format %{ "STW $src,$mem" %}
6418 opcode(Assembler::stw_op3);
6419 ins_encode(simple_form3_mem_reg( mem, src ) );
6420 ins_pipe(istore_mem_reg);
6421 %}
6423 // Store Long
6424 instruct storeL(memory mem, iRegL src) %{
6425 match(Set mem (StoreL mem src));
6426 ins_cost(MEMORY_REF_COST);
6427 size(4);
6428 format %{ "STX $src,$mem\t! long" %}
6429 opcode(Assembler::stx_op3);
6430 ins_encode(simple_form3_mem_reg( mem, src ) );
6431 ins_pipe(istore_mem_reg);
6432 %}
6434 instruct storeI0(memory mem, immI0 src) %{
6435 match(Set mem (StoreI mem src));
6436 ins_cost(MEMORY_REF_COST);
6438 size(4);
6439 format %{ "STW $src,$mem" %}
6440 opcode(Assembler::stw_op3);
6441 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6442 ins_pipe(istore_mem_zero);
6443 %}
6445 instruct storeL0(memory mem, immL0 src) %{
6446 match(Set mem (StoreL mem src));
6447 ins_cost(MEMORY_REF_COST);
6449 size(4);
6450 format %{ "STX $src,$mem" %}
6451 opcode(Assembler::stx_op3);
6452 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6453 ins_pipe(istore_mem_zero);
6454 %}
6456 // Store Integer from float register (used after fstoi)
6457 instruct storeI_Freg(memory mem, regF src) %{
6458 match(Set mem (StoreI mem src));
6459 ins_cost(MEMORY_REF_COST);
6461 size(4);
6462 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6463 opcode(Assembler::stf_op3);
6464 ins_encode(simple_form3_mem_reg( mem, src ) );
6465 ins_pipe(fstoreF_mem_reg);
6466 %}
6468 // Store Pointer
6469 instruct storeP(memory dst, sp_ptr_RegP src) %{
6470 match(Set dst (StoreP dst src));
6471 ins_cost(MEMORY_REF_COST);
6472 size(4);
6474 #ifndef _LP64
6475 format %{ "STW $src,$dst\t! ptr" %}
6476 opcode(Assembler::stw_op3, 0, REGP_OP);
6477 #else
6478 format %{ "STX $src,$dst\t! ptr" %}
6479 opcode(Assembler::stx_op3, 0, REGP_OP);
6480 #endif
6481 ins_encode( form3_mem_reg( dst, src ) );
6482 ins_pipe(istore_mem_spORreg);
6483 %}
6485 instruct storeP0(memory dst, immP0 src) %{
6486 match(Set dst (StoreP dst src));
6487 ins_cost(MEMORY_REF_COST);
6488 size(4);
6490 #ifndef _LP64
6491 format %{ "STW $src,$dst\t! ptr" %}
6492 opcode(Assembler::stw_op3, 0, REGP_OP);
6493 #else
6494 format %{ "STX $src,$dst\t! ptr" %}
6495 opcode(Assembler::stx_op3, 0, REGP_OP);
6496 #endif
6497 ins_encode( form3_mem_reg( dst, R_G0 ) );
6498 ins_pipe(istore_mem_zero);
6499 %}
6501 // Store Compressed Pointer
6502 instruct storeN(memory dst, iRegN src) %{
6503 match(Set dst (StoreN dst src));
6504 ins_cost(MEMORY_REF_COST);
6505 size(4);
6507 format %{ "STW $src,$dst\t! compressed ptr" %}
6508 ins_encode %{
6509 Register base = as_Register($dst$$base);
6510 Register index = as_Register($dst$$index);
6511 Register src = $src$$Register;
6512 if (index != G0) {
6513 __ stw(src, base, index);
6514 } else {
6515 __ stw(src, base, $dst$$disp);
6516 }
6517 %}
6518 ins_pipe(istore_mem_spORreg);
6519 %}
6521 instruct storeNKlass(memory dst, iRegN src) %{
6522 match(Set dst (StoreNKlass dst src));
6523 ins_cost(MEMORY_REF_COST);
6524 size(4);
6526 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6527 ins_encode %{
6528 Register base = as_Register($dst$$base);
6529 Register index = as_Register($dst$$index);
6530 Register src = $src$$Register;
6531 if (index != G0) {
6532 __ stw(src, base, index);
6533 } else {
6534 __ stw(src, base, $dst$$disp);
6535 }
6536 %}
6537 ins_pipe(istore_mem_spORreg);
6538 %}
6540 instruct storeN0(memory dst, immN0 src) %{
6541 match(Set dst (StoreN dst src));
6542 ins_cost(MEMORY_REF_COST);
6543 size(4);
6545 format %{ "STW $src,$dst\t! compressed ptr" %}
6546 ins_encode %{
6547 Register base = as_Register($dst$$base);
6548 Register index = as_Register($dst$$index);
6549 if (index != G0) {
6550 __ stw(0, base, index);
6551 } else {
6552 __ stw(0, base, $dst$$disp);
6553 }
6554 %}
6555 ins_pipe(istore_mem_zero);
6556 %}
6558 // Store Double
6559 instruct storeD( memory mem, regD src) %{
6560 match(Set mem (StoreD mem src));
6561 ins_cost(MEMORY_REF_COST);
6563 size(4);
6564 format %{ "STDF $src,$mem" %}
6565 opcode(Assembler::stdf_op3);
6566 ins_encode(simple_form3_mem_reg( mem, src ) );
6567 ins_pipe(fstoreD_mem_reg);
6568 %}
6570 instruct storeD0( memory mem, immD0 src) %{
6571 match(Set mem (StoreD mem src));
6572 ins_cost(MEMORY_REF_COST);
6574 size(4);
6575 format %{ "STX $src,$mem" %}
6576 opcode(Assembler::stx_op3);
6577 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6578 ins_pipe(fstoreD_mem_zero);
6579 %}
6581 // Store Float
6582 instruct storeF( memory mem, regF src) %{
6583 match(Set mem (StoreF mem src));
6584 ins_cost(MEMORY_REF_COST);
6586 size(4);
6587 format %{ "STF $src,$mem" %}
6588 opcode(Assembler::stf_op3);
6589 ins_encode(simple_form3_mem_reg( mem, src ) );
6590 ins_pipe(fstoreF_mem_reg);
6591 %}
6593 instruct storeF0( memory mem, immF0 src) %{
6594 match(Set mem (StoreF mem src));
6595 ins_cost(MEMORY_REF_COST);
6597 size(4);
6598 format %{ "STW $src,$mem\t! storeF0" %}
6599 opcode(Assembler::stw_op3);
6600 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6601 ins_pipe(fstoreF_mem_zero);
6602 %}
6604 // Convert oop pointer into compressed form
6605 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6606 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6607 match(Set dst (EncodeP src));
6608 format %{ "encode_heap_oop $src, $dst" %}
6609 ins_encode %{
6610 __ encode_heap_oop($src$$Register, $dst$$Register);
6611 %}
6612 ins_pipe(ialu_reg);
6613 %}
6615 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6616 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6617 match(Set dst (EncodeP src));
6618 format %{ "encode_heap_oop_not_null $src, $dst" %}
6619 ins_encode %{
6620 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6621 %}
6622 ins_pipe(ialu_reg);
6623 %}
6625 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6626 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6627 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6628 match(Set dst (DecodeN src));
6629 format %{ "decode_heap_oop $src, $dst" %}
6630 ins_encode %{
6631 __ decode_heap_oop($src$$Register, $dst$$Register);
6632 %}
6633 ins_pipe(ialu_reg);
6634 %}
6636 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6637 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6638 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6639 match(Set dst (DecodeN src));
6640 format %{ "decode_heap_oop_not_null $src, $dst" %}
6641 ins_encode %{
6642 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6643 %}
6644 ins_pipe(ialu_reg);
6645 %}
6647 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6648 match(Set dst (EncodePKlass src));
6649 format %{ "encode_klass_not_null $src, $dst" %}
6650 ins_encode %{
6651 __ encode_klass_not_null($src$$Register, $dst$$Register);
6652 %}
6653 ins_pipe(ialu_reg);
6654 %}
6656 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6657 match(Set dst (DecodeNKlass src));
6658 format %{ "decode_klass_not_null $src, $dst" %}
6659 ins_encode %{
6660 __ decode_klass_not_null($src$$Register, $dst$$Register);
6661 %}
6662 ins_pipe(ialu_reg);
6663 %}
6665 //----------MemBar Instructions-----------------------------------------------
6666 // Memory barrier flavors
6668 instruct membar_acquire() %{
6669 match(MemBarAcquire);
6670 match(LoadFence);
6671 ins_cost(4*MEMORY_REF_COST);
6673 size(0);
6674 format %{ "MEMBAR-acquire" %}
6675 ins_encode( enc_membar_acquire );
6676 ins_pipe(long_memory_op);
6677 %}
6679 instruct membar_acquire_lock() %{
6680 match(MemBarAcquireLock);
6681 ins_cost(0);
6683 size(0);
6684 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6685 ins_encode( );
6686 ins_pipe(empty);
6687 %}
6689 instruct membar_release() %{
6690 match(MemBarRelease);
6691 match(StoreFence);
6692 ins_cost(4*MEMORY_REF_COST);
6694 size(0);
6695 format %{ "MEMBAR-release" %}
6696 ins_encode( enc_membar_release );
6697 ins_pipe(long_memory_op);
6698 %}
6700 instruct membar_release_lock() %{
6701 match(MemBarReleaseLock);
6702 ins_cost(0);
6704 size(0);
6705 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6706 ins_encode( );
6707 ins_pipe(empty);
6708 %}
6710 instruct membar_volatile() %{
6711 match(MemBarVolatile);
6712 ins_cost(4*MEMORY_REF_COST);
6714 size(4);
6715 format %{ "MEMBAR-volatile" %}
6716 ins_encode( enc_membar_volatile );
6717 ins_pipe(long_memory_op);
6718 %}
6720 instruct unnecessary_membar_volatile() %{
6721 match(MemBarVolatile);
6722 predicate(Matcher::post_store_load_barrier(n));
6723 ins_cost(0);
6725 size(0);
6726 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6727 ins_encode( );
6728 ins_pipe(empty);
6729 %}
6731 instruct membar_storestore() %{
6732 match(MemBarStoreStore);
6733 ins_cost(0);
6735 size(0);
6736 format %{ "!MEMBAR-storestore (empty encoding)" %}
6737 ins_encode( );
6738 ins_pipe(empty);
6739 %}
6741 //----------Register Move Instructions-----------------------------------------
6742 instruct roundDouble_nop(regD dst) %{
6743 match(Set dst (RoundDouble dst));
6744 ins_cost(0);
6745 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6746 ins_encode( );
6747 ins_pipe(empty);
6748 %}
6751 instruct roundFloat_nop(regF dst) %{
6752 match(Set dst (RoundFloat dst));
6753 ins_cost(0);
6754 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6755 ins_encode( );
6756 ins_pipe(empty);
6757 %}
6760 // Cast Index to Pointer for unsafe natives
6761 instruct castX2P(iRegX src, iRegP dst) %{
6762 match(Set dst (CastX2P src));
6764 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6765 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6766 ins_pipe(ialu_reg);
6767 %}
6769 // Cast Pointer to Index for unsafe natives
6770 instruct castP2X(iRegP src, iRegX dst) %{
6771 match(Set dst (CastP2X src));
6773 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6774 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6775 ins_pipe(ialu_reg);
6776 %}
6778 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6779 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6780 match(Set stkSlot src); // chain rule
6781 ins_cost(MEMORY_REF_COST);
6782 format %{ "STDF $src,$stkSlot\t!stk" %}
6783 opcode(Assembler::stdf_op3);
6784 ins_encode(simple_form3_mem_reg(stkSlot, src));
6785 ins_pipe(fstoreD_stk_reg);
6786 %}
6788 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6789 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6790 match(Set dst stkSlot); // chain rule
6791 ins_cost(MEMORY_REF_COST);
6792 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6793 opcode(Assembler::lddf_op3);
6794 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6795 ins_pipe(floadD_stk);
6796 %}
6798 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6799 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6800 match(Set stkSlot src); // chain rule
6801 ins_cost(MEMORY_REF_COST);
6802 format %{ "STF $src,$stkSlot\t!stk" %}
6803 opcode(Assembler::stf_op3);
6804 ins_encode(simple_form3_mem_reg(stkSlot, src));
6805 ins_pipe(fstoreF_stk_reg);
6806 %}
6808 //----------Conditional Move---------------------------------------------------
6809 // Conditional move
6810 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6811 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6812 ins_cost(150);
6813 format %{ "MOV$cmp $pcc,$src,$dst" %}
6814 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6815 ins_pipe(ialu_reg);
6816 %}
6818 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6819 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6820 ins_cost(140);
6821 format %{ "MOV$cmp $pcc,$src,$dst" %}
6822 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6823 ins_pipe(ialu_imm);
6824 %}
6826 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6827 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6828 ins_cost(150);
6829 size(4);
6830 format %{ "MOV$cmp $icc,$src,$dst" %}
6831 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6832 ins_pipe(ialu_reg);
6833 %}
6835 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6836 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6837 ins_cost(140);
6838 size(4);
6839 format %{ "MOV$cmp $icc,$src,$dst" %}
6840 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6841 ins_pipe(ialu_imm);
6842 %}
6844 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6845 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6846 ins_cost(150);
6847 size(4);
6848 format %{ "MOV$cmp $icc,$src,$dst" %}
6849 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6850 ins_pipe(ialu_reg);
6851 %}
6853 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6854 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6855 ins_cost(140);
6856 size(4);
6857 format %{ "MOV$cmp $icc,$src,$dst" %}
6858 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6859 ins_pipe(ialu_imm);
6860 %}
6862 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6863 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6864 ins_cost(150);
6865 size(4);
6866 format %{ "MOV$cmp $fcc,$src,$dst" %}
6867 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6868 ins_pipe(ialu_reg);
6869 %}
6871 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6872 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6873 ins_cost(140);
6874 size(4);
6875 format %{ "MOV$cmp $fcc,$src,$dst" %}
6876 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6877 ins_pipe(ialu_imm);
6878 %}
6880 // Conditional move for RegN. Only cmov(reg,reg).
6881 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6882 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6883 ins_cost(150);
6884 format %{ "MOV$cmp $pcc,$src,$dst" %}
6885 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6886 ins_pipe(ialu_reg);
6887 %}
6889 // This instruction also works with CmpN so we don't need cmovNN_reg.
6890 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6891 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6892 ins_cost(150);
6893 size(4);
6894 format %{ "MOV$cmp $icc,$src,$dst" %}
6895 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6896 ins_pipe(ialu_reg);
6897 %}
6899 // This instruction also works with CmpN so we don't need cmovNN_reg.
6900 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6901 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6902 ins_cost(150);
6903 size(4);
6904 format %{ "MOV$cmp $icc,$src,$dst" %}
6905 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6906 ins_pipe(ialu_reg);
6907 %}
6909 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6910 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6911 ins_cost(150);
6912 size(4);
6913 format %{ "MOV$cmp $fcc,$src,$dst" %}
6914 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6915 ins_pipe(ialu_reg);
6916 %}
6918 // Conditional move
6919 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6920 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6921 ins_cost(150);
6922 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6923 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6924 ins_pipe(ialu_reg);
6925 %}
6927 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6928 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6929 ins_cost(140);
6930 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6931 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6932 ins_pipe(ialu_imm);
6933 %}
6935 // This instruction also works with CmpN so we don't need cmovPN_reg.
6936 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6937 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6938 ins_cost(150);
6940 size(4);
6941 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6942 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6943 ins_pipe(ialu_reg);
6944 %}
6946 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6947 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6948 ins_cost(150);
6950 size(4);
6951 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6952 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6953 ins_pipe(ialu_reg);
6954 %}
6956 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6957 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6958 ins_cost(140);
6960 size(4);
6961 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6962 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6963 ins_pipe(ialu_imm);
6964 %}
6966 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6967 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6968 ins_cost(140);
6970 size(4);
6971 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6972 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6973 ins_pipe(ialu_imm);
6974 %}
6976 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6977 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6978 ins_cost(150);
6979 size(4);
6980 format %{ "MOV$cmp $fcc,$src,$dst" %}
6981 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6982 ins_pipe(ialu_imm);
6983 %}
6985 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6986 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6987 ins_cost(140);
6988 size(4);
6989 format %{ "MOV$cmp $fcc,$src,$dst" %}
6990 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6991 ins_pipe(ialu_imm);
6992 %}
6994 // Conditional move
6995 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6996 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6997 ins_cost(150);
6998 opcode(0x101);
6999 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7000 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7001 ins_pipe(int_conditional_float_move);
7002 %}
7004 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7005 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7006 ins_cost(150);
7008 size(4);
7009 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7010 opcode(0x101);
7011 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7012 ins_pipe(int_conditional_float_move);
7013 %}
7015 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7016 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7017 ins_cost(150);
7019 size(4);
7020 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7021 opcode(0x101);
7022 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7023 ins_pipe(int_conditional_float_move);
7024 %}
7026 // Conditional move,
7027 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7028 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7029 ins_cost(150);
7030 size(4);
7031 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7032 opcode(0x1);
7033 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7034 ins_pipe(int_conditional_double_move);
7035 %}
7037 // Conditional move
7038 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7039 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7040 ins_cost(150);
7041 size(4);
7042 opcode(0x102);
7043 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7044 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7045 ins_pipe(int_conditional_double_move);
7046 %}
7048 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7049 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7050 ins_cost(150);
7052 size(4);
7053 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7054 opcode(0x102);
7055 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7056 ins_pipe(int_conditional_double_move);
7057 %}
7059 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7060 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7061 ins_cost(150);
7063 size(4);
7064 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7065 opcode(0x102);
7066 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7067 ins_pipe(int_conditional_double_move);
7068 %}
7070 // Conditional move,
7071 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7072 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7073 ins_cost(150);
7074 size(4);
7075 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7076 opcode(0x2);
7077 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7078 ins_pipe(int_conditional_double_move);
7079 %}
7081 // Conditional move
7082 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7083 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7084 ins_cost(150);
7085 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7086 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7087 ins_pipe(ialu_reg);
7088 %}
7090 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7091 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7092 ins_cost(140);
7093 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7094 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7095 ins_pipe(ialu_imm);
7096 %}
7098 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7099 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7100 ins_cost(150);
7102 size(4);
7103 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7104 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7105 ins_pipe(ialu_reg);
7106 %}
7109 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7110 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7111 ins_cost(150);
7113 size(4);
7114 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7115 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7116 ins_pipe(ialu_reg);
7117 %}
7120 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7121 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7122 ins_cost(150);
7124 size(4);
7125 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7126 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7127 ins_pipe(ialu_reg);
7128 %}
7132 //----------OS and Locking Instructions----------------------------------------
7134 // This name is KNOWN by the ADLC and cannot be changed.
7135 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7136 // for this guy.
7137 instruct tlsLoadP(g2RegP dst) %{
7138 match(Set dst (ThreadLocal));
7140 size(0);
7141 ins_cost(0);
7142 format %{ "# TLS is in G2" %}
7143 ins_encode( /*empty encoding*/ );
7144 ins_pipe(ialu_none);
7145 %}
7147 instruct checkCastPP( iRegP dst ) %{
7148 match(Set dst (CheckCastPP dst));
7150 size(0);
7151 format %{ "# checkcastPP of $dst" %}
7152 ins_encode( /*empty encoding*/ );
7153 ins_pipe(empty);
7154 %}
7157 instruct castPP( iRegP dst ) %{
7158 match(Set dst (CastPP dst));
7159 format %{ "# castPP of $dst" %}
7160 ins_encode( /*empty encoding*/ );
7161 ins_pipe(empty);
7162 %}
7164 instruct castII( iRegI dst ) %{
7165 match(Set dst (CastII dst));
7166 format %{ "# castII of $dst" %}
7167 ins_encode( /*empty encoding*/ );
7168 ins_cost(0);
7169 ins_pipe(empty);
7170 %}
7172 //----------Arithmetic Instructions--------------------------------------------
7173 // Addition Instructions
7174 // Register Addition
7175 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7176 match(Set dst (AddI src1 src2));
7178 size(4);
7179 format %{ "ADD $src1,$src2,$dst" %}
7180 ins_encode %{
7181 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7182 %}
7183 ins_pipe(ialu_reg_reg);
7184 %}
7186 // Immediate Addition
7187 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7188 match(Set dst (AddI src1 src2));
7190 size(4);
7191 format %{ "ADD $src1,$src2,$dst" %}
7192 opcode(Assembler::add_op3, Assembler::arith_op);
7193 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7194 ins_pipe(ialu_reg_imm);
7195 %}
7197 // Pointer Register Addition
7198 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7199 match(Set dst (AddP src1 src2));
7201 size(4);
7202 format %{ "ADD $src1,$src2,$dst" %}
7203 opcode(Assembler::add_op3, Assembler::arith_op);
7204 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7205 ins_pipe(ialu_reg_reg);
7206 %}
7208 // Pointer Immediate Addition
7209 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7210 match(Set dst (AddP src1 src2));
7212 size(4);
7213 format %{ "ADD $src1,$src2,$dst" %}
7214 opcode(Assembler::add_op3, Assembler::arith_op);
7215 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7216 ins_pipe(ialu_reg_imm);
7217 %}
7219 // Long Addition
7220 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7221 match(Set dst (AddL src1 src2));
7223 size(4);
7224 format %{ "ADD $src1,$src2,$dst\t! long" %}
7225 opcode(Assembler::add_op3, Assembler::arith_op);
7226 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7227 ins_pipe(ialu_reg_reg);
7228 %}
7230 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7231 match(Set dst (AddL src1 con));
7233 size(4);
7234 format %{ "ADD $src1,$con,$dst" %}
7235 opcode(Assembler::add_op3, Assembler::arith_op);
7236 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7237 ins_pipe(ialu_reg_imm);
7238 %}
7240 //----------Conditional_store--------------------------------------------------
7241 // Conditional-store of the updated heap-top.
7242 // Used during allocation of the shared heap.
7243 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7245 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7246 instruct loadPLocked(iRegP dst, memory mem) %{
7247 match(Set dst (LoadPLocked mem));
7248 ins_cost(MEMORY_REF_COST);
7250 #ifndef _LP64
7251 size(4);
7252 format %{ "LDUW $mem,$dst\t! ptr" %}
7253 opcode(Assembler::lduw_op3, 0, REGP_OP);
7254 #else
7255 format %{ "LDX $mem,$dst\t! ptr" %}
7256 opcode(Assembler::ldx_op3, 0, REGP_OP);
7257 #endif
7258 ins_encode( form3_mem_reg( mem, dst ) );
7259 ins_pipe(iload_mem);
7260 %}
7262 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7263 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7264 effect( KILL newval );
7265 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7266 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7267 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7268 ins_pipe( long_memory_op );
7269 %}
7271 // Conditional-store of an int value.
7272 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7273 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7274 effect( KILL newval );
7275 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7276 "CMP $oldval,$newval\t\t! See if we made progress" %}
7277 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7278 ins_pipe( long_memory_op );
7279 %}
7281 // Conditional-store of a long value.
7282 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7283 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7284 effect( KILL newval );
7285 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7286 "CMP $oldval,$newval\t\t! See if we made progress" %}
7287 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7288 ins_pipe( long_memory_op );
7289 %}
7291 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7293 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7294 predicate(VM_Version::supports_cx8());
7295 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7296 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7297 format %{
7298 "MOV $newval,O7\n\t"
7299 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7300 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7301 "MOV 1,$res\n\t"
7302 "MOVne xcc,R_G0,$res"
7303 %}
7304 ins_encode( enc_casx(mem_ptr, oldval, newval),
7305 enc_lflags_ne_to_boolean(res) );
7306 ins_pipe( long_memory_op );
7307 %}
7310 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7311 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7312 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7313 format %{
7314 "MOV $newval,O7\n\t"
7315 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7316 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7317 "MOV 1,$res\n\t"
7318 "MOVne icc,R_G0,$res"
7319 %}
7320 ins_encode( enc_casi(mem_ptr, oldval, newval),
7321 enc_iflags_ne_to_boolean(res) );
7322 ins_pipe( long_memory_op );
7323 %}
7325 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7326 #ifdef _LP64
7327 predicate(VM_Version::supports_cx8());
7328 #endif
7329 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7330 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7331 format %{
7332 "MOV $newval,O7\n\t"
7333 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7334 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7335 "MOV 1,$res\n\t"
7336 "MOVne xcc,R_G0,$res"
7337 %}
7338 #ifdef _LP64
7339 ins_encode( enc_casx(mem_ptr, oldval, newval),
7340 enc_lflags_ne_to_boolean(res) );
7341 #else
7342 ins_encode( enc_casi(mem_ptr, oldval, newval),
7343 enc_iflags_ne_to_boolean(res) );
7344 #endif
7345 ins_pipe( long_memory_op );
7346 %}
7348 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7349 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7350 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7351 format %{
7352 "MOV $newval,O7\n\t"
7353 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7354 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7355 "MOV 1,$res\n\t"
7356 "MOVne icc,R_G0,$res"
7357 %}
7358 ins_encode( enc_casi(mem_ptr, oldval, newval),
7359 enc_iflags_ne_to_boolean(res) );
7360 ins_pipe( long_memory_op );
7361 %}
7363 instruct xchgI( memory mem, iRegI newval) %{
7364 match(Set newval (GetAndSetI mem newval));
7365 format %{ "SWAP [$mem],$newval" %}
7366 size(4);
7367 ins_encode %{
7368 __ swap($mem$$Address, $newval$$Register);
7369 %}
7370 ins_pipe( long_memory_op );
7371 %}
7373 #ifndef _LP64
7374 instruct xchgP( memory mem, iRegP newval) %{
7375 match(Set newval (GetAndSetP mem newval));
7376 format %{ "SWAP [$mem],$newval" %}
7377 size(4);
7378 ins_encode %{
7379 __ swap($mem$$Address, $newval$$Register);
7380 %}
7381 ins_pipe( long_memory_op );
7382 %}
7383 #endif
7385 instruct xchgN( memory mem, iRegN newval) %{
7386 match(Set newval (GetAndSetN mem newval));
7387 format %{ "SWAP [$mem],$newval" %}
7388 size(4);
7389 ins_encode %{
7390 __ swap($mem$$Address, $newval$$Register);
7391 %}
7392 ins_pipe( long_memory_op );
7393 %}
7395 //---------------------
7396 // Subtraction Instructions
7397 // Register Subtraction
7398 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7399 match(Set dst (SubI src1 src2));
7401 size(4);
7402 format %{ "SUB $src1,$src2,$dst" %}
7403 opcode(Assembler::sub_op3, Assembler::arith_op);
7404 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7405 ins_pipe(ialu_reg_reg);
7406 %}
7408 // Immediate Subtraction
7409 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7410 match(Set dst (SubI src1 src2));
7412 size(4);
7413 format %{ "SUB $src1,$src2,$dst" %}
7414 opcode(Assembler::sub_op3, Assembler::arith_op);
7415 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7416 ins_pipe(ialu_reg_imm);
7417 %}
7419 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7420 match(Set dst (SubI zero src2));
7422 size(4);
7423 format %{ "NEG $src2,$dst" %}
7424 opcode(Assembler::sub_op3, Assembler::arith_op);
7425 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7426 ins_pipe(ialu_zero_reg);
7427 %}
7429 // Long subtraction
7430 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7431 match(Set dst (SubL src1 src2));
7433 size(4);
7434 format %{ "SUB $src1,$src2,$dst\t! long" %}
7435 opcode(Assembler::sub_op3, Assembler::arith_op);
7436 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7437 ins_pipe(ialu_reg_reg);
7438 %}
7440 // Immediate Subtraction
7441 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7442 match(Set dst (SubL src1 con));
7444 size(4);
7445 format %{ "SUB $src1,$con,$dst\t! long" %}
7446 opcode(Assembler::sub_op3, Assembler::arith_op);
7447 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7448 ins_pipe(ialu_reg_imm);
7449 %}
7451 // Long negation
7452 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7453 match(Set dst (SubL zero src2));
7455 size(4);
7456 format %{ "NEG $src2,$dst\t! long" %}
7457 opcode(Assembler::sub_op3, Assembler::arith_op);
7458 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7459 ins_pipe(ialu_zero_reg);
7460 %}
7462 // Multiplication Instructions
7463 // Integer Multiplication
7464 // Register Multiplication
7465 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7466 match(Set dst (MulI src1 src2));
7468 size(4);
7469 format %{ "MULX $src1,$src2,$dst" %}
7470 opcode(Assembler::mulx_op3, Assembler::arith_op);
7471 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7472 ins_pipe(imul_reg_reg);
7473 %}
7475 // Immediate Multiplication
7476 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7477 match(Set dst (MulI src1 src2));
7479 size(4);
7480 format %{ "MULX $src1,$src2,$dst" %}
7481 opcode(Assembler::mulx_op3, Assembler::arith_op);
7482 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7483 ins_pipe(imul_reg_imm);
7484 %}
7486 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7487 match(Set dst (MulL src1 src2));
7488 ins_cost(DEFAULT_COST * 5);
7489 size(4);
7490 format %{ "MULX $src1,$src2,$dst\t! long" %}
7491 opcode(Assembler::mulx_op3, Assembler::arith_op);
7492 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7493 ins_pipe(mulL_reg_reg);
7494 %}
7496 // Immediate Multiplication
7497 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7498 match(Set dst (MulL src1 src2));
7499 ins_cost(DEFAULT_COST * 5);
7500 size(4);
7501 format %{ "MULX $src1,$src2,$dst" %}
7502 opcode(Assembler::mulx_op3, Assembler::arith_op);
7503 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7504 ins_pipe(mulL_reg_imm);
7505 %}
7507 // Integer Division
7508 // Register Division
7509 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7510 match(Set dst (DivI src1 src2));
7511 ins_cost((2+71)*DEFAULT_COST);
7513 format %{ "SRA $src2,0,$src2\n\t"
7514 "SRA $src1,0,$src1\n\t"
7515 "SDIVX $src1,$src2,$dst" %}
7516 ins_encode( idiv_reg( src1, src2, dst ) );
7517 ins_pipe(sdiv_reg_reg);
7518 %}
7520 // Immediate Division
7521 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7522 match(Set dst (DivI src1 src2));
7523 ins_cost((2+71)*DEFAULT_COST);
7525 format %{ "SRA $src1,0,$src1\n\t"
7526 "SDIVX $src1,$src2,$dst" %}
7527 ins_encode( idiv_imm( src1, src2, dst ) );
7528 ins_pipe(sdiv_reg_imm);
7529 %}
7531 //----------Div-By-10-Expansion------------------------------------------------
7532 // Extract hi bits of a 32x32->64 bit multiply.
7533 // Expand rule only, not matched
7534 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7535 effect( DEF dst, USE src1, USE src2 );
7536 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7537 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7538 ins_encode( enc_mul_hi(dst,src1,src2));
7539 ins_pipe(sdiv_reg_reg);
7540 %}
7542 // Magic constant, reciprocal of 10
7543 instruct loadConI_x66666667(iRegIsafe dst) %{
7544 effect( DEF dst );
7546 size(8);
7547 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7548 ins_encode( Set32(0x66666667, dst) );
7549 ins_pipe(ialu_hi_lo_reg);
7550 %}
7552 // Register Shift Right Arithmetic Long by 32-63
7553 instruct sra_31( iRegI dst, iRegI src ) %{
7554 effect( DEF dst, USE src );
7555 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7556 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7557 ins_pipe(ialu_reg_reg);
7558 %}
7560 // Arithmetic Shift Right by 8-bit immediate
7561 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7562 effect( DEF dst, USE src );
7563 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7564 opcode(Assembler::sra_op3, Assembler::arith_op);
7565 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7566 ins_pipe(ialu_reg_imm);
7567 %}
7569 // Integer DIV with 10
7570 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7571 match(Set dst (DivI src div));
7572 ins_cost((6+6)*DEFAULT_COST);
7573 expand %{
7574 iRegIsafe tmp1; // Killed temps;
7575 iRegIsafe tmp2; // Killed temps;
7576 iRegI tmp3; // Killed temps;
7577 iRegI tmp4; // Killed temps;
7578 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7579 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7580 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7581 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7582 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7583 %}
7584 %}
7586 // Register Long Division
7587 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7588 match(Set dst (DivL src1 src2));
7589 ins_cost(DEFAULT_COST*71);
7590 size(4);
7591 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7592 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7593 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7594 ins_pipe(divL_reg_reg);
7595 %}
7597 // Register Long Division
7598 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7599 match(Set dst (DivL src1 src2));
7600 ins_cost(DEFAULT_COST*71);
7601 size(4);
7602 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7603 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7604 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7605 ins_pipe(divL_reg_imm);
7606 %}
7608 // Integer Remainder
7609 // Register Remainder
7610 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7611 match(Set dst (ModI src1 src2));
7612 effect( KILL ccr, KILL temp);
7614 format %{ "SREM $src1,$src2,$dst" %}
7615 ins_encode( irem_reg(src1, src2, dst, temp) );
7616 ins_pipe(sdiv_reg_reg);
7617 %}
7619 // Immediate Remainder
7620 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7621 match(Set dst (ModI src1 src2));
7622 effect( KILL ccr, KILL temp);
7624 format %{ "SREM $src1,$src2,$dst" %}
7625 ins_encode( irem_imm(src1, src2, dst, temp) );
7626 ins_pipe(sdiv_reg_imm);
7627 %}
7629 // Register Long Remainder
7630 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7631 effect(DEF dst, USE src1, USE src2);
7632 size(4);
7633 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7634 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7635 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7636 ins_pipe(divL_reg_reg);
7637 %}
7639 // Register Long Division
7640 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7641 effect(DEF dst, USE src1, USE src2);
7642 size(4);
7643 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7644 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7645 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7646 ins_pipe(divL_reg_imm);
7647 %}
7649 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7650 effect(DEF dst, USE src1, USE src2);
7651 size(4);
7652 format %{ "MULX $src1,$src2,$dst\t! long" %}
7653 opcode(Assembler::mulx_op3, Assembler::arith_op);
7654 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7655 ins_pipe(mulL_reg_reg);
7656 %}
7658 // Immediate Multiplication
7659 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7660 effect(DEF dst, USE src1, USE src2);
7661 size(4);
7662 format %{ "MULX $src1,$src2,$dst" %}
7663 opcode(Assembler::mulx_op3, Assembler::arith_op);
7664 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7665 ins_pipe(mulL_reg_imm);
7666 %}
7668 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7669 effect(DEF dst, USE src1, USE src2);
7670 size(4);
7671 format %{ "SUB $src1,$src2,$dst\t! long" %}
7672 opcode(Assembler::sub_op3, Assembler::arith_op);
7673 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7674 ins_pipe(ialu_reg_reg);
7675 %}
7677 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7678 effect(DEF dst, USE src1, USE src2);
7679 size(4);
7680 format %{ "SUB $src1,$src2,$dst\t! long" %}
7681 opcode(Assembler::sub_op3, Assembler::arith_op);
7682 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7683 ins_pipe(ialu_reg_reg);
7684 %}
7686 // Register Long Remainder
7687 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7688 match(Set dst (ModL src1 src2));
7689 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7690 expand %{
7691 iRegL tmp1;
7692 iRegL tmp2;
7693 divL_reg_reg_1(tmp1, src1, src2);
7694 mulL_reg_reg_1(tmp2, tmp1, src2);
7695 subL_reg_reg_1(dst, src1, tmp2);
7696 %}
7697 %}
7699 // Register Long Remainder
7700 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7701 match(Set dst (ModL src1 src2));
7702 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7703 expand %{
7704 iRegL tmp1;
7705 iRegL tmp2;
7706 divL_reg_imm13_1(tmp1, src1, src2);
7707 mulL_reg_imm13_1(tmp2, tmp1, src2);
7708 subL_reg_reg_2 (dst, src1, tmp2);
7709 %}
7710 %}
7712 // Integer Shift Instructions
7713 // Register Shift Left
7714 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7715 match(Set dst (LShiftI src1 src2));
7717 size(4);
7718 format %{ "SLL $src1,$src2,$dst" %}
7719 opcode(Assembler::sll_op3, Assembler::arith_op);
7720 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7721 ins_pipe(ialu_reg_reg);
7722 %}
7724 // Register Shift Left Immediate
7725 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7726 match(Set dst (LShiftI src1 src2));
7728 size(4);
7729 format %{ "SLL $src1,$src2,$dst" %}
7730 opcode(Assembler::sll_op3, Assembler::arith_op);
7731 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7732 ins_pipe(ialu_reg_imm);
7733 %}
7735 // Register Shift Left
7736 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7737 match(Set dst (LShiftL src1 src2));
7739 size(4);
7740 format %{ "SLLX $src1,$src2,$dst" %}
7741 opcode(Assembler::sllx_op3, Assembler::arith_op);
7742 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7743 ins_pipe(ialu_reg_reg);
7744 %}
7746 // Register Shift Left Immediate
7747 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7748 match(Set dst (LShiftL src1 src2));
7750 size(4);
7751 format %{ "SLLX $src1,$src2,$dst" %}
7752 opcode(Assembler::sllx_op3, Assembler::arith_op);
7753 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7754 ins_pipe(ialu_reg_imm);
7755 %}
7757 // Register Arithmetic Shift Right
7758 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7759 match(Set dst (RShiftI src1 src2));
7760 size(4);
7761 format %{ "SRA $src1,$src2,$dst" %}
7762 opcode(Assembler::sra_op3, Assembler::arith_op);
7763 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7764 ins_pipe(ialu_reg_reg);
7765 %}
7767 // Register Arithmetic Shift Right Immediate
7768 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7769 match(Set dst (RShiftI src1 src2));
7771 size(4);
7772 format %{ "SRA $src1,$src2,$dst" %}
7773 opcode(Assembler::sra_op3, Assembler::arith_op);
7774 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7775 ins_pipe(ialu_reg_imm);
7776 %}
7778 // Register Shift Right Arithmatic Long
7779 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7780 match(Set dst (RShiftL src1 src2));
7782 size(4);
7783 format %{ "SRAX $src1,$src2,$dst" %}
7784 opcode(Assembler::srax_op3, Assembler::arith_op);
7785 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7786 ins_pipe(ialu_reg_reg);
7787 %}
7789 // Register Shift Left Immediate
7790 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7791 match(Set dst (RShiftL src1 src2));
7793 size(4);
7794 format %{ "SRAX $src1,$src2,$dst" %}
7795 opcode(Assembler::srax_op3, Assembler::arith_op);
7796 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7797 ins_pipe(ialu_reg_imm);
7798 %}
7800 // Register Shift Right
7801 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7802 match(Set dst (URShiftI src1 src2));
7804 size(4);
7805 format %{ "SRL $src1,$src2,$dst" %}
7806 opcode(Assembler::srl_op3, Assembler::arith_op);
7807 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7808 ins_pipe(ialu_reg_reg);
7809 %}
7811 // Register Shift Right Immediate
7812 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7813 match(Set dst (URShiftI src1 src2));
7815 size(4);
7816 format %{ "SRL $src1,$src2,$dst" %}
7817 opcode(Assembler::srl_op3, Assembler::arith_op);
7818 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7819 ins_pipe(ialu_reg_imm);
7820 %}
7822 // Register Shift Right
7823 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7824 match(Set dst (URShiftL src1 src2));
7826 size(4);
7827 format %{ "SRLX $src1,$src2,$dst" %}
7828 opcode(Assembler::srlx_op3, Assembler::arith_op);
7829 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7830 ins_pipe(ialu_reg_reg);
7831 %}
7833 // Register Shift Right Immediate
7834 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7835 match(Set dst (URShiftL src1 src2));
7837 size(4);
7838 format %{ "SRLX $src1,$src2,$dst" %}
7839 opcode(Assembler::srlx_op3, Assembler::arith_op);
7840 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7841 ins_pipe(ialu_reg_imm);
7842 %}
7844 // Register Shift Right Immediate with a CastP2X
7845 #ifdef _LP64
7846 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7847 match(Set dst (URShiftL (CastP2X src1) src2));
7848 size(4);
7849 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7850 opcode(Assembler::srlx_op3, Assembler::arith_op);
7851 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7852 ins_pipe(ialu_reg_imm);
7853 %}
7854 #else
7855 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7856 match(Set dst (URShiftI (CastP2X src1) src2));
7857 size(4);
7858 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7859 opcode(Assembler::srl_op3, Assembler::arith_op);
7860 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7861 ins_pipe(ialu_reg_imm);
7862 %}
7863 #endif
7866 //----------Floating Point Arithmetic Instructions-----------------------------
7868 // Add float single precision
7869 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7870 match(Set dst (AddF src1 src2));
7872 size(4);
7873 format %{ "FADDS $src1,$src2,$dst" %}
7874 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7875 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7876 ins_pipe(faddF_reg_reg);
7877 %}
7879 // Add float double precision
7880 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7881 match(Set dst (AddD src1 src2));
7883 size(4);
7884 format %{ "FADDD $src1,$src2,$dst" %}
7885 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7886 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7887 ins_pipe(faddD_reg_reg);
7888 %}
7890 // Sub float single precision
7891 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7892 match(Set dst (SubF src1 src2));
7894 size(4);
7895 format %{ "FSUBS $src1,$src2,$dst" %}
7896 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7897 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7898 ins_pipe(faddF_reg_reg);
7899 %}
7901 // Sub float double precision
7902 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7903 match(Set dst (SubD src1 src2));
7905 size(4);
7906 format %{ "FSUBD $src1,$src2,$dst" %}
7907 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7908 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7909 ins_pipe(faddD_reg_reg);
7910 %}
7912 // Mul float single precision
7913 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7914 match(Set dst (MulF src1 src2));
7916 size(4);
7917 format %{ "FMULS $src1,$src2,$dst" %}
7918 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7919 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7920 ins_pipe(fmulF_reg_reg);
7921 %}
7923 // Mul float double precision
7924 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7925 match(Set dst (MulD src1 src2));
7927 size(4);
7928 format %{ "FMULD $src1,$src2,$dst" %}
7929 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7930 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7931 ins_pipe(fmulD_reg_reg);
7932 %}
7934 // Div float single precision
7935 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7936 match(Set dst (DivF src1 src2));
7938 size(4);
7939 format %{ "FDIVS $src1,$src2,$dst" %}
7940 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7941 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7942 ins_pipe(fdivF_reg_reg);
7943 %}
7945 // Div float double precision
7946 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7947 match(Set dst (DivD src1 src2));
7949 size(4);
7950 format %{ "FDIVD $src1,$src2,$dst" %}
7951 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7952 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7953 ins_pipe(fdivD_reg_reg);
7954 %}
7956 // Absolute float double precision
7957 instruct absD_reg(regD dst, regD src) %{
7958 match(Set dst (AbsD src));
7960 format %{ "FABSd $src,$dst" %}
7961 ins_encode(fabsd(dst, src));
7962 ins_pipe(faddD_reg);
7963 %}
7965 // Absolute float single precision
7966 instruct absF_reg(regF dst, regF src) %{
7967 match(Set dst (AbsF src));
7969 format %{ "FABSs $src,$dst" %}
7970 ins_encode(fabss(dst, src));
7971 ins_pipe(faddF_reg);
7972 %}
7974 instruct negF_reg(regF dst, regF src) %{
7975 match(Set dst (NegF src));
7977 size(4);
7978 format %{ "FNEGs $src,$dst" %}
7979 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7980 ins_encode(form3_opf_rs2F_rdF(src, dst));
7981 ins_pipe(faddF_reg);
7982 %}
7984 instruct negD_reg(regD dst, regD src) %{
7985 match(Set dst (NegD src));
7987 format %{ "FNEGd $src,$dst" %}
7988 ins_encode(fnegd(dst, src));
7989 ins_pipe(faddD_reg);
7990 %}
7992 // Sqrt float double precision
7993 instruct sqrtF_reg_reg(regF dst, regF src) %{
7994 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7996 size(4);
7997 format %{ "FSQRTS $src,$dst" %}
7998 ins_encode(fsqrts(dst, src));
7999 ins_pipe(fdivF_reg_reg);
8000 %}
8002 // Sqrt float double precision
8003 instruct sqrtD_reg_reg(regD dst, regD src) %{
8004 match(Set dst (SqrtD src));
8006 size(4);
8007 format %{ "FSQRTD $src,$dst" %}
8008 ins_encode(fsqrtd(dst, src));
8009 ins_pipe(fdivD_reg_reg);
8010 %}
8012 //----------Logical Instructions-----------------------------------------------
8013 // And Instructions
8014 // Register And
8015 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8016 match(Set dst (AndI src1 src2));
8018 size(4);
8019 format %{ "AND $src1,$src2,$dst" %}
8020 opcode(Assembler::and_op3, Assembler::arith_op);
8021 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8022 ins_pipe(ialu_reg_reg);
8023 %}
8025 // Immediate And
8026 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8027 match(Set dst (AndI src1 src2));
8029 size(4);
8030 format %{ "AND $src1,$src2,$dst" %}
8031 opcode(Assembler::and_op3, Assembler::arith_op);
8032 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8033 ins_pipe(ialu_reg_imm);
8034 %}
8036 // Register And Long
8037 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8038 match(Set dst (AndL src1 src2));
8040 ins_cost(DEFAULT_COST);
8041 size(4);
8042 format %{ "AND $src1,$src2,$dst\t! long" %}
8043 opcode(Assembler::and_op3, Assembler::arith_op);
8044 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8045 ins_pipe(ialu_reg_reg);
8046 %}
8048 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8049 match(Set dst (AndL src1 con));
8051 ins_cost(DEFAULT_COST);
8052 size(4);
8053 format %{ "AND $src1,$con,$dst\t! long" %}
8054 opcode(Assembler::and_op3, Assembler::arith_op);
8055 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8056 ins_pipe(ialu_reg_imm);
8057 %}
8059 // Or Instructions
8060 // Register Or
8061 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8062 match(Set dst (OrI src1 src2));
8064 size(4);
8065 format %{ "OR $src1,$src2,$dst" %}
8066 opcode(Assembler::or_op3, Assembler::arith_op);
8067 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8068 ins_pipe(ialu_reg_reg);
8069 %}
8071 // Immediate Or
8072 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8073 match(Set dst (OrI src1 src2));
8075 size(4);
8076 format %{ "OR $src1,$src2,$dst" %}
8077 opcode(Assembler::or_op3, Assembler::arith_op);
8078 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8079 ins_pipe(ialu_reg_imm);
8080 %}
8082 // Register Or Long
8083 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8084 match(Set dst (OrL src1 src2));
8086 ins_cost(DEFAULT_COST);
8087 size(4);
8088 format %{ "OR $src1,$src2,$dst\t! long" %}
8089 opcode(Assembler::or_op3, Assembler::arith_op);
8090 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8091 ins_pipe(ialu_reg_reg);
8092 %}
8094 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8095 match(Set dst (OrL src1 con));
8096 ins_cost(DEFAULT_COST*2);
8098 ins_cost(DEFAULT_COST);
8099 size(4);
8100 format %{ "OR $src1,$con,$dst\t! long" %}
8101 opcode(Assembler::or_op3, Assembler::arith_op);
8102 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8103 ins_pipe(ialu_reg_imm);
8104 %}
8106 #ifndef _LP64
8108 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8109 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8110 match(Set dst (OrI src1 (CastP2X src2)));
8112 size(4);
8113 format %{ "OR $src1,$src2,$dst" %}
8114 opcode(Assembler::or_op3, Assembler::arith_op);
8115 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8116 ins_pipe(ialu_reg_reg);
8117 %}
8119 #else
8121 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8122 match(Set dst (OrL src1 (CastP2X src2)));
8124 ins_cost(DEFAULT_COST);
8125 size(4);
8126 format %{ "OR $src1,$src2,$dst\t! long" %}
8127 opcode(Assembler::or_op3, Assembler::arith_op);
8128 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8129 ins_pipe(ialu_reg_reg);
8130 %}
8132 #endif
8134 // Xor Instructions
8135 // Register Xor
8136 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8137 match(Set dst (XorI src1 src2));
8139 size(4);
8140 format %{ "XOR $src1,$src2,$dst" %}
8141 opcode(Assembler::xor_op3, Assembler::arith_op);
8142 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8143 ins_pipe(ialu_reg_reg);
8144 %}
8146 // Immediate Xor
8147 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8148 match(Set dst (XorI src1 src2));
8150 size(4);
8151 format %{ "XOR $src1,$src2,$dst" %}
8152 opcode(Assembler::xor_op3, Assembler::arith_op);
8153 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8154 ins_pipe(ialu_reg_imm);
8155 %}
8157 // Register Xor Long
8158 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8159 match(Set dst (XorL src1 src2));
8161 ins_cost(DEFAULT_COST);
8162 size(4);
8163 format %{ "XOR $src1,$src2,$dst\t! long" %}
8164 opcode(Assembler::xor_op3, Assembler::arith_op);
8165 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8166 ins_pipe(ialu_reg_reg);
8167 %}
8169 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8170 match(Set dst (XorL src1 con));
8172 ins_cost(DEFAULT_COST);
8173 size(4);
8174 format %{ "XOR $src1,$con,$dst\t! long" %}
8175 opcode(Assembler::xor_op3, Assembler::arith_op);
8176 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8177 ins_pipe(ialu_reg_imm);
8178 %}
8180 //----------Convert to Boolean-------------------------------------------------
8181 // Nice hack for 32-bit tests but doesn't work for
8182 // 64-bit pointers.
8183 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8184 match(Set dst (Conv2B src));
8185 effect( KILL ccr );
8186 ins_cost(DEFAULT_COST*2);
8187 format %{ "CMP R_G0,$src\n\t"
8188 "ADDX R_G0,0,$dst" %}
8189 ins_encode( enc_to_bool( src, dst ) );
8190 ins_pipe(ialu_reg_ialu);
8191 %}
8193 #ifndef _LP64
8194 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8195 match(Set dst (Conv2B src));
8196 effect( KILL ccr );
8197 ins_cost(DEFAULT_COST*2);
8198 format %{ "CMP R_G0,$src\n\t"
8199 "ADDX R_G0,0,$dst" %}
8200 ins_encode( enc_to_bool( src, dst ) );
8201 ins_pipe(ialu_reg_ialu);
8202 %}
8203 #else
8204 instruct convP2B( iRegI dst, iRegP src ) %{
8205 match(Set dst (Conv2B src));
8206 ins_cost(DEFAULT_COST*2);
8207 format %{ "MOV $src,$dst\n\t"
8208 "MOVRNZ $src,1,$dst" %}
8209 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8210 ins_pipe(ialu_clr_and_mover);
8211 %}
8212 #endif
8214 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8215 match(Set dst (CmpLTMask src zero));
8216 effect(KILL ccr);
8217 size(4);
8218 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8219 ins_encode %{
8220 __ sra($src$$Register, 31, $dst$$Register);
8221 %}
8222 ins_pipe(ialu_reg_imm);
8223 %}
8225 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8226 match(Set dst (CmpLTMask p q));
8227 effect( KILL ccr );
8228 ins_cost(DEFAULT_COST*4);
8229 format %{ "CMP $p,$q\n\t"
8230 "MOV #0,$dst\n\t"
8231 "BLT,a .+8\n\t"
8232 "MOV #-1,$dst" %}
8233 ins_encode( enc_ltmask(p,q,dst) );
8234 ins_pipe(ialu_reg_reg_ialu);
8235 %}
8237 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8238 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8239 effect(KILL ccr, TEMP tmp);
8240 ins_cost(DEFAULT_COST*3);
8242 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8243 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8244 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8245 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8246 ins_pipe(cadd_cmpltmask);
8247 %}
8249 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8250 match(Set p (AndI (CmpLTMask p q) y));
8251 effect(KILL ccr);
8252 ins_cost(DEFAULT_COST*3);
8254 format %{ "CMP $p,$q\n\t"
8255 "MOV $y,$p\n\t"
8256 "MOVge G0,$p" %}
8257 ins_encode %{
8258 __ cmp($p$$Register, $q$$Register);
8259 __ mov($y$$Register, $p$$Register);
8260 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8261 %}
8262 ins_pipe(ialu_reg_reg_ialu);
8263 %}
8265 //-----------------------------------------------------------------
8266 // Direct raw moves between float and general registers using VIS3.
8268 // ins_pipe(faddF_reg);
8269 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8270 predicate(UseVIS >= 3);
8271 match(Set dst (MoveF2I src));
8273 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8274 ins_encode %{
8275 __ movstouw($src$$FloatRegister, $dst$$Register);
8276 %}
8277 ins_pipe(ialu_reg_reg);
8278 %}
8280 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8281 predicate(UseVIS >= 3);
8282 match(Set dst (MoveI2F src));
8284 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8285 ins_encode %{
8286 __ movwtos($src$$Register, $dst$$FloatRegister);
8287 %}
8288 ins_pipe(ialu_reg_reg);
8289 %}
8291 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8292 predicate(UseVIS >= 3);
8293 match(Set dst (MoveD2L src));
8295 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8296 ins_encode %{
8297 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8298 %}
8299 ins_pipe(ialu_reg_reg);
8300 %}
8302 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8303 predicate(UseVIS >= 3);
8304 match(Set dst (MoveL2D src));
8306 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8307 ins_encode %{
8308 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8309 %}
8310 ins_pipe(ialu_reg_reg);
8311 %}
8314 // Raw moves between float and general registers using stack.
8316 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8317 match(Set dst (MoveF2I src));
8318 effect(DEF dst, USE src);
8319 ins_cost(MEMORY_REF_COST);
8321 size(4);
8322 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8323 opcode(Assembler::lduw_op3);
8324 ins_encode(simple_form3_mem_reg( src, dst ) );
8325 ins_pipe(iload_mem);
8326 %}
8328 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8329 match(Set dst (MoveI2F src));
8330 effect(DEF dst, USE src);
8331 ins_cost(MEMORY_REF_COST);
8333 size(4);
8334 format %{ "LDF $src,$dst\t! MoveI2F" %}
8335 opcode(Assembler::ldf_op3);
8336 ins_encode(simple_form3_mem_reg(src, dst));
8337 ins_pipe(floadF_stk);
8338 %}
8340 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8341 match(Set dst (MoveD2L src));
8342 effect(DEF dst, USE src);
8343 ins_cost(MEMORY_REF_COST);
8345 size(4);
8346 format %{ "LDX $src,$dst\t! MoveD2L" %}
8347 opcode(Assembler::ldx_op3);
8348 ins_encode(simple_form3_mem_reg( src, dst ) );
8349 ins_pipe(iload_mem);
8350 %}
8352 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8353 match(Set dst (MoveL2D src));
8354 effect(DEF dst, USE src);
8355 ins_cost(MEMORY_REF_COST);
8357 size(4);
8358 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8359 opcode(Assembler::lddf_op3);
8360 ins_encode(simple_form3_mem_reg(src, dst));
8361 ins_pipe(floadD_stk);
8362 %}
8364 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8365 match(Set dst (MoveF2I src));
8366 effect(DEF dst, USE src);
8367 ins_cost(MEMORY_REF_COST);
8369 size(4);
8370 format %{ "STF $src,$dst\t! MoveF2I" %}
8371 opcode(Assembler::stf_op3);
8372 ins_encode(simple_form3_mem_reg(dst, src));
8373 ins_pipe(fstoreF_stk_reg);
8374 %}
8376 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8377 match(Set dst (MoveI2F src));
8378 effect(DEF dst, USE src);
8379 ins_cost(MEMORY_REF_COST);
8381 size(4);
8382 format %{ "STW $src,$dst\t! MoveI2F" %}
8383 opcode(Assembler::stw_op3);
8384 ins_encode(simple_form3_mem_reg( dst, src ) );
8385 ins_pipe(istore_mem_reg);
8386 %}
8388 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8389 match(Set dst (MoveD2L src));
8390 effect(DEF dst, USE src);
8391 ins_cost(MEMORY_REF_COST);
8393 size(4);
8394 format %{ "STDF $src,$dst\t! MoveD2L" %}
8395 opcode(Assembler::stdf_op3);
8396 ins_encode(simple_form3_mem_reg(dst, src));
8397 ins_pipe(fstoreD_stk_reg);
8398 %}
8400 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8401 match(Set dst (MoveL2D src));
8402 effect(DEF dst, USE src);
8403 ins_cost(MEMORY_REF_COST);
8405 size(4);
8406 format %{ "STX $src,$dst\t! MoveL2D" %}
8407 opcode(Assembler::stx_op3);
8408 ins_encode(simple_form3_mem_reg( dst, src ) );
8409 ins_pipe(istore_mem_reg);
8410 %}
8413 //----------Arithmetic Conversion Instructions---------------------------------
8414 // The conversions operations are all Alpha sorted. Please keep it that way!
8416 instruct convD2F_reg(regF dst, regD src) %{
8417 match(Set dst (ConvD2F src));
8418 size(4);
8419 format %{ "FDTOS $src,$dst" %}
8420 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8421 ins_encode(form3_opf_rs2D_rdF(src, dst));
8422 ins_pipe(fcvtD2F);
8423 %}
8426 // Convert a double to an int in a float register.
8427 // If the double is a NAN, stuff a zero in instead.
8428 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8429 effect(DEF dst, USE src, KILL fcc0);
8430 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8431 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8432 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8433 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8434 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8435 "skip:" %}
8436 ins_encode(form_d2i_helper(src,dst));
8437 ins_pipe(fcvtD2I);
8438 %}
8440 instruct convD2I_stk(stackSlotI dst, regD src) %{
8441 match(Set dst (ConvD2I src));
8442 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8443 expand %{
8444 regF tmp;
8445 convD2I_helper(tmp, src);
8446 regF_to_stkI(dst, tmp);
8447 %}
8448 %}
8450 instruct convD2I_reg(iRegI dst, regD src) %{
8451 predicate(UseVIS >= 3);
8452 match(Set dst (ConvD2I src));
8453 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8454 expand %{
8455 regF tmp;
8456 convD2I_helper(tmp, src);
8457 MoveF2I_reg_reg(dst, tmp);
8458 %}
8459 %}
8462 // Convert a double to a long in a double register.
8463 // If the double is a NAN, stuff a zero in instead.
8464 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8465 effect(DEF dst, USE src, KILL fcc0);
8466 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8467 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8468 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8469 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8470 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8471 "skip:" %}
8472 ins_encode(form_d2l_helper(src,dst));
8473 ins_pipe(fcvtD2L);
8474 %}
8476 instruct convD2L_stk(stackSlotL dst, regD src) %{
8477 match(Set dst (ConvD2L src));
8478 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8479 expand %{
8480 regD tmp;
8481 convD2L_helper(tmp, src);
8482 regD_to_stkL(dst, tmp);
8483 %}
8484 %}
8486 instruct convD2L_reg(iRegL dst, regD src) %{
8487 predicate(UseVIS >= 3);
8488 match(Set dst (ConvD2L src));
8489 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8490 expand %{
8491 regD tmp;
8492 convD2L_helper(tmp, src);
8493 MoveD2L_reg_reg(dst, tmp);
8494 %}
8495 %}
8498 instruct convF2D_reg(regD dst, regF src) %{
8499 match(Set dst (ConvF2D src));
8500 format %{ "FSTOD $src,$dst" %}
8501 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8502 ins_encode(form3_opf_rs2F_rdD(src, dst));
8503 ins_pipe(fcvtF2D);
8504 %}
8507 // Convert a float to an int in a float register.
8508 // If the float is a NAN, stuff a zero in instead.
8509 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8510 effect(DEF dst, USE src, KILL fcc0);
8511 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8512 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8513 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8514 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8515 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8516 "skip:" %}
8517 ins_encode(form_f2i_helper(src,dst));
8518 ins_pipe(fcvtF2I);
8519 %}
8521 instruct convF2I_stk(stackSlotI dst, regF src) %{
8522 match(Set dst (ConvF2I src));
8523 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8524 expand %{
8525 regF tmp;
8526 convF2I_helper(tmp, src);
8527 regF_to_stkI(dst, tmp);
8528 %}
8529 %}
8531 instruct convF2I_reg(iRegI dst, regF src) %{
8532 predicate(UseVIS >= 3);
8533 match(Set dst (ConvF2I src));
8534 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8535 expand %{
8536 regF tmp;
8537 convF2I_helper(tmp, src);
8538 MoveF2I_reg_reg(dst, tmp);
8539 %}
8540 %}
8543 // Convert a float to a long in a float register.
8544 // If the float is a NAN, stuff a zero in instead.
8545 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8546 effect(DEF dst, USE src, KILL fcc0);
8547 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8548 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8549 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8550 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8551 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8552 "skip:" %}
8553 ins_encode(form_f2l_helper(src,dst));
8554 ins_pipe(fcvtF2L);
8555 %}
8557 instruct convF2L_stk(stackSlotL dst, regF src) %{
8558 match(Set dst (ConvF2L src));
8559 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8560 expand %{
8561 regD tmp;
8562 convF2L_helper(tmp, src);
8563 regD_to_stkL(dst, tmp);
8564 %}
8565 %}
8567 instruct convF2L_reg(iRegL dst, regF src) %{
8568 predicate(UseVIS >= 3);
8569 match(Set dst (ConvF2L src));
8570 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8571 expand %{
8572 regD tmp;
8573 convF2L_helper(tmp, src);
8574 MoveD2L_reg_reg(dst, tmp);
8575 %}
8576 %}
8579 instruct convI2D_helper(regD dst, regF tmp) %{
8580 effect(USE tmp, DEF dst);
8581 format %{ "FITOD $tmp,$dst" %}
8582 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8583 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8584 ins_pipe(fcvtI2D);
8585 %}
8587 instruct convI2D_stk(stackSlotI src, regD dst) %{
8588 match(Set dst (ConvI2D src));
8589 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8590 expand %{
8591 regF tmp;
8592 stkI_to_regF(tmp, src);
8593 convI2D_helper(dst, tmp);
8594 %}
8595 %}
8597 instruct convI2D_reg(regD_low dst, iRegI src) %{
8598 predicate(UseVIS >= 3);
8599 match(Set dst (ConvI2D src));
8600 expand %{
8601 regF tmp;
8602 MoveI2F_reg_reg(tmp, src);
8603 convI2D_helper(dst, tmp);
8604 %}
8605 %}
8607 instruct convI2D_mem(regD_low dst, memory mem) %{
8608 match(Set dst (ConvI2D (LoadI mem)));
8609 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8610 size(8);
8611 format %{ "LDF $mem,$dst\n\t"
8612 "FITOD $dst,$dst" %}
8613 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8614 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8615 ins_pipe(floadF_mem);
8616 %}
8619 instruct convI2F_helper(regF dst, regF tmp) %{
8620 effect(DEF dst, USE tmp);
8621 format %{ "FITOS $tmp,$dst" %}
8622 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8623 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8624 ins_pipe(fcvtI2F);
8625 %}
8627 instruct convI2F_stk(regF dst, stackSlotI src) %{
8628 match(Set dst (ConvI2F src));
8629 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8630 expand %{
8631 regF tmp;
8632 stkI_to_regF(tmp,src);
8633 convI2F_helper(dst, tmp);
8634 %}
8635 %}
8637 instruct convI2F_reg(regF dst, iRegI src) %{
8638 predicate(UseVIS >= 3);
8639 match(Set dst (ConvI2F src));
8640 ins_cost(DEFAULT_COST);
8641 expand %{
8642 regF tmp;
8643 MoveI2F_reg_reg(tmp, src);
8644 convI2F_helper(dst, tmp);
8645 %}
8646 %}
8648 instruct convI2F_mem( regF dst, memory mem ) %{
8649 match(Set dst (ConvI2F (LoadI mem)));
8650 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8651 size(8);
8652 format %{ "LDF $mem,$dst\n\t"
8653 "FITOS $dst,$dst" %}
8654 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8655 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8656 ins_pipe(floadF_mem);
8657 %}
8660 instruct convI2L_reg(iRegL dst, iRegI src) %{
8661 match(Set dst (ConvI2L src));
8662 size(4);
8663 format %{ "SRA $src,0,$dst\t! int->long" %}
8664 opcode(Assembler::sra_op3, Assembler::arith_op);
8665 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8666 ins_pipe(ialu_reg_reg);
8667 %}
8669 // Zero-extend convert int to long
8670 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8671 match(Set dst (AndL (ConvI2L src) mask) );
8672 size(4);
8673 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8674 opcode(Assembler::srl_op3, Assembler::arith_op);
8675 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8676 ins_pipe(ialu_reg_reg);
8677 %}
8679 // Zero-extend long
8680 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8681 match(Set dst (AndL src mask) );
8682 size(4);
8683 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8684 opcode(Assembler::srl_op3, Assembler::arith_op);
8685 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8686 ins_pipe(ialu_reg_reg);
8687 %}
8690 //-----------
8691 // Long to Double conversion using V8 opcodes.
8692 // Still useful because cheetah traps and becomes
8693 // amazingly slow for some common numbers.
8695 // Magic constant, 0x43300000
8696 instruct loadConI_x43300000(iRegI dst) %{
8697 effect(DEF dst);
8698 size(4);
8699 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8700 ins_encode(SetHi22(0x43300000, dst));
8701 ins_pipe(ialu_none);
8702 %}
8704 // Magic constant, 0x41f00000
8705 instruct loadConI_x41f00000(iRegI dst) %{
8706 effect(DEF dst);
8707 size(4);
8708 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8709 ins_encode(SetHi22(0x41f00000, dst));
8710 ins_pipe(ialu_none);
8711 %}
8713 // Construct a double from two float halves
8714 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8715 effect(DEF dst, USE src1, USE src2);
8716 size(8);
8717 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8718 "FMOVS $src2.lo,$dst.lo" %}
8719 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8720 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8721 ins_pipe(faddD_reg_reg);
8722 %}
8724 // Convert integer in high half of a double register (in the lower half of
8725 // the double register file) to double
8726 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8727 effect(DEF dst, USE src);
8728 size(4);
8729 format %{ "FITOD $src,$dst" %}
8730 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8731 ins_encode(form3_opf_rs2D_rdD(src, dst));
8732 ins_pipe(fcvtLHi2D);
8733 %}
8735 // Add float double precision
8736 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8737 effect(DEF dst, USE src1, USE src2);
8738 size(4);
8739 format %{ "FADDD $src1,$src2,$dst" %}
8740 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8741 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8742 ins_pipe(faddD_reg_reg);
8743 %}
8745 // Sub float double precision
8746 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8747 effect(DEF dst, USE src1, USE src2);
8748 size(4);
8749 format %{ "FSUBD $src1,$src2,$dst" %}
8750 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8751 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8752 ins_pipe(faddD_reg_reg);
8753 %}
8755 // Mul float double precision
8756 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8757 effect(DEF dst, USE src1, USE src2);
8758 size(4);
8759 format %{ "FMULD $src1,$src2,$dst" %}
8760 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8761 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8762 ins_pipe(fmulD_reg_reg);
8763 %}
8765 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8766 match(Set dst (ConvL2D src));
8767 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8769 expand %{
8770 regD_low tmpsrc;
8771 iRegI ix43300000;
8772 iRegI ix41f00000;
8773 stackSlotL lx43300000;
8774 stackSlotL lx41f00000;
8775 regD_low dx43300000;
8776 regD dx41f00000;
8777 regD tmp1;
8778 regD_low tmp2;
8779 regD tmp3;
8780 regD tmp4;
8782 stkL_to_regD(tmpsrc, src);
8784 loadConI_x43300000(ix43300000);
8785 loadConI_x41f00000(ix41f00000);
8786 regI_to_stkLHi(lx43300000, ix43300000);
8787 regI_to_stkLHi(lx41f00000, ix41f00000);
8788 stkL_to_regD(dx43300000, lx43300000);
8789 stkL_to_regD(dx41f00000, lx41f00000);
8791 convI2D_regDHi_regD(tmp1, tmpsrc);
8792 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8793 subD_regD_regD(tmp3, tmp2, dx43300000);
8794 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8795 addD_regD_regD(dst, tmp3, tmp4);
8796 %}
8797 %}
8799 // Long to Double conversion using fast fxtof
8800 instruct convL2D_helper(regD dst, regD tmp) %{
8801 effect(DEF dst, USE tmp);
8802 size(4);
8803 format %{ "FXTOD $tmp,$dst" %}
8804 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8805 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8806 ins_pipe(fcvtL2D);
8807 %}
8809 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8810 predicate(VM_Version::has_fast_fxtof());
8811 match(Set dst (ConvL2D src));
8812 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8813 expand %{
8814 regD tmp;
8815 stkL_to_regD(tmp, src);
8816 convL2D_helper(dst, tmp);
8817 %}
8818 %}
8820 instruct convL2D_reg(regD dst, iRegL src) %{
8821 predicate(UseVIS >= 3);
8822 match(Set dst (ConvL2D src));
8823 expand %{
8824 regD tmp;
8825 MoveL2D_reg_reg(tmp, src);
8826 convL2D_helper(dst, tmp);
8827 %}
8828 %}
8830 // Long to Float conversion using fast fxtof
8831 instruct convL2F_helper(regF dst, regD tmp) %{
8832 effect(DEF dst, USE tmp);
8833 size(4);
8834 format %{ "FXTOS $tmp,$dst" %}
8835 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8836 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8837 ins_pipe(fcvtL2F);
8838 %}
8840 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8841 match(Set dst (ConvL2F src));
8842 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8843 expand %{
8844 regD tmp;
8845 stkL_to_regD(tmp, src);
8846 convL2F_helper(dst, tmp);
8847 %}
8848 %}
8850 instruct convL2F_reg(regF dst, iRegL src) %{
8851 predicate(UseVIS >= 3);
8852 match(Set dst (ConvL2F src));
8853 ins_cost(DEFAULT_COST);
8854 expand %{
8855 regD tmp;
8856 MoveL2D_reg_reg(tmp, src);
8857 convL2F_helper(dst, tmp);
8858 %}
8859 %}
8861 //-----------
8863 instruct convL2I_reg(iRegI dst, iRegL src) %{
8864 match(Set dst (ConvL2I src));
8865 #ifndef _LP64
8866 format %{ "MOV $src.lo,$dst\t! long->int" %}
8867 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8868 ins_pipe(ialu_move_reg_I_to_L);
8869 #else
8870 size(4);
8871 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8872 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8873 ins_pipe(ialu_reg);
8874 #endif
8875 %}
8877 // Register Shift Right Immediate
8878 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8879 match(Set dst (ConvL2I (RShiftL src cnt)));
8881 size(4);
8882 format %{ "SRAX $src,$cnt,$dst" %}
8883 opcode(Assembler::srax_op3, Assembler::arith_op);
8884 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8885 ins_pipe(ialu_reg_imm);
8886 %}
8888 //----------Control Flow Instructions------------------------------------------
8889 // Compare Instructions
8890 // Compare Integers
8891 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8892 match(Set icc (CmpI op1 op2));
8893 effect( DEF icc, USE op1, USE op2 );
8895 size(4);
8896 format %{ "CMP $op1,$op2" %}
8897 opcode(Assembler::subcc_op3, Assembler::arith_op);
8898 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8899 ins_pipe(ialu_cconly_reg_reg);
8900 %}
8902 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8903 match(Set icc (CmpU op1 op2));
8905 size(4);
8906 format %{ "CMP $op1,$op2\t! unsigned" %}
8907 opcode(Assembler::subcc_op3, Assembler::arith_op);
8908 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8909 ins_pipe(ialu_cconly_reg_reg);
8910 %}
8912 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8913 match(Set icc (CmpI op1 op2));
8914 effect( DEF icc, USE op1 );
8916 size(4);
8917 format %{ "CMP $op1,$op2" %}
8918 opcode(Assembler::subcc_op3, Assembler::arith_op);
8919 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8920 ins_pipe(ialu_cconly_reg_imm);
8921 %}
8923 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8924 match(Set icc (CmpI (AndI op1 op2) zero));
8926 size(4);
8927 format %{ "BTST $op2,$op1" %}
8928 opcode(Assembler::andcc_op3, Assembler::arith_op);
8929 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8930 ins_pipe(ialu_cconly_reg_reg_zero);
8931 %}
8933 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8934 match(Set icc (CmpI (AndI op1 op2) zero));
8936 size(4);
8937 format %{ "BTST $op2,$op1" %}
8938 opcode(Assembler::andcc_op3, Assembler::arith_op);
8939 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8940 ins_pipe(ialu_cconly_reg_imm_zero);
8941 %}
8943 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8944 match(Set xcc (CmpL op1 op2));
8945 effect( DEF xcc, USE op1, USE op2 );
8947 size(4);
8948 format %{ "CMP $op1,$op2\t\t! long" %}
8949 opcode(Assembler::subcc_op3, Assembler::arith_op);
8950 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8951 ins_pipe(ialu_cconly_reg_reg);
8952 %}
8954 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8955 match(Set xcc (CmpL op1 con));
8956 effect( DEF xcc, USE op1, USE con );
8958 size(4);
8959 format %{ "CMP $op1,$con\t\t! long" %}
8960 opcode(Assembler::subcc_op3, Assembler::arith_op);
8961 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8962 ins_pipe(ialu_cconly_reg_reg);
8963 %}
8965 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8966 match(Set xcc (CmpL (AndL op1 op2) zero));
8967 effect( DEF xcc, USE op1, USE op2 );
8969 size(4);
8970 format %{ "BTST $op1,$op2\t\t! long" %}
8971 opcode(Assembler::andcc_op3, Assembler::arith_op);
8972 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8973 ins_pipe(ialu_cconly_reg_reg);
8974 %}
8976 // useful for checking the alignment of a pointer:
8977 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8978 match(Set xcc (CmpL (AndL op1 con) zero));
8979 effect( DEF xcc, USE op1, USE con );
8981 size(4);
8982 format %{ "BTST $op1,$con\t\t! long" %}
8983 opcode(Assembler::andcc_op3, Assembler::arith_op);
8984 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8985 ins_pipe(ialu_cconly_reg_reg);
8986 %}
8988 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8989 match(Set icc (CmpU op1 op2));
8991 size(4);
8992 format %{ "CMP $op1,$op2\t! unsigned" %}
8993 opcode(Assembler::subcc_op3, Assembler::arith_op);
8994 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8995 ins_pipe(ialu_cconly_reg_imm);
8996 %}
8998 // Compare Pointers
8999 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9000 match(Set pcc (CmpP op1 op2));
9002 size(4);
9003 format %{ "CMP $op1,$op2\t! ptr" %}
9004 opcode(Assembler::subcc_op3, Assembler::arith_op);
9005 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9006 ins_pipe(ialu_cconly_reg_reg);
9007 %}
9009 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9010 match(Set pcc (CmpP op1 op2));
9012 size(4);
9013 format %{ "CMP $op1,$op2\t! ptr" %}
9014 opcode(Assembler::subcc_op3, Assembler::arith_op);
9015 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9016 ins_pipe(ialu_cconly_reg_imm);
9017 %}
9019 // Compare Narrow oops
9020 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9021 match(Set icc (CmpN op1 op2));
9023 size(4);
9024 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9025 opcode(Assembler::subcc_op3, Assembler::arith_op);
9026 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9027 ins_pipe(ialu_cconly_reg_reg);
9028 %}
9030 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9031 match(Set icc (CmpN op1 op2));
9033 size(4);
9034 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9035 opcode(Assembler::subcc_op3, Assembler::arith_op);
9036 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9037 ins_pipe(ialu_cconly_reg_imm);
9038 %}
9040 //----------Max and Min--------------------------------------------------------
9041 // Min Instructions
9042 // Conditional move for min
9043 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9044 effect( USE_DEF op2, USE op1, USE icc );
9046 size(4);
9047 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9048 opcode(Assembler::less);
9049 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9050 ins_pipe(ialu_reg_flags);
9051 %}
9053 // Min Register with Register.
9054 instruct minI_eReg(iRegI op1, iRegI op2) %{
9055 match(Set op2 (MinI op1 op2));
9056 ins_cost(DEFAULT_COST*2);
9057 expand %{
9058 flagsReg icc;
9059 compI_iReg(icc,op1,op2);
9060 cmovI_reg_lt(op2,op1,icc);
9061 %}
9062 %}
9064 // Max Instructions
9065 // Conditional move for max
9066 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9067 effect( USE_DEF op2, USE op1, USE icc );
9068 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9069 opcode(Assembler::greater);
9070 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9071 ins_pipe(ialu_reg_flags);
9072 %}
9074 // Max Register with Register
9075 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9076 match(Set op2 (MaxI op1 op2));
9077 ins_cost(DEFAULT_COST*2);
9078 expand %{
9079 flagsReg icc;
9080 compI_iReg(icc,op1,op2);
9081 cmovI_reg_gt(op2,op1,icc);
9082 %}
9083 %}
9086 //----------Float Compares----------------------------------------------------
9087 // Compare floating, generate condition code
9088 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9089 match(Set fcc (CmpF src1 src2));
9091 size(4);
9092 format %{ "FCMPs $fcc,$src1,$src2" %}
9093 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9094 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9095 ins_pipe(faddF_fcc_reg_reg_zero);
9096 %}
9098 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9099 match(Set fcc (CmpD src1 src2));
9101 size(4);
9102 format %{ "FCMPd $fcc,$src1,$src2" %}
9103 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9104 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9105 ins_pipe(faddD_fcc_reg_reg_zero);
9106 %}
9109 // Compare floating, generate -1,0,1
9110 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9111 match(Set dst (CmpF3 src1 src2));
9112 effect(KILL fcc0);
9113 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9114 format %{ "fcmpl $dst,$src1,$src2" %}
9115 // Primary = float
9116 opcode( true );
9117 ins_encode( floating_cmp( dst, src1, src2 ) );
9118 ins_pipe( floating_cmp );
9119 %}
9121 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9122 match(Set dst (CmpD3 src1 src2));
9123 effect(KILL fcc0);
9124 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9125 format %{ "dcmpl $dst,$src1,$src2" %}
9126 // Primary = double (not float)
9127 opcode( false );
9128 ins_encode( floating_cmp( dst, src1, src2 ) );
9129 ins_pipe( floating_cmp );
9130 %}
9132 //----------Branches---------------------------------------------------------
9133 // Jump
9134 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9135 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9136 match(Jump switch_val);
9137 effect(TEMP table);
9139 ins_cost(350);
9141 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9142 "LD [O7 + $switch_val], O7\n\t"
9143 "JUMP O7" %}
9144 ins_encode %{
9145 // Calculate table address into a register.
9146 Register table_reg;
9147 Register label_reg = O7;
9148 // If we are calculating the size of this instruction don't trust
9149 // zero offsets because they might change when
9150 // MachConstantBaseNode decides to optimize the constant table
9151 // base.
9152 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9153 table_reg = $constanttablebase;
9154 } else {
9155 table_reg = O7;
9156 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9157 __ add($constanttablebase, con_offset, table_reg);
9158 }
9160 // Jump to base address + switch value
9161 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9162 __ jmp(label_reg, G0);
9163 __ delayed()->nop();
9164 %}
9165 ins_pipe(ialu_reg_reg);
9166 %}
9168 // Direct Branch. Use V8 version with longer range.
9169 instruct branch(label labl) %{
9170 match(Goto);
9171 effect(USE labl);
9173 size(8);
9174 ins_cost(BRANCH_COST);
9175 format %{ "BA $labl" %}
9176 ins_encode %{
9177 Label* L = $labl$$label;
9178 __ ba(*L);
9179 __ delayed()->nop();
9180 %}
9181 ins_pipe(br);
9182 %}
9184 // Direct Branch, short with no delay slot
9185 instruct branch_short(label labl) %{
9186 match(Goto);
9187 predicate(UseCBCond);
9188 effect(USE labl);
9190 size(4);
9191 ins_cost(BRANCH_COST);
9192 format %{ "BA $labl\t! short branch" %}
9193 ins_encode %{
9194 Label* L = $labl$$label;
9195 assert(__ use_cbcond(*L), "back to back cbcond");
9196 __ ba_short(*L);
9197 %}
9198 ins_short_branch(1);
9199 ins_avoid_back_to_back(1);
9200 ins_pipe(cbcond_reg_imm);
9201 %}
9203 // Conditional Direct Branch
9204 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9205 match(If cmp icc);
9206 effect(USE labl);
9208 size(8);
9209 ins_cost(BRANCH_COST);
9210 format %{ "BP$cmp $icc,$labl" %}
9211 // Prim = bits 24-22, Secnd = bits 31-30
9212 ins_encode( enc_bp( labl, cmp, icc ) );
9213 ins_pipe(br_cc);
9214 %}
9216 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9217 match(If cmp icc);
9218 effect(USE labl);
9220 ins_cost(BRANCH_COST);
9221 format %{ "BP$cmp $icc,$labl" %}
9222 // Prim = bits 24-22, Secnd = bits 31-30
9223 ins_encode( enc_bp( labl, cmp, icc ) );
9224 ins_pipe(br_cc);
9225 %}
9227 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9228 match(If cmp pcc);
9229 effect(USE labl);
9231 size(8);
9232 ins_cost(BRANCH_COST);
9233 format %{ "BP$cmp $pcc,$labl" %}
9234 ins_encode %{
9235 Label* L = $labl$$label;
9236 Assembler::Predict predict_taken =
9237 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9239 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9240 __ delayed()->nop();
9241 %}
9242 ins_pipe(br_cc);
9243 %}
9245 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9246 match(If cmp fcc);
9247 effect(USE labl);
9249 size(8);
9250 ins_cost(BRANCH_COST);
9251 format %{ "FBP$cmp $fcc,$labl" %}
9252 ins_encode %{
9253 Label* L = $labl$$label;
9254 Assembler::Predict predict_taken =
9255 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9257 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9258 __ delayed()->nop();
9259 %}
9260 ins_pipe(br_fcc);
9261 %}
9263 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9264 match(CountedLoopEnd cmp icc);
9265 effect(USE labl);
9267 size(8);
9268 ins_cost(BRANCH_COST);
9269 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9270 // Prim = bits 24-22, Secnd = bits 31-30
9271 ins_encode( enc_bp( labl, cmp, icc ) );
9272 ins_pipe(br_cc);
9273 %}
9275 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9276 match(CountedLoopEnd cmp icc);
9277 effect(USE labl);
9279 size(8);
9280 ins_cost(BRANCH_COST);
9281 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9282 // Prim = bits 24-22, Secnd = bits 31-30
9283 ins_encode( enc_bp( labl, cmp, icc ) );
9284 ins_pipe(br_cc);
9285 %}
9287 // Compare and branch instructions
9288 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9289 match(If cmp (CmpI op1 op2));
9290 effect(USE labl, KILL icc);
9292 size(12);
9293 ins_cost(BRANCH_COST);
9294 format %{ "CMP $op1,$op2\t! int\n\t"
9295 "BP$cmp $labl" %}
9296 ins_encode %{
9297 Label* L = $labl$$label;
9298 Assembler::Predict predict_taken =
9299 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9300 __ cmp($op1$$Register, $op2$$Register);
9301 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9302 __ delayed()->nop();
9303 %}
9304 ins_pipe(cmp_br_reg_reg);
9305 %}
9307 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9308 match(If cmp (CmpI op1 op2));
9309 effect(USE labl, KILL icc);
9311 size(12);
9312 ins_cost(BRANCH_COST);
9313 format %{ "CMP $op1,$op2\t! int\n\t"
9314 "BP$cmp $labl" %}
9315 ins_encode %{
9316 Label* L = $labl$$label;
9317 Assembler::Predict predict_taken =
9318 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9319 __ cmp($op1$$Register, $op2$$constant);
9320 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9321 __ delayed()->nop();
9322 %}
9323 ins_pipe(cmp_br_reg_imm);
9324 %}
9326 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9327 match(If cmp (CmpU op1 op2));
9328 effect(USE labl, KILL icc);
9330 size(12);
9331 ins_cost(BRANCH_COST);
9332 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9333 "BP$cmp $labl" %}
9334 ins_encode %{
9335 Label* L = $labl$$label;
9336 Assembler::Predict predict_taken =
9337 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9338 __ cmp($op1$$Register, $op2$$Register);
9339 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9340 __ delayed()->nop();
9341 %}
9342 ins_pipe(cmp_br_reg_reg);
9343 %}
9345 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9346 match(If cmp (CmpU op1 op2));
9347 effect(USE labl, KILL icc);
9349 size(12);
9350 ins_cost(BRANCH_COST);
9351 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9352 "BP$cmp $labl" %}
9353 ins_encode %{
9354 Label* L = $labl$$label;
9355 Assembler::Predict predict_taken =
9356 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9357 __ cmp($op1$$Register, $op2$$constant);
9358 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9359 __ delayed()->nop();
9360 %}
9361 ins_pipe(cmp_br_reg_imm);
9362 %}
9364 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9365 match(If cmp (CmpL op1 op2));
9366 effect(USE labl, KILL xcc);
9368 size(12);
9369 ins_cost(BRANCH_COST);
9370 format %{ "CMP $op1,$op2\t! long\n\t"
9371 "BP$cmp $labl" %}
9372 ins_encode %{
9373 Label* L = $labl$$label;
9374 Assembler::Predict predict_taken =
9375 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9376 __ cmp($op1$$Register, $op2$$Register);
9377 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9378 __ delayed()->nop();
9379 %}
9380 ins_pipe(cmp_br_reg_reg);
9381 %}
9383 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9384 match(If cmp (CmpL op1 op2));
9385 effect(USE labl, KILL xcc);
9387 size(12);
9388 ins_cost(BRANCH_COST);
9389 format %{ "CMP $op1,$op2\t! long\n\t"
9390 "BP$cmp $labl" %}
9391 ins_encode %{
9392 Label* L = $labl$$label;
9393 Assembler::Predict predict_taken =
9394 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9395 __ cmp($op1$$Register, $op2$$constant);
9396 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9397 __ delayed()->nop();
9398 %}
9399 ins_pipe(cmp_br_reg_imm);
9400 %}
9402 // Compare Pointers and branch
9403 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9404 match(If cmp (CmpP op1 op2));
9405 effect(USE labl, KILL pcc);
9407 size(12);
9408 ins_cost(BRANCH_COST);
9409 format %{ "CMP $op1,$op2\t! ptr\n\t"
9410 "B$cmp $labl" %}
9411 ins_encode %{
9412 Label* L = $labl$$label;
9413 Assembler::Predict predict_taken =
9414 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9415 __ cmp($op1$$Register, $op2$$Register);
9416 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9417 __ delayed()->nop();
9418 %}
9419 ins_pipe(cmp_br_reg_reg);
9420 %}
9422 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9423 match(If cmp (CmpP op1 null));
9424 effect(USE labl, KILL pcc);
9426 size(12);
9427 ins_cost(BRANCH_COST);
9428 format %{ "CMP $op1,0\t! ptr\n\t"
9429 "B$cmp $labl" %}
9430 ins_encode %{
9431 Label* L = $labl$$label;
9432 Assembler::Predict predict_taken =
9433 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9434 __ cmp($op1$$Register, G0);
9435 // bpr() is not used here since it has shorter distance.
9436 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9437 __ delayed()->nop();
9438 %}
9439 ins_pipe(cmp_br_reg_reg);
9440 %}
9442 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9443 match(If cmp (CmpN op1 op2));
9444 effect(USE labl, KILL icc);
9446 size(12);
9447 ins_cost(BRANCH_COST);
9448 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9449 "BP$cmp $labl" %}
9450 ins_encode %{
9451 Label* L = $labl$$label;
9452 Assembler::Predict predict_taken =
9453 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9454 __ cmp($op1$$Register, $op2$$Register);
9455 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9456 __ delayed()->nop();
9457 %}
9458 ins_pipe(cmp_br_reg_reg);
9459 %}
9461 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9462 match(If cmp (CmpN op1 null));
9463 effect(USE labl, KILL icc);
9465 size(12);
9466 ins_cost(BRANCH_COST);
9467 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9468 "BP$cmp $labl" %}
9469 ins_encode %{
9470 Label* L = $labl$$label;
9471 Assembler::Predict predict_taken =
9472 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9473 __ cmp($op1$$Register, G0);
9474 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9475 __ delayed()->nop();
9476 %}
9477 ins_pipe(cmp_br_reg_reg);
9478 %}
9480 // Loop back branch
9481 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9482 match(CountedLoopEnd cmp (CmpI op1 op2));
9483 effect(USE labl, KILL icc);
9485 size(12);
9486 ins_cost(BRANCH_COST);
9487 format %{ "CMP $op1,$op2\t! int\n\t"
9488 "BP$cmp $labl\t! Loop end" %}
9489 ins_encode %{
9490 Label* L = $labl$$label;
9491 Assembler::Predict predict_taken =
9492 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9493 __ cmp($op1$$Register, $op2$$Register);
9494 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9495 __ delayed()->nop();
9496 %}
9497 ins_pipe(cmp_br_reg_reg);
9498 %}
9500 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9501 match(CountedLoopEnd cmp (CmpI op1 op2));
9502 effect(USE labl, KILL icc);
9504 size(12);
9505 ins_cost(BRANCH_COST);
9506 format %{ "CMP $op1,$op2\t! int\n\t"
9507 "BP$cmp $labl\t! Loop end" %}
9508 ins_encode %{
9509 Label* L = $labl$$label;
9510 Assembler::Predict predict_taken =
9511 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9512 __ cmp($op1$$Register, $op2$$constant);
9513 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9514 __ delayed()->nop();
9515 %}
9516 ins_pipe(cmp_br_reg_imm);
9517 %}
9519 // Short compare and branch instructions
9520 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9521 match(If cmp (CmpI op1 op2));
9522 predicate(UseCBCond);
9523 effect(USE labl, KILL icc);
9525 size(4);
9526 ins_cost(BRANCH_COST);
9527 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9528 ins_encode %{
9529 Label* L = $labl$$label;
9530 assert(__ use_cbcond(*L), "back to back cbcond");
9531 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9532 %}
9533 ins_short_branch(1);
9534 ins_avoid_back_to_back(1);
9535 ins_pipe(cbcond_reg_reg);
9536 %}
9538 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9539 match(If cmp (CmpI op1 op2));
9540 predicate(UseCBCond);
9541 effect(USE labl, KILL icc);
9543 size(4);
9544 ins_cost(BRANCH_COST);
9545 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9546 ins_encode %{
9547 Label* L = $labl$$label;
9548 assert(__ use_cbcond(*L), "back to back cbcond");
9549 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9550 %}
9551 ins_short_branch(1);
9552 ins_avoid_back_to_back(1);
9553 ins_pipe(cbcond_reg_imm);
9554 %}
9556 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9557 match(If cmp (CmpU op1 op2));
9558 predicate(UseCBCond);
9559 effect(USE labl, KILL icc);
9561 size(4);
9562 ins_cost(BRANCH_COST);
9563 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9564 ins_encode %{
9565 Label* L = $labl$$label;
9566 assert(__ use_cbcond(*L), "back to back cbcond");
9567 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9568 %}
9569 ins_short_branch(1);
9570 ins_avoid_back_to_back(1);
9571 ins_pipe(cbcond_reg_reg);
9572 %}
9574 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9575 match(If cmp (CmpU op1 op2));
9576 predicate(UseCBCond);
9577 effect(USE labl, KILL icc);
9579 size(4);
9580 ins_cost(BRANCH_COST);
9581 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9582 ins_encode %{
9583 Label* L = $labl$$label;
9584 assert(__ use_cbcond(*L), "back to back cbcond");
9585 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9586 %}
9587 ins_short_branch(1);
9588 ins_avoid_back_to_back(1);
9589 ins_pipe(cbcond_reg_imm);
9590 %}
9592 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9593 match(If cmp (CmpL op1 op2));
9594 predicate(UseCBCond);
9595 effect(USE labl, KILL xcc);
9597 size(4);
9598 ins_cost(BRANCH_COST);
9599 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9600 ins_encode %{
9601 Label* L = $labl$$label;
9602 assert(__ use_cbcond(*L), "back to back cbcond");
9603 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9604 %}
9605 ins_short_branch(1);
9606 ins_avoid_back_to_back(1);
9607 ins_pipe(cbcond_reg_reg);
9608 %}
9610 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9611 match(If cmp (CmpL op1 op2));
9612 predicate(UseCBCond);
9613 effect(USE labl, KILL xcc);
9615 size(4);
9616 ins_cost(BRANCH_COST);
9617 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9618 ins_encode %{
9619 Label* L = $labl$$label;
9620 assert(__ use_cbcond(*L), "back to back cbcond");
9621 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9622 %}
9623 ins_short_branch(1);
9624 ins_avoid_back_to_back(1);
9625 ins_pipe(cbcond_reg_imm);
9626 %}
9628 // Compare Pointers and branch
9629 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9630 match(If cmp (CmpP op1 op2));
9631 predicate(UseCBCond);
9632 effect(USE labl, KILL pcc);
9634 size(4);
9635 ins_cost(BRANCH_COST);
9636 #ifdef _LP64
9637 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9638 #else
9639 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9640 #endif
9641 ins_encode %{
9642 Label* L = $labl$$label;
9643 assert(__ use_cbcond(*L), "back to back cbcond");
9644 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9645 %}
9646 ins_short_branch(1);
9647 ins_avoid_back_to_back(1);
9648 ins_pipe(cbcond_reg_reg);
9649 %}
9651 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9652 match(If cmp (CmpP op1 null));
9653 predicate(UseCBCond);
9654 effect(USE labl, KILL pcc);
9656 size(4);
9657 ins_cost(BRANCH_COST);
9658 #ifdef _LP64
9659 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9660 #else
9661 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9662 #endif
9663 ins_encode %{
9664 Label* L = $labl$$label;
9665 assert(__ use_cbcond(*L), "back to back cbcond");
9666 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9667 %}
9668 ins_short_branch(1);
9669 ins_avoid_back_to_back(1);
9670 ins_pipe(cbcond_reg_reg);
9671 %}
9673 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9674 match(If cmp (CmpN op1 op2));
9675 predicate(UseCBCond);
9676 effect(USE labl, KILL icc);
9678 size(4);
9679 ins_cost(BRANCH_COST);
9680 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9681 ins_encode %{
9682 Label* L = $labl$$label;
9683 assert(__ use_cbcond(*L), "back to back cbcond");
9684 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9685 %}
9686 ins_short_branch(1);
9687 ins_avoid_back_to_back(1);
9688 ins_pipe(cbcond_reg_reg);
9689 %}
9691 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9692 match(If cmp (CmpN op1 null));
9693 predicate(UseCBCond);
9694 effect(USE labl, KILL icc);
9696 size(4);
9697 ins_cost(BRANCH_COST);
9698 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9699 ins_encode %{
9700 Label* L = $labl$$label;
9701 assert(__ use_cbcond(*L), "back to back cbcond");
9702 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9703 %}
9704 ins_short_branch(1);
9705 ins_avoid_back_to_back(1);
9706 ins_pipe(cbcond_reg_reg);
9707 %}
9709 // Loop back branch
9710 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9711 match(CountedLoopEnd cmp (CmpI op1 op2));
9712 predicate(UseCBCond);
9713 effect(USE labl, KILL icc);
9715 size(4);
9716 ins_cost(BRANCH_COST);
9717 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9718 ins_encode %{
9719 Label* L = $labl$$label;
9720 assert(__ use_cbcond(*L), "back to back cbcond");
9721 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9722 %}
9723 ins_short_branch(1);
9724 ins_avoid_back_to_back(1);
9725 ins_pipe(cbcond_reg_reg);
9726 %}
9728 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9729 match(CountedLoopEnd cmp (CmpI op1 op2));
9730 predicate(UseCBCond);
9731 effect(USE labl, KILL icc);
9733 size(4);
9734 ins_cost(BRANCH_COST);
9735 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9736 ins_encode %{
9737 Label* L = $labl$$label;
9738 assert(__ use_cbcond(*L), "back to back cbcond");
9739 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9740 %}
9741 ins_short_branch(1);
9742 ins_avoid_back_to_back(1);
9743 ins_pipe(cbcond_reg_imm);
9744 %}
9746 // Branch-on-register tests all 64 bits. We assume that values
9747 // in 64-bit registers always remains zero or sign extended
9748 // unless our code munges the high bits. Interrupts can chop
9749 // the high order bits to zero or sign at any time.
9750 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9751 match(If cmp (CmpI op1 zero));
9752 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9753 effect(USE labl);
9755 size(8);
9756 ins_cost(BRANCH_COST);
9757 format %{ "BR$cmp $op1,$labl" %}
9758 ins_encode( enc_bpr( labl, cmp, op1 ) );
9759 ins_pipe(br_reg);
9760 %}
9762 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9763 match(If cmp (CmpP op1 null));
9764 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9765 effect(USE labl);
9767 size(8);
9768 ins_cost(BRANCH_COST);
9769 format %{ "BR$cmp $op1,$labl" %}
9770 ins_encode( enc_bpr( labl, cmp, op1 ) );
9771 ins_pipe(br_reg);
9772 %}
9774 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9775 match(If cmp (CmpL op1 zero));
9776 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9777 effect(USE labl);
9779 size(8);
9780 ins_cost(BRANCH_COST);
9781 format %{ "BR$cmp $op1,$labl" %}
9782 ins_encode( enc_bpr( labl, cmp, op1 ) );
9783 ins_pipe(br_reg);
9784 %}
9787 // ============================================================================
9788 // Long Compare
9789 //
9790 // Currently we hold longs in 2 registers. Comparing such values efficiently
9791 // is tricky. The flavor of compare used depends on whether we are testing
9792 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9793 // The GE test is the negated LT test. The LE test can be had by commuting
9794 // the operands (yielding a GE test) and then negating; negate again for the
9795 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9796 // NE test is negated from that.
9798 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9799 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9800 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9801 // are collapsed internally in the ADLC's dfa-gen code. The match for
9802 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9803 // foo match ends up with the wrong leaf. One fix is to not match both
9804 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9805 // both forms beat the trinary form of long-compare and both are very useful
9806 // on Intel which has so few registers.
9808 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9809 match(If cmp xcc);
9810 effect(USE labl);
9812 size(8);
9813 ins_cost(BRANCH_COST);
9814 format %{ "BP$cmp $xcc,$labl" %}
9815 ins_encode %{
9816 Label* L = $labl$$label;
9817 Assembler::Predict predict_taken =
9818 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9820 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9821 __ delayed()->nop();
9822 %}
9823 ins_pipe(br_cc);
9824 %}
9826 // Manifest a CmpL3 result in an integer register. Very painful.
9827 // This is the test to avoid.
9828 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9829 match(Set dst (CmpL3 src1 src2) );
9830 effect( KILL ccr );
9831 ins_cost(6*DEFAULT_COST);
9832 size(24);
9833 format %{ "CMP $src1,$src2\t\t! long\n"
9834 "\tBLT,a,pn done\n"
9835 "\tMOV -1,$dst\t! delay slot\n"
9836 "\tBGT,a,pn done\n"
9837 "\tMOV 1,$dst\t! delay slot\n"
9838 "\tCLR $dst\n"
9839 "done:" %}
9840 ins_encode( cmpl_flag(src1,src2,dst) );
9841 ins_pipe(cmpL_reg);
9842 %}
9844 // Conditional move
9845 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9846 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9847 ins_cost(150);
9848 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9849 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9850 ins_pipe(ialu_reg);
9851 %}
9853 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9854 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9855 ins_cost(140);
9856 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9857 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9858 ins_pipe(ialu_imm);
9859 %}
9861 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9862 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9863 ins_cost(150);
9864 format %{ "MOV$cmp $xcc,$src,$dst" %}
9865 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9866 ins_pipe(ialu_reg);
9867 %}
9869 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9870 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9871 ins_cost(140);
9872 format %{ "MOV$cmp $xcc,$src,$dst" %}
9873 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9874 ins_pipe(ialu_imm);
9875 %}
9877 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9878 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9879 ins_cost(150);
9880 format %{ "MOV$cmp $xcc,$src,$dst" %}
9881 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9882 ins_pipe(ialu_reg);
9883 %}
9885 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9886 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9887 ins_cost(150);
9888 format %{ "MOV$cmp $xcc,$src,$dst" %}
9889 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9890 ins_pipe(ialu_reg);
9891 %}
9893 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9894 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9895 ins_cost(140);
9896 format %{ "MOV$cmp $xcc,$src,$dst" %}
9897 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9898 ins_pipe(ialu_imm);
9899 %}
9901 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9902 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9903 ins_cost(150);
9904 opcode(0x101);
9905 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9906 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9907 ins_pipe(int_conditional_float_move);
9908 %}
9910 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9911 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9912 ins_cost(150);
9913 opcode(0x102);
9914 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9915 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9916 ins_pipe(int_conditional_float_move);
9917 %}
9919 // ============================================================================
9920 // Safepoint Instruction
9921 instruct safePoint_poll(iRegP poll) %{
9922 match(SafePoint poll);
9923 effect(USE poll);
9925 size(4);
9926 #ifdef _LP64
9927 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9928 #else
9929 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9930 #endif
9931 ins_encode %{
9932 __ relocate(relocInfo::poll_type);
9933 __ ld_ptr($poll$$Register, 0, G0);
9934 %}
9935 ins_pipe(loadPollP);
9936 %}
9938 // ============================================================================
9939 // Call Instructions
9940 // Call Java Static Instruction
9941 instruct CallStaticJavaDirect( method meth ) %{
9942 match(CallStaticJava);
9943 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9944 effect(USE meth);
9946 size(8);
9947 ins_cost(CALL_COST);
9948 format %{ "CALL,static ; NOP ==> " %}
9949 ins_encode( Java_Static_Call( meth ), call_epilog );
9950 ins_pipe(simple_call);
9951 %}
9953 // Call Java Static Instruction (method handle version)
9954 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9955 match(CallStaticJava);
9956 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9957 effect(USE meth, KILL l7_mh_SP_save);
9959 size(16);
9960 ins_cost(CALL_COST);
9961 format %{ "CALL,static/MethodHandle" %}
9962 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9963 ins_pipe(simple_call);
9964 %}
9966 // Call Java Dynamic Instruction
9967 instruct CallDynamicJavaDirect( method meth ) %{
9968 match(CallDynamicJava);
9969 effect(USE meth);
9971 ins_cost(CALL_COST);
9972 format %{ "SET (empty),R_G5\n\t"
9973 "CALL,dynamic ; NOP ==> " %}
9974 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9975 ins_pipe(call);
9976 %}
9978 // Call Runtime Instruction
9979 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9980 match(CallRuntime);
9981 effect(USE meth, KILL l7);
9982 ins_cost(CALL_COST);
9983 format %{ "CALL,runtime" %}
9984 ins_encode( Java_To_Runtime( meth ),
9985 call_epilog, adjust_long_from_native_call );
9986 ins_pipe(simple_call);
9987 %}
9989 // Call runtime without safepoint - same as CallRuntime
9990 instruct CallLeafDirect(method meth, l7RegP l7) %{
9991 match(CallLeaf);
9992 effect(USE meth, KILL l7);
9993 ins_cost(CALL_COST);
9994 format %{ "CALL,runtime leaf" %}
9995 ins_encode( Java_To_Runtime( meth ),
9996 call_epilog,
9997 adjust_long_from_native_call );
9998 ins_pipe(simple_call);
9999 %}
10001 // Call runtime without safepoint - same as CallLeaf
10002 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10003 match(CallLeafNoFP);
10004 effect(USE meth, KILL l7);
10005 ins_cost(CALL_COST);
10006 format %{ "CALL,runtime leaf nofp" %}
10007 ins_encode( Java_To_Runtime( meth ),
10008 call_epilog,
10009 adjust_long_from_native_call );
10010 ins_pipe(simple_call);
10011 %}
10013 // Tail Call; Jump from runtime stub to Java code.
10014 // Also known as an 'interprocedural jump'.
10015 // Target of jump will eventually return to caller.
10016 // TailJump below removes the return address.
10017 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10018 match(TailCall jump_target method_oop );
10020 ins_cost(CALL_COST);
10021 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10022 ins_encode(form_jmpl(jump_target));
10023 ins_pipe(tail_call);
10024 %}
10027 // Return Instruction
10028 instruct Ret() %{
10029 match(Return);
10031 // The epilogue node did the ret already.
10032 size(0);
10033 format %{ "! return" %}
10034 ins_encode();
10035 ins_pipe(empty);
10036 %}
10039 // Tail Jump; remove the return address; jump to target.
10040 // TailCall above leaves the return address around.
10041 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10042 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10043 // "restore" before this instruction (in Epilogue), we need to materialize it
10044 // in %i0.
10045 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10046 match( TailJump jump_target ex_oop );
10047 ins_cost(CALL_COST);
10048 format %{ "! discard R_O7\n\t"
10049 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10050 ins_encode(form_jmpl_set_exception_pc(jump_target));
10051 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10052 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10053 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10054 ins_pipe(tail_call);
10055 %}
10057 // Create exception oop: created by stack-crawling runtime code.
10058 // Created exception is now available to this handler, and is setup
10059 // just prior to jumping to this handler. No code emitted.
10060 instruct CreateException( o0RegP ex_oop )
10061 %{
10062 match(Set ex_oop (CreateEx));
10063 ins_cost(0);
10065 size(0);
10066 // use the following format syntax
10067 format %{ "! exception oop is in R_O0; no code emitted" %}
10068 ins_encode();
10069 ins_pipe(empty);
10070 %}
10073 // Rethrow exception:
10074 // The exception oop will come in the first argument position.
10075 // Then JUMP (not call) to the rethrow stub code.
10076 instruct RethrowException()
10077 %{
10078 match(Rethrow);
10079 ins_cost(CALL_COST);
10081 // use the following format syntax
10082 format %{ "Jmp rethrow_stub" %}
10083 ins_encode(enc_rethrow);
10084 ins_pipe(tail_call);
10085 %}
10088 // Die now
10089 instruct ShouldNotReachHere( )
10090 %{
10091 match(Halt);
10092 ins_cost(CALL_COST);
10094 size(4);
10095 // Use the following format syntax
10096 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10097 ins_encode( form2_illtrap() );
10098 ins_pipe(tail_call);
10099 %}
10101 // ============================================================================
10102 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10103 // array for an instance of the superklass. Set a hidden internal cache on a
10104 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10105 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10106 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10107 match(Set index (PartialSubtypeCheck sub super));
10108 effect( KILL pcc, KILL o7 );
10109 ins_cost(DEFAULT_COST*10);
10110 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10111 ins_encode( enc_PartialSubtypeCheck() );
10112 ins_pipe(partial_subtype_check_pipe);
10113 %}
10115 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10116 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10117 effect( KILL idx, KILL o7 );
10118 ins_cost(DEFAULT_COST*10);
10119 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10120 ins_encode( enc_PartialSubtypeCheck() );
10121 ins_pipe(partial_subtype_check_pipe);
10122 %}
10125 // ============================================================================
10126 // inlined locking and unlocking
10128 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10129 match(Set pcc (FastLock object box));
10131 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10132 ins_cost(100);
10134 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10135 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10136 ins_pipe(long_memory_op);
10137 %}
10140 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10141 match(Set pcc (FastUnlock object box));
10142 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10143 ins_cost(100);
10145 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10146 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10147 ins_pipe(long_memory_op);
10148 %}
10150 // The encodings are generic.
10151 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10152 predicate(!use_block_zeroing(n->in(2)) );
10153 match(Set dummy (ClearArray cnt base));
10154 effect(TEMP temp, KILL ccr);
10155 ins_cost(300);
10156 format %{ "MOV $cnt,$temp\n"
10157 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10158 " BRge loop\t\t! Clearing loop\n"
10159 " STX G0,[$base+$temp]\t! delay slot" %}
10161 ins_encode %{
10162 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10163 Register nof_bytes_arg = $cnt$$Register;
10164 Register nof_bytes_tmp = $temp$$Register;
10165 Register base_pointer_arg = $base$$Register;
10167 Label loop;
10168 __ mov(nof_bytes_arg, nof_bytes_tmp);
10170 // Loop and clear, walking backwards through the array.
10171 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10172 __ bind(loop);
10173 __ deccc(nof_bytes_tmp, 8);
10174 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10175 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10176 // %%%% this mini-loop must not cross a cache boundary!
10177 %}
10178 ins_pipe(long_memory_op);
10179 %}
10181 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10182 predicate(use_block_zeroing(n->in(2)));
10183 match(Set dummy (ClearArray cnt base));
10184 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10185 ins_cost(300);
10186 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10188 ins_encode %{
10190 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10191 Register to = $base$$Register;
10192 Register count = $cnt$$Register;
10194 Label Ldone;
10195 __ nop(); // Separate short branches
10196 // Use BIS for zeroing (temp is not used).
10197 __ bis_zeroing(to, count, G0, Ldone);
10198 __ bind(Ldone);
10200 %}
10201 ins_pipe(long_memory_op);
10202 %}
10204 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10205 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10206 match(Set dummy (ClearArray cnt base));
10207 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10208 ins_cost(300);
10209 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10211 ins_encode %{
10213 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10214 Register to = $base$$Register;
10215 Register count = $cnt$$Register;
10216 Register temp = $tmp$$Register;
10218 Label Ldone;
10219 __ nop(); // Separate short branches
10220 // Use BIS for zeroing
10221 __ bis_zeroing(to, count, temp, Ldone);
10222 __ bind(Ldone);
10224 %}
10225 ins_pipe(long_memory_op);
10226 %}
10228 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10229 o7RegI tmp, flagsReg ccr) %{
10230 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10231 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10232 ins_cost(300);
10233 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10234 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10235 ins_pipe(long_memory_op);
10236 %}
10238 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10239 o7RegI tmp, flagsReg ccr) %{
10240 match(Set result (StrEquals (Binary str1 str2) cnt));
10241 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10242 ins_cost(300);
10243 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10244 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10245 ins_pipe(long_memory_op);
10246 %}
10248 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10249 o7RegI tmp2, flagsReg ccr) %{
10250 match(Set result (AryEq ary1 ary2));
10251 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10252 ins_cost(300);
10253 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10254 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10255 ins_pipe(long_memory_op);
10256 %}
10259 //---------- Zeros Count Instructions ------------------------------------------
10261 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10262 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10263 match(Set dst (CountLeadingZerosI src));
10264 effect(TEMP dst, TEMP tmp, KILL cr);
10266 // x |= (x >> 1);
10267 // x |= (x >> 2);
10268 // x |= (x >> 4);
10269 // x |= (x >> 8);
10270 // x |= (x >> 16);
10271 // return (WORDBITS - popc(x));
10272 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10273 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10274 "OR $dst,$tmp,$dst\n\t"
10275 "SRL $dst,2,$tmp\n\t"
10276 "OR $dst,$tmp,$dst\n\t"
10277 "SRL $dst,4,$tmp\n\t"
10278 "OR $dst,$tmp,$dst\n\t"
10279 "SRL $dst,8,$tmp\n\t"
10280 "OR $dst,$tmp,$dst\n\t"
10281 "SRL $dst,16,$tmp\n\t"
10282 "OR $dst,$tmp,$dst\n\t"
10283 "POPC $dst,$dst\n\t"
10284 "MOV 32,$tmp\n\t"
10285 "SUB $tmp,$dst,$dst" %}
10286 ins_encode %{
10287 Register Rdst = $dst$$Register;
10288 Register Rsrc = $src$$Register;
10289 Register Rtmp = $tmp$$Register;
10290 __ srl(Rsrc, 1, Rtmp);
10291 __ srl(Rsrc, 0, Rdst);
10292 __ or3(Rdst, Rtmp, Rdst);
10293 __ srl(Rdst, 2, Rtmp);
10294 __ or3(Rdst, Rtmp, Rdst);
10295 __ srl(Rdst, 4, Rtmp);
10296 __ or3(Rdst, Rtmp, Rdst);
10297 __ srl(Rdst, 8, Rtmp);
10298 __ or3(Rdst, Rtmp, Rdst);
10299 __ srl(Rdst, 16, Rtmp);
10300 __ or3(Rdst, Rtmp, Rdst);
10301 __ popc(Rdst, Rdst);
10302 __ mov(BitsPerInt, Rtmp);
10303 __ sub(Rtmp, Rdst, Rdst);
10304 %}
10305 ins_pipe(ialu_reg);
10306 %}
10308 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10309 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10310 match(Set dst (CountLeadingZerosL src));
10311 effect(TEMP dst, TEMP tmp, KILL cr);
10313 // x |= (x >> 1);
10314 // x |= (x >> 2);
10315 // x |= (x >> 4);
10316 // x |= (x >> 8);
10317 // x |= (x >> 16);
10318 // x |= (x >> 32);
10319 // return (WORDBITS - popc(x));
10320 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10321 "OR $src,$tmp,$dst\n\t"
10322 "SRLX $dst,2,$tmp\n\t"
10323 "OR $dst,$tmp,$dst\n\t"
10324 "SRLX $dst,4,$tmp\n\t"
10325 "OR $dst,$tmp,$dst\n\t"
10326 "SRLX $dst,8,$tmp\n\t"
10327 "OR $dst,$tmp,$dst\n\t"
10328 "SRLX $dst,16,$tmp\n\t"
10329 "OR $dst,$tmp,$dst\n\t"
10330 "SRLX $dst,32,$tmp\n\t"
10331 "OR $dst,$tmp,$dst\n\t"
10332 "POPC $dst,$dst\n\t"
10333 "MOV 64,$tmp\n\t"
10334 "SUB $tmp,$dst,$dst" %}
10335 ins_encode %{
10336 Register Rdst = $dst$$Register;
10337 Register Rsrc = $src$$Register;
10338 Register Rtmp = $tmp$$Register;
10339 __ srlx(Rsrc, 1, Rtmp);
10340 __ or3( Rsrc, Rtmp, Rdst);
10341 __ srlx(Rdst, 2, Rtmp);
10342 __ or3( Rdst, Rtmp, Rdst);
10343 __ srlx(Rdst, 4, Rtmp);
10344 __ or3( Rdst, Rtmp, Rdst);
10345 __ srlx(Rdst, 8, Rtmp);
10346 __ or3( Rdst, Rtmp, Rdst);
10347 __ srlx(Rdst, 16, Rtmp);
10348 __ or3( Rdst, Rtmp, Rdst);
10349 __ srlx(Rdst, 32, Rtmp);
10350 __ or3( Rdst, Rtmp, Rdst);
10351 __ popc(Rdst, Rdst);
10352 __ mov(BitsPerLong, Rtmp);
10353 __ sub(Rtmp, Rdst, Rdst);
10354 %}
10355 ins_pipe(ialu_reg);
10356 %}
10358 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10359 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10360 match(Set dst (CountTrailingZerosI src));
10361 effect(TEMP dst, KILL cr);
10363 // return popc(~x & (x - 1));
10364 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10365 "ANDN $dst,$src,$dst\n\t"
10366 "SRL $dst,R_G0,$dst\n\t"
10367 "POPC $dst,$dst" %}
10368 ins_encode %{
10369 Register Rdst = $dst$$Register;
10370 Register Rsrc = $src$$Register;
10371 __ sub(Rsrc, 1, Rdst);
10372 __ andn(Rdst, Rsrc, Rdst);
10373 __ srl(Rdst, G0, Rdst);
10374 __ popc(Rdst, Rdst);
10375 %}
10376 ins_pipe(ialu_reg);
10377 %}
10379 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10380 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10381 match(Set dst (CountTrailingZerosL src));
10382 effect(TEMP dst, KILL cr);
10384 // return popc(~x & (x - 1));
10385 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10386 "ANDN $dst,$src,$dst\n\t"
10387 "POPC $dst,$dst" %}
10388 ins_encode %{
10389 Register Rdst = $dst$$Register;
10390 Register Rsrc = $src$$Register;
10391 __ sub(Rsrc, 1, Rdst);
10392 __ andn(Rdst, Rsrc, Rdst);
10393 __ popc(Rdst, Rdst);
10394 %}
10395 ins_pipe(ialu_reg);
10396 %}
10399 //---------- Population Count Instructions -------------------------------------
10401 instruct popCountI(iRegIsafe dst, iRegI src) %{
10402 predicate(UsePopCountInstruction);
10403 match(Set dst (PopCountI src));
10405 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10406 "POPC $dst, $dst" %}
10407 ins_encode %{
10408 __ srl($src$$Register, G0, $dst$$Register);
10409 __ popc($dst$$Register, $dst$$Register);
10410 %}
10411 ins_pipe(ialu_reg);
10412 %}
10414 // Note: Long.bitCount(long) returns an int.
10415 instruct popCountL(iRegIsafe dst, iRegL src) %{
10416 predicate(UsePopCountInstruction);
10417 match(Set dst (PopCountL src));
10419 format %{ "POPC $src, $dst" %}
10420 ins_encode %{
10421 __ popc($src$$Register, $dst$$Register);
10422 %}
10423 ins_pipe(ialu_reg);
10424 %}
10427 // ============================================================================
10428 //------------Bytes reverse--------------------------------------------------
10430 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10431 match(Set dst (ReverseBytesI src));
10433 // Op cost is artificially doubled to make sure that load or store
10434 // instructions are preferred over this one which requires a spill
10435 // onto a stack slot.
10436 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10437 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10439 ins_encode %{
10440 __ set($src$$disp + STACK_BIAS, O7);
10441 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10442 %}
10443 ins_pipe( iload_mem );
10444 %}
10446 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10447 match(Set dst (ReverseBytesL src));
10449 // Op cost is artificially doubled to make sure that load or store
10450 // instructions are preferred over this one which requires a spill
10451 // onto a stack slot.
10452 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10453 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10455 ins_encode %{
10456 __ set($src$$disp + STACK_BIAS, O7);
10457 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10458 %}
10459 ins_pipe( iload_mem );
10460 %}
10462 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10463 match(Set dst (ReverseBytesUS src));
10465 // Op cost is artificially doubled to make sure that load or store
10466 // instructions are preferred over this one which requires a spill
10467 // onto a stack slot.
10468 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10469 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10471 ins_encode %{
10472 // the value was spilled as an int so bias the load
10473 __ set($src$$disp + STACK_BIAS + 2, O7);
10474 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10475 %}
10476 ins_pipe( iload_mem );
10477 %}
10479 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10480 match(Set dst (ReverseBytesS src));
10482 // Op cost is artificially doubled to make sure that load or store
10483 // instructions are preferred over this one which requires a spill
10484 // onto a stack slot.
10485 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10486 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10488 ins_encode %{
10489 // the value was spilled as an int so bias the load
10490 __ set($src$$disp + STACK_BIAS + 2, O7);
10491 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10492 %}
10493 ins_pipe( iload_mem );
10494 %}
10496 // Load Integer reversed byte order
10497 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10498 match(Set dst (ReverseBytesI (LoadI src)));
10500 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10501 size(4);
10502 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10504 ins_encode %{
10505 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10506 %}
10507 ins_pipe(iload_mem);
10508 %}
10510 // Load Long - aligned and reversed
10511 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10512 match(Set dst (ReverseBytesL (LoadL src)));
10514 ins_cost(MEMORY_REF_COST);
10515 size(4);
10516 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10518 ins_encode %{
10519 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10520 %}
10521 ins_pipe(iload_mem);
10522 %}
10524 // Load unsigned short / char reversed byte order
10525 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10526 match(Set dst (ReverseBytesUS (LoadUS src)));
10528 ins_cost(MEMORY_REF_COST);
10529 size(4);
10530 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10532 ins_encode %{
10533 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10534 %}
10535 ins_pipe(iload_mem);
10536 %}
10538 // Load short reversed byte order
10539 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10540 match(Set dst (ReverseBytesS (LoadS src)));
10542 ins_cost(MEMORY_REF_COST);
10543 size(4);
10544 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10546 ins_encode %{
10547 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10548 %}
10549 ins_pipe(iload_mem);
10550 %}
10552 // Store Integer reversed byte order
10553 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10554 match(Set dst (StoreI dst (ReverseBytesI src)));
10556 ins_cost(MEMORY_REF_COST);
10557 size(4);
10558 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10560 ins_encode %{
10561 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10562 %}
10563 ins_pipe(istore_mem_reg);
10564 %}
10566 // Store Long reversed byte order
10567 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10568 match(Set dst (StoreL dst (ReverseBytesL src)));
10570 ins_cost(MEMORY_REF_COST);
10571 size(4);
10572 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10574 ins_encode %{
10575 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10576 %}
10577 ins_pipe(istore_mem_reg);
10578 %}
10580 // Store unsighed short/char reversed byte order
10581 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10582 match(Set dst (StoreC dst (ReverseBytesUS src)));
10584 ins_cost(MEMORY_REF_COST);
10585 size(4);
10586 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10588 ins_encode %{
10589 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10590 %}
10591 ins_pipe(istore_mem_reg);
10592 %}
10594 // Store short reversed byte order
10595 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10596 match(Set dst (StoreC dst (ReverseBytesS src)));
10598 ins_cost(MEMORY_REF_COST);
10599 size(4);
10600 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10602 ins_encode %{
10603 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10604 %}
10605 ins_pipe(istore_mem_reg);
10606 %}
10608 // ====================VECTOR INSTRUCTIONS=====================================
10610 // Load Aligned Packed values into a Double Register
10611 instruct loadV8(regD dst, memory mem) %{
10612 predicate(n->as_LoadVector()->memory_size() == 8);
10613 match(Set dst (LoadVector mem));
10614 ins_cost(MEMORY_REF_COST);
10615 size(4);
10616 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10617 ins_encode %{
10618 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10619 %}
10620 ins_pipe(floadD_mem);
10621 %}
10623 // Store Vector in Double register to memory
10624 instruct storeV8(memory mem, regD src) %{
10625 predicate(n->as_StoreVector()->memory_size() == 8);
10626 match(Set mem (StoreVector mem src));
10627 ins_cost(MEMORY_REF_COST);
10628 size(4);
10629 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10630 ins_encode %{
10631 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10632 %}
10633 ins_pipe(fstoreD_mem_reg);
10634 %}
10636 // Store Zero into vector in memory
10637 instruct storeV8B_zero(memory mem, immI0 zero) %{
10638 predicate(n->as_StoreVector()->memory_size() == 8);
10639 match(Set mem (StoreVector mem (ReplicateB zero)));
10640 ins_cost(MEMORY_REF_COST);
10641 size(4);
10642 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10643 ins_encode %{
10644 __ stx(G0, $mem$$Address);
10645 %}
10646 ins_pipe(fstoreD_mem_zero);
10647 %}
10649 instruct storeV4S_zero(memory mem, immI0 zero) %{
10650 predicate(n->as_StoreVector()->memory_size() == 8);
10651 match(Set mem (StoreVector mem (ReplicateS zero)));
10652 ins_cost(MEMORY_REF_COST);
10653 size(4);
10654 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10655 ins_encode %{
10656 __ stx(G0, $mem$$Address);
10657 %}
10658 ins_pipe(fstoreD_mem_zero);
10659 %}
10661 instruct storeV2I_zero(memory mem, immI0 zero) %{
10662 predicate(n->as_StoreVector()->memory_size() == 8);
10663 match(Set mem (StoreVector mem (ReplicateI zero)));
10664 ins_cost(MEMORY_REF_COST);
10665 size(4);
10666 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10667 ins_encode %{
10668 __ stx(G0, $mem$$Address);
10669 %}
10670 ins_pipe(fstoreD_mem_zero);
10671 %}
10673 instruct storeV2F_zero(memory mem, immF0 zero) %{
10674 predicate(n->as_StoreVector()->memory_size() == 8);
10675 match(Set mem (StoreVector mem (ReplicateF zero)));
10676 ins_cost(MEMORY_REF_COST);
10677 size(4);
10678 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10679 ins_encode %{
10680 __ stx(G0, $mem$$Address);
10681 %}
10682 ins_pipe(fstoreD_mem_zero);
10683 %}
10685 // Replicate scalar to packed byte values into Double register
10686 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10687 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10688 match(Set dst (ReplicateB src));
10689 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10690 format %{ "SLLX $src,56,$tmp\n\t"
10691 "SRLX $tmp, 8,$tmp2\n\t"
10692 "OR $tmp,$tmp2,$tmp\n\t"
10693 "SRLX $tmp,16,$tmp2\n\t"
10694 "OR $tmp,$tmp2,$tmp\n\t"
10695 "SRLX $tmp,32,$tmp2\n\t"
10696 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10697 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10698 ins_encode %{
10699 Register Rsrc = $src$$Register;
10700 Register Rtmp = $tmp$$Register;
10701 Register Rtmp2 = $tmp2$$Register;
10702 __ sllx(Rsrc, 56, Rtmp);
10703 __ srlx(Rtmp, 8, Rtmp2);
10704 __ or3 (Rtmp, Rtmp2, Rtmp);
10705 __ srlx(Rtmp, 16, Rtmp2);
10706 __ or3 (Rtmp, Rtmp2, Rtmp);
10707 __ srlx(Rtmp, 32, Rtmp2);
10708 __ or3 (Rtmp, Rtmp2, Rtmp);
10709 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10710 %}
10711 ins_pipe(ialu_reg);
10712 %}
10714 // Replicate scalar to packed byte values into Double stack
10715 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10716 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10717 match(Set dst (ReplicateB src));
10718 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10719 format %{ "SLLX $src,56,$tmp\n\t"
10720 "SRLX $tmp, 8,$tmp2\n\t"
10721 "OR $tmp,$tmp2,$tmp\n\t"
10722 "SRLX $tmp,16,$tmp2\n\t"
10723 "OR $tmp,$tmp2,$tmp\n\t"
10724 "SRLX $tmp,32,$tmp2\n\t"
10725 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10726 "STX $tmp,$dst\t! regL to stkD" %}
10727 ins_encode %{
10728 Register Rsrc = $src$$Register;
10729 Register Rtmp = $tmp$$Register;
10730 Register Rtmp2 = $tmp2$$Register;
10731 __ sllx(Rsrc, 56, Rtmp);
10732 __ srlx(Rtmp, 8, Rtmp2);
10733 __ or3 (Rtmp, Rtmp2, Rtmp);
10734 __ srlx(Rtmp, 16, Rtmp2);
10735 __ or3 (Rtmp, Rtmp2, Rtmp);
10736 __ srlx(Rtmp, 32, Rtmp2);
10737 __ or3 (Rtmp, Rtmp2, Rtmp);
10738 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10739 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10740 %}
10741 ins_pipe(ialu_reg);
10742 %}
10744 // Replicate scalar constant to packed byte values in Double register
10745 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10746 predicate(n->as_Vector()->length() == 8);
10747 match(Set dst (ReplicateB con));
10748 effect(KILL tmp);
10749 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10750 ins_encode %{
10751 // XXX This is a quick fix for 6833573.
10752 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10753 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10754 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10755 %}
10756 ins_pipe(loadConFD);
10757 %}
10759 // Replicate scalar to packed char/short values into Double register
10760 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10761 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10762 match(Set dst (ReplicateS src));
10763 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10764 format %{ "SLLX $src,48,$tmp\n\t"
10765 "SRLX $tmp,16,$tmp2\n\t"
10766 "OR $tmp,$tmp2,$tmp\n\t"
10767 "SRLX $tmp,32,$tmp2\n\t"
10768 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10769 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10770 ins_encode %{
10771 Register Rsrc = $src$$Register;
10772 Register Rtmp = $tmp$$Register;
10773 Register Rtmp2 = $tmp2$$Register;
10774 __ sllx(Rsrc, 48, Rtmp);
10775 __ srlx(Rtmp, 16, Rtmp2);
10776 __ or3 (Rtmp, Rtmp2, Rtmp);
10777 __ srlx(Rtmp, 32, Rtmp2);
10778 __ or3 (Rtmp, Rtmp2, Rtmp);
10779 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10780 %}
10781 ins_pipe(ialu_reg);
10782 %}
10784 // Replicate scalar to packed char/short values into Double stack
10785 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10786 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10787 match(Set dst (ReplicateS src));
10788 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10789 format %{ "SLLX $src,48,$tmp\n\t"
10790 "SRLX $tmp,16,$tmp2\n\t"
10791 "OR $tmp,$tmp2,$tmp\n\t"
10792 "SRLX $tmp,32,$tmp2\n\t"
10793 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10794 "STX $tmp,$dst\t! regL to stkD" %}
10795 ins_encode %{
10796 Register Rsrc = $src$$Register;
10797 Register Rtmp = $tmp$$Register;
10798 Register Rtmp2 = $tmp2$$Register;
10799 __ sllx(Rsrc, 48, Rtmp);
10800 __ srlx(Rtmp, 16, Rtmp2);
10801 __ or3 (Rtmp, Rtmp2, Rtmp);
10802 __ srlx(Rtmp, 32, Rtmp2);
10803 __ or3 (Rtmp, Rtmp2, Rtmp);
10804 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10805 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10806 %}
10807 ins_pipe(ialu_reg);
10808 %}
10810 // Replicate scalar constant to packed char/short values in Double register
10811 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10812 predicate(n->as_Vector()->length() == 4);
10813 match(Set dst (ReplicateS con));
10814 effect(KILL tmp);
10815 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10816 ins_encode %{
10817 // XXX This is a quick fix for 6833573.
10818 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10819 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10820 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10821 %}
10822 ins_pipe(loadConFD);
10823 %}
10825 // Replicate scalar to packed int values into Double register
10826 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10827 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10828 match(Set dst (ReplicateI src));
10829 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10830 format %{ "SLLX $src,32,$tmp\n\t"
10831 "SRLX $tmp,32,$tmp2\n\t"
10832 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10833 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10834 ins_encode %{
10835 Register Rsrc = $src$$Register;
10836 Register Rtmp = $tmp$$Register;
10837 Register Rtmp2 = $tmp2$$Register;
10838 __ sllx(Rsrc, 32, Rtmp);
10839 __ srlx(Rtmp, 32, Rtmp2);
10840 __ or3 (Rtmp, Rtmp2, Rtmp);
10841 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10842 %}
10843 ins_pipe(ialu_reg);
10844 %}
10846 // Replicate scalar to packed int values into Double stack
10847 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10848 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10849 match(Set dst (ReplicateI src));
10850 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10851 format %{ "SLLX $src,32,$tmp\n\t"
10852 "SRLX $tmp,32,$tmp2\n\t"
10853 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10854 "STX $tmp,$dst\t! regL to stkD" %}
10855 ins_encode %{
10856 Register Rsrc = $src$$Register;
10857 Register Rtmp = $tmp$$Register;
10858 Register Rtmp2 = $tmp2$$Register;
10859 __ sllx(Rsrc, 32, Rtmp);
10860 __ srlx(Rtmp, 32, Rtmp2);
10861 __ or3 (Rtmp, Rtmp2, Rtmp);
10862 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10863 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10864 %}
10865 ins_pipe(ialu_reg);
10866 %}
10868 // Replicate scalar zero constant to packed int values in Double register
10869 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10870 predicate(n->as_Vector()->length() == 2);
10871 match(Set dst (ReplicateI con));
10872 effect(KILL tmp);
10873 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10874 ins_encode %{
10875 // XXX This is a quick fix for 6833573.
10876 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10877 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10878 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10879 %}
10880 ins_pipe(loadConFD);
10881 %}
10883 // Replicate scalar to packed float values into Double stack
10884 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10885 predicate(n->as_Vector()->length() == 2);
10886 match(Set dst (ReplicateF src));
10887 ins_cost(MEMORY_REF_COST*2);
10888 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10889 "STF $src,$dst.lo" %}
10890 opcode(Assembler::stf_op3);
10891 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10892 ins_pipe(fstoreF_stk_reg);
10893 %}
10895 // Replicate scalar zero constant to packed float values in Double register
10896 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10897 predicate(n->as_Vector()->length() == 2);
10898 match(Set dst (ReplicateF con));
10899 effect(KILL tmp);
10900 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10901 ins_encode %{
10902 // XXX This is a quick fix for 6833573.
10903 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10904 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10905 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10906 %}
10907 ins_pipe(loadConFD);
10908 %}
10910 //----------PEEPHOLE RULES-----------------------------------------------------
10911 // These must follow all instruction definitions as they use the names
10912 // defined in the instructions definitions.
10913 //
10914 // peepmatch ( root_instr_name [preceding_instruction]* );
10915 //
10916 // peepconstraint %{
10917 // (instruction_number.operand_name relational_op instruction_number.operand_name
10918 // [, ...] );
10919 // // instruction numbers are zero-based using left to right order in peepmatch
10920 //
10921 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10922 // // provide an instruction_number.operand_name for each operand that appears
10923 // // in the replacement instruction's match rule
10924 //
10925 // ---------VM FLAGS---------------------------------------------------------
10926 //
10927 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10928 //
10929 // Each peephole rule is given an identifying number starting with zero and
10930 // increasing by one in the order seen by the parser. An individual peephole
10931 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10932 // on the command-line.
10933 //
10934 // ---------CURRENT LIMITATIONS----------------------------------------------
10935 //
10936 // Only match adjacent instructions in same basic block
10937 // Only equality constraints
10938 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10939 // Only one replacement instruction
10940 //
10941 // ---------EXAMPLE----------------------------------------------------------
10942 //
10943 // // pertinent parts of existing instructions in architecture description
10944 // instruct movI(eRegI dst, eRegI src) %{
10945 // match(Set dst (CopyI src));
10946 // %}
10947 //
10948 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10949 // match(Set dst (AddI dst src));
10950 // effect(KILL cr);
10951 // %}
10952 //
10953 // // Change (inc mov) to lea
10954 // peephole %{
10955 // // increment preceeded by register-register move
10956 // peepmatch ( incI_eReg movI );
10957 // // require that the destination register of the increment
10958 // // match the destination register of the move
10959 // peepconstraint ( 0.dst == 1.dst );
10960 // // construct a replacement instruction that sets
10961 // // the destination to ( move's source register + one )
10962 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10963 // %}
10964 //
10966 // // Change load of spilled value to only a spill
10967 // instruct storeI(memory mem, eRegI src) %{
10968 // match(Set mem (StoreI mem src));
10969 // %}
10970 //
10971 // instruct loadI(eRegI dst, memory mem) %{
10972 // match(Set dst (LoadI mem));
10973 // %}
10974 //
10975 // peephole %{
10976 // peepmatch ( loadI storeI );
10977 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10978 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10979 // %}
10981 //----------SMARTSPILL RULES---------------------------------------------------
10982 // These must follow all instruction definitions as they use the names
10983 // defined in the instructions definitions.
10984 //
10985 // SPARC will probably not have any of these rules due to RISC instruction set.
10987 //----------PIPELINE-----------------------------------------------------------
10988 // Rules which define the behavior of the target architectures pipeline.