Tue, 17 Jul 2018 20:32:39 +0800
#7326 mips generates wrong code for jal/j machine instructions
Reviewed-by: aoqi, zhaixiang
1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2017, 2018, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "gc_interface/collectedHeap.inline.hpp"
32 #include "interpreter/interpreter.hpp"
33 #include "memory/cardTableModRefBS.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "prims/methodHandles.hpp"
37 #include "runtime/biasedLocking.hpp"
38 #include "runtime/interfaceSupport.hpp"
39 #include "runtime/objectMonitor.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/stubRoutines.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
46 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc_implementation/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
50 // Implementation of MacroAssembler
52 intptr_t MacroAssembler::i[32] = {0};
53 float MacroAssembler::f[32] = {0.0};
55 void MacroAssembler::print(outputStream *s) {
56 unsigned int k;
57 for(k=0; k<sizeof(i)/sizeof(i[0]); k++) {
58 s->print_cr("i%d = 0x%.16lx", k, i[k]);
59 }
60 s->cr();
62 for(k=0; k<sizeof(f)/sizeof(f[0]); k++) {
63 s->print_cr("f%d = %f", k, f[k]);
64 }
65 s->cr();
66 }
68 int MacroAssembler::i_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->i[k]; }
69 int MacroAssembler::f_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->f[k]; }
71 void MacroAssembler::save_registers(MacroAssembler *masm) {
72 #define __ masm->
73 for(int k=0; k<32; k++) {
74 __ sw (as_Register(k), A0, i_offset(k));
75 }
77 for(int k=0; k<32; k++) {
78 __ swc1 (as_FloatRegister(k), A0, f_offset(k));
79 }
80 #undef __
81 }
83 void MacroAssembler::restore_registers(MacroAssembler *masm) {
84 #define __ masm->
85 for(int k=0; k<32; k++) {
86 __ lw (as_Register(k), A0, i_offset(k));
87 }
89 for(int k=0; k<32; k++) {
90 __ lwc1 (as_FloatRegister(k), A0, f_offset(k));
91 }
92 #undef __
93 }
96 void MacroAssembler::pd_patch_instruction(address branch, address target) {
97 jint& stub_inst = *(jint*) branch;
98 jint *pc = (jint *)branch;
100 if((opcode(stub_inst) == special_op) && (special(stub_inst) == dadd_op)) {
101 //b_far:
102 // move(AT, RA); // dadd
103 // emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
104 // nop();
105 // lui(T9, 0); // to be patched
106 // ori(T9, 0);
107 // daddu(T9, T9, RA);
108 // move(RA, AT);
109 // jr(T9);
111 assert(opcode(pc[3]) == lui_op
112 && opcode(pc[4]) == ori_op
113 && special(pc[5]) == daddu_op, "Not a branch label patch");
114 if(!(opcode(pc[3]) == lui_op
115 && opcode(pc[4]) == ori_op
116 && special(pc[5]) == daddu_op)) { tty->print_cr("Not a branch label patch"); }
118 int offset = target - branch;
119 if (!is_simm16(offset)) {
120 pc[3] = (pc[3] & 0xffff0000) | high16(offset - 12);
121 pc[4] = (pc[4] & 0xffff0000) | low16(offset - 12);
122 } else {
123 /* revert to "beq + nop" */
124 CodeBuffer cb(branch, 4 * 10);
125 MacroAssembler masm(&cb);
126 #define __ masm.
127 __ b(target);
128 __ delayed()->nop();
129 __ nop();
130 __ nop();
131 __ nop();
132 __ nop();
133 __ nop();
134 __ nop();
135 }
136 return;
137 } else if (special(pc[4]) == jr_op
138 && opcode(pc[4]) == special_op
139 && (((opcode(pc[0]) == lui_op) || opcode(pc[0]) == daddiu_op) || (opcode(pc[0]) == ori_op))) {
140 //jmp_far:
141 // patchable_set48(T9, target);
142 // jr(T9);
143 // nop();
145 CodeBuffer cb(branch, 4 * 4);
146 MacroAssembler masm(&cb);
147 masm.patchable_set48(T9, (long)(target));
148 return;
149 }
151 #ifndef PRODUCT
152 if (!is_simm16((target - branch - 4) >> 2)) {
153 tty->print_cr("Illegal patching: branch = 0x%lx, target = 0x%lx", branch, target);
154 tty->print_cr("======= Start decoding at branch = 0x%lx =======", branch);
155 Disassembler::decode(branch - 4 * 16, branch + 4 * 16, tty);
156 tty->print_cr("======= End of decoding =======");
157 }
158 #endif
160 stub_inst = patched_branch(target - branch, stub_inst, 0);
161 }
163 static inline address first_cache_address() {
164 return CodeCache::low_bound() + sizeof(HeapBlock::Header);
165 }
167 static inline address last_cache_address() {
168 return CodeCache::high_bound() - Assembler::InstructionSize;
169 }
171 int MacroAssembler::call_size(address target, bool far, bool patchable) {
172 if (patchable) return 6 << Assembler::LogInstructionSize;
173 if (!far) return 2 << Assembler::LogInstructionSize; // jal + nop
174 return (insts_for_set64((jlong)target) + 2) << Assembler::LogInstructionSize;
175 }
177 // Can we reach target using jal/j from anywhere
178 // in the code cache (because code can be relocated)?
179 bool MacroAssembler::reachable_from_cache(address target) {
180 address cl = first_cache_address();
181 address ch = last_cache_address();
183 return (cl <= target) && (target <= ch) && fit_in_jal(cl, ch);
184 }
186 void MacroAssembler::general_jump(address target) {
187 if (reachable_from_cache(target)) {
188 j(target);
189 delayed()->nop();
190 } else {
191 set64(T9, (long)target);
192 jr(T9);
193 delayed()->nop();
194 }
195 }
197 int MacroAssembler::insts_for_general_jump(address target) {
198 if (reachable_from_cache(target)) {
199 //j(target);
200 //nop();
201 return 2;
202 } else {
203 //set64(T9, (long)target);
204 //jr(T9);
205 //nop();
206 return insts_for_set64((jlong)target) + 2;
207 }
208 }
210 void MacroAssembler::patchable_jump(address target) {
211 if (reachable_from_cache(target)) {
212 nop();
213 nop();
214 nop();
215 nop();
216 j(target);
217 delayed()->nop();
218 } else {
219 patchable_set48(T9, (long)target);
220 jr(T9);
221 delayed()->nop();
222 }
223 }
225 int MacroAssembler::insts_for_patchable_jump(address target) {
226 return 6;
227 }
229 void MacroAssembler::general_call(address target) {
230 if (reachable_from_cache(target)) {
231 jal(target);
232 delayed()->nop();
233 } else {
234 set64(T9, (long)target);
235 jalr(T9);
236 delayed()->nop();
237 }
238 }
240 int MacroAssembler::insts_for_general_call(address target) {
241 if (reachable_from_cache(target)) {
242 //jal(target);
243 //nop();
244 return 2;
245 } else {
246 //set64(T9, (long)target);
247 //jalr(T9);
248 //nop();
249 return insts_for_set64((jlong)target) + 2;
250 }
251 }
253 void MacroAssembler::patchable_call(address target) {
254 if (reachable_from_cache(target)) {
255 nop();
256 nop();
257 nop();
258 nop();
259 jal(target);
260 delayed()->nop();
261 } else {
262 patchable_set48(T9, (long)target);
263 jalr(T9);
264 delayed()->nop();
265 }
266 }
268 int MacroAssembler::insts_for_patchable_call(address target) {
269 return 6;
270 }
272 void MacroAssembler::beq_far(Register rs, Register rt, address entry) {
273 u_char * cur_pc = pc();
275 /* Jin: Near/Far jump */
276 if(is_simm16((entry - pc() - 4) / 4)) {
277 Assembler::beq(rs, rt, offset(entry));
278 } else {
279 Label not_jump;
280 bne(rs, rt, not_jump);
281 delayed()->nop();
283 b_far(entry);
284 delayed()->nop();
286 bind(not_jump);
287 has_delay_slot();
288 }
289 }
291 void MacroAssembler::beq_far(Register rs, Register rt, Label& L) {
292 if (L.is_bound()) {
293 beq_far(rs, rt, target(L));
294 } else {
295 u_char * cur_pc = pc();
296 Label not_jump;
297 bne(rs, rt, not_jump);
298 delayed()->nop();
300 b_far(L);
301 delayed()->nop();
303 bind(not_jump);
304 has_delay_slot();
305 }
306 }
308 void MacroAssembler::bne_far(Register rs, Register rt, address entry) {
309 u_char * cur_pc = pc();
311 /* Jin: Near/Far jump */
312 if(is_simm16((entry - pc() - 4) / 4)) {
313 Assembler::bne(rs, rt, offset(entry));
314 } else {
315 Label not_jump;
316 beq(rs, rt, not_jump);
317 delayed()->nop();
319 b_far(entry);
320 delayed()->nop();
322 bind(not_jump);
323 has_delay_slot();
324 }
325 }
327 void MacroAssembler::bne_far(Register rs, Register rt, Label& L) {
328 if (L.is_bound()) {
329 bne_far(rs, rt, target(L));
330 } else {
331 u_char * cur_pc = pc();
332 Label not_jump;
333 beq(rs, rt, not_jump);
334 delayed()->nop();
336 b_far(L);
337 delayed()->nop();
339 bind(not_jump);
340 has_delay_slot();
341 }
342 }
344 void MacroAssembler::beq_long(Register rs, Register rt, Label& L) {
345 Label not_taken;
347 bne(rs, rt, not_taken);
348 delayed()->nop();
350 jmp_far(L);
352 bind(not_taken);
353 }
355 void MacroAssembler::bne_long(Register rs, Register rt, Label& L) {
356 Label not_taken;
358 beq(rs, rt, not_taken);
359 delayed()->nop();
361 jmp_far(L);
363 bind(not_taken);
364 }
366 void MacroAssembler::bc1t_long(Label& L) {
367 Label not_taken;
369 bc1f(not_taken);
370 delayed()->nop();
372 jmp_far(L);
374 bind(not_taken);
375 }
377 void MacroAssembler::bc1f_long(Label& L) {
378 Label not_taken;
380 bc1t(not_taken);
381 delayed()->nop();
383 jmp_far(L);
385 bind(not_taken);
386 }
388 void MacroAssembler::b_far(Label& L) {
389 if (L.is_bound()) {
390 b_far(target(L));
391 } else {
392 volatile address dest = target(L);
393 /*
394 MacroAssembler::pd_patch_instruction branch=55651ed514, target=55651ef6d8
395 0x00000055651ed514: dadd at, ra, zero
396 0x00000055651ed518: [4110001]bgezal zero, 0x00000055651ed520
398 0x00000055651ed51c: sll zero, zero, 0
399 0x00000055651ed520: lui t9, 0x0
400 0x00000055651ed524: ori t9, t9, 0x21b8
401 0x00000055651ed528: daddu t9, t9, ra
402 0x00000055651ed52c: dadd ra, at, zero
403 0x00000055651ed530: jr t9
404 0x00000055651ed534: sll zero, zero, 0
405 */
406 move(AT, RA);
407 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
408 nop();
409 lui(T9, 0); // to be patched
410 ori(T9, T9, 0);
411 daddu(T9, T9, RA);
412 move(RA, AT);
413 jr(T9);
414 }
415 }
417 void MacroAssembler::b_far(address entry) {
418 u_char * cur_pc = pc();
420 /* Jin: Near/Far jump */
421 if(is_simm16((entry - pc() - 4) / 4)) {
422 b(offset(entry));
423 } else {
424 /* address must be bounded */
425 move(AT, RA);
426 emit_long(insn_ORRI(regimm_op, 0, bgezal_op, 1));
427 nop();
428 li32(T9, entry - pc());
429 daddu(T9, T9, RA);
430 move(RA, AT);
431 jr(T9);
432 }
433 }
435 void MacroAssembler::ld_ptr(Register rt, Register offset, Register base) {
436 addu_long(AT, base, offset);
437 ld_ptr(rt, 0, AT);
438 }
440 void MacroAssembler::st_ptr(Register rt, Register offset, Register base) {
441 addu_long(AT, base, offset);
442 st_ptr(rt, 0, AT);
443 }
445 void MacroAssembler::ld_long(Register rt, Register offset, Register base) {
446 addu_long(AT, base, offset);
447 ld_long(rt, 0, AT);
448 }
450 void MacroAssembler::st_long(Register rt, Register offset, Register base) {
451 addu_long(AT, base, offset);
452 st_long(rt, 0, AT);
453 }
455 Address MacroAssembler::as_Address(AddressLiteral adr) {
456 return Address(adr.target(), adr.rspec());
457 }
459 Address MacroAssembler::as_Address(ArrayAddress adr) {
460 return Address::make_array(adr);
461 }
463 // tmp_reg1 and tmp_reg2 should be saved outside of atomic_inc32 (caller saved).
464 void MacroAssembler::atomic_inc32(address counter_addr, int inc, Register tmp_reg1, Register tmp_reg2) {
465 Label again;
467 li(tmp_reg1, counter_addr);
468 bind(again);
469 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
470 ll(tmp_reg2, tmp_reg1, 0);
471 addi(tmp_reg2, tmp_reg2, inc);
472 sc(tmp_reg2, tmp_reg1, 0);
473 beq(tmp_reg2, R0, again);
474 delayed()->nop();
475 }
477 int MacroAssembler::biased_locking_enter(Register lock_reg,
478 Register obj_reg,
479 Register swap_reg,
480 Register tmp_reg,
481 bool swap_reg_contains_mark,
482 Label& done,
483 Label* slow_case,
484 BiasedLockingCounters* counters) {
485 assert(UseBiasedLocking, "why call this otherwise?");
486 bool need_tmp_reg = false;
487 if (tmp_reg == noreg) {
488 need_tmp_reg = true;
489 tmp_reg = T9;
490 }
491 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg, AT);
492 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
493 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
494 Address saved_mark_addr(lock_reg, 0);
496 // Biased locking
497 // See whether the lock is currently biased toward our thread and
498 // whether the epoch is still valid
499 // Note that the runtime guarantees sufficient alignment of JavaThread
500 // pointers to allow age to be placed into low bits
501 // First check to see whether biasing is even enabled for this object
502 Label cas_label;
503 int null_check_offset = -1;
504 if (!swap_reg_contains_mark) {
505 null_check_offset = offset();
506 ld_ptr(swap_reg, mark_addr);
507 }
509 if (need_tmp_reg) {
510 push(tmp_reg);
511 }
512 move(tmp_reg, swap_reg);
513 andi(tmp_reg, tmp_reg, markOopDesc::biased_lock_mask_in_place);
514 #ifdef _LP64
515 daddi(AT, R0, markOopDesc::biased_lock_pattern);
516 dsub(AT, AT, tmp_reg);
517 #else
518 addi(AT, R0, markOopDesc::biased_lock_pattern);
519 sub(AT, AT, tmp_reg);
520 #endif
521 if (need_tmp_reg) {
522 pop(tmp_reg);
523 }
525 bne(AT, R0, cas_label);
526 delayed()->nop();
529 // The bias pattern is present in the object's header. Need to check
530 // whether the bias owner and the epoch are both still current.
531 // Note that because there is no current thread register on MIPS we
532 // need to store off the mark word we read out of the object to
533 // avoid reloading it and needing to recheck invariants below. This
534 // store is unfortunate but it makes the overall code shorter and
535 // simpler.
536 st_ptr(swap_reg, saved_mark_addr);
537 if (need_tmp_reg) {
538 push(tmp_reg);
539 }
540 if (swap_reg_contains_mark) {
541 null_check_offset = offset();
542 }
543 load_prototype_header(tmp_reg, obj_reg);
544 xorr(tmp_reg, tmp_reg, swap_reg);
545 get_thread(swap_reg);
546 xorr(swap_reg, swap_reg, tmp_reg);
548 move(AT, ~((int) markOopDesc::age_mask_in_place));
549 andr(swap_reg, swap_reg, AT);
551 if (PrintBiasedLockingStatistics) {
552 Label L;
553 bne(swap_reg, R0, L);
554 delayed()->nop();
555 push(tmp_reg);
556 push(A0);
557 atomic_inc32((address)BiasedLocking::biased_lock_entry_count_addr(), 1, A0, tmp_reg);
558 pop(A0);
559 pop(tmp_reg);
560 bind(L);
561 }
562 if (need_tmp_reg) {
563 pop(tmp_reg);
564 }
565 beq(swap_reg, R0, done);
566 delayed()->nop();
567 Label try_revoke_bias;
568 Label try_rebias;
570 // At this point we know that the header has the bias pattern and
571 // that we are not the bias owner in the current epoch. We need to
572 // figure out more details about the state of the header in order to
573 // know what operations can be legally performed on the object's
574 // header.
576 // If the low three bits in the xor result aren't clear, that means
577 // the prototype header is no longer biased and we have to revoke
578 // the bias on this object.
580 move(AT, markOopDesc::biased_lock_mask_in_place);
581 andr(AT, swap_reg, AT);
582 bne(AT, R0, try_revoke_bias);
583 delayed()->nop();
584 // Biasing is still enabled for this data type. See whether the
585 // epoch of the current bias is still valid, meaning that the epoch
586 // bits of the mark word are equal to the epoch bits of the
587 // prototype header. (Note that the prototype header's epoch bits
588 // only change at a safepoint.) If not, attempt to rebias the object
589 // toward the current thread. Note that we must be absolutely sure
590 // that the current epoch is invalid in order to do this because
591 // otherwise the manipulations it performs on the mark word are
592 // illegal.
594 move(AT, markOopDesc::epoch_mask_in_place);
595 andr(AT,swap_reg, AT);
596 bne(AT, R0, try_rebias);
597 delayed()->nop();
598 // The epoch of the current bias is still valid but we know nothing
599 // about the owner; it might be set or it might be clear. Try to
600 // acquire the bias of the object using an atomic operation. If this
601 // fails we will go in to the runtime to revoke the object's bias.
602 // Note that we first construct the presumed unbiased header so we
603 // don't accidentally blow away another thread's valid bias.
605 ld_ptr(swap_reg, saved_mark_addr);
607 move(AT, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
608 andr(swap_reg, swap_reg, AT);
610 if (need_tmp_reg) {
611 push(tmp_reg);
612 }
613 get_thread(tmp_reg);
614 orr(tmp_reg, tmp_reg, swap_reg);
615 //if (os::is_MP()) {
616 // sync();
617 //}
618 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
619 if (need_tmp_reg) {
620 pop(tmp_reg);
621 }
622 // If the biasing toward our thread failed, this means that
623 // another thread succeeded in biasing it toward itself and we
624 // need to revoke that bias. The revocation will occur in the
625 // interpreter runtime in the slow case.
626 if (PrintBiasedLockingStatistics) {
627 Label L;
628 bne(AT, R0, L);
629 delayed()->nop();
630 push(tmp_reg);
631 push(A0);
632 atomic_inc32((address)BiasedLocking::anonymously_biased_lock_entry_count_addr(), 1, A0, tmp_reg);
633 pop(A0);
634 pop(tmp_reg);
635 bind(L);
636 }
637 if (slow_case != NULL) {
638 beq_far(AT, R0, *slow_case);
639 delayed()->nop();
640 }
641 b(done);
642 delayed()->nop();
644 bind(try_rebias);
645 // At this point we know the epoch has expired, meaning that the
646 // current "bias owner", if any, is actually invalid. Under these
647 // circumstances _only_, we are allowed to use the current header's
648 // value as the comparison value when doing the cas to acquire the
649 // bias in the current epoch. In other words, we allow transfer of
650 // the bias from one thread to another directly in this situation.
651 //
652 // FIXME: due to a lack of registers we currently blow away the age
653 // bits in this situation. Should attempt to preserve them.
654 if (need_tmp_reg) {
655 push(tmp_reg);
656 }
657 load_prototype_header(tmp_reg, obj_reg);
658 get_thread(swap_reg);
659 orr(tmp_reg, tmp_reg, swap_reg);
660 ld_ptr(swap_reg, saved_mark_addr);
662 //if (os::is_MP()) {
663 // sync();
664 //}
665 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
666 if (need_tmp_reg) {
667 pop(tmp_reg);
668 }
669 // If the biasing toward our thread failed, then another thread
670 // succeeded in biasing it toward itself and we need to revoke that
671 // bias. The revocation will occur in the runtime in the slow case.
672 if (PrintBiasedLockingStatistics) {
673 Label L;
674 bne(AT, R0, L);
675 delayed()->nop();
676 push(AT);
677 push(tmp_reg);
678 atomic_inc32((address)BiasedLocking::rebiased_lock_entry_count_addr(), 1, AT, tmp_reg);
679 pop(tmp_reg);
680 pop(AT);
681 bind(L);
682 }
683 if (slow_case != NULL) {
684 beq_far(AT, R0, *slow_case);
685 delayed()->nop();
686 }
688 b(done);
689 delayed()->nop();
690 bind(try_revoke_bias);
691 // The prototype mark in the klass doesn't have the bias bit set any
692 // more, indicating that objects of this data type are not supposed
693 // to be biased any more. We are going to try to reset the mark of
694 // this object to the prototype value and fall through to the
695 // CAS-based locking scheme. Note that if our CAS fails, it means
696 // that another thread raced us for the privilege of revoking the
697 // bias of this particular object, so it's okay to continue in the
698 // normal locking code.
699 //
700 // FIXME: due to a lack of registers we currently blow away the age
701 // bits in this situation. Should attempt to preserve them.
702 ld_ptr(swap_reg, saved_mark_addr);
704 if (need_tmp_reg) {
705 push(tmp_reg);
706 }
707 load_prototype_header(tmp_reg, obj_reg);
708 //if (os::is_MP()) {
709 // lock();
710 //}
711 cmpxchg(tmp_reg, Address(obj_reg, 0), swap_reg);
712 if (need_tmp_reg) {
713 pop(tmp_reg);
714 }
715 // Fall through to the normal CAS-based lock, because no matter what
716 // the result of the above CAS, some thread must have succeeded in
717 // removing the bias bit from the object's header.
718 if (PrintBiasedLockingStatistics) {
719 Label L;
720 bne(AT, R0, L);
721 delayed()->nop();
722 push(AT);
723 push(tmp_reg);
724 atomic_inc32((address)BiasedLocking::revoked_lock_entry_count_addr(), 1, AT, tmp_reg);
725 pop(tmp_reg);
726 pop(AT);
727 bind(L);
728 }
730 bind(cas_label);
731 return null_check_offset;
732 }
734 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
735 assert(UseBiasedLocking, "why call this otherwise?");
737 // Check for biased locking unlock case, which is a no-op
738 // Note: we do not have to check the thread ID for two reasons.
739 // First, the interpreter checks for IllegalMonitorStateException at
740 // a higher level. Second, if the bias was revoked while we held the
741 // lock, the object could not be rebiased toward another thread, so
742 // the bias bit would be clear.
743 #ifdef _LP64
744 ld(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
745 andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
746 daddi(AT, R0, markOopDesc::biased_lock_pattern);
747 #else
748 lw(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
749 andi(temp_reg, temp_reg, markOopDesc::biased_lock_mask_in_place);
750 addi(AT, R0, markOopDesc::biased_lock_pattern);
751 #endif
753 beq(AT, temp_reg, done);
754 delayed()->nop();
755 }
757 // the stack pointer adjustment is needed. see InterpreterMacroAssembler::super_call_VM_leaf
758 // this method will handle the stack problem, you need not to preserve the stack space for the argument now
759 void MacroAssembler::call_VM_leaf_base(address entry_point, int number_of_arguments) {
760 Label L, E;
762 assert(number_of_arguments <= 4, "just check");
764 andi(AT, SP, 0xf);
765 beq(AT, R0, L);
766 delayed()->nop();
767 daddi(SP, SP, -8);
768 call(entry_point, relocInfo::runtime_call_type);
769 delayed()->nop();
770 daddi(SP, SP, 8);
771 b(E);
772 delayed()->nop();
774 bind(L);
775 call(entry_point, relocInfo::runtime_call_type);
776 delayed()->nop();
777 bind(E);
778 }
781 void MacroAssembler::jmp(address entry) {
782 patchable_set48(T9, (long)entry);
783 jr(T9);
784 }
786 void MacroAssembler::jmp(address entry, relocInfo::relocType rtype) {
787 switch (rtype) {
788 case relocInfo::runtime_call_type:
789 case relocInfo::none:
790 jmp(entry);
791 break;
792 default:
793 {
794 InstructionMark im(this);
795 relocate(rtype);
796 patchable_set48(T9, (long)entry);
797 jr(T9);
798 }
799 break;
800 }
801 }
803 void MacroAssembler::jmp_far(Label& L) {
804 if (L.is_bound()) {
805 address entry = target(L);
806 assert(entry != NULL, "jmp most probably wrong");
807 InstructionMark im(this);
809 relocate(relocInfo::internal_word_type);
810 patchable_set48(T9, (long)entry);
811 } else {
812 InstructionMark im(this);
813 L.add_patch_at(code(), locator());
815 relocate(relocInfo::internal_word_type);
816 patchable_set48(T9, (long)pc());
817 }
819 jr(T9);
820 delayed()->nop();
821 }
822 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
823 int oop_index;
824 if (obj) {
825 oop_index = oop_recorder()->find_index(obj);
826 } else {
827 oop_index = oop_recorder()->allocate_metadata_index(obj);
828 }
829 relocate(metadata_Relocation::spec(oop_index));
830 patchable_set48(AT, (long)obj);
831 sd(AT, dst);
832 }
834 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
835 int oop_index;
836 if (obj) {
837 oop_index = oop_recorder()->find_index(obj);
838 } else {
839 oop_index = oop_recorder()->allocate_metadata_index(obj);
840 }
841 relocate(metadata_Relocation::spec(oop_index));
842 patchable_set48(dst, (long)obj);
843 }
845 void MacroAssembler::call(address entry) {
846 // c/c++ code assume T9 is entry point, so we just always move entry to t9
847 // maybe there is some more graceful method to handle this. FIXME
848 // For more info, see class NativeCall.
849 #ifndef _LP64
850 move(T9, (int)entry);
851 #else
852 patchable_set48(T9, (long)entry);
853 #endif
854 jalr(T9);
855 }
857 void MacroAssembler::call(address entry, relocInfo::relocType rtype) {
858 switch (rtype) {
859 case relocInfo::runtime_call_type:
860 case relocInfo::none:
861 call(entry);
862 break;
863 default:
864 {
865 InstructionMark im(this);
866 relocate(rtype);
867 call(entry);
868 }
869 break;
870 }
871 }
873 void MacroAssembler::call(address entry, RelocationHolder& rh)
874 {
875 switch (rh.type()) {
876 case relocInfo::runtime_call_type:
877 case relocInfo::none:
878 call(entry);
879 break;
880 default:
881 {
882 InstructionMark im(this);
883 relocate(rh);
884 call(entry);
885 }
886 break;
887 }
888 }
890 void MacroAssembler::ic_call(address entry) {
891 RelocationHolder rh = virtual_call_Relocation::spec(pc());
892 patchable_set48(IC_Klass, (long)Universe::non_oop_word());
893 assert(entry != NULL, "call most probably wrong");
894 InstructionMark im(this);
895 relocate(rh);
896 patchable_call(entry);
897 }
899 void MacroAssembler::c2bool(Register r) {
900 Label L;
901 Assembler::beq(r, R0, L);
902 delayed()->nop();
903 move(r, 1);
904 bind(L);
905 }
907 #ifndef PRODUCT
908 extern "C" void findpc(intptr_t x);
909 #endif
911 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
912 // In order to get locks to work, we need to fake a in_VM state
913 JavaThread* thread = JavaThread::current();
914 JavaThreadState saved_state = thread->thread_state();
915 thread->set_thread_state(_thread_in_vm);
916 if (ShowMessageBoxOnError) {
917 JavaThread* thread = JavaThread::current();
918 JavaThreadState saved_state = thread->thread_state();
919 thread->set_thread_state(_thread_in_vm);
920 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
921 ttyLocker ttyl;
922 BytecodeCounter::print();
923 }
924 // To see where a verify_oop failed, get $ebx+40/X for this frame.
925 // This is the value of eip which points to where verify_oop will return.
926 if (os::message_box(msg, "Execution stopped, print registers?")) {
927 ttyLocker ttyl;
928 tty->print_cr("eip = 0x%08x", eip);
929 #ifndef PRODUCT
930 tty->cr();
931 findpc(eip);
932 tty->cr();
933 #endif
934 tty->print_cr("rax, = 0x%08x", rax);
935 tty->print_cr("rbx, = 0x%08x", rbx);
936 tty->print_cr("rcx = 0x%08x", rcx);
937 tty->print_cr("rdx = 0x%08x", rdx);
938 tty->print_cr("rdi = 0x%08x", rdi);
939 tty->print_cr("rsi = 0x%08x", rsi);
940 tty->print_cr("rbp, = 0x%08x", rbp);
941 tty->print_cr("rsp = 0x%08x", rsp);
942 BREAKPOINT;
943 }
944 } else {
945 ttyLocker ttyl;
946 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
947 assert(false, "DEBUG MESSAGE");
948 }
949 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
950 }
952 void MacroAssembler::debug(char* msg/*, RegistersForDebugging* regs*/) {
953 if ( ShowMessageBoxOnError ) {
954 JavaThreadState saved_state = JavaThread::current()->thread_state();
955 JavaThread::current()->set_thread_state(_thread_in_vm);
956 {
957 // In order to get locks work, we need to fake a in_VM state
958 ttyLocker ttyl;
959 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
960 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
961 BytecodeCounter::print();
962 }
964 // if (os::message_box(msg, "Execution stopped, print registers?"))
965 // regs->print(::tty);
966 }
967 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
968 }
969 else
970 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
971 }
974 void MacroAssembler::stop(const char* msg) {
975 li(A0, (long)msg);
976 #ifndef _LP64
977 //reserver space for argument. added by yjl 7/10/2005
978 addiu(SP, SP, - 1 * wordSize);
979 #endif
980 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
981 delayed()->nop();
982 #ifndef _LP64
983 //restore space for argument
984 addiu(SP, SP, 1 * wordSize);
985 #endif
986 brk(17);
987 }
989 void MacroAssembler::warn(const char* msg) {
990 #ifdef _LP64
991 pushad();
992 li(A0, (long)msg);
993 push(S2);
994 move(AT, -(StackAlignmentInBytes));
995 move(S2, SP); // use S2 as a sender SP holder
996 andr(SP, SP, AT); // align stack as required by ABI
997 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
998 delayed()->nop();
999 move(SP, S2); // use S2 as a sender SP holder
1000 pop(S2);
1001 popad();
1002 #else
1003 pushad();
1004 addi(SP, SP, -4);
1005 sw(A0, SP, -1 * wordSize);
1006 li(A0, (long)msg);
1007 addi(SP, SP, -1 * wordSize);
1008 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
1009 delayed()->nop();
1010 addi(SP, SP, 1 * wordSize);
1011 lw(A0, SP, -1 * wordSize);
1012 addi(SP, SP, 4);
1013 popad();
1014 #endif
1015 }
1017 void MacroAssembler::print_reg(Register reg) {
1018 /*
1019 char *s = getenv("PRINT_REG");
1020 if (s == NULL)
1021 return;
1022 if (strcmp(s, "1") != 0)
1023 return;
1024 */
1025 void * cur_pc = pc();
1026 pushad();
1027 NOT_LP64(push(FP);)
1029 li(A0, (long)reg->name());
1030 if (reg == SP)
1031 addiu(A1, SP, wordSize * 23); //23 registers saved in pushad()
1032 else if (reg == A0)
1033 ld(A1, SP, wordSize * 19); //A0 has been modified by li(A0, (long)reg->name()). Ugly Code!
1034 else
1035 move(A1, reg);
1036 li(A2, (long)cur_pc);
1037 push(S2);
1038 move(AT, -(StackAlignmentInBytes));
1039 move(S2, SP); // use S2 as a sender SP holder
1040 andr(SP, SP, AT); // align stack as required by ABI
1041 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_reg_with_pc),relocInfo::runtime_call_type);
1042 delayed()->nop();
1043 move(SP, S2); // use S2 as a sender SP holder
1044 pop(S2);
1045 NOT_LP64(pop(FP);)
1046 popad();
1048 /*
1049 pushad();
1050 #ifdef _LP64
1051 if (reg == SP)
1052 addiu(A0, SP, wordSize * 23); //23 registers saved in pushad()
1053 else
1054 move(A0, reg);
1055 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_long),relocInfo::runtime_call_type);
1056 delayed()->nop();
1057 #else
1058 push(FP);
1059 move(A0, reg);
1060 dsrl32(A1, reg, 0);
1061 //call(CAST_FROM_FN_PTR(address, SharedRuntime::print_int),relocInfo::runtime_call_type);
1062 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_long),relocInfo::runtime_call_type);
1063 delayed()->nop();
1064 pop(FP);
1065 #endif
1066 popad();
1067 pushad();
1068 NOT_LP64(push(FP);)
1069 char b[50];
1070 sprintf((char *)b, " pc: %p\n",cur_pc);
1071 li(A0, (long)(char *)b);
1072 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1073 delayed()->nop();
1074 NOT_LP64(pop(FP);)
1075 popad();
1076 */
1077 }
1079 void MacroAssembler::print_reg(FloatRegister reg) {
1080 void * cur_pc = pc();
1081 pushad();
1082 NOT_LP64(push(FP);)
1083 li(A0, (long)reg->name());
1084 push(S2);
1085 move(AT, -(StackAlignmentInBytes));
1086 move(S2, SP); // use S2 as a sender SP holder
1087 andr(SP, SP, AT); // align stack as required by ABI
1088 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1089 delayed()->nop();
1090 move(SP, S2); // use S2 as a sender SP holder
1091 pop(S2);
1092 NOT_LP64(pop(FP);)
1093 popad();
1095 pushad();
1096 NOT_LP64(push(FP);)
1097 #if 1
1098 move(FP, SP);
1099 move(AT, -(StackAlignmentInBytes));
1100 andr(SP , SP , AT);
1101 mov_d(F12, reg);
1102 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_double),relocInfo::runtime_call_type);
1103 delayed()->nop();
1104 move(SP, FP);
1105 #else
1106 mov_s(F12, reg);
1107 //call(CAST_FROM_FN_PTR(address, SharedRuntime::print_float),relocInfo::runtime_call_type);
1108 //delayed()->nop();
1109 #endif
1110 NOT_LP64(pop(FP);)
1111 popad();
1113 #if 0
1114 pushad();
1115 NOT_LP64(push(FP);)
1116 char* b = new char[50];
1117 sprintf(b, " pc: %p\n", cur_pc);
1118 li(A0, (long)b);
1119 call(CAST_FROM_FN_PTR(address, SharedRuntime::print_str),relocInfo::runtime_call_type);
1120 delayed()->nop();
1121 NOT_LP64(pop(FP);)
1122 popad();
1123 #endif
1124 }
1126 void MacroAssembler::increment(Register reg, int imm) {
1127 if (!imm) return;
1128 if (is_simm16(imm)) {
1129 #ifdef _LP64
1130 daddiu(reg, reg, imm);
1131 #else
1132 addiu(reg, reg, imm);
1133 #endif
1134 } else {
1135 move(AT, imm);
1136 #ifdef _LP64
1137 daddu(reg, reg, AT);
1138 #else
1139 addu(reg, reg, AT);
1140 #endif
1141 }
1142 }
1144 void MacroAssembler::decrement(Register reg, int imm) {
1145 increment(reg, -imm);
1146 }
1149 void MacroAssembler::call_VM(Register oop_result,
1150 address entry_point,
1151 bool check_exceptions) {
1152 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1153 }
1155 void MacroAssembler::call_VM(Register oop_result,
1156 address entry_point,
1157 Register arg_1,
1158 bool check_exceptions) {
1159 if (arg_1!=A1) move(A1, arg_1);
1160 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1161 }
1163 void MacroAssembler::call_VM(Register oop_result,
1164 address entry_point,
1165 Register arg_1,
1166 Register arg_2,
1167 bool check_exceptions) {
1168 if (arg_1!=A1) move(A1, arg_1);
1169 if (arg_2!=A2) move(A2, arg_2);
1170 assert(arg_2 != A1, "smashed argument");
1171 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1172 }
1174 void MacroAssembler::call_VM(Register oop_result,
1175 address entry_point,
1176 Register arg_1,
1177 Register arg_2,
1178 Register arg_3,
1179 bool check_exceptions) {
1180 if (arg_1!=A1) move(A1, arg_1);
1181 if (arg_2!=A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1182 if (arg_3!=A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument");
1183 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1184 }
1186 void MacroAssembler::call_VM(Register oop_result,
1187 Register last_java_sp,
1188 address entry_point,
1189 int number_of_arguments,
1190 bool check_exceptions) {
1191 call_VM_base(oop_result, NOREG, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1192 }
1194 void MacroAssembler::call_VM(Register oop_result,
1195 Register last_java_sp,
1196 address entry_point,
1197 Register arg_1,
1198 bool check_exceptions) {
1199 if (arg_1 != A1) move(A1, arg_1);
1200 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1201 }
1203 void MacroAssembler::call_VM(Register oop_result,
1204 Register last_java_sp,
1205 address entry_point,
1206 Register arg_1,
1207 Register arg_2,
1208 bool check_exceptions) {
1209 if (arg_1 != A1) move(A1, arg_1);
1210 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1211 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1212 }
1214 void MacroAssembler::call_VM(Register oop_result,
1215 Register last_java_sp,
1216 address entry_point,
1217 Register arg_1,
1218 Register arg_2,
1219 Register arg_3,
1220 bool check_exceptions) {
1221 if (arg_1 != A1) move(A1, arg_1);
1222 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A1, "smashed argument");
1223 if (arg_3 != A3) move(A3, arg_3); assert(arg_3 != A1 && arg_3 != A2, "smashed argument");
1224 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1225 }
1227 void MacroAssembler::call_VM_base(Register oop_result,
1228 Register java_thread,
1229 Register last_java_sp,
1230 address entry_point,
1231 int number_of_arguments,
1232 bool check_exceptions) {
1234 address before_call_pc;
1235 // determine java_thread register
1236 if (!java_thread->is_valid()) {
1237 #ifndef OPT_THREAD
1238 java_thread = T2;
1239 get_thread(java_thread);
1240 #else
1241 java_thread = TREG;
1242 #endif
1243 }
1244 // determine last_java_sp register
1245 if (!last_java_sp->is_valid()) {
1246 last_java_sp = SP;
1247 }
1248 // debugging support
1249 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1250 assert(number_of_arguments <= 4 , "cannot have negative number of arguments");
1251 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1252 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1254 assert(last_java_sp != FP, "this code doesn't work for last_java_sp == fp, which currently can't portably work anyway since C2 doesn't save ebp");
1256 // set last Java frame before call
1257 before_call_pc = (address)pc();
1258 set_last_Java_frame(java_thread, last_java_sp, FP, before_call_pc);
1260 // do the call
1261 move(A0, java_thread);
1262 call(entry_point, relocInfo::runtime_call_type);
1263 delayed()->nop();
1265 // restore the thread (cannot use the pushed argument since arguments
1266 // may be overwritten by C code generated by an optimizing compiler);
1267 // however can use the register value directly if it is callee saved.
1268 #ifndef OPT_THREAD
1269 get_thread(java_thread);
1270 #else
1271 #ifdef ASSERT
1272 {
1273 Label L;
1274 get_thread(AT);
1275 beq(java_thread, AT, L);
1276 delayed()->nop();
1277 stop("MacroAssembler::call_VM_base: TREG not callee saved?");
1278 bind(L);
1279 }
1280 #endif
1281 #endif
1283 // discard thread and arguments
1284 ld_ptr(SP, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1285 // reset last Java frame
1286 reset_last_Java_frame(java_thread, false, true);
1288 check_and_handle_popframe(java_thread);
1289 check_and_handle_earlyret(java_thread);
1290 if (check_exceptions) {
1291 // check for pending exceptions (java_thread is set upon return)
1292 Label L;
1293 #ifdef _LP64
1294 ld(AT, java_thread, in_bytes(Thread::pending_exception_offset()));
1295 #else
1296 lw(AT, java_thread, in_bytes(Thread::pending_exception_offset()));
1297 #endif
1298 beq(AT, R0, L);
1299 delayed()->nop();
1300 li(AT, before_call_pc);
1301 push(AT);
1302 jmp(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1303 delayed()->nop();
1304 bind(L);
1305 }
1307 // get oop result if there is one and reset the value in the thread
1308 if (oop_result->is_valid()) {
1309 #ifdef _LP64
1310 ld(oop_result, java_thread, in_bytes(JavaThread::vm_result_offset()));
1311 sd(R0, java_thread, in_bytes(JavaThread::vm_result_offset()));
1312 #else
1313 lw(oop_result, java_thread, in_bytes(JavaThread::vm_result_offset()));
1314 sw(R0, java_thread, in_bytes(JavaThread::vm_result_offset()));
1315 #endif
1316 verify_oop(oop_result);
1317 }
1318 }
1320 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1322 move(V0, SP);
1323 //we also reserve space for java_thread here
1324 #ifndef _LP64
1325 daddi(SP, SP, (1 + number_of_arguments) * (- wordSize));
1326 #endif
1327 move(AT, -(StackAlignmentInBytes));
1328 andr(SP, SP, AT);
1329 call_VM_base(oop_result, NOREG, V0, entry_point, number_of_arguments, check_exceptions);
1331 }
1333 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1334 call_VM_leaf_base(entry_point, number_of_arguments);
1335 }
1337 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1338 if (arg_0 != A0) move(A0, arg_0);
1339 call_VM_leaf(entry_point, 1);
1340 }
1342 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1343 if (arg_0 != A0) move(A0, arg_0);
1344 if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument");
1345 call_VM_leaf(entry_point, 2);
1346 }
1348 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1349 if (arg_0 != A0) move(A0, arg_0);
1350 if (arg_1 != A1) move(A1, arg_1); assert(arg_1 != A0, "smashed argument");
1351 if (arg_2 != A2) move(A2, arg_2); assert(arg_2 != A0 && arg_2 != A1, "smashed argument");
1352 call_VM_leaf(entry_point, 3);
1353 }
1354 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1355 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1356 }
1359 void MacroAssembler::super_call_VM_leaf(address entry_point,
1360 Register arg_1) {
1361 if (arg_1 != A0) move(A0, arg_1);
1362 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1363 }
1366 void MacroAssembler::super_call_VM_leaf(address entry_point,
1367 Register arg_1,
1368 Register arg_2) {
1369 if (arg_1 != A0) move(A0, arg_1);
1370 if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument");
1371 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1372 }
1373 void MacroAssembler::super_call_VM_leaf(address entry_point,
1374 Register arg_1,
1375 Register arg_2,
1376 Register arg_3) {
1377 if (arg_1 != A0) move(A0, arg_1);
1378 if (arg_2 != A1) move(A1, arg_2); assert(arg_2 != A0, "smashed argument");
1379 if (arg_3 != A2) move(A2, arg_3); assert(arg_3 != A0 && arg_3 != A1, "smashed argument");
1380 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1381 }
1383 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1384 }
1386 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1387 }
1389 void MacroAssembler::null_check(Register reg, int offset) {
1390 if (needs_explicit_null_check(offset)) {
1391 // provoke OS NULL exception if reg = NULL by
1392 // accessing M[reg] w/o changing any (non-CC) registers
1393 // NOTE: cmpl is plenty here to provoke a segv
1394 lw(AT, reg, 0);
1395 // Note: should probably use testl(rax, Address(reg, 0));
1396 // may be shorter code (however, this version of
1397 // testl needs to be implemented first)
1398 } else {
1399 // nothing to do, (later) access of M[reg + offset]
1400 // will provoke OS NULL exception if reg = NULL
1401 }
1402 }
1404 void MacroAssembler::enter() {
1405 push2(RA, FP);
1406 move(FP, SP);
1407 }
1409 void MacroAssembler::leave() {
1410 #ifndef _LP64
1411 //move(SP, FP);
1412 //pop2(FP, RA);
1413 addi(SP, FP, 2 * wordSize);
1414 lw(RA, SP, - 1 * wordSize);
1415 lw(FP, SP, - 2 * wordSize);
1416 #else
1417 daddi(SP, FP, 2 * wordSize);
1418 ld(RA, SP, - 1 * wordSize);
1419 ld(FP, SP, - 2 * wordSize);
1420 #endif
1421 }
1422 /*
1423 void MacroAssembler::os_breakpoint() {
1424 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
1425 // (e.g., MSVC can't call ps() otherwise)
1426 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
1427 }
1428 */
1429 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
1430 // determine java_thread register
1431 if (!java_thread->is_valid()) {
1432 #ifndef OPT_THREAD
1433 java_thread = T1;
1434 get_thread(java_thread);
1435 #else
1436 java_thread = TREG;
1437 #endif
1438 }
1439 // we must set sp to zero to clear frame
1440 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1441 // must clear fp, so that compiled frames are not confused; it is possible
1442 // that we need it only for debugging
1443 if(clear_fp)
1444 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_fp_offset()));
1446 if (clear_pc)
1447 st_ptr(R0, java_thread, in_bytes(JavaThread::last_Java_pc_offset()));
1448 }
1450 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
1451 bool clear_pc) {
1452 Register thread = TREG;
1453 #ifndef OPT_THREAD
1454 get_thread(thread);
1455 #endif
1456 // we must set sp to zero to clear frame
1457 sd(R0, Address(thread, JavaThread::last_Java_sp_offset()));
1458 // must clear fp, so that compiled frames are not confused; it is
1459 // possible that we need it only for debugging
1460 if (clear_fp) {
1461 sd(R0, Address(thread, JavaThread::last_Java_fp_offset()));
1462 }
1464 if (clear_pc) {
1465 sd(R0, Address(thread, JavaThread::last_Java_pc_offset()));
1466 }
1467 }
1469 // Write serialization page so VM thread can do a pseudo remote membar.
1470 // We use the current thread pointer to calculate a thread specific
1471 // offset to write to within the page. This minimizes bus traffic
1472 // due to cache line collision.
1473 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
1474 move(tmp, thread);
1475 srl(tmp, tmp,os::get_serialize_page_shift_count());
1476 move(AT, (os::vm_page_size() - sizeof(int)));
1477 andr(tmp, tmp,AT);
1478 sw(tmp,Address(tmp, (intptr_t)os::get_memory_serialize_page()));
1479 }
1481 // Calls to C land
1482 //
1483 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
1484 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
1485 // has to be reset to 0. This is required to allow proper stack traversal.
1486 void MacroAssembler::set_last_Java_frame(Register java_thread,
1487 Register last_java_sp,
1488 Register last_java_fp,
1489 address last_java_pc) {
1490 // determine java_thread register
1491 if (!java_thread->is_valid()) {
1492 #ifndef OPT_THREAD
1493 java_thread = T2;
1494 get_thread(java_thread);
1495 #else
1496 java_thread = TREG;
1497 #endif
1498 }
1499 // determine last_java_sp register
1500 if (!last_java_sp->is_valid()) {
1501 last_java_sp = SP;
1502 }
1504 // last_java_fp is optional
1506 if (last_java_fp->is_valid()) {
1507 st_ptr(last_java_fp, java_thread, in_bytes(JavaThread::last_Java_fp_offset()));
1508 }
1510 // last_java_pc is optional
1512 if (last_java_pc != NULL) {
1513 relocate(relocInfo::internal_pc_type);
1514 patchable_set48(AT, (long)last_java_pc);
1515 st_ptr(AT, java_thread, in_bytes(JavaThread::last_Java_pc_offset()));
1516 }
1517 st_ptr(last_java_sp, java_thread, in_bytes(JavaThread::last_Java_sp_offset()));
1518 }
1520 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
1521 Register last_java_fp,
1522 address last_java_pc) {
1523 // determine last_java_sp register
1524 if (!last_java_sp->is_valid()) {
1525 last_java_sp = SP;
1526 }
1528 Register thread = TREG;
1529 #ifndef OPT_THREAD
1530 get_thread(thread);
1531 #endif
1532 // last_java_fp is optional
1533 if (last_java_fp->is_valid()) {
1534 sd(last_java_fp, Address(thread, JavaThread::last_Java_fp_offset()));
1535 }
1537 // last_java_pc is optional
1538 if (last_java_pc != NULL) {
1539 Address java_pc(thread,
1540 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1541 li(AT, (intptr_t)(last_java_pc));
1542 sd(AT, java_pc);
1543 }
1545 sd(last_java_sp, Address(thread, JavaThread::last_Java_sp_offset()));
1546 }
1548 //////////////////////////////////////////////////////////////////////////////////
1549 #if INCLUDE_ALL_GCS
1551 void MacroAssembler::g1_write_barrier_pre(Register obj,
1552 Register pre_val,
1553 Register thread,
1554 Register tmp,
1555 bool tosca_live,
1556 bool expand_call) {
1558 // If expand_call is true then we expand the call_VM_leaf macro
1559 // directly to skip generating the check by
1560 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
1562 #ifdef _LP64
1563 assert(thread == TREG, "must be");
1564 #endif // _LP64
1566 Label done;
1567 Label runtime;
1569 assert(pre_val != noreg, "check this code");
1571 if (obj != noreg) {
1572 assert_different_registers(obj, pre_val, tmp);
1573 assert(pre_val != V0, "check this code");
1574 }
1576 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1577 PtrQueue::byte_offset_of_active()));
1578 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1579 PtrQueue::byte_offset_of_index()));
1580 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1581 PtrQueue::byte_offset_of_buf()));
1584 // Is marking active?
1585 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
1586 lw(AT, in_progress);
1587 } else {
1588 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
1589 lb(AT, in_progress);
1590 }
1591 beq(AT, R0, done);
1592 delayed()->nop();
1594 // Do we need to load the previous value?
1595 if (obj != noreg) {
1596 load_heap_oop(pre_val, Address(obj, 0));
1597 }
1599 // Is the previous value null?
1600 beq(pre_val, R0, done);
1601 delayed()->nop();
1603 // Can we store original value in the thread's buffer?
1604 // Is index == 0?
1605 // (The index field is typed as size_t.)
1607 ld(tmp, index);
1608 beq(tmp, R0, runtime);
1609 delayed()->nop();
1611 daddiu(tmp, tmp, -1 * wordSize);
1612 sd(tmp, index);
1613 ld(AT, buffer);
1614 daddu(tmp, tmp, AT);
1616 // Record the previous value
1617 sd(pre_val, tmp, 0);
1618 beq(R0, R0, done);
1619 delayed()->nop();
1621 bind(runtime);
1622 // save the live input values
1623 if (tosca_live) push(V0);
1625 if (obj != noreg && obj != V0) push(obj);
1627 if (pre_val != V0) push(pre_val);
1629 // Calling the runtime using the regular call_VM_leaf mechanism generates
1630 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
1631 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
1632 //
1633 // If we care generating the pre-barrier without a frame (e.g. in the
1634 // intrinsified Reference.get() routine) then ebp might be pointing to
1635 // the caller frame and so this check will most likely fail at runtime.
1636 //
1637 // Expanding the call directly bypasses the generation of the check.
1638 // So when we do not have have a full interpreter frame on the stack
1639 // expand_call should be passed true.
1641 NOT_LP64( push(thread); )
1643 if (expand_call) {
1644 LP64_ONLY( assert(pre_val != A1, "smashed arg"); )
1645 if (thread != A1) move(A1, thread);
1646 if (pre_val != A0) move(A0, pre_val);
1647 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
1648 } else {
1649 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
1650 }
1652 NOT_LP64( pop(thread); )
1654 // save the live input values
1655 if (pre_val != V0)
1656 pop(pre_val);
1658 if (obj != noreg && obj != V0)
1659 pop(obj);
1661 if(tosca_live) pop(V0);
1663 bind(done);
1664 }
1666 void MacroAssembler::g1_write_barrier_post(Register store_addr,
1667 Register new_val,
1668 Register thread,
1669 Register tmp,
1670 Register tmp2) {
1671 assert(tmp != AT, "must be");
1672 assert(tmp2 != AT, "must be");
1673 #ifdef _LP64
1674 assert(thread == TREG, "must be");
1675 #endif // _LP64
1677 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1678 PtrQueue::byte_offset_of_index()));
1679 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1680 PtrQueue::byte_offset_of_buf()));
1682 BarrierSet* bs = Universe::heap()->barrier_set();
1683 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
1684 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1686 Label done;
1687 Label runtime;
1689 // Does store cross heap regions?
1690 xorr(AT, store_addr, new_val);
1691 dsrl(AT, AT, HeapRegion::LogOfHRGrainBytes);
1692 beq(AT, R0, done);
1693 delayed()->nop();
1696 // crosses regions, storing NULL?
1697 beq(new_val, R0, done);
1698 delayed()->nop();
1700 // storing region crossing non-NULL, is card already dirty?
1701 const Register card_addr = tmp;
1702 const Register cardtable = tmp2;
1704 move(card_addr, store_addr);
1705 dsrl(card_addr, card_addr, CardTableModRefBS::card_shift);
1706 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
1707 // a valid address and therefore is not properly handled by the relocation code.
1708 set64(cardtable, (intptr_t)ct->byte_map_base);
1709 daddu(card_addr, card_addr, cardtable);
1711 lb(AT, card_addr, 0);
1712 daddiu(AT, AT, -1 * (int)G1SATBCardTableModRefBS::g1_young_card_val());
1713 beq(AT, R0, done);
1714 delayed()->nop();
1716 sync();
1717 lb(AT, card_addr, 0);
1718 daddiu(AT, AT, -1 * (int)(int)CardTableModRefBS::dirty_card_val());
1719 beq(AT, R0, done);
1720 delayed()->nop();
1723 // storing a region crossing, non-NULL oop, card is clean.
1724 // dirty card and log.
1725 move(AT, (int)CardTableModRefBS::dirty_card_val());
1726 sb(AT, card_addr, 0);
1728 lw(AT, queue_index);
1729 beq(AT, R0, runtime);
1730 delayed()->nop();
1731 daddiu(AT, AT, -1 * wordSize);
1732 sw(AT, queue_index);
1733 ld(tmp2, buffer);
1734 #ifdef _LP64
1735 ld(AT, queue_index);
1736 daddu(tmp2, tmp2, AT);
1737 sd(card_addr, tmp2, 0);
1738 #else
1739 lw(AT, queue_index);
1740 addu32(tmp2, tmp2, AT);
1741 sw(card_addr, tmp2, 0);
1742 #endif
1743 beq(R0, R0, done);
1744 delayed()->nop();
1746 bind(runtime);
1747 // save the live input values
1748 push(store_addr);
1749 push(new_val);
1750 #ifdef _LP64
1751 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, TREG);
1752 #else
1753 push(thread);
1754 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
1755 pop(thread);
1756 #endif
1757 pop(new_val);
1758 pop(store_addr);
1760 bind(done);
1761 }
1763 #endif // INCLUDE_ALL_GCS
1764 //////////////////////////////////////////////////////////////////////////////////
1767 void MacroAssembler::store_check(Register obj) {
1768 // Does a store check for the oop in register obj. The content of
1769 // register obj is destroyed afterwards.
1770 store_check_part_1(obj);
1771 store_check_part_2(obj);
1772 }
1774 void MacroAssembler::store_check(Register obj, Address dst) {
1775 store_check(obj);
1776 }
1779 // split the store check operation so that other instructions can be scheduled inbetween
1780 void MacroAssembler::store_check_part_1(Register obj) {
1781 BarrierSet* bs = Universe::heap()->barrier_set();
1782 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
1783 #ifdef _LP64
1784 dsrl(obj, obj, CardTableModRefBS::card_shift);
1785 #else
1786 shr(obj, CardTableModRefBS::card_shift);
1787 #endif
1788 }
1790 void MacroAssembler::store_check_part_2(Register obj) {
1791 BarrierSet* bs = Universe::heap()->barrier_set();
1792 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
1793 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
1794 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1796 set64(AT, (long)ct->byte_map_base);
1797 #ifdef _LP64
1798 dadd(AT, AT, obj);
1799 #else
1800 add(AT, AT, obj);
1801 #endif
1802 if (UseConcMarkSweepGC) sync();
1803 sb(R0, AT, 0);
1804 }
1806 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
1807 void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
1808 Register t1, Register t2, Label& slow_case) {
1809 assert_different_registers(obj, var_size_in_bytes, t1, t2, AT);
1811 Register end = t2;
1812 #ifndef OPT_THREAD
1813 Register thread = t1;
1814 get_thread(thread);
1815 #else
1816 Register thread = TREG;
1817 #endif
1818 verify_tlab(t1, t2);//blows t1&t2
1820 ld_ptr(obj, thread, in_bytes(JavaThread::tlab_top_offset()));
1822 if (var_size_in_bytes == NOREG) {
1823 // i dont think we need move con_size_in_bytes to a register first.
1824 // by yjl 8/17/2005
1825 assert(is_simm16(con_size_in_bytes), "fixme by moving imm to a register first");
1826 addi(end, obj, con_size_in_bytes);
1827 } else {
1828 add(end, obj, var_size_in_bytes);
1829 }
1831 ld_ptr(AT, thread, in_bytes(JavaThread::tlab_end_offset()));
1832 sltu(AT, AT, end);
1833 bne_far(AT, R0, slow_case);
1834 delayed()->nop();
1837 // update the tlab top pointer
1838 st_ptr(end, thread, in_bytes(JavaThread::tlab_top_offset()));
1840 // recover var_size_in_bytes if necessary
1841 /*if (var_size_in_bytes == end) {
1842 sub(var_size_in_bytes, end, obj);
1843 }*/
1845 verify_tlab(t1, t2);
1846 }
1848 // Defines obj, preserves var_size_in_bytes
1849 void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
1850 Register t1, Register t2, Label& slow_case) {
1851 assert_different_registers(obj, var_size_in_bytes, t1, AT);
1852 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
1853 // No allocation in the shared eden.
1854 b_far(slow_case);
1855 delayed()->nop();
1856 } else {
1858 #ifndef _LP64
1859 Address heap_top(t1, Assembler::split_low((intptr_t)Universe::heap()->top_addr()));
1860 lui(t1, split_high((intptr_t)Universe::heap()->top_addr()));
1861 #else
1862 Address heap_top(t1);
1863 li(t1, (long)Universe::heap()->top_addr());
1864 #endif
1865 ld_ptr(obj, heap_top);
1867 Register end = t2;
1868 Label retry;
1870 bind(retry);
1871 if (var_size_in_bytes == NOREG) {
1872 // i dont think we need move con_size_in_bytes to a register first.
1873 assert(is_simm16(con_size_in_bytes), "fixme by moving imm to a register first");
1874 addi(end, obj, con_size_in_bytes);
1875 } else {
1876 add(end, obj, var_size_in_bytes);
1877 }
1878 // if end < obj then we wrapped around => object too long => slow case
1879 sltu(AT, end, obj);
1880 bne_far(AT, R0, slow_case);
1881 delayed()->nop();
1883 li(AT, (long)Universe::heap()->end_addr());
1884 ld_ptr(AT, AT, 0);
1885 sltu(AT, AT, end);
1886 bne_far(AT, R0, slow_case);
1887 delayed()->nop();
1888 // Compare obj with the top addr, and if still equal, store the new top addr in
1889 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
1890 // it otherwise. Use lock prefix for atomicity on MPs.
1891 //if (os::is_MP()) {
1892 // sync();
1893 //}
1895 // if someone beat us on the allocation, try again, otherwise continue
1896 cmpxchg(end, heap_top, obj);
1897 beq_far(AT, R0, retry); //by yyq
1898 delayed()->nop();
1899 }
1900 }
1902 // C2 doesn't invoke this one.
1903 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
1904 Register top = T0;
1905 Register t1 = T1;
1906 Register t2 = T9;
1907 Register t3 = T3;
1908 Register thread_reg = T8;
1909 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ T2, A4);
1910 Label do_refill, discard_tlab;
1912 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { //by yyq
1913 // No allocation in the shared eden.
1914 b(slow_case);
1915 delayed()->nop();
1916 }
1918 get_thread(thread_reg);
1920 ld_ptr(top, thread_reg, in_bytes(JavaThread::tlab_top_offset()));
1921 ld_ptr(t1, thread_reg, in_bytes(JavaThread::tlab_end_offset()));
1923 // calculate amount of free space
1924 sub(t1, t1, top);
1925 shr(t1, LogHeapWordSize);
1927 // Retain tlab and allocate object in shared space if
1928 // the amount free in the tlab is too large to discard.
1929 ld_ptr(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
1930 slt(AT, t2, t1);
1931 beq(AT, R0, discard_tlab);
1932 delayed()->nop();
1934 // Retain
1935 #ifndef _LP64
1936 move(AT, ThreadLocalAllocBuffer::refill_waste_limit_increment());
1937 #else
1938 li(AT, ThreadLocalAllocBuffer::refill_waste_limit_increment());
1939 #endif
1940 add(t2, t2, AT);
1941 st_ptr(t2, thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
1943 if (TLABStats) {
1944 // increment number of slow_allocations
1945 lw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset()));
1946 addiu(AT, AT, 1);
1947 sw(AT, thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset()));
1948 }
1949 b(try_eden);
1950 delayed()->nop();
1952 bind(discard_tlab);
1953 if (TLABStats) {
1954 // increment number of refills
1955 lw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset()));
1956 addi(AT, AT, 1);
1957 sw(AT, thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset()));
1958 // accumulate wastage -- t1 is amount free in tlab
1959 lw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
1960 add(AT, AT, t1);
1961 sw(AT, thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
1962 }
1964 // if tlab is currently allocated (top or end != null) then
1965 // fill [top, end + alignment_reserve) with array object
1966 beq(top, R0, do_refill);
1967 delayed()->nop();
1969 // set up the mark word
1970 li(AT, (long)markOopDesc::prototype()->copy_set_hash(0x2));
1971 st_ptr(AT, top, oopDesc::mark_offset_in_bytes());
1973 // set the length to the remaining space
1974 addi(t1, t1, - typeArrayOopDesc::header_size(T_INT));
1975 addi(t1, t1, ThreadLocalAllocBuffer::alignment_reserve());
1976 shl(t1, log2_intptr(HeapWordSize/sizeof(jint)));
1977 sw(t1, top, arrayOopDesc::length_offset_in_bytes());
1979 // set klass to intArrayKlass
1980 #ifndef _LP64
1981 lui(AT, split_high((intptr_t)Universe::intArrayKlassObj_addr()));
1982 lw(t1, AT, split_low((intptr_t)Universe::intArrayKlassObj_addr()));
1983 #else
1984 li(AT, (intptr_t)Universe::intArrayKlassObj_addr());
1985 ld_ptr(t1, AT, 0);
1986 #endif
1987 //st_ptr(t1, top, oopDesc::klass_offset_in_bytes());
1988 store_klass(top, t1);
1990 // refill the tlab with an eden allocation
1991 bind(do_refill);
1992 ld_ptr(t1, thread_reg, in_bytes(JavaThread::tlab_size_offset()));
1993 shl(t1, LogHeapWordSize);
1994 // add object_size ??
1995 eden_allocate(top, t1, 0, t2, t3, slow_case);
1997 // Check that t1 was preserved in eden_allocate.
1998 #ifdef ASSERT
1999 if (UseTLAB) {
2000 Label ok;
2001 assert_different_registers(thread_reg, t1);
2002 ld_ptr(AT, thread_reg, in_bytes(JavaThread::tlab_size_offset()));
2003 shl(AT, LogHeapWordSize);
2004 beq(AT, t1, ok);
2005 delayed()->nop();
2006 stop("assert(t1 != tlab size)");
2007 should_not_reach_here();
2009 bind(ok);
2010 }
2011 #endif
2012 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_start_offset()));
2013 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_top_offset()));
2014 add(top, top, t1);
2015 addi(top, top, - ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
2016 st_ptr(top, thread_reg, in_bytes(JavaThread::tlab_end_offset()));
2017 verify_tlab(t1, t2);
2018 b(retry);
2019 delayed()->nop();
2020 }
2022 static const double pi_4 = 0.7853981633974483;
2024 // the x86 version is to clumsy, i dont think we need that fuss. maybe i'm wrong, FIXME
2025 // must get argument(a double) in F12/F13
2026 //void MacroAssembler::trigfunc(char trig, bool preserve_cpu_regs, int num_fpu_regs_in_use) {
2027 //We need to preseve the register which maybe modified during the Call @Jerome
2028 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
2029 //save all modified register here
2030 // if (preserve_cpu_regs) {
2031 // }
2032 //FIXME, in the disassembly of tirgfunc, only used V0,V1,T9, SP,RA,so we ony save V0,V1,T9
2033 pushad();
2034 //we should preserve the stack space before we call
2035 addi(SP, SP, -wordSize * 2);
2036 switch (trig){
2037 case 's' :
2038 call( CAST_FROM_FN_PTR(address, SharedRuntime::dsin), relocInfo::runtime_call_type );
2039 delayed()->nop();
2040 break;
2041 case 'c':
2042 call( CAST_FROM_FN_PTR(address, SharedRuntime::dcos), relocInfo::runtime_call_type );
2043 delayed()->nop();
2044 break;
2045 case 't':
2046 call( CAST_FROM_FN_PTR(address, SharedRuntime::dtan), relocInfo::runtime_call_type );
2047 delayed()->nop();
2048 break;
2049 default:assert (false, "bad intrinsic");
2050 break;
2052 }
2054 addi(SP, SP, wordSize * 2);
2055 popad();
2056 // if (preserve_cpu_regs) {
2057 // }
2058 }
2060 #ifdef _LP64
2061 void MacroAssembler::li(Register rd, long imm) {
2062 if (imm <= max_jint && imm >= min_jint) {
2063 li32(rd, (int)imm);
2064 } else if (julong(imm) <= 0xFFFFFFFF) {
2065 assert_not_delayed();
2066 // lui sign-extends, so we can't use that.
2067 ori(rd, R0, julong(imm) >> 16);
2068 dsll(rd, rd, 16);
2069 ori(rd, rd, split_low(imm));
2070 //aoqi_test
2071 //} else if ((imm > 0) && ((imm >> 48) == 0)) {
2072 } else if ((imm > 0) && is_simm16(imm >> 32)) {
2073 /* A 48-bit address */
2074 li48(rd, imm);
2075 } else {
2076 li64(rd, imm);
2077 }
2078 }
2079 #else
2080 void MacroAssembler::li(Register rd, long imm) {
2081 li32(rd, (int)imm);
2082 }
2083 #endif
2085 void MacroAssembler::li32(Register reg, int imm) {
2086 if (is_simm16(imm)) {
2087 /* Jin: for imm < 0, we should use addi instead of addiu.
2088 *
2089 * java.lang.StringCoding$StringDecoder.decode(jobject, jint, jint)
2090 *
2091 * 78 move [int:-1|I] [a0|I]
2092 * : daddi a0, zero, 0xffffffff (correct)
2093 * : daddiu a0, zero, 0xffffffff (incorrect)
2094 */
2095 if (imm >= 0)
2096 addiu(reg, R0, imm);
2097 else
2098 addi(reg, R0, imm);
2099 } else {
2100 lui(reg, split_low(imm >> 16));
2101 if (split_low(imm))
2102 ori(reg, reg, split_low(imm));
2103 }
2104 }
2106 #ifdef _LP64
2107 void MacroAssembler::set64(Register d, jlong value) {
2108 assert_not_delayed();
2110 int hi = (int)(value >> 32);
2111 int lo = (int)(value & ~0);
2113 if (value == lo) { // 32-bit integer
2114 if (is_simm16(value)) {
2115 daddiu(d, R0, value);
2116 } else {
2117 lui(d, split_low(value >> 16));
2118 if (split_low(value)) {
2119 ori(d, d, split_low(value));
2120 }
2121 }
2122 } else if (hi == 0) { // hardware zero-extends to upper 32
2123 ori(d, R0, julong(value) >> 16);
2124 dsll(d, d, 16);
2125 if (split_low(value)) {
2126 ori(d, d, split_low(value));
2127 }
2128 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2129 // 4 insts
2130 li48(d, value);
2131 } else { // li64
2132 // 6 insts
2133 li64(d, value);
2134 }
2135 }
2138 int MacroAssembler::insts_for_set64(jlong value) {
2139 int hi = (int)(value >> 32);
2140 int lo = (int)(value & ~0);
2142 int count = 0;
2144 if (value == lo) { // 32-bit integer
2145 if (is_simm16(value)) {
2146 //daddiu(d, R0, value);
2147 count++;
2148 } else {
2149 //lui(d, split_low(value >> 16));
2150 count++;
2151 if (split_low(value)) {
2152 //ori(d, d, split_low(value));
2153 count++;
2154 }
2155 }
2156 } else if (hi == 0) { // hardware zero-extends to upper 32
2157 //ori(d, R0, julong(value) >> 16);
2158 //dsll(d, d, 16);
2159 count += 2;
2160 if (split_low(value)) {
2161 //ori(d, d, split_low(value));
2162 count++;
2163 }
2164 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2165 // 4 insts
2166 //li48(d, value);
2167 count += 4;
2168 } else { // li64
2169 // 6 insts
2170 //li64(d, value);
2171 count += 6;
2172 }
2174 return count;
2175 }
2177 void MacroAssembler::patchable_set48(Register d, jlong value) {
2178 assert_not_delayed();
2180 int hi = (int)(value >> 32);
2181 int lo = (int)(value & ~0);
2183 int count = 0;
2185 if (value == lo) { // 32-bit integer
2186 if (is_simm16(value)) {
2187 daddiu(d, R0, value);
2188 count += 1;
2189 } else {
2190 lui(d, split_low(value >> 16));
2191 count += 1;
2192 if (split_low(value)) {
2193 ori(d, d, split_low(value));
2194 count += 1;
2195 }
2196 }
2197 } else if (hi == 0) { // hardware zero-extends to upper 32
2198 ori(d, R0, julong(value) >> 16);
2199 dsll(d, d, 16);
2200 count += 2;
2201 if (split_low(value)) {
2202 ori(d, d, split_low(value));
2203 count += 1;
2204 }
2205 } else if ((value> 0) && is_simm16(value >> 32)) { // li48
2206 // 4 insts
2207 li48(d, value);
2208 count += 4;
2209 } else { // li64
2210 tty->print_cr("value = 0x%x", value);
2211 guarantee(false, "Not supported yet !");
2212 }
2214 for (count; count < 4; count++) {
2215 nop();
2216 }
2217 }
2219 void MacroAssembler::patchable_set32(Register d, jlong value) {
2220 assert_not_delayed();
2222 int hi = (int)(value >> 32);
2223 int lo = (int)(value & ~0);
2225 int count = 0;
2227 if (value == lo) { // 32-bit integer
2228 if (is_simm16(value)) {
2229 daddiu(d, R0, value);
2230 count += 1;
2231 } else {
2232 lui(d, split_low(value >> 16));
2233 count += 1;
2234 if (split_low(value)) {
2235 ori(d, d, split_low(value));
2236 count += 1;
2237 }
2238 }
2239 } else if (hi == 0) { // hardware zero-extends to upper 32
2240 ori(d, R0, julong(value) >> 16);
2241 dsll(d, d, 16);
2242 count += 2;
2243 if (split_low(value)) {
2244 ori(d, d, split_low(value));
2245 count += 1;
2246 }
2247 } else {
2248 tty->print_cr("value = 0x%x", value);
2249 guarantee(false, "Not supported yet !");
2250 }
2252 for (count; count < 3; count++) {
2253 nop();
2254 }
2255 }
2257 void MacroAssembler::patchable_call32(Register d, jlong value) {
2258 assert_not_delayed();
2260 int hi = (int)(value >> 32);
2261 int lo = (int)(value & ~0);
2263 int count = 0;
2265 if (value == lo) { // 32-bit integer
2266 if (is_simm16(value)) {
2267 daddiu(d, R0, value);
2268 count += 1;
2269 } else {
2270 lui(d, split_low(value >> 16));
2271 count += 1;
2272 if (split_low(value)) {
2273 ori(d, d, split_low(value));
2274 count += 1;
2275 }
2276 }
2277 } else {
2278 tty->print_cr("value = 0x%x", value);
2279 guarantee(false, "Not supported yet !");
2280 }
2282 for (count; count < 2; count++) {
2283 nop();
2284 }
2285 }
2287 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
2288 assert(UseCompressedClassPointers, "should only be used for compressed header");
2289 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2291 int klass_index = oop_recorder()->find_index(k);
2292 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
2293 long narrowKlass = (long)Klass::encode_klass(k);
2295 relocate(rspec, Assembler::narrow_oop_operand);
2296 patchable_set48(dst, narrowKlass);
2297 }
2300 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
2301 assert(UseCompressedOops, "should only be used for compressed header");
2302 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
2304 int oop_index = oop_recorder()->find_index(obj);
2305 RelocationHolder rspec = oop_Relocation::spec(oop_index);
2307 relocate(rspec, Assembler::narrow_oop_operand);
2308 patchable_set48(dst, oop_index);
2309 }
2311 void MacroAssembler::li64(Register rd, long imm) {
2312 assert_not_delayed();
2313 lui(rd, imm >> 48);
2314 ori(rd, rd, split_low(imm >> 32));
2315 dsll(rd, rd, 16);
2316 ori(rd, rd, split_low(imm >> 16));
2317 dsll(rd, rd, 16);
2318 ori(rd, rd, split_low(imm));
2319 }
2321 void MacroAssembler::li48(Register rd, long imm) {
2322 assert_not_delayed();
2323 assert(is_simm16(imm >> 32), "Not a 48-bit address");
2324 lui(rd, imm >> 32);
2325 ori(rd, rd, split_low(imm >> 16));
2326 dsll(rd, rd, 16);
2327 ori(rd, rd, split_low(imm));
2328 }
2329 #endif
2330 // NOTE: i dont push eax as i486.
2331 // the x86 save eax for it use eax as the jump register
2332 void MacroAssembler::verify_oop(Register reg, const char* s) {
2333 /*
2334 if (!VerifyOops) return;
2336 // Pass register number to verify_oop_subroutine
2337 char* b = new char[strlen(s) + 50];
2338 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
2339 push(rax); // save rax,
2340 push(reg); // pass register argument
2341 ExternalAddress buffer((address) b);
2342 // avoid using pushptr, as it modifies scratch registers
2343 // and our contract is not to modify anything
2344 movptr(rax, buffer.addr());
2345 push(rax);
2346 // call indirectly to solve generation ordering problem
2347 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2348 call(rax);
2349 */
2350 if (!VerifyOops) return;
2351 const char * b = NULL;
2352 stringStream ss;
2353 ss.print("verify_oop: %s: %s", reg->name(), s);
2354 b = code_string(ss.as_string());
2355 #ifdef _LP64
2356 pushad();
2357 move(A1, reg);
2358 li(A0, (long)b);
2359 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2360 ld(T9, AT, 0);
2361 jalr(T9);
2362 delayed()->nop();
2363 popad();
2364 #else
2365 // Pass register number to verify_oop_subroutine
2366 sw(T0, SP, - wordSize);
2367 sw(T1, SP, - 2*wordSize);
2368 sw(RA, SP, - 3*wordSize);
2369 sw(A0, SP ,- 4*wordSize);
2370 sw(A1, SP ,- 5*wordSize);
2371 sw(AT, SP ,- 6*wordSize);
2372 sw(T9, SP ,- 7*wordSize);
2373 addiu(SP, SP, - 7 * wordSize);
2374 move(A1, reg);
2375 li(A0, (long)b);
2376 // call indirectly to solve generation ordering problem
2377 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2378 lw(T9, AT, 0);
2379 jalr(T9);
2380 delayed()->nop();
2381 lw(T0, SP, 6* wordSize);
2382 lw(T1, SP, 5* wordSize);
2383 lw(RA, SP, 4* wordSize);
2384 lw(A0, SP, 3* wordSize);
2385 lw(A1, SP, 2* wordSize);
2386 lw(AT, SP, 1* wordSize);
2387 lw(T9, SP, 0* wordSize);
2388 addiu(SP, SP, 7 * wordSize);
2389 #endif
2390 }
2393 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
2394 if (!VerifyOops) {
2395 nop();
2396 return;
2397 }
2398 // Pass register number to verify_oop_subroutine
2399 const char * b = NULL;
2400 stringStream ss;
2401 ss.print("verify_oop_addr: %s", s);
2402 b = code_string(ss.as_string());
2404 st_ptr(T0, SP, - wordSize);
2405 st_ptr(T1, SP, - 2*wordSize);
2406 st_ptr(RA, SP, - 3*wordSize);
2407 st_ptr(A0, SP, - 4*wordSize);
2408 st_ptr(A1, SP, - 5*wordSize);
2409 st_ptr(AT, SP, - 6*wordSize);
2410 st_ptr(T9, SP, - 7*wordSize);
2411 ld_ptr(A1, addr); // addr may use SP, so load from it before change SP
2412 addiu(SP, SP, - 7 * wordSize);
2414 li(A0, (long)b);
2415 // call indirectly to solve generation ordering problem
2416 li(AT, (long)StubRoutines::verify_oop_subroutine_entry_address());
2417 ld_ptr(T9, AT, 0);
2418 jalr(T9);
2419 delayed()->nop();
2420 ld_ptr(T0, SP, 6* wordSize);
2421 ld_ptr(T1, SP, 5* wordSize);
2422 ld_ptr(RA, SP, 4* wordSize);
2423 ld_ptr(A0, SP, 3* wordSize);
2424 ld_ptr(A1, SP, 2* wordSize);
2425 ld_ptr(AT, SP, 1* wordSize);
2426 ld_ptr(T9, SP, 0* wordSize);
2427 addiu(SP, SP, 7 * wordSize);
2428 }
2430 // used registers : T0, T1
2431 void MacroAssembler::verify_oop_subroutine() {
2432 // RA: ra
2433 // A0: char* error message
2434 // A1: oop object to verify
2436 Label exit, error;
2437 // increment counter
2438 li(T0, (long)StubRoutines::verify_oop_count_addr());
2439 lw(AT, T0, 0);
2440 #ifdef _LP64
2441 daddi(AT, AT, 1);
2442 #else
2443 addi(AT, AT, 1);
2444 #endif
2445 sw(AT, T0, 0);
2447 // make sure object is 'reasonable'
2448 beq(A1, R0, exit); // if obj is NULL it is ok
2449 delayed()->nop();
2451 // Check if the oop is in the right area of memory
2452 //const int oop_mask = Universe::verify_oop_mask();
2453 //const int oop_bits = Universe::verify_oop_bits();
2454 const uintptr_t oop_mask = Universe::verify_oop_mask();
2455 const uintptr_t oop_bits = Universe::verify_oop_bits();
2456 li(AT, oop_mask);
2457 andr(T0, A1, AT);
2458 li(AT, oop_bits);
2459 bne(T0, AT, error);
2460 delayed()->nop();
2462 // make sure klass is 'reasonable'
2463 //add for compressedoops
2464 reinit_heapbase();
2465 //add for compressedoops
2466 load_klass(T0, A1);
2467 beq(T0, R0, error); // if klass is NULL it is broken
2468 delayed()->nop();
2469 #if 0
2470 //FIXME:wuhui.
2471 // Check if the klass is in the right area of memory
2472 //const int klass_mask = Universe::verify_klass_mask();
2473 //const int klass_bits = Universe::verify_klass_bits();
2474 const uintptr_t klass_mask = Universe::verify_klass_mask();
2475 const uintptr_t klass_bits = Universe::verify_klass_bits();
2477 li(AT, klass_mask);
2478 andr(T1, T0, AT);
2479 li(AT, klass_bits);
2480 bne(T1, AT, error);
2481 delayed()->nop();
2482 // make sure klass' klass is 'reasonable'
2483 //add for compressedoops
2484 load_klass(T0, T0);
2485 beq(T0, R0, error); // if klass' klass is NULL it is broken
2486 delayed()->nop();
2488 li(AT, klass_mask);
2489 andr(T1, T0, AT);
2490 li(AT, klass_bits);
2491 bne(T1, AT, error);
2492 delayed()->nop(); // if klass not in right area of memory it is broken too.
2493 #endif
2494 // return if everything seems ok
2495 bind(exit);
2497 jr(RA);
2498 delayed()->nop();
2500 // handle errors
2501 bind(error);
2502 pushad();
2503 #ifndef _LP64
2504 addi(SP, SP, (-1) * wordSize);
2505 #endif
2506 call(CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
2507 delayed()->nop();
2508 #ifndef _LP64
2509 addiu(SP, SP, 1 * wordSize);
2510 #endif
2511 popad();
2512 jr(RA);
2513 delayed()->nop();
2514 }
2516 void MacroAssembler::verify_tlab(Register t1, Register t2) {
2517 #ifdef ASSERT
2518 assert_different_registers(t1, t2, AT);
2519 if (UseTLAB && VerifyOops) {
2520 Label next, ok;
2522 get_thread(t1);
2524 ld_ptr(t2, t1, in_bytes(JavaThread::tlab_top_offset()));
2525 ld_ptr(AT, t1, in_bytes(JavaThread::tlab_start_offset()));
2526 sltu(AT, t2, AT);
2527 beq(AT, R0, next);
2528 delayed()->nop();
2530 stop("assert(top >= start)");
2532 bind(next);
2533 ld_ptr(AT, t1, in_bytes(JavaThread::tlab_end_offset()));
2534 sltu(AT, AT, t2);
2535 beq(AT, R0, ok);
2536 delayed()->nop();
2538 stop("assert(top <= end)");
2540 bind(ok);
2542 }
2543 #endif
2544 }
2545 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2546 Register tmp,
2547 int offset) {
2548 intptr_t value = *delayed_value_addr;
2549 if (value != 0)
2550 return RegisterOrConstant(value + offset);
2551 AddressLiteral a(delayed_value_addr);
2552 // load indirectly to solve generation ordering problem
2553 //movptr(tmp, ExternalAddress((address) delayed_value_addr));
2554 //ld(tmp, a);
2555 if (offset != 0)
2556 daddi(tmp,tmp, offset);
2558 return RegisterOrConstant(tmp);
2559 }
2561 void MacroAssembler::hswap(Register reg) {
2562 //short
2563 //andi(reg, reg, 0xffff);
2564 srl(AT, reg, 8);
2565 sll(reg, reg, 24);
2566 sra(reg, reg, 16);
2567 orr(reg, reg, AT);
2568 }
2570 void MacroAssembler::huswap(Register reg) {
2571 #ifdef _LP64
2572 dsrl(AT, reg, 8);
2573 dsll(reg, reg, 24);
2574 dsrl(reg, reg, 16);
2575 orr(reg, reg, AT);
2576 andi(reg, reg, 0xffff);
2577 #else
2578 //andi(reg, reg, 0xffff);
2579 srl(AT, reg, 8);
2580 sll(reg, reg, 24);
2581 srl(reg, reg, 16);
2582 orr(reg, reg, AT);
2583 #endif
2584 }
2586 // something funny to do this will only one more register AT
2587 // 32 bits
2588 void MacroAssembler::swap(Register reg) {
2589 srl(AT, reg, 8);
2590 sll(reg, reg, 24);
2591 orr(reg, reg, AT);
2592 //reg : 4 1 2 3
2593 srl(AT, AT, 16);
2594 xorr(AT, AT, reg);
2595 andi(AT, AT, 0xff);
2596 //AT : 0 0 0 1^3);
2597 xorr(reg, reg, AT);
2598 //reg : 4 1 2 1
2599 sll(AT, AT, 16);
2600 xorr(reg, reg, AT);
2601 //reg : 4 3 2 1
2602 }
2604 #ifdef _LP64
2606 /* do 32-bit CAS using MIPS64 lld/scd
2608 Jin: cas_int should only compare 32-bits of the memory value.
2609 However, lld/scd will do 64-bit operation, which violates the intention of cas_int.
2610 To simulate a 32-bit atomic operation, the value loaded with LLD should be split into
2611 tow halves, and only the low-32 bits is compared. If equals, the low-32 bits of newval,
2612 plus the high-32 bits or memory value, are stored togethor with SCD.
2614 Example:
2616 double d = 3.1415926;
2617 System.err.println("hello" + d);
2619 sun.misc.FloatingDecimal$1.<init>()
2620 |
2621 `- java.util.concurrent.atomic.AtomicInteger::compareAndSet()
2623 38 cas_int [a7a7|J] [a0|I] [a6|I]
2624 // a0: 0xffffffffe8ea9f63 pc: 0x55647f3354
2625 // a6: 0x4ab325aa
2627 again:
2628 0x00000055647f3c5c: lld at, 0x0(a7) ; 64-bit load, "0xe8ea9f63"
2630 0x00000055647f3c60: sll t9, at, 0 ; t9: low-32 bits (sign extended)
2631 0x00000055647f3c64: dsrl32 t8, at, 0 ; t8: high-32 bits
2632 0x00000055647f3c68: dsll32 t8, t8, 0
2633 0x00000055647f3c6c: bne t9, a0, 0x00000055647f3c9c ; goto nequal
2634 0x00000055647f3c70: sll zero, zero, 0
2636 0x00000055647f3c74: ori v1, zero, 0xffffffff ; v1: low-32 bits of newval (sign unextended)
2637 0x00000055647f3c78: dsll v1, v1, 16 ; v1 = a6 & 0xFFFFFFFF;
2638 0x00000055647f3c7c: ori v1, v1, 0xffffffff
2639 0x00000055647f3c80: and v1, a6, v1
2640 0x00000055647f3c84: or at, t8, v1
2641 0x00000055647f3c88: scd at, 0x0(a7)
2642 0x00000055647f3c8c: beq at, zero, 0x00000055647f3c5c ; goto again
2643 0x00000055647f3c90: sll zero, zero, 0
2644 0x00000055647f3c94: beq zero, zero, 0x00000055647f45ac ; goto done
2645 0x00000055647f3c98: sll zero, zero, 0
2646 nequal:
2647 0x00000055647f45a4: dadd a0, t9, zero
2648 0x00000055647f45a8: dadd at, zero, zero
2649 done:
2650 */
2652 void MacroAssembler::cmpxchg32(Register x_reg, Address dest, Register c_reg) {
2653 /* 2012/11/11 Jin: MIPS64 can use ll/sc for 32-bit atomic memory access */
2654 Label done, again, nequal;
2656 bind(again);
2658 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
2659 ll(AT, dest);
2660 bne(AT, c_reg, nequal);
2661 delayed()->nop();
2663 move(AT, x_reg);
2664 sc(AT, dest);
2665 beq(AT, R0, again);
2666 delayed()->nop();
2667 b(done);
2668 delayed()->nop();
2670 // not xchged
2671 bind(nequal);
2672 sync();
2673 move(c_reg, AT);
2674 move(AT, R0);
2676 bind(done);
2677 }
2678 #endif // cmpxchg32
2680 void MacroAssembler::cmpxchg(Register x_reg, Address dest, Register c_reg) {
2681 Label done, again, nequal;
2683 bind(again);
2684 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
2685 #ifdef _LP64
2686 lld(AT, dest);
2687 #else
2688 ll(AT, dest);
2689 #endif
2690 bne(AT, c_reg, nequal);
2691 delayed()->nop();
2693 move(AT, x_reg);
2694 #ifdef _LP64
2695 scd(AT, dest);
2696 #else
2697 sc(AT, dest);
2698 #endif
2699 beq(AT, R0, again);
2700 delayed()->nop();
2701 b(done);
2702 delayed()->nop();
2704 // not xchged
2705 bind(nequal);
2706 sync();
2707 move(c_reg, AT);
2708 move(AT, R0);
2710 bind(done);
2711 }
2713 void MacroAssembler::cmpxchg8(Register x_regLo, Register x_regHi, Address dest, Register c_regLo, Register c_regHi) {
2714 Label done, again, nequal;
2716 Register x_reg = x_regLo;
2717 dsll32(x_regHi, x_regHi, 0);
2718 dsll32(x_regLo, x_regLo, 0);
2719 dsrl32(x_regLo, x_regLo, 0);
2720 orr(x_reg, x_regLo, x_regHi);
2722 Register c_reg = c_regLo;
2723 dsll32(c_regHi, c_regHi, 0);
2724 dsll32(c_regLo, c_regLo, 0);
2725 dsrl32(c_regLo, c_regLo, 0);
2726 orr(c_reg, c_regLo, c_regHi);
2728 bind(again);
2730 if(UseSyncLevel >= 3000 || UseSyncLevel < 2000) sync();
2731 lld(AT, dest);
2732 bne(AT, c_reg, nequal);
2733 delayed()->nop();
2735 //move(AT, x_reg);
2736 dadd(AT, x_reg, R0);
2737 scd(AT, dest);
2738 beq(AT, R0, again);
2739 delayed()->nop();
2740 b(done);
2741 delayed()->nop();
2743 // not xchged
2744 bind(nequal);
2745 sync();
2746 //move(c_reg, AT);
2747 //move(AT, R0);
2748 dadd(c_reg, AT, R0);
2749 dadd(AT, R0, R0);
2750 bind(done);
2751 }
2753 // be sure the three register is different
2754 void MacroAssembler::rem_s(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
2755 assert_different_registers(tmp, fs, ft);
2756 div_s(tmp, fs, ft);
2757 trunc_l_s(tmp, tmp);
2758 cvt_s_l(tmp, tmp);
2759 mul_s(tmp, tmp, ft);
2760 sub_s(fd, fs, tmp);
2761 }
2763 // be sure the three register is different
2764 void MacroAssembler::rem_d(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
2765 assert_different_registers(tmp, fs, ft);
2766 div_d(tmp, fs, ft);
2767 trunc_l_d(tmp, tmp);
2768 cvt_d_l(tmp, tmp);
2769 mul_d(tmp, tmp, ft);
2770 sub_d(fd, fs, tmp);
2771 }
2773 // Fast_Lock and Fast_Unlock used by C2
2775 // Because the transitions from emitted code to the runtime
2776 // monitorenter/exit helper stubs are so slow it's critical that
2777 // we inline both the stack-locking fast-path and the inflated fast path.
2778 //
2779 // See also: cmpFastLock and cmpFastUnlock.
2780 //
2781 // What follows is a specialized inline transliteration of the code
2782 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2783 // another option would be to emit TrySlowEnter and TrySlowExit methods
2784 // at startup-time. These methods would accept arguments as
2785 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2786 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2787 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2788 // In practice, however, the # of lock sites is bounded and is usually small.
2789 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2790 // if the processor uses simple bimodal branch predictors keyed by EIP
2791 // Since the helper routines would be called from multiple synchronization
2792 // sites.
2793 //
2794 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2795 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2796 // to those specialized methods. That'd give us a mostly platform-independent
2797 // implementation that the JITs could optimize and inline at their pleasure.
2798 // Done correctly, the only time we'd need to cross to native could would be
2799 // to park() or unpark() threads. We'd also need a few more unsafe operators
2800 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2801 // (b) explicit barriers or fence operations.
2802 //
2803 // TODO:
2804 //
2805 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2806 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2807 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2808 // the lock operators would typically be faster than reifying Self.
2809 //
2810 // * Ideally I'd define the primitives as:
2811 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2812 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2813 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2814 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2815 // Furthermore the register assignments are overconstrained, possibly resulting in
2816 // sub-optimal code near the synchronization site.
2817 //
2818 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2819 // Alternately, use a better sp-proximity test.
2820 //
2821 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2822 // Either one is sufficient to uniquely identify a thread.
2823 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2824 //
2825 // * Intrinsify notify() and notifyAll() for the common cases where the
2826 // object is locked by the calling thread but the waitlist is empty.
2827 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
2828 //
2829 // * use jccb and jmpb instead of jcc and jmp to improve code density.
2830 // But beware of excessive branch density on AMD Opterons.
2831 //
2832 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
2833 // or failure of the fast-path. If the fast-path fails then we pass
2834 // control to the slow-path, typically in C. In Fast_Lock and
2835 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
2836 // will emit a conditional branch immediately after the node.
2837 // So we have branches to branches and lots of ICC.ZF games.
2838 // Instead, it might be better to have C2 pass a "FailureLabel"
2839 // into Fast_Lock and Fast_Unlock. In the case of success, control
2840 // will drop through the node. ICC.ZF is undefined at exit.
2841 // In the case of failure, the node will branch directly to the
2842 // FailureLabel
2845 // obj: object to lock
2846 // box: on-stack box address (displaced header location) - KILLED
2847 // rax,: tmp -- KILLED
2848 // scr: tmp -- KILLED
2849 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, Register scrReg) {
2851 // Ensure the register assignents are disjoint
2852 guarantee (objReg != boxReg, "") ;
2853 guarantee (objReg != tmpReg, "") ;
2854 guarantee (objReg != scrReg, "") ;
2855 guarantee (boxReg != tmpReg, "") ;
2856 guarantee (boxReg != scrReg, "") ;
2859 block_comment("FastLock");
2860 /*
2861 move(AT, 0x0);
2862 return;
2863 */
2864 if (PrintBiasedLockingStatistics) {
2865 push(tmpReg);
2866 atomic_inc32((address)BiasedLocking::total_entry_count_addr(), 1, AT, tmpReg);
2867 pop(tmpReg);
2868 }
2870 if (EmitSync & 1) {
2871 move(AT, 0x0);
2872 return;
2873 } else
2874 if (EmitSync & 2) {
2875 Label DONE_LABEL ;
2876 if (UseBiasedLocking) {
2877 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
2878 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL);
2879 }
2881 ld(tmpReg, Address(objReg, 0)) ; // fetch markword
2882 ori(tmpReg, tmpReg, 0x1);
2883 sd(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS
2885 cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg
2886 bne(AT, R0, DONE_LABEL);
2887 delayed()->nop();
2889 // Recursive locking
2890 dsubu(tmpReg, tmpReg, SP);
2891 li(AT, (7 - os::vm_page_size() ));
2892 andr(tmpReg, tmpReg, AT);
2893 sd(tmpReg, Address(boxReg, 0));
2894 bind(DONE_LABEL) ;
2895 } else {
2896 // Possible cases that we'll encounter in fast_lock
2897 // ------------------------------------------------
2898 // * Inflated
2899 // -- unlocked
2900 // -- Locked
2901 // = by self
2902 // = by other
2903 // * biased
2904 // -- by Self
2905 // -- by other
2906 // * neutral
2907 // * stack-locked
2908 // -- by self
2909 // = sp-proximity test hits
2910 // = sp-proximity test generates false-negative
2911 // -- by other
2912 //
2914 Label IsInflated, DONE_LABEL, PopDone ;
2916 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
2917 // order to reduce the number of conditional branches in the most common cases.
2918 // Beware -- there's a subtle invariant that fetch of the markword
2919 // at [FETCH], below, will never observe a biased encoding (*101b).
2920 // If this invariant is not held we risk exclusion (safety) failure.
2921 if (UseBiasedLocking && !UseOptoBiasInlining) {
2922 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL);
2923 }
2925 ld(tmpReg, Address(objReg, 0)) ; //Fetch the markword of the object.
2926 andi(AT, tmpReg, markOopDesc::monitor_value);
2927 bne(AT, R0, IsInflated); // inflated vs stack-locked|neutral|bias
2928 delayed()->nop();
2930 // Attempt stack-locking ...
2931 ori (tmpReg, tmpReg, markOopDesc::unlocked_value);
2932 sd(tmpReg, Address(boxReg, 0)); // Anticipate successful CAS
2933 //if (os::is_MP()) {
2934 // sync();
2935 //}
2937 cmpxchg(boxReg, Address(objReg, 0), tmpReg); // Updates tmpReg
2938 //AT == 1: unlocked
2940 if (PrintBiasedLockingStatistics) {
2941 Label L;
2942 beq(AT, R0, L);
2943 delayed()->nop();
2944 push(T0);
2945 push(T1);
2946 atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1);
2947 pop(T1);
2948 pop(T0);
2949 bind(L);
2950 }
2951 bne(AT, R0, DONE_LABEL);
2952 delayed()->nop();
2954 // Recursive locking
2955 // The object is stack-locked: markword contains stack pointer to BasicLock.
2956 // Locked by current thread if difference with current SP is less than one page.
2957 dsubu(tmpReg, tmpReg, SP);
2958 li(AT, 7 - os::vm_page_size() );
2959 andr(tmpReg, tmpReg, AT);
2960 sd(tmpReg, Address(boxReg, 0));
2961 if (PrintBiasedLockingStatistics) {
2962 Label L;
2963 // tmpReg == 0 => BiasedLocking::_fast_path_entry_count++
2964 bne(tmpReg, R0, L);
2965 delayed()->nop();
2966 push(T0);
2967 push(T1);
2968 atomic_inc32((address)BiasedLocking::fast_path_entry_count_addr(), 1, T0, T1);
2969 pop(T1);
2970 pop(T0);
2971 bind(L);
2972 }
2973 sltiu(AT, tmpReg, 1); /* AT = (tmpReg == 0) ? 1 : 0 */
2975 b(DONE_LABEL) ;
2976 delayed()->nop();
2978 bind(IsInflated) ;
2979 // The object's monitor m is unlocked iff m->owner == NULL,
2980 // otherwise m->owner may contain a thread or a stack address.
2982 // TODO: someday avoid the ST-before-CAS penalty by
2983 // relocating (deferring) the following ST.
2984 // We should also think about trying a CAS without having
2985 // fetched _owner. If the CAS is successful we may
2986 // avoid an RTO->RTS upgrade on the $line.
2987 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2988 li(AT, (int32_t)intptr_t(markOopDesc::unused_mark()));
2989 sd(AT, Address(boxReg, 0));
2991 move(boxReg, tmpReg) ;
2992 ld(tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
2993 // if (m->owner != 0) => AT = 0, goto slow path.
2994 move(AT, R0);
2995 bne(tmpReg, R0, DONE_LABEL);
2996 delayed()->nop();
2998 #ifndef OPT_THREAD
2999 get_thread (TREG) ;
3000 #endif
3001 // It's inflated and appears unlocked
3002 //if (os::is_MP()) {
3003 // sync();
3004 //}
3005 cmpxchg(TREG, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), tmpReg) ;
3006 // Intentional fall-through into DONE_LABEL ...
3009 // DONE_LABEL is a hot target - we'd really like to place it at the
3010 // start of cache line by padding with NOPs.
3011 // See the AMD and Intel software optimization manuals for the
3012 // most efficient "long" NOP encodings.
3013 // Unfortunately none of our alignment mechanisms suffice.
3014 bind(DONE_LABEL);
3016 // At DONE_LABEL the AT is set as follows ...
3017 // Fast_Unlock uses the same protocol.
3018 // AT == 1 -> Success
3019 // AT == 0 -> Failure - force control through the slow-path
3021 // Avoid branch-to-branch on AMD processors
3022 // This appears to be superstition.
3023 if (EmitSync & 32) nop() ;
3025 }
3026 }
3028 // obj: object to unlock
3029 // box: box address (displaced header location), killed. Must be EAX.
3030 // rbx,: killed tmp; cannot be obj nor box.
3031 //
3032 // Some commentary on balanced locking:
3033 //
3034 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3035 // Methods that don't have provably balanced locking are forced to run in the
3036 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3037 // The interpreter provides two properties:
3038 // I1: At return-time the interpreter automatically and quietly unlocks any
3039 // objects acquired the current activation (frame). Recall that the
3040 // interpreter maintains an on-stack list of locks currently held by
3041 // a frame.
3042 // I2: If a method attempts to unlock an object that is not held by the
3043 // the frame the interpreter throws IMSX.
3044 //
3045 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3046 // B() doesn't have provably balanced locking so it runs in the interpreter.
3047 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3048 // is still locked by A().
3049 //
3050 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3051 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3052 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3053 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3055 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg) {
3057 guarantee (objReg != boxReg, "") ;
3058 guarantee (objReg != tmpReg, "") ;
3059 guarantee (boxReg != tmpReg, "") ;
3063 block_comment("FastUnlock");
3066 if (EmitSync & 4) {
3067 // Disable - inhibit all inlining. Force control through the slow-path
3068 move(AT, 0x0);
3069 return;
3070 } else
3071 if (EmitSync & 8) {
3072 Label DONE_LABEL ;
3073 if (UseBiasedLocking) {
3074 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3075 }
3076 // classic stack-locking code ...
3077 ld(tmpReg, Address(boxReg, 0)) ;
3078 beq(tmpReg, R0, DONE_LABEL) ;
3079 move(AT, 0x1); // delay slot
3081 cmpxchg(tmpReg, Address(objReg, 0), boxReg); // Uses EAX which is box
3082 bind(DONE_LABEL);
3083 } else {
3084 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3086 // Critically, the biased locking test must have precedence over
3087 // and appear before the (box->dhw == 0) recursive stack-lock test.
3088 if (UseBiasedLocking && !UseOptoBiasInlining) {
3089 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3090 }
3092 ld(AT, Address(boxReg, 0)) ; // Examine the displaced header
3093 beq(AT, R0, DONE_LABEL) ; // 0 indicates recursive stack-lock
3094 delayed()->daddiu(AT, R0, 0x1);
3096 ld(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3097 andi(AT, tmpReg, markOopDesc::monitor_value) ; // Inflated?
3098 beq(AT, R0, Stacked) ; // Inflated?
3099 delayed()->nop();
3101 bind(Inflated) ;
3102 // It's inflated.
3103 // Despite our balanced locking property we still check that m->_owner == Self
3104 // as java routines or native JNI code called by this thread might
3105 // have released the lock.
3106 // Refer to the comments in synchronizer.cpp for how we might encode extra
3107 // state in _succ so we can avoid fetching EntryList|cxq.
3108 //
3109 // I'd like to add more cases in fast_lock() and fast_unlock() --
3110 // such as recursive enter and exit -- but we have to be wary of
3111 // I$ bloat, T$ effects and BP$ effects.
3112 //
3113 // If there's no contention try a 1-0 exit. That is, exit without
3114 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3115 // we detect and recover from the race that the 1-0 exit admits.
3116 //
3117 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3118 // before it STs null into _owner, releasing the lock. Updates
3119 // to data protected by the critical section must be visible before
3120 // we drop the lock (and thus before any other thread could acquire
3121 // the lock and observe the fields protected by the lock).
3122 // IA32's memory-model is SPO, so STs are ordered with respect to
3123 // each other and there's no need for an explicit barrier (fence).
3124 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3125 #ifndef OPT_THREAD
3126 get_thread (TREG) ;
3127 #endif
3129 // It's inflated
3130 ld(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3131 xorr(boxReg, boxReg, TREG);
3133 ld(AT, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3134 orr(boxReg, boxReg, AT);
3136 move(AT, R0);
3137 bne(boxReg, R0, DONE_LABEL);
3138 delayed()->nop();
3140 ld(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3141 ld(AT, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3142 orr(boxReg, boxReg, AT);
3144 move(AT, R0);
3145 bne(boxReg, R0, DONE_LABEL);
3146 delayed()->nop();
3148 sync();
3149 sd(R0, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3150 move(AT, 0x1);
3151 b(DONE_LABEL);
3152 delayed()->nop();
3154 bind (Stacked);
3155 ld(tmpReg, Address(boxReg, 0)) ;
3156 //if (os::is_MP()) { sync(); }
3157 cmpxchg(tmpReg, Address(objReg, 0), boxReg);
3159 if (EmitSync & 65536) {
3160 bind (CheckSucc);
3161 }
3163 bind(DONE_LABEL);
3165 // Avoid branch to branch on AMD processors
3166 if (EmitSync & 32768) { nop() ; }
3167 }
3168 }
3170 void MacroAssembler::align(int modulus) {
3171 while (offset() % modulus != 0) nop();
3172 }
3175 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3176 //Unimplemented();
3177 }
3179 #ifdef _LP64
3180 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, A4, A5, A6, A7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3182 /* FIXME: Jin: In MIPS64, F0~23 are all caller-saved registers */
3183 FloatRegister caller_saved_fpu_registers[] = {F0, F12, F13};
3184 #else
3185 Register caller_saved_registers[] = {AT, V0, V1, A0, A1, A2, A3, T4, T5, T6, T7, T0, T1, T2, T3, T8, T9, GP, RA, FP};
3187 Register caller_saved_fpu_registers[] = {};
3188 #endif
3190 //We preserve all caller-saved register
3191 void MacroAssembler::pushad(){
3192 int i;
3194 /* Fixed-point registers */
3195 int len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]);
3196 daddi(SP, SP, -1 * len * wordSize);
3197 for (i = 0; i < len; i++)
3198 {
3199 #ifdef _LP64
3200 sd(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3201 #else
3202 sw(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3203 #endif
3204 }
3206 /* Floating-point registers */
3207 len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3208 daddi(SP, SP, -1 * len * wordSize);
3209 for (i = 0; i < len; i++)
3210 {
3211 #ifdef _LP64
3212 sdc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3213 #else
3214 swc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3215 #endif
3216 }
3217 };
3219 void MacroAssembler::popad(){
3220 int i;
3222 /* Floating-point registers */
3223 int len = sizeof(caller_saved_fpu_registers) / sizeof(caller_saved_fpu_registers[0]);
3224 for (i = 0; i < len; i++)
3225 {
3226 #ifdef _LP64
3227 ldc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3228 #else
3229 lwc1(caller_saved_fpu_registers[i], SP, (len - i - 1) * wordSize);
3230 #endif
3231 }
3232 daddi(SP, SP, len * wordSize);
3234 /* Fixed-point registers */
3235 len = sizeof(caller_saved_registers) / sizeof(caller_saved_registers[0]);
3236 for (i = 0; i < len; i++)
3237 {
3238 #ifdef _LP64
3239 ld(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3240 #else
3241 lw(caller_saved_registers[i], SP, (len - i - 1) * wordSize);
3242 #endif
3243 }
3244 daddi(SP, SP, len * wordSize);
3245 };
3247 void MacroAssembler::push2(Register reg1, Register reg2) {
3248 #ifdef _LP64
3249 daddi(SP, SP, -16);
3250 sd(reg2, SP, 0);
3251 sd(reg1, SP, 8);
3252 #else
3253 addi(SP, SP, -8);
3254 sw(reg2, SP, 0);
3255 sw(reg1, SP, 4);
3256 #endif
3257 }
3259 void MacroAssembler::pop2(Register reg1, Register reg2) {
3260 #ifdef _LP64
3261 ld(reg1, SP, 0);
3262 ld(reg2, SP, 8);
3263 daddi(SP, SP, 16);
3264 #else
3265 lw(reg1, SP, 0);
3266 lw(reg2, SP, 4);
3267 addi(SP, SP, 8);
3268 #endif
3269 }
3271 //for UseCompressedOops Option
3272 void MacroAssembler::load_klass(Register dst, Register src) {
3273 #ifdef _LP64
3274 if(UseCompressedClassPointers){
3275 lwu(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3276 decode_klass_not_null(dst);
3277 } else
3278 #endif
3279 ld(dst, src, oopDesc::klass_offset_in_bytes());
3280 }
3282 void MacroAssembler::store_klass(Register dst, Register src) {
3283 #ifdef _LP64
3284 if(UseCompressedClassPointers){
3285 encode_klass_not_null(src);
3286 sw(src, dst, oopDesc::klass_offset_in_bytes());
3287 } else {
3288 #endif
3289 sd(src, dst, oopDesc::klass_offset_in_bytes());
3290 }
3291 }
3293 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3294 load_klass(dst, src);
3295 ld(dst, Address(dst, Klass::prototype_header_offset()));
3296 }
3298 #ifdef _LP64
3299 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3300 if (UseCompressedClassPointers) {
3301 sw(src, dst, oopDesc::klass_gap_offset_in_bytes());
3302 }
3303 }
3305 void MacroAssembler::load_heap_oop(Register dst, Address src) {
3306 if(UseCompressedOops){
3307 lwu(dst, src);
3308 decode_heap_oop(dst);
3309 } else {
3310 ld(dst, src);
3311 }
3312 }
3314 void MacroAssembler::store_heap_oop(Address dst, Register src){
3315 if(UseCompressedOops){
3316 assert(!dst.uses(src), "not enough registers");
3317 encode_heap_oop(src);
3318 sw(src, dst);
3319 } else {
3320 sd(src, dst);
3321 }
3322 }
3324 void MacroAssembler::store_heap_oop_null(Address dst){
3325 if(UseCompressedOops){
3326 sw(R0, dst);
3327 } else {
3328 sd(R0, dst);
3329 }
3330 }
3332 #ifdef ASSERT
3333 void MacroAssembler::verify_heapbase(const char* msg) {
3334 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3335 assert (Universe::heap() != NULL, "java heap should be initialized");
3336 }
3337 #endif
3340 // Algorithm must match oop.inline.hpp encode_heap_oop.
3341 void MacroAssembler::encode_heap_oop(Register r) {
3342 #ifdef ASSERT
3343 verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?");
3344 #endif
3345 verify_oop(r, "broken oop in encode_heap_oop");
3346 if (Universe::narrow_oop_base() == NULL) {
3347 if (Universe::narrow_oop_shift() != 0) {
3348 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3349 shr(r, LogMinObjAlignmentInBytes);
3350 }
3351 return;
3352 }
3354 movz(r, S5_heapbase, r);
3355 dsub(r, r, S5_heapbase);
3356 if (Universe::narrow_oop_shift() != 0) {
3357 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3358 shr(r, LogMinObjAlignmentInBytes);
3359 }
3360 }
3362 void MacroAssembler::encode_heap_oop(Register dst, Register src) {
3363 #ifdef ASSERT
3364 verify_heapbase("MacroAssembler::encode_heap_oop:heap base corrupted?");
3365 #endif
3366 verify_oop(src, "broken oop in encode_heap_oop");
3367 if (Universe::narrow_oop_base() == NULL) {
3368 if (Universe::narrow_oop_shift() != 0) {
3369 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3370 dsrl(dst, src, LogMinObjAlignmentInBytes);
3371 } else {
3372 if (dst != src) move(dst, src);
3373 }
3374 } else {
3375 if (dst == src) {
3376 movz(dst, S5_heapbase, dst);
3377 dsub(dst, dst, S5_heapbase);
3378 if (Universe::narrow_oop_shift() != 0) {
3379 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3380 shr(dst, LogMinObjAlignmentInBytes);
3381 }
3382 } else {
3383 dsub(dst, src, S5_heapbase);
3384 if (Universe::narrow_oop_shift() != 0) {
3385 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3386 shr(dst, LogMinObjAlignmentInBytes);
3387 }
3388 movz(dst, R0, src);
3389 }
3390 }
3391 }
3393 void MacroAssembler::encode_heap_oop_not_null(Register r) {
3394 assert (UseCompressedOops, "should be compressed");
3395 #ifdef ASSERT
3396 if (CheckCompressedOops) {
3397 Label ok;
3398 bne(r, R0, ok);
3399 delayed()->nop();
3400 stop("null oop passed to encode_heap_oop_not_null");
3401 bind(ok);
3402 }
3403 #endif
3404 verify_oop(r, "broken oop in encode_heap_oop_not_null");
3405 if (Universe::narrow_oop_base() != NULL) {
3406 dsub(r, r, S5_heapbase);
3407 }
3408 if (Universe::narrow_oop_shift() != 0) {
3409 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3410 shr(r, LogMinObjAlignmentInBytes);
3411 }
3413 }
3415 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
3416 assert (UseCompressedOops, "should be compressed");
3417 #ifdef ASSERT
3418 if (CheckCompressedOops) {
3419 Label ok;
3420 bne(src, R0, ok);
3421 delayed()->nop();
3422 stop("null oop passed to encode_heap_oop_not_null2");
3423 bind(ok);
3424 }
3425 #endif
3426 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
3428 if (Universe::narrow_oop_base() != NULL) {
3429 dsub(dst, src, S5_heapbase);
3430 if (Universe::narrow_oop_shift() != 0) {
3431 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3432 shr(dst, LogMinObjAlignmentInBytes);
3433 }
3434 } else {
3435 if (Universe::narrow_oop_shift() != 0) {
3436 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3437 dsrl(dst, src, LogMinObjAlignmentInBytes);
3438 } else {
3439 if (dst != src) move(dst, src);
3440 }
3441 }
3442 }
3444 void MacroAssembler::decode_heap_oop(Register r) {
3445 #ifdef ASSERT
3446 verify_heapbase("MacroAssembler::decode_heap_oop corrupted?");
3447 #endif
3448 if (Universe::narrow_oop_base() == NULL) {
3449 if (Universe::narrow_oop_shift() != 0) {
3450 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3451 shl(r, LogMinObjAlignmentInBytes);
3452 }
3453 } else {
3454 move(AT, r);
3455 if (Universe::narrow_oop_shift() != 0) {
3456 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3457 shl(r, LogMinObjAlignmentInBytes);
3458 }
3459 dadd(r, r, S5_heapbase);
3460 movz(r, R0, AT);
3461 }
3462 verify_oop(r, "broken oop in decode_heap_oop");
3463 }
3465 void MacroAssembler::decode_heap_oop(Register dst, Register src) {
3466 #ifdef ASSERT
3467 verify_heapbase("MacroAssembler::decode_heap_oop corrupted?");
3468 #endif
3469 if (Universe::narrow_oop_base() == NULL) {
3470 if (Universe::narrow_oop_shift() != 0) {
3471 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3472 if (dst != src) nop(); // DON'T DELETE THIS GUY.
3473 dsll(dst, src, LogMinObjAlignmentInBytes);
3474 } else {
3475 if (dst != src) move(dst, src);
3476 }
3477 } else {
3478 if (dst == src) {
3479 move(AT, dst);
3480 if (Universe::narrow_oop_shift() != 0) {
3481 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3482 shl(dst, LogMinObjAlignmentInBytes);
3483 }
3484 dadd(dst, dst, S5_heapbase);
3485 movz(dst, R0, AT);
3486 } else {
3487 if (Universe::narrow_oop_shift() != 0) {
3488 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3489 dsll(dst, src, LogMinObjAlignmentInBytes);
3490 daddu(dst, dst, S5_heapbase);
3491 } else {
3492 daddu(dst, src, S5_heapbase);
3493 }
3494 movz(dst, R0, src);
3495 }
3496 }
3497 verify_oop(dst, "broken oop in decode_heap_oop");
3498 }
3500 void MacroAssembler::decode_heap_oop_not_null(Register r) {
3501 // Note: it will change flags
3502 assert (UseCompressedOops, "should only be used for compressed headers");
3503 assert (Universe::heap() != NULL, "java heap should be initialized");
3504 // Cannot assert, unverified entry point counts instructions (see .ad file)
3505 // vtableStubs also counts instructions in pd_code_size_limit.
3506 // Also do not verify_oop as this is called by verify_oop.
3507 if (Universe::narrow_oop_shift() != 0) {
3508 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3509 shl(r, LogMinObjAlignmentInBytes);
3510 if (Universe::narrow_oop_base() != NULL) {
3511 daddu(r, r, S5_heapbase);
3512 }
3513 } else {
3514 assert (Universe::narrow_oop_base() == NULL, "sanity");
3515 }
3516 }
3518 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
3519 assert (UseCompressedOops, "should only be used for compressed headers");
3520 assert (Universe::heap() != NULL, "java heap should be initialized");
3522 // Cannot assert, unverified entry point counts instructions (see .ad file)
3523 // vtableStubs also counts instructions in pd_code_size_limit.
3524 // Also do not verify_oop as this is called by verify_oop.
3525 //lea(dst, Address(S5_heapbase, src, Address::times_8, 0));
3526 if (Universe::narrow_oop_shift() != 0) {
3527 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
3528 if (LogMinObjAlignmentInBytes == Address::times_8) {
3529 dsll(dst, src, LogMinObjAlignmentInBytes);
3530 daddu(dst, dst, S5_heapbase);
3531 } else {
3532 dsll(dst, src, LogMinObjAlignmentInBytes);
3533 if (Universe::narrow_oop_base() != NULL) {
3534 daddu(dst, dst, S5_heapbase);
3535 }
3536 }
3537 } else {
3538 assert (Universe::narrow_oop_base() == NULL, "sanity");
3539 if (dst != src) {
3540 move(dst, src);
3541 }
3542 }
3543 }
3545 void MacroAssembler::encode_klass_not_null(Register r) {
3546 if (Universe::narrow_klass_base() != NULL) {
3547 assert(r != AT, "Encoding a klass in AT");
3548 set64(AT, (int64_t)Universe::narrow_klass_base());
3549 dsub(r, r, AT);
3550 }
3551 if (Universe::narrow_klass_shift() != 0) {
3552 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3553 shr(r, LogKlassAlignmentInBytes);
3554 }
3555 }
3557 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3558 if (dst == src) {
3559 encode_klass_not_null(src);
3560 } else {
3561 if (Universe::narrow_klass_base() != NULL) {
3562 set64(dst, (int64_t)Universe::narrow_klass_base());
3563 dsub(dst, src, dst);
3564 if (Universe::narrow_klass_shift() != 0) {
3565 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3566 shr(dst, LogKlassAlignmentInBytes);
3567 }
3568 } else {
3569 if (Universe::narrow_klass_shift() != 0) {
3570 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3571 dsrl(dst, src, LogKlassAlignmentInBytes);
3572 } else {
3573 move(dst, src);
3574 }
3575 }
3576 }
3577 }
3579 // Function instr_size_for_decode_klass_not_null() counts the instructions
3580 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
3581 // when (Universe::heap() != NULL). Hence, if the instructions they
3582 // generate change, then this method needs to be updated.
3583 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3584 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
3585 if (Universe::narrow_klass_base() != NULL) {
3586 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
3587 return (Universe::narrow_klass_shift() == 0 ? 4 * 9 : 4 * 10);
3588 } else {
3589 // longest load decode klass function, mov64, leaq
3590 return (Universe::narrow_klass_shift() == 0 ? 4 * 0 : 4 * 1);
3591 }
3592 }
3594 void MacroAssembler::decode_klass_not_null(Register r) {
3595 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3596 assert(r != AT, "Decoding a klass in AT");
3597 // Cannot assert, unverified entry point counts instructions (see .ad file)
3598 // vtableStubs also counts instructions in pd_code_size_limit.
3599 // Also do not verify_oop as this is called by verify_oop.
3600 if (Universe::narrow_klass_shift() != 0) {
3601 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3602 shl(r, LogKlassAlignmentInBytes);
3603 }
3604 if (Universe::narrow_klass_base() != NULL) {
3605 set64(AT, (int64_t)Universe::narrow_klass_base());
3606 daddu(r, r, AT);
3607 //Not neccessary for MIPS at all.
3608 //reinit_heapbase();
3609 }
3610 }
3612 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
3613 assert (UseCompressedClassPointers, "should only be used for compressed headers");
3615 if (dst == src) {
3616 decode_klass_not_null(dst);
3617 } else {
3618 // Cannot assert, unverified entry point counts instructions (see .ad file)
3619 // vtableStubs also counts instructions in pd_code_size_limit.
3620 // Also do not verify_oop as this is called by verify_oop.
3621 set64(dst, (int64_t)Universe::narrow_klass_base());
3622 if (Universe::narrow_klass_shift() != 0) {
3623 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
3624 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
3625 dsll(AT, src, Address::times_8);
3626 daddu(dst, dst, AT);
3627 } else {
3628 daddu(dst, src, dst);
3629 }
3630 }
3631 }
3633 void MacroAssembler::incrementl(Register reg, int value) {
3634 if (value == min_jint) {
3635 move(AT, value);
3636 LP64_ONLY(addu32(reg, reg, AT)) NOT_LP64(addu(reg, reg, AT));
3637 return;
3638 }
3639 if (value < 0) { decrementl(reg, -value); return; }
3640 if (value == 0) { ; return; }
3642 if(Assembler::is_simm16(value)) {
3643 NOT_LP64(addiu(reg, reg, value));
3644 LP64_ONLY(move(AT, value); addu32(reg, reg, AT));
3645 } else {
3646 move(AT, value);
3647 LP64_ONLY(addu32(reg, reg, AT)) NOT_LP64(addu(reg, reg, AT));
3648 }
3649 }
3651 void MacroAssembler::decrementl(Register reg, int value) {
3652 if (value == min_jint) {
3653 move(AT, value);
3654 LP64_ONLY(subu32(reg, reg, AT)) NOT_LP64(subu(reg, reg, AT));
3655 return;
3656 }
3657 if (value < 0) { incrementl(reg, -value); return; }
3658 if (value == 0) { ; return; }
3660 if (Assembler::is_simm16(value)) {
3661 NOT_LP64(addiu(reg, reg, -value));
3662 LP64_ONLY(move(AT, value); subu32(reg, reg, AT));
3663 } else {
3664 move(AT, value);
3665 LP64_ONLY(subu32(reg, reg, AT)) NOT_LP64(subu(reg, reg, AT));
3666 }
3667 }
3669 void MacroAssembler::reinit_heapbase() {
3670 if (UseCompressedOops || UseCompressedClassPointers) {
3671 if (Universe::heap() != NULL) {
3672 if (Universe::narrow_oop_base() == NULL) {
3673 move(S5_heapbase, R0);
3674 } else {
3675 set64(S5_heapbase, (int64_t)Universe::narrow_ptrs_base());
3676 }
3677 } else {
3678 set64(S5_heapbase, (intptr_t)Universe::narrow_ptrs_base_addr());
3679 ld(S5_heapbase, S5_heapbase, 0);
3680 }
3681 }
3682 }
3683 #endif // _LP64
3685 void MacroAssembler::check_klass_subtype(Register sub_klass,
3686 Register super_klass,
3687 Register temp_reg,
3688 Label& L_success) {
3689 //implement ind gen_subtype_check
3690 Label L_failure;
3691 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
3692 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3693 bind(L_failure);
3694 }
3696 SkipIfEqual::SkipIfEqual(
3697 MacroAssembler* masm, const bool* flag_addr, bool value) {
3698 _masm = masm;
3699 _masm->li(AT, (address)flag_addr);
3700 _masm->lb(AT,AT,0);
3701 _masm->addi(AT,AT,-value);
3702 _masm->beq(AT,R0,_label);
3703 _masm->delayed()->nop();
3704 }
3705 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3706 Register super_klass,
3707 Register temp_reg,
3708 Label* L_success,
3709 Label* L_failure,
3710 Label* L_slow_path,
3711 RegisterOrConstant super_check_offset) {
3712 assert_different_registers(sub_klass, super_klass, temp_reg);
3713 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3714 if (super_check_offset.is_register()) {
3715 assert_different_registers(sub_klass, super_klass,
3716 super_check_offset.as_register());
3717 } else if (must_load_sco) {
3718 assert(temp_reg != noreg, "supply either a temp or a register offset");
3719 }
3721 Label L_fallthrough;
3722 int label_nulls = 0;
3723 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3724 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3725 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3726 assert(label_nulls <= 1, "at most one NULL in the batch");
3728 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3729 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3730 // If the pointers are equal, we are done (e.g., String[] elements).
3731 // This self-check enables sharing of secondary supertype arrays among
3732 // non-primary types such as array-of-interface. Otherwise, each such
3733 // type would need its own customized SSA.
3734 // We move this check to the front of the fast path because many
3735 // type checks are in fact trivially successful in this manner,
3736 // so we get a nicely predicted branch right at the start of the check.
3737 beq(sub_klass, super_klass, *L_success);
3738 delayed()->nop();
3739 // Check the supertype display:
3740 if (must_load_sco) {
3741 // Positive movl does right thing on LP64.
3742 lwu(temp_reg, super_klass, sco_offset);
3743 super_check_offset = RegisterOrConstant(temp_reg);
3744 }
3745 dsll(AT, super_check_offset.register_or_noreg(), Address::times_1);
3746 daddu(AT, sub_klass, AT);
3747 ld(AT, AT, super_check_offset.constant_or_zero()*Address::times_1);
3749 // This check has worked decisively for primary supers.
3750 // Secondary supers are sought in the super_cache ('super_cache_addr').
3751 // (Secondary supers are interfaces and very deeply nested subtypes.)
3752 // This works in the same check above because of a tricky aliasing
3753 // between the super_cache and the primary super display elements.
3754 // (The 'super_check_addr' can address either, as the case requires.)
3755 // Note that the cache is updated below if it does not help us find
3756 // what we need immediately.
3757 // So if it was a primary super, we can just fail immediately.
3758 // Otherwise, it's the slow path for us (no success at this point).
3760 if (super_check_offset.is_register()) {
3761 beq(super_klass, AT, *L_success);
3762 delayed()->nop();
3763 addi(AT, super_check_offset.as_register(), -sc_offset);
3764 if (L_failure == &L_fallthrough) {
3765 beq(AT, R0, *L_slow_path);
3766 delayed()->nop();
3767 } else {
3768 bne_far(AT, R0, *L_failure);
3769 delayed()->nop();
3770 b(*L_slow_path);
3771 delayed()->nop();
3772 }
3773 } else if (super_check_offset.as_constant() == sc_offset) {
3774 // Need a slow path; fast failure is impossible.
3775 if (L_slow_path == &L_fallthrough) {
3776 beq(super_klass, AT, *L_success);
3777 delayed()->nop();
3778 } else {
3779 bne(super_klass, AT, *L_slow_path);
3780 delayed()->nop();
3781 b(*L_success);
3782 delayed()->nop();
3783 }
3784 } else {
3785 // No slow path; it's a fast decision.
3786 if (L_failure == &L_fallthrough) {
3787 beq(super_klass, AT, *L_success);
3788 delayed()->nop();
3789 } else {
3790 bne_far(super_klass, AT, *L_failure);
3791 delayed()->nop();
3792 b(*L_success);
3793 delayed()->nop();
3794 }
3795 }
3797 bind(L_fallthrough);
3799 }
3802 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3803 Register super_klass,
3804 Register temp_reg,
3805 Register temp2_reg,
3806 Label* L_success,
3807 Label* L_failure,
3808 bool set_cond_codes) {
3809 assert_different_registers(sub_klass, super_klass, temp_reg);
3810 if (temp2_reg != noreg)
3811 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
3812 else
3813 temp2_reg = T9;
3814 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
3816 Label L_fallthrough;
3817 int label_nulls = 0;
3818 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3819 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3820 assert(label_nulls <= 1, "at most one NULL in the batch");
3822 // a couple of useful fields in sub_klass:
3823 int ss_offset = in_bytes(Klass::secondary_supers_offset());
3824 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3825 Address secondary_supers_addr(sub_klass, ss_offset);
3826 Address super_cache_addr( sub_klass, sc_offset);
3828 // Do a linear scan of the secondary super-klass chain.
3829 // This code is rarely used, so simplicity is a virtue here.
3830 // The repne_scan instruction uses fixed registers, which we must spill.
3831 // Don't worry too much about pre-existing connections with the input regs.
3833 // Get super_klass value into rax (even if it was in rdi or rcx).
3834 #ifndef PRODUCT
3835 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
3836 ExternalAddress pst_counter_addr((address) pst_counter);
3837 NOT_LP64( incrementl(pst_counter_addr) );
3838 #endif //PRODUCT
3840 // We will consult the secondary-super array.
3841 ld(temp_reg, secondary_supers_addr);
3842 // Load the array length. (Positive movl does right thing on LP64.)
3843 lw(temp2_reg, Address(temp_reg, Array<Klass*>::length_offset_in_bytes()));
3844 // Skip to start of data.
3845 daddiu(temp_reg, temp_reg, Array<Klass*>::base_offset_in_bytes());
3847 // Scan RCX words at [RDI] for an occurrence of RAX.
3848 // Set NZ/Z based on last compare.
3849 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
3850 // not change flags (only scas instruction which is repeated sets flags).
3851 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
3853 /* 2013/4/3 Jin: OpenJDK8 never compresses klass pointers in secondary-super array. */
3854 Label Loop, subtype;
3855 bind(Loop);
3856 beq(temp2_reg, R0, *L_failure);
3857 delayed()->nop();
3858 ld(AT, temp_reg, 0);
3859 beq(AT, super_klass, subtype);
3860 delayed()->daddi(temp_reg, temp_reg, 1 * wordSize);
3861 b(Loop);
3862 delayed()->daddi(temp2_reg, temp2_reg, -1);
3864 bind(subtype);
3865 sd(super_klass, super_cache_addr);
3866 if (L_success != &L_fallthrough) {
3867 b(*L_success);
3868 delayed()->nop();
3869 }
3871 // Success. Cache the super we found and proceed in triumph.
3872 #undef IS_A_TEMP
3874 bind(L_fallthrough);
3875 }
3877 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
3878 ld(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
3879 sd(R0, Address(java_thread, JavaThread::vm_result_offset()));
3880 verify_oop(oop_result, "broken oop in call_VM_base");
3881 }
3883 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
3884 ld(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
3885 sd(R0, Address(java_thread, JavaThread::vm_result_2_offset()));
3886 }
3888 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
3889 int extra_slot_offset) {
3890 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
3891 int stackElementSize = Interpreter::stackElementSize;
3892 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
3893 #ifdef ASSERT
3894 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
3895 assert(offset1 - offset == stackElementSize, "correct arithmetic");
3896 #endif
3897 Register scale_reg = NOREG;
3898 Address::ScaleFactor scale_factor = Address::no_scale;
3899 if (arg_slot.is_constant()) {
3900 offset += arg_slot.as_constant() * stackElementSize;
3901 } else {
3902 scale_reg = arg_slot.as_register();
3903 scale_factor = Address::times_8;
3904 }
3905 // 2014/07/31 Fu: We don't push RA on stack in prepare_invoke.
3906 // offset += wordSize; // return PC is on stack
3907 if(scale_reg==NOREG) return Address(SP, offset);
3908 else {
3909 dsll(scale_reg, scale_reg, scale_factor);
3910 daddu(scale_reg, SP, scale_reg);
3911 return Address(scale_reg, offset);
3912 }
3913 }
3915 SkipIfEqual::~SkipIfEqual() {
3916 _masm->bind(_label);
3917 }
3919 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3920 switch (size_in_bytes) {
3921 #ifndef _LP64
3922 case 8:
3923 assert(dst2 != noreg, "second dest register required");
3924 lw(dst, src);
3925 lw(dst2, src.plus_disp(BytesPerInt));
3926 break;
3927 #else
3928 case 8: ld(dst, src); break;
3929 #endif
3930 case 4: lw(dst, src); break;
3931 case 2: is_signed ? lh(dst, src) : lhu(dst, src); break;
3932 case 1: is_signed ? lb( dst, src) : lbu( dst, src); break;
3933 default: ShouldNotReachHere();
3934 }
3935 }
3937 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3938 switch (size_in_bytes) {
3939 #ifndef _LP64
3940 case 8:
3941 assert(src2 != noreg, "second source register required");
3942 sw(src, dst);
3943 sw(src2, dst.plus_disp(BytesPerInt));
3944 break;
3945 #else
3946 case 8: sd(src, dst); break;
3947 #endif
3948 case 4: sw(src, dst); break;
3949 case 2: sh(src, dst); break;
3950 case 1: sb(src, dst); break;
3951 default: ShouldNotReachHere();
3952 }
3953 }
3955 // Look up the method for a megamorphic invokeinterface call.
3956 // The target method is determined by <intf_klass, itable_index>.
3957 // The receiver klass is in recv_klass.
3958 // On success, the result will be in method_result, and execution falls through.
3959 // On failure, execution transfers to the given label.
3960 void MacroAssembler::lookup_interface_method(Register recv_klass,
3961 Register intf_klass,
3962 RegisterOrConstant itable_index,
3963 Register method_result,
3964 Register scan_temp,
3965 Label& L_no_such_interface,
3966 bool return_method) {
3967 assert_different_registers(recv_klass, intf_klass, scan_temp, AT);
3968 assert_different_registers(method_result, intf_klass, scan_temp, AT);
3969 assert(recv_klass != method_result || !return_method,
3970 "recv_klass can be destroyed when method isn't needed");
3972 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3973 "caller must use same register for non-constant itable index as for method");
3975 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3976 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
3977 int itentry_off = itableMethodEntry::method_offset_in_bytes();
3978 int scan_step = itableOffsetEntry::size() * wordSize;
3979 int vte_size = vtableEntry::size() * wordSize;
3980 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3981 assert(vte_size == wordSize, "else adjust times_vte_scale");
3983 lw(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
3985 // %%% Could store the aligned, prescaled offset in the klassoop.
3986 dsll(scan_temp, scan_temp, times_vte_scale);
3987 daddu(scan_temp, recv_klass, scan_temp);
3988 daddiu(scan_temp, scan_temp, vtable_base);
3989 if (HeapWordsPerLong > 1) {
3990 // Round up to align_object_offset boundary
3991 // see code for InstanceKlass::start_of_itable!
3992 round_to(scan_temp, BytesPerLong);
3993 }
3995 if (return_method) {
3996 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3997 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3998 if (itable_index.is_constant()) {
3999 set64(AT, (int)itable_index.is_constant());
4000 dsll(AT, AT, (int)Address::times_ptr);
4001 } else {
4002 dsll(AT, itable_index.as_register(), (int)Address::times_ptr);
4003 }
4004 daddu(AT, AT, recv_klass);
4005 daddiu(recv_klass, AT, itentry_off);
4006 }
4008 Label search, found_method;
4010 for (int peel = 1; peel >= 0; peel--) {
4011 ld(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4013 if (peel) {
4014 beq(intf_klass, method_result, found_method);
4015 delayed()->nop();
4016 } else {
4017 bne(intf_klass, method_result, search);
4018 delayed()->nop();
4019 // (invert the test to fall through to found_method...)
4020 }
4022 if (!peel) break;
4024 bind(search);
4026 // Check that the previous entry is non-null. A null entry means that
4027 // the receiver class doesn't implement the interface, and wasn't the
4028 // same as when the caller was compiled.
4029 beq(method_result, R0, L_no_such_interface);
4030 delayed()->nop();
4031 daddiu(scan_temp, scan_temp, scan_step);
4032 }
4034 bind(found_method);
4036 if (return_method) {
4037 // Got a hit.
4038 lw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4039 if(UseLoongsonISA) {
4040 gsldx(method_result, recv_klass, scan_temp, 0);
4041 } else {
4042 daddu(AT, recv_klass, scan_temp);
4043 ld(method_result, AT);
4044 }
4045 }
4046 }
4048 // virtual method calling
4049 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4050 RegisterOrConstant vtable_index,
4051 Register method_result) {
4052 Register tmp = GP;
4053 push(tmp);
4055 if (vtable_index.is_constant()) {
4056 assert_different_registers(recv_klass, method_result, tmp);
4057 } else {
4058 assert_different_registers(recv_klass, method_result, vtable_index.as_register(), tmp);
4059 }
4060 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4061 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4062 /*
4063 Address vtable_entry_addr(recv_klass,
4064 vtable_index, Address::times_ptr,
4065 base + vtableEntry::method_offset_in_bytes());
4066 */
4067 if (vtable_index.is_constant()) {
4068 set64(AT, vtable_index.as_constant());
4069 dsll(AT, AT, (int)Address::times_ptr);
4070 } else {
4071 dsll(AT, vtable_index.as_register(), (int)Address::times_ptr);
4072 }
4073 set64(tmp, base + vtableEntry::method_offset_in_bytes());
4074 daddu(tmp, tmp, AT);
4075 daddu(tmp, tmp, recv_klass);
4076 ld(method_result, tmp, 0);
4078 pop(tmp);
4079 }