Mercurial > jdk8-mips64-public > hotspot / file revision

src/cpu/sparc/vm/assembler_sparc.inline.hpp@6b2273dd6fa9

src/cpu/sparc/vm/assembler_sparc.inline.hpp

Tue, 21 Apr 2009 11:16:30 -0700

author
twisti
date
Tue, 21 Apr 2009 11:16:30 -0700
changeset 1162
6b2273dd6fa9
parent 1145
e5b0439ef4ae
child 1441
dcf03e02b020
permissions
-rw-r--r--

6822110: Add AddressLiteral class on SPARC
Summary: The Address class on SPARC currently handles both, addresses and address literals, what makes the Address class more complicated than it has to be.
Reviewed-by: never, kvn

     1 /*

     2  * Copyright 1997-2009 Sun Microsystems, Inc.  All Rights Reserved.

     3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

     4  *

     5  * This code is free software; you can redistribute it and/or modify it

     6  * under the terms of the GNU General Public License version 2 only, as

     7  * published by the Free Software Foundation.

     8  *

     9  * This code is distributed in the hope that it will be useful, but WITHOUT

    10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

    11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    12  * version 2 for more details (a copy is included in the LICENSE file that

    13  * accompanied this code).

    14  *

    15  * You should have received a copy of the GNU General Public License version

    16  * 2 along with this work; if not, write to the Free Software Foundation,

    17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

    18  *

    19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,

    20  * CA 95054 USA or visit www.sun.com if you need additional information or

    21  * have any questions.

    22  *

    23  */

    24 

    25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {

    26   jint& stub_inst = *(jint*) branch;

    27   stub_inst = patched_branch(target - branch, stub_inst, 0);

    28 }

    29 

    30 #ifndef PRODUCT

    31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {

    32   jint stub_inst = *(jint*) branch;

    33   print_instruction(stub_inst);

    34   ::tty->print("%s", " (unresolved)");

    35 }

    36 #endif // PRODUCT

    37 

    38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }

    39 

    40 

    41 inline int AddressLiteral::low10() const {

    42   return Assembler::low10(value());

    43 }

    44 

    45 

    46 // inlines for SPARC assembler -- dmu 5/97

    47 

    48 inline void Assembler::check_delay() {

    49 # ifdef CHECK_DELAY

    50   guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");

    51   delay_state = no_delay;

    52 # endif

    53 }

    54 

    55 inline void Assembler::emit_long(int x) {

    56   check_delay();

    57   AbstractAssembler::emit_long(x);

    58 }

    59 

    60 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {

    61   relocate(rtype);

    62   emit_long(x);

    63 }

    64 

    65 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {

    66   relocate(rspec);

    67   emit_long(x);

    68 }

    69 

    70 

    71 inline void Assembler::add(Register s1, Register s2, Register d )                             { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }

    72 inline void Assembler::add(Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }

    73 inline void Assembler::add(Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }

    74 

    75 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt);  has_delay_slot(); }

    76 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }

    77 

    78 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }

    79 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }

    80 

    81 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }

    82 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }

    83 

    84 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }

    85 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }

    86 

    87 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep();   emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt);  has_delay_slot(); }

    88 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }

    89 

    90 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only();  emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt);  has_delay_slot(); }

    91 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }

    92 

    93 inline void Assembler::call( address d,  relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt);  has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }

    94 inline void Assembler::call( Label& L,   relocInfo::relocType rt ) { call( target(L), rt); }

    95 

    96 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }

    97 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

    98 

    99 inline void Assembler::jmpl( Register s1, Register s2, Register d                          ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }

   100 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec);  has_delay_slot(); }

   101 

   102 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }

   103 inline void Assembler::ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); }

   104 

   105 inline void Assembler::ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }

   106 

   107 inline void Assembler::ldfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }

   108 inline void Assembler::ldfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   109 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }

   110 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   111 

   112 inline void Assembler::ldc(   Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | rs2(s2) ); }

   113 inline void Assembler::ldc(   Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3  ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   114 inline void Assembler::lddc(  Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }

   115 inline void Assembler::lddc(  Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   116 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }

   117 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   118 

   119 inline void Assembler::ldsb(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }

   120 inline void Assembler::ldsb(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   121 

   122 inline void Assembler::ldsh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }

   123 inline void Assembler::ldsh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   124 inline void Assembler::ldsw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }

   125 inline void Assembler::ldsw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   126 inline void Assembler::ldub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }

   127 inline void Assembler::ldub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   128 inline void Assembler::lduh(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }

   129 inline void Assembler::lduh(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   130 inline void Assembler::lduw(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }

   131 inline void Assembler::lduw(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   132 

   133 inline void Assembler::ldx(   Register s1, Register s2, Register d) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }

   134 inline void Assembler::ldx(   Register s1, int simm13a, Register d) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   135 inline void Assembler::ldd(   Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }

   136 inline void Assembler::ldd(   Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   137 

   138 #ifdef _LP64

   139 // Make all 32 bit loads signed so 64 bit registers maintain proper sign

   140 inline void Assembler::ld(  Register s1, Register s2, Register d)      { ldsw( s1, s2, d); }

   141 inline void Assembler::ld(  Register s1, int simm13a, Register d)      { ldsw( s1, simm13a, d); }

   142 #else

   143 inline void Assembler::ld(  Register s1, Register s2, Register d)      { lduw( s1, s2, d); }

   144 inline void Assembler::ld(  Register s1, int simm13a, Register d)      { lduw( s1, simm13a, d); }

   145 #endif

   146 

   147 #ifdef ASSERT

   148   // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   149 # ifdef _LP64

   150 inline void Assembler::ld(  Register s1, ByteSize simm13a, Register d) { ldsw( s1, in_bytes(simm13a), d); }

   151 # else

   152 inline void Assembler::ld(  Register s1, ByteSize simm13a, Register d) { lduw( s1, in_bytes(simm13a), d); }

   153 # endif

   154 #endif

   155 

   156 inline void Assembler::ld(  const Address& a, Register d, int offset) {

   157   if (a.has_index()) { assert(offset == 0, ""); ld(  a.base(), a.index(),         d); }

   158   else               {                          ld(  a.base(), a.disp() + offset, d); }

   159 }

   160 inline void Assembler::ldsb(const Address& a, Register d, int offset) {

   161   if (a.has_index()) { assert(offset == 0, ""); ldsb(a.base(), a.index(),         d); }

   162   else               {                          ldsb(a.base(), a.disp() + offset, d); }

   163 }

   164 inline void Assembler::ldsh(const Address& a, Register d, int offset) {

   165   if (a.has_index()) { assert(offset == 0, ""); ldsh(a.base(), a.index(),         d); }

   166   else               {                          ldsh(a.base(), a.disp() + offset, d); }

   167 }

   168 inline void Assembler::ldsw(const Address& a, Register d, int offset) {

   169   if (a.has_index()) { assert(offset == 0, ""); ldsw(a.base(), a.index(),         d); }

   170   else               {                          ldsw(a.base(), a.disp() + offset, d); }

   171 }

   172 inline void Assembler::ldub(const Address& a, Register d, int offset) {

   173   if (a.has_index()) { assert(offset == 0, ""); ldub(a.base(), a.index(),         d); }

   174   else               {                          ldub(a.base(), a.disp() + offset, d); }

   175 }

   176 inline void Assembler::lduh(const Address& a, Register d, int offset) {

   177   if (a.has_index()) { assert(offset == 0, ""); lduh(a.base(), a.index(),         d); }

   178   else               {                          lduh(a.base(), a.disp() + offset, d); }

   179 }

   180 inline void Assembler::lduw(const Address& a, Register d, int offset) {

   181   if (a.has_index()) { assert(offset == 0, ""); lduw(a.base(), a.index(),         d); }

   182   else               {                          lduw(a.base(), a.disp() + offset, d); }

   183 }

   184 inline void Assembler::ldd( const Address& a, Register d, int offset) {

   185   if (a.has_index()) { assert(offset == 0, ""); ldd( a.base(), a.index(),         d); }

   186   else               {                          ldd( a.base(), a.disp() + offset, d); }

   187 }

   188 inline void Assembler::ldx( const Address& a, Register d, int offset) {

   189   if (a.has_index()) { assert(offset == 0, ""); ldx( a.base(), a.index(),         d); }

   190   else               {                          ldx( a.base(), a.disp() + offset, d); }

   191 }

   192 

   193 inline void Assembler::ldub(Register s1, RegisterOrConstant s2, Register d) { ldub(Address(s1, s2), d); }

   194 inline void Assembler::ldsb(Register s1, RegisterOrConstant s2, Register d) { ldsb(Address(s1, s2), d); }

   195 inline void Assembler::lduh(Register s1, RegisterOrConstant s2, Register d) { lduh(Address(s1, s2), d); }

   196 inline void Assembler::ldsh(Register s1, RegisterOrConstant s2, Register d) { ldsh(Address(s1, s2), d); }

   197 inline void Assembler::lduw(Register s1, RegisterOrConstant s2, Register d) { lduw(Address(s1, s2), d); }

   198 inline void Assembler::ldsw(Register s1, RegisterOrConstant s2, Register d) { ldsw(Address(s1, s2), d); }

   199 inline void Assembler::ldx( Register s1, RegisterOrConstant s2, Register d) { ldx( Address(s1, s2), d); }

   200 inline void Assembler::ld(  Register s1, RegisterOrConstant s2, Register d) { ld(  Address(s1, s2), d); }

   201 inline void Assembler::ldd( Register s1, RegisterOrConstant s2, Register d) { ldd( Address(s1, s2), d); }

   202 

   203 // form effective addresses this way:

   204 inline void Assembler::add(   Register s1, RegisterOrConstant s2, Register d, int offset) {

   205   if (s2.is_register())  add(s1, s2.as_register(), d);

   206   else                 { add(s1, s2.as_constant() + offset, d); offset = 0; }

   207   if (offset != 0)       add(d,  offset,                    d);

   208 }

   209 

   210 inline void Assembler::ldstub(  Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }

   211 inline void Assembler::ldstub(  Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   212 

   213 

   214 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only();  emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }

   215 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only();  emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   216 

   217 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }

   218 

   219 

   220 inline void Assembler::rett( Register s1, Register s2                         ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2));  has_delay_slot(); }

   221 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt);  has_delay_slot(); }

   222 

   223 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }

   224 

   225   // pp 222

   226 

   227 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }

   228 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   229 

   230 inline void Assembler::stf(    FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }

   231 

   232 inline void Assembler::stfsr(  Register s1, Register s2) { v9_dep();   emit_long( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }

   233 inline void Assembler::stfsr(  Register s1, int simm13a) { v9_dep();   emit_data( op(ldst_op) |             op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   234 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }

   235 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(G1)    | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   236 

   237   // p 226

   238 

   239 inline void Assembler::stb(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }

   240 inline void Assembler::stb(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   241 inline void Assembler::sth(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }

   242 inline void Assembler::sth(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   243 inline void Assembler::stw(  Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }

   244 inline void Assembler::stw(  Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   245 

   246 

   247 inline void Assembler::stx(  Register d, Register s1, Register s2) { v9_only();  emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }

   248 inline void Assembler::stx(  Register d, Register s1, int simm13a) { v9_only();  emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   249 inline void Assembler::std(  Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }

   250 inline void Assembler::std(  Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   251 

   252 inline void Assembler::st( Register d, Register s1, Register s2)      { stw(d, s1, s2); }

   253 inline void Assembler::st( Register d, Register s1, int simm13a)      { stw(d, s1, simm13a); }

   254 

   255 #ifdef ASSERT

   256 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   257 inline void Assembler::st( Register d, Register s1, ByteSize simm13a) { stw(d, s1, in_bytes(simm13a)); }

   258 #endif

   259 

   260 inline void Assembler::stb(Register d, const Address& a, int offset) {

   261   if (a.has_index()) { assert(offset == 0, ""); stb(d, a.base(), a.index()        ); }

   262   else               {                          stb(d, a.base(), a.disp() + offset); }

   263 }

   264 inline void Assembler::sth(Register d, const Address& a, int offset) {

   265   if (a.has_index()) { assert(offset == 0, ""); sth(d, a.base(), a.index()        ); }

   266   else               {                          sth(d, a.base(), a.disp() + offset); }

   267 }

   268 inline void Assembler::stw(Register d, const Address& a, int offset) {

   269   if (a.has_index()) { assert(offset == 0, ""); stw(d, a.base(), a.index()        ); }

   270   else               {                          stw(d, a.base(), a.disp() + offset); }

   271 }

   272 inline void Assembler::st( Register d, const Address& a, int offset) {

   273   if (a.has_index()) { assert(offset == 0, ""); st( d, a.base(), a.index()        ); }

   274   else               {                          st( d, a.base(), a.disp() + offset); }

   275 }

   276 inline void Assembler::std(Register d, const Address& a, int offset) {

   277   if (a.has_index()) { assert(offset == 0, ""); std(d, a.base(), a.index()        ); }

   278   else               {                          std(d, a.base(), a.disp() + offset); }

   279 }

   280 inline void Assembler::stx(Register d, const Address& a, int offset) {

   281   if (a.has_index()) { assert(offset == 0, ""); stx(d, a.base(), a.index()        ); }

   282   else               {                          stx(d, a.base(), a.disp() + offset); }

   283 }

   284 

   285 inline void Assembler::stb(Register d, Register s1, RegisterOrConstant s2) { stb(d, Address(s1, s2)); }

   286 inline void Assembler::sth(Register d, Register s1, RegisterOrConstant s2) { sth(d, Address(s1, s2)); }

   287 inline void Assembler::stx(Register d, Register s1, RegisterOrConstant s2) { stx(d, Address(s1, s2)); }

   288 inline void Assembler::std(Register d, Register s1, RegisterOrConstant s2) { std(d, Address(s1, s2)); }

   289 inline void Assembler::st( Register d, Register s1, RegisterOrConstant s2) { st( d, Address(s1, s2)); }

   290 

   291 // v8 p 99

   292 

   293 inline void Assembler::stc(    int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }

   294 inline void Assembler::stc(    int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   295 inline void Assembler::stdc(   int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }

   296 inline void Assembler::stdc(   int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   297 inline void Assembler::stcsr(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }

   298 inline void Assembler::stcsr(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   299 inline void Assembler::stdcq(  int crd, Register s1, Register s2) { v8_only();  emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }

   300 inline void Assembler::stdcq(  int crd, Register s1, int simm13a) { v8_only();  emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   301 

   302 

   303 // pp 231

   304 

   305 inline void Assembler::swap(    Register s1, Register s2, Register d) { v9_dep();  emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }

   306 inline void Assembler::swap(    Register s1, int simm13a, Register d) { v9_dep();  emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }

   307 

   308 inline void Assembler::swap(    Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap(  a.base(), a.disp() + offset, d ); }

   309 

   310 

   311 // Use the right loads/stores for the platform

   312 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {

   313 #ifdef _LP64

   314   Assembler::ldx(s1, s2, d);

   315 #else

   316   Assembler::ld( s1, s2, d);

   317 #endif

   318 }

   319 

   320 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {

   321 #ifdef _LP64

   322   Assembler::ldx(s1, simm13a, d);

   323 #else

   324   Assembler::ld( s1, simm13a, d);

   325 #endif

   326 }

   327 

   328 #ifdef ASSERT

   329 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   330 inline void MacroAssembler::ld_ptr( Register s1, ByteSize simm13a, Register d ) {

   331   ld_ptr(s1, in_bytes(simm13a), d);

   332 }

   333 #endif

   334 

   335 inline void MacroAssembler::ld_ptr( Register s1, RegisterOrConstant s2, Register d ) {

   336 #ifdef _LP64

   337   Assembler::ldx(s1, s2, d);

   338 #else

   339   Assembler::ld( s1, s2, d);

   340 #endif

   341 }

   342 

   343 inline void MacroAssembler::ld_ptr(const Address& a, Register d, int offset) {

   344 #ifdef _LP64

   345   Assembler::ldx(a, d, offset);

   346 #else

   347   Assembler::ld( a, d, offset);

   348 #endif

   349 }

   350 

   351 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {

   352 #ifdef _LP64

   353   Assembler::stx(d, s1, s2);

   354 #else

   355   Assembler::st( d, s1, s2);

   356 #endif

   357 }

   358 

   359 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {

   360 #ifdef _LP64

   361   Assembler::stx(d, s1, simm13a);

   362 #else

   363   Assembler::st( d, s1, simm13a);

   364 #endif

   365 }

   366 

   367 #ifdef ASSERT

   368 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.

   369 inline void MacroAssembler::st_ptr( Register d, Register s1, ByteSize simm13a ) {

   370   st_ptr(d, s1, in_bytes(simm13a));

   371 }

   372 #endif

   373 

   374 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterOrConstant s2 ) {

   375 #ifdef _LP64

   376   Assembler::stx(d, s1, s2);

   377 #else

   378   Assembler::st( d, s1, s2);

   379 #endif

   380 }

   381 

   382 inline void MacroAssembler::st_ptr(Register d, const Address& a, int offset) {

   383 #ifdef _LP64

   384   Assembler::stx(d, a, offset);

   385 #else

   386   Assembler::st( d, a, offset);

   387 #endif

   388 }

   389 

   390 // Use the right loads/stores for the platform

   391 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {

   392 #ifdef _LP64

   393   Assembler::ldx(s1, s2, d);

   394 #else

   395   Assembler::ldd(s1, s2, d);

   396 #endif

   397 }

   398 

   399 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {

   400 #ifdef _LP64

   401   Assembler::ldx(s1, simm13a, d);

   402 #else

   403   Assembler::ldd(s1, simm13a, d);

   404 #endif

   405 }

   406 

   407 inline void MacroAssembler::ld_long( Register s1, RegisterOrConstant s2, Register d ) {

   408 #ifdef _LP64

   409   Assembler::ldx(s1, s2, d);

   410 #else

   411   Assembler::ldd(s1, s2, d);

   412 #endif

   413 }

   414 

   415 inline void MacroAssembler::ld_long(const Address& a, Register d, int offset) {

   416 #ifdef _LP64

   417   Assembler::ldx(a, d, offset);

   418 #else

   419   Assembler::ldd(a, d, offset);

   420 #endif

   421 }

   422 

   423 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {

   424 #ifdef _LP64

   425   Assembler::stx(d, s1, s2);

   426 #else

   427   Assembler::std(d, s1, s2);

   428 #endif

   429 }

   430 

   431 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {

   432 #ifdef _LP64

   433   Assembler::stx(d, s1, simm13a);

   434 #else

   435   Assembler::std(d, s1, simm13a);

   436 #endif

   437 }

   438 

   439 inline void MacroAssembler::st_long( Register d, Register s1, RegisterOrConstant s2 ) {

   440 #ifdef _LP64

   441   Assembler::stx(d, s1, s2);

   442 #else

   443   Assembler::std(d, s1, s2);

   444 #endif

   445 }

   446 

   447 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {

   448 #ifdef _LP64

   449   Assembler::stx(d, a, offset);

   450 #else

   451   Assembler::std(d, a, offset);

   452 #endif

   453 }

   454 

   455 // Functions for isolating 64 bit shifts for LP64

   456 

   457 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {

   458 #ifdef _LP64

   459   Assembler::sllx(s1, s2, d);

   460 #else

   461   Assembler::sll( s1, s2, d);

   462 #endif

   463 }

   464 

   465 inline void MacroAssembler::sll_ptr( Register s1, int imm6a,   Register d ) {

   466 #ifdef _LP64

   467   Assembler::sllx(s1, imm6a, d);

   468 #else

   469   Assembler::sll( s1, imm6a, d);

   470 #endif

   471 }

   472 

   473 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {

   474 #ifdef _LP64

   475   Assembler::srlx(s1, s2, d);

   476 #else

   477   Assembler::srl( s1, s2, d);

   478 #endif

   479 }

   480 

   481 inline void MacroAssembler::srl_ptr( Register s1, int imm6a,   Register d ) {

   482 #ifdef _LP64

   483   Assembler::srlx(s1, imm6a, d);

   484 #else

   485   Assembler::srl( s1, imm6a, d);

   486 #endif

   487 }

   488 

   489 inline void MacroAssembler::sll_ptr( Register s1, RegisterOrConstant s2, Register d ) {

   490   if (s2.is_register())  sll_ptr(s1, s2.as_register(), d);

   491   else                   sll_ptr(s1, s2.as_constant(), d);

   492 }

   493 

   494 // Use the right branch for the platform

   495 

   496 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {

   497   if (VM_Version::v9_instructions_work())

   498     Assembler::bp(c, a, icc, p, d, rt);

   499   else

   500     Assembler::br(c, a, d, rt);

   501 }

   502 

   503 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {

   504   br(c, a, p, target(L));

   505 }

   506 

   507 

   508 // Branch that tests either xcc or icc depending on the

   509 // architecture compiled (LP64 or not)

   510 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {

   511 #ifdef _LP64

   512     Assembler::bp(c, a, xcc, p, d, rt);

   513 #else

   514     MacroAssembler::br(c, a, p, d, rt);

   515 #endif

   516 }

   517 

   518 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {

   519   brx(c, a, p, target(L));

   520 }

   521 

   522 inline void MacroAssembler::ba( bool a, Label& L ) {

   523   br(always, a, pt, L);

   524 }

   525 

   526 // Warning: V9 only functions

   527 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {

   528   Assembler::bp(c, a, cc, p, d, rt);

   529 }

   530 

   531 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {

   532   Assembler::bp(c, a, cc, p, L);

   533 }

   534 

   535 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {

   536   if (VM_Version::v9_instructions_work())

   537     fbp(c, a, fcc0, p, d, rt);

   538   else

   539     Assembler::fb(c, a, d, rt);

   540 }

   541 

   542 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {

   543   fb(c, a, p, target(L));

   544 }

   545 

   546 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {

   547   Assembler::fbp(c, a, cc, p, d, rt);

   548 }

   549 

   550 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {

   551   Assembler::fbp(c, a, cc, p, L);

   552 }

   553 

   554 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }

   555 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }

   556 

   557 // Call with a check to see if we need to deal with the added

   558 // expense of relocation and if we overflow the displacement

   559 // of the quick call instruction./

   560 // Check to see if we have to deal with relocations

   561 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {

   562 #ifdef _LP64

   563   intptr_t disp;

   564   // NULL is ok because it will be relocated later.

   565   // Must change NULL to a reachable address in order to

   566   // pass asserts here and in wdisp.

   567   if ( d == NULL )

   568     d = pc();

   569 

   570   // Is this address within range of the call instruction?

   571   // If not, use the expensive instruction sequence

   572   disp = (intptr_t)d - (intptr_t)pc();

   573   if ( disp != (intptr_t)(int32_t)disp ) {

   574     relocate(rt);

   575     AddressLiteral dest(d);

   576     jumpl_to(dest, O7, O7);

   577   }

   578   else {

   579     Assembler::call( d, rt );

   580   }

   581 #else

   582   Assembler::call( d, rt );

   583 #endif

   584 }

   585 

   586 inline void MacroAssembler::call( Label& L,   relocInfo::relocType rt ) {

   587   MacroAssembler::call( target(L), rt);

   588 }

   589 

   590 

   591 

   592 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }

   593 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }

   594 

   595 // prefetch instruction

   596 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {

   597   if (VM_Version::v9_instructions_work())

   598     Assembler::bp( never, true, xcc, pt, d, rt );

   599 }

   600 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }

   601 

   602 

   603 // clobbers o7 on V8!!

   604 // returns delta from gotten pc to addr after

   605 inline int MacroAssembler::get_pc( Register d ) {

   606   int x = offset();

   607   if (VM_Version::v9_instructions_work())

   608     rdpc(d);

   609   else {

   610     Label lbl;

   611     Assembler::call(lbl, relocInfo::none);  // No relocation as this is call to pc+0x8

   612     if (d == O7)  delayed()->nop();

   613     else          delayed()->mov(O7, d);

   614     bind(lbl);

   615   }

   616   return offset() - x;

   617 }

   618 

   619 

   620 // Note:  All MacroAssembler::set_foo functions are defined out-of-line.

   621 

   622 

   623 // Loads the current PC of the following instruction as an immediate value in

   624 // 2 instructions.  All PCs in the CodeCache are within 2 Gig of each other.

   625 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {

   626   intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;

   627 #ifdef _LP64

   628   Unimplemented();

   629 #else

   630   Assembler::sethi(  thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));

   631   Assembler::add(reg,thepc &  0x3ff, reg, internal_word_Relocation::spec((address)thepc));

   632 #endif

   633   return thepc;

   634 }

   635 

   636 

   637 inline void MacroAssembler::load_contents(AddressLiteral& addrlit, Register d, int offset) {

   638   assert_not_delayed();

   639   sethi(addrlit, d);

   640   ld(d, addrlit.low10() + offset, d);

   641 }

   642 

   643 

   644 inline void MacroAssembler::load_ptr_contents(AddressLiteral& addrlit, Register d, int offset) {

   645   assert_not_delayed();

   646   sethi(addrlit, d);

   647   ld_ptr(d, addrlit.low10() + offset, d);

   648 }

   649 

   650 

   651 inline void MacroAssembler::store_contents(Register s, AddressLiteral& addrlit, Register temp, int offset) {

   652   assert_not_delayed();

   653   sethi(addrlit, temp);

   654   st(s, temp, addrlit.low10() + offset);

   655 }

   656 

   657 

   658 inline void MacroAssembler::store_ptr_contents(Register s, AddressLiteral& addrlit, Register temp, int offset) {

   659   assert_not_delayed();

   660   sethi(addrlit, temp);

   661   st_ptr(s, temp, addrlit.low10() + offset);

   662 }

   663 

   664 

   665 // This code sequence is relocatable to any address, even on LP64.

   666 inline void MacroAssembler::jumpl_to(AddressLiteral& addrlit, Register temp, Register d, int offset) {

   667   assert_not_delayed();

   668   // Force fixed length sethi because NativeJump and NativeFarCall don't handle

   669   // variable length instruction streams.

   670   patchable_sethi(addrlit, temp);

   671   jmpl(temp, addrlit.low10() + offset, d);

   672 }

   673 

   674 

   675 inline void MacroAssembler::jump_to(AddressLiteral& addrlit, Register temp, int offset) {

   676   jumpl_to(addrlit, temp, G0, offset);

   677 }

   678 

   679 

   680 inline void MacroAssembler::jump_indirect_to(Address& a, Register temp,

   681                                              int ld_offset, int jmp_offset) {

   682   assert_not_delayed();

   683   //sethi(al);                   // sethi is caller responsibility for this one

   684   ld_ptr(a, temp, ld_offset);

   685   jmp(temp, jmp_offset);

   686 }

   687 

   688 

   689 inline void MacroAssembler::set_oop(jobject obj, Register d) {

   690   set_oop(allocate_oop_address(obj), d);

   691 }

   692 

   693 

   694 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {

   695   set_oop(constant_oop_address(obj), d);

   696 }

   697 

   698 

   699 inline void MacroAssembler::set_oop(AddressLiteral& obj_addr, Register d) {

   700   assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");

   701   set(obj_addr, d);

   702 }

   703 

   704 

   705 inline void MacroAssembler::load_argument( Argument& a, Register  d ) {

   706   if (a.is_register())

   707     mov(a.as_register(), d);

   708   else

   709     ld (a.as_address(),  d);

   710 }

   711 

   712 inline void MacroAssembler::store_argument( Register s, Argument& a ) {

   713   if (a.is_register())

   714     mov(s, a.as_register());

   715   else

   716     st_ptr (s, a.as_address());         // ABI says everything is right justified.

   717 }

   718 

   719 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {

   720   if (a.is_register())

   721     mov(s, a.as_register());

   722   else

   723     st_ptr (s, a.as_address());

   724 }

   725 

   726 

   727 #ifdef _LP64

   728 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {

   729   if (a.is_float_register())

   730 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2

   731     fmov(FloatRegisterImpl::S, s, a.as_float_register() );

   732   else

   733     // Floats are stored in the high half of the stack entry

   734     // The low half is undefined per the ABI.

   735     stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));

   736 }

   737 

   738 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {

   739   if (a.is_float_register())

   740 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2

   741     fmov(FloatRegisterImpl::D, s, a.as_double_register() );

   742   else

   743     stf(FloatRegisterImpl::D, s, a.as_address());

   744 }

   745 

   746 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {

   747   if (a.is_register())

   748     mov(s, a.as_register());

   749   else

   750     stx(s, a.as_address());

   751 }

   752 #endif

   753 

   754 inline void MacroAssembler::clrb( Register s1, Register s2) {  stb( G0, s1, s2 ); }

   755 inline void MacroAssembler::clrh( Register s1, Register s2) {  sth( G0, s1, s2 ); }

   756 inline void MacroAssembler::clr(  Register s1, Register s2) {  stw( G0, s1, s2 ); }

   757 inline void MacroAssembler::clrx( Register s1, Register s2) {  stx( G0, s1, s2 ); }

   758 

   759 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }

   760 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }

   761 inline void MacroAssembler::clr(  Register s1, int simm13a) { stw( G0, s1, simm13a); }

   762 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }

   763 

   764 // returns if membar generates anything, obviously this code should mirror

   765 // membar below.

   766 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {

   767   if( !os::is_MP() ) return false;  // Not needed on single CPU

   768   if( VM_Version::v9_instructions_work() ) {

   769     const Membar_mask_bits effective_mask =

   770         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));

   771     return (effective_mask != 0);

   772   } else {

   773     return true;

   774   }

   775 }

   776 

   777 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {

   778   // Uniprocessors do not need memory barriers

   779   if (!os::is_MP()) return;

   780   // Weakened for current Sparcs and TSO.  See the v9 manual, sections 8.4.3,

   781   // 8.4.4.3, a.31 and a.50.

   782   if( VM_Version::v9_instructions_work() ) {

   783     // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value

   784     // of the mmask subfield of const7a that does anything that isn't done

   785     // implicitly is StoreLoad.

   786     const Membar_mask_bits effective_mask =

   787         Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));

   788     if ( effective_mask != 0 ) {

   789       Assembler::membar( effective_mask );

   790     }

   791   } else {

   792     // stbar is the closest there is on v8.  Equivalent to membar(StoreStore).  We

   793     // do not issue the stbar because to my knowledge all v8 machines implement TSO,

   794     // which guarantees that all stores behave as if an stbar were issued just after

   795     // each one of them.  On these machines, stbar ought to be a nop.  There doesn't

   796     // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,

   797     // it can't be specified by stbar, nor have I come up with a way to simulate it.

   798     //

   799     // Addendum.  Dave says that ldstub guarantees a write buffer flush to coherent

   800     // space.  Put one here to be on the safe side.

   801     Assembler::ldstub(SP, 0, G0);

   802   }

   803 }

Mercurial Repository: jdk8-mips64-public/hotspot

mercurial