Thu, 07 Sep 2017 09:12:16 +0800
#5745 [Code Reorganization] code cleanup and code style fix
This is a huge patch, but only code cleanup, code style fix and useless code deletion are included, for example:
tab -> two spaces, deleted spacees at the end of a line, delete useless comments.
This patch also included:
Declaration and definition of class MacroAssembler is moved from assembler_mips.h/cpp to macroAssembler_mips.h/cpp
1 /*
2 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #ifndef CPU_MIPS_VM_C1_FRAMEMAP_MIPS_HPP
27 #define CPU_MIPS_VM_C1_FRAMEMAP_MIPS_HPP
29 // On i486/gs2 the frame looks as follows:
30 //
31 // +----------------+---------+----------------------------+----------------+-----------
32 // | size_arguments | 2 words | size_locals-size_arguments | _size_monitors | spilling .
33 // +----------------+---------+----------------------------+----------------+-----------
34 //
35 private:
37 //static FloatRegister _fpu_regs [nof_fpu_regs];
38 static FloatRegister _fpu_regs [32];
40 WordSize fp_offset_for_slot (int slot) const;
41 int local_to_slot (int local_name, bool is_two_word) const;
42 // NOTE : name consist of argument, local, spill, they are not continuous
43 WordSize fp_offset_for_name (int name, bool is_two_word, bool for_hi_word) const;
44 WordSize fp_offset_for_monitor_lock (int monitor_index) const;
45 WordSize fp_offset_for_monitor_object(int monitor_index) const;
46 bool location_for_fp_offset (WordSize word_offset_from_fp,
47 Location::Type loc_type,
48 Location* loc) const;
49 WordSize fp2sp_offset (WordSize fp_offset) const;
52 public:
53 static const int pd_c_runtime_reserved_arg_size;
54 enum {
55 nof_reg_args = 5, // registers t0,a0-a3 are available for parameter passing
56 first_available_sp_in_frame = 0,
57 //frame_pad_in_bytes = 8
58 frame_pad_in_bytes = 2 * sizeof(intptr_t)
59 };
61 static LIR_Opr _zero_opr;
62 static LIR_Opr _at_opr;
63 static LIR_Opr _v0_opr;
64 static LIR_Opr _v1_opr;
65 static LIR_Opr _a0_opr;
66 static LIR_Opr _a1_opr;
67 static LIR_Opr _a2_opr;
68 static LIR_Opr _a3_opr;
69 static LIR_Opr _t0_opr;
70 static LIR_Opr _t1_opr;
71 static LIR_Opr _t2_opr;
72 static LIR_Opr _t3_opr;
73 #ifndef _LP64
74 static LIR_Opr _t4_opr;
75 static LIR_Opr _t5_opr;
76 static LIR_Opr _t6_opr;
77 static LIR_Opr _t7_opr;
78 #else
79 static LIR_Opr _a4_opr;
80 static LIR_Opr _a5_opr;
81 static LIR_Opr _a6_opr;
82 static LIR_Opr _a7_opr;
83 #endif
84 static LIR_Opr _t8_opr;
85 static LIR_Opr _t9_opr;
86 static LIR_Opr _s0_opr;
87 static LIR_Opr _s1_opr;
88 static LIR_Opr _s2_opr;
89 static LIR_Opr _s3_opr;
90 static LIR_Opr _s4_opr;
91 static LIR_Opr _s5_opr;
92 static LIR_Opr _s6_opr;
93 static LIR_Opr _s7_opr;
94 static LIR_Opr _gp_opr;
95 static LIR_Opr _fp_opr;
96 static LIR_Opr _sp_opr;
97 static LIR_Opr _ra_opr;
98 static LIR_Opr _k0_opr;
99 static LIR_Opr _k1_opr;
101 static LIR_Opr _f0_opr;
102 static LIR_Opr _f12_opr;
103 static LIR_Opr _f14_opr;
104 static LIR_Opr _d0_opr;
105 static LIR_Opr _d12_opr;
106 static LIR_Opr _d14_opr;
108 static LIR_Opr _a0_a1_opr;
109 static LIR_Opr _a2_a3_opr;
110 static LIR_Opr _v0_v1_opr;
113 static LIR_Opr receiver_opr;
114 static LIR_Opr _zero_oop_opr;
115 static LIR_Opr _at_oop_opr;
116 static LIR_Opr _v0_oop_opr;
117 static LIR_Opr _v1_oop_opr;
118 static LIR_Opr _a0_oop_opr;
119 static LIR_Opr _a1_oop_opr;
120 static LIR_Opr _a2_oop_opr;
121 static LIR_Opr _a3_oop_opr;
122 static LIR_Opr _t0_oop_opr;
123 static LIR_Opr _t1_oop_opr;
124 static LIR_Opr _t2_oop_opr;
125 static LIR_Opr _t3_oop_opr;
126 #ifndef _LP64
127 static LIR_Opr _t4_oop_opr;
128 static LIR_Opr _t5_oop_opr;
129 static LIR_Opr _t6_oop_opr;
130 static LIR_Opr _t7_oop_opr;
131 #else
132 static LIR_Opr _a4_oop_opr;
133 static LIR_Opr _a5_oop_opr;
134 static LIR_Opr _a6_oop_opr;
135 static LIR_Opr _a7_oop_opr;
136 #endif
137 static LIR_Opr _t8_oop_opr;
138 static LIR_Opr _t9_oop_opr;
139 static LIR_Opr _s0_oop_opr;
140 static LIR_Opr _s1_oop_opr;
141 static LIR_Opr _s2_oop_opr;
142 static LIR_Opr _s3_oop_opr;
143 static LIR_Opr _s4_oop_opr;
144 static LIR_Opr _s5_oop_opr;
145 static LIR_Opr _s6_oop_opr;
146 static LIR_Opr _s7_oop_opr;
147 static LIR_Opr _gp_oop_opr;
148 static LIR_Opr _fp_oop_opr;
149 static LIR_Opr _sp_oop_opr;
150 static LIR_Opr _ra_oop_opr;
151 static LIR_Opr _k0_oop_opr;
152 static LIR_Opr _k1_oop_opr;
154 static LIR_Opr _f0_oop_opr;
155 static LIR_Opr _f12_oop_opr;
156 static LIR_Opr _f14_oop_opr;
157 static LIR_Opr _d0_oop_opr;
158 static LIR_Opr _d12_oop_opr;
159 static LIR_Opr _d14_oop_opr;
161 static LIR_Opr _a0_a1_oop_opr;
162 static LIR_Opr _a2_a3_oop_opr;
163 static LIR_Opr _v0_v1_oop_opr;
165 //FIXME, needed under 64-bit? by aoqi
166 static LIR_Opr _a0_a1_long_opr;
167 static LIR_Opr _a2_a3_long_opr;
168 static LIR_Opr _v0_v1_long_opr;
169 static LIR_Opr _f0_float_opr;
170 static LIR_Opr _f12_float_opr;
171 static LIR_Opr _f14_float_opr;
172 static LIR_Opr _d0_double_opr;
173 static LIR_Opr _d12_double_opr;
174 static LIR_Opr _d14_double_opr;
177 static LIR_Opr as_long_opr(Register r, Register r2){
178 return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
179 }
181 static LIR_Opr as_float_opr(FloatRegister r) {
182 return LIR_OprFact::single_fpu(r->encoding());
183 }
186 static bool is_caller_save_register (LIR_Opr opr);
187 static bool is_caller_save_register (Register r);
190 // OptoReg name for spilled virtual FPU register n
191 //OptoReg::Name fpu_regname (int n);
193 static VMReg fpu_regname (int n);
194 static Register first_register();
195 static FloatRegister nr2floatreg (int rnr);
196 static int adjust_reg_range(int range) {
197 // Reduce the number of available regs (to free r12) in case of compressed oops
198 if (UseCompressedOops || UseCompressedClassPointers) return range - 1;
199 return range;
200 }
202 static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); }
203 static int last_cpu_reg() { return adjust_reg_range(pd_last_cpu_reg); }
204 //static int last_byte_reg() { return adjust_reg_range(pd_last_byte_reg); }
206 #endif // CPU_MIPS_VM_C1_FRAMEMAP_MIPS_HPP