Wed, 29 Mar 2017 09:41:51 +0800
#4662 TieredCompilation is turned off.
TieredCompilation is not supported yet.
1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 // Interface for updating the instruction cache. Whenever the VM modifies
27 // code, part of the processor instruction cache potentially has to be flushed.
29 // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
30 // after the next jump, and the VM never modifies instructions directly ahead
31 // of the instruction fetch path.
33 // [phh] It's not clear that the above comment is correct, because on an MP
34 // system where the dcaches are not snooped, only the thread doing the invalidate
35 // will see the update. Even in the snooped case, a memory fence would be
36 // necessary if stores weren't ordered. Fortunately, they are on all known
37 // x86 implementations.
39 class ICache : public AbstractICache {
40 public:
41 enum {
42 stub_size = 0, // Size of the icache flush stub in bytes
43 //FIXME aoqi
44 //line_size = BytesPerWord, // conservative
45 //log2_line_size = LogBytesPerWord // log2(line_size)
46 line_size = 32, // flush instruction affects a dword
47 log2_line_size = 5 // log2(line_size)
48 };
50 //nothing to do
51 static void initialize() {}
53 static void call_flush_stub(address start, int lines);
55 static void invalidate_word(address addr);
57 static void invalidate_range(address start, int nbytes);
59 static void invalidate_all();
61 };