jdk8-mips64-public/hotspot: src/cpu/mips/vm/icache

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     3  * Copyright (c) 2015, 2016, Loongson Technology. All rights reserved.

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    10  * This code is distributed in the hope that it will be useful, but WITHOUT

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    12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

    13  * version 2 for more details (a copy is included in the LICENSE file that

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    26 // Interface for updating the instruction cache.  Whenever the VM modifies

    27 // code, part of the processor instruction cache potentially has to be flushed.

    29 // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent

    30 // after the next jump, and the VM never modifies instructions directly ahead

    31 // of the instruction fetch path.

    33 // [phh] It's not clear that the above comment is correct, because on an MP

    34 // system where the dcaches are not snooped, only the thread doing the invalidate

    35 // will see the update.  Even in the snooped case, a memory fence would be

    36 // necessary if stores weren't ordered.  Fortunately, they are on all known

    37 // x86 implementations.

    39 class ICache : public AbstractICache {

    40  public:

    41   enum {

    42     stub_size      = 0,                 // Size of the icache flush stub in bytes

    43 		//FIXME aoqi

    44     //line_size      = BytesPerWord,      // conservative

    45     //log2_line_size = LogBytesPerWord    // log2(line_size)

    46 		line_size      = 32,  // flush instruction affects a dword

    47 		log2_line_size = 5    // log2(line_size)

    48   };

    50 	//nothing to do

    51 	static void initialize() {}

    53 	static void call_flush_stub(address start, int lines);

    55 	static void invalidate_word(address addr);

    57 	static void invalidate_range(address start, int nbytes);

    59 	static void invalidate_all();

    61 };

src/cpu/mips/vm/icache_mips.hpp@2d8a650513c2