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src/cpu/ppc/vm/vm_version_ppc.cpp@41b780b43b74
src/cpu/ppc/vm/vm_version_ppc.cpp
Wed, 27 Nov 2013 16:16:21 -0800
- author
- goetz
- date
- Wed, 27 Nov 2013 16:16:21 -0800
- changeset 6490
- 41b780b43b74
- parent 6458
- ec28f9c041ff
- child 6495
- 67fa91961822
- permissions
- -rw-r--r--
8029015: PPC64 (part 216): opto: trap based null and range checks
Summary: On PPC64 use tdi instruction that does a compare and raises SIGTRAP for NULL and range checks.
Reviewed-by: kvn
1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2013 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
26 #include "precompiled.hpp"
27 #include "assembler_ppc.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "utilities/defaultStream.hpp"
33 #include "vm_version_ppc.hpp"
34 #ifdef TARGET_OS_FAMILY_aix
35 # include "os_aix.inline.hpp"
36 #endif
37 #ifdef TARGET_OS_FAMILY_linux
38 # include "os_linux.inline.hpp"
39 #endif
41 # include <sys/sysinfo.h>
43 int VM_Version::_features = VM_Version::unknown_m;
44 int VM_Version::_measured_cache_line_size = 128; // default value
45 const char* VM_Version::_features_str = "";
46 bool VM_Version::_is_determine_features_test_running = false;
49 #define MSG(flag) \
50 if (flag && !FLAG_IS_DEFAULT(flag)) \
51 jio_fprintf(defaultStream::error_stream(), \
52 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
53 " -XX:+" #flag " will be disabled!\n");
55 void VM_Version::initialize() {
57 // Test which instructions are supported and measure cache line size.
58 determine_features();
60 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
61 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
62 if (VM_Version::has_popcntw()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
64 } else if (VM_Version::has_cmpb()) {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
66 } else if (VM_Version::has_popcntb()) {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
68 } else {
69 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
70 }
71 }
72 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
73 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7,
74 "PowerArchitecturePPC64 should be 0, 5, 6 or 7");
76 if (!UseSIGTRAP) {
77 MSG(TrapBasedICMissChecks);
78 MSG(TrapBasedNotEntrantChecks);
79 MSG(TrapBasedNullChecks);
80 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
81 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
82 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
83 }
85 #ifdef COMPILER2
86 if (!UseSIGTRAP) {
87 MSG(TrapBasedRangeChecks);
88 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
89 }
91 // On Power6 test for section size.
92 if (PowerArchitecturePPC64 == 6)
93 determine_section_size();
94 // TODO: PPC port else
95 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
97 MaxVectorSize = 8;
98 #endif
100 // Create and print feature-string.
101 char buf[(num_features+1) * 16]; // max 16 chars per feature
102 jio_snprintf(buf, sizeof(buf),
103 "ppc64%s%s%s%s%s%s%s%s",
104 (has_fsqrt() ? " fsqrt" : ""),
105 (has_isel() ? " isel" : ""),
106 (has_lxarxeh() ? " lxarxeh" : ""),
107 (has_cmpb() ? " cmpb" : ""),
108 //(has_mftgpr()? " mftgpr" : ""),
109 (has_popcntb() ? " popcntb" : ""),
110 (has_popcntw() ? " popcntw" : ""),
111 (has_fcfids() ? " fcfids" : ""),
112 (has_vand() ? " vand" : "")
113 // Make sure number of %s matches num_features!
114 );
115 _features_str = strdup(buf);
116 NOT_PRODUCT(if (Verbose) print_features(););
118 // PPC64 supports 8-byte compare-exchange operations (see
119 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
120 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
121 _supports_cx8 = true;
123 UseSSE = 0; // Only on x86 and x64
125 intx cache_line_size = _measured_cache_line_size;
127 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
129 if (AllocatePrefetchStyle == 4) {
130 AllocatePrefetchStepSize = cache_line_size; // need exact value
131 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // use larger blocks by default
132 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // default is not defined ?
133 } else {
134 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
135 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value
136 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // default is not defined ?
137 }
139 assert(AllocatePrefetchLines > 0, "invalid value");
140 if (AllocatePrefetchLines < 1) // Set valid value in product VM.
141 AllocatePrefetchLines = 1; // Conservative value
143 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size)
144 AllocatePrefetchStyle = 1; // fall back if inappropriate
146 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
147 }
149 void VM_Version::print_features() {
150 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), get_cache_line_size());
151 }
153 #ifdef COMPILER2
154 // Determine section size on power6: If section size is 8 instructions,
155 // there should be a difference between the two testloops of ~15 %. If
156 // no difference is detected the section is assumed to be 32 instructions.
157 void VM_Version::determine_section_size() {
159 int unroll = 80;
161 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
163 // Allocate space for the code
164 ResourceMark rm;
165 CodeBuffer cb("detect_section_size", code_size, 0);
166 MacroAssembler* a = new MacroAssembler(&cb);
168 uint32_t *code = (uint32_t *)a->pc();
169 // emit code.
170 void (*test1)() = (void(*)())(void *)a->emit_fd();
172 Label l1;
174 a->li(R4, 1);
175 a->sldi(R4, R4, 28);
176 a->b(l1);
177 a->align(CodeEntryAlignment);
179 a->bind(l1);
181 for (int i = 0; i < unroll; i++) {
182 // Schleife 1
183 // ------- sector 0 ------------
184 // ;; 0
185 a->nop(); // 1
186 a->fpnop0(); // 2
187 a->fpnop1(); // 3
188 a->addi(R4,R4, -1); // 4
190 // ;; 1
191 a->nop(); // 5
192 a->fmr(F6, F6); // 6
193 a->fmr(F7, F7); // 7
194 a->endgroup(); // 8
195 // ------- sector 8 ------------
197 // ;; 2
198 a->nop(); // 9
199 a->nop(); // 10
200 a->fmr(F8, F8); // 11
201 a->fmr(F9, F9); // 12
203 // ;; 3
204 a->nop(); // 13
205 a->fmr(F10, F10); // 14
206 a->fmr(F11, F11); // 15
207 a->endgroup(); // 16
208 // -------- sector 16 -------------
210 // ;; 4
211 a->nop(); // 17
212 a->nop(); // 18
213 a->fmr(F15, F15); // 19
214 a->fmr(F16, F16); // 20
216 // ;; 5
217 a->nop(); // 21
218 a->fmr(F17, F17); // 22
219 a->fmr(F18, F18); // 23
220 a->endgroup(); // 24
221 // ------- sector 24 ------------
223 // ;; 6
224 a->nop(); // 25
225 a->nop(); // 26
226 a->fmr(F19, F19); // 27
227 a->fmr(F20, F20); // 28
229 // ;; 7
230 a->nop(); // 29
231 a->fmr(F21, F21); // 30
232 a->fmr(F22, F22); // 31
233 a->brnop0(); // 32
235 // ------- sector 32 ------------
236 }
238 // ;; 8
239 a->cmpdi(CCR0, R4, unroll);// 33
240 a->bge(CCR0, l1); // 34
241 a->blr();
243 // emit code.
244 void (*test2)() = (void(*)())(void *)a->emit_fd();
245 // uint32_t *code = (uint32_t *)a->pc();
247 Label l2;
249 a->li(R4, 1);
250 a->sldi(R4, R4, 28);
251 a->b(l2);
252 a->align(CodeEntryAlignment);
254 a->bind(l2);
256 for (int i = 0; i < unroll; i++) {
257 // Schleife 2
258 // ------- sector 0 ------------
259 // ;; 0
260 a->brnop0(); // 1
261 a->nop(); // 2
262 //a->cmpdi(CCR0, R4, unroll);
263 a->fpnop0(); // 3
264 a->fpnop1(); // 4
265 a->addi(R4,R4, -1); // 5
267 // ;; 1
269 a->nop(); // 6
270 a->fmr(F6, F6); // 7
271 a->fmr(F7, F7); // 8
272 // ------- sector 8 ---------------
274 // ;; 2
275 a->endgroup(); // 9
277 // ;; 3
278 a->nop(); // 10
279 a->nop(); // 11
280 a->fmr(F8, F8); // 12
282 // ;; 4
283 a->fmr(F9, F9); // 13
284 a->nop(); // 14
285 a->fmr(F10, F10); // 15
287 // ;; 5
288 a->fmr(F11, F11); // 16
289 // -------- sector 16 -------------
291 // ;; 6
292 a->endgroup(); // 17
294 // ;; 7
295 a->nop(); // 18
296 a->nop(); // 19
297 a->fmr(F15, F15); // 20
299 // ;; 8
300 a->fmr(F16, F16); // 21
301 a->nop(); // 22
302 a->fmr(F17, F17); // 23
304 // ;; 9
305 a->fmr(F18, F18); // 24
306 // -------- sector 24 -------------
308 // ;; 10
309 a->endgroup(); // 25
311 // ;; 11
312 a->nop(); // 26
313 a->nop(); // 27
314 a->fmr(F19, F19); // 28
316 // ;; 12
317 a->fmr(F20, F20); // 29
318 a->nop(); // 30
319 a->fmr(F21, F21); // 31
321 // ;; 13
322 a->fmr(F22, F22); // 32
323 }
325 // -------- sector 32 -------------
326 // ;; 14
327 a->cmpdi(CCR0, R4, unroll); // 33
328 a->bge(CCR0, l2); // 34
330 a->blr();
331 uint32_t *code_end = (uint32_t *)a->pc();
332 a->flush();
334 double loop1_seconds,loop2_seconds, rel_diff;
335 uint64_t start1, stop1;
337 start1 = os::current_thread_cpu_time(false);
338 (*test1)();
339 stop1 = os::current_thread_cpu_time(false);
340 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
343 start1 = os::current_thread_cpu_time(false);
344 (*test2)();
345 stop1 = os::current_thread_cpu_time(false);
347 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
349 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
351 if (PrintAssembly) {
352 ttyLocker ttyl;
353 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", code);
354 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
355 tty->print_cr("Time loop1 :%f", loop1_seconds);
356 tty->print_cr("Time loop2 :%f", loop2_seconds);
357 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
359 if (rel_diff > 12.0) {
360 tty->print_cr("Section Size 8 Instructions");
361 } else{
362 tty->print_cr("Section Size 32 Instructions or Power5");
363 }
364 }
366 #if 0 // TODO: PPC port
367 // Set sector size (if not set explicitly).
368 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
369 if (rel_diff > 12.0) {
370 PdScheduling::power6SectorSize = 0x20;
371 } else {
372 PdScheduling::power6SectorSize = 0x80;
373 }
374 } else if (Power6SectorSize128PPC64) {
375 PdScheduling::power6SectorSize = 0x80;
376 } else {
377 PdScheduling::power6SectorSize = 0x20;
378 }
379 #endif
380 if (UsePower6SchedulerPPC64) Unimplemented();
381 }
382 #endif // COMPILER2
384 void VM_Version::determine_features() {
385 const int code_size = (num_features+1+2*7)*BytesPerInstWord; // 7 InstWords for each call (function descriptor + blr instruction)
386 int features = 0;
388 // create test area
389 enum { BUFFER_SIZE = 2*4*K }; // needs to be >=2* max cache line size (cache line size can't exceed min page size)
390 char test_area[BUFFER_SIZE];
391 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
393 // Allocate space for the code
394 ResourceMark rm;
395 CodeBuffer cb("detect_cpu_features", code_size, 0);
396 MacroAssembler* a = new MacroAssembler(&cb);
398 // emit code.
399 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->emit_fd();
400 uint32_t *code = (uint32_t *)a->pc();
401 // Don't use R0 in ldarx.
402 // keep R3_ARG1 = R3 unmodified, it contains &field (see below)
403 // keep R4_ARG2 = R4 unmodified, it contains offset = 0 (see below)
404 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
405 a->isel(R7, R5, R6, 0); // code[1] -> isel_m
406 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1);// code[2] -> lxarx_m
407 a->cmpb(R7, R5, R6); // code[3] -> bcmp
408 //a->mftgpr(R7, F3); // code[4] -> mftgpr
409 a->popcntb(R7, R5); // code[5] -> popcntb
410 a->popcntw(R7, R5); // code[6] -> popcntw
411 a->fcfids(F3, F4); // code[7] -> fcfids
412 a->vand(VR0, VR0, VR0); // code[8] -> vand
413 a->blr();
415 // Emit function to set one cache line to zero
416 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->emit_fd(); // emit function descriptor and get pointer to it
417 a->dcbz(R3_ARG1); // R3_ARG1 = R3 = addr
418 a->blr();
420 uint32_t *code_end = (uint32_t *)a->pc();
421 a->flush();
423 // Print the detection code.
424 if (PrintAssembly) {
425 ttyLocker ttyl;
426 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", code);
427 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
428 }
430 // Measure cache line size.
431 memset(test_area, 0xFF, BUFFER_SIZE); // fill test area with 0xFF
432 (*zero_cacheline_func_ptr)(mid_of_test_area); // call function which executes dcbz to the middle
433 int count = 0; // count zeroed bytes
434 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
435 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
436 _measured_cache_line_size = count;
438 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
439 VM_Version::_is_determine_features_test_running = true;
440 (*test)((address)mid_of_test_area, (uint64_t)0);
441 VM_Version::_is_determine_features_test_running = false;
443 // determine which instructions are legal.
444 int feature_cntr = 0;
445 if (code[feature_cntr++]) features |= fsqrt_m;
446 if (code[feature_cntr++]) features |= isel_m;
447 if (code[feature_cntr++]) features |= lxarxeh_m;
448 if (code[feature_cntr++]) features |= cmpb_m;
449 //if(code[feature_cntr++])features |= mftgpr_m;
450 if (code[feature_cntr++]) features |= popcntb_m;
451 if (code[feature_cntr++]) features |= popcntw_m;
452 if (code[feature_cntr++]) features |= fcfids_m;
453 if (code[feature_cntr++]) features |= vand_m;
455 // Print the detection code.
456 if (PrintAssembly) {
457 ttyLocker ttyl;
458 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", code);
459 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
460 }
462 _features = features;
463 }
466 static int saved_features = 0;
468 void VM_Version::allow_all() {
469 saved_features = _features;
470 _features = all_features_m;
471 }
473 void VM_Version::revert() {
474 _features = saved_features;
475 }
